1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
4 2011 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
87 #include "hard-reg-set.h"
88 #include "basic-block.h"
89 #include "insn-config.h"
91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
93 #include "insn-attr.h"
95 #include "diagnostic-core.h"
98 #include "insn-codes.h"
99 #include "rtlhooks-def.h"
100 /* Include output.h for dump_file. */
104 #include "tree-pass.h"
108 /* Number of attempts to combine instructions in this function. */
110 static int combine_attempts;
112 /* Number of attempts that got as far as substitution in this function. */
114 static int combine_merges;
116 /* Number of instructions combined with added SETs in this function. */
118 static int combine_extras;
120 /* Number of instructions combined in this function. */
122 static int combine_successes;
124 /* Totals over entire compilation. */
126 static int total_attempts, total_merges, total_extras, total_successes;
128 /* combine_instructions may try to replace the right hand side of the
129 second instruction with the value of an associated REG_EQUAL note
130 before throwing it at try_combine. That is problematic when there
131 is a REG_DEAD note for a register used in the old right hand side
132 and can cause distribute_notes to do wrong things. This is the
133 second instruction if it has been so modified, null otherwise. */
137 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
139 static rtx i2mod_old_rhs;
141 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
143 static rtx i2mod_new_rhs;
145 typedef struct reg_stat_struct {
146 /* Record last point of death of (hard or pseudo) register n. */
149 /* Record last point of modification of (hard or pseudo) register n. */
152 /* The next group of fields allows the recording of the last value assigned
153 to (hard or pseudo) register n. We use this information to see if an
154 operation being processed is redundant given a prior operation performed
155 on the register. For example, an `and' with a constant is redundant if
156 all the zero bits are already known to be turned off.
158 We use an approach similar to that used by cse, but change it in the
161 (1) We do not want to reinitialize at each label.
162 (2) It is useful, but not critical, to know the actual value assigned
163 to a register. Often just its form is helpful.
165 Therefore, we maintain the following fields:
167 last_set_value the last value assigned
168 last_set_label records the value of label_tick when the
169 register was assigned
170 last_set_table_tick records the value of label_tick when a
171 value using the register is assigned
172 last_set_invalid set to nonzero when it is not valid
173 to use the value of this register in some
176 To understand the usage of these tables, it is important to understand
177 the distinction between the value in last_set_value being valid and
178 the register being validly contained in some other expression in the
181 (The next two parameters are out of date).
183 reg_stat[i].last_set_value is valid if it is nonzero, and either
184 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
186 Register I may validly appear in any expression returned for the value
187 of another register if reg_n_sets[i] is 1. It may also appear in the
188 value for register J if reg_stat[j].last_set_invalid is zero, or
189 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
191 If an expression is found in the table containing a register which may
192 not validly appear in an expression, the register is replaced by
193 something that won't match, (clobber (const_int 0)). */
195 /* Record last value assigned to (hard or pseudo) register n. */
199 /* Record the value of label_tick when an expression involving register n
200 is placed in last_set_value. */
202 int last_set_table_tick;
204 /* Record the value of label_tick when the value for register n is placed in
209 /* These fields are maintained in parallel with last_set_value and are
210 used to store the mode in which the register was last set, the bits
211 that were known to be zero when it was last set, and the number of
212 sign bits copies it was known to have when it was last set. */
214 unsigned HOST_WIDE_INT last_set_nonzero_bits;
215 char last_set_sign_bit_copies;
216 ENUM_BITFIELD(machine_mode) last_set_mode : 8;
218 /* Set nonzero if references to register n in expressions should not be
219 used. last_set_invalid is set nonzero when this register is being
220 assigned to and last_set_table_tick == label_tick. */
222 char last_set_invalid;
224 /* Some registers that are set more than once and used in more than one
225 basic block are nevertheless always set in similar ways. For example,
226 a QImode register may be loaded from memory in two places on a machine
227 where byte loads zero extend.
229 We record in the following fields if a register has some leading bits
230 that are always equal to the sign bit, and what we know about the
231 nonzero bits of a register, specifically which bits are known to be
234 If an entry is zero, it means that we don't know anything special. */
236 unsigned char sign_bit_copies;
238 unsigned HOST_WIDE_INT nonzero_bits;
240 /* Record the value of the label_tick when the last truncation
241 happened. The field truncated_to_mode is only valid if
242 truncation_label == label_tick. */
244 int truncation_label;
246 /* Record the last truncation seen for this register. If truncation
247 is not a nop to this mode we might be able to save an explicit
248 truncation if we know that value already contains a truncated
251 ENUM_BITFIELD(machine_mode) truncated_to_mode : 8;
254 DEF_VEC_O(reg_stat_type);
255 DEF_VEC_ALLOC_O(reg_stat_type,heap);
257 static VEC(reg_stat_type,heap) *reg_stat;
259 /* Record the luid of the last insn that invalidated memory
260 (anything that writes memory, and subroutine calls, but not pushes). */
262 static int mem_last_set;
264 /* Record the luid of the last CALL_INSN
265 so we can tell whether a potential combination crosses any calls. */
267 static int last_call_luid;
269 /* When `subst' is called, this is the insn that is being modified
270 (by combining in a previous insn). The PATTERN of this insn
271 is still the old pattern partially modified and it should not be
272 looked at, but this may be used to examine the successors of the insn
273 to judge whether a simplification is valid. */
275 static rtx subst_insn;
277 /* This is the lowest LUID that `subst' is currently dealing with.
278 get_last_value will not return a value if the register was set at or
279 after this LUID. If not for this mechanism, we could get confused if
280 I2 or I1 in try_combine were an insn that used the old value of a register
281 to obtain a new value. In that case, we might erroneously get the
282 new value of the register when we wanted the old one. */
284 static int subst_low_luid;
286 /* This contains any hard registers that are used in newpat; reg_dead_at_p
287 must consider all these registers to be always live. */
289 static HARD_REG_SET newpat_used_regs;
291 /* This is an insn to which a LOG_LINKS entry has been added. If this
292 insn is the earlier than I2 or I3, combine should rescan starting at
295 static rtx added_links_insn;
297 /* Basic block in which we are performing combines. */
298 static basic_block this_basic_block;
299 static bool optimize_this_for_speed_p;
302 /* Length of the currently allocated uid_insn_cost array. */
304 static int max_uid_known;
306 /* The following array records the insn_rtx_cost for every insn
307 in the instruction stream. */
309 static int *uid_insn_cost;
311 /* The following array records the LOG_LINKS for every insn in the
312 instruction stream as an INSN_LIST rtx. */
314 static rtx *uid_log_links;
316 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
317 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
319 /* Incremented for each basic block. */
321 static int label_tick;
323 /* Reset to label_tick for each extended basic block in scanning order. */
325 static int label_tick_ebb_start;
327 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
328 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
330 static enum machine_mode nonzero_bits_mode;
332 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
333 be safely used. It is zero while computing them and after combine has
334 completed. This former test prevents propagating values based on
335 previously set values, which can be incorrect if a variable is modified
338 static int nonzero_sign_valid;
341 /* Record one modification to rtl structure
342 to be undone by storing old_contents into *where. */
344 enum undo_kind { UNDO_RTX, UNDO_INT, UNDO_MODE };
350 union { rtx r; int i; enum machine_mode m; } old_contents;
351 union { rtx *r; int *i; } where;
354 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
355 num_undo says how many are currently recorded.
357 other_insn is nonzero if we have modified some other insn in the process
358 of working on subst_insn. It must be verified too. */
367 static struct undobuf undobuf;
369 /* Number of times the pseudo being substituted for
370 was found and replaced. */
372 static int n_occurrences;
374 static rtx reg_nonzero_bits_for_combine (const_rtx, enum machine_mode, const_rtx,
376 unsigned HOST_WIDE_INT,
377 unsigned HOST_WIDE_INT *);
378 static rtx reg_num_sign_bit_copies_for_combine (const_rtx, enum machine_mode, const_rtx,
380 unsigned int, unsigned int *);
381 static void do_SUBST (rtx *, rtx);
382 static void do_SUBST_INT (int *, int);
383 static void init_reg_last (void);
384 static void setup_incoming_promotions (rtx);
385 static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *);
386 static int cant_combine_insn_p (rtx);
387 static int can_combine_p (rtx, rtx, rtx, rtx, rtx, rtx, rtx *, rtx *);
388 static int combinable_i3pat (rtx, rtx *, rtx, rtx, rtx, int, int, rtx *);
389 static int contains_muldiv (rtx);
390 static rtx try_combine (rtx, rtx, rtx, rtx, int *);
391 static void undo_all (void);
392 static void undo_commit (void);
393 static rtx *find_split_point (rtx *, rtx, bool);
394 static rtx subst (rtx, rtx, rtx, int, int);
395 static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
396 static rtx simplify_if_then_else (rtx);
397 static rtx simplify_set (rtx);
398 static rtx simplify_logical (rtx);
399 static rtx expand_compound_operation (rtx);
400 static const_rtx expand_field_assignment (const_rtx);
401 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
402 rtx, unsigned HOST_WIDE_INT, int, int, int);
403 static rtx extract_left_shift (rtx, int);
404 static rtx make_compound_operation (rtx, enum rtx_code);
405 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
406 unsigned HOST_WIDE_INT *);
407 static rtx canon_reg_for_combine (rtx, rtx);
408 static rtx force_to_mode (rtx, enum machine_mode,
409 unsigned HOST_WIDE_INT, int);
410 static rtx if_then_else_cond (rtx, rtx *, rtx *);
411 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
412 static int rtx_equal_for_field_assignment_p (rtx, rtx);
413 static rtx make_field_assignment (rtx);
414 static rtx apply_distributive_law (rtx);
415 static rtx distribute_and_simplify_rtx (rtx, int);
416 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
417 unsigned HOST_WIDE_INT);
418 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
419 unsigned HOST_WIDE_INT);
420 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
421 HOST_WIDE_INT, enum machine_mode, int *);
422 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
423 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
425 static int recog_for_combine (rtx *, rtx, rtx *);
426 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
427 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
428 static void update_table_tick (rtx);
429 static void record_value_for_reg (rtx, rtx, rtx);
430 static void check_promoted_subreg (rtx, rtx);
431 static void record_dead_and_set_regs_1 (rtx, const_rtx, void *);
432 static void record_dead_and_set_regs (rtx);
433 static int get_last_value_validate (rtx *, rtx, int, int);
434 static rtx get_last_value (const_rtx);
435 static int use_crosses_set_p (const_rtx, int);
436 static void reg_dead_at_p_1 (rtx, const_rtx, void *);
437 static int reg_dead_at_p (rtx, rtx);
438 static void move_deaths (rtx, rtx, int, rtx, rtx *);
439 static int reg_bitfield_target_p (rtx, rtx);
440 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx, rtx);
441 static void distribute_links (rtx);
442 static void mark_used_regs_combine (rtx);
443 static void record_promoted_value (rtx, rtx);
444 static int unmentioned_reg_p_1 (rtx *, void *);
445 static bool unmentioned_reg_p (rtx, rtx);
446 static int record_truncated_value (rtx *, void *);
447 static void record_truncated_values (rtx *, void *);
448 static bool reg_truncated_to_mode (enum machine_mode, const_rtx);
449 static rtx gen_lowpart_or_truncate (enum machine_mode, rtx);
452 /* It is not safe to use ordinary gen_lowpart in combine.
453 See comments in gen_lowpart_for_combine. */
454 #undef RTL_HOOKS_GEN_LOWPART
455 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
457 /* Our implementation of gen_lowpart never emits a new pseudo. */
458 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
459 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
461 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
462 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
464 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
465 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
467 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
468 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
470 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
473 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
474 PATTERN can not be split. Otherwise, it returns an insn sequence.
475 This is a wrapper around split_insns which ensures that the
476 reg_stat vector is made larger if the splitter creates a new
480 combine_split_insns (rtx pattern, rtx insn)
485 ret = split_insns (pattern, insn);
486 nregs = max_reg_num ();
487 if (nregs > VEC_length (reg_stat_type, reg_stat))
488 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
492 /* This is used by find_single_use to locate an rtx in LOC that
493 contains exactly one use of DEST, which is typically either a REG
494 or CC0. It returns a pointer to the innermost rtx expression
495 containing DEST. Appearances of DEST that are being used to
496 totally replace it are not counted. */
499 find_single_use_1 (rtx dest, rtx *loc)
502 enum rtx_code code = GET_CODE (x);
520 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
521 of a REG that occupies all of the REG, the insn uses DEST if
522 it is mentioned in the destination or the source. Otherwise, we
523 need just check the source. */
524 if (GET_CODE (SET_DEST (x)) != CC0
525 && GET_CODE (SET_DEST (x)) != PC
526 && !REG_P (SET_DEST (x))
527 && ! (GET_CODE (SET_DEST (x)) == SUBREG
528 && REG_P (SUBREG_REG (SET_DEST (x)))
529 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
530 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
531 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
532 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
535 return find_single_use_1 (dest, &SET_SRC (x));
539 return find_single_use_1 (dest, &XEXP (x, 0));
545 /* If it wasn't one of the common cases above, check each expression and
546 vector of this code. Look for a unique usage of DEST. */
548 fmt = GET_RTX_FORMAT (code);
549 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
553 if (dest == XEXP (x, i)
554 || (REG_P (dest) && REG_P (XEXP (x, i))
555 && REGNO (dest) == REGNO (XEXP (x, i))))
558 this_result = find_single_use_1 (dest, &XEXP (x, i));
561 result = this_result;
562 else if (this_result)
563 /* Duplicate usage. */
566 else if (fmt[i] == 'E')
570 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
572 if (XVECEXP (x, i, j) == dest
574 && REG_P (XVECEXP (x, i, j))
575 && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
578 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
581 result = this_result;
582 else if (this_result)
592 /* See if DEST, produced in INSN, is used only a single time in the
593 sequel. If so, return a pointer to the innermost rtx expression in which
596 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
598 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
599 care about REG_DEAD notes or LOG_LINKS.
601 Otherwise, we find the single use by finding an insn that has a
602 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
603 only referenced once in that insn, we know that it must be the first
604 and last insn referencing DEST. */
607 find_single_use (rtx dest, rtx insn, rtx *ploc)
617 next = NEXT_INSN (insn);
619 || (!NONJUMP_INSN_P (next) && !JUMP_P (next)))
622 result = find_single_use_1 (dest, &PATTERN (next));
632 bb = BLOCK_FOR_INSN (insn);
633 for (next = NEXT_INSN (insn);
634 next && BLOCK_FOR_INSN (next) == bb;
635 next = NEXT_INSN (next))
636 if (INSN_P (next) && dead_or_set_p (next, dest))
638 for (link = LOG_LINKS (next); link; link = XEXP (link, 1))
639 if (XEXP (link, 0) == insn)
644 result = find_single_use_1 (dest, &PATTERN (next));
654 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
655 insn. The substitution can be undone by undo_all. If INTO is already
656 set to NEWVAL, do not record this change. Because computing NEWVAL might
657 also call SUBST, we have to compute it before we put anything into
661 do_SUBST (rtx *into, rtx newval)
666 if (oldval == newval)
669 /* We'd like to catch as many invalid transformations here as
670 possible. Unfortunately, there are way too many mode changes
671 that are perfectly valid, so we'd waste too much effort for
672 little gain doing the checks here. Focus on catching invalid
673 transformations involving integer constants. */
674 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
675 && CONST_INT_P (newval))
677 /* Sanity check that we're replacing oldval with a CONST_INT
678 that is a valid sign-extension for the original mode. */
679 gcc_assert (INTVAL (newval)
680 == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
682 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
683 CONST_INT is not valid, because after the replacement, the
684 original mode would be gone. Unfortunately, we can't tell
685 when do_SUBST is called to replace the operand thereof, so we
686 perform this test on oldval instead, checking whether an
687 invalid replacement took place before we got here. */
688 gcc_assert (!(GET_CODE (oldval) == SUBREG
689 && CONST_INT_P (SUBREG_REG (oldval))));
690 gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
691 && CONST_INT_P (XEXP (oldval, 0))));
695 buf = undobuf.frees, undobuf.frees = buf->next;
697 buf = XNEW (struct undo);
699 buf->kind = UNDO_RTX;
701 buf->old_contents.r = oldval;
704 buf->next = undobuf.undos, undobuf.undos = buf;
707 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
709 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
710 for the value of a HOST_WIDE_INT value (including CONST_INT) is
714 do_SUBST_INT (int *into, int newval)
719 if (oldval == newval)
723 buf = undobuf.frees, undobuf.frees = buf->next;
725 buf = XNEW (struct undo);
727 buf->kind = UNDO_INT;
729 buf->old_contents.i = oldval;
732 buf->next = undobuf.undos, undobuf.undos = buf;
735 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
737 /* Similar to SUBST, but just substitute the mode. This is used when
738 changing the mode of a pseudo-register, so that any other
739 references to the entry in the regno_reg_rtx array will change as
743 do_SUBST_MODE (rtx *into, enum machine_mode newval)
746 enum machine_mode oldval = GET_MODE (*into);
748 if (oldval == newval)
752 buf = undobuf.frees, undobuf.frees = buf->next;
754 buf = XNEW (struct undo);
756 buf->kind = UNDO_MODE;
758 buf->old_contents.m = oldval;
759 adjust_reg_mode (*into, newval);
761 buf->next = undobuf.undos, undobuf.undos = buf;
764 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE(&(INTO), (NEWVAL))
766 /* Subroutine of try_combine. Determine whether the combine replacement
767 patterns NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to
768 insn_rtx_cost that the original instruction sequence I0, I1, I2, I3 and
769 undobuf.other_insn. Note that I1 and/or NEWI2PAT may be NULL_RTX.
770 NEWOTHERPAT and undobuf.other_insn may also both be NULL_RTX. This
771 function returns false, if the costs of all instructions can be
772 estimated, and the replacements are more expensive than the original
776 combine_validate_cost (rtx i0, rtx i1, rtx i2, rtx i3, rtx newpat,
777 rtx newi2pat, rtx newotherpat)
779 int i0_cost, i1_cost, i2_cost, i3_cost;
780 int new_i2_cost, new_i3_cost;
781 int old_cost, new_cost;
783 /* Lookup the original insn_rtx_costs. */
784 i2_cost = INSN_COST (i2);
785 i3_cost = INSN_COST (i3);
789 i1_cost = INSN_COST (i1);
792 i0_cost = INSN_COST (i0);
793 old_cost = (i0_cost > 0 && i1_cost > 0 && i2_cost > 0 && i3_cost > 0
794 ? i0_cost + i1_cost + i2_cost + i3_cost : 0);
798 old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0
799 ? i1_cost + i2_cost + i3_cost : 0);
805 old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
806 i1_cost = i0_cost = 0;
809 /* Calculate the replacement insn_rtx_costs. */
810 new_i3_cost = insn_rtx_cost (newpat, optimize_this_for_speed_p);
813 new_i2_cost = insn_rtx_cost (newi2pat, optimize_this_for_speed_p);
814 new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
815 ? new_i2_cost + new_i3_cost : 0;
819 new_cost = new_i3_cost;
823 if (undobuf.other_insn)
825 int old_other_cost, new_other_cost;
827 old_other_cost = INSN_COST (undobuf.other_insn);
828 new_other_cost = insn_rtx_cost (newotherpat, optimize_this_for_speed_p);
829 if (old_other_cost > 0 && new_other_cost > 0)
831 old_cost += old_other_cost;
832 new_cost += new_other_cost;
838 /* Disallow this recombination if both new_cost and old_cost are
839 greater than zero, and new_cost is greater than old cost. */
841 && new_cost > old_cost)
848 "rejecting combination of insns %d, %d, %d and %d\n",
849 INSN_UID (i0), INSN_UID (i1), INSN_UID (i2),
851 fprintf (dump_file, "original costs %d + %d + %d + %d = %d\n",
852 i0_cost, i1_cost, i2_cost, i3_cost, old_cost);
857 "rejecting combination of insns %d, %d and %d\n",
858 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
859 fprintf (dump_file, "original costs %d + %d + %d = %d\n",
860 i1_cost, i2_cost, i3_cost, old_cost);
865 "rejecting combination of insns %d and %d\n",
866 INSN_UID (i2), INSN_UID (i3));
867 fprintf (dump_file, "original costs %d + %d = %d\n",
868 i2_cost, i3_cost, old_cost);
873 fprintf (dump_file, "replacement costs %d + %d = %d\n",
874 new_i2_cost, new_i3_cost, new_cost);
877 fprintf (dump_file, "replacement cost %d\n", new_cost);
883 /* Update the uid_insn_cost array with the replacement costs. */
884 INSN_COST (i2) = new_i2_cost;
885 INSN_COST (i3) = new_i3_cost;
893 /* Delete any insns that copy a register to itself. */
896 delete_noop_moves (void)
903 for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
905 next = NEXT_INSN (insn);
906 if (INSN_P (insn) && noop_move_p (insn))
909 fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn));
911 delete_insn_and_edges (insn);
918 /* Fill in log links field for all insns. */
921 create_log_links (void)
925 df_ref *def_vec, *use_vec;
927 next_use = XCNEWVEC (rtx, max_reg_num ());
929 /* Pass through each block from the end, recording the uses of each
930 register and establishing log links when def is encountered.
931 Note that we do not clear next_use array in order to save time,
932 so we have to test whether the use is in the same basic block as def.
934 There are a few cases below when we do not consider the definition or
935 usage -- these are taken from original flow.c did. Don't ask me why it is
936 done this way; I don't know and if it works, I don't want to know. */
940 FOR_BB_INSNS_REVERSE (bb, insn)
942 if (!NONDEBUG_INSN_P (insn))
945 /* Log links are created only once. */
946 gcc_assert (!LOG_LINKS (insn));
948 for (def_vec = DF_INSN_DEFS (insn); *def_vec; def_vec++)
950 df_ref def = *def_vec;
951 int regno = DF_REF_REGNO (def);
954 if (!next_use[regno])
957 /* Do not consider if it is pre/post modification in MEM. */
958 if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY)
961 /* Do not make the log link for frame pointer. */
962 if ((regno == FRAME_POINTER_REGNUM
963 && (! reload_completed || frame_pointer_needed))
964 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
965 || (regno == HARD_FRAME_POINTER_REGNUM
966 && (! reload_completed || frame_pointer_needed))
968 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
969 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
974 use_insn = next_use[regno];
975 if (BLOCK_FOR_INSN (use_insn) == bb)
979 We don't build a LOG_LINK for hard registers contained
980 in ASM_OPERANDs. If these registers get replaced,
981 we might wind up changing the semantics of the insn,
982 even if reload can make what appear to be valid
983 assignments later. */
984 if (regno >= FIRST_PSEUDO_REGISTER
985 || asm_noperands (PATTERN (use_insn)) < 0)
987 /* Don't add duplicate links between instructions. */
989 for (links = LOG_LINKS (use_insn); links;
990 links = XEXP (links, 1))
991 if (insn == XEXP (links, 0))
995 LOG_LINKS (use_insn) =
996 alloc_INSN_LIST (insn, LOG_LINKS (use_insn));
999 next_use[regno] = NULL_RTX;
1002 for (use_vec = DF_INSN_USES (insn); *use_vec; use_vec++)
1004 df_ref use = *use_vec;
1005 int regno = DF_REF_REGNO (use);
1007 /* Do not consider the usage of the stack pointer
1008 by function call. */
1009 if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE)
1012 next_use[regno] = insn;
1020 /* Clear LOG_LINKS fields of insns. */
1023 clear_log_links (void)
1027 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
1029 free_INSN_LIST_list (&LOG_LINKS (insn));
1032 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1033 true if we found a LOG_LINK that proves that A feeds B. This only works
1034 if there are no instructions between A and B which could have a link
1035 depending on A, since in that case we would not record a link for B.
1036 We also check the implicit dependency created by a cc0 setter/user
1040 insn_a_feeds_b (rtx a, rtx b)
1043 for (links = LOG_LINKS (b); links; links = XEXP (links, 1))
1044 if (XEXP (links, 0) == a)
1053 /* Main entry point for combiner. F is the first insn of the function.
1054 NREGS is the first unused pseudo-reg number.
1056 Return nonzero if the combiner has turned an indirect jump
1057 instruction into a direct jump. */
1059 combine_instructions (rtx f, unsigned int nregs)
1065 rtx links, nextlinks;
1067 basic_block last_bb;
1069 int new_direct_jump_p = 0;
1071 for (first = f; first && !INSN_P (first); )
1072 first = NEXT_INSN (first);
1076 combine_attempts = 0;
1079 combine_successes = 0;
1081 rtl_hooks = combine_rtl_hooks;
1083 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
1085 init_recog_no_volatile ();
1087 /* Allocate array for insn info. */
1088 max_uid_known = get_max_uid ();
1089 uid_log_links = XCNEWVEC (rtx, max_uid_known + 1);
1090 uid_insn_cost = XCNEWVEC (int, max_uid_known + 1);
1092 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
1094 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1095 problems when, for example, we have j <<= 1 in a loop. */
1097 nonzero_sign_valid = 0;
1098 label_tick = label_tick_ebb_start = 1;
1100 /* Scan all SETs and see if we can deduce anything about what
1101 bits are known to be zero for some registers and how many copies
1102 of the sign bit are known to exist for those registers.
1104 Also set any known values so that we can use it while searching
1105 for what bits are known to be set. */
1107 setup_incoming_promotions (first);
1108 /* Allow the entry block and the first block to fall into the same EBB.
1109 Conceptually the incoming promotions are assigned to the entry block. */
1110 last_bb = ENTRY_BLOCK_PTR;
1112 create_log_links ();
1113 FOR_EACH_BB (this_basic_block)
1115 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1120 if (!single_pred_p (this_basic_block)
1121 || single_pred (this_basic_block) != last_bb)
1122 label_tick_ebb_start = label_tick;
1123 last_bb = this_basic_block;
1125 FOR_BB_INSNS (this_basic_block, insn)
1126 if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
1128 subst_low_luid = DF_INSN_LUID (insn);
1131 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
1133 record_dead_and_set_regs (insn);
1136 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
1137 if (REG_NOTE_KIND (links) == REG_INC)
1138 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
1142 /* Record the current insn_rtx_cost of this instruction. */
1143 if (NONJUMP_INSN_P (insn))
1144 INSN_COST (insn) = insn_rtx_cost (PATTERN (insn),
1145 optimize_this_for_speed_p);
1147 fprintf(dump_file, "insn_cost %d: %d\n",
1148 INSN_UID (insn), INSN_COST (insn));
1152 nonzero_sign_valid = 1;
1154 /* Now scan all the insns in forward order. */
1155 label_tick = label_tick_ebb_start = 1;
1157 setup_incoming_promotions (first);
1158 last_bb = ENTRY_BLOCK_PTR;
1160 FOR_EACH_BB (this_basic_block)
1162 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1167 if (!single_pred_p (this_basic_block)
1168 || single_pred (this_basic_block) != last_bb)
1169 label_tick_ebb_start = label_tick;
1170 last_bb = this_basic_block;
1172 rtl_profile_for_bb (this_basic_block);
1173 for (insn = BB_HEAD (this_basic_block);
1174 insn != NEXT_INSN (BB_END (this_basic_block));
1175 insn = next ? next : NEXT_INSN (insn))
1178 if (NONDEBUG_INSN_P (insn))
1180 /* See if we know about function return values before this
1181 insn based upon SUBREG flags. */
1182 check_promoted_subreg (insn, PATTERN (insn));
1184 /* See if we can find hardregs and subreg of pseudos in
1185 narrower modes. This could help turning TRUNCATEs
1187 note_uses (&PATTERN (insn), record_truncated_values, NULL);
1189 /* Try this insn with each insn it links back to. */
1191 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1192 if ((next = try_combine (insn, XEXP (links, 0), NULL_RTX,
1193 NULL_RTX, &new_direct_jump_p)) != 0)
1196 /* Try each sequence of three linked insns ending with this one. */
1198 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1200 rtx link = XEXP (links, 0);
1202 /* If the linked insn has been replaced by a note, then there
1203 is no point in pursuing this chain any further. */
1207 for (nextlinks = LOG_LINKS (link);
1209 nextlinks = XEXP (nextlinks, 1))
1210 if ((next = try_combine (insn, link, XEXP (nextlinks, 0),
1212 &new_direct_jump_p)) != 0)
1217 /* Try to combine a jump insn that uses CC0
1218 with a preceding insn that sets CC0, and maybe with its
1219 logical predecessor as well.
1220 This is how we make decrement-and-branch insns.
1221 We need this special code because data flow connections
1222 via CC0 do not get entered in LOG_LINKS. */
1225 && (prev = prev_nonnote_insn (insn)) != 0
1226 && NONJUMP_INSN_P (prev)
1227 && sets_cc0_p (PATTERN (prev)))
1229 if ((next = try_combine (insn, prev, NULL_RTX, NULL_RTX,
1230 &new_direct_jump_p)) != 0)
1233 for (nextlinks = LOG_LINKS (prev); nextlinks;
1234 nextlinks = XEXP (nextlinks, 1))
1235 if ((next = try_combine (insn, prev, XEXP (nextlinks, 0),
1237 &new_direct_jump_p)) != 0)
1241 /* Do the same for an insn that explicitly references CC0. */
1242 if (NONJUMP_INSN_P (insn)
1243 && (prev = prev_nonnote_insn (insn)) != 0
1244 && NONJUMP_INSN_P (prev)
1245 && sets_cc0_p (PATTERN (prev))
1246 && GET_CODE (PATTERN (insn)) == SET
1247 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
1249 if ((next = try_combine (insn, prev, NULL_RTX, NULL_RTX,
1250 &new_direct_jump_p)) != 0)
1253 for (nextlinks = LOG_LINKS (prev); nextlinks;
1254 nextlinks = XEXP (nextlinks, 1))
1255 if ((next = try_combine (insn, prev, XEXP (nextlinks, 0),
1257 &new_direct_jump_p)) != 0)
1261 /* Finally, see if any of the insns that this insn links to
1262 explicitly references CC0. If so, try this insn, that insn,
1263 and its predecessor if it sets CC0. */
1264 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1265 if (NONJUMP_INSN_P (XEXP (links, 0))
1266 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
1267 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
1268 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
1269 && NONJUMP_INSN_P (prev)
1270 && sets_cc0_p (PATTERN (prev))
1271 && (next = try_combine (insn, XEXP (links, 0),
1273 &new_direct_jump_p)) != 0)
1277 /* Try combining an insn with two different insns whose results it
1279 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1280 for (nextlinks = XEXP (links, 1); nextlinks;
1281 nextlinks = XEXP (nextlinks, 1))
1282 if ((next = try_combine (insn, XEXP (links, 0),
1283 XEXP (nextlinks, 0), NULL_RTX,
1284 &new_direct_jump_p)) != 0)
1287 /* Try four-instruction combinations. */
1288 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1291 rtx link = XEXP (links, 0);
1293 /* If the linked insn has been replaced by a note, then there
1294 is no point in pursuing this chain any further. */
1298 for (next1 = LOG_LINKS (link); next1; next1 = XEXP (next1, 1))
1300 rtx link1 = XEXP (next1, 0);
1303 /* I0 -> I1 -> I2 -> I3. */
1304 for (nextlinks = LOG_LINKS (link1); nextlinks;
1305 nextlinks = XEXP (nextlinks, 1))
1306 if ((next = try_combine (insn, link, link1,
1307 XEXP (nextlinks, 0),
1308 &new_direct_jump_p)) != 0)
1310 /* I0, I1 -> I2, I2 -> I3. */
1311 for (nextlinks = XEXP (next1, 1); nextlinks;
1312 nextlinks = XEXP (nextlinks, 1))
1313 if ((next = try_combine (insn, link, link1,
1314 XEXP (nextlinks, 0),
1315 &new_direct_jump_p)) != 0)
1319 for (next1 = XEXP (links, 1); next1; next1 = XEXP (next1, 1))
1321 rtx link1 = XEXP (next1, 0);
1324 /* I0 -> I2; I1, I2 -> I3. */
1325 for (nextlinks = LOG_LINKS (link); nextlinks;
1326 nextlinks = XEXP (nextlinks, 1))
1327 if ((next = try_combine (insn, link, link1,
1328 XEXP (nextlinks, 0),
1329 &new_direct_jump_p)) != 0)
1331 /* I0 -> I1; I1, I2 -> I3. */
1332 for (nextlinks = LOG_LINKS (link1); nextlinks;
1333 nextlinks = XEXP (nextlinks, 1))
1334 if ((next = try_combine (insn, link, link1,
1335 XEXP (nextlinks, 0),
1336 &new_direct_jump_p)) != 0)
1341 /* Try this insn with each REG_EQUAL note it links back to. */
1342 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1345 rtx temp = XEXP (links, 0);
1346 if ((set = single_set (temp)) != 0
1347 && (note = find_reg_equal_equiv_note (temp)) != 0
1348 && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
1349 /* Avoid using a register that may already been marked
1350 dead by an earlier instruction. */
1351 && ! unmentioned_reg_p (note, SET_SRC (set))
1352 && (GET_MODE (note) == VOIDmode
1353 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
1354 : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
1356 /* Temporarily replace the set's source with the
1357 contents of the REG_EQUAL note. The insn will
1358 be deleted or recognized by try_combine. */
1359 rtx orig = SET_SRC (set);
1360 SET_SRC (set) = note;
1362 i2mod_old_rhs = copy_rtx (orig);
1363 i2mod_new_rhs = copy_rtx (note);
1364 next = try_combine (insn, i2mod, NULL_RTX, NULL_RTX,
1365 &new_direct_jump_p);
1369 SET_SRC (set) = orig;
1374 record_dead_and_set_regs (insn);
1382 default_rtl_profile ();
1385 new_direct_jump_p |= purge_all_dead_edges ();
1386 delete_noop_moves ();
1389 free (uid_log_links);
1390 free (uid_insn_cost);
1391 VEC_free (reg_stat_type, heap, reg_stat);
1394 struct undo *undo, *next;
1395 for (undo = undobuf.frees; undo; undo = next)
1403 total_attempts += combine_attempts;
1404 total_merges += combine_merges;
1405 total_extras += combine_extras;
1406 total_successes += combine_successes;
1408 nonzero_sign_valid = 0;
1409 rtl_hooks = general_rtl_hooks;
1411 /* Make recognizer allow volatile MEMs again. */
1414 return new_direct_jump_p;
1417 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1420 init_reg_last (void)
1425 FOR_EACH_VEC_ELT (reg_stat_type, reg_stat, i, p)
1426 memset (p, 0, offsetof (reg_stat_type, sign_bit_copies));
1429 /* Set up any promoted values for incoming argument registers. */
1432 setup_incoming_promotions (rtx first)
1435 bool strictly_local = false;
1437 for (arg = DECL_ARGUMENTS (current_function_decl); arg;
1438 arg = DECL_CHAIN (arg))
1440 rtx x, reg = DECL_INCOMING_RTL (arg);
1442 enum machine_mode mode1, mode2, mode3, mode4;
1444 /* Only continue if the incoming argument is in a register. */
1448 /* Determine, if possible, whether all call sites of the current
1449 function lie within the current compilation unit. (This does
1450 take into account the exporting of a function via taking its
1451 address, and so forth.) */
1452 strictly_local = cgraph_local_info (current_function_decl)->local;
1454 /* The mode and signedness of the argument before any promotions happen
1455 (equal to the mode of the pseudo holding it at that stage). */
1456 mode1 = TYPE_MODE (TREE_TYPE (arg));
1457 uns1 = TYPE_UNSIGNED (TREE_TYPE (arg));
1459 /* The mode and signedness of the argument after any source language and
1460 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1461 mode2 = TYPE_MODE (DECL_ARG_TYPE (arg));
1462 uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg));
1464 /* The mode and signedness of the argument as it is actually passed,
1465 after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */
1466 mode3 = promote_function_mode (DECL_ARG_TYPE (arg), mode2, &uns3,
1467 TREE_TYPE (cfun->decl), 0);
1469 /* The mode of the register in which the argument is being passed. */
1470 mode4 = GET_MODE (reg);
1472 /* Eliminate sign extensions in the callee when:
1473 (a) A mode promotion has occurred; */
1476 /* (b) The mode of the register is the same as the mode of
1477 the argument as it is passed; */
1480 /* (c) There's no language level extension; */
1483 /* (c.1) All callers are from the current compilation unit. If that's
1484 the case we don't have to rely on an ABI, we only have to know
1485 what we're generating right now, and we know that we will do the
1486 mode1 to mode2 promotion with the given sign. */
1487 else if (!strictly_local)
1489 /* (c.2) The combination of the two promotions is useful. This is
1490 true when the signs match, or if the first promotion is unsigned.
1491 In the later case, (sign_extend (zero_extend x)) is the same as
1492 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1498 /* Record that the value was promoted from mode1 to mode3,
1499 so that any sign extension at the head of the current
1500 function may be eliminated. */
1501 x = gen_rtx_CLOBBER (mode1, const0_rtx);
1502 x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x);
1503 record_value_for_reg (reg, first, x);
1507 /* Called via note_stores. If X is a pseudo that is narrower than
1508 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1510 If we are setting only a portion of X and we can't figure out what
1511 portion, assume all bits will be used since we don't know what will
1514 Similarly, set how many bits of X are known to be copies of the sign bit
1515 at all locations in the function. This is the smallest number implied
1519 set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data)
1521 rtx insn = (rtx) data;
1525 && REGNO (x) >= FIRST_PSEUDO_REGISTER
1526 /* If this register is undefined at the start of the file, we can't
1527 say what its contents were. */
1528 && ! REGNO_REG_SET_P
1529 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x))
1530 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
1532 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
1534 if (set == 0 || GET_CODE (set) == CLOBBER)
1536 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1537 rsp->sign_bit_copies = 1;
1541 /* If this register is being initialized using itself, and the
1542 register is uninitialized in this basic block, and there are
1543 no LOG_LINKS which set the register, then part of the
1544 register is uninitialized. In that case we can't assume
1545 anything about the number of nonzero bits.
1547 ??? We could do better if we checked this in
1548 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1549 could avoid making assumptions about the insn which initially
1550 sets the register, while still using the information in other
1551 insns. We would have to be careful to check every insn
1552 involved in the combination. */
1555 && reg_referenced_p (x, PATTERN (insn))
1556 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)),
1561 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
1563 if (dead_or_set_p (XEXP (link, 0), x))
1568 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1569 rsp->sign_bit_copies = 1;
1574 /* If this is a complex assignment, see if we can convert it into a
1575 simple assignment. */
1576 set = expand_field_assignment (set);
1578 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1579 set what we know about X. */
1581 if (SET_DEST (set) == x
1582 || (GET_CODE (SET_DEST (set)) == SUBREG
1583 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
1584 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
1585 && SUBREG_REG (SET_DEST (set)) == x))
1587 rtx src = SET_SRC (set);
1589 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1590 /* If X is narrower than a word and SRC is a non-negative
1591 constant that would appear negative in the mode of X,
1592 sign-extend it for use in reg_stat[].nonzero_bits because some
1593 machines (maybe most) will actually do the sign-extension
1594 and this is the conservative approach.
1596 ??? For 2.5, try to tighten up the MD files in this regard
1597 instead of this kludge. */
1599 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
1600 && CONST_INT_P (src)
1602 && 0 != (UINTVAL (src)
1603 & ((unsigned HOST_WIDE_INT) 1
1604 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
1605 src = GEN_INT (UINTVAL (src)
1606 | ((unsigned HOST_WIDE_INT) (-1)
1607 << GET_MODE_BITSIZE (GET_MODE (x))));
1610 /* Don't call nonzero_bits if it cannot change anything. */
1611 if (rsp->nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1612 rsp->nonzero_bits |= nonzero_bits (src, nonzero_bits_mode);
1613 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1614 if (rsp->sign_bit_copies == 0
1615 || rsp->sign_bit_copies > num)
1616 rsp->sign_bit_copies = num;
1620 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1621 rsp->sign_bit_copies = 1;
1626 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1627 optionally insns that were previously combined into I3 or that will be
1628 combined into the merger of INSN and I3. The order is PRED, PRED2,
1629 INSN, SUCC, SUCC2, I3.
1631 Return 0 if the combination is not allowed for any reason.
1633 If the combination is allowed, *PDEST will be set to the single
1634 destination of INSN and *PSRC to the single source, and this function
1638 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED,
1639 rtx pred2 ATTRIBUTE_UNUSED, rtx succ, rtx succ2,
1640 rtx *pdest, rtx *psrc)
1649 bool all_adjacent = true;
1655 if (next_active_insn (succ2) != i3)
1656 all_adjacent = false;
1657 if (next_active_insn (succ) != succ2)
1658 all_adjacent = false;
1660 else if (next_active_insn (succ) != i3)
1661 all_adjacent = false;
1662 if (next_active_insn (insn) != succ)
1663 all_adjacent = false;
1665 else if (next_active_insn (insn) != i3)
1666 all_adjacent = false;
1668 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1669 or a PARALLEL consisting of such a SET and CLOBBERs.
1671 If INSN has CLOBBER parallel parts, ignore them for our processing.
1672 By definition, these happen during the execution of the insn. When it
1673 is merged with another insn, all bets are off. If they are, in fact,
1674 needed and aren't also supplied in I3, they may be added by
1675 recog_for_combine. Otherwise, it won't match.
1677 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1680 Get the source and destination of INSN. If more than one, can't
1683 if (GET_CODE (PATTERN (insn)) == SET)
1684 set = PATTERN (insn);
1685 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1686 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1688 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1690 rtx elt = XVECEXP (PATTERN (insn), 0, i);
1692 switch (GET_CODE (elt))
1694 /* This is important to combine floating point insns
1695 for the SH4 port. */
1697 /* Combining an isolated USE doesn't make sense.
1698 We depend here on combinable_i3pat to reject them. */
1699 /* The code below this loop only verifies that the inputs of
1700 the SET in INSN do not change. We call reg_set_between_p
1701 to verify that the REG in the USE does not change between
1703 If the USE in INSN was for a pseudo register, the matching
1704 insn pattern will likely match any register; combining this
1705 with any other USE would only be safe if we knew that the
1706 used registers have identical values, or if there was
1707 something to tell them apart, e.g. different modes. For
1708 now, we forgo such complicated tests and simply disallow
1709 combining of USES of pseudo registers with any other USE. */
1710 if (REG_P (XEXP (elt, 0))
1711 && GET_CODE (PATTERN (i3)) == PARALLEL)
1713 rtx i3pat = PATTERN (i3);
1714 int i = XVECLEN (i3pat, 0) - 1;
1715 unsigned int regno = REGNO (XEXP (elt, 0));
1719 rtx i3elt = XVECEXP (i3pat, 0, i);
1721 if (GET_CODE (i3elt) == USE
1722 && REG_P (XEXP (i3elt, 0))
1723 && (REGNO (XEXP (i3elt, 0)) == regno
1724 ? reg_set_between_p (XEXP (elt, 0),
1725 PREV_INSN (insn), i3)
1726 : regno >= FIRST_PSEUDO_REGISTER))
1733 /* We can ignore CLOBBERs. */
1738 /* Ignore SETs whose result isn't used but not those that
1739 have side-effects. */
1740 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1741 && insn_nothrow_p (insn)
1742 && !side_effects_p (elt))
1745 /* If we have already found a SET, this is a second one and
1746 so we cannot combine with this insn. */
1754 /* Anything else means we can't combine. */
1760 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1761 so don't do anything with it. */
1762 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1771 set = expand_field_assignment (set);
1772 src = SET_SRC (set), dest = SET_DEST (set);
1774 /* Don't eliminate a store in the stack pointer. */
1775 if (dest == stack_pointer_rtx
1776 /* Don't combine with an insn that sets a register to itself if it has
1777 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1778 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1779 /* Can't merge an ASM_OPERANDS. */
1780 || GET_CODE (src) == ASM_OPERANDS
1781 /* Can't merge a function call. */
1782 || GET_CODE (src) == CALL
1783 /* Don't eliminate a function call argument. */
1785 && (find_reg_fusage (i3, USE, dest)
1787 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1788 && global_regs[REGNO (dest)])))
1789 /* Don't substitute into an incremented register. */
1790 || FIND_REG_INC_NOTE (i3, dest)
1791 || (succ && FIND_REG_INC_NOTE (succ, dest))
1792 || (succ2 && FIND_REG_INC_NOTE (succ2, dest))
1793 /* Don't substitute into a non-local goto, this confuses CFG. */
1794 || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1795 /* Make sure that DEST is not used after SUCC but before I3. */
1798 && (reg_used_between_p (dest, succ2, i3)
1799 || reg_used_between_p (dest, succ, succ2)))
1800 || (!succ2 && succ && reg_used_between_p (dest, succ, i3))))
1801 /* Make sure that the value that is to be substituted for the register
1802 does not use any registers whose values alter in between. However,
1803 If the insns are adjacent, a use can't cross a set even though we
1804 think it might (this can happen for a sequence of insns each setting
1805 the same destination; last_set of that register might point to
1806 a NOTE). If INSN has a REG_EQUIV note, the register is always
1807 equivalent to the memory so the substitution is valid even if there
1808 are intervening stores. Also, don't move a volatile asm or
1809 UNSPEC_VOLATILE across any other insns. */
1812 || ! find_reg_note (insn, REG_EQUIV, src))
1813 && use_crosses_set_p (src, DF_INSN_LUID (insn)))
1814 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1815 || GET_CODE (src) == UNSPEC_VOLATILE))
1816 /* Don't combine across a CALL_INSN, because that would possibly
1817 change whether the life span of some REGs crosses calls or not,
1818 and it is a pain to update that information.
1819 Exception: if source is a constant, moving it later can't hurt.
1820 Accept that as a special case. */
1821 || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src)))
1824 /* DEST must either be a REG or CC0. */
1827 /* If register alignment is being enforced for multi-word items in all
1828 cases except for parameters, it is possible to have a register copy
1829 insn referencing a hard register that is not allowed to contain the
1830 mode being copied and which would not be valid as an operand of most
1831 insns. Eliminate this problem by not combining with such an insn.
1833 Also, on some machines we don't want to extend the life of a hard
1837 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1838 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1839 /* Don't extend the life of a hard register unless it is
1840 user variable (if we have few registers) or it can't
1841 fit into the desired register (meaning something special
1843 Also avoid substituting a return register into I3, because
1844 reload can't handle a conflict with constraints of other
1846 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1847 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1850 else if (GET_CODE (dest) != CC0)
1854 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1855 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1856 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1858 /* Don't substitute for a register intended as a clobberable
1860 rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1861 if (rtx_equal_p (reg, dest))
1864 /* If the clobber represents an earlyclobber operand, we must not
1865 substitute an expression containing the clobbered register.
1866 As we do not analyze the constraint strings here, we have to
1867 make the conservative assumption. However, if the register is
1868 a fixed hard reg, the clobber cannot represent any operand;
1869 we leave it up to the machine description to either accept or
1870 reject use-and-clobber patterns. */
1872 || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1873 || !fixed_regs[REGNO (reg)])
1874 if (reg_overlap_mentioned_p (reg, src))
1878 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1879 or not), reject, unless nothing volatile comes between it and I3 */
1881 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1883 /* Make sure neither succ nor succ2 contains a volatile reference. */
1884 if (succ2 != 0 && volatile_refs_p (PATTERN (succ2)))
1886 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1888 /* We'll check insns between INSN and I3 below. */
1891 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1892 to be an explicit register variable, and was chosen for a reason. */
1894 if (GET_CODE (src) == ASM_OPERANDS
1895 && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1898 /* If there are any volatile insns between INSN and I3, reject, because
1899 they might affect machine state. */
1901 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1902 if (INSN_P (p) && p != succ && p != succ2 && volatile_insn_p (PATTERN (p)))
1905 /* If INSN contains an autoincrement or autodecrement, make sure that
1906 register is not used between there and I3, and not already used in
1907 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1908 Also insist that I3 not be a jump; if it were one
1909 and the incremented register were spilled, we would lose. */
1912 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1913 if (REG_NOTE_KIND (link) == REG_INC
1915 || reg_used_between_p (XEXP (link, 0), insn, i3)
1916 || (pred != NULL_RTX
1917 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1918 || (pred2 != NULL_RTX
1919 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred2)))
1920 || (succ != NULL_RTX
1921 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1922 || (succ2 != NULL_RTX
1923 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ2)))
1924 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1929 /* Don't combine an insn that follows a CC0-setting insn.
1930 An insn that uses CC0 must not be separated from the one that sets it.
1931 We do, however, allow I2 to follow a CC0-setting insn if that insn
1932 is passed as I1; in that case it will be deleted also.
1933 We also allow combining in this case if all the insns are adjacent
1934 because that would leave the two CC0 insns adjacent as well.
1935 It would be more logical to test whether CC0 occurs inside I1 or I2,
1936 but that would be much slower, and this ought to be equivalent. */
1938 p = prev_nonnote_insn (insn);
1939 if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
1944 /* If we get here, we have passed all the tests and the combination is
1953 /* LOC is the location within I3 that contains its pattern or the component
1954 of a PARALLEL of the pattern. We validate that it is valid for combining.
1956 One problem is if I3 modifies its output, as opposed to replacing it
1957 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
1958 doing so would produce an insn that is not equivalent to the original insns.
1962 (set (reg:DI 101) (reg:DI 100))
1963 (set (subreg:SI (reg:DI 101) 0) <foo>)
1965 This is NOT equivalent to:
1967 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1968 (set (reg:DI 101) (reg:DI 100))])
1970 Not only does this modify 100 (in which case it might still be valid
1971 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1973 We can also run into a problem if I2 sets a register that I1
1974 uses and I1 gets directly substituted into I3 (not via I2). In that
1975 case, we would be getting the wrong value of I2DEST into I3, so we
1976 must reject the combination. This case occurs when I2 and I1 both
1977 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1978 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1979 of a SET must prevent combination from occurring. The same situation
1980 can occur for I0, in which case I0_NOT_IN_SRC is set.
1982 Before doing the above check, we first try to expand a field assignment
1983 into a set of logical operations.
1985 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1986 we place a register that is both set and used within I3. If more than one
1987 such register is detected, we fail.
1989 Return 1 if the combination is valid, zero otherwise. */
1992 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest, rtx i0dest,
1993 int i1_not_in_src, int i0_not_in_src, rtx *pi3dest_killed)
1997 if (GET_CODE (x) == SET)
2000 rtx dest = SET_DEST (set);
2001 rtx src = SET_SRC (set);
2002 rtx inner_dest = dest;
2005 while (GET_CODE (inner_dest) == STRICT_LOW_PART
2006 || GET_CODE (inner_dest) == SUBREG
2007 || GET_CODE (inner_dest) == ZERO_EXTRACT)
2008 inner_dest = XEXP (inner_dest, 0);
2010 /* Check for the case where I3 modifies its output, as discussed
2011 above. We don't want to prevent pseudos from being combined
2012 into the address of a MEM, so only prevent the combination if
2013 i1 or i2 set the same MEM. */
2014 if ((inner_dest != dest &&
2015 (!MEM_P (inner_dest)
2016 || rtx_equal_p (i2dest, inner_dest)
2017 || (i1dest && rtx_equal_p (i1dest, inner_dest))
2018 || (i0dest && rtx_equal_p (i0dest, inner_dest)))
2019 && (reg_overlap_mentioned_p (i2dest, inner_dest)
2020 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))
2021 || (i0dest && reg_overlap_mentioned_p (i0dest, inner_dest))))
2023 /* This is the same test done in can_combine_p except we can't test
2024 all_adjacent; we don't have to, since this instruction will stay
2025 in place, thus we are not considering increasing the lifetime of
2028 Also, if this insn sets a function argument, combining it with
2029 something that might need a spill could clobber a previous
2030 function argument; the all_adjacent test in can_combine_p also
2031 checks this; here, we do a more specific test for this case. */
2033 || (REG_P (inner_dest)
2034 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
2035 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
2036 GET_MODE (inner_dest))))
2037 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src))
2038 || (i0_not_in_src && reg_overlap_mentioned_p (i0dest, src)))
2041 /* If DEST is used in I3, it is being killed in this insn, so
2042 record that for later. We have to consider paradoxical
2043 subregs here, since they kill the whole register, but we
2044 ignore partial subregs, STRICT_LOW_PART, etc.
2045 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2046 STACK_POINTER_REGNUM, since these are always considered to be
2047 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2049 if (GET_CODE (subdest) == SUBREG
2050 && (GET_MODE_SIZE (GET_MODE (subdest))
2051 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
2052 subdest = SUBREG_REG (subdest);
2055 && reg_referenced_p (subdest, PATTERN (i3))
2056 && REGNO (subdest) != FRAME_POINTER_REGNUM
2057 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2058 && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
2060 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2061 && (REGNO (subdest) != ARG_POINTER_REGNUM
2062 || ! fixed_regs [REGNO (subdest)])
2064 && REGNO (subdest) != STACK_POINTER_REGNUM)
2066 if (*pi3dest_killed)
2069 *pi3dest_killed = subdest;
2073 else if (GET_CODE (x) == PARALLEL)
2077 for (i = 0; i < XVECLEN (x, 0); i++)
2078 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest, i0dest,
2079 i1_not_in_src, i0_not_in_src, pi3dest_killed))
2086 /* Return 1 if X is an arithmetic expression that contains a multiplication
2087 and division. We don't count multiplications by powers of two here. */
2090 contains_muldiv (rtx x)
2092 switch (GET_CODE (x))
2094 case MOD: case DIV: case UMOD: case UDIV:
2098 return ! (CONST_INT_P (XEXP (x, 1))
2099 && exact_log2 (UINTVAL (XEXP (x, 1))) >= 0);
2102 return contains_muldiv (XEXP (x, 0))
2103 || contains_muldiv (XEXP (x, 1));
2106 return contains_muldiv (XEXP (x, 0));
2112 /* Determine whether INSN can be used in a combination. Return nonzero if
2113 not. This is used in try_combine to detect early some cases where we
2114 can't perform combinations. */
2117 cant_combine_insn_p (rtx insn)
2122 /* If this isn't really an insn, we can't do anything.
2123 This can occur when flow deletes an insn that it has merged into an
2124 auto-increment address. */
2125 if (! INSN_P (insn))
2128 /* Never combine loads and stores involving hard regs that are likely
2129 to be spilled. The register allocator can usually handle such
2130 reg-reg moves by tying. If we allow the combiner to make
2131 substitutions of likely-spilled regs, reload might die.
2132 As an exception, we allow combinations involving fixed regs; these are
2133 not available to the register allocator so there's no risk involved. */
2135 set = single_set (insn);
2138 src = SET_SRC (set);
2139 dest = SET_DEST (set);
2140 if (GET_CODE (src) == ZERO_EXTEND
2141 || GET_CODE (src) == SIGN_EXTEND)
2142 src = XEXP (src, 0);
2143 if (GET_CODE (dest) == ZERO_EXTEND
2144 || GET_CODE (dest) == SIGN_EXTEND)
2145 dest = XEXP (dest, 0);
2146 if (GET_CODE (src) == SUBREG)
2147 src = SUBREG_REG (src);
2148 if (GET_CODE (dest) == SUBREG)
2149 dest = SUBREG_REG (dest);
2150 if (REG_P (src) && REG_P (dest)
2151 && ((HARD_REGISTER_P (src)
2152 && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (src))
2153 && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src))))
2154 || (HARD_REGISTER_P (dest)
2155 && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (dest))
2156 && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest))))))
2162 struct likely_spilled_retval_info
2164 unsigned regno, nregs;
2168 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2169 hard registers that are known to be written to / clobbered in full. */
2171 likely_spilled_retval_1 (rtx x, const_rtx set, void *data)
2173 struct likely_spilled_retval_info *const info =
2174 (struct likely_spilled_retval_info *) data;
2175 unsigned regno, nregs;
2178 if (!REG_P (XEXP (set, 0)))
2181 if (regno >= info->regno + info->nregs)
2183 nregs = hard_regno_nregs[regno][GET_MODE (x)];
2184 if (regno + nregs <= info->regno)
2186 new_mask = (2U << (nregs - 1)) - 1;
2187 if (regno < info->regno)
2188 new_mask >>= info->regno - regno;
2190 new_mask <<= regno - info->regno;
2191 info->mask &= ~new_mask;
2194 /* Return nonzero iff part of the return value is live during INSN, and
2195 it is likely spilled. This can happen when more than one insn is needed
2196 to copy the return value, e.g. when we consider to combine into the
2197 second copy insn for a complex value. */
2200 likely_spilled_retval_p (rtx insn)
2202 rtx use = BB_END (this_basic_block);
2204 unsigned regno, nregs;
2205 /* We assume here that no machine mode needs more than
2206 32 hard registers when the value overlaps with a register
2207 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2209 struct likely_spilled_retval_info info;
2211 if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
2213 reg = XEXP (PATTERN (use), 0);
2214 if (!REG_P (reg) || !targetm.calls.function_value_regno_p (REGNO (reg)))
2216 regno = REGNO (reg);
2217 nregs = hard_regno_nregs[regno][GET_MODE (reg)];
2220 mask = (2U << (nregs - 1)) - 1;
2222 /* Disregard parts of the return value that are set later. */
2226 for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
2228 note_stores (PATTERN (p), likely_spilled_retval_1, &info);
2231 /* Check if any of the (probably) live return value registers is
2236 if ((mask & 1 << nregs)
2237 && targetm.class_likely_spilled_p (REGNO_REG_CLASS (regno + nregs)))
2243 /* Adjust INSN after we made a change to its destination.
2245 Changing the destination can invalidate notes that say something about
2246 the results of the insn and a LOG_LINK pointing to the insn. */
2249 adjust_for_new_dest (rtx insn)
2251 /* For notes, be conservative and simply remove them. */
2252 remove_reg_equal_equiv_notes (insn);
2254 /* The new insn will have a destination that was previously the destination
2255 of an insn just above it. Call distribute_links to make a LOG_LINK from
2256 the next use of that destination. */
2257 distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX));
2259 df_insn_rescan (insn);
2262 /* Return TRUE if combine can reuse reg X in mode MODE.
2263 ADDED_SETS is nonzero if the original set is still required. */
2265 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
2273 /* Allow hard registers if the new mode is legal, and occupies no more
2274 registers than the old mode. */
2275 if (regno < FIRST_PSEUDO_REGISTER)
2276 return (HARD_REGNO_MODE_OK (regno, mode)
2277 && (hard_regno_nregs[regno][GET_MODE (x)]
2278 >= hard_regno_nregs[regno][mode]));
2280 /* Or a pseudo that is only used once. */
2281 return (REG_N_SETS (regno) == 1 && !added_sets
2282 && !REG_USERVAR_P (x));
2286 /* Check whether X, the destination of a set, refers to part of
2287 the register specified by REG. */
2290 reg_subword_p (rtx x, rtx reg)
2292 /* Check that reg is an integer mode register. */
2293 if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
2296 if (GET_CODE (x) == STRICT_LOW_PART
2297 || GET_CODE (x) == ZERO_EXTRACT)
2300 return GET_CODE (x) == SUBREG
2301 && SUBREG_REG (x) == reg
2302 && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
2306 /* Replace auto-increment addressing modes with explicit operations to access
2307 the same addresses without modifying the corresponding registers. */
2310 cleanup_auto_inc_dec (rtx src, enum machine_mode mem_mode)
2313 const RTX_CODE code = GET_CODE (x);
2329 /* SCRATCH must be shared because they represent distinct values. */
2332 if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
2337 if (shared_const_p (x))
2342 mem_mode = GET_MODE (x);
2347 gcc_assert (mem_mode != VOIDmode && mem_mode != BLKmode);
2348 return gen_rtx_PLUS (GET_MODE (x),
2349 cleanup_auto_inc_dec (XEXP (x, 0), mem_mode),
2350 GEN_INT (code == PRE_INC
2351 ? GET_MODE_SIZE (mem_mode)
2352 : -GET_MODE_SIZE (mem_mode)));
2358 return cleanup_auto_inc_dec (code == PRE_MODIFY
2359 ? XEXP (x, 1) : XEXP (x, 0),
2366 /* Copy the various flags, fields, and other information. We assume
2367 that all fields need copying, and then clear the fields that should
2368 not be copied. That is the sensible default behavior, and forces
2369 us to explicitly document why we are *not* copying a flag. */
2370 x = shallow_copy_rtx (x);
2372 /* We do not copy the USED flag, which is used as a mark bit during
2373 walks over the RTL. */
2374 RTX_FLAG (x, used) = 0;
2376 /* We do not copy FRAME_RELATED for INSNs. */
2378 RTX_FLAG (x, frame_related) = 0;
2380 fmt = GET_RTX_FORMAT (code);
2381 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2383 XEXP (x, i) = cleanup_auto_inc_dec (XEXP (x, i), mem_mode);
2384 else if (fmt[i] == 'E' || fmt[i] == 'V')
2387 XVEC (x, i) = rtvec_alloc (XVECLEN (x, i));
2388 for (j = 0; j < XVECLEN (x, i); j++)
2390 = cleanup_auto_inc_dec (XVECEXP (src, i, j), mem_mode);
2397 /* Auxiliary data structure for propagate_for_debug_stmt. */
2399 struct rtx_subst_pair
2405 /* DATA points to an rtx_subst_pair. Return the value that should be
2409 propagate_for_debug_subst (rtx from, const_rtx old_rtx, void *data)
2411 struct rtx_subst_pair *pair = (struct rtx_subst_pair *)data;
2413 if (!rtx_equal_p (from, old_rtx))
2415 if (!pair->adjusted)
2417 pair->adjusted = true;
2419 pair->to = cleanup_auto_inc_dec (pair->to, VOIDmode);
2421 pair->to = copy_rtx (pair->to);
2423 pair->to = make_compound_operation (pair->to, SET);
2426 return copy_rtx (pair->to);
2429 /* Replace all the occurrences of DEST with SRC in DEBUG_INSNs between INSN
2433 propagate_for_debug (rtx insn, rtx last, rtx dest, rtx src)
2437 struct rtx_subst_pair p;
2441 next = NEXT_INSN (insn);
2442 while (next != last)
2445 next = NEXT_INSN (insn);
2446 if (DEBUG_INSN_P (insn))
2448 loc = simplify_replace_fn_rtx (INSN_VAR_LOCATION_LOC (insn),
2449 dest, propagate_for_debug_subst, &p);
2450 if (loc == INSN_VAR_LOCATION_LOC (insn))
2452 INSN_VAR_LOCATION_LOC (insn) = loc;
2453 df_insn_rescan (insn);
2458 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2459 Note that the INSN should be deleted *after* removing dead edges, so
2460 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2461 but not for a (set (pc) (label_ref FOO)). */
2464 update_cfg_for_uncondjump (rtx insn)
2466 basic_block bb = BLOCK_FOR_INSN (insn);
2467 bool at_end = (BB_END (bb) == insn);
2470 purge_dead_edges (bb);
2473 if (at_end && EDGE_COUNT (bb->succs) == 1)
2477 single_succ_edge (bb)->flags |= EDGE_FALLTHRU;
2479 /* Remove barriers from the footer if there are any. */
2480 for (insn = bb->il.rtl->footer; insn; insn = NEXT_INSN (insn))
2481 if (BARRIER_P (insn))
2483 if (PREV_INSN (insn))
2484 NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
2486 bb->il.rtl->footer = NEXT_INSN (insn);
2487 if (NEXT_INSN (insn))
2488 PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
2490 else if (LABEL_P (insn))
2495 /* Try to combine the insns I0, I1 and I2 into I3.
2496 Here I0, I1 and I2 appear earlier than I3.
2497 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2500 If we are combining more than two insns and the resulting insn is not
2501 recognized, try splitting it into two insns. If that happens, I2 and I3
2502 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2503 Otherwise, I0, I1 and I2 are pseudo-deleted.
2505 Return 0 if the combination does not work. Then nothing is changed.
2506 If we did the combination, return the insn at which combine should
2509 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2510 new direct jump instruction. */
2513 try_combine (rtx i3, rtx i2, rtx i1, rtx i0, int *new_direct_jump_p)
2515 /* New patterns for I3 and I2, respectively. */
2516 rtx newpat, newi2pat = 0;
2517 rtvec newpat_vec_with_clobbers = 0;
2518 int substed_i2 = 0, substed_i1 = 0, substed_i0 = 0;
2519 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2521 int added_sets_0, added_sets_1, added_sets_2;
2522 /* Total number of SETs to put into I3. */
2524 /* Nonzero if I2's or I1's body now appears in I3. */
2525 int i2_is_used = 0, i1_is_used = 0;
2526 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2527 int insn_code_number, i2_code_number = 0, other_code_number = 0;
2528 /* Contains I3 if the destination of I3 is used in its source, which means
2529 that the old life of I3 is being killed. If that usage is placed into
2530 I2 and not in I3, a REG_DEAD note must be made. */
2531 rtx i3dest_killed = 0;
2532 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2533 rtx i2dest = 0, i2src = 0, i1dest = 0, i1src = 0, i0dest = 0, i0src = 0;
2534 /* Copy of SET_SRC of I1, if needed. */
2536 /* Set if I2DEST was reused as a scratch register. */
2537 bool i2scratch = false;
2538 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2539 rtx i0pat = 0, i1pat = 0, i2pat = 0;
2540 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2541 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
2542 int i0dest_in_i0src = 0, i1dest_in_i0src = 0, i2dest_in_i0src = 0;
2543 int i2dest_killed = 0, i1dest_killed = 0, i0dest_killed = 0;
2544 int i1_feeds_i2_n = 0, i0_feeds_i2_n = 0, i0_feeds_i1_n = 0;
2545 /* Notes that must be added to REG_NOTES in I3 and I2. */
2546 rtx new_i3_notes, new_i2_notes;
2547 /* Notes that we substituted I3 into I2 instead of the normal case. */
2548 int i3_subst_into_i2 = 0;
2549 /* Notes that I1, I2 or I3 is a MULT operation. */
2552 int changed_i3_dest = 0;
2558 rtx new_other_notes;
2561 /* Only try four-insn combinations when there's high likelihood of
2562 success. Look for simple insns, such as loads of constants or
2563 binary operations involving a constant. */
2570 if (!flag_expensive_optimizations)
2573 for (i = 0; i < 4; i++)
2575 rtx insn = i == 0 ? i0 : i == 1 ? i1 : i == 2 ? i2 : i3;
2576 rtx set = single_set (insn);
2580 src = SET_SRC (set);
2581 if (CONSTANT_P (src))
2586 else if (BINARY_P (src) && CONSTANT_P (XEXP (src, 1)))
2588 else if (GET_CODE (src) == ASHIFT || GET_CODE (src) == ASHIFTRT
2589 || GET_CODE (src) == LSHIFTRT)
2592 if (ngood < 2 && nshift < 2)
2596 /* Exit early if one of the insns involved can't be used for
2598 if (cant_combine_insn_p (i3)
2599 || cant_combine_insn_p (i2)
2600 || (i1 && cant_combine_insn_p (i1))
2601 || (i0 && cant_combine_insn_p (i0))
2602 || likely_spilled_retval_p (i3))
2606 undobuf.other_insn = 0;
2608 /* Reset the hard register usage information. */
2609 CLEAR_HARD_REG_SET (newpat_used_regs);
2611 if (dump_file && (dump_flags & TDF_DETAILS))
2614 fprintf (dump_file, "\nTrying %d, %d, %d -> %d:\n",
2615 INSN_UID (i0), INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2617 fprintf (dump_file, "\nTrying %d, %d -> %d:\n",
2618 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2620 fprintf (dump_file, "\nTrying %d -> %d:\n",
2621 INSN_UID (i2), INSN_UID (i3));
2624 /* If multiple insns feed into one of I2 or I3, they can be in any
2625 order. To simplify the code below, reorder them in sequence. */
2626 if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i2))
2627 temp = i2, i2 = i0, i0 = temp;
2628 if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i1))
2629 temp = i1, i1 = i0, i0 = temp;
2630 if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2))
2631 temp = i1, i1 = i2, i2 = temp;
2633 added_links_insn = 0;
2635 /* First check for one important special case that the code below will
2636 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2637 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2638 we may be able to replace that destination with the destination of I3.
2639 This occurs in the common code where we compute both a quotient and
2640 remainder into a structure, in which case we want to do the computation
2641 directly into the structure to avoid register-register copies.
2643 Note that this case handles both multiple sets in I2 and also cases
2644 where I2 has a number of CLOBBERs inside the PARALLEL.
2646 We make very conservative checks below and only try to handle the
2647 most common cases of this. For example, we only handle the case
2648 where I2 and I3 are adjacent to avoid making difficult register
2651 if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
2652 && REG_P (SET_SRC (PATTERN (i3)))
2653 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
2654 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
2655 && GET_CODE (PATTERN (i2)) == PARALLEL
2656 && ! side_effects_p (SET_DEST (PATTERN (i3)))
2657 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2658 below would need to check what is inside (and reg_overlap_mentioned_p
2659 doesn't support those codes anyway). Don't allow those destinations;
2660 the resulting insn isn't likely to be recognized anyway. */
2661 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
2662 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
2663 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
2664 SET_DEST (PATTERN (i3)))
2665 && next_active_insn (i2) == i3)
2667 rtx p2 = PATTERN (i2);
2669 /* Make sure that the destination of I3,
2670 which we are going to substitute into one output of I2,
2671 is not used within another output of I2. We must avoid making this:
2672 (parallel [(set (mem (reg 69)) ...)
2673 (set (reg 69) ...)])
2674 which is not well-defined as to order of actions.
2675 (Besides, reload can't handle output reloads for this.)
2677 The problem can also happen if the dest of I3 is a memory ref,
2678 if another dest in I2 is an indirect memory ref. */
2679 for (i = 0; i < XVECLEN (p2, 0); i++)
2680 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2681 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2682 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
2683 SET_DEST (XVECEXP (p2, 0, i))))
2686 if (i == XVECLEN (p2, 0))
2687 for (i = 0; i < XVECLEN (p2, 0); i++)
2688 if (GET_CODE (XVECEXP (p2, 0, i)) == SET
2689 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
2694 subst_low_luid = DF_INSN_LUID (i2);
2696 added_sets_2 = added_sets_1 = added_sets_0 = 0;
2697 i2src = SET_SRC (XVECEXP (p2, 0, i));
2698 i2dest = SET_DEST (XVECEXP (p2, 0, i));
2699 i2dest_killed = dead_or_set_p (i2, i2dest);
2701 /* Replace the dest in I2 with our dest and make the resulting
2702 insn the new pattern for I3. Then skip to where we validate
2703 the pattern. Everything was set up above. */
2704 SUBST (SET_DEST (XVECEXP (p2, 0, i)), SET_DEST (PATTERN (i3)));
2706 i3_subst_into_i2 = 1;
2707 goto validate_replacement;
2711 /* If I2 is setting a pseudo to a constant and I3 is setting some
2712 sub-part of it to another constant, merge them by making a new
2715 && (temp = single_set (i2)) != 0
2716 && (CONST_INT_P (SET_SRC (temp))
2717 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
2718 && GET_CODE (PATTERN (i3)) == SET
2719 && (CONST_INT_P (SET_SRC (PATTERN (i3)))
2720 || GET_CODE (SET_SRC (PATTERN (i3))) == CONST_DOUBLE)
2721 && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
2723 rtx dest = SET_DEST (PATTERN (i3));
2727 if (GET_CODE (dest) == ZERO_EXTRACT)
2729 if (CONST_INT_P (XEXP (dest, 1))
2730 && CONST_INT_P (XEXP (dest, 2)))
2732 width = INTVAL (XEXP (dest, 1));
2733 offset = INTVAL (XEXP (dest, 2));
2734 dest = XEXP (dest, 0);
2735 if (BITS_BIG_ENDIAN)
2736 offset = GET_MODE_BITSIZE (GET_MODE (dest)) - width - offset;
2741 if (GET_CODE (dest) == STRICT_LOW_PART)
2742 dest = XEXP (dest, 0);
2743 width = GET_MODE_BITSIZE (GET_MODE (dest));
2749 /* If this is the low part, we're done. */
2750 if (subreg_lowpart_p (dest))
2752 /* Handle the case where inner is twice the size of outer. */
2753 else if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2754 == 2 * GET_MODE_BITSIZE (GET_MODE (dest)))
2755 offset += GET_MODE_BITSIZE (GET_MODE (dest));
2756 /* Otherwise give up for now. */
2762 && (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2763 <= HOST_BITS_PER_DOUBLE_INT))
2766 rtx inner = SET_SRC (PATTERN (i3));
2767 rtx outer = SET_SRC (temp);
2769 o = rtx_to_double_int (outer);
2770 i = rtx_to_double_int (inner);
2772 m = double_int_mask (width);
2773 i = double_int_and (i, m);
2774 m = double_int_lshift (m, offset, HOST_BITS_PER_DOUBLE_INT, false);
2775 i = double_int_lshift (i, offset, HOST_BITS_PER_DOUBLE_INT, false);
2776 o = double_int_ior (double_int_and_not (o, m), i);
2780 subst_low_luid = DF_INSN_LUID (i2);
2781 added_sets_2 = added_sets_1 = added_sets_0 = 0;
2782 i2dest = SET_DEST (temp);
2783 i2dest_killed = dead_or_set_p (i2, i2dest);
2785 /* Replace the source in I2 with the new constant and make the
2786 resulting insn the new pattern for I3. Then skip to where we
2787 validate the pattern. Everything was set up above. */
2788 SUBST (SET_SRC (temp),
2789 immed_double_int_const (o, GET_MODE (SET_DEST (temp))));
2791 newpat = PATTERN (i2);
2793 /* The dest of I3 has been replaced with the dest of I2. */
2794 changed_i3_dest = 1;
2795 goto validate_replacement;
2800 /* If we have no I1 and I2 looks like:
2801 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2803 make up a dummy I1 that is
2806 (set (reg:CC X) (compare:CC Y (const_int 0)))
2808 (We can ignore any trailing CLOBBERs.)
2810 This undoes a previous combination and allows us to match a branch-and-
2813 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2814 && XVECLEN (PATTERN (i2), 0) >= 2
2815 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2816 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2818 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2819 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2820 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2821 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2822 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2823 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2825 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2826 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2831 /* We make I1 with the same INSN_UID as I2. This gives it
2832 the same DF_INSN_LUID for value tracking. Our fake I1 will
2833 never appear in the insn stream so giving it the same INSN_UID
2834 as I2 will not cause a problem. */
2836 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
2837 BLOCK_FOR_INSN (i2), XVECEXP (PATTERN (i2), 0, 1),
2838 INSN_LOCATOR (i2), -1, NULL_RTX);
2840 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2841 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2842 SET_DEST (PATTERN (i1)));
2847 /* Verify that I2 and I1 are valid for combining. */
2848 if (! can_combine_p (i2, i3, i0, i1, NULL_RTX, NULL_RTX, &i2dest, &i2src)
2849 || (i1 && ! can_combine_p (i1, i3, i0, NULL_RTX, i2, NULL_RTX,
2851 || (i0 && ! can_combine_p (i0, i3, NULL_RTX, NULL_RTX, i1, i2,
2858 /* Record whether I2DEST is used in I2SRC and similarly for the other
2859 cases. Knowing this will help in register status updating below. */
2860 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2861 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2862 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2863 i0dest_in_i0src = i0 && reg_overlap_mentioned_p (i0dest, i0src);
2864 i1dest_in_i0src = i0 && reg_overlap_mentioned_p (i1dest, i0src);
2865 i2dest_in_i0src = i0 && reg_overlap_mentioned_p (i2dest, i0src);
2866 i2dest_killed = dead_or_set_p (i2, i2dest);
2867 i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2868 i0dest_killed = i0 && dead_or_set_p (i0, i0dest);
2870 /* For the earlier insns, determine which of the subsequent ones they
2872 i1_feeds_i2_n = i1 && insn_a_feeds_b (i1, i2);
2873 i0_feeds_i1_n = i0 && insn_a_feeds_b (i0, i1);
2874 i0_feeds_i2_n = (i0 && (!i0_feeds_i1_n ? insn_a_feeds_b (i0, i2)
2875 : (!reg_overlap_mentioned_p (i1dest, i0dest)
2876 && reg_overlap_mentioned_p (i0dest, i2src))));
2878 /* Ensure that I3's pattern can be the destination of combines. */
2879 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest, i0dest,
2880 i1 && i2dest_in_i1src && !i1_feeds_i2_n,
2881 i0 && ((i2dest_in_i0src && !i0_feeds_i2_n)
2882 || (i1dest_in_i0src && !i0_feeds_i1_n)),
2889 /* See if any of the insns is a MULT operation. Unless one is, we will
2890 reject a combination that is, since it must be slower. Be conservative
2892 if (GET_CODE (i2src) == MULT
2893 || (i1 != 0 && GET_CODE (i1src) == MULT)
2894 || (i0 != 0 && GET_CODE (i0src) == MULT)
2895 || (GET_CODE (PATTERN (i3)) == SET
2896 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2899 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2900 We used to do this EXCEPT in one case: I3 has a post-inc in an
2901 output operand. However, that exception can give rise to insns like
2903 which is a famous insn on the PDP-11 where the value of r3 used as the
2904 source was model-dependent. Avoid this sort of thing. */
2907 if (!(GET_CODE (PATTERN (i3)) == SET
2908 && REG_P (SET_SRC (PATTERN (i3)))
2909 && MEM_P (SET_DEST (PATTERN (i3)))
2910 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2911 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2912 /* It's not the exception. */
2915 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2916 if (REG_NOTE_KIND (link) == REG_INC
2917 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2919 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2926 /* See if the SETs in I1 or I2 need to be kept around in the merged
2927 instruction: whenever the value set there is still needed past I3.
2928 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2930 For the SET in I1, we have two cases: If I1 and I2 independently
2931 feed into I3, the set in I1 needs to be kept around if I1DEST dies
2932 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2933 in I1 needs to be kept around unless I1DEST dies or is set in either
2934 I2 or I3. The same consideration applies to I0. */
2936 added_sets_2 = !dead_or_set_p (i3, i2dest);
2939 added_sets_1 = !(dead_or_set_p (i3, i1dest)
2940 || (i1_feeds_i2_n && dead_or_set_p (i2, i1dest)));
2945 added_sets_0 = !(dead_or_set_p (i3, i0dest)
2946 || (i0_feeds_i2_n && dead_or_set_p (i2, i0dest))
2947 || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest)));
2951 /* We are about to copy insns for the case where they need to be kept
2952 around. Check that they can be copied in the merged instruction. */
2954 if (targetm.cannot_copy_insn_p
2955 && ((added_sets_2 && targetm.cannot_copy_insn_p (i2))
2956 || (i1 && added_sets_1 && targetm.cannot_copy_insn_p (i1))
2957 || (i0 && added_sets_0 && targetm.cannot_copy_insn_p (i0))))
2963 /* If the set in I2 needs to be kept around, we must make a copy of
2964 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2965 PATTERN (I2), we are only substituting for the original I1DEST, not into
2966 an already-substituted copy. This also prevents making self-referential
2967 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2972 if (GET_CODE (PATTERN (i2)) == PARALLEL)
2973 i2pat = gen_rtx_SET (VOIDmode, i2dest, copy_rtx (i2src));
2975 i2pat = copy_rtx (PATTERN (i2));
2980 if (GET_CODE (PATTERN (i1)) == PARALLEL)
2981 i1pat = gen_rtx_SET (VOIDmode, i1dest, copy_rtx (i1src));
2983 i1pat = copy_rtx (PATTERN (i1));
2988 if (GET_CODE (PATTERN (i0)) == PARALLEL)
2989 i0pat = gen_rtx_SET (VOIDmode, i0dest, copy_rtx (i0src));
2991 i0pat = copy_rtx (PATTERN (i0));
2996 /* Substitute in the latest insn for the regs set by the earlier ones. */
2998 maxreg = max_reg_num ();
3003 /* Many machines that don't use CC0 have insns that can both perform an
3004 arithmetic operation and set the condition code. These operations will
3005 be represented as a PARALLEL with the first element of the vector
3006 being a COMPARE of an arithmetic operation with the constant zero.
3007 The second element of the vector will set some pseudo to the result
3008 of the same arithmetic operation. If we simplify the COMPARE, we won't
3009 match such a pattern and so will generate an extra insn. Here we test
3010 for this case, where both the comparison and the operation result are
3011 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3012 I2SRC. Later we will make the PARALLEL that contains I2. */
3014 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
3015 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
3016 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
3017 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
3019 #ifdef SELECT_CC_MODE
3021 enum machine_mode compare_mode;
3024 newpat = PATTERN (i3);
3025 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
3029 #ifdef SELECT_CC_MODE
3030 /* See if a COMPARE with the operand we substituted in should be done
3031 with the mode that is currently being used. If not, do the same
3032 processing we do in `subst' for a SET; namely, if the destination
3033 is used only once, try to replace it with a register of the proper
3034 mode and also replace the COMPARE. */
3035 if (undobuf.other_insn == 0
3036 && (cc_use = find_single_use (SET_DEST (newpat), i3,
3037 &undobuf.other_insn))
3038 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
3040 != GET_MODE (SET_DEST (newpat))))
3042 if (can_change_dest_mode (SET_DEST (newpat), added_sets_2,
3045 unsigned int regno = REGNO (SET_DEST (newpat));
3048 if (regno < FIRST_PSEUDO_REGISTER)
3049 new_dest = gen_rtx_REG (compare_mode, regno);
3052 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
3053 new_dest = regno_reg_rtx[regno];
3056 SUBST (SET_DEST (newpat), new_dest);
3057 SUBST (XEXP (*cc_use, 0), new_dest);
3058 SUBST (SET_SRC (newpat),
3059 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
3062 undobuf.other_insn = 0;
3069 /* It is possible that the source of I2 or I1 may be performing
3070 an unneeded operation, such as a ZERO_EXTEND of something
3071 that is known to have the high part zero. Handle that case
3072 by letting subst look at the innermost one of them.
3074 Another way to do this would be to have a function that tries
3075 to simplify a single insn instead of merging two or more
3076 insns. We don't do this because of the potential of infinite
3077 loops and because of the potential extra memory required.
3078 However, doing it the way we are is a bit of a kludge and
3079 doesn't catch all cases.
3081 But only do this if -fexpensive-optimizations since it slows
3082 things down and doesn't usually win.
3084 This is not done in the COMPARE case above because the
3085 unmodified I2PAT is used in the PARALLEL and so a pattern
3086 with a modified I2SRC would not match. */
3088 if (flag_expensive_optimizations)
3090 /* Pass pc_rtx so no substitutions are done, just
3094 subst_low_luid = DF_INSN_LUID (i1);
3095 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
3099 subst_low_luid = DF_INSN_LUID (i2);
3100 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
3104 n_occurrences = 0; /* `subst' counts here */
3105 subst_low_luid = DF_INSN_LUID (i2);
3107 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3108 copy of I2SRC each time we substitute it, in order to avoid creating
3109 self-referential RTL when we will be substituting I1SRC for I1DEST
3110 later. Likewise if I0 feeds into I2, either directly or indirectly
3111 through I1, and I0DEST is in I0SRC. */
3112 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
3113 (i1_feeds_i2_n && i1dest_in_i1src)
3114 || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
3115 && i0dest_in_i0src));
3118 /* Record whether I2's body now appears within I3's body. */
3119 i2_is_used = n_occurrences;
3122 /* If we already got a failure, don't try to do more. Otherwise, try to
3123 substitute I1 if we have it. */
3125 if (i1 && GET_CODE (newpat) != CLOBBER)
3127 /* Check that an autoincrement side-effect on I1 has not been lost.
3128 This happens if I1DEST is mentioned in I2 and dies there, and
3129 has disappeared from the new pattern. */
3130 if ((FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3132 && dead_or_set_p (i2, i1dest)
3133 && !reg_overlap_mentioned_p (i1dest, newpat))
3134 /* Before we can do this substitution, we must redo the test done
3135 above (see detailed comments there) that ensures I1DEST isn't
3136 mentioned in any SETs in NEWPAT that are field assignments. */
3137 || !combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX, NULL_RTX,
3145 subst_low_luid = DF_INSN_LUID (i1);
3147 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3148 copy of I1SRC each time we substitute it, in order to avoid creating
3149 self-referential RTL when we will be substituting I0SRC for I0DEST
3151 newpat = subst (newpat, i1dest, i1src, 0,
3152 i0_feeds_i1_n && i0dest_in_i0src);
3155 /* Record whether I1's body now appears within I3's body. */
3156 i1_is_used = n_occurrences;
3159 /* Likewise for I0 if we have it. */
3161 if (i0 && GET_CODE (newpat) != CLOBBER)
3163 if ((FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3164 && ((i0_feeds_i2_n && dead_or_set_p (i2, i0dest))
3165 || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest)))
3166 && !reg_overlap_mentioned_p (i0dest, newpat))
3167 || !combinable_i3pat (NULL_RTX, &newpat, i0dest, NULL_RTX, NULL_RTX,
3174 /* If the following substitution will modify I1SRC, make a copy of it
3175 for the case where it is substituted for I1DEST in I2PAT later. */
3176 if (i0_feeds_i1_n && added_sets_2 && i1_feeds_i2_n)
3177 i1src_copy = copy_rtx (i1src);
3180 subst_low_luid = DF_INSN_LUID (i0);
3181 newpat = subst (newpat, i0dest, i0src, 0, 0);
3185 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3186 to count all the ways that I2SRC and I1SRC can be used. */
3187 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
3188 && i2_is_used + added_sets_2 > 1)
3189 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3190 && (i1_is_used + added_sets_1 + (added_sets_2 && i1_feeds_i2_n)
3192 || (i0 != 0 && FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3193 && (n_occurrences + added_sets_0
3194 + (added_sets_1 && i0_feeds_i1_n)
3195 + (added_sets_2 && i0_feeds_i2_n)
3197 /* Fail if we tried to make a new register. */
3198 || max_reg_num () != maxreg
3199 /* Fail if we couldn't do something and have a CLOBBER. */
3200 || GET_CODE (newpat) == CLOBBER
3201 /* Fail if this new pattern is a MULT and we didn't have one before
3202 at the outer level. */
3203 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
3210 /* If the actions of the earlier insns must be kept
3211 in addition to substituting them into the latest one,
3212 we must make a new PARALLEL for the latest insn
3213 to hold additional the SETs. */
3215 if (added_sets_0 || added_sets_1 || added_sets_2)
3217 int extra_sets = added_sets_0 + added_sets_1 + added_sets_2;
3220 if (GET_CODE (newpat) == PARALLEL)
3222 rtvec old = XVEC (newpat, 0);
3223 total_sets = XVECLEN (newpat, 0) + extra_sets;
3224 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3225 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
3226 sizeof (old->elem[0]) * old->num_elem);
3231 total_sets = 1 + extra_sets;
3232 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3233 XVECEXP (newpat, 0, 0) = old;
3237 XVECEXP (newpat, 0, --total_sets) = i0pat;
3243 t = subst (t, i0dest, i0src, 0, 0);
3245 XVECEXP (newpat, 0, --total_sets) = t;
3251 t = subst (t, i1dest, i1src_copy ? i1src_copy : i1src, 0,
3252 i0_feeds_i1_n && i0dest_in_i0src);
3253 if ((i0_feeds_i1_n && i1_feeds_i2_n) || i0_feeds_i2_n)
3254 t = subst (t, i0dest, i0src, 0, 0);
3256 XVECEXP (newpat, 0, --total_sets) = t;
3260 validate_replacement:
3262 /* Note which hard regs this insn has as inputs. */
3263 mark_used_regs_combine (newpat);
3265 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3266 consider splitting this pattern, we might need these clobbers. */
3267 if (i1 && GET_CODE (newpat) == PARALLEL
3268 && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
3270 int len = XVECLEN (newpat, 0);
3272 newpat_vec_with_clobbers = rtvec_alloc (len);
3273 for (i = 0; i < len; i++)
3274 RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
3277 /* Is the result of combination a valid instruction? */
3278 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3280 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
3281 the second SET's destination is a register that is unused and isn't
3282 marked as an instruction that might trap in an EH region. In that case,
3283 we just need the first SET. This can occur when simplifying a divmod
3284 insn. We *must* test for this case here because the code below that
3285 splits two independent SETs doesn't handle this case correctly when it
3286 updates the register status.
3288 It's pointless doing this if we originally had two sets, one from
3289 i3, and one from i2. Combining then splitting the parallel results
3290 in the original i2 again plus an invalid insn (which we delete).
3291 The net effect is only to move instructions around, which makes
3292 debug info less accurate.
3294 Also check the case where the first SET's destination is unused.
3295 That would not cause incorrect code, but does cause an unneeded
3298 if (insn_code_number < 0
3299 && !(added_sets_2 && i1 == 0)
3300 && GET_CODE (newpat) == PARALLEL
3301 && XVECLEN (newpat, 0) == 2
3302 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3303 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3304 && asm_noperands (newpat) < 0)
3306 rtx set0 = XVECEXP (newpat, 0, 0);
3307 rtx set1 = XVECEXP (newpat, 0, 1);
3309 if (((REG_P (SET_DEST (set1))
3310 && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
3311 || (GET_CODE (SET_DEST (set1)) == SUBREG
3312 && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
3313 && insn_nothrow_p (i3)
3314 && !side_effects_p (SET_SRC (set1)))
3317 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3320 else if (((REG_P (SET_DEST (set0))
3321 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
3322 || (GET_CODE (SET_DEST (set0)) == SUBREG
3323 && find_reg_note (i3, REG_UNUSED,
3324 SUBREG_REG (SET_DEST (set0)))))
3325 && insn_nothrow_p (i3)
3326 && !side_effects_p (SET_SRC (set0)))
3329 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3331 if (insn_code_number >= 0)
3332 changed_i3_dest = 1;
3336 /* If we were combining three insns and the result is a simple SET
3337 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3338 insns. There are two ways to do this. It can be split using a
3339 machine-specific method (like when you have an addition of a large
3340 constant) or by combine in the function find_split_point. */
3342 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
3343 && asm_noperands (newpat) < 0)
3345 rtx parallel, m_split, *split;
3347 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3348 use I2DEST as a scratch register will help. In the latter case,
3349 convert I2DEST to the mode of the source of NEWPAT if we can. */
3351 m_split = combine_split_insns (newpat, i3);
3353 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3354 inputs of NEWPAT. */
3356 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3357 possible to try that as a scratch reg. This would require adding
3358 more code to make it work though. */
3360 if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
3362 enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
3364 /* First try to split using the original register as a
3365 scratch register. */
3366 parallel = gen_rtx_PARALLEL (VOIDmode,
3367 gen_rtvec (2, newpat,
3368 gen_rtx_CLOBBER (VOIDmode,
3370 m_split = combine_split_insns (parallel, i3);
3372 /* If that didn't work, try changing the mode of I2DEST if
3375 && new_mode != GET_MODE (i2dest)
3376 && new_mode != VOIDmode
3377 && can_change_dest_mode (i2dest, added_sets_2, new_mode))
3379 enum machine_mode old_mode = GET_MODE (i2dest);
3382 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3383 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
3386 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
3387 ni2dest = regno_reg_rtx[REGNO (i2dest)];
3390 parallel = (gen_rtx_PARALLEL
3392 gen_rtvec (2, newpat,
3393 gen_rtx_CLOBBER (VOIDmode,
3395 m_split = combine_split_insns (parallel, i3);
3398 && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
3402 adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode);
3403 buf = undobuf.undos;
3404 undobuf.undos = buf->next;
3405 buf->next = undobuf.frees;
3406 undobuf.frees = buf;
3410 i2scratch = m_split != 0;
3413 /* If recog_for_combine has discarded clobbers, try to use them
3414 again for the split. */
3415 if (m_split == 0 && newpat_vec_with_clobbers)
3417 parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers);
3418 m_split = combine_split_insns (parallel, i3);
3421 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
3423 m_split = PATTERN (m_split);
3424 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
3425 if (insn_code_number >= 0)
3428 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
3429 && (next_real_insn (i2) == i3
3430 || ! use_crosses_set_p (PATTERN (m_split), DF_INSN_LUID (i2))))
3433 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
3434 newi2pat = PATTERN (m_split);
3436 i3set = single_set (NEXT_INSN (m_split));
3437 i2set = single_set (m_split);
3439 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3441 /* If I2 or I3 has multiple SETs, we won't know how to track
3442 register status, so don't use these insns. If I2's destination
3443 is used between I2 and I3, we also can't use these insns. */
3445 if (i2_code_number >= 0 && i2set && i3set
3446 && (next_real_insn (i2) == i3
3447 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
3448 insn_code_number = recog_for_combine (&newi3pat, i3,
3450 if (insn_code_number >= 0)
3453 /* It is possible that both insns now set the destination of I3.
3454 If so, we must show an extra use of it. */
3456 if (insn_code_number >= 0)
3458 rtx new_i3_dest = SET_DEST (i3set);
3459 rtx new_i2_dest = SET_DEST (i2set);
3461 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
3462 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
3463 || GET_CODE (new_i3_dest) == SUBREG)
3464 new_i3_dest = XEXP (new_i3_dest, 0);
3466 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
3467 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
3468 || GET_CODE (new_i2_dest) == SUBREG)
3469 new_i2_dest = XEXP (new_i2_dest, 0);
3471 if (REG_P (new_i3_dest)
3472 && REG_P (new_i2_dest)
3473 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
3474 INC_REG_N_SETS (REGNO (new_i2_dest), 1);
3478 /* If we can split it and use I2DEST, go ahead and see if that
3479 helps things be recognized. Verify that none of the registers
3480 are set between I2 and I3. */
3481 if (insn_code_number < 0
3482 && (split = find_split_point (&newpat, i3, false)) != 0
3486 /* We need I2DEST in the proper mode. If it is a hard register
3487 or the only use of a pseudo, we can change its mode.
3488 Make sure we don't change a hard register to have a mode that
3489 isn't valid for it, or change the number of registers. */
3490 && (GET_MODE (*split) == GET_MODE (i2dest)
3491 || GET_MODE (*split) == VOIDmode
3492 || can_change_dest_mode (i2dest, added_sets_2,
3494 && (next_real_insn (i2) == i3
3495 || ! use_crosses_set_p (*split, DF_INSN_LUID (i2)))
3496 /* We can't overwrite I2DEST if its value is still used by
3498 && ! reg_referenced_p (i2dest, newpat))
3500 rtx newdest = i2dest;
3501 enum rtx_code split_code = GET_CODE (*split);
3502 enum machine_mode split_mode = GET_MODE (*split);
3503 bool subst_done = false;
3504 newi2pat = NULL_RTX;
3508 /* *SPLIT may be part of I2SRC, so make sure we have the
3509 original expression around for later debug processing.
3510 We should not need I2SRC any more in other cases. */
3511 if (MAY_HAVE_DEBUG_INSNS)
3512 i2src = copy_rtx (i2src);
3516 /* Get NEWDEST as a register in the proper mode. We have already
3517 validated that we can do this. */
3518 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
3520 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3521 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
3524 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
3525 newdest = regno_reg_rtx[REGNO (i2dest)];
3529 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3530 an ASHIFT. This can occur if it was inside a PLUS and hence
3531 appeared to be a memory address. This is a kludge. */
3532 if (split_code == MULT
3533 && CONST_INT_P (XEXP (*split, 1))
3534 && INTVAL (XEXP (*split, 1)) > 0
3535 && (i = exact_log2 (UINTVAL (XEXP (*split, 1)))) >= 0)
3537 SUBST (*split, gen_rtx_ASHIFT (split_mode,
3538 XEXP (*split, 0), GEN_INT (i)));
3539 /* Update split_code because we may not have a multiply
3541 split_code = GET_CODE (*split);
3544 #ifdef INSN_SCHEDULING
3545 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3546 be written as a ZERO_EXTEND. */
3547 if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
3549 #ifdef LOAD_EXTEND_OP
3550 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3551 what it really is. */
3552 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
3554 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
3555 SUBREG_REG (*split)));
3558 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
3559 SUBREG_REG (*split)));
3563 /* Attempt to split binary operators using arithmetic identities. */
3564 if (BINARY_P (SET_SRC (newpat))
3565 && split_mode == GET_MODE (SET_SRC (newpat))
3566 && ! side_effects_p (SET_SRC (newpat)))
3568 rtx setsrc = SET_SRC (newpat);
3569 enum machine_mode mode = GET_MODE (setsrc);
3570 enum rtx_code code = GET_CODE (setsrc);
3571 rtx src_op0 = XEXP (setsrc, 0);
3572 rtx src_op1 = XEXP (setsrc, 1);
3574 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3575 if (rtx_equal_p (src_op0, src_op1))
3577 newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
3578 SUBST (XEXP (setsrc, 0), newdest);
3579 SUBST (XEXP (setsrc, 1), newdest);
3582 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3583 else if ((code == PLUS || code == MULT)
3584 && GET_CODE (src_op0) == code
3585 && GET_CODE (XEXP (src_op0, 0)) == code
3586 && (INTEGRAL_MODE_P (mode)
3587 || (FLOAT_MODE_P (mode)
3588 && flag_unsafe_math_optimizations)))
3590 rtx p = XEXP (XEXP (src_op0, 0), 0);
3591 rtx q = XEXP (XEXP (src_op0, 0), 1);
3592 rtx r = XEXP (src_op0, 1);
3595 /* Split both "((X op Y) op X) op Y" and
3596 "((X op Y) op Y) op X" as "T op T" where T is
3598 if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
3599 || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
3601 newi2pat = gen_rtx_SET (VOIDmode, newdest,
3603 SUBST (XEXP (setsrc, 0), newdest);
3604 SUBST (XEXP (setsrc, 1), newdest);
3607 /* Split "((X op X) op Y) op Y)" as "T op T" where
3609 else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
3611 rtx tmp = simplify_gen_binary (code, mode, p, r);
3612 newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
3613 SUBST (XEXP (setsrc, 0), newdest);
3614 SUBST (XEXP (setsrc, 1), newdest);
3622 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
3623 SUBST (*split, newdest);
3626 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3628 /* recog_for_combine might have added CLOBBERs to newi2pat.
3629 Make sure NEWPAT does not depend on the clobbered regs. */
3630 if (GET_CODE (newi2pat) == PARALLEL)
3631 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3632 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3634 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3635 if (reg_overlap_mentioned_p (reg, newpat))
3642 /* If the split point was a MULT and we didn't have one before,
3643 don't use one now. */
3644 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
3645 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3649 /* Check for a case where we loaded from memory in a narrow mode and
3650 then sign extended it, but we need both registers. In that case,
3651 we have a PARALLEL with both loads from the same memory location.
3652 We can split this into a load from memory followed by a register-register
3653 copy. This saves at least one insn, more if register allocation can
3656 We cannot do this if the destination of the first assignment is a
3657 condition code register or cc0. We eliminate this case by making sure
3658 the SET_DEST and SET_SRC have the same mode.
3660 We cannot do this if the destination of the second assignment is
3661 a register that we have already assumed is zero-extended. Similarly
3662 for a SUBREG of such a register. */
3664 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3665 && GET_CODE (newpat) == PARALLEL
3666 && XVECLEN (newpat, 0) == 2
3667 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3668 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
3669 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
3670 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
3671 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3672 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3673 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
3674 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3676 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3677 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3678 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
3680 && VEC_index (reg_stat_type, reg_stat,
3681 REGNO (temp))->nonzero_bits != 0
3682 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3683 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3684 && (VEC_index (reg_stat_type, reg_stat,
3685 REGNO (temp))->nonzero_bits
3686 != GET_MODE_MASK (word_mode))))
3687 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
3688 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
3690 && VEC_index (reg_stat_type, reg_stat,
3691 REGNO (temp))->nonzero_bits != 0
3692 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3693 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3694 && (VEC_index (reg_stat_type, reg_stat,
3695 REGNO (temp))->nonzero_bits
3696 != GET_MODE_MASK (word_mode)))))
3697 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3698 SET_SRC (XVECEXP (newpat, 0, 1)))
3699 && ! find_reg_note (i3, REG_UNUSED,
3700 SET_DEST (XVECEXP (newpat, 0, 0))))
3704 newi2pat = XVECEXP (newpat, 0, 0);
3705 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
3706 newpat = XVECEXP (newpat, 0, 1);
3707 SUBST (SET_SRC (newpat),
3708 gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
3709 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3711 if (i2_code_number >= 0)
3712 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3714 if (insn_code_number >= 0)
3718 /* Similarly, check for a case where we have a PARALLEL of two independent
3719 SETs but we started with three insns. In this case, we can do the sets
3720 as two separate insns. This case occurs when some SET allows two
3721 other insns to combine, but the destination of that SET is still live. */
3723 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3724 && GET_CODE (newpat) == PARALLEL
3725 && XVECLEN (newpat, 0) == 2
3726 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3727 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
3728 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
3729 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3730 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3731 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3732 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3733 XVECEXP (newpat, 0, 0))
3734 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
3735 XVECEXP (newpat, 0, 1))
3736 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
3737 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
3739 /* Normally, it doesn't matter which of the two is done first,
3740 but the one that references cc0 can't be the second, and
3741 one which uses any regs/memory set in between i2 and i3 can't
3743 if (!use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3746 && !reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0))
3750 newi2pat = XVECEXP (newpat, 0, 1);
3751 newpat = XVECEXP (newpat, 0, 0);
3753 else if (!use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 0)),
3756 && !reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 1))
3760 newi2pat = XVECEXP (newpat, 0, 0);
3761 newpat = XVECEXP (newpat, 0, 1);
3769 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3771 if (i2_code_number >= 0)
3773 /* recog_for_combine might have added CLOBBERs to newi2pat.
3774 Make sure NEWPAT does not depend on the clobbered regs. */
3775 if (GET_CODE (newi2pat) == PARALLEL)
3777 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3778 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3780 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3781 if (reg_overlap_mentioned_p (reg, newpat))
3789 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3793 /* If it still isn't recognized, fail and change things back the way they
3795 if ((insn_code_number < 0
3796 /* Is the result a reasonable ASM_OPERANDS? */
3797 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
3803 /* If we had to change another insn, make sure it is valid also. */
3804 if (undobuf.other_insn)
3806 CLEAR_HARD_REG_SET (newpat_used_regs);
3808 other_pat = PATTERN (undobuf.other_insn);
3809 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
3812 if (other_code_number < 0 && ! check_asm_operands (other_pat))
3820 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3821 they are adjacent to each other or not. */
3823 rtx p = prev_nonnote_insn (i3);
3824 if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
3825 && sets_cc0_p (newi2pat))
3833 /* Only allow this combination if insn_rtx_costs reports that the
3834 replacement instructions are cheaper than the originals. */
3835 if (!combine_validate_cost (i0, i1, i2, i3, newpat, newi2pat, other_pat))
3841 if (MAY_HAVE_DEBUG_INSNS)
3845 for (undo = undobuf.undos; undo; undo = undo->next)
3846 if (undo->kind == UNDO_MODE)
3848 rtx reg = *undo->where.r;
3849 enum machine_mode new_mode = GET_MODE (reg);
3850 enum machine_mode old_mode = undo->old_contents.m;
3852 /* Temporarily revert mode back. */
3853 adjust_reg_mode (reg, old_mode);
3855 if (reg == i2dest && i2scratch)
3857 /* If we used i2dest as a scratch register with a
3858 different mode, substitute it for the original
3859 i2src while its original mode is temporarily
3860 restored, and then clear i2scratch so that we don't
3861 do it again later. */
3862 propagate_for_debug (i2, i3, reg, i2src);
3864 /* Put back the new mode. */
3865 adjust_reg_mode (reg, new_mode);
3869 rtx tempreg = gen_raw_REG (old_mode, REGNO (reg));
3880 last = undobuf.other_insn;
3884 /* We're dealing with a reg that changed mode but not
3885 meaning, so we want to turn it into a subreg for
3886 the new mode. However, because of REG sharing and
3887 because its mode had already changed, we have to do
3888 it in two steps. First, replace any debug uses of
3889 reg, with its original mode temporarily restored,
3890 with this copy we have created; then, replace the
3891 copy with the SUBREG of the original shared reg,
3892 once again changed to the new mode. */
3893 propagate_for_debug (first, last, reg, tempreg);
3894 adjust_reg_mode (reg, new_mode);
3895 propagate_for_debug (first, last, tempreg,
3896 lowpart_subreg (old_mode, reg, new_mode));
3901 /* If we will be able to accept this, we have made a
3902 change to the destination of I3. This requires us to
3903 do a few adjustments. */
3905 if (changed_i3_dest)
3907 PATTERN (i3) = newpat;
3908 adjust_for_new_dest (i3);
3911 /* We now know that we can do this combination. Merge the insns and
3912 update the status of registers and LOG_LINKS. */
3914 if (undobuf.other_insn)
3918 PATTERN (undobuf.other_insn) = other_pat;
3920 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
3921 are still valid. Then add any non-duplicate notes added by
3922 recog_for_combine. */
3923 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
3925 next = XEXP (note, 1);
3927 if (REG_NOTE_KIND (note) == REG_UNUSED
3928 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
3929 remove_note (undobuf.other_insn, note);
3932 distribute_notes (new_other_notes, undobuf.other_insn,
3933 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX,
3943 /* I3 now uses what used to be its destination and which is now
3944 I2's destination. This requires us to do a few adjustments. */
3945 PATTERN (i3) = newpat;
3946 adjust_for_new_dest (i3);
3948 /* We need a LOG_LINK from I3 to I2. But we used to have one,
3951 However, some later insn might be using I2's dest and have
3952 a LOG_LINK pointing at I3. We must remove this link.
3953 The simplest way to remove the link is to point it at I1,
3954 which we know will be a NOTE. */
3956 /* newi2pat is usually a SET here; however, recog_for_combine might
3957 have added some clobbers. */
3958 if (GET_CODE (newi2pat) == PARALLEL)
3959 ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
3961 ni2dest = SET_DEST (newi2pat);
3963 for (insn = NEXT_INSN (i3);
3964 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3965 || insn != BB_HEAD (this_basic_block->next_bb));
3966 insn = NEXT_INSN (insn))
3968 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
3970 for (link = LOG_LINKS (insn); link;
3971 link = XEXP (link, 1))
3972 if (XEXP (link, 0) == i3)
3973 XEXP (link, 0) = i1;
3981 rtx i3notes, i2notes, i1notes = 0, i0notes = 0;
3982 rtx i3links, i2links, i1links = 0, i0links = 0;
3986 /* Compute which registers we expect to eliminate. newi2pat may be setting
3987 either i3dest or i2dest, so we must check it. Also, i1dest may be the
3988 same as i3dest, in which case newi2pat may be setting i1dest. */
3989 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
3990 || i2dest_in_i2src || i2dest_in_i1src || i2dest_in_i0src
3993 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src || i1dest_in_i0src
3994 || (newi2pat && reg_set_p (i1dest, newi2pat))
3997 rtx elim_i0 = (i0 == 0 || i0dest_in_i0src
3998 || (newi2pat && reg_set_p (i0dest, newi2pat))
4002 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4004 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
4005 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
4007 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
4009 i0notes = REG_NOTES (i0), i0links = LOG_LINKS (i0);
4011 /* Ensure that we do not have something that should not be shared but
4012 occurs multiple times in the new insns. Check this by first
4013 resetting all the `used' flags and then copying anything is shared. */
4015 reset_used_flags (i3notes);
4016 reset_used_flags (i2notes);
4017 reset_used_flags (i1notes);
4018 reset_used_flags (i0notes);
4019 reset_used_flags (newpat);
4020 reset_used_flags (newi2pat);
4021 if (undobuf.other_insn)
4022 reset_used_flags (PATTERN (undobuf.other_insn));
4024 i3notes = copy_rtx_if_shared (i3notes);
4025 i2notes = copy_rtx_if_shared (i2notes);
4026 i1notes = copy_rtx_if_shared (i1notes);
4027 i0notes = copy_rtx_if_shared (i0notes);
4028 newpat = copy_rtx_if_shared (newpat);
4029 newi2pat = copy_rtx_if_shared (newi2pat);
4030 if (undobuf.other_insn)
4031 reset_used_flags (PATTERN (undobuf.other_insn));
4033 INSN_CODE (i3) = insn_code_number;
4034 PATTERN (i3) = newpat;
4036 if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
4038 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
4040 reset_used_flags (call_usage);
4041 call_usage = copy_rtx (call_usage);
4045 /* I2SRC must still be meaningful at this point. Some splitting
4046 operations can invalidate I2SRC, but those operations do not
4049 replace_rtx (call_usage, i2dest, i2src);
4053 replace_rtx (call_usage, i1dest, i1src);
4055 replace_rtx (call_usage, i0dest, i0src);
4057 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
4060 if (undobuf.other_insn)
4061 INSN_CODE (undobuf.other_insn) = other_code_number;
4063 /* We had one special case above where I2 had more than one set and
4064 we replaced a destination of one of those sets with the destination
4065 of I3. In that case, we have to update LOG_LINKS of insns later
4066 in this basic block. Note that this (expensive) case is rare.
4068 Also, in this case, we must pretend that all REG_NOTEs for I2
4069 actually came from I3, so that REG_UNUSED notes from I2 will be
4070 properly handled. */
4072 if (i3_subst_into_i2)
4074 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
4075 if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
4076 || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
4077 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
4078 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
4079 && ! find_reg_note (i2, REG_UNUSED,
4080 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
4081 for (temp = NEXT_INSN (i2);
4082 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
4083 || BB_HEAD (this_basic_block) != temp);
4084 temp = NEXT_INSN (temp))
4085 if (temp != i3 && INSN_P (temp))
4086 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
4087 if (XEXP (link, 0) == i2)
4088 XEXP (link, 0) = i3;
4093 while (XEXP (link, 1))
4094 link = XEXP (link, 1);
4095 XEXP (link, 1) = i2notes;
4109 if (MAY_HAVE_DEBUG_INSNS && i2scratch)
4110 propagate_for_debug (i2, i3, i2dest, i2src);
4111 INSN_CODE (i2) = i2_code_number;
4112 PATTERN (i2) = newi2pat;
4116 if (MAY_HAVE_DEBUG_INSNS && i2src)
4117 propagate_for_debug (i2, i3, i2dest, i2src);
4118 SET_INSN_DELETED (i2);
4125 if (MAY_HAVE_DEBUG_INSNS)
4126 propagate_for_debug (i1, i3, i1dest, i1src);
4127 SET_INSN_DELETED (i1);
4134 if (MAY_HAVE_DEBUG_INSNS)
4135 propagate_for_debug (i0, i3, i0dest, i0src);
4136 SET_INSN_DELETED (i0);
4139 /* Get death notes for everything that is now used in either I3 or
4140 I2 and used to die in a previous insn. If we built two new
4141 patterns, move from I1 to I2 then I2 to I3 so that we get the
4142 proper movement on registers that I2 modifies. */
4145 from_luid = DF_INSN_LUID (i0);
4147 from_luid = DF_INSN_LUID (i1);
4149 from_luid = DF_INSN_LUID (i2);
4151 move_deaths (newi2pat, NULL_RTX, from_luid, i2, &midnotes);
4152 move_deaths (newpat, newi2pat, from_luid, i3, &midnotes);
4154 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4156 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
4157 elim_i2, elim_i1, elim_i0);
4159 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
4160 elim_i2, elim_i1, elim_i0);
4162 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
4163 elim_i2, elim_i1, elim_i0);
4165 distribute_notes (i0notes, i0, i3, newi2pat ? i2 : NULL_RTX,
4166 elim_i2, elim_i1, elim_i0);
4168 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4169 elim_i2, elim_i1, elim_i0);
4171 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4172 know these are REG_UNUSED and want them to go to the desired insn,
4173 so we always pass it as i3. */
4175 if (newi2pat && new_i2_notes)
4176 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX,
4180 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX,
4183 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4184 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4185 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4186 in that case, it might delete I2. Similarly for I2 and I1.
4187 Show an additional death due to the REG_DEAD note we make here. If
4188 we discard it in distribute_notes, we will decrement it again. */
4192 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
4193 distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
4195 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1, elim_i0);
4197 distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
4199 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4200 elim_i2, elim_i1, elim_i0);
4203 if (i2dest_in_i2src)
4205 rtx new_note = alloc_reg_note (REG_DEAD, i2dest, NULL_RTX);
4206 if (newi2pat && reg_set_p (i2dest, newi2pat))
4207 distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4208 NULL_RTX, NULL_RTX);
4210 distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4211 NULL_RTX, NULL_RTX, NULL_RTX);
4214 if (i1dest_in_i1src)
4216 rtx new_note = alloc_reg_note (REG_DEAD, i1dest, NULL_RTX);
4217 if (newi2pat && reg_set_p (i1dest, newi2pat))
4218 distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4219 NULL_RTX, NULL_RTX);
4221 distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4222 NULL_RTX, NULL_RTX, NULL_RTX);
4225 if (i0dest_in_i0src)
4227 rtx new_note = alloc_reg_note (REG_DEAD, i0dest, NULL_RTX);
4228 if (newi2pat && reg_set_p (i0dest, newi2pat))
4229 distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4230 NULL_RTX, NULL_RTX);
4232 distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4233 NULL_RTX, NULL_RTX, NULL_RTX);
4236 distribute_links (i3links);
4237 distribute_links (i2links);
4238 distribute_links (i1links);
4239 distribute_links (i0links);
4244 rtx i2_insn = 0, i2_val = 0, set;
4246 /* The insn that used to set this register doesn't exist, and
4247 this life of the register may not exist either. See if one of
4248 I3's links points to an insn that sets I2DEST. If it does,
4249 that is now the last known value for I2DEST. If we don't update
4250 this and I2 set the register to a value that depended on its old
4251 contents, we will get confused. If this insn is used, thing
4252 will be set correctly in combine_instructions. */
4254 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
4255 if ((set = single_set (XEXP (link, 0))) != 0
4256 && rtx_equal_p (i2dest, SET_DEST (set)))
4257 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
4259 record_value_for_reg (i2dest, i2_insn, i2_val);
4261 /* If the reg formerly set in I2 died only once and that was in I3,
4262 zero its use count so it won't make `reload' do any work. */
4264 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
4265 && ! i2dest_in_i2src)
4267 regno = REGNO (i2dest);
4268 INC_REG_N_SETS (regno, -1);
4272 if (i1 && REG_P (i1dest))
4275 rtx i1_insn = 0, i1_val = 0, set;
4277 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
4278 if ((set = single_set (XEXP (link, 0))) != 0
4279 && rtx_equal_p (i1dest, SET_DEST (set)))
4280 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
4282 record_value_for_reg (i1dest, i1_insn, i1_val);
4284 regno = REGNO (i1dest);
4285 if (! added_sets_1 && ! i1dest_in_i1src)
4286 INC_REG_N_SETS (regno, -1);
4289 if (i0 && REG_P (i0dest))
4292 rtx i0_insn = 0, i0_val = 0, set;
4294 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
4295 if ((set = single_set (XEXP (link, 0))) != 0
4296 && rtx_equal_p (i0dest, SET_DEST (set)))
4297 i0_insn = XEXP (link, 0), i0_val = SET_SRC (set);
4299 record_value_for_reg (i0dest, i0_insn, i0_val);
4301 regno = REGNO (i0dest);
4302 if (! added_sets_0 && ! i0dest_in_i0src)
4303 INC_REG_N_SETS (regno, -1);
4306 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4307 been made to this insn. The order of
4308 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
4309 can affect nonzero_bits of newpat */
4311 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
4312 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
4315 if (undobuf.other_insn != NULL_RTX)
4319 fprintf (dump_file, "modifying other_insn ");
4320 dump_insn_slim (dump_file, undobuf.other_insn);
4322 df_insn_rescan (undobuf.other_insn);
4325 if (i0 && !(NOTE_P(i0) && (NOTE_KIND (i0) == NOTE_INSN_DELETED)))
4329 fprintf (dump_file, "modifying insn i1 ");
4330 dump_insn_slim (dump_file, i0);
4332 df_insn_rescan (i0);
4335 if (i1 && !(NOTE_P(i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED)))
4339 fprintf (dump_file, "modifying insn i1 ");
4340 dump_insn_slim (dump_file, i1);
4342 df_insn_rescan (i1);
4345 if (i2 && !(NOTE_P(i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED)))
4349 fprintf (dump_file, "modifying insn i2 ");
4350 dump_insn_slim (dump_file, i2);
4352 df_insn_rescan (i2);
4355 if (i3 && !(NOTE_P(i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED)))
4359 fprintf (dump_file, "modifying insn i3 ");
4360 dump_insn_slim (dump_file, i3);
4362 df_insn_rescan (i3);
4365 /* Set new_direct_jump_p if a new return or simple jump instruction
4366 has been created. Adjust the CFG accordingly. */
4368 if (returnjump_p (i3) || any_uncondjump_p (i3))
4370 *new_direct_jump_p = 1;
4371 mark_jump_label (PATTERN (i3), i3, 0);
4372 update_cfg_for_uncondjump (i3);
4375 if (undobuf.other_insn != NULL_RTX
4376 && (returnjump_p (undobuf.other_insn)
4377 || any_uncondjump_p (undobuf.other_insn)))
4379 *new_direct_jump_p = 1;
4380 update_cfg_for_uncondjump (undobuf.other_insn);
4383 /* A noop might also need cleaning up of CFG, if it comes from the
4384 simplification of a jump. */
4385 if (GET_CODE (newpat) == SET
4386 && SET_SRC (newpat) == pc_rtx
4387 && SET_DEST (newpat) == pc_rtx)
4389 *new_direct_jump_p = 1;
4390 update_cfg_for_uncondjump (i3);
4393 if (undobuf.other_insn != NULL_RTX
4394 && GET_CODE (PATTERN (undobuf.other_insn)) == SET
4395 && SET_SRC (PATTERN (undobuf.other_insn)) == pc_rtx
4396 && SET_DEST (PATTERN (undobuf.other_insn)) == pc_rtx)
4398 *new_direct_jump_p = 1;
4399 update_cfg_for_uncondjump (undobuf.other_insn);
4402 combine_successes++;
4405 if (added_links_insn
4406 && (newi2pat == 0 || DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i2))
4407 && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i3))
4408 return added_links_insn;
4410 return newi2pat ? i2 : i3;
4413 /* Undo all the modifications recorded in undobuf. */
4418 struct undo *undo, *next;
4420 for (undo = undobuf.undos; undo; undo = next)
4426 *undo->where.r = undo->old_contents.r;
4429 *undo->where.i = undo->old_contents.i;
4432 adjust_reg_mode (*undo->where.r, undo->old_contents.m);
4438 undo->next = undobuf.frees;
4439 undobuf.frees = undo;
4445 /* We've committed to accepting the changes we made. Move all
4446 of the undos to the free list. */
4451 struct undo *undo, *next;
4453 for (undo = undobuf.undos; undo; undo = next)
4456 undo->next = undobuf.frees;
4457 undobuf.frees = undo;
4462 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4463 where we have an arithmetic expression and return that point. LOC will
4466 try_combine will call this function to see if an insn can be split into
4470 find_split_point (rtx *loc, rtx insn, bool set_src)
4473 enum rtx_code code = GET_CODE (x);
4475 unsigned HOST_WIDE_INT len = 0;
4476 HOST_WIDE_INT pos = 0;
4478 rtx inner = NULL_RTX;
4480 /* First special-case some codes. */
4484 #ifdef INSN_SCHEDULING
4485 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4487 if (MEM_P (SUBREG_REG (x)))
4490 return find_split_point (&SUBREG_REG (x), insn, false);
4494 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4495 using LO_SUM and HIGH. */
4496 if (GET_CODE (XEXP (x, 0)) == CONST
4497 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
4499 enum machine_mode address_mode
4500 = targetm.addr_space.address_mode (MEM_ADDR_SPACE (x));
4503 gen_rtx_LO_SUM (address_mode,
4504 gen_rtx_HIGH (address_mode, XEXP (x, 0)),
4506 return &XEXP (XEXP (x, 0), 0);
4510 /* If we have a PLUS whose second operand is a constant and the
4511 address is not valid, perhaps will can split it up using
4512 the machine-specific way to split large constants. We use
4513 the first pseudo-reg (one of the virtual regs) as a placeholder;
4514 it will not remain in the result. */
4515 if (GET_CODE (XEXP (x, 0)) == PLUS
4516 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
4517 && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4518 MEM_ADDR_SPACE (x)))
4520 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
4521 rtx seq = combine_split_insns (gen_rtx_SET (VOIDmode, reg,
4525 /* This should have produced two insns, each of which sets our
4526 placeholder. If the source of the second is a valid address,
4527 we can make put both sources together and make a split point
4531 && NEXT_INSN (seq) != NULL_RTX
4532 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
4533 && NONJUMP_INSN_P (seq)
4534 && GET_CODE (PATTERN (seq)) == SET
4535 && SET_DEST (PATTERN (seq)) == reg
4536 && ! reg_mentioned_p (reg,
4537 SET_SRC (PATTERN (seq)))
4538 && NONJUMP_INSN_P (NEXT_INSN (seq))
4539 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
4540 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
4541 && memory_address_addr_space_p
4542 (GET_MODE (x), SET_SRC (PATTERN (NEXT_INSN (seq))),
4543 MEM_ADDR_SPACE (x)))
4545 rtx src1 = SET_SRC (PATTERN (seq));
4546 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
4548 /* Replace the placeholder in SRC2 with SRC1. If we can
4549 find where in SRC2 it was placed, that can become our
4550 split point and we can replace this address with SRC2.
4551 Just try two obvious places. */
4553 src2 = replace_rtx (src2, reg, src1);
4555 if (XEXP (src2, 0) == src1)
4556 split = &XEXP (src2, 0);
4557 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
4558 && XEXP (XEXP (src2, 0), 0) == src1)
4559 split = &XEXP (XEXP (src2, 0), 0);
4563 SUBST (XEXP (x, 0), src2);
4568 /* If that didn't work, perhaps the first operand is complex and
4569 needs to be computed separately, so make a split point there.
4570 This will occur on machines that just support REG + CONST
4571 and have a constant moved through some previous computation. */
4573 else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
4574 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4575 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4576 return &XEXP (XEXP (x, 0), 0);
4579 /* If we have a PLUS whose first operand is complex, try computing it
4580 separately by making a split there. */
4581 if (GET_CODE (XEXP (x, 0)) == PLUS
4582 && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4584 && ! OBJECT_P (XEXP (XEXP (x, 0), 0))
4585 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4586 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4587 return &XEXP (XEXP (x, 0), 0);
4592 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4593 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4594 we need to put the operand into a register. So split at that
4597 if (SET_DEST (x) == cc0_rtx
4598 && GET_CODE (SET_SRC (x)) != COMPARE
4599 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
4600 && !OBJECT_P (SET_SRC (x))
4601 && ! (GET_CODE (SET_SRC (x)) == SUBREG
4602 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
4603 return &SET_SRC (x);
4606 /* See if we can split SET_SRC as it stands. */
4607 split = find_split_point (&SET_SRC (x), insn, true);
4608 if (split && split != &SET_SRC (x))
4611 /* See if we can split SET_DEST as it stands. */
4612 split = find_split_point (&SET_DEST (x), insn, false);
4613 if (split && split != &SET_DEST (x))
4616 /* See if this is a bitfield assignment with everything constant. If
4617 so, this is an IOR of an AND, so split it into that. */
4618 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
4619 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
4620 <= HOST_BITS_PER_WIDE_INT)
4621 && CONST_INT_P (XEXP (SET_DEST (x), 1))
4622 && CONST_INT_P (XEXP (SET_DEST (x), 2))
4623 && CONST_INT_P (SET_SRC (x))
4624 && ((INTVAL (XEXP (SET_DEST (x), 1))
4625 + INTVAL (XEXP (SET_DEST (x), 2)))
4626 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
4627 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
4629 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
4630 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
4631 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
4632 rtx dest = XEXP (SET_DEST (x), 0);
4633 enum machine_mode mode = GET_MODE (dest);
4634 unsigned HOST_WIDE_INT mask
4635 = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
4638 if (BITS_BIG_ENDIAN)
4639 pos = GET_MODE_BITSIZE (mode) - len - pos;
4641 or_mask = gen_int_mode (src << pos, mode);
4644 simplify_gen_binary (IOR, mode, dest, or_mask));
4647 rtx negmask = gen_int_mode (~(mask << pos), mode);
4649 simplify_gen_binary (IOR, mode,
4650 simplify_gen_binary (AND, mode,
4655 SUBST (SET_DEST (x), dest);
4657 split = find_split_point (&SET_SRC (x), insn, true);
4658 if (split && split != &SET_SRC (x))
4662 /* Otherwise, see if this is an operation that we can split into two.
4663 If so, try to split that. */
4664 code = GET_CODE (SET_SRC (x));
4669 /* If we are AND'ing with a large constant that is only a single
4670 bit and the result is only being used in a context where we
4671 need to know if it is zero or nonzero, replace it with a bit
4672 extraction. This will avoid the large constant, which might
4673 have taken more than one insn to make. If the constant were
4674 not a valid argument to the AND but took only one insn to make,
4675 this is no worse, but if it took more than one insn, it will
4678 if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4679 && REG_P (XEXP (SET_SRC (x), 0))
4680 && (pos = exact_log2 (UINTVAL (XEXP (SET_SRC (x), 1)))) >= 7
4681 && REG_P (SET_DEST (x))
4682 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
4683 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
4684 && XEXP (*split, 0) == SET_DEST (x)
4685 && XEXP (*split, 1) == const0_rtx)
4687 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
4688 XEXP (SET_SRC (x), 0),
4689 pos, NULL_RTX, 1, 1, 0, 0);
4690 if (extraction != 0)
4692 SUBST (SET_SRC (x), extraction);
4693 return find_split_point (loc, insn, false);
4699 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4700 is known to be on, this can be converted into a NEG of a shift. */
4701 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
4702 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
4703 && 1 <= (pos = exact_log2
4704 (nonzero_bits (XEXP (SET_SRC (x), 0),
4705 GET_MODE (XEXP (SET_SRC (x), 0))))))
4707 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
4711 gen_rtx_LSHIFTRT (mode,
4712 XEXP (SET_SRC (x), 0),
4715 split = find_split_point (&SET_SRC (x), insn, true);
4716 if (split && split != &SET_SRC (x))
4722 inner = XEXP (SET_SRC (x), 0);
4724 /* We can't optimize if either mode is a partial integer
4725 mode as we don't know how many bits are significant
4727 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
4728 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
4732 len = GET_MODE_BITSIZE (GET_MODE (inner));
4738 if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4739 && CONST_INT_P (XEXP (SET_SRC (x), 2)))
4741 inner = XEXP (SET_SRC (x), 0);
4742 len = INTVAL (XEXP (SET_SRC (x), 1));
4743 pos = INTVAL (XEXP (SET_SRC (x), 2));
4745 if (BITS_BIG_ENDIAN)
4746 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
4747 unsignedp = (code == ZERO_EXTRACT);
4755 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
4757 enum machine_mode mode = GET_MODE (SET_SRC (x));
4759 /* For unsigned, we have a choice of a shift followed by an
4760 AND or two shifts. Use two shifts for field sizes where the
4761 constant might be too large. We assume here that we can
4762 always at least get 8-bit constants in an AND insn, which is
4763 true for every current RISC. */
4765 if (unsignedp && len <= 8)
4770 (mode, gen_lowpart (mode, inner),
4772 GEN_INT (((unsigned HOST_WIDE_INT) 1 << len)
4775 split = find_split_point (&SET_SRC (x), insn, true);
4776 if (split && split != &SET_SRC (x))
4783 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
4784 gen_rtx_ASHIFT (mode,
4785 gen_lowpart (mode, inner),
4786 GEN_INT (GET_MODE_BITSIZE (mode)
4788 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
4790 split = find_split_point (&SET_SRC (x), insn, true);
4791 if (split && split != &SET_SRC (x))
4796 /* See if this is a simple operation with a constant as the second
4797 operand. It might be that this constant is out of range and hence
4798 could be used as a split point. */
4799 if (BINARY_P (SET_SRC (x))
4800 && CONSTANT_P (XEXP (SET_SRC (x), 1))
4801 && (OBJECT_P (XEXP (SET_SRC (x), 0))
4802 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
4803 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
4804 return &XEXP (SET_SRC (x), 1);
4806 /* Finally, see if this is a simple operation with its first operand
4807 not in a register. The operation might require this operand in a
4808 register, so return it as a split point. We can always do this
4809 because if the first operand were another operation, we would have
4810 already found it as a split point. */
4811 if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
4812 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
4813 return &XEXP (SET_SRC (x), 0);
4819 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4820 it is better to write this as (not (ior A B)) so we can split it.
4821 Similarly for IOR. */
4822 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
4825 gen_rtx_NOT (GET_MODE (x),
4826 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
4828 XEXP (XEXP (x, 0), 0),
4829 XEXP (XEXP (x, 1), 0))));
4830 return find_split_point (loc, insn, set_src);
4833 /* Many RISC machines have a large set of logical insns. If the
4834 second operand is a NOT, put it first so we will try to split the
4835 other operand first. */
4836 if (GET_CODE (XEXP (x, 1)) == NOT)
4838 rtx tem = XEXP (x, 0);
4839 SUBST (XEXP (x, 0), XEXP (x, 1));
4840 SUBST (XEXP (x, 1), tem);
4846 /* Canonicalization can produce (minus A (mult B C)), where C is a
4847 constant. It may be better to try splitting (plus (mult B -C) A)
4848 instead if this isn't a multiply by a power of two. */
4849 if (set_src && code == MINUS && GET_CODE (XEXP (x, 1)) == MULT
4850 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4851 && exact_log2 (INTVAL (XEXP (XEXP (x, 1), 1))) < 0)
4853 enum machine_mode mode = GET_MODE (x);
4854 unsigned HOST_WIDE_INT this_int = INTVAL (XEXP (XEXP (x, 1), 1));
4855 HOST_WIDE_INT other_int = trunc_int_for_mode (-this_int, mode);
4856 SUBST (*loc, gen_rtx_PLUS (mode, gen_rtx_MULT (mode,
4857 XEXP (XEXP (x, 1), 0),
4858 GEN_INT (other_int)),
4860 return find_split_point (loc, insn, set_src);
4863 /* Split at a multiply-accumulate instruction. However if this is
4864 the SET_SRC, we likely do not have such an instruction and it's
4865 worthless to try this split. */
4866 if (!set_src && GET_CODE (XEXP (x, 0)) == MULT)
4873 /* Otherwise, select our actions depending on our rtx class. */
4874 switch (GET_RTX_CLASS (code))
4876 case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
4878 split = find_split_point (&XEXP (x, 2), insn, false);
4881 /* ... fall through ... */
4883 case RTX_COMM_ARITH:
4885 case RTX_COMM_COMPARE:
4886 split = find_split_point (&XEXP (x, 1), insn, false);
4889 /* ... fall through ... */
4891 /* Some machines have (and (shift ...) ...) insns. If X is not
4892 an AND, but XEXP (X, 0) is, use it as our split point. */
4893 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
4894 return &XEXP (x, 0);
4896 split = find_split_point (&XEXP (x, 0), insn, false);
4902 /* Otherwise, we don't have a split point. */
4907 /* Throughout X, replace FROM with TO, and return the result.
4908 The result is TO if X is FROM;
4909 otherwise the result is X, but its contents may have been modified.
4910 If they were modified, a record was made in undobuf so that
4911 undo_all will (among other things) return X to its original state.
4913 If the number of changes necessary is too much to record to undo,
4914 the excess changes are not made, so the result is invalid.
4915 The changes already made can still be undone.
4916 undobuf.num_undo is incremented for such changes, so by testing that
4917 the caller can tell whether the result is valid.
4919 `n_occurrences' is incremented each time FROM is replaced.
4921 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4923 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
4924 by copying if `n_occurrences' is nonzero. */
4927 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
4929 enum rtx_code code = GET_CODE (x);
4930 enum machine_mode op0_mode = VOIDmode;
4935 /* Two expressions are equal if they are identical copies of a shared
4936 RTX or if they are both registers with the same register number
4939 #define COMBINE_RTX_EQUAL_P(X,Y) \
4941 || (REG_P (X) && REG_P (Y) \
4942 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4944 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
4947 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
4950 /* If X and FROM are the same register but different modes, they
4951 will not have been seen as equal above. However, the log links code
4952 will make a LOG_LINKS entry for that case. If we do nothing, we
4953 will try to rerecognize our original insn and, when it succeeds,
4954 we will delete the feeding insn, which is incorrect.
4956 So force this insn not to match in this (rare) case. */
4957 if (! in_dest && code == REG && REG_P (from)
4958 && reg_overlap_mentioned_p (x, from))
4959 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
4961 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4962 of which may contain things that can be combined. */
4963 if (code != MEM && code != LO_SUM && OBJECT_P (x))
4966 /* It is possible to have a subexpression appear twice in the insn.
4967 Suppose that FROM is a register that appears within TO.
4968 Then, after that subexpression has been scanned once by `subst',
4969 the second time it is scanned, TO may be found. If we were
4970 to scan TO here, we would find FROM within it and create a
4971 self-referent rtl structure which is completely wrong. */
4972 if (COMBINE_RTX_EQUAL_P (x, to))
4975 /* Parallel asm_operands need special attention because all of the
4976 inputs are shared across the arms. Furthermore, unsharing the
4977 rtl results in recognition failures. Failure to handle this case
4978 specially can result in circular rtl.
4980 Solve this by doing a normal pass across the first entry of the
4981 parallel, and only processing the SET_DESTs of the subsequent
4984 if (code == PARALLEL
4985 && GET_CODE (XVECEXP (x, 0, 0)) == SET
4986 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
4988 new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
4990 /* If this substitution failed, this whole thing fails. */
4991 if (GET_CODE (new_rtx) == CLOBBER
4992 && XEXP (new_rtx, 0) == const0_rtx)
4995 SUBST (XVECEXP (x, 0, 0), new_rtx);
4997 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
4999 rtx dest = SET_DEST (XVECEXP (x, 0, i));
5002 && GET_CODE (dest) != CC0
5003 && GET_CODE (dest) != PC)
5005 new_rtx = subst (dest, from, to, 0, unique_copy);
5007 /* If this substitution failed, this whole thing fails. */
5008 if (GET_CODE (new_rtx) == CLOBBER
5009 && XEXP (new_rtx, 0) == const0_rtx)
5012 SUBST (SET_DEST (XVECEXP (x, 0, i)), new_rtx);
5018 len = GET_RTX_LENGTH (code);
5019 fmt = GET_RTX_FORMAT (code);
5021 /* We don't need to process a SET_DEST that is a register, CC0,
5022 or PC, so set up to skip this common case. All other cases
5023 where we want to suppress replacing something inside a
5024 SET_SRC are handled via the IN_DEST operand. */
5026 && (REG_P (SET_DEST (x))
5027 || GET_CODE (SET_DEST (x)) == CC0
5028 || GET_CODE (SET_DEST (x)) == PC))
5031 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5034 op0_mode = GET_MODE (XEXP (x, 0));
5036 for (i = 0; i < len; i++)
5041 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5043 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
5045 new_rtx = (unique_copy && n_occurrences
5046 ? copy_rtx (to) : to);
5051 new_rtx = subst (XVECEXP (x, i, j), from, to, 0,
5054 /* If this substitution failed, this whole thing
5056 if (GET_CODE (new_rtx) == CLOBBER
5057 && XEXP (new_rtx, 0) == const0_rtx)
5061 SUBST (XVECEXP (x, i, j), new_rtx);
5064 else if (fmt[i] == 'e')
5066 /* If this is a register being set, ignore it. */
5067 new_rtx = XEXP (x, i);
5070 && (((code == SUBREG || code == ZERO_EXTRACT)
5072 || code == STRICT_LOW_PART))
5075 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
5077 /* In general, don't install a subreg involving two
5078 modes not tieable. It can worsen register
5079 allocation, and can even make invalid reload
5080 insns, since the reg inside may need to be copied
5081 from in the outside mode, and that may be invalid
5082 if it is an fp reg copied in integer mode.
5084 We allow two exceptions to this: It is valid if
5085 it is inside another SUBREG and the mode of that
5086 SUBREG and the mode of the inside of TO is
5087 tieable and it is valid if X is a SET that copies
5090 if (GET_CODE (to) == SUBREG
5091 && ! MODES_TIEABLE_P (GET_MODE (to),
5092 GET_MODE (SUBREG_REG (to)))
5093 && ! (code == SUBREG
5094 && MODES_TIEABLE_P (GET_MODE (x),
5095 GET_MODE (SUBREG_REG (to))))
5097 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
5100 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5102 #ifdef CANNOT_CHANGE_MODE_CLASS
5105 && REGNO (to) < FIRST_PSEUDO_REGISTER
5106 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
5109 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5112 new_rtx = (unique_copy && n_occurrences ? copy_rtx (to) : to);
5116 /* If we are in a SET_DEST, suppress most cases unless we
5117 have gone inside a MEM, in which case we want to
5118 simplify the address. We assume here that things that
5119 are actually part of the destination have their inner
5120 parts in the first expression. This is true for SUBREG,
5121 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5122 things aside from REG and MEM that should appear in a
5124 new_rtx = subst (XEXP (x, i), from, to,
5126 && (code == SUBREG || code == STRICT_LOW_PART
5127 || code == ZERO_EXTRACT))
5129 && i == 0), unique_copy);
5131 /* If we found that we will have to reject this combination,
5132 indicate that by returning the CLOBBER ourselves, rather than
5133 an expression containing it. This will speed things up as
5134 well as prevent accidents where two CLOBBERs are considered
5135 to be equal, thus producing an incorrect simplification. */
5137 if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx)
5140 if (GET_CODE (x) == SUBREG
5141 && (CONST_INT_P (new_rtx)
5142 || GET_CODE (new_rtx) == CONST_DOUBLE))
5144 enum machine_mode mode = GET_MODE (x);
5146 x = simplify_subreg (GET_MODE (x), new_rtx,
5147 GET_MODE (SUBREG_REG (x)),
5150 x = gen_rtx_CLOBBER (mode, const0_rtx);
5152 else if (CONST_INT_P (new_rtx)
5153 && GET_CODE (x) == ZERO_EXTEND)
5155 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
5156 new_rtx, GET_MODE (XEXP (x, 0)));
5160 SUBST (XEXP (x, i), new_rtx);
5165 /* Check if we are loading something from the constant pool via float
5166 extension; in this case we would undo compress_float_constant
5167 optimization and degenerate constant load to an immediate value. */
5168 if (GET_CODE (x) == FLOAT_EXTEND
5169 && MEM_P (XEXP (x, 0))
5170 && MEM_READONLY_P (XEXP (x, 0)))
5172 rtx tmp = avoid_constant_pool_reference (x);
5177 /* Try to simplify X. If the simplification changed the code, it is likely
5178 that further simplification will help, so loop, but limit the number
5179 of repetitions that will be performed. */
5181 for (i = 0; i < 4; i++)
5183 /* If X is sufficiently simple, don't bother trying to do anything
5185 if (code != CONST_INT && code != REG && code != CLOBBER)
5186 x = combine_simplify_rtx (x, op0_mode, in_dest);
5188 if (GET_CODE (x) == code)
5191 code = GET_CODE (x);
5193 /* We no longer know the original mode of operand 0 since we
5194 have changed the form of X) */
5195 op0_mode = VOIDmode;
5201 /* Simplify X, a piece of RTL. We just operate on the expression at the
5202 outer level; call `subst' to simplify recursively. Return the new
5205 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5206 if we are inside a SET_DEST. */
5209 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
5211 enum rtx_code code = GET_CODE (x);
5212 enum machine_mode mode = GET_MODE (x);
5216 /* If this is a commutative operation, put a constant last and a complex
5217 expression first. We don't need to do this for comparisons here. */
5218 if (COMMUTATIVE_ARITH_P (x)
5219 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
5222 SUBST (XEXP (x, 0), XEXP (x, 1));
5223 SUBST (XEXP (x, 1), temp);
5226 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5227 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5228 things. Check for cases where both arms are testing the same
5231 Don't do anything if all operands are very simple. */
5234 && ((!OBJECT_P (XEXP (x, 0))
5235 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5236 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
5237 || (!OBJECT_P (XEXP (x, 1))
5238 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
5239 && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
5241 && (!OBJECT_P (XEXP (x, 0))
5242 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5243 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
5245 rtx cond, true_rtx, false_rtx;
5247 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
5249 /* If everything is a comparison, what we have is highly unlikely
5250 to be simpler, so don't use it. */
5251 && ! (COMPARISON_P (x)
5252 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
5254 rtx cop1 = const0_rtx;
5255 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
5257 if (cond_code == NE && COMPARISON_P (cond))
5260 /* Simplify the alternative arms; this may collapse the true and
5261 false arms to store-flag values. Be careful to use copy_rtx
5262 here since true_rtx or false_rtx might share RTL with x as a
5263 result of the if_then_else_cond call above. */
5264 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
5265 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
5267 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5268 is unlikely to be simpler. */
5269 if (general_operand (true_rtx, VOIDmode)
5270 && general_operand (false_rtx, VOIDmode))
5272 enum rtx_code reversed;
5274 /* Restarting if we generate a store-flag expression will cause
5275 us to loop. Just drop through in this case. */
5277 /* If the result values are STORE_FLAG_VALUE and zero, we can
5278 just make the comparison operation. */
5279 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
5280 x = simplify_gen_relational (cond_code, mode, VOIDmode,
5282 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
5283 && ((reversed = reversed_comparison_code_parts
5284 (cond_code, cond, cop1, NULL))
5286 x = simplify_gen_relational (reversed, mode, VOIDmode,
5289 /* Likewise, we can make the negate of a comparison operation
5290 if the result values are - STORE_FLAG_VALUE and zero. */
5291 else if (CONST_INT_P (true_rtx)
5292 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
5293 && false_rtx == const0_rtx)
5294 x = simplify_gen_unary (NEG, mode,
5295 simplify_gen_relational (cond_code,
5299 else if (CONST_INT_P (false_rtx)
5300 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
5301 && true_rtx == const0_rtx
5302 && ((reversed = reversed_comparison_code_parts
5303 (cond_code, cond, cop1, NULL))
5305 x = simplify_gen_unary (NEG, mode,
5306 simplify_gen_relational (reversed,
5311 return gen_rtx_IF_THEN_ELSE (mode,
5312 simplify_gen_relational (cond_code,
5317 true_rtx, false_rtx);
5319 code = GET_CODE (x);
5320 op0_mode = VOIDmode;
5325 /* Try to fold this expression in case we have constants that weren't
5328 switch (GET_RTX_CLASS (code))
5331 if (op0_mode == VOIDmode)
5332 op0_mode = GET_MODE (XEXP (x, 0));
5333 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
5336 case RTX_COMM_COMPARE:
5338 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
5339 if (cmp_mode == VOIDmode)
5341 cmp_mode = GET_MODE (XEXP (x, 1));
5342 if (cmp_mode == VOIDmode)
5343 cmp_mode = op0_mode;
5345 temp = simplify_relational_operation (code, mode, cmp_mode,
5346 XEXP (x, 0), XEXP (x, 1));
5349 case RTX_COMM_ARITH:
5351 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
5353 case RTX_BITFIELD_OPS:
5355 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
5356 XEXP (x, 1), XEXP (x, 2));
5365 code = GET_CODE (temp);
5366 op0_mode = VOIDmode;
5367 mode = GET_MODE (temp);
5370 /* First see if we can apply the inverse distributive law. */
5371 if (code == PLUS || code == MINUS
5372 || code == AND || code == IOR || code == XOR)
5374 x = apply_distributive_law (x);
5375 code = GET_CODE (x);
5376 op0_mode = VOIDmode;
5379 /* If CODE is an associative operation not otherwise handled, see if we
5380 can associate some operands. This can win if they are constants or
5381 if they are logically related (i.e. (a & b) & a). */
5382 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
5383 || code == AND || code == IOR || code == XOR
5384 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
5385 && ((INTEGRAL_MODE_P (mode) && code != DIV)
5386 || (flag_associative_math && FLOAT_MODE_P (mode))))
5388 if (GET_CODE (XEXP (x, 0)) == code)
5390 rtx other = XEXP (XEXP (x, 0), 0);
5391 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
5392 rtx inner_op1 = XEXP (x, 1);
5395 /* Make sure we pass the constant operand if any as the second
5396 one if this is a commutative operation. */
5397 if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
5399 rtx tem = inner_op0;
5400 inner_op0 = inner_op1;
5403 inner = simplify_binary_operation (code == MINUS ? PLUS
5404 : code == DIV ? MULT
5406 mode, inner_op0, inner_op1);
5408 /* For commutative operations, try the other pair if that one
5410 if (inner == 0 && COMMUTATIVE_ARITH_P (x))
5412 other = XEXP (XEXP (x, 0), 1);
5413 inner = simplify_binary_operation (code, mode,
5414 XEXP (XEXP (x, 0), 0),
5419 return simplify_gen_binary (code, mode, other, inner);
5423 /* A little bit of algebraic simplification here. */
5427 /* Ensure that our address has any ASHIFTs converted to MULT in case
5428 address-recognizing predicates are called later. */
5429 temp = make_compound_operation (XEXP (x, 0), MEM);
5430 SUBST (XEXP (x, 0), temp);
5434 if (op0_mode == VOIDmode)
5435 op0_mode = GET_MODE (SUBREG_REG (x));
5437 /* See if this can be moved to simplify_subreg. */
5438 if (CONSTANT_P (SUBREG_REG (x))
5439 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
5440 /* Don't call gen_lowpart if the inner mode
5441 is VOIDmode and we cannot simplify it, as SUBREG without
5442 inner mode is invalid. */
5443 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
5444 || gen_lowpart_common (mode, SUBREG_REG (x))))
5445 return gen_lowpart (mode, SUBREG_REG (x));
5447 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
5451 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
5457 /* Don't change the mode of the MEM if that would change the meaning
5459 if (MEM_P (SUBREG_REG (x))
5460 && (MEM_VOLATILE_P (SUBREG_REG (x))
5461 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
5462 return gen_rtx_CLOBBER (mode, const0_rtx);
5464 /* Note that we cannot do any narrowing for non-constants since
5465 we might have been counting on using the fact that some bits were
5466 zero. We now do this in the SET. */
5471 temp = expand_compound_operation (XEXP (x, 0));
5473 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5474 replaced by (lshiftrt X C). This will convert
5475 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5477 if (GET_CODE (temp) == ASHIFTRT
5478 && CONST_INT_P (XEXP (temp, 1))
5479 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
5480 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
5481 INTVAL (XEXP (temp, 1)));
5483 /* If X has only a single bit that might be nonzero, say, bit I, convert
5484 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5485 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5486 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5487 or a SUBREG of one since we'd be making the expression more
5488 complex if it was just a register. */
5491 && ! (GET_CODE (temp) == SUBREG
5492 && REG_P (SUBREG_REG (temp)))
5493 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
5495 rtx temp1 = simplify_shift_const
5496 (NULL_RTX, ASHIFTRT, mode,
5497 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
5498 GET_MODE_BITSIZE (mode) - 1 - i),
5499 GET_MODE_BITSIZE (mode) - 1 - i);
5501 /* If all we did was surround TEMP with the two shifts, we
5502 haven't improved anything, so don't use it. Otherwise,
5503 we are better off with TEMP1. */
5504 if (GET_CODE (temp1) != ASHIFTRT
5505 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
5506 || XEXP (XEXP (temp1, 0), 0) != temp)
5512 /* We can't handle truncation to a partial integer mode here
5513 because we don't know the real bitsize of the partial
5515 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
5518 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5520 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
5521 GET_MODE_MASK (mode), 0));
5523 /* We can truncate a constant value and return it. */
5524 if (CONST_INT_P (XEXP (x, 0)))
5525 return gen_int_mode (INTVAL (XEXP (x, 0)), mode);
5527 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5528 whose value is a comparison can be replaced with a subreg if
5529 STORE_FLAG_VALUE permits. */
5530 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5531 && (STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
5532 && (temp = get_last_value (XEXP (x, 0)))
5533 && COMPARISON_P (temp))
5534 return gen_lowpart (mode, XEXP (x, 0));
5538 /* (const (const X)) can become (const X). Do it this way rather than
5539 returning the inner CONST since CONST can be shared with a
5541 if (GET_CODE (XEXP (x, 0)) == CONST)
5542 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
5547 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5548 can add in an offset. find_split_point will split this address up
5549 again if it doesn't match. */
5550 if (GET_CODE (XEXP (x, 0)) == HIGH
5551 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
5557 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5558 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5559 bit-field and can be replaced by either a sign_extend or a
5560 sign_extract. The `and' may be a zero_extend and the two
5561 <c>, -<c> constants may be reversed. */
5562 if (GET_CODE (XEXP (x, 0)) == XOR
5563 && CONST_INT_P (XEXP (x, 1))
5564 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
5565 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
5566 && ((i = exact_log2 (UINTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
5567 || (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0)
5568 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5569 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
5570 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
5571 && (UINTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
5572 == ((unsigned HOST_WIDE_INT) 1 << (i + 1)) - 1))
5573 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
5574 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
5575 == (unsigned int) i + 1))))
5576 return simplify_shift_const
5577 (NULL_RTX, ASHIFTRT, mode,
5578 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5579 XEXP (XEXP (XEXP (x, 0), 0), 0),
5580 GET_MODE_BITSIZE (mode) - (i + 1)),
5581 GET_MODE_BITSIZE (mode) - (i + 1));
5583 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5584 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5585 the bitsize of the mode - 1. This allows simplification of
5586 "a = (b & 8) == 0;" */
5587 if (XEXP (x, 1) == constm1_rtx
5588 && !REG_P (XEXP (x, 0))
5589 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5590 && REG_P (SUBREG_REG (XEXP (x, 0))))
5591 && nonzero_bits (XEXP (x, 0), mode) == 1)
5592 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
5593 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5594 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
5595 GET_MODE_BITSIZE (mode) - 1),
5596 GET_MODE_BITSIZE (mode) - 1);
5598 /* If we are adding two things that have no bits in common, convert
5599 the addition into an IOR. This will often be further simplified,
5600 for example in cases like ((a & 1) + (a & 2)), which can
5603 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5604 && (nonzero_bits (XEXP (x, 0), mode)
5605 & nonzero_bits (XEXP (x, 1), mode)) == 0)
5607 /* Try to simplify the expression further. */
5608 rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
5609 temp = combine_simplify_rtx (tor, mode, in_dest);
5611 /* If we could, great. If not, do not go ahead with the IOR
5612 replacement, since PLUS appears in many special purpose
5613 address arithmetic instructions. */
5614 if (GET_CODE (temp) != CLOBBER && temp != tor)
5620 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5621 (and <foo> (const_int pow2-1)) */
5622 if (GET_CODE (XEXP (x, 1)) == AND
5623 && CONST_INT_P (XEXP (XEXP (x, 1), 1))
5624 && exact_log2 (-UINTVAL (XEXP (XEXP (x, 1), 1))) >= 0
5625 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
5626 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
5627 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
5631 /* If we have (mult (plus A B) C), apply the distributive law and then
5632 the inverse distributive law to see if things simplify. This
5633 occurs mostly in addresses, often when unrolling loops. */
5635 if (GET_CODE (XEXP (x, 0)) == PLUS)
5637 rtx result = distribute_and_simplify_rtx (x, 0);
5642 /* Try simplify a*(b/c) as (a*b)/c. */
5643 if (FLOAT_MODE_P (mode) && flag_associative_math
5644 && GET_CODE (XEXP (x, 0)) == DIV)
5646 rtx tem = simplify_binary_operation (MULT, mode,
5647 XEXP (XEXP (x, 0), 0),
5650 return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
5655 /* If this is a divide by a power of two, treat it as a shift if
5656 its first operand is a shift. */
5657 if (CONST_INT_P (XEXP (x, 1))
5658 && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0
5659 && (GET_CODE (XEXP (x, 0)) == ASHIFT
5660 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
5661 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
5662 || GET_CODE (XEXP (x, 0)) == ROTATE
5663 || GET_CODE (XEXP (x, 0)) == ROTATERT))
5664 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
5668 case GT: case GTU: case GE: case GEU:
5669 case LT: case LTU: case LE: case LEU:
5670 case UNEQ: case LTGT:
5671 case UNGT: case UNGE:
5672 case UNLT: case UNLE:
5673 case UNORDERED: case ORDERED:
5674 /* If the first operand is a condition code, we can't do anything
5676 if (GET_CODE (XEXP (x, 0)) == COMPARE
5677 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
5678 && ! CC0_P (XEXP (x, 0))))
5680 rtx op0 = XEXP (x, 0);
5681 rtx op1 = XEXP (x, 1);
5682 enum rtx_code new_code;
5684 if (GET_CODE (op0) == COMPARE)
5685 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
5687 /* Simplify our comparison, if possible. */
5688 new_code = simplify_comparison (code, &op0, &op1);
5690 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5691 if only the low-order bit is possibly nonzero in X (such as when
5692 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5693 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5694 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5697 Remove any ZERO_EXTRACT we made when thinking this was a
5698 comparison. It may now be simpler to use, e.g., an AND. If a
5699 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5700 the call to make_compound_operation in the SET case. */
5702 if (STORE_FLAG_VALUE == 1
5703 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5704 && op1 == const0_rtx
5705 && mode == GET_MODE (op0)
5706 && nonzero_bits (op0, mode) == 1)
5707 return gen_lowpart (mode,
5708 expand_compound_operation (op0));
5710 else if (STORE_FLAG_VALUE == 1
5711 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5712 && op1 == const0_rtx
5713 && mode == GET_MODE (op0)
5714 && (num_sign_bit_copies (op0, mode)
5715 == GET_MODE_BITSIZE (mode)))
5717 op0 = expand_compound_operation (op0);
5718 return simplify_gen_unary (NEG, mode,
5719 gen_lowpart (mode, op0),
5723 else if (STORE_FLAG_VALUE == 1
5724 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5725 && op1 == const0_rtx
5726 && mode == GET_MODE (op0)
5727 && nonzero_bits (op0, mode) == 1)
5729 op0 = expand_compound_operation (op0);
5730 return simplify_gen_binary (XOR, mode,
5731 gen_lowpart (mode, op0),
5735 else if (STORE_FLAG_VALUE == 1
5736 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5737 && op1 == const0_rtx
5738 && mode == GET_MODE (op0)
5739 && (num_sign_bit_copies (op0, mode)
5740 == GET_MODE_BITSIZE (mode)))
5742 op0 = expand_compound_operation (op0);
5743 return plus_constant (gen_lowpart (mode, op0), 1);
5746 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5748 if (STORE_FLAG_VALUE == -1
5749 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5750 && op1 == const0_rtx
5751 && (num_sign_bit_copies (op0, mode)
5752 == GET_MODE_BITSIZE (mode)))
5753 return gen_lowpart (mode,
5754 expand_compound_operation (op0));
5756 else if (STORE_FLAG_VALUE == -1
5757 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5758 && op1 == const0_rtx
5759 && mode == GET_MODE (op0)
5760 && nonzero_bits (op0, mode) == 1)
5762 op0 = expand_compound_operation (op0);
5763 return simplify_gen_unary (NEG, mode,
5764 gen_lowpart (mode, op0),
5768 else if (STORE_FLAG_VALUE == -1
5769 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5770 && op1 == const0_rtx
5771 && mode == GET_MODE (op0)
5772 && (num_sign_bit_copies (op0, mode)
5773 == GET_MODE_BITSIZE (mode)))
5775 op0 = expand_compound_operation (op0);
5776 return simplify_gen_unary (NOT, mode,
5777 gen_lowpart (mode, op0),
5781 /* If X is 0/1, (eq X 0) is X-1. */
5782 else if (STORE_FLAG_VALUE == -1
5783 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5784 && op1 == const0_rtx
5785 && mode == GET_MODE (op0)
5786 && nonzero_bits (op0, mode) == 1)
5788 op0 = expand_compound_operation (op0);
5789 return plus_constant (gen_lowpart (mode, op0), -1);
5792 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5793 one bit that might be nonzero, we can convert (ne x 0) to
5794 (ashift x c) where C puts the bit in the sign bit. Remove any
5795 AND with STORE_FLAG_VALUE when we are done, since we are only
5796 going to test the sign bit. */
5797 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5798 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5799 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5800 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5801 && op1 == const0_rtx
5802 && mode == GET_MODE (op0)
5803 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
5805 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
5806 expand_compound_operation (op0),
5807 GET_MODE_BITSIZE (mode) - 1 - i);
5808 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
5814 /* If the code changed, return a whole new comparison. */
5815 if (new_code != code)
5816 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
5818 /* Otherwise, keep this operation, but maybe change its operands.
5819 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5820 SUBST (XEXP (x, 0), op0);
5821 SUBST (XEXP (x, 1), op1);
5826 return simplify_if_then_else (x);
5832 /* If we are processing SET_DEST, we are done. */
5836 return expand_compound_operation (x);
5839 return simplify_set (x);
5843 return simplify_logical (x);
5850 /* If this is a shift by a constant amount, simplify it. */
5851 if (CONST_INT_P (XEXP (x, 1)))
5852 return simplify_shift_const (x, code, mode, XEXP (x, 0),
5853 INTVAL (XEXP (x, 1)));
5855 else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
5857 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
5858 ((unsigned HOST_WIDE_INT) 1
5859 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
5871 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5874 simplify_if_then_else (rtx x)
5876 enum machine_mode mode = GET_MODE (x);
5877 rtx cond = XEXP (x, 0);
5878 rtx true_rtx = XEXP (x, 1);
5879 rtx false_rtx = XEXP (x, 2);
5880 enum rtx_code true_code = GET_CODE (cond);
5881 int comparison_p = COMPARISON_P (cond);
5884 enum rtx_code false_code;
5887 /* Simplify storing of the truth value. */
5888 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
5889 return simplify_gen_relational (true_code, mode, VOIDmode,
5890 XEXP (cond, 0), XEXP (cond, 1));
5892 /* Also when the truth value has to be reversed. */
5894 && true_rtx == const0_rtx && false_rtx == const_true_rtx
5895 && (reversed = reversed_comparison (cond, mode)))
5898 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5899 in it is being compared against certain values. Get the true and false
5900 comparisons and see if that says anything about the value of each arm. */
5903 && ((false_code = reversed_comparison_code (cond, NULL))
5905 && REG_P (XEXP (cond, 0)))
5908 rtx from = XEXP (cond, 0);
5909 rtx true_val = XEXP (cond, 1);
5910 rtx false_val = true_val;
5913 /* If FALSE_CODE is EQ, swap the codes and arms. */
5915 if (false_code == EQ)
5917 swapped = 1, true_code = EQ, false_code = NE;
5918 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5921 /* If we are comparing against zero and the expression being tested has
5922 only a single bit that might be nonzero, that is its value when it is
5923 not equal to zero. Similarly if it is known to be -1 or 0. */
5925 if (true_code == EQ && true_val == const0_rtx
5926 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
5929 false_val = GEN_INT (trunc_int_for_mode (nzb, GET_MODE (from)));
5931 else if (true_code == EQ && true_val == const0_rtx
5932 && (num_sign_bit_copies (from, GET_MODE (from))
5933 == GET_MODE_BITSIZE (GET_MODE (from))))
5936 false_val = constm1_rtx;
5939 /* Now simplify an arm if we know the value of the register in the
5940 branch and it is used in the arm. Be careful due to the potential
5941 of locally-shared RTL. */
5943 if (reg_mentioned_p (from, true_rtx))
5944 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
5946 pc_rtx, pc_rtx, 0, 0);
5947 if (reg_mentioned_p (from, false_rtx))
5948 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
5950 pc_rtx, pc_rtx, 0, 0);
5952 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
5953 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
5955 true_rtx = XEXP (x, 1);
5956 false_rtx = XEXP (x, 2);
5957 true_code = GET_CODE (cond);
5960 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
5961 reversed, do so to avoid needing two sets of patterns for
5962 subtract-and-branch insns. Similarly if we have a constant in the true
5963 arm, the false arm is the same as the first operand of the comparison, or
5964 the false arm is more complicated than the true arm. */
5967 && reversed_comparison_code (cond, NULL) != UNKNOWN
5968 && (true_rtx == pc_rtx
5969 || (CONSTANT_P (true_rtx)
5970 && !CONST_INT_P (false_rtx) && false_rtx != pc_rtx)
5971 || true_rtx == const0_rtx
5972 || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
5973 || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
5974 && !OBJECT_P (false_rtx))
5975 || reg_mentioned_p (true_rtx, false_rtx)
5976 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
5978 true_code = reversed_comparison_code (cond, NULL);
5979 SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
5980 SUBST (XEXP (x, 1), false_rtx);
5981 SUBST (XEXP (x, 2), true_rtx);
5983 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5986 /* It is possible that the conditional has been simplified out. */
5987 true_code = GET_CODE (cond);
5988 comparison_p = COMPARISON_P (cond);
5991 /* If the two arms are identical, we don't need the comparison. */
5993 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
5996 /* Convert a == b ? b : a to "a". */
5997 if (true_code == EQ && ! side_effects_p (cond)
5998 && !HONOR_NANS (mode)
5999 && rtx_equal_p (XEXP (cond, 0), false_rtx)
6000 && rtx_equal_p (XEXP (cond, 1), true_rtx))
6002 else if (true_code == NE && ! side_effects_p (cond)
6003 && !HONOR_NANS (mode)
6004 && rtx_equal_p (XEXP (cond, 0), true_rtx)
6005 && rtx_equal_p (XEXP (cond, 1), false_rtx))
6008 /* Look for cases where we have (abs x) or (neg (abs X)). */
6010 if (GET_MODE_CLASS (mode) == MODE_INT
6012 && XEXP (cond, 1) == const0_rtx
6013 && GET_CODE (false_rtx) == NEG
6014 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
6015 && rtx_equal_p (true_rtx, XEXP (cond, 0))
6016 && ! side_effects_p (true_rtx))
6021 return simplify_gen_unary (ABS, mode, true_rtx, mode);
6025 simplify_gen_unary (NEG, mode,
6026 simplify_gen_unary (ABS, mode, true_rtx, mode),
6032 /* Look for MIN or MAX. */
6034 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
6036 && rtx_equal_p (XEXP (cond, 0), true_rtx)
6037 && rtx_equal_p (XEXP (cond, 1), false_rtx)
6038 && ! side_effects_p (cond))
6043 return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
6046 return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
6049 return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
6052 return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
6057 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6058 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6059 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6060 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6061 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6062 neither 1 or -1, but it isn't worth checking for. */
6064 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6066 && GET_MODE_CLASS (mode) == MODE_INT
6067 && ! side_effects_p (x))
6069 rtx t = make_compound_operation (true_rtx, SET);
6070 rtx f = make_compound_operation (false_rtx, SET);
6071 rtx cond_op0 = XEXP (cond, 0);
6072 rtx cond_op1 = XEXP (cond, 1);
6073 enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
6074 enum machine_mode m = mode;
6075 rtx z = 0, c1 = NULL_RTX;
6077 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
6078 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
6079 || GET_CODE (t) == ASHIFT
6080 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
6081 && rtx_equal_p (XEXP (t, 0), f))
6082 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
6084 /* If an identity-zero op is commutative, check whether there
6085 would be a match if we swapped the operands. */
6086 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
6087 || GET_CODE (t) == XOR)
6088 && rtx_equal_p (XEXP (t, 1), f))
6089 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
6090 else if (GET_CODE (t) == SIGN_EXTEND
6091 && (GET_CODE (XEXP (t, 0)) == PLUS
6092 || GET_CODE (XEXP (t, 0)) == MINUS
6093 || GET_CODE (XEXP (t, 0)) == IOR
6094 || GET_CODE (XEXP (t, 0)) == XOR
6095 || GET_CODE (XEXP (t, 0)) == ASHIFT
6096 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6097 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6098 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6099 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6100 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6101 && (num_sign_bit_copies (f, GET_MODE (f))
6103 (GET_MODE_BITSIZE (mode)
6104 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
6106 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6107 extend_op = SIGN_EXTEND;
6108 m = GET_MODE (XEXP (t, 0));
6110 else if (GET_CODE (t) == SIGN_EXTEND
6111 && (GET_CODE (XEXP (t, 0)) == PLUS
6112 || GET_CODE (XEXP (t, 0)) == IOR
6113 || GET_CODE (XEXP (t, 0)) == XOR)
6114 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6115 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6116 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6117 && (num_sign_bit_copies (f, GET_MODE (f))
6119 (GET_MODE_BITSIZE (mode)
6120 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
6122 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6123 extend_op = SIGN_EXTEND;
6124 m = GET_MODE (XEXP (t, 0));
6126 else if (GET_CODE (t) == ZERO_EXTEND
6127 && (GET_CODE (XEXP (t, 0)) == PLUS
6128 || GET_CODE (XEXP (t, 0)) == MINUS
6129 || GET_CODE (XEXP (t, 0)) == IOR
6130 || GET_CODE (XEXP (t, 0)) == XOR
6131 || GET_CODE (XEXP (t, 0)) == ASHIFT
6132 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6133 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6134 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6135 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
6136 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6137 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6138 && ((nonzero_bits (f, GET_MODE (f))
6139 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
6142 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6143 extend_op = ZERO_EXTEND;
6144 m = GET_MODE (XEXP (t, 0));
6146 else if (GET_CODE (t) == ZERO_EXTEND
6147 && (GET_CODE (XEXP (t, 0)) == PLUS
6148 || GET_CODE (XEXP (t, 0)) == IOR
6149 || GET_CODE (XEXP (t, 0)) == XOR)
6150 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6151 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
6152 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6153 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6154 && ((nonzero_bits (f, GET_MODE (f))
6155 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
6158 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6159 extend_op = ZERO_EXTEND;
6160 m = GET_MODE (XEXP (t, 0));
6165 temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
6166 cond_op0, cond_op1),
6167 pc_rtx, pc_rtx, 0, 0);
6168 temp = simplify_gen_binary (MULT, m, temp,
6169 simplify_gen_binary (MULT, m, c1,
6171 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
6172 temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
6174 if (extend_op != UNKNOWN)
6175 temp = simplify_gen_unary (extend_op, mode, temp, m);
6181 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6182 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6183 negation of a single bit, we can convert this operation to a shift. We
6184 can actually do this more generally, but it doesn't seem worth it. */
6186 if (true_code == NE && XEXP (cond, 1) == const0_rtx
6187 && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6188 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
6189 && (i = exact_log2 (UINTVAL (true_rtx))) >= 0)
6190 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
6191 == GET_MODE_BITSIZE (mode))
6192 && (i = exact_log2 (-UINTVAL (true_rtx))) >= 0)))
6194 simplify_shift_const (NULL_RTX, ASHIFT, mode,
6195 gen_lowpart (mode, XEXP (cond, 0)), i);
6197 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
6198 if (true_code == NE && XEXP (cond, 1) == const0_rtx
6199 && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6200 && GET_MODE (XEXP (cond, 0)) == mode
6201 && (UINTVAL (true_rtx) & GET_MODE_MASK (mode))
6202 == nonzero_bits (XEXP (cond, 0), mode)
6203 && (i = exact_log2 (UINTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
6204 return XEXP (cond, 0);
6209 /* Simplify X, a SET expression. Return the new expression. */
6212 simplify_set (rtx x)
6214 rtx src = SET_SRC (x);
6215 rtx dest = SET_DEST (x);
6216 enum machine_mode mode
6217 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
6221 /* (set (pc) (return)) gets written as (return). */
6222 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
6225 /* Now that we know for sure which bits of SRC we are using, see if we can
6226 simplify the expression for the object knowing that we only need the
6229 if (GET_MODE_CLASS (mode) == MODE_INT
6230 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
6232 src = force_to_mode (src, mode, ~(unsigned HOST_WIDE_INT) 0, 0);
6233 SUBST (SET_SRC (x), src);
6236 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6237 the comparison result and try to simplify it unless we already have used
6238 undobuf.other_insn. */
6239 if ((GET_MODE_CLASS (mode) == MODE_CC
6240 || GET_CODE (src) == COMPARE
6242 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
6243 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
6244 && COMPARISON_P (*cc_use)
6245 && rtx_equal_p (XEXP (*cc_use, 0), dest))
6247 enum rtx_code old_code = GET_CODE (*cc_use);
6248 enum rtx_code new_code;
6250 int other_changed = 0;
6251 enum machine_mode compare_mode = GET_MODE (dest);
6253 if (GET_CODE (src) == COMPARE)
6254 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
6256 op0 = src, op1 = CONST0_RTX (GET_MODE (src));
6258 tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
6261 new_code = old_code;
6262 else if (!CONSTANT_P (tmp))
6264 new_code = GET_CODE (tmp);
6265 op0 = XEXP (tmp, 0);
6266 op1 = XEXP (tmp, 1);
6270 rtx pat = PATTERN (other_insn);
6271 undobuf.other_insn = other_insn;
6272 SUBST (*cc_use, tmp);
6274 /* Attempt to simplify CC user. */
6275 if (GET_CODE (pat) == SET)
6277 rtx new_rtx = simplify_rtx (SET_SRC (pat));
6278 if (new_rtx != NULL_RTX)
6279 SUBST (SET_SRC (pat), new_rtx);
6282 /* Convert X into a no-op move. */
6283 SUBST (SET_DEST (x), pc_rtx);
6284 SUBST (SET_SRC (x), pc_rtx);
6288 /* Simplify our comparison, if possible. */
6289 new_code = simplify_comparison (new_code, &op0, &op1);
6291 #ifdef SELECT_CC_MODE
6292 /* If this machine has CC modes other than CCmode, check to see if we
6293 need to use a different CC mode here. */
6294 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
6295 compare_mode = GET_MODE (op0);
6297 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
6300 /* If the mode changed, we have to change SET_DEST, the mode in the
6301 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6302 a hard register, just build new versions with the proper mode. If it
6303 is a pseudo, we lose unless it is only time we set the pseudo, in
6304 which case we can safely change its mode. */
6305 if (compare_mode != GET_MODE (dest))
6307 if (can_change_dest_mode (dest, 0, compare_mode))
6309 unsigned int regno = REGNO (dest);
6312 if (regno < FIRST_PSEUDO_REGISTER)
6313 new_dest = gen_rtx_REG (compare_mode, regno);
6316 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
6317 new_dest = regno_reg_rtx[regno];
6320 SUBST (SET_DEST (x), new_dest);
6321 SUBST (XEXP (*cc_use, 0), new_dest);
6328 #endif /* SELECT_CC_MODE */
6330 /* If the code changed, we have to build a new comparison in
6331 undobuf.other_insn. */
6332 if (new_code != old_code)
6334 int other_changed_previously = other_changed;
6335 unsigned HOST_WIDE_INT mask;
6336 rtx old_cc_use = *cc_use;
6338 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
6342 /* If the only change we made was to change an EQ into an NE or
6343 vice versa, OP0 has only one bit that might be nonzero, and OP1
6344 is zero, check if changing the user of the condition code will
6345 produce a valid insn. If it won't, we can keep the original code
6346 in that insn by surrounding our operation with an XOR. */
6348 if (((old_code == NE && new_code == EQ)
6349 || (old_code == EQ && new_code == NE))
6350 && ! other_changed_previously && op1 == const0_rtx
6351 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
6352 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
6354 rtx pat = PATTERN (other_insn), note = 0;
6356 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
6357 && ! check_asm_operands (pat)))
6359 *cc_use = old_cc_use;
6362 op0 = simplify_gen_binary (XOR, GET_MODE (op0),
6363 op0, GEN_INT (mask));
6369 undobuf.other_insn = other_insn;
6371 /* Otherwise, if we didn't previously have a COMPARE in the
6372 correct mode, we need one. */
6373 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
6375 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6378 else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
6380 SUBST (SET_SRC (x), op0);
6383 /* Otherwise, update the COMPARE if needed. */
6384 else if (XEXP (src, 0) != op0 || XEXP (src, 1) != op1)
6386 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6392 /* Get SET_SRC in a form where we have placed back any
6393 compound expressions. Then do the checks below. */
6394 src = make_compound_operation (src, SET);
6395 SUBST (SET_SRC (x), src);
6398 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6399 and X being a REG or (subreg (reg)), we may be able to convert this to
6400 (set (subreg:m2 x) (op)).
6402 We can always do this if M1 is narrower than M2 because that means that
6403 we only care about the low bits of the result.
6405 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6406 perform a narrower operation than requested since the high-order bits will
6407 be undefined. On machine where it is defined, this transformation is safe
6408 as long as M1 and M2 have the same number of words. */
6410 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6411 && !OBJECT_P (SUBREG_REG (src))
6412 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
6414 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
6415 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
6416 #ifndef WORD_REGISTER_OPERATIONS
6417 && (GET_MODE_SIZE (GET_MODE (src))
6418 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
6420 #ifdef CANNOT_CHANGE_MODE_CLASS
6421 && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
6422 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
6423 GET_MODE (SUBREG_REG (src)),
6427 || (GET_CODE (dest) == SUBREG
6428 && REG_P (SUBREG_REG (dest)))))
6430 SUBST (SET_DEST (x),
6431 gen_lowpart (GET_MODE (SUBREG_REG (src)),
6433 SUBST (SET_SRC (x), SUBREG_REG (src));
6435 src = SET_SRC (x), dest = SET_DEST (x);
6439 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6442 && GET_CODE (src) == SUBREG
6443 && subreg_lowpart_p (src)
6444 && (GET_MODE_BITSIZE (GET_MODE (src))
6445 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
6447 rtx inner = SUBREG_REG (src);
6448 enum machine_mode inner_mode = GET_MODE (inner);
6450 /* Here we make sure that we don't have a sign bit on. */
6451 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
6452 && (nonzero_bits (inner, inner_mode)
6453 < ((unsigned HOST_WIDE_INT) 1
6454 << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
6456 SUBST (SET_SRC (x), inner);
6462 #ifdef LOAD_EXTEND_OP
6463 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6464 would require a paradoxical subreg. Replace the subreg with a
6465 zero_extend to avoid the reload that would otherwise be required. */
6467 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6468 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src)))
6469 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
6470 && SUBREG_BYTE (src) == 0
6471 && (GET_MODE_SIZE (GET_MODE (src))
6472 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
6473 && MEM_P (SUBREG_REG (src)))
6476 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
6477 GET_MODE (src), SUBREG_REG (src)));
6483 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6484 are comparing an item known to be 0 or -1 against 0, use a logical
6485 operation instead. Check for one of the arms being an IOR of the other
6486 arm with some value. We compute three terms to be IOR'ed together. In
6487 practice, at most two will be nonzero. Then we do the IOR's. */
6489 if (GET_CODE (dest) != PC
6490 && GET_CODE (src) == IF_THEN_ELSE
6491 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
6492 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
6493 && XEXP (XEXP (src, 0), 1) == const0_rtx
6494 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
6495 #ifdef HAVE_conditional_move
6496 && ! can_conditionally_move_p (GET_MODE (src))
6498 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
6499 GET_MODE (XEXP (XEXP (src, 0), 0)))
6500 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
6501 && ! side_effects_p (src))
6503 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
6504 ? XEXP (src, 1) : XEXP (src, 2));
6505 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
6506 ? XEXP (src, 2) : XEXP (src, 1));
6507 rtx term1 = const0_rtx, term2, term3;
6509 if (GET_CODE (true_rtx) == IOR
6510 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
6511 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
6512 else if (GET_CODE (true_rtx) == IOR
6513 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
6514 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
6515 else if (GET_CODE (false_rtx) == IOR
6516 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
6517 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
6518 else if (GET_CODE (false_rtx) == IOR
6519 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
6520 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
6522 term2 = simplify_gen_binary (AND, GET_MODE (src),
6523 XEXP (XEXP (src, 0), 0), true_rtx);
6524 term3 = simplify_gen_binary (AND, GET_MODE (src),
6525 simplify_gen_unary (NOT, GET_MODE (src),
6526 XEXP (XEXP (src, 0), 0),
6531 simplify_gen_binary (IOR, GET_MODE (src),
6532 simplify_gen_binary (IOR, GET_MODE (src),
6539 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6540 whole thing fail. */
6541 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
6543 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
6546 /* Convert this into a field assignment operation, if possible. */
6547 return make_field_assignment (x);
6550 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6554 simplify_logical (rtx x)
6556 enum machine_mode mode = GET_MODE (x);
6557 rtx op0 = XEXP (x, 0);
6558 rtx op1 = XEXP (x, 1);
6560 switch (GET_CODE (x))
6563 /* We can call simplify_and_const_int only if we don't lose
6564 any (sign) bits when converting INTVAL (op1) to
6565 "unsigned HOST_WIDE_INT". */
6566 if (CONST_INT_P (op1)
6567 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
6568 || INTVAL (op1) > 0))
6570 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
6571 if (GET_CODE (x) != AND)
6578 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6579 apply the distributive law and then the inverse distributive
6580 law to see if things simplify. */
6581 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
6583 rtx result = distribute_and_simplify_rtx (x, 0);
6587 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
6589 rtx result = distribute_and_simplify_rtx (x, 1);
6596 /* If we have (ior (and A B) C), apply the distributive law and then
6597 the inverse distributive law to see if things simplify. */
6599 if (GET_CODE (op0) == AND)
6601 rtx result = distribute_and_simplify_rtx (x, 0);
6606 if (GET_CODE (op1) == AND)
6608 rtx result = distribute_and_simplify_rtx (x, 1);
6621 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6622 operations" because they can be replaced with two more basic operations.
6623 ZERO_EXTEND is also considered "compound" because it can be replaced with
6624 an AND operation, which is simpler, though only one operation.
6626 The function expand_compound_operation is called with an rtx expression
6627 and will convert it to the appropriate shifts and AND operations,
6628 simplifying at each stage.
6630 The function make_compound_operation is called to convert an expression
6631 consisting of shifts and ANDs into the equivalent compound expression.
6632 It is the inverse of this function, loosely speaking. */
6635 expand_compound_operation (rtx x)
6637 unsigned HOST_WIDE_INT pos = 0, len;
6639 unsigned int modewidth;
6642 switch (GET_CODE (x))
6647 /* We can't necessarily use a const_int for a multiword mode;
6648 it depends on implicitly extending the value.
6649 Since we don't know the right way to extend it,
6650 we can't tell whether the implicit way is right.
6652 Even for a mode that is no wider than a const_int,
6653 we can't win, because we need to sign extend one of its bits through
6654 the rest of it, and we don't know which bit. */
6655 if (CONST_INT_P (XEXP (x, 0)))
6658 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6659 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6660 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6661 reloaded. If not for that, MEM's would very rarely be safe.
6663 Reject MODEs bigger than a word, because we might not be able
6664 to reference a two-register group starting with an arbitrary register
6665 (and currently gen_lowpart might crash for a SUBREG). */
6667 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
6670 /* Reject MODEs that aren't scalar integers because turning vector
6671 or complex modes into shifts causes problems. */
6673 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6676 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
6677 /* If the inner object has VOIDmode (the only way this can happen
6678 is if it is an ASM_OPERANDS), we can't do anything since we don't
6679 know how much masking to do. */
6688 /* ... fall through ... */
6691 /* If the operand is a CLOBBER, just return it. */
6692 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
6695 if (!CONST_INT_P (XEXP (x, 1))
6696 || !CONST_INT_P (XEXP (x, 2))
6697 || GET_MODE (XEXP (x, 0)) == VOIDmode)
6700 /* Reject MODEs that aren't scalar integers because turning vector
6701 or complex modes into shifts causes problems. */
6703 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6706 len = INTVAL (XEXP (x, 1));
6707 pos = INTVAL (XEXP (x, 2));
6709 /* This should stay within the object being extracted, fail otherwise. */
6710 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
6713 if (BITS_BIG_ENDIAN)
6714 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
6721 /* Convert sign extension to zero extension, if we know that the high
6722 bit is not set, as this is easier to optimize. It will be converted
6723 back to cheaper alternative in make_extraction. */
6724 if (GET_CODE (x) == SIGN_EXTEND
6725 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6726 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6727 & ~(((unsigned HOST_WIDE_INT)
6728 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
6732 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
6733 rtx temp2 = expand_compound_operation (temp);
6735 /* Make sure this is a profitable operation. */
6736 if (rtx_cost (x, SET, optimize_this_for_speed_p)
6737 > rtx_cost (temp2, SET, optimize_this_for_speed_p))
6739 else if (rtx_cost (x, SET, optimize_this_for_speed_p)
6740 > rtx_cost (temp, SET, optimize_this_for_speed_p))
6746 /* We can optimize some special cases of ZERO_EXTEND. */
6747 if (GET_CODE (x) == ZERO_EXTEND)
6749 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6750 know that the last value didn't have any inappropriate bits
6752 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6753 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6754 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6755 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
6756 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6757 return XEXP (XEXP (x, 0), 0);
6759 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6760 if (GET_CODE (XEXP (x, 0)) == SUBREG
6761 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6762 && subreg_lowpart_p (XEXP (x, 0))
6763 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6764 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
6765 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6766 return SUBREG_REG (XEXP (x, 0));
6768 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6769 is a comparison and STORE_FLAG_VALUE permits. This is like
6770 the first case, but it works even when GET_MODE (x) is larger
6771 than HOST_WIDE_INT. */
6772 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6773 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6774 && COMPARISON_P (XEXP (XEXP (x, 0), 0))
6775 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6776 <= HOST_BITS_PER_WIDE_INT)
6777 && (STORE_FLAG_VALUE & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6778 return XEXP (XEXP (x, 0), 0);
6780 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6781 if (GET_CODE (XEXP (x, 0)) == SUBREG
6782 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6783 && subreg_lowpart_p (XEXP (x, 0))
6784 && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
6785 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6786 <= HOST_BITS_PER_WIDE_INT)
6787 && (STORE_FLAG_VALUE & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6788 return SUBREG_REG (XEXP (x, 0));
6792 /* If we reach here, we want to return a pair of shifts. The inner
6793 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6794 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6795 logical depending on the value of UNSIGNEDP.
6797 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6798 converted into an AND of a shift.
6800 We must check for the case where the left shift would have a negative
6801 count. This can happen in a case like (x >> 31) & 255 on machines
6802 that can't shift by a constant. On those machines, we would first
6803 combine the shift with the AND to produce a variable-position
6804 extraction. Then the constant of 31 would be substituted in
6805 to produce such a position. */
6807 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
6808 if (modewidth >= pos + len)
6810 enum machine_mode mode = GET_MODE (x);
6811 tem = gen_lowpart (mode, XEXP (x, 0));
6812 if (!tem || GET_CODE (tem) == CLOBBER)
6814 tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
6815 tem, modewidth - pos - len);
6816 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
6817 mode, tem, modewidth - len);
6819 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
6820 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
6821 simplify_shift_const (NULL_RTX, LSHIFTRT,
6824 ((unsigned HOST_WIDE_INT) 1 << len) - 1);
6826 /* Any other cases we can't handle. */
6829 /* If we couldn't do this for some reason, return the original
6831 if (GET_CODE (tem) == CLOBBER)
6837 /* X is a SET which contains an assignment of one object into
6838 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6839 or certain SUBREGS). If possible, convert it into a series of
6842 We half-heartedly support variable positions, but do not at all
6843 support variable lengths. */
6846 expand_field_assignment (const_rtx x)
6849 rtx pos; /* Always counts from low bit. */
6851 rtx mask, cleared, masked;
6852 enum machine_mode compute_mode;
6854 /* Loop until we find something we can't simplify. */
6857 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
6858 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
6860 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
6861 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
6862 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
6864 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
6865 && CONST_INT_P (XEXP (SET_DEST (x), 1)))
6867 inner = XEXP (SET_DEST (x), 0);
6868 len = INTVAL (XEXP (SET_DEST (x), 1));
6869 pos = XEXP (SET_DEST (x), 2);
6871 /* A constant position should stay within the width of INNER. */
6872 if (CONST_INT_P (pos)
6873 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
6876 if (BITS_BIG_ENDIAN)
6878 if (CONST_INT_P (pos))
6879 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
6881 else if (GET_CODE (pos) == MINUS
6882 && CONST_INT_P (XEXP (pos, 1))
6883 && (INTVAL (XEXP (pos, 1))
6884 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
6885 /* If position is ADJUST - X, new position is X. */
6886 pos = XEXP (pos, 0);
6888 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
6889 GEN_INT (GET_MODE_BITSIZE (
6896 /* A SUBREG between two modes that occupy the same numbers of words
6897 can be done by moving the SUBREG to the source. */
6898 else if (GET_CODE (SET_DEST (x)) == SUBREG
6899 /* We need SUBREGs to compute nonzero_bits properly. */
6900 && nonzero_sign_valid
6901 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
6902 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
6903 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
6904 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
6906 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
6908 (GET_MODE (SUBREG_REG (SET_DEST (x))),
6915 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6916 inner = SUBREG_REG (inner);
6918 compute_mode = GET_MODE (inner);
6920 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6921 if (! SCALAR_INT_MODE_P (compute_mode))
6923 enum machine_mode imode;
6925 /* Don't do anything for vector or complex integral types. */
6926 if (! FLOAT_MODE_P (compute_mode))
6929 /* Try to find an integral mode to pun with. */
6930 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
6931 if (imode == BLKmode)
6934 compute_mode = imode;
6935 inner = gen_lowpart (imode, inner);
6938 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6939 if (len >= HOST_BITS_PER_WIDE_INT)
6942 /* Now compute the equivalent expression. Make a copy of INNER
6943 for the SET_DEST in case it is a MEM into which we will substitute;
6944 we don't want shared RTL in that case. */
6945 mask = GEN_INT (((unsigned HOST_WIDE_INT) 1 << len) - 1);
6946 cleared = simplify_gen_binary (AND, compute_mode,
6947 simplify_gen_unary (NOT, compute_mode,
6948 simplify_gen_binary (ASHIFT,
6953 masked = simplify_gen_binary (ASHIFT, compute_mode,
6954 simplify_gen_binary (
6956 gen_lowpart (compute_mode, SET_SRC (x)),
6960 x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
6961 simplify_gen_binary (IOR, compute_mode,
6968 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6969 it is an RTX that represents a variable starting position; otherwise,
6970 POS is the (constant) starting bit position (counted from the LSB).
6972 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6975 IN_DEST is nonzero if this is a reference in the destination of a
6976 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6977 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6980 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6981 ZERO_EXTRACT should be built even for bits starting at bit 0.
6983 MODE is the desired mode of the result (if IN_DEST == 0).
6985 The result is an RTX for the extraction or NULL_RTX if the target
6989 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
6990 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
6991 int in_dest, int in_compare)
6993 /* This mode describes the size of the storage area
6994 to fetch the overall value from. Within that, we
6995 ignore the POS lowest bits, etc. */
6996 enum machine_mode is_mode = GET_MODE (inner);
6997 enum machine_mode inner_mode;
6998 enum machine_mode wanted_inner_mode;
6999 enum machine_mode wanted_inner_reg_mode = word_mode;
7000 enum machine_mode pos_mode = word_mode;
7001 enum machine_mode extraction_mode = word_mode;
7002 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
7004 rtx orig_pos_rtx = pos_rtx;
7005 HOST_WIDE_INT orig_pos;
7007 if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
7009 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7010 consider just the QI as the memory to extract from.
7011 The subreg adds or removes high bits; its mode is
7012 irrelevant to the meaning of this extraction,
7013 since POS and LEN count from the lsb. */
7014 if (MEM_P (SUBREG_REG (inner)))
7015 is_mode = GET_MODE (SUBREG_REG (inner));
7016 inner = SUBREG_REG (inner);
7018 else if (GET_CODE (inner) == ASHIFT
7019 && CONST_INT_P (XEXP (inner, 1))
7020 && pos_rtx == 0 && pos == 0
7021 && len > UINTVAL (XEXP (inner, 1)))
7023 /* We're extracting the least significant bits of an rtx
7024 (ashift X (const_int C)), where LEN > C. Extract the
7025 least significant (LEN - C) bits of X, giving an rtx
7026 whose mode is MODE, then shift it left C times. */
7027 new_rtx = make_extraction (mode, XEXP (inner, 0),
7028 0, 0, len - INTVAL (XEXP (inner, 1)),
7029 unsignedp, in_dest, in_compare);
7031 return gen_rtx_ASHIFT (mode, new_rtx, XEXP (inner, 1));
7034 inner_mode = GET_MODE (inner);
7036 if (pos_rtx && CONST_INT_P (pos_rtx))
7037 pos = INTVAL (pos_rtx), pos_rtx = 0;
7039 /* See if this can be done without an extraction. We never can if the
7040 width of the field is not the same as that of some integer mode. For
7041 registers, we can only avoid the extraction if the position is at the
7042 low-order bit and this is either not in the destination or we have the
7043 appropriate STRICT_LOW_PART operation available.
7045 For MEM, we can avoid an extract if the field starts on an appropriate
7046 boundary and we can change the mode of the memory reference. */
7048 if (tmode != BLKmode
7049 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
7051 && (inner_mode == tmode
7053 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
7054 GET_MODE_BITSIZE (inner_mode))
7055 || reg_truncated_to_mode (tmode, inner))
7058 && have_insn_for (STRICT_LOW_PART, tmode))))
7059 || (MEM_P (inner) && pos_rtx == 0
7061 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
7062 : BITS_PER_UNIT)) == 0
7063 /* We can't do this if we are widening INNER_MODE (it
7064 may not be aligned, for one thing). */
7065 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
7066 && (inner_mode == tmode
7067 || (! mode_dependent_address_p (XEXP (inner, 0))
7068 && ! MEM_VOLATILE_P (inner))))))
7070 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7071 field. If the original and current mode are the same, we need not
7072 adjust the offset. Otherwise, we do if bytes big endian.
7074 If INNER is not a MEM, get a piece consisting of just the field
7075 of interest (in this case POS % BITS_PER_WORD must be 0). */
7079 HOST_WIDE_INT offset;
7081 /* POS counts from lsb, but make OFFSET count in memory order. */
7082 if (BYTES_BIG_ENDIAN)
7083 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
7085 offset = pos / BITS_PER_UNIT;
7087 new_rtx = adjust_address_nv (inner, tmode, offset);
7089 else if (REG_P (inner))
7091 if (tmode != inner_mode)
7093 /* We can't call gen_lowpart in a DEST since we
7094 always want a SUBREG (see below) and it would sometimes
7095 return a new hard register. */
7098 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
7100 if (WORDS_BIG_ENDIAN
7101 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
7102 final_word = ((GET_MODE_SIZE (inner_mode)
7103 - GET_MODE_SIZE (tmode))
7104 / UNITS_PER_WORD) - final_word;
7106 final_word *= UNITS_PER_WORD;
7107 if (BYTES_BIG_ENDIAN &&
7108 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
7109 final_word += (GET_MODE_SIZE (inner_mode)
7110 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
7112 /* Avoid creating invalid subregs, for example when
7113 simplifying (x>>32)&255. */
7114 if (!validate_subreg (tmode, inner_mode, inner, final_word))
7117 new_rtx = gen_rtx_SUBREG (tmode, inner, final_word);
7120 new_rtx = gen_lowpart (tmode, inner);
7126 new_rtx = force_to_mode (inner, tmode,
7127 len >= HOST_BITS_PER_WIDE_INT
7128 ? ~(unsigned HOST_WIDE_INT) 0
7129 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7132 /* If this extraction is going into the destination of a SET,
7133 make a STRICT_LOW_PART unless we made a MEM. */
7136 return (MEM_P (new_rtx) ? new_rtx
7137 : (GET_CODE (new_rtx) != SUBREG
7138 ? gen_rtx_CLOBBER (tmode, const0_rtx)
7139 : gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx)));
7144 if (CONST_INT_P (new_rtx)
7145 || GET_CODE (new_rtx) == CONST_DOUBLE)
7146 return simplify_unary_operation (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7147 mode, new_rtx, tmode);
7149 /* If we know that no extraneous bits are set, and that the high
7150 bit is not set, convert the extraction to the cheaper of
7151 sign and zero extension, that are equivalent in these cases. */
7152 if (flag_expensive_optimizations
7153 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
7154 && ((nonzero_bits (new_rtx, tmode)
7155 & ~(((unsigned HOST_WIDE_INT)
7156 GET_MODE_MASK (tmode))
7160 rtx temp = gen_rtx_ZERO_EXTEND (mode, new_rtx);
7161 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new_rtx);
7163 /* Prefer ZERO_EXTENSION, since it gives more information to
7165 if (rtx_cost (temp, SET, optimize_this_for_speed_p)
7166 <= rtx_cost (temp1, SET, optimize_this_for_speed_p))
7171 /* Otherwise, sign- or zero-extend unless we already are in the
7174 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7178 /* Unless this is a COMPARE or we have a funny memory reference,
7179 don't do anything with zero-extending field extracts starting at
7180 the low-order bit since they are simple AND operations. */
7181 if (pos_rtx == 0 && pos == 0 && ! in_dest
7182 && ! in_compare && unsignedp)
7185 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7186 if the position is not a constant and the length is not 1. In all
7187 other cases, we would only be going outside our object in cases when
7188 an original shift would have been undefined. */
7190 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
7191 || (pos_rtx != 0 && len != 1)))
7194 /* Get the mode to use should INNER not be a MEM, the mode for the position,
7195 and the mode for the result. */
7196 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
7198 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
7199 pos_mode = mode_for_extraction (EP_insv, 2);
7200 extraction_mode = mode_for_extraction (EP_insv, 3);
7203 if (! in_dest && unsignedp
7204 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
7206 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
7207 pos_mode = mode_for_extraction (EP_extzv, 3);
7208 extraction_mode = mode_for_extraction (EP_extzv, 0);
7211 if (! in_dest && ! unsignedp
7212 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
7214 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
7215 pos_mode = mode_for_extraction (EP_extv, 3);
7216 extraction_mode = mode_for_extraction (EP_extv, 0);
7219 /* Never narrow an object, since that might not be safe. */
7221 if (mode != VOIDmode
7222 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
7223 extraction_mode = mode;
7225 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
7226 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
7227 pos_mode = GET_MODE (pos_rtx);
7229 /* If this is not from memory, the desired mode is the preferred mode
7230 for an extraction pattern's first input operand, or word_mode if there
7233 wanted_inner_mode = wanted_inner_reg_mode;
7236 /* Be careful not to go beyond the extracted object and maintain the
7237 natural alignment of the memory. */
7238 wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
7239 while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
7240 > GET_MODE_BITSIZE (wanted_inner_mode))
7242 wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
7243 gcc_assert (wanted_inner_mode != VOIDmode);
7246 /* If we have to change the mode of memory and cannot, the desired mode
7247 is EXTRACTION_MODE. */
7248 if (inner_mode != wanted_inner_mode
7249 && (mode_dependent_address_p (XEXP (inner, 0))
7250 || MEM_VOLATILE_P (inner)
7252 wanted_inner_mode = extraction_mode;
7257 if (BITS_BIG_ENDIAN)
7259 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7260 BITS_BIG_ENDIAN style. If position is constant, compute new
7261 position. Otherwise, build subtraction.
7262 Note that POS is relative to the mode of the original argument.
7263 If it's a MEM we need to recompute POS relative to that.
7264 However, if we're extracting from (or inserting into) a register,
7265 we want to recompute POS relative to wanted_inner_mode. */
7266 int width = (MEM_P (inner)
7267 ? GET_MODE_BITSIZE (is_mode)
7268 : GET_MODE_BITSIZE (wanted_inner_mode));
7271 pos = width - len - pos;
7274 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
7275 /* POS may be less than 0 now, but we check for that below.
7276 Note that it can only be less than 0 if !MEM_P (inner). */
7279 /* If INNER has a wider mode, and this is a constant extraction, try to
7280 make it smaller and adjust the byte to point to the byte containing
7282 if (wanted_inner_mode != VOIDmode
7283 && inner_mode != wanted_inner_mode
7285 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
7287 && ! mode_dependent_address_p (XEXP (inner, 0))
7288 && ! MEM_VOLATILE_P (inner))
7292 /* The computations below will be correct if the machine is big
7293 endian in both bits and bytes or little endian in bits and bytes.
7294 If it is mixed, we must adjust. */
7296 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7297 adjust OFFSET to compensate. */
7298 if (BYTES_BIG_ENDIAN
7299 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
7300 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
7302 /* We can now move to the desired byte. */
7303 offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
7304 * GET_MODE_SIZE (wanted_inner_mode);
7305 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
7307 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
7308 && is_mode != wanted_inner_mode)
7309 offset = (GET_MODE_SIZE (is_mode)
7310 - GET_MODE_SIZE (wanted_inner_mode) - offset);
7312 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
7315 /* If INNER is not memory, get it into the proper mode. If we are changing
7316 its mode, POS must be a constant and smaller than the size of the new
7318 else if (!MEM_P (inner))
7320 /* On the LHS, don't create paradoxical subregs implicitely truncating
7321 the register unless TRULY_NOOP_TRUNCATION. */
7323 && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE (inner)),
7324 GET_MODE_BITSIZE (wanted_inner_mode)))
7327 if (GET_MODE (inner) != wanted_inner_mode
7329 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
7335 inner = force_to_mode (inner, wanted_inner_mode,
7337 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
7338 ? ~(unsigned HOST_WIDE_INT) 0
7339 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
7344 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7345 have to zero extend. Otherwise, we can just use a SUBREG. */
7347 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
7349 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
7351 /* If we know that no extraneous bits are set, and that the high
7352 bit is not set, convert extraction to cheaper one - either
7353 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7355 if (flag_expensive_optimizations
7356 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
7357 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
7358 & ~(((unsigned HOST_WIDE_INT)
7359 GET_MODE_MASK (GET_MODE (pos_rtx)))
7363 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
7365 /* Prefer ZERO_EXTENSION, since it gives more information to
7367 if (rtx_cost (temp1, SET, optimize_this_for_speed_p)
7368 < rtx_cost (temp, SET, optimize_this_for_speed_p))
7373 else if (pos_rtx != 0
7374 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
7375 pos_rtx = gen_lowpart (pos_mode, pos_rtx);
7377 /* Make POS_RTX unless we already have it and it is correct. If we don't
7378 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7380 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
7381 pos_rtx = orig_pos_rtx;
7383 else if (pos_rtx == 0)
7384 pos_rtx = GEN_INT (pos);
7386 /* Make the required operation. See if we can use existing rtx. */
7387 new_rtx = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
7388 extraction_mode, inner, GEN_INT (len), pos_rtx);
7390 new_rtx = gen_lowpart (mode, new_rtx);
7395 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7396 with any other operations in X. Return X without that shift if so. */
7399 extract_left_shift (rtx x, int count)
7401 enum rtx_code code = GET_CODE (x);
7402 enum machine_mode mode = GET_MODE (x);
7408 /* This is the shift itself. If it is wide enough, we will return
7409 either the value being shifted if the shift count is equal to
7410 COUNT or a shift for the difference. */
7411 if (CONST_INT_P (XEXP (x, 1))
7412 && INTVAL (XEXP (x, 1)) >= count)
7413 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
7414 INTVAL (XEXP (x, 1)) - count);
7418 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7419 return simplify_gen_unary (code, mode, tem, mode);
7423 case PLUS: case IOR: case XOR: case AND:
7424 /* If we can safely shift this constant and we find the inner shift,
7425 make a new operation. */
7426 if (CONST_INT_P (XEXP (x, 1))
7427 && (UINTVAL (XEXP (x, 1))
7428 & ((((unsigned HOST_WIDE_INT) 1 << count)) - 1)) == 0
7429 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7430 return simplify_gen_binary (code, mode, tem,
7431 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
7442 /* Look at the expression rooted at X. Look for expressions
7443 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7444 Form these expressions.
7446 Return the new rtx, usually just X.
7448 Also, for machines like the VAX that don't have logical shift insns,
7449 try to convert logical to arithmetic shift operations in cases where
7450 they are equivalent. This undoes the canonicalizations to logical
7451 shifts done elsewhere.
7453 We try, as much as possible, to re-use rtl expressions to save memory.
7455 IN_CODE says what kind of expression we are processing. Normally, it is
7456 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
7457 being kludges), it is MEM. When processing the arguments of a comparison
7458 or a COMPARE against zero, it is COMPARE. */
7461 make_compound_operation (rtx x, enum rtx_code in_code)
7463 enum rtx_code code = GET_CODE (x);
7464 enum machine_mode mode = GET_MODE (x);
7465 int mode_width = GET_MODE_BITSIZE (mode);
7467 enum rtx_code next_code;
7473 /* Select the code to be used in recursive calls. Once we are inside an
7474 address, we stay there. If we have a comparison, set to COMPARE,
7475 but once inside, go back to our default of SET. */
7477 next_code = (code == MEM ? MEM
7478 : ((code == PLUS || code == MINUS)
7479 && SCALAR_INT_MODE_P (mode)) ? MEM
7480 : ((code == COMPARE || COMPARISON_P (x))
7481 && XEXP (x, 1) == const0_rtx) ? COMPARE
7482 : in_code == COMPARE ? SET : in_code);
7484 /* Process depending on the code of this operation. If NEW is set
7485 nonzero, it will be returned. */
7490 /* Convert shifts by constants into multiplications if inside
7492 if (in_code == MEM && CONST_INT_P (XEXP (x, 1))
7493 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7494 && INTVAL (XEXP (x, 1)) >= 0
7495 && SCALAR_INT_MODE_P (mode))
7497 HOST_WIDE_INT count = INTVAL (XEXP (x, 1));
7498 HOST_WIDE_INT multval = (HOST_WIDE_INT) 1 << count;
7500 new_rtx = make_compound_operation (XEXP (x, 0), next_code);
7501 if (GET_CODE (new_rtx) == NEG)
7503 new_rtx = XEXP (new_rtx, 0);
7506 multval = trunc_int_for_mode (multval, mode);
7507 new_rtx = gen_rtx_MULT (mode, new_rtx, GEN_INT (multval));
7514 lhs = make_compound_operation (lhs, next_code);
7515 rhs = make_compound_operation (rhs, next_code);
7516 if (GET_CODE (lhs) == MULT && GET_CODE (XEXP (lhs, 0)) == NEG
7517 && SCALAR_INT_MODE_P (mode))
7519 tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (lhs, 0), 0),
7521 new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
7523 else if (GET_CODE (lhs) == MULT
7524 && (CONST_INT_P (XEXP (lhs, 1)) && INTVAL (XEXP (lhs, 1)) < 0))
7526 tem = simplify_gen_binary (MULT, mode, XEXP (lhs, 0),
7527 simplify_gen_unary (NEG, mode,
7530 new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
7534 SUBST (XEXP (x, 0), lhs);
7535 SUBST (XEXP (x, 1), rhs);
7538 x = gen_lowpart (mode, new_rtx);
7544 lhs = make_compound_operation (lhs, next_code);
7545 rhs = make_compound_operation (rhs, next_code);
7546 if (GET_CODE (rhs) == MULT && GET_CODE (XEXP (rhs, 0)) == NEG
7547 && SCALAR_INT_MODE_P (mode))
7549 tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (rhs, 0), 0),
7551 new_rtx = simplify_gen_binary (PLUS, mode, tem, lhs);
7553 else if (GET_CODE (rhs) == MULT
7554 && (CONST_INT_P (XEXP (rhs, 1)) && INTVAL (XEXP (rhs, 1)) < 0))
7556 tem = simplify_gen_binary (MULT, mode, XEXP (rhs, 0),
7557 simplify_gen_unary (NEG, mode,
7560 new_rtx = simplify_gen_binary (PLUS, mode, tem, lhs);
7564 SUBST (XEXP (x, 0), lhs);
7565 SUBST (XEXP (x, 1), rhs);
7568 return gen_lowpart (mode, new_rtx);
7571 /* If the second operand is not a constant, we can't do anything
7573 if (!CONST_INT_P (XEXP (x, 1)))
7576 /* If the constant is a power of two minus one and the first operand
7577 is a logical right shift, make an extraction. */
7578 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7579 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7581 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7582 new_rtx = make_extraction (mode, new_rtx, 0, XEXP (XEXP (x, 0), 1), i, 1,
7583 0, in_code == COMPARE);
7586 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7587 else if (GET_CODE (XEXP (x, 0)) == SUBREG
7588 && subreg_lowpart_p (XEXP (x, 0))
7589 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
7590 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7592 new_rtx = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
7594 new_rtx = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new_rtx, 0,
7595 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
7596 0, in_code == COMPARE);
7598 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7599 else if ((GET_CODE (XEXP (x, 0)) == XOR
7600 || GET_CODE (XEXP (x, 0)) == IOR)
7601 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
7602 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
7603 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7605 /* Apply the distributive law, and then try to make extractions. */
7606 new_rtx = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
7607 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
7609 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
7611 new_rtx = make_compound_operation (new_rtx, in_code);
7614 /* If we are have (and (rotate X C) M) and C is larger than the number
7615 of bits in M, this is an extraction. */
7617 else if (GET_CODE (XEXP (x, 0)) == ROTATE
7618 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7619 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0
7620 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
7622 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7623 new_rtx = make_extraction (mode, new_rtx,
7624 (GET_MODE_BITSIZE (mode)
7625 - INTVAL (XEXP (XEXP (x, 0), 1))),
7626 NULL_RTX, i, 1, 0, in_code == COMPARE);
7629 /* On machines without logical shifts, if the operand of the AND is
7630 a logical shift and our mask turns off all the propagated sign
7631 bits, we can replace the logical shift with an arithmetic shift. */
7632 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7633 && !have_insn_for (LSHIFTRT, mode)
7634 && have_insn_for (ASHIFTRT, mode)
7635 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7636 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7637 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7638 && mode_width <= HOST_BITS_PER_WIDE_INT)
7640 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
7642 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
7643 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
7645 gen_rtx_ASHIFTRT (mode,
7646 make_compound_operation
7647 (XEXP (XEXP (x, 0), 0), next_code),
7648 XEXP (XEXP (x, 0), 1)));
7651 /* If the constant is one less than a power of two, this might be
7652 representable by an extraction even if no shift is present.
7653 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7654 we are in a COMPARE. */
7655 else if ((i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7656 new_rtx = make_extraction (mode,
7657 make_compound_operation (XEXP (x, 0),
7659 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
7661 /* If we are in a comparison and this is an AND with a power of two,
7662 convert this into the appropriate bit extract. */
7663 else if (in_code == COMPARE
7664 && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0)
7665 new_rtx = make_extraction (mode,
7666 make_compound_operation (XEXP (x, 0),
7668 i, NULL_RTX, 1, 1, 0, 1);
7673 /* If the sign bit is known to be zero, replace this with an
7674 arithmetic shift. */
7675 if (have_insn_for (ASHIFTRT, mode)
7676 && ! have_insn_for (LSHIFTRT, mode)
7677 && mode_width <= HOST_BITS_PER_WIDE_INT
7678 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
7680 new_rtx = gen_rtx_ASHIFTRT (mode,
7681 make_compound_operation (XEXP (x, 0),
7687 /* ... fall through ... */
7693 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7694 this is a SIGN_EXTRACT. */
7695 if (CONST_INT_P (rhs)
7696 && GET_CODE (lhs) == ASHIFT
7697 && CONST_INT_P (XEXP (lhs, 1))
7698 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))
7699 && INTVAL (rhs) < mode_width)
7701 new_rtx = make_compound_operation (XEXP (lhs, 0), next_code);
7702 new_rtx = make_extraction (mode, new_rtx,
7703 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
7704 NULL_RTX, mode_width - INTVAL (rhs),
7705 code == LSHIFTRT, 0, in_code == COMPARE);
7709 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7710 If so, try to merge the shifts into a SIGN_EXTEND. We could
7711 also do this for some cases of SIGN_EXTRACT, but it doesn't
7712 seem worth the effort; the case checked for occurs on Alpha. */
7715 && ! (GET_CODE (lhs) == SUBREG
7716 && (OBJECT_P (SUBREG_REG (lhs))))
7717 && CONST_INT_P (rhs)
7718 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
7719 && INTVAL (rhs) < mode_width
7720 && (new_rtx = extract_left_shift (lhs, INTVAL (rhs))) != 0)
7721 new_rtx = make_extraction (mode, make_compound_operation (new_rtx, next_code),
7722 0, NULL_RTX, mode_width - INTVAL (rhs),
7723 code == LSHIFTRT, 0, in_code == COMPARE);
7728 /* Call ourselves recursively on the inner expression. If we are
7729 narrowing the object and it has a different RTL code from
7730 what it originally did, do this SUBREG as a force_to_mode. */
7732 rtx inner = SUBREG_REG (x), simplified;
7734 tem = make_compound_operation (inner, in_code);
7737 = simplify_subreg (mode, tem, GET_MODE (inner), SUBREG_BYTE (x));
7741 if (GET_CODE (tem) != GET_CODE (inner)
7742 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (inner))
7743 && subreg_lowpart_p (x))
7746 = force_to_mode (tem, mode, ~(unsigned HOST_WIDE_INT) 0, 0);
7748 /* If we have something other than a SUBREG, we might have
7749 done an expansion, so rerun ourselves. */
7750 if (GET_CODE (newer) != SUBREG)
7751 newer = make_compound_operation (newer, in_code);
7753 /* force_to_mode can expand compounds. If it just re-expanded the
7754 compound, use gen_lowpart to convert to the desired mode. */
7755 if (rtx_equal_p (newer, x)
7756 /* Likewise if it re-expanded the compound only partially.
7757 This happens for SUBREG of ZERO_EXTRACT if they extract
7758 the same number of bits. */
7759 || (GET_CODE (newer) == SUBREG
7760 && (GET_CODE (SUBREG_REG (newer)) == LSHIFTRT
7761 || GET_CODE (SUBREG_REG (newer)) == ASHIFTRT)
7762 && GET_CODE (inner) == AND
7763 && rtx_equal_p (SUBREG_REG (newer), XEXP (inner, 0))))
7764 return gen_lowpart (GET_MODE (x), tem);
7780 x = gen_lowpart (mode, new_rtx);
7781 code = GET_CODE (x);
7784 /* Now recursively process each operand of this operation. */
7785 fmt = GET_RTX_FORMAT (code);
7786 for (i = 0; i < GET_RTX_LENGTH (code); i++)
7789 new_rtx = make_compound_operation (XEXP (x, i), next_code);
7790 SUBST (XEXP (x, i), new_rtx);
7792 else if (fmt[i] == 'E')
7793 for (j = 0; j < XVECLEN (x, i); j++)
7795 new_rtx = make_compound_operation (XVECEXP (x, i, j), next_code);
7796 SUBST (XVECEXP (x, i, j), new_rtx);
7800 /* If this is a commutative operation, the changes to the operands
7801 may have made it noncanonical. */
7802 if (COMMUTATIVE_ARITH_P (x)
7803 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
7806 SUBST (XEXP (x, 0), XEXP (x, 1));
7807 SUBST (XEXP (x, 1), tem);
7813 /* Given M see if it is a value that would select a field of bits
7814 within an item, but not the entire word. Return -1 if not.
7815 Otherwise, return the starting position of the field, where 0 is the
7818 *PLEN is set to the length of the field. */
7821 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
7823 /* Get the bit number of the first 1 bit from the right, -1 if none. */
7824 int pos = m ? ctz_hwi (m) : -1;
7828 /* Now shift off the low-order zero bits and see if we have a
7829 power of two minus 1. */
7830 len = exact_log2 ((m >> pos) + 1);
7839 /* If X refers to a register that equals REG in value, replace these
7840 references with REG. */
7842 canon_reg_for_combine (rtx x, rtx reg)
7849 enum rtx_code code = GET_CODE (x);
7850 switch (GET_RTX_CLASS (code))
7853 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7854 if (op0 != XEXP (x, 0))
7855 return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
7860 case RTX_COMM_ARITH:
7861 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7862 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7863 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7864 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
7868 case RTX_COMM_COMPARE:
7869 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7870 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7871 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7872 return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
7873 GET_MODE (op0), op0, op1);
7877 case RTX_BITFIELD_OPS:
7878 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7879 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7880 op2 = canon_reg_for_combine (XEXP (x, 2), reg);
7881 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
7882 return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
7883 GET_MODE (op0), op0, op1, op2);
7888 if (rtx_equal_p (get_last_value (reg), x)
7889 || rtx_equal_p (reg, get_last_value (x)))
7898 fmt = GET_RTX_FORMAT (code);
7900 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7903 rtx op = canon_reg_for_combine (XEXP (x, i), reg);
7904 if (op != XEXP (x, i))
7914 else if (fmt[i] == 'E')
7917 for (j = 0; j < XVECLEN (x, i); j++)
7919 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
7920 if (op != XVECEXP (x, i, j))
7927 XVECEXP (x, i, j) = op;
7938 /* Return X converted to MODE. If the value is already truncated to
7939 MODE we can just return a subreg even though in the general case we
7940 would need an explicit truncation. */
7943 gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
7945 if (!CONST_INT_P (x)
7946 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
7947 && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
7948 GET_MODE_BITSIZE (GET_MODE (x)))
7949 && !(REG_P (x) && reg_truncated_to_mode (mode, x)))
7951 /* Bit-cast X into an integer mode. */
7952 if (!SCALAR_INT_MODE_P (GET_MODE (x)))
7953 x = gen_lowpart (int_mode_for_mode (GET_MODE (x)), x);
7954 x = simplify_gen_unary (TRUNCATE, int_mode_for_mode (mode),
7958 return gen_lowpart (mode, x);
7961 /* See if X can be simplified knowing that we will only refer to it in
7962 MODE and will only refer to those bits that are nonzero in MASK.
7963 If other bits are being computed or if masking operations are done
7964 that select a superset of the bits in MASK, they can sometimes be
7967 Return a possibly simplified expression, but always convert X to
7968 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
7970 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
7971 are all off in X. This is used when X will be complemented, by either
7972 NOT, NEG, or XOR. */
7975 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
7978 enum rtx_code code = GET_CODE (x);
7979 int next_select = just_select || code == XOR || code == NOT || code == NEG;
7980 enum machine_mode op_mode;
7981 unsigned HOST_WIDE_INT fuller_mask, nonzero;
7984 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
7985 code below will do the wrong thing since the mode of such an
7986 expression is VOIDmode.
7988 Also do nothing if X is a CLOBBER; this can happen if X was
7989 the return value from a call to gen_lowpart. */
7990 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
7993 /* We want to perform the operation is its present mode unless we know
7994 that the operation is valid in MODE, in which case we do the operation
7996 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
7997 && have_insn_for (code, mode))
7998 ? mode : GET_MODE (x));
8000 /* It is not valid to do a right-shift in a narrower mode
8001 than the one it came in with. */
8002 if ((code == LSHIFTRT || code == ASHIFTRT)
8003 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
8004 op_mode = GET_MODE (x);
8006 /* Truncate MASK to fit OP_MODE. */
8008 mask &= GET_MODE_MASK (op_mode);
8010 /* When we have an arithmetic operation, or a shift whose count we
8011 do not know, we need to assume that all bits up to the highest-order
8012 bit in MASK will be needed. This is how we form such a mask. */
8013 if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
8014 fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
8016 fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
8019 /* Determine what bits of X are guaranteed to be (non)zero. */
8020 nonzero = nonzero_bits (x, mode);
8022 /* If none of the bits in X are needed, return a zero. */
8023 if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
8026 /* If X is a CONST_INT, return a new one. Do this here since the
8027 test below will fail. */
8028 if (CONST_INT_P (x))
8030 if (SCALAR_INT_MODE_P (mode))
8031 return gen_int_mode (INTVAL (x) & mask, mode);
8034 x = GEN_INT (INTVAL (x) & mask);
8035 return gen_lowpart_common (mode, x);
8039 /* If X is narrower than MODE and we want all the bits in X's mode, just
8040 get X in the proper mode. */
8041 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
8042 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
8043 return gen_lowpart (mode, x);
8045 /* We can ignore the effect of a SUBREG if it narrows the mode or
8046 if the constant masks to zero all the bits the mode doesn't have. */
8047 if (GET_CODE (x) == SUBREG
8048 && subreg_lowpart_p (x)
8049 && ((GET_MODE_SIZE (GET_MODE (x))
8050 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8052 & GET_MODE_MASK (GET_MODE (x))
8053 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
8054 return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
8056 /* The arithmetic simplifications here only work for scalar integer modes. */
8057 if (!SCALAR_INT_MODE_P (mode) || !SCALAR_INT_MODE_P (GET_MODE (x)))
8058 return gen_lowpart_or_truncate (mode, x);
8063 /* If X is a (clobber (const_int)), return it since we know we are
8064 generating something that won't match. */
8071 x = expand_compound_operation (x);
8072 if (GET_CODE (x) != code)
8073 return force_to_mode (x, mode, mask, next_select);
8077 /* Similarly for a truncate. */
8078 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8081 /* If this is an AND with a constant, convert it into an AND
8082 whose constant is the AND of that constant with MASK. If it
8083 remains an AND of MASK, delete it since it is redundant. */
8085 if (CONST_INT_P (XEXP (x, 1)))
8087 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
8088 mask & INTVAL (XEXP (x, 1)));
8090 /* If X is still an AND, see if it is an AND with a mask that
8091 is just some low-order bits. If so, and it is MASK, we don't
8094 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8095 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
8099 /* If it remains an AND, try making another AND with the bits
8100 in the mode mask that aren't in MASK turned on. If the
8101 constant in the AND is wide enough, this might make a
8102 cheaper constant. */
8104 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8105 && GET_MODE_MASK (GET_MODE (x)) != mask
8106 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
8108 unsigned HOST_WIDE_INT cval
8109 = UINTVAL (XEXP (x, 1))
8110 | (GET_MODE_MASK (GET_MODE (x)) & ~mask);
8111 int width = GET_MODE_BITSIZE (GET_MODE (x));
8114 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
8115 number, sign extend it. */
8116 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
8117 && (cval & ((unsigned HOST_WIDE_INT) 1 << (width - 1))) != 0)
8118 cval |= (unsigned HOST_WIDE_INT) -1 << width;
8120 y = simplify_gen_binary (AND, GET_MODE (x),
8121 XEXP (x, 0), GEN_INT (cval));
8122 if (rtx_cost (y, SET, optimize_this_for_speed_p)
8123 < rtx_cost (x, SET, optimize_this_for_speed_p))
8133 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8134 low-order bits (as in an alignment operation) and FOO is already
8135 aligned to that boundary, mask C1 to that boundary as well.
8136 This may eliminate that PLUS and, later, the AND. */
8139 unsigned int width = GET_MODE_BITSIZE (mode);
8140 unsigned HOST_WIDE_INT smask = mask;
8142 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8143 number, sign extend it. */
8145 if (width < HOST_BITS_PER_WIDE_INT
8146 && (smask & ((unsigned HOST_WIDE_INT) 1 << (width - 1))) != 0)
8147 smask |= (unsigned HOST_WIDE_INT) (-1) << width;
8149 if (CONST_INT_P (XEXP (x, 1))
8150 && exact_log2 (- smask) >= 0
8151 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
8152 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
8153 return force_to_mode (plus_constant (XEXP (x, 0),
8154 (INTVAL (XEXP (x, 1)) & smask)),
8155 mode, smask, next_select);
8158 /* ... fall through ... */
8161 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8162 most significant bit in MASK since carries from those bits will
8163 affect the bits we are interested in. */
8168 /* If X is (minus C Y) where C's least set bit is larger than any bit
8169 in the mask, then we may replace with (neg Y). */
8170 if (CONST_INT_P (XEXP (x, 0))
8171 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
8172 & -INTVAL (XEXP (x, 0))))
8175 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
8177 return force_to_mode (x, mode, mask, next_select);
8180 /* Similarly, if C contains every bit in the fuller_mask, then we may
8181 replace with (not Y). */
8182 if (CONST_INT_P (XEXP (x, 0))
8183 && ((UINTVAL (XEXP (x, 0)) | fuller_mask) == UINTVAL (XEXP (x, 0))))
8185 x = simplify_gen_unary (NOT, GET_MODE (x),
8186 XEXP (x, 1), GET_MODE (x));
8187 return force_to_mode (x, mode, mask, next_select);
8195 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8196 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8197 operation which may be a bitfield extraction. Ensure that the
8198 constant we form is not wider than the mode of X. */
8200 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8201 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8202 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8203 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
8204 && CONST_INT_P (XEXP (x, 1))
8205 && ((INTVAL (XEXP (XEXP (x, 0), 1))
8206 + floor_log2 (INTVAL (XEXP (x, 1))))
8207 < GET_MODE_BITSIZE (GET_MODE (x)))
8208 && (UINTVAL (XEXP (x, 1))
8209 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
8211 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
8212 << INTVAL (XEXP (XEXP (x, 0), 1)));
8213 temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
8214 XEXP (XEXP (x, 0), 0), temp);
8215 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
8216 XEXP (XEXP (x, 0), 1));
8217 return force_to_mode (x, mode, mask, next_select);
8221 /* For most binary operations, just propagate into the operation and
8222 change the mode if we have an operation of that mode. */
8224 op0 = force_to_mode (XEXP (x, 0), mode, mask, next_select);
8225 op1 = force_to_mode (XEXP (x, 1), mode, mask, next_select);
8227 /* If we ended up truncating both operands, truncate the result of the
8228 operation instead. */
8229 if (GET_CODE (op0) == TRUNCATE
8230 && GET_CODE (op1) == TRUNCATE)
8232 op0 = XEXP (op0, 0);
8233 op1 = XEXP (op1, 0);
8236 op0 = gen_lowpart_or_truncate (op_mode, op0);
8237 op1 = gen_lowpart_or_truncate (op_mode, op1);
8239 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8240 x = simplify_gen_binary (code, op_mode, op0, op1);
8244 /* For left shifts, do the same, but just for the first operand.
8245 However, we cannot do anything with shifts where we cannot
8246 guarantee that the counts are smaller than the size of the mode
8247 because such a count will have a different meaning in a
8250 if (! (CONST_INT_P (XEXP (x, 1))
8251 && INTVAL (XEXP (x, 1)) >= 0
8252 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
8253 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
8254 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
8255 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
8258 /* If the shift count is a constant and we can do arithmetic in
8259 the mode of the shift, refine which bits we need. Otherwise, use the
8260 conservative form of the mask. */
8261 if (CONST_INT_P (XEXP (x, 1))
8262 && INTVAL (XEXP (x, 1)) >= 0
8263 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
8264 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
8265 mask >>= INTVAL (XEXP (x, 1));
8269 op0 = gen_lowpart_or_truncate (op_mode,
8270 force_to_mode (XEXP (x, 0), op_mode,
8271 mask, next_select));
8273 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8274 x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
8278 /* Here we can only do something if the shift count is a constant,
8279 this shift constant is valid for the host, and we can do arithmetic
8282 if (CONST_INT_P (XEXP (x, 1))
8283 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
8284 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
8286 rtx inner = XEXP (x, 0);
8287 unsigned HOST_WIDE_INT inner_mask;
8289 /* Select the mask of the bits we need for the shift operand. */
8290 inner_mask = mask << INTVAL (XEXP (x, 1));
8292 /* We can only change the mode of the shift if we can do arithmetic
8293 in the mode of the shift and INNER_MASK is no wider than the
8294 width of X's mode. */
8295 if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
8296 op_mode = GET_MODE (x);
8298 inner = force_to_mode (inner, op_mode, inner_mask, next_select);
8300 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
8301 x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
8304 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8305 shift and AND produces only copies of the sign bit (C2 is one less
8306 than a power of two), we can do this with just a shift. */
8308 if (GET_CODE (x) == LSHIFTRT
8309 && CONST_INT_P (XEXP (x, 1))
8310 /* The shift puts one of the sign bit copies in the least significant
8312 && ((INTVAL (XEXP (x, 1))
8313 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
8314 >= GET_MODE_BITSIZE (GET_MODE (x)))
8315 && exact_log2 (mask + 1) >= 0
8316 /* Number of bits left after the shift must be more than the mask
8318 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
8319 <= GET_MODE_BITSIZE (GET_MODE (x)))
8320 /* Must be more sign bit copies than the mask needs. */
8321 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
8322 >= exact_log2 (mask + 1)))
8323 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
8324 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
8325 - exact_log2 (mask + 1)));
8330 /* If we are just looking for the sign bit, we don't need this shift at
8331 all, even if it has a variable count. */
8332 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
8333 && (mask == ((unsigned HOST_WIDE_INT) 1
8334 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8335 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8337 /* If this is a shift by a constant, get a mask that contains those bits
8338 that are not copies of the sign bit. We then have two cases: If
8339 MASK only includes those bits, this can be a logical shift, which may
8340 allow simplifications. If MASK is a single-bit field not within
8341 those bits, we are requesting a copy of the sign bit and hence can
8342 shift the sign bit to the appropriate location. */
8344 if (CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) >= 0
8345 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8349 /* If the considered data is wider than HOST_WIDE_INT, we can't
8350 represent a mask for all its bits in a single scalar.
8351 But we only care about the lower bits, so calculate these. */
8353 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
8355 nonzero = ~(unsigned HOST_WIDE_INT) 0;
8357 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8358 is the number of bits a full-width mask would have set.
8359 We need only shift if these are fewer than nonzero can
8360 hold. If not, we must keep all bits set in nonzero. */
8362 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8363 < HOST_BITS_PER_WIDE_INT)
8364 nonzero >>= INTVAL (XEXP (x, 1))
8365 + HOST_BITS_PER_WIDE_INT
8366 - GET_MODE_BITSIZE (GET_MODE (x)) ;
8370 nonzero = GET_MODE_MASK (GET_MODE (x));
8371 nonzero >>= INTVAL (XEXP (x, 1));
8374 if ((mask & ~nonzero) == 0)
8376 x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
8377 XEXP (x, 0), INTVAL (XEXP (x, 1)));
8378 if (GET_CODE (x) != ASHIFTRT)
8379 return force_to_mode (x, mode, mask, next_select);
8382 else if ((i = exact_log2 (mask)) >= 0)
8384 x = simplify_shift_const
8385 (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
8386 GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
8388 if (GET_CODE (x) != ASHIFTRT)
8389 return force_to_mode (x, mode, mask, next_select);
8393 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8394 even if the shift count isn't a constant. */
8396 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8397 XEXP (x, 0), XEXP (x, 1));
8401 /* If this is a zero- or sign-extension operation that just affects bits
8402 we don't care about, remove it. Be sure the call above returned
8403 something that is still a shift. */
8405 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
8406 && CONST_INT_P (XEXP (x, 1))
8407 && INTVAL (XEXP (x, 1)) >= 0
8408 && (INTVAL (XEXP (x, 1))
8409 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
8410 && GET_CODE (XEXP (x, 0)) == ASHIFT
8411 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
8412 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
8419 /* If the shift count is constant and we can do computations
8420 in the mode of X, compute where the bits we care about are.
8421 Otherwise, we can't do anything. Don't change the mode of
8422 the shift or propagate MODE into the shift, though. */
8423 if (CONST_INT_P (XEXP (x, 1))
8424 && INTVAL (XEXP (x, 1)) >= 0)
8426 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
8427 GET_MODE (x), GEN_INT (mask),
8429 if (temp && CONST_INT_P (temp))
8431 force_to_mode (XEXP (x, 0), GET_MODE (x),
8432 INTVAL (temp), next_select));
8437 /* If we just want the low-order bit, the NEG isn't needed since it
8438 won't change the low-order bit. */
8440 return force_to_mode (XEXP (x, 0), mode, mask, just_select);
8442 /* We need any bits less significant than the most significant bit in
8443 MASK since carries from those bits will affect the bits we are
8449 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8450 same as the XOR case above. Ensure that the constant we form is not
8451 wider than the mode of X. */
8453 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8454 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8455 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8456 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
8457 < GET_MODE_BITSIZE (GET_MODE (x)))
8458 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
8460 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
8462 temp = simplify_gen_binary (XOR, GET_MODE (x),
8463 XEXP (XEXP (x, 0), 0), temp);
8464 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8465 temp, XEXP (XEXP (x, 0), 1));
8467 return force_to_mode (x, mode, mask, next_select);
8470 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8471 use the full mask inside the NOT. */
8475 op0 = gen_lowpart_or_truncate (op_mode,
8476 force_to_mode (XEXP (x, 0), mode, mask,
8478 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8479 x = simplify_gen_unary (code, op_mode, op0, op_mode);
8483 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8484 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8485 which is equal to STORE_FLAG_VALUE. */
8486 if ((mask & ~STORE_FLAG_VALUE) == 0
8487 && XEXP (x, 1) == const0_rtx
8488 && GET_MODE (XEXP (x, 0)) == mode
8489 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
8490 && (nonzero_bits (XEXP (x, 0), mode)
8491 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
8492 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8497 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8498 written in a narrower mode. We play it safe and do not do so. */
8501 gen_lowpart_or_truncate (GET_MODE (x),
8502 force_to_mode (XEXP (x, 1), mode,
8503 mask, next_select)));
8505 gen_lowpart_or_truncate (GET_MODE (x),
8506 force_to_mode (XEXP (x, 2), mode,
8507 mask, next_select)));
8514 /* Ensure we return a value of the proper mode. */
8515 return gen_lowpart_or_truncate (mode, x);
8518 /* Return nonzero if X is an expression that has one of two values depending on
8519 whether some other value is zero or nonzero. In that case, we return the
8520 value that is being tested, *PTRUE is set to the value if the rtx being
8521 returned has a nonzero value, and *PFALSE is set to the other alternative.
8523 If we return zero, we set *PTRUE and *PFALSE to X. */
8526 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
8528 enum machine_mode mode = GET_MODE (x);
8529 enum rtx_code code = GET_CODE (x);
8530 rtx cond0, cond1, true0, true1, false0, false1;
8531 unsigned HOST_WIDE_INT nz;
8533 /* If we are comparing a value against zero, we are done. */
8534 if ((code == NE || code == EQ)
8535 && XEXP (x, 1) == const0_rtx)
8537 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
8538 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
8542 /* If this is a unary operation whose operand has one of two values, apply
8543 our opcode to compute those values. */
8544 else if (UNARY_P (x)
8545 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
8547 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
8548 *pfalse = simplify_gen_unary (code, mode, false0,
8549 GET_MODE (XEXP (x, 0)));
8553 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8554 make can't possibly match and would suppress other optimizations. */
8555 else if (code == COMPARE)
8558 /* If this is a binary operation, see if either side has only one of two
8559 values. If either one does or if both do and they are conditional on
8560 the same value, compute the new true and false values. */
8561 else if (BINARY_P (x))
8563 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
8564 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
8566 if ((cond0 != 0 || cond1 != 0)
8567 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
8569 /* If if_then_else_cond returned zero, then true/false are the
8570 same rtl. We must copy one of them to prevent invalid rtl
8573 true0 = copy_rtx (true0);
8574 else if (cond1 == 0)
8575 true1 = copy_rtx (true1);
8577 if (COMPARISON_P (x))
8579 *ptrue = simplify_gen_relational (code, mode, VOIDmode,
8581 *pfalse = simplify_gen_relational (code, mode, VOIDmode,
8586 *ptrue = simplify_gen_binary (code, mode, true0, true1);
8587 *pfalse = simplify_gen_binary (code, mode, false0, false1);
8590 return cond0 ? cond0 : cond1;
8593 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8594 operands is zero when the other is nonzero, and vice-versa,
8595 and STORE_FLAG_VALUE is 1 or -1. */
8597 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8598 && (code == PLUS || code == IOR || code == XOR || code == MINUS
8600 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8602 rtx op0 = XEXP (XEXP (x, 0), 1);
8603 rtx op1 = XEXP (XEXP (x, 1), 1);
8605 cond0 = XEXP (XEXP (x, 0), 0);
8606 cond1 = XEXP (XEXP (x, 1), 0);
8608 if (COMPARISON_P (cond0)
8609 && COMPARISON_P (cond1)
8610 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8611 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8612 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8613 || ((swap_condition (GET_CODE (cond0))
8614 == reversed_comparison_code (cond1, NULL))
8615 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8616 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8617 && ! side_effects_p (x))
8619 *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
8620 *pfalse = simplify_gen_binary (MULT, mode,
8622 ? simplify_gen_unary (NEG, mode,
8630 /* Similarly for MULT, AND and UMIN, except that for these the result
8632 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8633 && (code == MULT || code == AND || code == UMIN)
8634 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8636 cond0 = XEXP (XEXP (x, 0), 0);
8637 cond1 = XEXP (XEXP (x, 1), 0);
8639 if (COMPARISON_P (cond0)
8640 && COMPARISON_P (cond1)
8641 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8642 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8643 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8644 || ((swap_condition (GET_CODE (cond0))
8645 == reversed_comparison_code (cond1, NULL))
8646 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8647 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8648 && ! side_effects_p (x))
8650 *ptrue = *pfalse = const0_rtx;
8656 else if (code == IF_THEN_ELSE)
8658 /* If we have IF_THEN_ELSE already, extract the condition and
8659 canonicalize it if it is NE or EQ. */
8660 cond0 = XEXP (x, 0);
8661 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
8662 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
8663 return XEXP (cond0, 0);
8664 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
8666 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
8667 return XEXP (cond0, 0);
8673 /* If X is a SUBREG, we can narrow both the true and false values
8674 if the inner expression, if there is a condition. */
8675 else if (code == SUBREG
8676 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
8679 true0 = simplify_gen_subreg (mode, true0,
8680 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8681 false0 = simplify_gen_subreg (mode, false0,
8682 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8683 if (true0 && false0)
8691 /* If X is a constant, this isn't special and will cause confusions
8692 if we treat it as such. Likewise if it is equivalent to a constant. */
8693 else if (CONSTANT_P (x)
8694 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
8697 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8698 will be least confusing to the rest of the compiler. */
8699 else if (mode == BImode)
8701 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
8705 /* If X is known to be either 0 or -1, those are the true and
8706 false values when testing X. */
8707 else if (x == constm1_rtx || x == const0_rtx
8708 || (mode != VOIDmode
8709 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
8711 *ptrue = constm1_rtx, *pfalse = const0_rtx;
8715 /* Likewise for 0 or a single bit. */
8716 else if (SCALAR_INT_MODE_P (mode)
8717 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8718 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
8720 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
8724 /* Otherwise fail; show no condition with true and false values the same. */
8725 *ptrue = *pfalse = x;
8729 /* Return the value of expression X given the fact that condition COND
8730 is known to be true when applied to REG as its first operand and VAL
8731 as its second. X is known to not be shared and so can be modified in
8734 We only handle the simplest cases, and specifically those cases that
8735 arise with IF_THEN_ELSE expressions. */
8738 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
8740 enum rtx_code code = GET_CODE (x);
8745 if (side_effects_p (x))
8748 /* If either operand of the condition is a floating point value,
8749 then we have to avoid collapsing an EQ comparison. */
8751 && rtx_equal_p (x, reg)
8752 && ! FLOAT_MODE_P (GET_MODE (x))
8753 && ! FLOAT_MODE_P (GET_MODE (val)))
8756 if (cond == UNEQ && rtx_equal_p (x, reg))
8759 /* If X is (abs REG) and we know something about REG's relationship
8760 with zero, we may be able to simplify this. */
8762 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
8765 case GE: case GT: case EQ:
8768 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
8770 GET_MODE (XEXP (x, 0)));
8775 /* The only other cases we handle are MIN, MAX, and comparisons if the
8776 operands are the same as REG and VAL. */
8778 else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
8780 if (rtx_equal_p (XEXP (x, 0), val))
8781 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
8783 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
8785 if (COMPARISON_P (x))
8787 if (comparison_dominates_p (cond, code))
8788 return const_true_rtx;
8790 code = reversed_comparison_code (x, NULL);
8792 && comparison_dominates_p (cond, code))
8797 else if (code == SMAX || code == SMIN
8798 || code == UMIN || code == UMAX)
8800 int unsignedp = (code == UMIN || code == UMAX);
8802 /* Do not reverse the condition when it is NE or EQ.
8803 This is because we cannot conclude anything about
8804 the value of 'SMAX (x, y)' when x is not equal to y,
8805 but we can when x equals y. */
8806 if ((code == SMAX || code == UMAX)
8807 && ! (cond == EQ || cond == NE))
8808 cond = reverse_condition (cond);
8813 return unsignedp ? x : XEXP (x, 1);
8815 return unsignedp ? x : XEXP (x, 0);
8817 return unsignedp ? XEXP (x, 1) : x;
8819 return unsignedp ? XEXP (x, 0) : x;
8826 else if (code == SUBREG)
8828 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
8829 rtx new_rtx, r = known_cond (SUBREG_REG (x), cond, reg, val);
8831 if (SUBREG_REG (x) != r)
8833 /* We must simplify subreg here, before we lose track of the
8834 original inner_mode. */
8835 new_rtx = simplify_subreg (GET_MODE (x), r,
8836 inner_mode, SUBREG_BYTE (x));
8840 SUBST (SUBREG_REG (x), r);
8845 /* We don't have to handle SIGN_EXTEND here, because even in the
8846 case of replacing something with a modeless CONST_INT, a
8847 CONST_INT is already (supposed to be) a valid sign extension for
8848 its narrower mode, which implies it's already properly
8849 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
8850 story is different. */
8851 else if (code == ZERO_EXTEND)
8853 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
8854 rtx new_rtx, r = known_cond (XEXP (x, 0), cond, reg, val);
8856 if (XEXP (x, 0) != r)
8858 /* We must simplify the zero_extend here, before we lose
8859 track of the original inner_mode. */
8860 new_rtx = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
8865 SUBST (XEXP (x, 0), r);
8871 fmt = GET_RTX_FORMAT (code);
8872 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8875 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
8876 else if (fmt[i] == 'E')
8877 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8878 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
8885 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8886 assignment as a field assignment. */
8889 rtx_equal_for_field_assignment_p (rtx x, rtx y)
8891 if (x == y || rtx_equal_p (x, y))
8894 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
8897 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8898 Note that all SUBREGs of MEM are paradoxical; otherwise they
8899 would have been rewritten. */
8900 if (MEM_P (x) && GET_CODE (y) == SUBREG
8901 && MEM_P (SUBREG_REG (y))
8902 && rtx_equal_p (SUBREG_REG (y),
8903 gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
8906 if (MEM_P (y) && GET_CODE (x) == SUBREG
8907 && MEM_P (SUBREG_REG (x))
8908 && rtx_equal_p (SUBREG_REG (x),
8909 gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
8912 /* We used to see if get_last_value of X and Y were the same but that's
8913 not correct. In one direction, we'll cause the assignment to have
8914 the wrong destination and in the case, we'll import a register into this
8915 insn that might have already have been dead. So fail if none of the
8916 above cases are true. */
8920 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8921 Return that assignment if so.
8923 We only handle the most common cases. */
8926 make_field_assignment (rtx x)
8928 rtx dest = SET_DEST (x);
8929 rtx src = SET_SRC (x);
8934 unsigned HOST_WIDE_INT len;
8936 enum machine_mode mode;
8938 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
8939 a clear of a one-bit field. We will have changed it to
8940 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
8943 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
8944 && CONST_INT_P (XEXP (XEXP (src, 0), 0))
8945 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
8946 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8948 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8951 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8955 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
8956 && subreg_lowpart_p (XEXP (src, 0))
8957 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
8958 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
8959 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
8960 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src, 0)), 0))
8961 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
8962 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8964 assign = make_extraction (VOIDmode, dest, 0,
8965 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
8968 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8972 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
8974 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
8975 && XEXP (XEXP (src, 0), 0) == const1_rtx
8976 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8978 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8981 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
8985 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
8986 SRC is an AND with all bits of that field set, then we can discard
8988 if (GET_CODE (dest) == ZERO_EXTRACT
8989 && CONST_INT_P (XEXP (dest, 1))
8990 && GET_CODE (src) == AND
8991 && CONST_INT_P (XEXP (src, 1)))
8993 HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
8994 unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
8995 unsigned HOST_WIDE_INT ze_mask;
8997 if (width >= HOST_BITS_PER_WIDE_INT)
9000 ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
9002 /* Complete overlap. We can remove the source AND. */
9003 if ((and_mask & ze_mask) == ze_mask)
9004 return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
9006 /* Partial overlap. We can reduce the source AND. */
9007 if ((and_mask & ze_mask) != and_mask)
9009 mode = GET_MODE (src);
9010 src = gen_rtx_AND (mode, XEXP (src, 0),
9011 gen_int_mode (and_mask & ze_mask, mode));
9012 return gen_rtx_SET (VOIDmode, dest, src);
9016 /* The other case we handle is assignments into a constant-position
9017 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9018 a mask that has all one bits except for a group of zero bits and
9019 OTHER is known to have zeros where C1 has ones, this is such an
9020 assignment. Compute the position and length from C1. Shift OTHER
9021 to the appropriate position, force it to the required mode, and
9022 make the extraction. Check for the AND in both operands. */
9024 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
9027 rhs = expand_compound_operation (XEXP (src, 0));
9028 lhs = expand_compound_operation (XEXP (src, 1));
9030 if (GET_CODE (rhs) == AND
9031 && CONST_INT_P (XEXP (rhs, 1))
9032 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
9033 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
9034 else if (GET_CODE (lhs) == AND
9035 && CONST_INT_P (XEXP (lhs, 1))
9036 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
9037 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
9041 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
9042 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
9043 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
9044 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
9047 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
9051 /* The mode to use for the source is the mode of the assignment, or of
9052 what is inside a possible STRICT_LOW_PART. */
9053 mode = (GET_CODE (assign) == STRICT_LOW_PART
9054 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
9056 /* Shift OTHER right POS places and make it the source, restricting it
9057 to the proper length and mode. */
9059 src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
9063 src = force_to_mode (src, mode,
9064 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
9065 ? ~(unsigned HOST_WIDE_INT) 0
9066 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
9069 /* If SRC is masked by an AND that does not make a difference in
9070 the value being stored, strip it. */
9071 if (GET_CODE (assign) == ZERO_EXTRACT
9072 && CONST_INT_P (XEXP (assign, 1))
9073 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
9074 && GET_CODE (src) == AND
9075 && CONST_INT_P (XEXP (src, 1))
9076 && UINTVAL (XEXP (src, 1))
9077 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1)
9078 src = XEXP (src, 0);
9080 return gen_rtx_SET (VOIDmode, assign, src);
9083 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9087 apply_distributive_law (rtx x)
9089 enum rtx_code code = GET_CODE (x);
9090 enum rtx_code inner_code;
9091 rtx lhs, rhs, other;
9094 /* Distributivity is not true for floating point as it can change the
9095 value. So we don't do it unless -funsafe-math-optimizations. */
9096 if (FLOAT_MODE_P (GET_MODE (x))
9097 && ! flag_unsafe_math_optimizations)
9100 /* The outer operation can only be one of the following: */
9101 if (code != IOR && code != AND && code != XOR
9102 && code != PLUS && code != MINUS)
9108 /* If either operand is a primitive we can't do anything, so get out
9110 if (OBJECT_P (lhs) || OBJECT_P (rhs))
9113 lhs = expand_compound_operation (lhs);
9114 rhs = expand_compound_operation (rhs);
9115 inner_code = GET_CODE (lhs);
9116 if (inner_code != GET_CODE (rhs))
9119 /* See if the inner and outer operations distribute. */
9126 /* These all distribute except over PLUS. */
9127 if (code == PLUS || code == MINUS)
9132 if (code != PLUS && code != MINUS)
9137 /* This is also a multiply, so it distributes over everything. */
9141 /* Non-paradoxical SUBREGs distributes over all operations,
9142 provided the inner modes and byte offsets are the same, this
9143 is an extraction of a low-order part, we don't convert an fp
9144 operation to int or vice versa, this is not a vector mode,
9145 and we would not be converting a single-word operation into a
9146 multi-word operation. The latter test is not required, but
9147 it prevents generating unneeded multi-word operations. Some
9148 of the previous tests are redundant given the latter test,
9149 but are retained because they are required for correctness.
9151 We produce the result slightly differently in this case. */
9153 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
9154 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
9155 || ! subreg_lowpart_p (lhs)
9156 || (GET_MODE_CLASS (GET_MODE (lhs))
9157 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
9158 || (GET_MODE_SIZE (GET_MODE (lhs))
9159 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
9160 || VECTOR_MODE_P (GET_MODE (lhs))
9161 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD
9162 /* Result might need to be truncated. Don't change mode if
9163 explicit truncation is needed. */
9164 || !TRULY_NOOP_TRUNCATION
9165 (GET_MODE_BITSIZE (GET_MODE (x)),
9166 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (lhs)))))
9169 tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
9170 SUBREG_REG (lhs), SUBREG_REG (rhs));
9171 return gen_lowpart (GET_MODE (x), tem);
9177 /* Set LHS and RHS to the inner operands (A and B in the example
9178 above) and set OTHER to the common operand (C in the example).
9179 There is only one way to do this unless the inner operation is
9181 if (COMMUTATIVE_ARITH_P (lhs)
9182 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
9183 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
9184 else if (COMMUTATIVE_ARITH_P (lhs)
9185 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
9186 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
9187 else if (COMMUTATIVE_ARITH_P (lhs)
9188 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
9189 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
9190 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
9191 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
9195 /* Form the new inner operation, seeing if it simplifies first. */
9196 tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
9198 /* There is one exception to the general way of distributing:
9199 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9200 if (code == XOR && inner_code == IOR)
9203 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
9206 /* We may be able to continuing distributing the result, so call
9207 ourselves recursively on the inner operation before forming the
9208 outer operation, which we return. */
9209 return simplify_gen_binary (inner_code, GET_MODE (x),
9210 apply_distributive_law (tem), other);
9213 /* See if X is of the form (* (+ A B) C), and if so convert to
9214 (+ (* A C) (* B C)) and try to simplify.
9216 Most of the time, this results in no change. However, if some of
9217 the operands are the same or inverses of each other, simplifications
9220 For example, (and (ior A B) (not B)) can occur as the result of
9221 expanding a bit field assignment. When we apply the distributive
9222 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9223 which then simplifies to (and (A (not B))).
9225 Note that no checks happen on the validity of applying the inverse
9226 distributive law. This is pointless since we can do it in the
9227 few places where this routine is called.
9229 N is the index of the term that is decomposed (the arithmetic operation,
9230 i.e. (+ A B) in the first example above). !N is the index of the term that
9231 is distributed, i.e. of C in the first example above. */
9233 distribute_and_simplify_rtx (rtx x, int n)
9235 enum machine_mode mode;
9236 enum rtx_code outer_code, inner_code;
9237 rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
9239 /* Distributivity is not true for floating point as it can change the
9240 value. So we don't do it unless -funsafe-math-optimizations. */
9241 if (FLOAT_MODE_P (GET_MODE (x))
9242 && ! flag_unsafe_math_optimizations)
9245 decomposed = XEXP (x, n);
9246 if (!ARITHMETIC_P (decomposed))
9249 mode = GET_MODE (x);
9250 outer_code = GET_CODE (x);
9251 distributed = XEXP (x, !n);
9253 inner_code = GET_CODE (decomposed);
9254 inner_op0 = XEXP (decomposed, 0);
9255 inner_op1 = XEXP (decomposed, 1);
9257 /* Special case (and (xor B C) (not A)), which is equivalent to
9258 (xor (ior A B) (ior A C)) */
9259 if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
9261 distributed = XEXP (distributed, 0);
9267 /* Distribute the second term. */
9268 new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
9269 new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
9273 /* Distribute the first term. */
9274 new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
9275 new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
9278 tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
9280 if (GET_CODE (tmp) != outer_code
9281 && rtx_cost (tmp, SET, optimize_this_for_speed_p)
9282 < rtx_cost (x, SET, optimize_this_for_speed_p))
9288 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9289 in MODE. Return an equivalent form, if different from (and VAROP
9290 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9293 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
9294 unsigned HOST_WIDE_INT constop)
9296 unsigned HOST_WIDE_INT nonzero;
9297 unsigned HOST_WIDE_INT orig_constop;
9302 orig_constop = constop;
9303 if (GET_CODE (varop) == CLOBBER)
9306 /* Simplify VAROP knowing that we will be only looking at some of the
9309 Note by passing in CONSTOP, we guarantee that the bits not set in
9310 CONSTOP are not significant and will never be examined. We must
9311 ensure that is the case by explicitly masking out those bits
9312 before returning. */
9313 varop = force_to_mode (varop, mode, constop, 0);
9315 /* If VAROP is a CLOBBER, we will fail so return it. */
9316 if (GET_CODE (varop) == CLOBBER)
9319 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9320 to VAROP and return the new constant. */
9321 if (CONST_INT_P (varop))
9322 return gen_int_mode (INTVAL (varop) & constop, mode);
9324 /* See what bits may be nonzero in VAROP. Unlike the general case of
9325 a call to nonzero_bits, here we don't care about bits outside
9328 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
9330 /* Turn off all bits in the constant that are known to already be zero.
9331 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9332 which is tested below. */
9336 /* If we don't have any bits left, return zero. */
9340 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9341 a power of two, we can replace this with an ASHIFT. */
9342 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
9343 && (i = exact_log2 (constop)) >= 0)
9344 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
9346 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9347 or XOR, then try to apply the distributive law. This may eliminate
9348 operations if either branch can be simplified because of the AND.
9349 It may also make some cases more complex, but those cases probably
9350 won't match a pattern either with or without this. */
9352 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
9356 apply_distributive_law
9357 (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
9358 simplify_and_const_int (NULL_RTX,
9362 simplify_and_const_int (NULL_RTX,
9367 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9368 the AND and see if one of the operands simplifies to zero. If so, we
9369 may eliminate it. */
9371 if (GET_CODE (varop) == PLUS
9372 && exact_log2 (constop + 1) >= 0)
9376 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
9377 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
9378 if (o0 == const0_rtx)
9380 if (o1 == const0_rtx)
9384 /* Make a SUBREG if necessary. If we can't make it, fail. */
9385 varop = gen_lowpart (mode, varop);
9386 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
9389 /* If we are only masking insignificant bits, return VAROP. */
9390 if (constop == nonzero)
9393 if (varop == orig_varop && constop == orig_constop)
9396 /* Otherwise, return an AND. */
9397 return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
9401 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9404 Return an equivalent form, if different from X. Otherwise, return X. If
9405 X is zero, we are to always construct the equivalent form. */
9408 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
9409 unsigned HOST_WIDE_INT constop)
9411 rtx tem = simplify_and_const_int_1 (mode, varop, constop);
9416 x = simplify_gen_binary (AND, GET_MODE (varop), varop,
9417 gen_int_mode (constop, mode));
9418 if (GET_MODE (x) != mode)
9419 x = gen_lowpart (mode, x);
9423 /* Given a REG, X, compute which bits in X can be nonzero.
9424 We don't care about bits outside of those defined in MODE.
9426 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9427 a shift, AND, or zero_extract, we can do better. */
9430 reg_nonzero_bits_for_combine (const_rtx x, enum machine_mode mode,
9431 const_rtx known_x ATTRIBUTE_UNUSED,
9432 enum machine_mode known_mode ATTRIBUTE_UNUSED,
9433 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
9434 unsigned HOST_WIDE_INT *nonzero)
9439 /* If X is a register whose nonzero bits value is current, use it.
9440 Otherwise, if X is a register whose value we can find, use that
9441 value. Otherwise, use the previously-computed global nonzero bits
9442 for this register. */
9444 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
9445 if (rsp->last_set_value != 0
9446 && (rsp->last_set_mode == mode
9447 || (GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT
9448 && GET_MODE_CLASS (mode) == MODE_INT))
9449 && ((rsp->last_set_label >= label_tick_ebb_start
9450 && rsp->last_set_label < label_tick)
9451 || (rsp->last_set_label == label_tick
9452 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9453 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9454 && REG_N_SETS (REGNO (x)) == 1
9456 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9458 *nonzero &= rsp->last_set_nonzero_bits;
9462 tem = get_last_value (x);
9466 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9467 /* If X is narrower than MODE and TEM is a non-negative
9468 constant that would appear negative in the mode of X,
9469 sign-extend it for use in reg_nonzero_bits because some
9470 machines (maybe most) will actually do the sign-extension
9471 and this is the conservative approach.
9473 ??? For 2.5, try to tighten up the MD files in this regard
9474 instead of this kludge. */
9476 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)
9477 && CONST_INT_P (tem)
9479 && 0 != (UINTVAL (tem)
9480 & ((unsigned HOST_WIDE_INT) 1
9481 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
9482 tem = GEN_INT (UINTVAL (tem)
9483 | ((unsigned HOST_WIDE_INT) (-1)
9484 << GET_MODE_BITSIZE (GET_MODE (x))));
9488 else if (nonzero_sign_valid && rsp->nonzero_bits)
9490 unsigned HOST_WIDE_INT mask = rsp->nonzero_bits;
9492 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode))
9493 /* We don't know anything about the upper bits. */
9494 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
9501 /* Return the number of bits at the high-order end of X that are known to
9502 be equal to the sign bit. X will be used in mode MODE; if MODE is
9503 VOIDmode, X will be used in its own mode. The returned value will always
9504 be between 1 and the number of bits in MODE. */
9507 reg_num_sign_bit_copies_for_combine (const_rtx x, enum machine_mode mode,
9508 const_rtx known_x ATTRIBUTE_UNUSED,
9509 enum machine_mode known_mode
9511 unsigned int known_ret ATTRIBUTE_UNUSED,
9512 unsigned int *result)
9517 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
9518 if (rsp->last_set_value != 0
9519 && rsp->last_set_mode == mode
9520 && ((rsp->last_set_label >= label_tick_ebb_start
9521 && rsp->last_set_label < label_tick)
9522 || (rsp->last_set_label == label_tick
9523 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9524 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9525 && REG_N_SETS (REGNO (x)) == 1
9527 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9529 *result = rsp->last_set_sign_bit_copies;
9533 tem = get_last_value (x);
9537 if (nonzero_sign_valid && rsp->sign_bit_copies != 0
9538 && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode))
9539 *result = rsp->sign_bit_copies;
9544 /* Return the number of "extended" bits there are in X, when interpreted
9545 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9546 unsigned quantities, this is the number of high-order zero bits.
9547 For signed quantities, this is the number of copies of the sign bit
9548 minus 1. In both case, this function returns the number of "spare"
9549 bits. For example, if two quantities for which this function returns
9550 at least 1 are added, the addition is known not to overflow.
9552 This function will always return 0 unless called during combine, which
9553 implies that it must be called from a define_split. */
9556 extended_count (const_rtx x, enum machine_mode mode, int unsignedp)
9558 if (nonzero_sign_valid == 0)
9562 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9563 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
9564 - floor_log2 (nonzero_bits (x, mode)))
9566 : num_sign_bit_copies (x, mode) - 1);
9569 /* This function is called from `simplify_shift_const' to merge two
9570 outer operations. Specifically, we have already found that we need
9571 to perform operation *POP0 with constant *PCONST0 at the outermost
9572 position. We would now like to also perform OP1 with constant CONST1
9573 (with *POP0 being done last).
9575 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9576 the resulting operation. *PCOMP_P is set to 1 if we would need to
9577 complement the innermost operand, otherwise it is unchanged.
9579 MODE is the mode in which the operation will be done. No bits outside
9580 the width of this mode matter. It is assumed that the width of this mode
9581 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9583 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9584 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9585 result is simply *PCONST0.
9587 If the resulting operation cannot be expressed as one operation, we
9588 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9591 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
9593 enum rtx_code op0 = *pop0;
9594 HOST_WIDE_INT const0 = *pconst0;
9596 const0 &= GET_MODE_MASK (mode);
9597 const1 &= GET_MODE_MASK (mode);
9599 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9603 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9606 if (op1 == UNKNOWN || op0 == SET)
9609 else if (op0 == UNKNOWN)
9610 op0 = op1, const0 = const1;
9612 else if (op0 == op1)
9636 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9637 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
9640 /* If the two constants aren't the same, we can't do anything. The
9641 remaining six cases can all be done. */
9642 else if (const0 != const1)
9650 /* (a & b) | b == b */
9652 else /* op1 == XOR */
9653 /* (a ^ b) | b == a | b */
9659 /* (a & b) ^ b == (~a) & b */
9660 op0 = AND, *pcomp_p = 1;
9661 else /* op1 == IOR */
9662 /* (a | b) ^ b == a & ~b */
9663 op0 = AND, const0 = ~const0;
9668 /* (a | b) & b == b */
9670 else /* op1 == XOR */
9671 /* (a ^ b) & b) == (~a) & b */
9678 /* Check for NO-OP cases. */
9679 const0 &= GET_MODE_MASK (mode);
9681 && (op0 == IOR || op0 == XOR || op0 == PLUS))
9683 else if (const0 == 0 && op0 == AND)
9685 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
9691 /* ??? Slightly redundant with the above mask, but not entirely.
9692 Moving this above means we'd have to sign-extend the mode mask
9693 for the final test. */
9694 if (op0 != UNKNOWN && op0 != NEG)
9695 *pconst0 = trunc_int_for_mode (const0, mode);
9700 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9701 the shift in. The original shift operation CODE is performed on OP in
9702 ORIG_MODE. Return the wider mode MODE if we can perform the operation
9703 in that mode. Return ORIG_MODE otherwise. We can also assume that the
9704 result of the shift is subject to operation OUTER_CODE with operand
9707 static enum machine_mode
9708 try_widen_shift_mode (enum rtx_code code, rtx op, int count,
9709 enum machine_mode orig_mode, enum machine_mode mode,
9710 enum rtx_code outer_code, HOST_WIDE_INT outer_const)
9712 if (orig_mode == mode)
9714 gcc_assert (GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (orig_mode));
9716 /* In general we can't perform in wider mode for right shift and rotate. */
9720 /* We can still widen if the bits brought in from the left are identical
9721 to the sign bit of ORIG_MODE. */
9722 if (num_sign_bit_copies (op, mode)
9723 > (unsigned) (GET_MODE_BITSIZE (mode)
9724 - GET_MODE_BITSIZE (orig_mode)))
9729 /* Similarly here but with zero bits. */
9730 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9731 && (nonzero_bits (op, mode) & ~GET_MODE_MASK (orig_mode)) == 0)
9734 /* We can also widen if the bits brought in will be masked off. This
9735 operation is performed in ORIG_MODE. */
9736 if (outer_code == AND)
9738 int care_bits = low_bitmask_len (orig_mode, outer_const);
9741 && GET_MODE_BITSIZE (orig_mode) - care_bits >= count)
9757 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9758 The result of the shift is RESULT_MODE. Return NULL_RTX if we cannot
9759 simplify it. Otherwise, return a simplified value.
9761 The shift is normally computed in the widest mode we find in VAROP, as
9762 long as it isn't a different number of words than RESULT_MODE. Exceptions
9763 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9766 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
9767 rtx varop, int orig_count)
9769 enum rtx_code orig_code = code;
9770 rtx orig_varop = varop;
9772 enum machine_mode mode = result_mode;
9773 enum machine_mode shift_mode, tmode;
9774 unsigned int mode_words
9775 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
9776 /* We form (outer_op (code varop count) (outer_const)). */
9777 enum rtx_code outer_op = UNKNOWN;
9778 HOST_WIDE_INT outer_const = 0;
9779 int complement_p = 0;
9782 /* Make sure and truncate the "natural" shift on the way in. We don't
9783 want to do this inside the loop as it makes it more difficult to
9785 if (SHIFT_COUNT_TRUNCATED)
9786 orig_count &= GET_MODE_BITSIZE (mode) - 1;
9788 /* If we were given an invalid count, don't do anything except exactly
9789 what was requested. */
9791 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
9796 /* Unless one of the branches of the `if' in this loop does a `continue',
9797 we will `break' the loop after the `if'. */
9801 /* If we have an operand of (clobber (const_int 0)), fail. */
9802 if (GET_CODE (varop) == CLOBBER)
9805 /* Convert ROTATERT to ROTATE. */
9806 if (code == ROTATERT)
9808 unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
9810 if (VECTOR_MODE_P (result_mode))
9811 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
9813 count = bitsize - count;
9816 shift_mode = try_widen_shift_mode (code, varop, count, result_mode,
9817 mode, outer_op, outer_const);
9819 /* Handle cases where the count is greater than the size of the mode
9820 minus 1. For ASHIFT, use the size minus one as the count (this can
9821 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9822 take the count modulo the size. For other shifts, the result is
9825 Since these shifts are being produced by the compiler by combining
9826 multiple operations, each of which are defined, we know what the
9827 result is supposed to be. */
9829 if (count > (GET_MODE_BITSIZE (shift_mode) - 1))
9831 if (code == ASHIFTRT)
9832 count = GET_MODE_BITSIZE (shift_mode) - 1;
9833 else if (code == ROTATE || code == ROTATERT)
9834 count %= GET_MODE_BITSIZE (shift_mode);
9837 /* We can't simply return zero because there may be an
9845 /* If we discovered we had to complement VAROP, leave. Making a NOT
9846 here would cause an infinite loop. */
9850 /* An arithmetic right shift of a quantity known to be -1 or 0
9852 if (code == ASHIFTRT
9853 && (num_sign_bit_copies (varop, shift_mode)
9854 == GET_MODE_BITSIZE (shift_mode)))
9860 /* If we are doing an arithmetic right shift and discarding all but
9861 the sign bit copies, this is equivalent to doing a shift by the
9862 bitsize minus one. Convert it into that shift because it will often
9863 allow other simplifications. */
9865 if (code == ASHIFTRT
9866 && (count + num_sign_bit_copies (varop, shift_mode)
9867 >= GET_MODE_BITSIZE (shift_mode)))
9868 count = GET_MODE_BITSIZE (shift_mode) - 1;
9870 /* We simplify the tests below and elsewhere by converting
9871 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9872 `make_compound_operation' will convert it to an ASHIFTRT for
9873 those machines (such as VAX) that don't have an LSHIFTRT. */
9874 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9876 && ((nonzero_bits (varop, shift_mode)
9877 & ((unsigned HOST_WIDE_INT) 1
9878 << (GET_MODE_BITSIZE (shift_mode) - 1))) == 0))
9881 if (((code == LSHIFTRT
9882 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9883 && !(nonzero_bits (varop, shift_mode) >> count))
9885 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9886 && !((nonzero_bits (varop, shift_mode) << count)
9887 & GET_MODE_MASK (shift_mode))))
9888 && !side_effects_p (varop))
9891 switch (GET_CODE (varop))
9897 new_rtx = expand_compound_operation (varop);
9898 if (new_rtx != varop)
9906 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9907 minus the width of a smaller mode, we can do this with a
9908 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9909 if ((code == ASHIFTRT || code == LSHIFTRT)
9910 && ! mode_dependent_address_p (XEXP (varop, 0))
9911 && ! MEM_VOLATILE_P (varop)
9912 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9913 MODE_INT, 1)) != BLKmode)
9915 new_rtx = adjust_address_nv (varop, tmode,
9916 BYTES_BIG_ENDIAN ? 0
9917 : count / BITS_PER_UNIT);
9919 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9920 : ZERO_EXTEND, mode, new_rtx);
9927 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9928 the same number of words as what we've seen so far. Then store
9929 the widest mode in MODE. */
9930 if (subreg_lowpart_p (varop)
9931 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9932 > GET_MODE_SIZE (GET_MODE (varop)))
9933 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9934 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9936 && GET_MODE_CLASS (GET_MODE (varop)) == MODE_INT
9937 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (varop))) == MODE_INT)
9939 varop = SUBREG_REG (varop);
9940 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9941 mode = GET_MODE (varop);
9947 /* Some machines use MULT instead of ASHIFT because MULT
9948 is cheaper. But it is still better on those machines to
9949 merge two shifts into one. */
9950 if (CONST_INT_P (XEXP (varop, 1))
9951 && exact_log2 (UINTVAL (XEXP (varop, 1))) >= 0)
9954 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
9956 GEN_INT (exact_log2 (
9957 UINTVAL (XEXP (varop, 1)))));
9963 /* Similar, for when divides are cheaper. */
9964 if (CONST_INT_P (XEXP (varop, 1))
9965 && exact_log2 (UINTVAL (XEXP (varop, 1))) >= 0)
9968 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
9970 GEN_INT (exact_log2 (
9971 UINTVAL (XEXP (varop, 1)))));
9977 /* If we are extracting just the sign bit of an arithmetic
9978 right shift, that shift is not needed. However, the sign
9979 bit of a wider mode may be different from what would be
9980 interpreted as the sign bit in a narrower mode, so, if
9981 the result is narrower, don't discard the shift. */
9982 if (code == LSHIFTRT
9983 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9984 && (GET_MODE_BITSIZE (result_mode)
9985 >= GET_MODE_BITSIZE (GET_MODE (varop))))
9987 varop = XEXP (varop, 0);
9991 /* ... fall through ... */
9996 /* Here we have two nested shifts. The result is usually the
9997 AND of a new shift with a mask. We compute the result below. */
9998 if (CONST_INT_P (XEXP (varop, 1))
9999 && INTVAL (XEXP (varop, 1)) >= 0
10000 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
10001 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
10002 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
10003 && !VECTOR_MODE_P (result_mode))
10005 enum rtx_code first_code = GET_CODE (varop);
10006 unsigned int first_count = INTVAL (XEXP (varop, 1));
10007 unsigned HOST_WIDE_INT mask;
10010 /* We have one common special case. We can't do any merging if
10011 the inner code is an ASHIFTRT of a smaller mode. However, if
10012 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10013 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10014 we can convert it to
10015 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
10016 This simplifies certain SIGN_EXTEND operations. */
10017 if (code == ASHIFT && first_code == ASHIFTRT
10018 && count == (GET_MODE_BITSIZE (result_mode)
10019 - GET_MODE_BITSIZE (GET_MODE (varop))))
10021 /* C3 has the low-order C1 bits zero. */
10023 mask = GET_MODE_MASK (mode)
10024 & ~(((unsigned HOST_WIDE_INT) 1 << first_count) - 1);
10026 varop = simplify_and_const_int (NULL_RTX, result_mode,
10027 XEXP (varop, 0), mask);
10028 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
10030 count = first_count;
10035 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10036 than C1 high-order bits equal to the sign bit, we can convert
10037 this to either an ASHIFT or an ASHIFTRT depending on the
10040 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10042 if (code == ASHIFTRT && first_code == ASHIFT
10043 && GET_MODE (varop) == shift_mode
10044 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
10047 varop = XEXP (varop, 0);
10048 count -= first_count;
10058 /* There are some cases we can't do. If CODE is ASHIFTRT,
10059 we can only do this if FIRST_CODE is also ASHIFTRT.
10061 We can't do the case when CODE is ROTATE and FIRST_CODE is
10064 If the mode of this shift is not the mode of the outer shift,
10065 we can't do this if either shift is a right shift or ROTATE.
10067 Finally, we can't do any of these if the mode is too wide
10068 unless the codes are the same.
10070 Handle the case where the shift codes are the same
10073 if (code == first_code)
10075 if (GET_MODE (varop) != result_mode
10076 && (code == ASHIFTRT || code == LSHIFTRT
10077 || code == ROTATE))
10080 count += first_count;
10081 varop = XEXP (varop, 0);
10085 if (code == ASHIFTRT
10086 || (code == ROTATE && first_code == ASHIFTRT)
10087 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
10088 || (GET_MODE (varop) != result_mode
10089 && (first_code == ASHIFTRT || first_code == LSHIFTRT
10090 || first_code == ROTATE
10091 || code == ROTATE)))
10094 /* To compute the mask to apply after the shift, shift the
10095 nonzero bits of the inner shift the same way the
10096 outer shift will. */
10098 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
10101 = simplify_const_binary_operation (code, result_mode, mask_rtx,
10104 /* Give up if we can't compute an outer operation to use. */
10106 || !CONST_INT_P (mask_rtx)
10107 || ! merge_outer_ops (&outer_op, &outer_const, AND,
10109 result_mode, &complement_p))
10112 /* If the shifts are in the same direction, we add the
10113 counts. Otherwise, we subtract them. */
10114 if ((code == ASHIFTRT || code == LSHIFTRT)
10115 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
10116 count += first_count;
10118 count -= first_count;
10120 /* If COUNT is positive, the new shift is usually CODE,
10121 except for the two exceptions below, in which case it is
10122 FIRST_CODE. If the count is negative, FIRST_CODE should
10125 && ((first_code == ROTATE && code == ASHIFT)
10126 || (first_code == ASHIFTRT && code == LSHIFTRT)))
10128 else if (count < 0)
10129 code = first_code, count = -count;
10131 varop = XEXP (varop, 0);
10135 /* If we have (A << B << C) for any shift, we can convert this to
10136 (A << C << B). This wins if A is a constant. Only try this if
10137 B is not a constant. */
10139 else if (GET_CODE (varop) == code
10140 && CONST_INT_P (XEXP (varop, 0))
10141 && !CONST_INT_P (XEXP (varop, 1)))
10143 rtx new_rtx = simplify_const_binary_operation (code, mode,
10146 varop = gen_rtx_fmt_ee (code, mode, new_rtx, XEXP (varop, 1));
10153 if (VECTOR_MODE_P (mode))
10156 /* Make this fit the case below. */
10157 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
10158 GEN_INT (GET_MODE_MASK (mode)));
10164 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10165 with C the size of VAROP - 1 and the shift is logical if
10166 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10167 we have an (le X 0) operation. If we have an arithmetic shift
10168 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10169 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10171 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
10172 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
10173 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
10174 && (code == LSHIFTRT || code == ASHIFTRT)
10175 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
10176 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
10179 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
10182 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
10183 varop = gen_rtx_NEG (GET_MODE (varop), varop);
10188 /* If we have (shift (logical)), move the logical to the outside
10189 to allow it to possibly combine with another logical and the
10190 shift to combine with another shift. This also canonicalizes to
10191 what a ZERO_EXTRACT looks like. Also, some machines have
10192 (and (shift)) insns. */
10194 if (CONST_INT_P (XEXP (varop, 1))
10195 /* We can't do this if we have (ashiftrt (xor)) and the
10196 constant has its sign bit set in shift_mode. */
10197 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
10198 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
10200 && (new_rtx = simplify_const_binary_operation (code, result_mode,
10202 GEN_INT (count))) != 0
10203 && CONST_INT_P (new_rtx)
10204 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
10205 INTVAL (new_rtx), result_mode, &complement_p))
10207 varop = XEXP (varop, 0);
10211 /* If we can't do that, try to simplify the shift in each arm of the
10212 logical expression, make a new logical expression, and apply
10213 the inverse distributive law. This also can't be done
10214 for some (ashiftrt (xor)). */
10215 if (CONST_INT_P (XEXP (varop, 1))
10216 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
10217 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
10220 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
10221 XEXP (varop, 0), count);
10222 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
10223 XEXP (varop, 1), count);
10225 varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
10227 varop = apply_distributive_law (varop);
10235 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10236 says that the sign bit can be tested, FOO has mode MODE, C is
10237 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
10238 that may be nonzero. */
10239 if (code == LSHIFTRT
10240 && XEXP (varop, 1) == const0_rtx
10241 && GET_MODE (XEXP (varop, 0)) == result_mode
10242 && count == (GET_MODE_BITSIZE (result_mode) - 1)
10243 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
10244 && STORE_FLAG_VALUE == -1
10245 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
10246 && merge_outer_ops (&outer_op, &outer_const, XOR, 1, result_mode,
10249 varop = XEXP (varop, 0);
10256 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10257 than the number of bits in the mode is equivalent to A. */
10258 if (code == LSHIFTRT
10259 && count == (GET_MODE_BITSIZE (result_mode) - 1)
10260 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
10262 varop = XEXP (varop, 0);
10267 /* NEG commutes with ASHIFT since it is multiplication. Move the
10268 NEG outside to allow shifts to combine. */
10270 && merge_outer_ops (&outer_op, &outer_const, NEG, 0, result_mode,
10273 varop = XEXP (varop, 0);
10279 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10280 is one less than the number of bits in the mode is
10281 equivalent to (xor A 1). */
10282 if (code == LSHIFTRT
10283 && count == (GET_MODE_BITSIZE (result_mode) - 1)
10284 && XEXP (varop, 1) == constm1_rtx
10285 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
10286 && merge_outer_ops (&outer_op, &outer_const, XOR, 1, result_mode,
10290 varop = XEXP (varop, 0);
10294 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10295 that might be nonzero in BAR are those being shifted out and those
10296 bits are known zero in FOO, we can replace the PLUS with FOO.
10297 Similarly in the other operand order. This code occurs when
10298 we are computing the size of a variable-size array. */
10300 if ((code == ASHIFTRT || code == LSHIFTRT)
10301 && count < HOST_BITS_PER_WIDE_INT
10302 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
10303 && (nonzero_bits (XEXP (varop, 1), result_mode)
10304 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
10306 varop = XEXP (varop, 0);
10309 else if ((code == ASHIFTRT || code == LSHIFTRT)
10310 && count < HOST_BITS_PER_WIDE_INT
10311 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
10312 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
10314 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
10315 & nonzero_bits (XEXP (varop, 1),
10318 varop = XEXP (varop, 1);
10322 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10324 && CONST_INT_P (XEXP (varop, 1))
10325 && (new_rtx = simplify_const_binary_operation (ASHIFT, result_mode,
10327 GEN_INT (count))) != 0
10328 && CONST_INT_P (new_rtx)
10329 && merge_outer_ops (&outer_op, &outer_const, PLUS,
10330 INTVAL (new_rtx), result_mode, &complement_p))
10332 varop = XEXP (varop, 0);
10336 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10337 signbit', and attempt to change the PLUS to an XOR and move it to
10338 the outer operation as is done above in the AND/IOR/XOR case
10339 leg for shift(logical). See details in logical handling above
10340 for reasoning in doing so. */
10341 if (code == LSHIFTRT
10342 && CONST_INT_P (XEXP (varop, 1))
10343 && mode_signbit_p (result_mode, XEXP (varop, 1))
10344 && (new_rtx = simplify_const_binary_operation (code, result_mode,
10346 GEN_INT (count))) != 0
10347 && CONST_INT_P (new_rtx)
10348 && merge_outer_ops (&outer_op, &outer_const, XOR,
10349 INTVAL (new_rtx), result_mode, &complement_p))
10351 varop = XEXP (varop, 0);
10358 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10359 with C the size of VAROP - 1 and the shift is logical if
10360 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10361 we have a (gt X 0) operation. If the shift is arithmetic with
10362 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10363 we have a (neg (gt X 0)) operation. */
10365 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
10366 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
10367 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
10368 && (code == LSHIFTRT || code == ASHIFTRT)
10369 && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
10370 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
10371 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
10374 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
10377 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
10378 varop = gen_rtx_NEG (GET_MODE (varop), varop);
10385 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10386 if the truncate does not affect the value. */
10387 if (code == LSHIFTRT
10388 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
10389 && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
10390 && (INTVAL (XEXP (XEXP (varop, 0), 1))
10391 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
10392 - GET_MODE_BITSIZE (GET_MODE (varop)))))
10394 rtx varop_inner = XEXP (varop, 0);
10397 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
10398 XEXP (varop_inner, 0),
10400 (count + INTVAL (XEXP (varop_inner, 1))));
10401 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
10414 shift_mode = try_widen_shift_mode (code, varop, count, result_mode, mode,
10415 outer_op, outer_const);
10417 /* We have now finished analyzing the shift. The result should be
10418 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10419 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10420 to the result of the shift. OUTER_CONST is the relevant constant,
10421 but we must turn off all bits turned off in the shift. */
10423 if (outer_op == UNKNOWN
10424 && orig_code == code && orig_count == count
10425 && varop == orig_varop
10426 && shift_mode == GET_MODE (varop))
10429 /* Make a SUBREG if necessary. If we can't make it, fail. */
10430 varop = gen_lowpart (shift_mode, varop);
10431 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
10434 /* If we have an outer operation and we just made a shift, it is
10435 possible that we could have simplified the shift were it not
10436 for the outer operation. So try to do the simplification
10439 if (outer_op != UNKNOWN)
10440 x = simplify_shift_const_1 (code, shift_mode, varop, count);
10445 x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
10447 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10448 turn off all the bits that the shift would have turned off. */
10449 if (orig_code == LSHIFTRT && result_mode != shift_mode)
10450 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
10451 GET_MODE_MASK (result_mode) >> orig_count);
10453 /* Do the remainder of the processing in RESULT_MODE. */
10454 x = gen_lowpart_or_truncate (result_mode, x);
10456 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10459 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
10461 if (outer_op != UNKNOWN)
10463 if (GET_RTX_CLASS (outer_op) != RTX_UNARY
10464 && GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
10465 outer_const = trunc_int_for_mode (outer_const, result_mode);
10467 if (outer_op == AND)
10468 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
10469 else if (outer_op == SET)
10471 /* This means that we have determined that the result is
10472 equivalent to a constant. This should be rare. */
10473 if (!side_effects_p (x))
10474 x = GEN_INT (outer_const);
10476 else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
10477 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
10479 x = simplify_gen_binary (outer_op, result_mode, x,
10480 GEN_INT (outer_const));
10486 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10487 The result of the shift is RESULT_MODE. If we cannot simplify it,
10488 return X or, if it is NULL, synthesize the expression with
10489 simplify_gen_binary. Otherwise, return a simplified value.
10491 The shift is normally computed in the widest mode we find in VAROP, as
10492 long as it isn't a different number of words than RESULT_MODE. Exceptions
10493 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10496 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
10497 rtx varop, int count)
10499 rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
10504 x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
10505 if (GET_MODE (x) != result_mode)
10506 x = gen_lowpart (result_mode, x);
10511 /* Like recog, but we receive the address of a pointer to a new pattern.
10512 We try to match the rtx that the pointer points to.
10513 If that fails, we may try to modify or replace the pattern,
10514 storing the replacement into the same pointer object.
10516 Modifications include deletion or addition of CLOBBERs.
10518 PNOTES is a pointer to a location where any REG_UNUSED notes added for
10519 the CLOBBERs are placed.
10521 The value is the final insn code from the pattern ultimately matched,
10525 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
10527 rtx pat = *pnewpat;
10528 int insn_code_number;
10529 int num_clobbers_to_add = 0;
10532 rtx old_notes, old_pat;
10534 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10535 we use to indicate that something didn't match. If we find such a
10536 thing, force rejection. */
10537 if (GET_CODE (pat) == PARALLEL)
10538 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
10539 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
10540 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
10543 old_pat = PATTERN (insn);
10544 old_notes = REG_NOTES (insn);
10545 PATTERN (insn) = pat;
10546 REG_NOTES (insn) = 0;
10548 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10549 if (dump_file && (dump_flags & TDF_DETAILS))
10551 if (insn_code_number < 0)
10552 fputs ("Failed to match this instruction:\n", dump_file);
10554 fputs ("Successfully matched this instruction:\n", dump_file);
10555 print_rtl_single (dump_file, pat);
10558 /* If it isn't, there is the possibility that we previously had an insn
10559 that clobbered some register as a side effect, but the combined
10560 insn doesn't need to do that. So try once more without the clobbers
10561 unless this represents an ASM insn. */
10563 if (insn_code_number < 0 && ! check_asm_operands (pat)
10564 && GET_CODE (pat) == PARALLEL)
10568 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
10569 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
10572 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
10576 SUBST_INT (XVECLEN (pat, 0), pos);
10579 pat = XVECEXP (pat, 0, 0);
10581 PATTERN (insn) = pat;
10582 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10583 if (dump_file && (dump_flags & TDF_DETAILS))
10585 if (insn_code_number < 0)
10586 fputs ("Failed to match this instruction:\n", dump_file);
10588 fputs ("Successfully matched this instruction:\n", dump_file);
10589 print_rtl_single (dump_file, pat);
10592 PATTERN (insn) = old_pat;
10593 REG_NOTES (insn) = old_notes;
10595 /* Recognize all noop sets, these will be killed by followup pass. */
10596 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
10597 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
10599 /* If we had any clobbers to add, make a new pattern than contains
10600 them. Then check to make sure that all of them are dead. */
10601 if (num_clobbers_to_add)
10603 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
10604 rtvec_alloc (GET_CODE (pat) == PARALLEL
10605 ? (XVECLEN (pat, 0)
10606 + num_clobbers_to_add)
10607 : num_clobbers_to_add + 1));
10609 if (GET_CODE (pat) == PARALLEL)
10610 for (i = 0; i < XVECLEN (pat, 0); i++)
10611 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
10613 XVECEXP (newpat, 0, 0) = pat;
10615 add_clobbers (newpat, insn_code_number);
10617 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
10618 i < XVECLEN (newpat, 0); i++)
10620 if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
10621 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
10623 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH)
10625 gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)));
10626 notes = alloc_reg_note (REG_UNUSED,
10627 XEXP (XVECEXP (newpat, 0, i), 0), notes);
10636 return insn_code_number;
10639 /* Like gen_lowpart_general but for use by combine. In combine it
10640 is not possible to create any new pseudoregs. However, it is
10641 safe to create invalid memory addresses, because combine will
10642 try to recognize them and all they will do is make the combine
10645 If for some reason this cannot do its job, an rtx
10646 (clobber (const_int 0)) is returned.
10647 An insn containing that will not be recognized. */
10650 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
10652 enum machine_mode imode = GET_MODE (x);
10653 unsigned int osize = GET_MODE_SIZE (omode);
10654 unsigned int isize = GET_MODE_SIZE (imode);
10657 if (omode == imode)
10660 /* Return identity if this is a CONST or symbolic reference. */
10662 && (GET_CODE (x) == CONST
10663 || GET_CODE (x) == SYMBOL_REF
10664 || GET_CODE (x) == LABEL_REF))
10667 /* We can only support MODE being wider than a word if X is a
10668 constant integer or has a mode the same size. */
10669 if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
10670 && ! ((imode == VOIDmode
10671 && (CONST_INT_P (x)
10672 || GET_CODE (x) == CONST_DOUBLE))
10673 || isize == osize))
10676 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10677 won't know what to do. So we will strip off the SUBREG here and
10678 process normally. */
10679 if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
10681 x = SUBREG_REG (x);
10683 /* For use in case we fall down into the address adjustments
10684 further below, we need to adjust the known mode and size of
10685 x; imode and isize, since we just adjusted x. */
10686 imode = GET_MODE (x);
10688 if (imode == omode)
10691 isize = GET_MODE_SIZE (imode);
10694 result = gen_lowpart_common (omode, x);
10703 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10705 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
10708 /* If we want to refer to something bigger than the original memref,
10709 generate a paradoxical subreg instead. That will force a reload
10710 of the original memref X. */
10712 return gen_rtx_SUBREG (omode, x, 0);
10714 if (WORDS_BIG_ENDIAN)
10715 offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
10717 /* Adjust the address so that the address-after-the-data is
10719 if (BYTES_BIG_ENDIAN)
10720 offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
10722 return adjust_address_nv (x, omode, offset);
10725 /* If X is a comparison operator, rewrite it in a new mode. This
10726 probably won't match, but may allow further simplifications. */
10727 else if (COMPARISON_P (x))
10728 return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
10730 /* If we couldn't simplify X any other way, just enclose it in a
10731 SUBREG. Normally, this SUBREG won't match, but some patterns may
10732 include an explicit SUBREG or we may simplify it further in combine. */
10738 offset = subreg_lowpart_offset (omode, imode);
10739 if (imode == VOIDmode)
10741 imode = int_mode_for_mode (omode);
10742 x = gen_lowpart_common (imode, x);
10746 res = simplify_gen_subreg (omode, x, imode, offset);
10752 return gen_rtx_CLOBBER (omode, const0_rtx);
10755 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10756 comparison code that will be tested.
10758 The result is a possibly different comparison code to use. *POP0 and
10759 *POP1 may be updated.
10761 It is possible that we might detect that a comparison is either always
10762 true or always false. However, we do not perform general constant
10763 folding in combine, so this knowledge isn't useful. Such tautologies
10764 should have been detected earlier. Hence we ignore all such cases. */
10766 static enum rtx_code
10767 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
10773 enum machine_mode mode, tmode;
10775 /* Try a few ways of applying the same transformation to both operands. */
10778 #ifndef WORD_REGISTER_OPERATIONS
10779 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10780 so check specially. */
10781 if (code != GTU && code != GEU && code != LTU && code != LEU
10782 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
10783 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10784 && GET_CODE (XEXP (op1, 0)) == ASHIFT
10785 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
10786 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
10787 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
10788 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
10789 && CONST_INT_P (XEXP (op0, 1))
10790 && XEXP (op0, 1) == XEXP (op1, 1)
10791 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10792 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
10793 && (INTVAL (XEXP (op0, 1))
10794 == (GET_MODE_BITSIZE (GET_MODE (op0))
10795 - (GET_MODE_BITSIZE
10796 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
10798 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
10799 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
10803 /* If both operands are the same constant shift, see if we can ignore the
10804 shift. We can if the shift is a rotate or if the bits shifted out of
10805 this shift are known to be zero for both inputs and if the type of
10806 comparison is compatible with the shift. */
10807 if (GET_CODE (op0) == GET_CODE (op1)
10808 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10809 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
10810 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
10811 && (code != GT && code != LT && code != GE && code != LE))
10812 || (GET_CODE (op0) == ASHIFTRT
10813 && (code != GTU && code != LTU
10814 && code != GEU && code != LEU)))
10815 && CONST_INT_P (XEXP (op0, 1))
10816 && INTVAL (XEXP (op0, 1)) >= 0
10817 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10818 && XEXP (op0, 1) == XEXP (op1, 1))
10820 enum machine_mode mode = GET_MODE (op0);
10821 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10822 int shift_count = INTVAL (XEXP (op0, 1));
10824 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
10825 mask &= (mask >> shift_count) << shift_count;
10826 else if (GET_CODE (op0) == ASHIFT)
10827 mask = (mask & (mask << shift_count)) >> shift_count;
10829 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
10830 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
10831 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
10836 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10837 SUBREGs are of the same mode, and, in both cases, the AND would
10838 be redundant if the comparison was done in the narrower mode,
10839 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10840 and the operand's possibly nonzero bits are 0xffffff01; in that case
10841 if we only care about QImode, we don't need the AND). This case
10842 occurs if the output mode of an scc insn is not SImode and
10843 STORE_FLAG_VALUE == 1 (e.g., the 386).
10845 Similarly, check for a case where the AND's are ZERO_EXTEND
10846 operations from some narrower mode even though a SUBREG is not
10849 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
10850 && CONST_INT_P (XEXP (op0, 1))
10851 && CONST_INT_P (XEXP (op1, 1)))
10853 rtx inner_op0 = XEXP (op0, 0);
10854 rtx inner_op1 = XEXP (op1, 0);
10855 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
10856 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
10859 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
10860 && (GET_MODE_SIZE (GET_MODE (inner_op0))
10861 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
10862 && (GET_MODE (SUBREG_REG (inner_op0))
10863 == GET_MODE (SUBREG_REG (inner_op1)))
10864 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
10865 <= HOST_BITS_PER_WIDE_INT)
10866 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
10867 GET_MODE (SUBREG_REG (inner_op0)))))
10868 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
10869 GET_MODE (SUBREG_REG (inner_op1))))))
10871 op0 = SUBREG_REG (inner_op0);
10872 op1 = SUBREG_REG (inner_op1);
10874 /* The resulting comparison is always unsigned since we masked
10875 off the original sign bit. */
10876 code = unsigned_condition (code);
10882 for (tmode = GET_CLASS_NARROWEST_MODE
10883 (GET_MODE_CLASS (GET_MODE (op0)));
10884 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
10885 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
10887 op0 = gen_lowpart (tmode, inner_op0);
10888 op1 = gen_lowpart (tmode, inner_op1);
10889 code = unsigned_condition (code);
10898 /* If both operands are NOT, we can strip off the outer operation
10899 and adjust the comparison code for swapped operands; similarly for
10900 NEG, except that this must be an equality comparison. */
10901 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
10902 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
10903 && (code == EQ || code == NE)))
10904 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
10910 /* If the first operand is a constant, swap the operands and adjust the
10911 comparison code appropriately, but don't do this if the second operand
10912 is already a constant integer. */
10913 if (swap_commutative_operands_p (op0, op1))
10915 tem = op0, op0 = op1, op1 = tem;
10916 code = swap_condition (code);
10919 /* We now enter a loop during which we will try to simplify the comparison.
10920 For the most part, we only are concerned with comparisons with zero,
10921 but some things may really be comparisons with zero but not start
10922 out looking that way. */
10924 while (CONST_INT_P (op1))
10926 enum machine_mode mode = GET_MODE (op0);
10927 unsigned int mode_width = GET_MODE_BITSIZE (mode);
10928 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10929 int equality_comparison_p;
10930 int sign_bit_comparison_p;
10931 int unsigned_comparison_p;
10932 HOST_WIDE_INT const_op;
10934 /* We only want to handle integral modes. This catches VOIDmode,
10935 CCmode, and the floating-point modes. An exception is that we
10936 can handle VOIDmode if OP0 is a COMPARE or a comparison
10939 if (GET_MODE_CLASS (mode) != MODE_INT
10940 && ! (mode == VOIDmode
10941 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
10944 /* Get the constant we are comparing against and turn off all bits
10945 not on in our mode. */
10946 const_op = INTVAL (op1);
10947 if (mode != VOIDmode)
10948 const_op = trunc_int_for_mode (const_op, mode);
10949 op1 = GEN_INT (const_op);
10951 /* If we are comparing against a constant power of two and the value
10952 being compared can only have that single bit nonzero (e.g., it was
10953 `and'ed with that bit), we can replace this with a comparison
10956 && (code == EQ || code == NE || code == GE || code == GEU
10957 || code == LT || code == LTU)
10958 && mode_width <= HOST_BITS_PER_WIDE_INT
10959 && exact_log2 (const_op) >= 0
10960 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10962 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10963 op1 = const0_rtx, const_op = 0;
10966 /* Similarly, if we are comparing a value known to be either -1 or
10967 0 with -1, change it to the opposite comparison against zero. */
10970 && (code == EQ || code == NE || code == GT || code == LE
10971 || code == GEU || code == LTU)
10972 && num_sign_bit_copies (op0, mode) == mode_width)
10974 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10975 op1 = const0_rtx, const_op = 0;
10978 /* Do some canonicalizations based on the comparison code. We prefer
10979 comparisons against zero and then prefer equality comparisons.
10980 If we can reduce the size of a constant, we will do that too. */
10985 /* < C is equivalent to <= (C - 1) */
10989 op1 = GEN_INT (const_op);
10991 /* ... fall through to LE case below. */
10997 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11001 op1 = GEN_INT (const_op);
11005 /* If we are doing a <= 0 comparison on a value known to have
11006 a zero sign bit, we can replace this with == 0. */
11007 else if (const_op == 0
11008 && mode_width <= HOST_BITS_PER_WIDE_INT
11009 && (nonzero_bits (op0, mode)
11010 & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11016 /* >= C is equivalent to > (C - 1). */
11020 op1 = GEN_INT (const_op);
11022 /* ... fall through to GT below. */
11028 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11032 op1 = GEN_INT (const_op);
11036 /* If we are doing a > 0 comparison on a value known to have
11037 a zero sign bit, we can replace this with != 0. */
11038 else if (const_op == 0
11039 && mode_width <= HOST_BITS_PER_WIDE_INT
11040 && (nonzero_bits (op0, mode)
11041 & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11047 /* < C is equivalent to <= (C - 1). */
11051 op1 = GEN_INT (const_op);
11053 /* ... fall through ... */
11056 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11057 else if (mode_width <= HOST_BITS_PER_WIDE_INT
11058 && (unsigned HOST_WIDE_INT) const_op
11059 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1))
11061 const_op = 0, op1 = const0_rtx;
11069 /* unsigned <= 0 is equivalent to == 0 */
11073 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11074 else if (mode_width <= HOST_BITS_PER_WIDE_INT
11075 && (unsigned HOST_WIDE_INT) const_op
11076 == ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
11078 const_op = 0, op1 = const0_rtx;
11084 /* >= C is equivalent to > (C - 1). */
11088 op1 = GEN_INT (const_op);
11090 /* ... fall through ... */
11093 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11094 else if (mode_width <= HOST_BITS_PER_WIDE_INT
11095 && (unsigned HOST_WIDE_INT) const_op
11096 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1))
11098 const_op = 0, op1 = const0_rtx;
11106 /* unsigned > 0 is equivalent to != 0 */
11110 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11111 else if (mode_width <= HOST_BITS_PER_WIDE_INT
11112 && (unsigned HOST_WIDE_INT) const_op
11113 == ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
11115 const_op = 0, op1 = const0_rtx;
11124 /* Compute some predicates to simplify code below. */
11126 equality_comparison_p = (code == EQ || code == NE);
11127 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
11128 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
11131 /* If this is a sign bit comparison and we can do arithmetic in
11132 MODE, say that we will only be needing the sign bit of OP0. */
11133 if (sign_bit_comparison_p
11134 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11135 op0 = force_to_mode (op0, mode,
11136 (unsigned HOST_WIDE_INT) 1
11137 << (GET_MODE_BITSIZE (mode) - 1),
11140 /* Now try cases based on the opcode of OP0. If none of the cases
11141 does a "continue", we exit this loop immediately after the
11144 switch (GET_CODE (op0))
11147 /* If we are extracting a single bit from a variable position in
11148 a constant that has only a single bit set and are comparing it
11149 with zero, we can convert this into an equality comparison
11150 between the position and the location of the single bit. */
11151 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11152 have already reduced the shift count modulo the word size. */
11153 if (!SHIFT_COUNT_TRUNCATED
11154 && CONST_INT_P (XEXP (op0, 0))
11155 && XEXP (op0, 1) == const1_rtx
11156 && equality_comparison_p && const_op == 0
11157 && (i = exact_log2 (UINTVAL (XEXP (op0, 0)))) >= 0)
11159 if (BITS_BIG_ENDIAN)
11161 enum machine_mode new_mode
11162 = mode_for_extraction (EP_extzv, 1);
11163 if (new_mode == MAX_MACHINE_MODE)
11164 i = BITS_PER_WORD - 1 - i;
11168 i = (GET_MODE_BITSIZE (mode) - 1 - i);
11172 op0 = XEXP (op0, 2);
11176 /* Result is nonzero iff shift count is equal to I. */
11177 code = reverse_condition (code);
11181 /* ... fall through ... */
11184 tem = expand_compound_operation (op0);
11193 /* If testing for equality, we can take the NOT of the constant. */
11194 if (equality_comparison_p
11195 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
11197 op0 = XEXP (op0, 0);
11202 /* If just looking at the sign bit, reverse the sense of the
11204 if (sign_bit_comparison_p)
11206 op0 = XEXP (op0, 0);
11207 code = (code == GE ? LT : GE);
11213 /* If testing for equality, we can take the NEG of the constant. */
11214 if (equality_comparison_p
11215 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
11217 op0 = XEXP (op0, 0);
11222 /* The remaining cases only apply to comparisons with zero. */
11226 /* When X is ABS or is known positive,
11227 (neg X) is < 0 if and only if X != 0. */
11229 if (sign_bit_comparison_p
11230 && (GET_CODE (XEXP (op0, 0)) == ABS
11231 || (mode_width <= HOST_BITS_PER_WIDE_INT
11232 && (nonzero_bits (XEXP (op0, 0), mode)
11233 & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11236 op0 = XEXP (op0, 0);
11237 code = (code == LT ? NE : EQ);
11241 /* If we have NEG of something whose two high-order bits are the
11242 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11243 if (num_sign_bit_copies (op0, mode) >= 2)
11245 op0 = XEXP (op0, 0);
11246 code = swap_condition (code);
11252 /* If we are testing equality and our count is a constant, we
11253 can perform the inverse operation on our RHS. */
11254 if (equality_comparison_p && CONST_INT_P (XEXP (op0, 1))
11255 && (tem = simplify_binary_operation (ROTATERT, mode,
11256 op1, XEXP (op0, 1))) != 0)
11258 op0 = XEXP (op0, 0);
11263 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11264 a particular bit. Convert it to an AND of a constant of that
11265 bit. This will be converted into a ZERO_EXTRACT. */
11266 if (const_op == 0 && sign_bit_comparison_p
11267 && CONST_INT_P (XEXP (op0, 1))
11268 && mode_width <= HOST_BITS_PER_WIDE_INT)
11270 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11271 ((unsigned HOST_WIDE_INT) 1
11273 - INTVAL (XEXP (op0, 1)))));
11274 code = (code == LT ? NE : EQ);
11278 /* Fall through. */
11281 /* ABS is ignorable inside an equality comparison with zero. */
11282 if (const_op == 0 && equality_comparison_p)
11284 op0 = XEXP (op0, 0);
11290 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11291 (compare FOO CONST) if CONST fits in FOO's mode and we
11292 are either testing inequality or have an unsigned
11293 comparison with ZERO_EXTEND or a signed comparison with
11294 SIGN_EXTEND. But don't do it if we don't have a compare
11295 insn of the given mode, since we'd have to revert it
11296 later on, and then we wouldn't know whether to sign- or
11298 mode = GET_MODE (XEXP (op0, 0));
11299 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11300 && ! unsigned_comparison_p
11301 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11302 && ((unsigned HOST_WIDE_INT) const_op
11303 < (((unsigned HOST_WIDE_INT) 1
11304 << (GET_MODE_BITSIZE (mode) - 1))))
11305 && have_insn_for (COMPARE, mode))
11307 op0 = XEXP (op0, 0);
11313 /* Check for the case where we are comparing A - C1 with C2, that is
11315 (subreg:MODE (plus (A) (-C1))) op (C2)
11317 with C1 a constant, and try to lift the SUBREG, i.e. to do the
11318 comparison in the wider mode. One of the following two conditions
11319 must be true in order for this to be valid:
11321 1. The mode extension results in the same bit pattern being added
11322 on both sides and the comparison is equality or unsigned. As
11323 C2 has been truncated to fit in MODE, the pattern can only be
11326 2. The mode extension results in the sign bit being copied on
11329 The difficulty here is that we have predicates for A but not for
11330 (A - C1) so we need to check that C1 is within proper bounds so
11331 as to perturbate A as little as possible. */
11333 if (mode_width <= HOST_BITS_PER_WIDE_INT
11334 && subreg_lowpart_p (op0)
11335 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) > mode_width
11336 && GET_CODE (SUBREG_REG (op0)) == PLUS
11337 && CONST_INT_P (XEXP (SUBREG_REG (op0), 1)))
11339 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
11340 rtx a = XEXP (SUBREG_REG (op0), 0);
11341 HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
11344 && (unsigned HOST_WIDE_INT) c1
11345 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
11346 && (equality_comparison_p || unsigned_comparison_p)
11347 /* (A - C1) zero-extends if it is positive and sign-extends
11348 if it is negative, C2 both zero- and sign-extends. */
11349 && ((0 == (nonzero_bits (a, inner_mode)
11350 & ~GET_MODE_MASK (mode))
11352 /* (A - C1) sign-extends if it is positive and 1-extends
11353 if it is negative, C2 both sign- and 1-extends. */
11354 || (num_sign_bit_copies (a, inner_mode)
11355 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
11358 || ((unsigned HOST_WIDE_INT) c1
11359 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
11360 /* (A - C1) always sign-extends, like C2. */
11361 && num_sign_bit_copies (a, inner_mode)
11362 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
11363 - (mode_width - 1))))
11365 op0 = SUBREG_REG (op0);
11370 /* If the inner mode is narrower and we are extracting the low part,
11371 we can treat the SUBREG as if it were a ZERO_EXTEND. */
11372 if (subreg_lowpart_p (op0)
11373 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
11374 /* Fall through */ ;
11378 /* ... fall through ... */
11381 mode = GET_MODE (XEXP (op0, 0));
11382 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11383 && (unsigned_comparison_p || equality_comparison_p)
11384 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11385 && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode))
11386 && have_insn_for (COMPARE, mode))
11388 op0 = XEXP (op0, 0);
11394 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
11395 this for equality comparisons due to pathological cases involving
11397 if (equality_comparison_p
11398 && 0 != (tem = simplify_binary_operation (MINUS, mode,
11399 op1, XEXP (op0, 1))))
11401 op0 = XEXP (op0, 0);
11406 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
11407 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
11408 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
11410 op0 = XEXP (XEXP (op0, 0), 0);
11411 code = (code == LT ? EQ : NE);
11417 /* We used to optimize signed comparisons against zero, but that
11418 was incorrect. Unsigned comparisons against zero (GTU, LEU)
11419 arrive here as equality comparisons, or (GEU, LTU) are
11420 optimized away. No need to special-case them. */
11422 /* (eq (minus A B) C) -> (eq A (plus B C)) or
11423 (eq B (minus A C)), whichever simplifies. We can only do
11424 this for equality comparisons due to pathological cases involving
11426 if (equality_comparison_p
11427 && 0 != (tem = simplify_binary_operation (PLUS, mode,
11428 XEXP (op0, 1), op1)))
11430 op0 = XEXP (op0, 0);
11435 if (equality_comparison_p
11436 && 0 != (tem = simplify_binary_operation (MINUS, mode,
11437 XEXP (op0, 0), op1)))
11439 op0 = XEXP (op0, 1);
11444 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11445 of bits in X minus 1, is one iff X > 0. */
11446 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
11447 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11448 && UINTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
11449 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11451 op0 = XEXP (op0, 1);
11452 code = (code == GE ? LE : GT);
11458 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11459 if C is zero or B is a constant. */
11460 if (equality_comparison_p
11461 && 0 != (tem = simplify_binary_operation (XOR, mode,
11462 XEXP (op0, 1), op1)))
11464 op0 = XEXP (op0, 0);
11471 case UNEQ: case LTGT:
11472 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
11473 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
11474 case UNORDERED: case ORDERED:
11475 /* We can't do anything if OP0 is a condition code value, rather
11476 than an actual data value. */
11478 || CC0_P (XEXP (op0, 0))
11479 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
11482 /* Get the two operands being compared. */
11483 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
11484 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
11486 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
11488 /* Check for the cases where we simply want the result of the
11489 earlier test or the opposite of that result. */
11490 if (code == NE || code == EQ
11491 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
11492 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11493 && (STORE_FLAG_VALUE
11494 & (((unsigned HOST_WIDE_INT) 1
11495 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
11496 && (code == LT || code == GE)))
11498 enum rtx_code new_code;
11499 if (code == LT || code == NE)
11500 new_code = GET_CODE (op0);
11502 new_code = reversed_comparison_code (op0, NULL);
11504 if (new_code != UNKNOWN)
11515 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11517 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
11518 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
11519 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11521 op0 = XEXP (op0, 1);
11522 code = (code == GE ? GT : LE);
11528 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11529 will be converted to a ZERO_EXTRACT later. */
11530 if (const_op == 0 && equality_comparison_p
11531 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11532 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
11534 op0 = gen_rtx_LSHIFTRT (mode, XEXP (op0, 1),
11535 XEXP (XEXP (op0, 0), 1));
11536 op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
11540 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11541 zero and X is a comparison and C1 and C2 describe only bits set
11542 in STORE_FLAG_VALUE, we can compare with X. */
11543 if (const_op == 0 && equality_comparison_p
11544 && mode_width <= HOST_BITS_PER_WIDE_INT
11545 && CONST_INT_P (XEXP (op0, 1))
11546 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
11547 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11548 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
11549 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
11551 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11552 << INTVAL (XEXP (XEXP (op0, 0), 1)));
11553 if ((~STORE_FLAG_VALUE & mask) == 0
11554 && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
11555 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
11556 && COMPARISON_P (tem))))
11558 op0 = XEXP (XEXP (op0, 0), 0);
11563 /* If we are doing an equality comparison of an AND of a bit equal
11564 to the sign bit, replace this with a LT or GE comparison of
11565 the underlying value. */
11566 if (equality_comparison_p
11568 && CONST_INT_P (XEXP (op0, 1))
11569 && mode_width <= HOST_BITS_PER_WIDE_INT
11570 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11571 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11573 op0 = XEXP (op0, 0);
11574 code = (code == EQ ? GE : LT);
11578 /* If this AND operation is really a ZERO_EXTEND from a narrower
11579 mode, the constant fits within that mode, and this is either an
11580 equality or unsigned comparison, try to do this comparison in
11585 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11586 -> (ne:DI (reg:SI 4) (const_int 0))
11588 unless TRULY_NOOP_TRUNCATION allows it or the register is
11589 known to hold a value of the required mode the
11590 transformation is invalid. */
11591 if ((equality_comparison_p || unsigned_comparison_p)
11592 && CONST_INT_P (XEXP (op0, 1))
11593 && (i = exact_log2 ((UINTVAL (XEXP (op0, 1))
11594 & GET_MODE_MASK (mode))
11596 && const_op >> i == 0
11597 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode
11598 && (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
11599 GET_MODE_BITSIZE (GET_MODE (op0)))
11600 || (REG_P (XEXP (op0, 0))
11601 && reg_truncated_to_mode (tmode, XEXP (op0, 0)))))
11603 op0 = gen_lowpart (tmode, XEXP (op0, 0));
11607 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11608 fits in both M1 and M2 and the SUBREG is either paradoxical
11609 or represents the low part, permute the SUBREG and the AND
11611 if (GET_CODE (XEXP (op0, 0)) == SUBREG)
11613 unsigned HOST_WIDE_INT c1;
11614 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
11615 /* Require an integral mode, to avoid creating something like
11617 if (SCALAR_INT_MODE_P (tmode)
11618 /* It is unsafe to commute the AND into the SUBREG if the
11619 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11620 not defined. As originally written the upper bits
11621 have a defined value due to the AND operation.
11622 However, if we commute the AND inside the SUBREG then
11623 they no longer have defined values and the meaning of
11624 the code has been changed. */
11626 #ifdef WORD_REGISTER_OPERATIONS
11627 || (mode_width > GET_MODE_BITSIZE (tmode)
11628 && mode_width <= BITS_PER_WORD)
11630 || (mode_width <= GET_MODE_BITSIZE (tmode)
11631 && subreg_lowpart_p (XEXP (op0, 0))))
11632 && CONST_INT_P (XEXP (op0, 1))
11633 && mode_width <= HOST_BITS_PER_WIDE_INT
11634 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
11635 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
11636 && (c1 & ~GET_MODE_MASK (tmode)) == 0
11638 && c1 != GET_MODE_MASK (tmode))
11640 op0 = simplify_gen_binary (AND, tmode,
11641 SUBREG_REG (XEXP (op0, 0)),
11642 gen_int_mode (c1, tmode));
11643 op0 = gen_lowpart (mode, op0);
11648 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
11649 if (const_op == 0 && equality_comparison_p
11650 && XEXP (op0, 1) == const1_rtx
11651 && GET_CODE (XEXP (op0, 0)) == NOT)
11653 op0 = simplify_and_const_int (NULL_RTX, mode,
11654 XEXP (XEXP (op0, 0), 0), 1);
11655 code = (code == NE ? EQ : NE);
11659 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11660 (eq (and (lshiftrt X) 1) 0).
11661 Also handle the case where (not X) is expressed using xor. */
11662 if (const_op == 0 && equality_comparison_p
11663 && XEXP (op0, 1) == const1_rtx
11664 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
11666 rtx shift_op = XEXP (XEXP (op0, 0), 0);
11667 rtx shift_count = XEXP (XEXP (op0, 0), 1);
11669 if (GET_CODE (shift_op) == NOT
11670 || (GET_CODE (shift_op) == XOR
11671 && CONST_INT_P (XEXP (shift_op, 1))
11672 && CONST_INT_P (shift_count)
11673 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
11674 && (UINTVAL (XEXP (shift_op, 1))
11675 == (unsigned HOST_WIDE_INT) 1
11676 << INTVAL (shift_count))))
11679 = gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count);
11680 op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
11681 code = (code == NE ? EQ : NE);
11688 /* If we have (compare (ashift FOO N) (const_int C)) and
11689 the high order N bits of FOO (N+1 if an inequality comparison)
11690 are known to be zero, we can do this by comparing FOO with C
11691 shifted right N bits so long as the low-order N bits of C are
11693 if (CONST_INT_P (XEXP (op0, 1))
11694 && INTVAL (XEXP (op0, 1)) >= 0
11695 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
11696 < HOST_BITS_PER_WIDE_INT)
11697 && (((unsigned HOST_WIDE_INT) const_op
11698 & (((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1)))
11700 && mode_width <= HOST_BITS_PER_WIDE_INT
11701 && (nonzero_bits (XEXP (op0, 0), mode)
11702 & ~(mask >> (INTVAL (XEXP (op0, 1))
11703 + ! equality_comparison_p))) == 0)
11705 /* We must perform a logical shift, not an arithmetic one,
11706 as we want the top N bits of C to be zero. */
11707 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
11709 temp >>= INTVAL (XEXP (op0, 1));
11710 op1 = gen_int_mode (temp, mode);
11711 op0 = XEXP (op0, 0);
11715 /* If we are doing a sign bit comparison, it means we are testing
11716 a particular bit. Convert it to the appropriate AND. */
11717 if (sign_bit_comparison_p && CONST_INT_P (XEXP (op0, 1))
11718 && mode_width <= HOST_BITS_PER_WIDE_INT)
11720 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11721 ((unsigned HOST_WIDE_INT) 1
11723 - INTVAL (XEXP (op0, 1)))));
11724 code = (code == LT ? NE : EQ);
11728 /* If this an equality comparison with zero and we are shifting
11729 the low bit to the sign bit, we can convert this to an AND of the
11731 if (const_op == 0 && equality_comparison_p
11732 && CONST_INT_P (XEXP (op0, 1))
11733 && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
11735 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), 1);
11741 /* If this is an equality comparison with zero, we can do this
11742 as a logical shift, which might be much simpler. */
11743 if (equality_comparison_p && const_op == 0
11744 && CONST_INT_P (XEXP (op0, 1)))
11746 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
11748 INTVAL (XEXP (op0, 1)));
11752 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11753 do the comparison in a narrower mode. */
11754 if (! unsigned_comparison_p
11755 && CONST_INT_P (XEXP (op0, 1))
11756 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11757 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11758 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11759 MODE_INT, 1)) != BLKmode
11760 && (((unsigned HOST_WIDE_INT) const_op
11761 + (GET_MODE_MASK (tmode) >> 1) + 1)
11762 <= GET_MODE_MASK (tmode)))
11764 op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
11768 /* Likewise if OP0 is a PLUS of a sign extension with a
11769 constant, which is usually represented with the PLUS
11770 between the shifts. */
11771 if (! unsigned_comparison_p
11772 && CONST_INT_P (XEXP (op0, 1))
11773 && GET_CODE (XEXP (op0, 0)) == PLUS
11774 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11775 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
11776 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
11777 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11778 MODE_INT, 1)) != BLKmode
11779 && (((unsigned HOST_WIDE_INT) const_op
11780 + (GET_MODE_MASK (tmode) >> 1) + 1)
11781 <= GET_MODE_MASK (tmode)))
11783 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
11784 rtx add_const = XEXP (XEXP (op0, 0), 1);
11785 rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
11786 add_const, XEXP (op0, 1));
11788 op0 = simplify_gen_binary (PLUS, tmode,
11789 gen_lowpart (tmode, inner),
11794 /* ... fall through ... */
11796 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11797 the low order N bits of FOO are known to be zero, we can do this
11798 by comparing FOO with C shifted left N bits so long as no
11799 overflow occurs. Even if the low order N bits of FOO aren't known
11800 to be zero, if the comparison is >= or < we can use the same
11801 optimization and for > or <= by setting all the low
11802 order N bits in the comparison constant. */
11803 if (CONST_INT_P (XEXP (op0, 1))
11804 && INTVAL (XEXP (op0, 1)) > 0
11805 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11806 && mode_width <= HOST_BITS_PER_WIDE_INT
11807 && (((unsigned HOST_WIDE_INT) const_op
11808 + (GET_CODE (op0) != LSHIFTRT
11809 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
11812 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
11814 unsigned HOST_WIDE_INT low_bits
11815 = (nonzero_bits (XEXP (op0, 0), mode)
11816 & (((unsigned HOST_WIDE_INT) 1
11817 << INTVAL (XEXP (op0, 1))) - 1));
11818 if (low_bits == 0 || !equality_comparison_p)
11820 /* If the shift was logical, then we must make the condition
11822 if (GET_CODE (op0) == LSHIFTRT)
11823 code = unsigned_condition (code);
11825 const_op <<= INTVAL (XEXP (op0, 1));
11827 && (code == GT || code == GTU
11828 || code == LE || code == LEU))
11830 |= (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1);
11831 op1 = GEN_INT (const_op);
11832 op0 = XEXP (op0, 0);
11837 /* If we are using this shift to extract just the sign bit, we
11838 can replace this with an LT or GE comparison. */
11840 && (equality_comparison_p || sign_bit_comparison_p)
11841 && CONST_INT_P (XEXP (op0, 1))
11842 && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
11844 op0 = XEXP (op0, 0);
11845 code = (code == NE || code == GT ? LT : GE);
11857 /* Now make any compound operations involved in this comparison. Then,
11858 check for an outmost SUBREG on OP0 that is not doing anything or is
11859 paradoxical. The latter transformation must only be performed when
11860 it is known that the "extra" bits will be the same in op0 and op1 or
11861 that they don't matter. There are three cases to consider:
11863 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11864 care bits and we can assume they have any convenient value. So
11865 making the transformation is safe.
11867 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11868 In this case the upper bits of op0 are undefined. We should not make
11869 the simplification in that case as we do not know the contents of
11872 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11873 UNKNOWN. In that case we know those bits are zeros or ones. We must
11874 also be sure that they are the same as the upper bits of op1.
11876 We can never remove a SUBREG for a non-equality comparison because
11877 the sign bit is in a different place in the underlying object. */
11879 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
11880 op1 = make_compound_operation (op1, SET);
11882 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11883 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11884 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
11885 && (code == NE || code == EQ))
11887 if (GET_MODE_SIZE (GET_MODE (op0))
11888 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
11890 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11892 if (REG_P (SUBREG_REG (op0)))
11894 op0 = SUBREG_REG (op0);
11895 op1 = gen_lowpart (GET_MODE (op0), op1);
11898 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
11899 <= HOST_BITS_PER_WIDE_INT)
11900 && (nonzero_bits (SUBREG_REG (op0),
11901 GET_MODE (SUBREG_REG (op0)))
11902 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11904 tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
11906 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11907 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11908 op0 = SUBREG_REG (op0), op1 = tem;
11912 /* We now do the opposite procedure: Some machines don't have compare
11913 insns in all modes. If OP0's mode is an integer mode smaller than a
11914 word and we can't do a compare in that mode, see if there is a larger
11915 mode for which we can do the compare. There are a number of cases in
11916 which we can use the wider mode. */
11918 mode = GET_MODE (op0);
11919 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11920 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11921 && ! have_insn_for (COMPARE, mode))
11922 for (tmode = GET_MODE_WIDER_MODE (mode);
11924 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
11925 tmode = GET_MODE_WIDER_MODE (tmode))
11926 if (have_insn_for (COMPARE, tmode))
11930 /* If this is a test for negative, we can make an explicit
11931 test of the sign bit. Test this first so we can use
11932 a paradoxical subreg to extend OP0. */
11934 if (op1 == const0_rtx && (code == LT || code == GE)
11935 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11937 op0 = simplify_gen_binary (AND, tmode,
11938 gen_lowpart (tmode, op0),
11939 GEN_INT ((unsigned HOST_WIDE_INT) 1
11940 << (GET_MODE_BITSIZE (mode)
11942 code = (code == LT) ? NE : EQ;
11946 /* If the only nonzero bits in OP0 and OP1 are those in the
11947 narrower mode and this is an equality or unsigned comparison,
11948 we can use the wider mode. Similarly for sign-extended
11949 values, in which case it is true for all comparisons. */
11950 zero_extended = ((code == EQ || code == NE
11951 || code == GEU || code == GTU
11952 || code == LEU || code == LTU)
11953 && (nonzero_bits (op0, tmode)
11954 & ~GET_MODE_MASK (mode)) == 0
11955 && ((CONST_INT_P (op1)
11956 || (nonzero_bits (op1, tmode)
11957 & ~GET_MODE_MASK (mode)) == 0)));
11960 || ((num_sign_bit_copies (op0, tmode)
11961 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11962 - GET_MODE_BITSIZE (mode)))
11963 && (num_sign_bit_copies (op1, tmode)
11964 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11965 - GET_MODE_BITSIZE (mode)))))
11967 /* If OP0 is an AND and we don't have an AND in MODE either,
11968 make a new AND in the proper mode. */
11969 if (GET_CODE (op0) == AND
11970 && !have_insn_for (AND, mode))
11971 op0 = simplify_gen_binary (AND, tmode,
11972 gen_lowpart (tmode,
11974 gen_lowpart (tmode,
11980 op0 = simplify_gen_unary (ZERO_EXTEND, tmode, op0, mode);
11981 op1 = simplify_gen_unary (ZERO_EXTEND, tmode, op1, mode);
11985 op0 = simplify_gen_unary (SIGN_EXTEND, tmode, op0, mode);
11986 op1 = simplify_gen_unary (SIGN_EXTEND, tmode, op1, mode);
11993 #ifdef CANONICALIZE_COMPARISON
11994 /* If this machine only supports a subset of valid comparisons, see if we
11995 can convert an unsupported one into a supported one. */
11996 CANONICALIZE_COMPARISON (code, op0, op1);
12005 /* Utility function for record_value_for_reg. Count number of
12010 enum rtx_code code = GET_CODE (x);
12014 if (GET_RTX_CLASS (code) == '2'
12015 || GET_RTX_CLASS (code) == 'c')
12017 rtx x0 = XEXP (x, 0);
12018 rtx x1 = XEXP (x, 1);
12021 return 1 + 2 * count_rtxs (x0);
12023 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
12024 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
12025 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12026 return 2 + 2 * count_rtxs (x0)
12027 + count_rtxs (x == XEXP (x1, 0)
12028 ? XEXP (x1, 1) : XEXP (x1, 0));
12030 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
12031 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
12032 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12033 return 2 + 2 * count_rtxs (x1)
12034 + count_rtxs (x == XEXP (x0, 0)
12035 ? XEXP (x0, 1) : XEXP (x0, 0));
12038 fmt = GET_RTX_FORMAT (code);
12039 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12041 ret += count_rtxs (XEXP (x, i));
12042 else if (fmt[i] == 'E')
12043 for (j = 0; j < XVECLEN (x, i); j++)
12044 ret += count_rtxs (XVECEXP (x, i, j));
12049 /* Utility function for following routine. Called when X is part of a value
12050 being stored into last_set_value. Sets last_set_table_tick
12051 for each register mentioned. Similar to mention_regs in cse.c */
12054 update_table_tick (rtx x)
12056 enum rtx_code code = GET_CODE (x);
12057 const char *fmt = GET_RTX_FORMAT (code);
12062 unsigned int regno = REGNO (x);
12063 unsigned int endregno = END_REGNO (x);
12066 for (r = regno; r < endregno; r++)
12068 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, r);
12069 rsp->last_set_table_tick = label_tick;
12075 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12078 /* Check for identical subexpressions. If x contains
12079 identical subexpression we only have to traverse one of
12081 if (i == 0 && ARITHMETIC_P (x))
12083 /* Note that at this point x1 has already been
12085 rtx x0 = XEXP (x, 0);
12086 rtx x1 = XEXP (x, 1);
12088 /* If x0 and x1 are identical then there is no need to
12093 /* If x0 is identical to a subexpression of x1 then while
12094 processing x1, x0 has already been processed. Thus we
12095 are done with x. */
12096 if (ARITHMETIC_P (x1)
12097 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12100 /* If x1 is identical to a subexpression of x0 then we
12101 still have to process the rest of x0. */
12102 if (ARITHMETIC_P (x0)
12103 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12105 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
12110 update_table_tick (XEXP (x, i));
12112 else if (fmt[i] == 'E')
12113 for (j = 0; j < XVECLEN (x, i); j++)
12114 update_table_tick (XVECEXP (x, i, j));
12117 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12118 are saying that the register is clobbered and we no longer know its
12119 value. If INSN is zero, don't update reg_stat[].last_set; this is
12120 only permitted with VALUE also zero and is used to invalidate the
12124 record_value_for_reg (rtx reg, rtx insn, rtx value)
12126 unsigned int regno = REGNO (reg);
12127 unsigned int endregno = END_REGNO (reg);
12129 reg_stat_type *rsp;
12131 /* If VALUE contains REG and we have a previous value for REG, substitute
12132 the previous value. */
12133 if (value && insn && reg_overlap_mentioned_p (reg, value))
12137 /* Set things up so get_last_value is allowed to see anything set up to
12139 subst_low_luid = DF_INSN_LUID (insn);
12140 tem = get_last_value (reg);
12142 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12143 it isn't going to be useful and will take a lot of time to process,
12144 so just use the CLOBBER. */
12148 if (ARITHMETIC_P (tem)
12149 && GET_CODE (XEXP (tem, 0)) == CLOBBER
12150 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
12151 tem = XEXP (tem, 0);
12152 else if (count_occurrences (value, reg, 1) >= 2)
12154 /* If there are two or more occurrences of REG in VALUE,
12155 prevent the value from growing too much. */
12156 if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
12157 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
12160 value = replace_rtx (copy_rtx (value), reg, tem);
12164 /* For each register modified, show we don't know its value, that
12165 we don't know about its bitwise content, that its value has been
12166 updated, and that we don't know the location of the death of the
12168 for (i = regno; i < endregno; i++)
12170 rsp = VEC_index (reg_stat_type, reg_stat, i);
12173 rsp->last_set = insn;
12175 rsp->last_set_value = 0;
12176 rsp->last_set_mode = VOIDmode;
12177 rsp->last_set_nonzero_bits = 0;
12178 rsp->last_set_sign_bit_copies = 0;
12179 rsp->last_death = 0;
12180 rsp->truncated_to_mode = VOIDmode;
12183 /* Mark registers that are being referenced in this value. */
12185 update_table_tick (value);
12187 /* Now update the status of each register being set.
12188 If someone is using this register in this block, set this register
12189 to invalid since we will get confused between the two lives in this
12190 basic block. This makes using this register always invalid. In cse, we
12191 scan the table to invalidate all entries using this register, but this
12192 is too much work for us. */
12194 for (i = regno; i < endregno; i++)
12196 rsp = VEC_index (reg_stat_type, reg_stat, i);
12197 rsp->last_set_label = label_tick;
12199 || (value && rsp->last_set_table_tick >= label_tick_ebb_start))
12200 rsp->last_set_invalid = 1;
12202 rsp->last_set_invalid = 0;
12205 /* The value being assigned might refer to X (like in "x++;"). In that
12206 case, we must replace it with (clobber (const_int 0)) to prevent
12208 rsp = VEC_index (reg_stat_type, reg_stat, regno);
12209 if (value && !get_last_value_validate (&value, insn, label_tick, 0))
12211 value = copy_rtx (value);
12212 if (!get_last_value_validate (&value, insn, label_tick, 1))
12216 /* For the main register being modified, update the value, the mode, the
12217 nonzero bits, and the number of sign bit copies. */
12219 rsp->last_set_value = value;
12223 enum machine_mode mode = GET_MODE (reg);
12224 subst_low_luid = DF_INSN_LUID (insn);
12225 rsp->last_set_mode = mode;
12226 if (GET_MODE_CLASS (mode) == MODE_INT
12227 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
12228 mode = nonzero_bits_mode;
12229 rsp->last_set_nonzero_bits = nonzero_bits (value, mode);
12230 rsp->last_set_sign_bit_copies
12231 = num_sign_bit_copies (value, GET_MODE (reg));
12235 /* Called via note_stores from record_dead_and_set_regs to handle one
12236 SET or CLOBBER in an insn. DATA is the instruction in which the
12237 set is occurring. */
12240 record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
12242 rtx record_dead_insn = (rtx) data;
12244 if (GET_CODE (dest) == SUBREG)
12245 dest = SUBREG_REG (dest);
12247 if (!record_dead_insn)
12250 record_value_for_reg (dest, NULL_RTX, NULL_RTX);
12256 /* If we are setting the whole register, we know its value. Otherwise
12257 show that we don't know the value. We can handle SUBREG in
12259 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
12260 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
12261 else if (GET_CODE (setter) == SET
12262 && GET_CODE (SET_DEST (setter)) == SUBREG
12263 && SUBREG_REG (SET_DEST (setter)) == dest
12264 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
12265 && subreg_lowpart_p (SET_DEST (setter)))
12266 record_value_for_reg (dest, record_dead_insn,
12267 gen_lowpart (GET_MODE (dest),
12268 SET_SRC (setter)));
12270 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
12272 else if (MEM_P (dest)
12273 /* Ignore pushes, they clobber nothing. */
12274 && ! push_operand (dest, GET_MODE (dest)))
12275 mem_last_set = DF_INSN_LUID (record_dead_insn);
12278 /* Update the records of when each REG was most recently set or killed
12279 for the things done by INSN. This is the last thing done in processing
12280 INSN in the combiner loop.
12282 We update reg_stat[], in particular fields last_set, last_set_value,
12283 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12284 last_death, and also the similar information mem_last_set (which insn
12285 most recently modified memory) and last_call_luid (which insn was the
12286 most recent subroutine call). */
12289 record_dead_and_set_regs (rtx insn)
12294 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
12296 if (REG_NOTE_KIND (link) == REG_DEAD
12297 && REG_P (XEXP (link, 0)))
12299 unsigned int regno = REGNO (XEXP (link, 0));
12300 unsigned int endregno = END_REGNO (XEXP (link, 0));
12302 for (i = regno; i < endregno; i++)
12304 reg_stat_type *rsp;
12306 rsp = VEC_index (reg_stat_type, reg_stat, i);
12307 rsp->last_death = insn;
12310 else if (REG_NOTE_KIND (link) == REG_INC)
12311 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
12316 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
12317 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
12319 reg_stat_type *rsp;
12321 rsp = VEC_index (reg_stat_type, reg_stat, i);
12322 rsp->last_set_invalid = 1;
12323 rsp->last_set = insn;
12324 rsp->last_set_value = 0;
12325 rsp->last_set_mode = VOIDmode;
12326 rsp->last_set_nonzero_bits = 0;
12327 rsp->last_set_sign_bit_copies = 0;
12328 rsp->last_death = 0;
12329 rsp->truncated_to_mode = VOIDmode;
12332 last_call_luid = mem_last_set = DF_INSN_LUID (insn);
12334 /* We can't combine into a call pattern. Remember, though, that
12335 the return value register is set at this LUID. We could
12336 still replace a register with the return value from the
12337 wrong subroutine call! */
12338 note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
12341 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
12344 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12345 register present in the SUBREG, so for each such SUBREG go back and
12346 adjust nonzero and sign bit information of the registers that are
12347 known to have some zero/sign bits set.
12349 This is needed because when combine blows the SUBREGs away, the
12350 information on zero/sign bits is lost and further combines can be
12351 missed because of that. */
12354 record_promoted_value (rtx insn, rtx subreg)
12357 unsigned int regno = REGNO (SUBREG_REG (subreg));
12358 enum machine_mode mode = GET_MODE (subreg);
12360 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
12363 for (links = LOG_LINKS (insn); links;)
12365 reg_stat_type *rsp;
12367 insn = XEXP (links, 0);
12368 set = single_set (insn);
12370 if (! set || !REG_P (SET_DEST (set))
12371 || REGNO (SET_DEST (set)) != regno
12372 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
12374 links = XEXP (links, 1);
12378 rsp = VEC_index (reg_stat_type, reg_stat, regno);
12379 if (rsp->last_set == insn)
12381 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
12382 rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode);
12385 if (REG_P (SET_SRC (set)))
12387 regno = REGNO (SET_SRC (set));
12388 links = LOG_LINKS (insn);
12395 /* Check if X, a register, is known to contain a value already
12396 truncated to MODE. In this case we can use a subreg to refer to
12397 the truncated value even though in the generic case we would need
12398 an explicit truncation. */
12401 reg_truncated_to_mode (enum machine_mode mode, const_rtx x)
12403 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
12404 enum machine_mode truncated = rsp->truncated_to_mode;
12407 || rsp->truncation_label < label_tick_ebb_start)
12409 if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
12411 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
12412 GET_MODE_BITSIZE (truncated)))
12417 /* Callback for for_each_rtx. If *P is a hard reg or a subreg record the mode
12418 that the register is accessed in. For non-TRULY_NOOP_TRUNCATION targets we
12419 might be able to turn a truncate into a subreg using this information.
12420 Return -1 if traversing *P is complete or 0 otherwise. */
12423 record_truncated_value (rtx *p, void *data ATTRIBUTE_UNUSED)
12426 enum machine_mode truncated_mode;
12427 reg_stat_type *rsp;
12429 if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
12431 enum machine_mode original_mode = GET_MODE (SUBREG_REG (x));
12432 truncated_mode = GET_MODE (x);
12434 if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
12437 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (truncated_mode),
12438 GET_MODE_BITSIZE (original_mode)))
12441 x = SUBREG_REG (x);
12443 /* ??? For hard-regs we now record everything. We might be able to
12444 optimize this using last_set_mode. */
12445 else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
12446 truncated_mode = GET_MODE (x);
12450 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
12451 if (rsp->truncated_to_mode == 0
12452 || rsp->truncation_label < label_tick_ebb_start
12453 || (GET_MODE_SIZE (truncated_mode)
12454 < GET_MODE_SIZE (rsp->truncated_to_mode)))
12456 rsp->truncated_to_mode = truncated_mode;
12457 rsp->truncation_label = label_tick;
12463 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12464 the modes they are used in. This can help truning TRUNCATEs into
12468 record_truncated_values (rtx *x, void *data ATTRIBUTE_UNUSED)
12470 for_each_rtx (x, record_truncated_value, NULL);
12473 /* Scan X for promoted SUBREGs. For each one found,
12474 note what it implies to the registers used in it. */
12477 check_promoted_subreg (rtx insn, rtx x)
12479 if (GET_CODE (x) == SUBREG
12480 && SUBREG_PROMOTED_VAR_P (x)
12481 && REG_P (SUBREG_REG (x)))
12482 record_promoted_value (insn, x);
12485 const char *format = GET_RTX_FORMAT (GET_CODE (x));
12488 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
12492 check_promoted_subreg (insn, XEXP (x, i));
12496 if (XVEC (x, i) != 0)
12497 for (j = 0; j < XVECLEN (x, i); j++)
12498 check_promoted_subreg (insn, XVECEXP (x, i, j));
12504 /* Verify that all the registers and memory references mentioned in *LOC are
12505 still valid. *LOC was part of a value set in INSN when label_tick was
12506 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12507 the invalid references with (clobber (const_int 0)) and return 1. This
12508 replacement is useful because we often can get useful information about
12509 the form of a value (e.g., if it was produced by a shift that always
12510 produces -1 or 0) even though we don't know exactly what registers it
12511 was produced from. */
12514 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
12517 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
12518 int len = GET_RTX_LENGTH (GET_CODE (x));
12523 unsigned int regno = REGNO (x);
12524 unsigned int endregno = END_REGNO (x);
12527 for (j = regno; j < endregno; j++)
12529 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, j);
12530 if (rsp->last_set_invalid
12531 /* If this is a pseudo-register that was only set once and not
12532 live at the beginning of the function, it is always valid. */
12533 || (! (regno >= FIRST_PSEUDO_REGISTER
12534 && REG_N_SETS (regno) == 1
12535 && (!REGNO_REG_SET_P
12536 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno)))
12537 && rsp->last_set_label > tick))
12540 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12547 /* If this is a memory reference, make sure that there were no stores after
12548 it that might have clobbered the value. We don't have alias info, so we
12549 assume any store invalidates it. Moreover, we only have local UIDs, so
12550 we also assume that there were stores in the intervening basic blocks. */
12551 else if (MEM_P (x) && !MEM_READONLY_P (x)
12552 && (tick != label_tick || DF_INSN_LUID (insn) <= mem_last_set))
12555 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12559 for (i = 0; i < len; i++)
12563 /* Check for identical subexpressions. If x contains
12564 identical subexpression we only have to traverse one of
12566 if (i == 1 && ARITHMETIC_P (x))
12568 /* Note that at this point x0 has already been checked
12569 and found valid. */
12570 rtx x0 = XEXP (x, 0);
12571 rtx x1 = XEXP (x, 1);
12573 /* If x0 and x1 are identical then x is also valid. */
12577 /* If x1 is identical to a subexpression of x0 then
12578 while checking x0, x1 has already been checked. Thus
12579 it is valid and so as x. */
12580 if (ARITHMETIC_P (x0)
12581 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12584 /* If x0 is identical to a subexpression of x1 then x is
12585 valid iff the rest of x1 is valid. */
12586 if (ARITHMETIC_P (x1)
12587 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12589 get_last_value_validate (&XEXP (x1,
12590 x0 == XEXP (x1, 0) ? 1 : 0),
12591 insn, tick, replace);
12594 if (get_last_value_validate (&XEXP (x, i), insn, tick,
12598 else if (fmt[i] == 'E')
12599 for (j = 0; j < XVECLEN (x, i); j++)
12600 if (get_last_value_validate (&XVECEXP (x, i, j),
12601 insn, tick, replace) == 0)
12605 /* If we haven't found a reason for it to be invalid, it is valid. */
12609 /* Get the last value assigned to X, if known. Some registers
12610 in the value may be replaced with (clobber (const_int 0)) if their value
12611 is known longer known reliably. */
12614 get_last_value (const_rtx x)
12616 unsigned int regno;
12618 reg_stat_type *rsp;
12620 /* If this is a non-paradoxical SUBREG, get the value of its operand and
12621 then convert it to the desired mode. If this is a paradoxical SUBREG,
12622 we cannot predict what values the "extra" bits might have. */
12623 if (GET_CODE (x) == SUBREG
12624 && subreg_lowpart_p (x)
12625 && (GET_MODE_SIZE (GET_MODE (x))
12626 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
12627 && (value = get_last_value (SUBREG_REG (x))) != 0)
12628 return gen_lowpart (GET_MODE (x), value);
12634 rsp = VEC_index (reg_stat_type, reg_stat, regno);
12635 value = rsp->last_set_value;
12637 /* If we don't have a value, or if it isn't for this basic block and
12638 it's either a hard register, set more than once, or it's a live
12639 at the beginning of the function, return 0.
12641 Because if it's not live at the beginning of the function then the reg
12642 is always set before being used (is never used without being set).
12643 And, if it's set only once, and it's always set before use, then all
12644 uses must have the same last value, even if it's not from this basic
12648 || (rsp->last_set_label < label_tick_ebb_start
12649 && (regno < FIRST_PSEUDO_REGISTER
12650 || REG_N_SETS (regno) != 1
12652 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno))))
12655 /* If the value was set in a later insn than the ones we are processing,
12656 we can't use it even if the register was only set once. */
12657 if (rsp->last_set_label == label_tick
12658 && DF_INSN_LUID (rsp->last_set) >= subst_low_luid)
12661 /* If the value has all its registers valid, return it. */
12662 if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 0))
12665 /* Otherwise, make a copy and replace any invalid register with
12666 (clobber (const_int 0)). If that fails for some reason, return 0. */
12668 value = copy_rtx (value);
12669 if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 1))
12675 /* Return nonzero if expression X refers to a REG or to memory
12676 that is set in an instruction more recent than FROM_LUID. */
12679 use_crosses_set_p (const_rtx x, int from_luid)
12683 enum rtx_code code = GET_CODE (x);
12687 unsigned int regno = REGNO (x);
12688 unsigned endreg = END_REGNO (x);
12690 #ifdef PUSH_ROUNDING
12691 /* Don't allow uses of the stack pointer to be moved,
12692 because we don't know whether the move crosses a push insn. */
12693 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
12696 for (; regno < endreg; regno++)
12698 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
12700 && rsp->last_set_label == label_tick
12701 && DF_INSN_LUID (rsp->last_set) > from_luid)
12707 if (code == MEM && mem_last_set > from_luid)
12710 fmt = GET_RTX_FORMAT (code);
12712 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12717 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12718 if (use_crosses_set_p (XVECEXP (x, i, j), from_luid))
12721 else if (fmt[i] == 'e'
12722 && use_crosses_set_p (XEXP (x, i), from_luid))
12728 /* Define three variables used for communication between the following
12731 static unsigned int reg_dead_regno, reg_dead_endregno;
12732 static int reg_dead_flag;
12734 /* Function called via note_stores from reg_dead_at_p.
12736 If DEST is within [reg_dead_regno, reg_dead_endregno), set
12737 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
12740 reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
12742 unsigned int regno, endregno;
12747 regno = REGNO (dest);
12748 endregno = END_REGNO (dest);
12749 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
12750 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
12753 /* Return nonzero if REG is known to be dead at INSN.
12755 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12756 referencing REG, it is dead. If we hit a SET referencing REG, it is
12757 live. Otherwise, see if it is live or dead at the start of the basic
12758 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12759 must be assumed to be always live. */
12762 reg_dead_at_p (rtx reg, rtx insn)
12767 /* Set variables for reg_dead_at_p_1. */
12768 reg_dead_regno = REGNO (reg);
12769 reg_dead_endregno = END_REGNO (reg);
12773 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
12774 we allow the machine description to decide whether use-and-clobber
12775 patterns are OK. */
12776 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
12778 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12779 if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
12783 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12784 beginning of basic block. */
12785 block = BLOCK_FOR_INSN (insn);
12790 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
12792 return reg_dead_flag == 1 ? 1 : 0;
12794 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
12798 if (insn == BB_HEAD (block))
12801 insn = PREV_INSN (insn);
12804 /* Look at live-in sets for the basic block that we were in. */
12805 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12806 if (REGNO_REG_SET_P (df_get_live_in (block), i))
12812 /* Note hard registers in X that are used. */
12815 mark_used_regs_combine (rtx x)
12817 RTX_CODE code = GET_CODE (x);
12818 unsigned int regno;
12831 case ADDR_DIFF_VEC:
12834 /* CC0 must die in the insn after it is set, so we don't need to take
12835 special note of it here. */
12841 /* If we are clobbering a MEM, mark any hard registers inside the
12842 address as used. */
12843 if (MEM_P (XEXP (x, 0)))
12844 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
12849 /* A hard reg in a wide mode may really be multiple registers.
12850 If so, mark all of them just like the first. */
12851 if (regno < FIRST_PSEUDO_REGISTER)
12853 /* None of this applies to the stack, frame or arg pointers. */
12854 if (regno == STACK_POINTER_REGNUM
12855 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
12856 || regno == HARD_FRAME_POINTER_REGNUM
12858 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12859 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
12861 || regno == FRAME_POINTER_REGNUM)
12864 add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno);
12870 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12872 rtx testreg = SET_DEST (x);
12874 while (GET_CODE (testreg) == SUBREG
12875 || GET_CODE (testreg) == ZERO_EXTRACT
12876 || GET_CODE (testreg) == STRICT_LOW_PART)
12877 testreg = XEXP (testreg, 0);
12879 if (MEM_P (testreg))
12880 mark_used_regs_combine (XEXP (testreg, 0));
12882 mark_used_regs_combine (SET_SRC (x));
12890 /* Recursively scan the operands of this expression. */
12893 const char *fmt = GET_RTX_FORMAT (code);
12895 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12898 mark_used_regs_combine (XEXP (x, i));
12899 else if (fmt[i] == 'E')
12903 for (j = 0; j < XVECLEN (x, i); j++)
12904 mark_used_regs_combine (XVECEXP (x, i, j));
12910 /* Remove register number REGNO from the dead registers list of INSN.
12912 Return the note used to record the death, if there was one. */
12915 remove_death (unsigned int regno, rtx insn)
12917 rtx note = find_regno_note (insn, REG_DEAD, regno);
12920 remove_note (insn, note);
12925 /* For each register (hardware or pseudo) used within expression X, if its
12926 death is in an instruction with luid between FROM_LUID (inclusive) and
12927 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12928 list headed by PNOTES.
12930 That said, don't move registers killed by maybe_kill_insn.
12932 This is done when X is being merged by combination into TO_INSN. These
12933 notes will then be distributed as needed. */
12936 move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx to_insn,
12941 enum rtx_code code = GET_CODE (x);
12945 unsigned int regno = REGNO (x);
12946 rtx where_dead = VEC_index (reg_stat_type, reg_stat, regno)->last_death;
12948 /* Don't move the register if it gets killed in between from and to. */
12949 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
12950 && ! reg_referenced_p (x, maybe_kill_insn))
12954 && BLOCK_FOR_INSN (where_dead) == BLOCK_FOR_INSN (to_insn)
12955 && DF_INSN_LUID (where_dead) >= from_luid
12956 && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn))
12958 rtx note = remove_death (regno, where_dead);
12960 /* It is possible for the call above to return 0. This can occur
12961 when last_death points to I2 or I1 that we combined with.
12962 In that case make a new note.
12964 We must also check for the case where X is a hard register
12965 and NOTE is a death note for a range of hard registers
12966 including X. In that case, we must put REG_DEAD notes for
12967 the remaining registers in place of NOTE. */
12969 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
12970 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12971 > GET_MODE_SIZE (GET_MODE (x))))
12973 unsigned int deadregno = REGNO (XEXP (note, 0));
12974 unsigned int deadend = END_HARD_REGNO (XEXP (note, 0));
12975 unsigned int ourend = END_HARD_REGNO (x);
12978 for (i = deadregno; i < deadend; i++)
12979 if (i < regno || i >= ourend)
12980 add_reg_note (where_dead, REG_DEAD, regno_reg_rtx[i]);
12983 /* If we didn't find any note, or if we found a REG_DEAD note that
12984 covers only part of the given reg, and we have a multi-reg hard
12985 register, then to be safe we must check for REG_DEAD notes
12986 for each register other than the first. They could have
12987 their own REG_DEAD notes lying around. */
12988 else if ((note == 0
12990 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12991 < GET_MODE_SIZE (GET_MODE (x)))))
12992 && regno < FIRST_PSEUDO_REGISTER
12993 && hard_regno_nregs[regno][GET_MODE (x)] > 1)
12995 unsigned int ourend = END_HARD_REGNO (x);
12996 unsigned int i, offset;
13000 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
13004 for (i = regno + offset; i < ourend; i++)
13005 move_deaths (regno_reg_rtx[i],
13006 maybe_kill_insn, from_luid, to_insn, &oldnotes);
13009 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
13011 XEXP (note, 1) = *pnotes;
13015 *pnotes = alloc_reg_note (REG_DEAD, x, *pnotes);
13021 else if (GET_CODE (x) == SET)
13023 rtx dest = SET_DEST (x);
13025 move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes);
13027 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13028 that accesses one word of a multi-word item, some
13029 piece of everything register in the expression is used by
13030 this insn, so remove any old death. */
13031 /* ??? So why do we test for equality of the sizes? */
13033 if (GET_CODE (dest) == ZERO_EXTRACT
13034 || GET_CODE (dest) == STRICT_LOW_PART
13035 || (GET_CODE (dest) == SUBREG
13036 && (((GET_MODE_SIZE (GET_MODE (dest))
13037 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
13038 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
13039 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
13041 move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes);
13045 /* If this is some other SUBREG, we know it replaces the entire
13046 value, so use that as the destination. */
13047 if (GET_CODE (dest) == SUBREG)
13048 dest = SUBREG_REG (dest);
13050 /* If this is a MEM, adjust deaths of anything used in the address.
13051 For a REG (the only other possibility), the entire value is
13052 being replaced so the old value is not used in this insn. */
13055 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid,
13060 else if (GET_CODE (x) == CLOBBER)
13063 len = GET_RTX_LENGTH (code);
13064 fmt = GET_RTX_FORMAT (code);
13066 for (i = 0; i < len; i++)
13071 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
13072 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid,
13075 else if (fmt[i] == 'e')
13076 move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes);
13080 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13081 pattern of an insn. X must be a REG. */
13084 reg_bitfield_target_p (rtx x, rtx body)
13088 if (GET_CODE (body) == SET)
13090 rtx dest = SET_DEST (body);
13092 unsigned int regno, tregno, endregno, endtregno;
13094 if (GET_CODE (dest) == ZERO_EXTRACT)
13095 target = XEXP (dest, 0);
13096 else if (GET_CODE (dest) == STRICT_LOW_PART)
13097 target = SUBREG_REG (XEXP (dest, 0));
13101 if (GET_CODE (target) == SUBREG)
13102 target = SUBREG_REG (target);
13104 if (!REG_P (target))
13107 tregno = REGNO (target), regno = REGNO (x);
13108 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
13109 return target == x;
13111 endtregno = end_hard_regno (GET_MODE (target), tregno);
13112 endregno = end_hard_regno (GET_MODE (x), regno);
13114 return endregno > tregno && regno < endtregno;
13117 else if (GET_CODE (body) == PARALLEL)
13118 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
13119 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
13125 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13126 as appropriate. I3 and I2 are the insns resulting from the combination
13127 insns including FROM (I2 may be zero).
13129 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13130 not need REG_DEAD notes because they are being substituted for. This
13131 saves searching in the most common cases.
13133 Each note in the list is either ignored or placed on some insns, depending
13134 on the type of note. */
13137 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
13138 rtx elim_i1, rtx elim_i0)
13140 rtx note, next_note;
13143 for (note = notes; note; note = next_note)
13145 rtx place = 0, place2 = 0;
13147 next_note = XEXP (note, 1);
13148 switch (REG_NOTE_KIND (note))
13152 /* Doesn't matter much where we put this, as long as it's somewhere.
13153 It is preferable to keep these notes on branches, which is most
13154 likely to be i3. */
13158 case REG_NON_LOCAL_GOTO:
13163 gcc_assert (i2 && JUMP_P (i2));
13168 case REG_EH_REGION:
13169 /* These notes must remain with the call or trapping instruction. */
13172 else if (i2 && CALL_P (i2))
13176 gcc_assert (cfun->can_throw_non_call_exceptions);
13177 if (may_trap_p (i3))
13179 else if (i2 && may_trap_p (i2))
13181 /* ??? Otherwise assume we've combined things such that we
13182 can now prove that the instructions can't trap. Drop the
13183 note in this case. */
13189 /* These notes must remain with the call. It should not be
13190 possible for both I2 and I3 to be a call. */
13195 gcc_assert (i2 && CALL_P (i2));
13201 /* Any clobbers for i3 may still exist, and so we must process
13202 REG_UNUSED notes from that insn.
13204 Any clobbers from i2 or i1 can only exist if they were added by
13205 recog_for_combine. In that case, recog_for_combine created the
13206 necessary REG_UNUSED notes. Trying to keep any original
13207 REG_UNUSED notes from these insns can cause incorrect output
13208 if it is for the same register as the original i3 dest.
13209 In that case, we will notice that the register is set in i3,
13210 and then add a REG_UNUSED note for the destination of i3, which
13211 is wrong. However, it is possible to have REG_UNUSED notes from
13212 i2 or i1 for register which were both used and clobbered, so
13213 we keep notes from i2 or i1 if they will turn into REG_DEAD
13216 /* If this register is set or clobbered in I3, put the note there
13217 unless there is one already. */
13218 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
13220 if (from_insn != i3)
13223 if (! (REG_P (XEXP (note, 0))
13224 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
13225 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
13228 /* Otherwise, if this register is used by I3, then this register
13229 now dies here, so we must put a REG_DEAD note here unless there
13231 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
13232 && ! (REG_P (XEXP (note, 0))
13233 ? find_regno_note (i3, REG_DEAD,
13234 REGNO (XEXP (note, 0)))
13235 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
13237 PUT_REG_NOTE_KIND (note, REG_DEAD);
13245 /* These notes say something about results of an insn. We can
13246 only support them if they used to be on I3 in which case they
13247 remain on I3. Otherwise they are ignored.
13249 If the note refers to an expression that is not a constant, we
13250 must also ignore the note since we cannot tell whether the
13251 equivalence is still true. It might be possible to do
13252 slightly better than this (we only have a problem if I2DEST
13253 or I1DEST is present in the expression), but it doesn't
13254 seem worth the trouble. */
13256 if (from_insn == i3
13257 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
13262 /* These notes say something about how a register is used. They must
13263 be present on any use of the register in I2 or I3. */
13264 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
13267 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
13276 case REG_LABEL_TARGET:
13277 case REG_LABEL_OPERAND:
13278 /* This can show up in several ways -- either directly in the
13279 pattern, or hidden off in the constant pool with (or without?)
13280 a REG_EQUAL note. */
13281 /* ??? Ignore the without-reg_equal-note problem for now. */
13282 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
13283 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
13284 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
13285 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
13289 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
13290 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
13291 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
13292 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
13300 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13301 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13303 if (place && JUMP_P (place)
13304 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
13305 && (JUMP_LABEL (place) == NULL
13306 || JUMP_LABEL (place) == XEXP (note, 0)))
13308 rtx label = JUMP_LABEL (place);
13311 JUMP_LABEL (place) = XEXP (note, 0);
13312 else if (LABEL_P (label))
13313 LABEL_NUSES (label)--;
13316 if (place2 && JUMP_P (place2)
13317 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
13318 && (JUMP_LABEL (place2) == NULL
13319 || JUMP_LABEL (place2) == XEXP (note, 0)))
13321 rtx label = JUMP_LABEL (place2);
13324 JUMP_LABEL (place2) = XEXP (note, 0);
13325 else if (LABEL_P (label))
13326 LABEL_NUSES (label)--;
13332 /* This note says something about the value of a register prior
13333 to the execution of an insn. It is too much trouble to see
13334 if the note is still correct in all situations. It is better
13335 to simply delete it. */
13339 /* If we replaced the right hand side of FROM_INSN with a
13340 REG_EQUAL note, the original use of the dying register
13341 will not have been combined into I3 and I2. In such cases,
13342 FROM_INSN is guaranteed to be the first of the combined
13343 instructions, so we simply need to search back before
13344 FROM_INSN for the previous use or set of this register,
13345 then alter the notes there appropriately.
13347 If the register is used as an input in I3, it dies there.
13348 Similarly for I2, if it is nonzero and adjacent to I3.
13350 If the register is not used as an input in either I3 or I2
13351 and it is not one of the registers we were supposed to eliminate,
13352 there are two possibilities. We might have a non-adjacent I2
13353 or we might have somehow eliminated an additional register
13354 from a computation. For example, we might have had A & B where
13355 we discover that B will always be zero. In this case we will
13356 eliminate the reference to A.
13358 In both cases, we must search to see if we can find a previous
13359 use of A and put the death note there. */
13362 && from_insn == i2mod
13363 && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
13368 && CALL_P (from_insn)
13369 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
13371 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
13373 else if (i2 != 0 && next_nonnote_nondebug_insn (i2) == i3
13374 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13376 else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
13378 && reg_overlap_mentioned_p (XEXP (note, 0),
13380 || rtx_equal_p (XEXP (note, 0), elim_i1)
13381 || rtx_equal_p (XEXP (note, 0), elim_i0))
13388 basic_block bb = this_basic_block;
13390 for (tem = PREV_INSN (tem); place == 0; tem = PREV_INSN (tem))
13392 if (!NONDEBUG_INSN_P (tem))
13394 if (tem == BB_HEAD (bb))
13399 /* If the register is being set at TEM, see if that is all
13400 TEM is doing. If so, delete TEM. Otherwise, make this
13401 into a REG_UNUSED note instead. Don't delete sets to
13402 global register vars. */
13403 if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
13404 || !global_regs[REGNO (XEXP (note, 0))])
13405 && reg_set_p (XEXP (note, 0), PATTERN (tem)))
13407 rtx set = single_set (tem);
13408 rtx inner_dest = 0;
13410 rtx cc0_setter = NULL_RTX;
13414 for (inner_dest = SET_DEST (set);
13415 (GET_CODE (inner_dest) == STRICT_LOW_PART
13416 || GET_CODE (inner_dest) == SUBREG
13417 || GET_CODE (inner_dest) == ZERO_EXTRACT);
13418 inner_dest = XEXP (inner_dest, 0))
13421 /* Verify that it was the set, and not a clobber that
13422 modified the register.
13424 CC0 targets must be careful to maintain setter/user
13425 pairs. If we cannot delete the setter due to side
13426 effects, mark the user with an UNUSED note instead
13429 if (set != 0 && ! side_effects_p (SET_SRC (set))
13430 && rtx_equal_p (XEXP (note, 0), inner_dest)
13432 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
13433 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
13434 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
13438 /* Move the notes and links of TEM elsewhere.
13439 This might delete other dead insns recursively.
13440 First set the pattern to something that won't use
13442 rtx old_notes = REG_NOTES (tem);
13444 PATTERN (tem) = pc_rtx;
13445 REG_NOTES (tem) = NULL;
13447 distribute_notes (old_notes, tem, tem, NULL_RTX,
13448 NULL_RTX, NULL_RTX, NULL_RTX);
13449 distribute_links (LOG_LINKS (tem));
13451 SET_INSN_DELETED (tem);
13456 /* Delete the setter too. */
13459 PATTERN (cc0_setter) = pc_rtx;
13460 old_notes = REG_NOTES (cc0_setter);
13461 REG_NOTES (cc0_setter) = NULL;
13463 distribute_notes (old_notes, cc0_setter,
13464 cc0_setter, NULL_RTX,
13465 NULL_RTX, NULL_RTX, NULL_RTX);
13466 distribute_links (LOG_LINKS (cc0_setter));
13468 SET_INSN_DELETED (cc0_setter);
13469 if (cc0_setter == i2)
13476 PUT_REG_NOTE_KIND (note, REG_UNUSED);
13478 /* If there isn't already a REG_UNUSED note, put one
13479 here. Do not place a REG_DEAD note, even if
13480 the register is also used here; that would not
13481 match the algorithm used in lifetime analysis
13482 and can cause the consistency check in the
13483 scheduler to fail. */
13484 if (! find_regno_note (tem, REG_UNUSED,
13485 REGNO (XEXP (note, 0))))
13490 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
13492 && find_reg_fusage (tem, USE, XEXP (note, 0))))
13496 /* If we are doing a 3->2 combination, and we have a
13497 register which formerly died in i3 and was not used
13498 by i2, which now no longer dies in i3 and is used in
13499 i2 but does not die in i2, and place is between i2
13500 and i3, then we may need to move a link from place to
13502 if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2)
13504 && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2)
13505 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13507 rtx links = LOG_LINKS (place);
13508 LOG_LINKS (place) = 0;
13509 distribute_links (links);
13514 if (tem == BB_HEAD (bb))
13520 /* If the register is set or already dead at PLACE, we needn't do
13521 anything with this note if it is still a REG_DEAD note.
13522 We check here if it is set at all, not if is it totally replaced,
13523 which is what `dead_or_set_p' checks, so also check for it being
13526 if (place && REG_NOTE_KIND (note) == REG_DEAD)
13528 unsigned int regno = REGNO (XEXP (note, 0));
13529 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
13531 if (dead_or_set_p (place, XEXP (note, 0))
13532 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
13534 /* Unless the register previously died in PLACE, clear
13535 last_death. [I no longer understand why this is
13537 if (rsp->last_death != place)
13538 rsp->last_death = 0;
13542 rsp->last_death = place;
13544 /* If this is a death note for a hard reg that is occupying
13545 multiple registers, ensure that we are still using all
13546 parts of the object. If we find a piece of the object
13547 that is unused, we must arrange for an appropriate REG_DEAD
13548 note to be added for it. However, we can't just emit a USE
13549 and tag the note to it, since the register might actually
13550 be dead; so we recourse, and the recursive call then finds
13551 the previous insn that used this register. */
13553 if (place && regno < FIRST_PSEUDO_REGISTER
13554 && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
13556 unsigned int endregno = END_HARD_REGNO (XEXP (note, 0));
13560 for (i = regno; i < endregno; i++)
13561 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
13562 && ! find_regno_fusage (place, USE, i))
13563 || dead_or_set_regno_p (place, i))
13568 /* Put only REG_DEAD notes for pieces that are
13569 not already dead or set. */
13571 for (i = regno; i < endregno;
13572 i += hard_regno_nregs[i][reg_raw_mode[i]])
13574 rtx piece = regno_reg_rtx[i];
13575 basic_block bb = this_basic_block;
13577 if (! dead_or_set_p (place, piece)
13578 && ! reg_bitfield_target_p (piece,
13581 rtx new_note = alloc_reg_note (REG_DEAD, piece,
13584 distribute_notes (new_note, place, place,
13585 NULL_RTX, NULL_RTX, NULL_RTX,
13588 else if (! refers_to_regno_p (i, i + 1,
13589 PATTERN (place), 0)
13590 && ! find_regno_fusage (place, USE, i))
13591 for (tem = PREV_INSN (place); ;
13592 tem = PREV_INSN (tem))
13594 if (!NONDEBUG_INSN_P (tem))
13596 if (tem == BB_HEAD (bb))
13600 if (dead_or_set_p (tem, piece)
13601 || reg_bitfield_target_p (piece,
13604 add_reg_note (tem, REG_UNUSED, piece);
13618 /* Any other notes should not be present at this point in the
13620 gcc_unreachable ();
13625 XEXP (note, 1) = REG_NOTES (place);
13626 REG_NOTES (place) = note;
13630 add_reg_note (place2, REG_NOTE_KIND (note), XEXP (note, 0));
13634 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13635 I3, I2, and I1 to new locations. This is also called to add a link
13636 pointing at I3 when I3's destination is changed. */
13639 distribute_links (rtx links)
13641 rtx link, next_link;
13643 for (link = links; link; link = next_link)
13649 next_link = XEXP (link, 1);
13651 /* If the insn that this link points to is a NOTE or isn't a single
13652 set, ignore it. In the latter case, it isn't clear what we
13653 can do other than ignore the link, since we can't tell which
13654 register it was for. Such links wouldn't be used by combine
13657 It is not possible for the destination of the target of the link to
13658 have been changed by combine. The only potential of this is if we
13659 replace I3, I2, and I1 by I3 and I2. But in that case the
13660 destination of I2 also remains unchanged. */
13662 if (NOTE_P (XEXP (link, 0))
13663 || (set = single_set (XEXP (link, 0))) == 0)
13666 reg = SET_DEST (set);
13667 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
13668 || GET_CODE (reg) == STRICT_LOW_PART)
13669 reg = XEXP (reg, 0);
13671 /* A LOG_LINK is defined as being placed on the first insn that uses
13672 a register and points to the insn that sets the register. Start
13673 searching at the next insn after the target of the link and stop
13674 when we reach a set of the register or the end of the basic block.
13676 Note that this correctly handles the link that used to point from
13677 I3 to I2. Also note that not much searching is typically done here
13678 since most links don't point very far away. */
13680 for (insn = NEXT_INSN (XEXP (link, 0));
13681 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
13682 || BB_HEAD (this_basic_block->next_bb) != insn));
13683 insn = NEXT_INSN (insn))
13684 if (DEBUG_INSN_P (insn))
13686 else if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
13688 if (reg_referenced_p (reg, PATTERN (insn)))
13692 else if (CALL_P (insn)
13693 && find_reg_fusage (insn, USE, reg))
13698 else if (INSN_P (insn) && reg_set_p (reg, insn))
13701 /* If we found a place to put the link, place it there unless there
13702 is already a link to the same insn as LINK at that point. */
13708 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
13709 if (XEXP (link2, 0) == XEXP (link, 0))
13714 XEXP (link, 1) = LOG_LINKS (place);
13715 LOG_LINKS (place) = link;
13717 /* Set added_links_insn to the earliest insn we added a
13719 if (added_links_insn == 0
13720 || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place))
13721 added_links_insn = place;
13727 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
13728 Check whether the expression pointer to by LOC is a register or
13729 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
13730 Otherwise return zero. */
13733 unmentioned_reg_p_1 (rtx *loc, void *expr)
13738 && (REG_P (x) || MEM_P (x))
13739 && ! reg_mentioned_p (x, (rtx) expr))
13744 /* Check for any register or memory mentioned in EQUIV that is not
13745 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
13746 of EXPR where some registers may have been replaced by constants. */
13749 unmentioned_reg_p (rtx equiv, rtx expr)
13751 return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
13755 dump_combine_stats (FILE *file)
13759 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13760 combine_attempts, combine_merges, combine_extras, combine_successes);
13764 dump_combine_total_stats (FILE *file)
13768 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13769 total_attempts, total_merges, total_extras, total_successes);
13773 gate_handle_combine (void)
13775 return (optimize > 0);
13778 /* Try combining insns through substitution. */
13779 static unsigned int
13780 rest_of_handle_combine (void)
13782 int rebuild_jump_labels_after_combine;
13784 df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN);
13785 df_note_add_problem ();
13788 regstat_init_n_sets_and_refs ();
13790 rebuild_jump_labels_after_combine
13791 = combine_instructions (get_insns (), max_reg_num ());
13793 /* Combining insns may have turned an indirect jump into a
13794 direct jump. Rebuild the JUMP_LABEL fields of jumping
13796 if (rebuild_jump_labels_after_combine)
13798 timevar_push (TV_JUMP);
13799 rebuild_jump_labels (get_insns ());
13801 timevar_pop (TV_JUMP);
13804 regstat_free_n_sets_and_refs ();
13808 struct rtl_opt_pass pass_combine =
13812 "combine", /* name */
13813 gate_handle_combine, /* gate */
13814 rest_of_handle_combine, /* execute */
13817 0, /* static_pass_number */
13818 TV_COMBINE, /* tv_id */
13819 PROP_cfglayout, /* properties_required */
13820 0, /* properties_provided */
13821 0, /* properties_destroyed */
13822 0, /* todo_flags_start */
13824 TODO_df_finish | TODO_verify_rtl_sharing |
13825 TODO_ggc_collect, /* todo_flags_finish */