1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
87 #include "hard-reg-set.h"
88 #include "basic-block.h"
89 #include "insn-config.h"
91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
93 #include "insn-attr.h"
99 #include "insn-codes.h"
100 #include "rtlhooks-def.h"
101 /* Include output.h for dump_file. */
105 #include "tree-pass.h"
109 /* Number of attempts to combine instructions in this function. */
111 static int combine_attempts;
113 /* Number of attempts that got as far as substitution in this function. */
115 static int combine_merges;
117 /* Number of instructions combined with added SETs in this function. */
119 static int combine_extras;
121 /* Number of instructions combined in this function. */
123 static int combine_successes;
125 /* Totals over entire compilation. */
127 static int total_attempts, total_merges, total_extras, total_successes;
129 /* combine_instructions may try to replace the right hand side of the
130 second instruction with the value of an associated REG_EQUAL note
131 before throwing it at try_combine. That is problematic when there
132 is a REG_DEAD note for a register used in the old right hand side
133 and can cause distribute_notes to do wrong things. This is the
134 second instruction if it has been so modified, null otherwise. */
138 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
140 static rtx i2mod_old_rhs;
142 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
144 static rtx i2mod_new_rhs;
146 typedef struct reg_stat_struct {
147 /* Record last point of death of (hard or pseudo) register n. */
150 /* Record last point of modification of (hard or pseudo) register n. */
153 /* The next group of fields allows the recording of the last value assigned
154 to (hard or pseudo) register n. We use this information to see if an
155 operation being processed is redundant given a prior operation performed
156 on the register. For example, an `and' with a constant is redundant if
157 all the zero bits are already known to be turned off.
159 We use an approach similar to that used by cse, but change it in the
162 (1) We do not want to reinitialize at each label.
163 (2) It is useful, but not critical, to know the actual value assigned
164 to a register. Often just its form is helpful.
166 Therefore, we maintain the following fields:
168 last_set_value the last value assigned
169 last_set_label records the value of label_tick when the
170 register was assigned
171 last_set_table_tick records the value of label_tick when a
172 value using the register is assigned
173 last_set_invalid set to nonzero when it is not valid
174 to use the value of this register in some
177 To understand the usage of these tables, it is important to understand
178 the distinction between the value in last_set_value being valid and
179 the register being validly contained in some other expression in the
182 (The next two parameters are out of date).
184 reg_stat[i].last_set_value is valid if it is nonzero, and either
185 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
187 Register I may validly appear in any expression returned for the value
188 of another register if reg_n_sets[i] is 1. It may also appear in the
189 value for register J if reg_stat[j].last_set_invalid is zero, or
190 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
192 If an expression is found in the table containing a register which may
193 not validly appear in an expression, the register is replaced by
194 something that won't match, (clobber (const_int 0)). */
196 /* Record last value assigned to (hard or pseudo) register n. */
200 /* Record the value of label_tick when an expression involving register n
201 is placed in last_set_value. */
203 int last_set_table_tick;
205 /* Record the value of label_tick when the value for register n is placed in
210 /* These fields are maintained in parallel with last_set_value and are
211 used to store the mode in which the register was last set, the bits
212 that were known to be zero when it was last set, and the number of
213 sign bits copies it was known to have when it was last set. */
215 unsigned HOST_WIDE_INT last_set_nonzero_bits;
216 char last_set_sign_bit_copies;
217 ENUM_BITFIELD(machine_mode) last_set_mode : 8;
219 /* Set nonzero if references to register n in expressions should not be
220 used. last_set_invalid is set nonzero when this register is being
221 assigned to and last_set_table_tick == label_tick. */
223 char last_set_invalid;
225 /* Some registers that are set more than once and used in more than one
226 basic block are nevertheless always set in similar ways. For example,
227 a QImode register may be loaded from memory in two places on a machine
228 where byte loads zero extend.
230 We record in the following fields if a register has some leading bits
231 that are always equal to the sign bit, and what we know about the
232 nonzero bits of a register, specifically which bits are known to be
235 If an entry is zero, it means that we don't know anything special. */
237 unsigned char sign_bit_copies;
239 unsigned HOST_WIDE_INT nonzero_bits;
241 /* Record the value of the label_tick when the last truncation
242 happened. The field truncated_to_mode is only valid if
243 truncation_label == label_tick. */
245 int truncation_label;
247 /* Record the last truncation seen for this register. If truncation
248 is not a nop to this mode we might be able to save an explicit
249 truncation if we know that value already contains a truncated
252 ENUM_BITFIELD(machine_mode) truncated_to_mode : 8;
255 DEF_VEC_O(reg_stat_type);
256 DEF_VEC_ALLOC_O(reg_stat_type,heap);
258 static VEC(reg_stat_type,heap) *reg_stat;
260 /* Record the luid of the last insn that invalidated memory
261 (anything that writes memory, and subroutine calls, but not pushes). */
263 static int mem_last_set;
265 /* Record the luid of the last CALL_INSN
266 so we can tell whether a potential combination crosses any calls. */
268 static int last_call_luid;
270 /* When `subst' is called, this is the insn that is being modified
271 (by combining in a previous insn). The PATTERN of this insn
272 is still the old pattern partially modified and it should not be
273 looked at, but this may be used to examine the successors of the insn
274 to judge whether a simplification is valid. */
276 static rtx subst_insn;
278 /* This is the lowest LUID that `subst' is currently dealing with.
279 get_last_value will not return a value if the register was set at or
280 after this LUID. If not for this mechanism, we could get confused if
281 I2 or I1 in try_combine were an insn that used the old value of a register
282 to obtain a new value. In that case, we might erroneously get the
283 new value of the register when we wanted the old one. */
285 static int subst_low_luid;
287 /* This contains any hard registers that are used in newpat; reg_dead_at_p
288 must consider all these registers to be always live. */
290 static HARD_REG_SET newpat_used_regs;
292 /* This is an insn to which a LOG_LINKS entry has been added. If this
293 insn is the earlier than I2 or I3, combine should rescan starting at
296 static rtx added_links_insn;
298 /* Basic block in which we are performing combines. */
299 static basic_block this_basic_block;
300 static bool optimize_this_for_speed_p;
303 /* Length of the currently allocated uid_insn_cost array. */
305 static int max_uid_known;
307 /* The following array records the insn_rtx_cost for every insn
308 in the instruction stream. */
310 static int *uid_insn_cost;
312 /* The following array records the LOG_LINKS for every insn in the
313 instruction stream as an INSN_LIST rtx. */
315 static rtx *uid_log_links;
317 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
318 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
320 /* Incremented for each basic block. */
322 static int label_tick;
324 /* Reset to label_tick for each label. */
326 static int label_tick_ebb_start;
328 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
329 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
331 static enum machine_mode nonzero_bits_mode;
333 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
334 be safely used. It is zero while computing them and after combine has
335 completed. This former test prevents propagating values based on
336 previously set values, which can be incorrect if a variable is modified
339 static int nonzero_sign_valid;
342 /* Record one modification to rtl structure
343 to be undone by storing old_contents into *where. */
345 enum undo_kind { UNDO_RTX, UNDO_INT, UNDO_MODE };
351 union { rtx r; int i; enum machine_mode m; } old_contents;
352 union { rtx *r; int *i; } where;
355 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
356 num_undo says how many are currently recorded.
358 other_insn is nonzero if we have modified some other insn in the process
359 of working on subst_insn. It must be verified too. */
368 static struct undobuf undobuf;
370 /* Number of times the pseudo being substituted for
371 was found and replaced. */
373 static int n_occurrences;
375 static rtx reg_nonzero_bits_for_combine (const_rtx, enum machine_mode, const_rtx,
377 unsigned HOST_WIDE_INT,
378 unsigned HOST_WIDE_INT *);
379 static rtx reg_num_sign_bit_copies_for_combine (const_rtx, enum machine_mode, const_rtx,
381 unsigned int, unsigned int *);
382 static void do_SUBST (rtx *, rtx);
383 static void do_SUBST_INT (int *, int);
384 static void init_reg_last (void);
385 static void setup_incoming_promotions (rtx);
386 static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *);
387 static int cant_combine_insn_p (rtx);
388 static int can_combine_p (rtx, rtx, rtx, rtx, rtx *, rtx *);
389 static int combinable_i3pat (rtx, rtx *, rtx, rtx, int, rtx *);
390 static int contains_muldiv (rtx);
391 static rtx try_combine (rtx, rtx, rtx, int *);
392 static void undo_all (void);
393 static void undo_commit (void);
394 static rtx *find_split_point (rtx *, rtx);
395 static rtx subst (rtx, rtx, rtx, int, int);
396 static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
397 static rtx simplify_if_then_else (rtx);
398 static rtx simplify_set (rtx);
399 static rtx simplify_logical (rtx);
400 static rtx expand_compound_operation (rtx);
401 static const_rtx expand_field_assignment (const_rtx);
402 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
403 rtx, unsigned HOST_WIDE_INT, int, int, int);
404 static rtx extract_left_shift (rtx, int);
405 static rtx make_compound_operation (rtx, enum rtx_code);
406 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
407 unsigned HOST_WIDE_INT *);
408 static rtx canon_reg_for_combine (rtx, rtx);
409 static rtx force_to_mode (rtx, enum machine_mode,
410 unsigned HOST_WIDE_INT, int);
411 static rtx if_then_else_cond (rtx, rtx *, rtx *);
412 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
413 static int rtx_equal_for_field_assignment_p (rtx, rtx);
414 static rtx make_field_assignment (rtx);
415 static rtx apply_distributive_law (rtx);
416 static rtx distribute_and_simplify_rtx (rtx, int);
417 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
418 unsigned HOST_WIDE_INT);
419 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
420 unsigned HOST_WIDE_INT);
421 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
422 HOST_WIDE_INT, enum machine_mode, int *);
423 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
424 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
426 static int recog_for_combine (rtx *, rtx, rtx *);
427 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
428 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
429 static void update_table_tick (rtx);
430 static void record_value_for_reg (rtx, rtx, rtx);
431 static void check_promoted_subreg (rtx, rtx);
432 static void record_dead_and_set_regs_1 (rtx, const_rtx, void *);
433 static void record_dead_and_set_regs (rtx);
434 static int get_last_value_validate (rtx *, rtx, int, int);
435 static rtx get_last_value (const_rtx);
436 static int use_crosses_set_p (const_rtx, int);
437 static void reg_dead_at_p_1 (rtx, const_rtx, void *);
438 static int reg_dead_at_p (rtx, rtx);
439 static void move_deaths (rtx, rtx, int, rtx, rtx *);
440 static int reg_bitfield_target_p (rtx, rtx);
441 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx);
442 static void distribute_links (rtx);
443 static void mark_used_regs_combine (rtx);
444 static void record_promoted_value (rtx, rtx);
445 static int unmentioned_reg_p_1 (rtx *, void *);
446 static bool unmentioned_reg_p (rtx, rtx);
447 static int record_truncated_value (rtx *, void *);
448 static void record_truncated_values (rtx *, void *);
449 static bool reg_truncated_to_mode (enum machine_mode, const_rtx);
450 static rtx gen_lowpart_or_truncate (enum machine_mode, rtx);
453 /* It is not safe to use ordinary gen_lowpart in combine.
454 See comments in gen_lowpart_for_combine. */
455 #undef RTL_HOOKS_GEN_LOWPART
456 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
458 /* Our implementation of gen_lowpart never emits a new pseudo. */
459 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
460 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
462 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
463 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
465 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
466 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
468 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
469 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
471 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
474 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
475 PATTERN can not be split. Otherwise, it returns an insn sequence.
476 This is a wrapper around split_insns which ensures that the
477 reg_stat vector is made larger if the splitter creates a new
481 combine_split_insns (rtx pattern, rtx insn)
486 ret = split_insns (pattern, insn);
487 nregs = max_reg_num ();
488 if (nregs > VEC_length (reg_stat_type, reg_stat))
489 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
493 /* This is used by find_single_use to locate an rtx in LOC that
494 contains exactly one use of DEST, which is typically either a REG
495 or CC0. It returns a pointer to the innermost rtx expression
496 containing DEST. Appearances of DEST that are being used to
497 totally replace it are not counted. */
500 find_single_use_1 (rtx dest, rtx *loc)
503 enum rtx_code code = GET_CODE (x);
521 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
522 of a REG that occupies all of the REG, the insn uses DEST if
523 it is mentioned in the destination or the source. Otherwise, we
524 need just check the source. */
525 if (GET_CODE (SET_DEST (x)) != CC0
526 && GET_CODE (SET_DEST (x)) != PC
527 && !REG_P (SET_DEST (x))
528 && ! (GET_CODE (SET_DEST (x)) == SUBREG
529 && REG_P (SUBREG_REG (SET_DEST (x)))
530 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
531 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
532 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
533 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
536 return find_single_use_1 (dest, &SET_SRC (x));
540 return find_single_use_1 (dest, &XEXP (x, 0));
546 /* If it wasn't one of the common cases above, check each expression and
547 vector of this code. Look for a unique usage of DEST. */
549 fmt = GET_RTX_FORMAT (code);
550 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
554 if (dest == XEXP (x, i)
555 || (REG_P (dest) && REG_P (XEXP (x, i))
556 && REGNO (dest) == REGNO (XEXP (x, i))))
559 this_result = find_single_use_1 (dest, &XEXP (x, i));
562 result = this_result;
563 else if (this_result)
564 /* Duplicate usage. */
567 else if (fmt[i] == 'E')
571 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
573 if (XVECEXP (x, i, j) == dest
575 && REG_P (XVECEXP (x, i, j))
576 && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
579 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
582 result = this_result;
583 else if (this_result)
593 /* See if DEST, produced in INSN, is used only a single time in the
594 sequel. If so, return a pointer to the innermost rtx expression in which
597 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
599 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
600 care about REG_DEAD notes or LOG_LINKS.
602 Otherwise, we find the single use by finding an insn that has a
603 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
604 only referenced once in that insn, we know that it must be the first
605 and last insn referencing DEST. */
608 find_single_use (rtx dest, rtx insn, rtx *ploc)
618 next = NEXT_INSN (insn);
620 || (!NONJUMP_INSN_P (next) && !JUMP_P (next)))
623 result = find_single_use_1 (dest, &PATTERN (next));
633 bb = BLOCK_FOR_INSN (insn);
634 for (next = NEXT_INSN (insn);
635 next && BLOCK_FOR_INSN (next) == bb;
636 next = NEXT_INSN (next))
637 if (INSN_P (next) && dead_or_set_p (next, dest))
639 for (link = LOG_LINKS (next); link; link = XEXP (link, 1))
640 if (XEXP (link, 0) == insn)
645 result = find_single_use_1 (dest, &PATTERN (next));
655 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
656 insn. The substitution can be undone by undo_all. If INTO is already
657 set to NEWVAL, do not record this change. Because computing NEWVAL might
658 also call SUBST, we have to compute it before we put anything into
662 do_SUBST (rtx *into, rtx newval)
667 if (oldval == newval)
670 /* We'd like to catch as many invalid transformations here as
671 possible. Unfortunately, there are way too many mode changes
672 that are perfectly valid, so we'd waste too much effort for
673 little gain doing the checks here. Focus on catching invalid
674 transformations involving integer constants. */
675 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
676 && CONST_INT_P (newval))
678 /* Sanity check that we're replacing oldval with a CONST_INT
679 that is a valid sign-extension for the original mode. */
680 gcc_assert (INTVAL (newval)
681 == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
683 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
684 CONST_INT is not valid, because after the replacement, the
685 original mode would be gone. Unfortunately, we can't tell
686 when do_SUBST is called to replace the operand thereof, so we
687 perform this test on oldval instead, checking whether an
688 invalid replacement took place before we got here. */
689 gcc_assert (!(GET_CODE (oldval) == SUBREG
690 && CONST_INT_P (SUBREG_REG (oldval))));
691 gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
692 && CONST_INT_P (XEXP (oldval, 0))));
696 buf = undobuf.frees, undobuf.frees = buf->next;
698 buf = XNEW (struct undo);
700 buf->kind = UNDO_RTX;
702 buf->old_contents.r = oldval;
705 buf->next = undobuf.undos, undobuf.undos = buf;
708 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
710 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
711 for the value of a HOST_WIDE_INT value (including CONST_INT) is
715 do_SUBST_INT (int *into, int newval)
720 if (oldval == newval)
724 buf = undobuf.frees, undobuf.frees = buf->next;
726 buf = XNEW (struct undo);
728 buf->kind = UNDO_INT;
730 buf->old_contents.i = oldval;
733 buf->next = undobuf.undos, undobuf.undos = buf;
736 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
738 /* Similar to SUBST, but just substitute the mode. This is used when
739 changing the mode of a pseudo-register, so that any other
740 references to the entry in the regno_reg_rtx array will change as
744 do_SUBST_MODE (rtx *into, enum machine_mode newval)
747 enum machine_mode oldval = GET_MODE (*into);
749 if (oldval == newval)
753 buf = undobuf.frees, undobuf.frees = buf->next;
755 buf = XNEW (struct undo);
757 buf->kind = UNDO_MODE;
759 buf->old_contents.m = oldval;
760 adjust_reg_mode (*into, newval);
762 buf->next = undobuf.undos, undobuf.undos = buf;
765 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE(&(INTO), (NEWVAL))
767 /* Subroutine of try_combine. Determine whether the combine replacement
768 patterns NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to
769 insn_rtx_cost that the original instruction sequence I1, I2, I3 and
770 undobuf.other_insn. Note that I1 and/or NEWI2PAT may be NULL_RTX.
771 NEWOTHERPAT and undobuf.other_insn may also both be NULL_RTX. This
772 function returns false, if the costs of all instructions can be
773 estimated, and the replacements are more expensive than the original
777 combine_validate_cost (rtx i1, rtx i2, rtx i3, rtx newpat, rtx newi2pat,
780 int i1_cost, i2_cost, i3_cost;
781 int new_i2_cost, new_i3_cost;
782 int old_cost, new_cost;
784 /* Lookup the original insn_rtx_costs. */
785 i2_cost = INSN_COST (i2);
786 i3_cost = INSN_COST (i3);
790 i1_cost = INSN_COST (i1);
791 old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0)
792 ? i1_cost + i2_cost + i3_cost : 0;
796 old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
800 /* Calculate the replacement insn_rtx_costs. */
801 new_i3_cost = insn_rtx_cost (newpat, optimize_this_for_speed_p);
804 new_i2_cost = insn_rtx_cost (newi2pat, optimize_this_for_speed_p);
805 new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
806 ? new_i2_cost + new_i3_cost : 0;
810 new_cost = new_i3_cost;
814 if (undobuf.other_insn)
816 int old_other_cost, new_other_cost;
818 old_other_cost = INSN_COST (undobuf.other_insn);
819 new_other_cost = insn_rtx_cost (newotherpat, optimize_this_for_speed_p);
820 if (old_other_cost > 0 && new_other_cost > 0)
822 old_cost += old_other_cost;
823 new_cost += new_other_cost;
829 /* Disallow this recombination if both new_cost and old_cost are
830 greater than zero, and new_cost is greater than old cost. */
832 && new_cost > old_cost)
839 "rejecting combination of insns %d, %d and %d\n",
840 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
841 fprintf (dump_file, "original costs %d + %d + %d = %d\n",
842 i1_cost, i2_cost, i3_cost, old_cost);
847 "rejecting combination of insns %d and %d\n",
848 INSN_UID (i2), INSN_UID (i3));
849 fprintf (dump_file, "original costs %d + %d = %d\n",
850 i2_cost, i3_cost, old_cost);
855 fprintf (dump_file, "replacement costs %d + %d = %d\n",
856 new_i2_cost, new_i3_cost, new_cost);
859 fprintf (dump_file, "replacement cost %d\n", new_cost);
865 /* Update the uid_insn_cost array with the replacement costs. */
866 INSN_COST (i2) = new_i2_cost;
867 INSN_COST (i3) = new_i3_cost;
875 /* Delete any insns that copy a register to itself. */
878 delete_noop_moves (void)
885 for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
887 next = NEXT_INSN (insn);
888 if (INSN_P (insn) && noop_move_p (insn))
891 fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn));
893 delete_insn_and_edges (insn);
900 /* Fill in log links field for all insns. */
903 create_log_links (void)
907 df_ref *def_vec, *use_vec;
909 next_use = XCNEWVEC (rtx, max_reg_num ());
911 /* Pass through each block from the end, recording the uses of each
912 register and establishing log links when def is encountered.
913 Note that we do not clear next_use array in order to save time,
914 so we have to test whether the use is in the same basic block as def.
916 There are a few cases below when we do not consider the definition or
917 usage -- these are taken from original flow.c did. Don't ask me why it is
918 done this way; I don't know and if it works, I don't want to know. */
922 FOR_BB_INSNS_REVERSE (bb, insn)
924 if (!NONDEBUG_INSN_P (insn))
927 /* Log links are created only once. */
928 gcc_assert (!LOG_LINKS (insn));
930 for (def_vec = DF_INSN_DEFS (insn); *def_vec; def_vec++)
932 df_ref def = *def_vec;
933 int regno = DF_REF_REGNO (def);
936 if (!next_use[regno])
939 /* Do not consider if it is pre/post modification in MEM. */
940 if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY)
943 /* Do not make the log link for frame pointer. */
944 if ((regno == FRAME_POINTER_REGNUM
945 && (! reload_completed || frame_pointer_needed))
946 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
947 || (regno == HARD_FRAME_POINTER_REGNUM
948 && (! reload_completed || frame_pointer_needed))
950 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
951 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
956 use_insn = next_use[regno];
957 if (BLOCK_FOR_INSN (use_insn) == bb)
961 We don't build a LOG_LINK for hard registers contained
962 in ASM_OPERANDs. If these registers get replaced,
963 we might wind up changing the semantics of the insn,
964 even if reload can make what appear to be valid
965 assignments later. */
966 if (regno >= FIRST_PSEUDO_REGISTER
967 || asm_noperands (PATTERN (use_insn)) < 0)
969 /* Don't add duplicate links between instructions. */
971 for (links = LOG_LINKS (use_insn); links;
972 links = XEXP (links, 1))
973 if (insn == XEXP (links, 0))
977 LOG_LINKS (use_insn) =
978 alloc_INSN_LIST (insn, LOG_LINKS (use_insn));
981 next_use[regno] = NULL_RTX;
984 for (use_vec = DF_INSN_USES (insn); *use_vec; use_vec++)
986 df_ref use = *use_vec;
987 int regno = DF_REF_REGNO (use);
989 /* Do not consider the usage of the stack pointer
991 if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE)
994 next_use[regno] = insn;
1002 /* Clear LOG_LINKS fields of insns. */
1005 clear_log_links (void)
1009 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
1011 free_INSN_LIST_list (&LOG_LINKS (insn));
1017 /* Main entry point for combiner. F is the first insn of the function.
1018 NREGS is the first unused pseudo-reg number.
1020 Return nonzero if the combiner has turned an indirect jump
1021 instruction into a direct jump. */
1023 combine_instructions (rtx f, unsigned int nregs)
1029 rtx links, nextlinks;
1032 int new_direct_jump_p = 0;
1034 for (first = f; first && !INSN_P (first); )
1035 first = NEXT_INSN (first);
1039 combine_attempts = 0;
1042 combine_successes = 0;
1044 rtl_hooks = combine_rtl_hooks;
1046 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
1048 init_recog_no_volatile ();
1050 /* Allocate array for insn info. */
1051 max_uid_known = get_max_uid ();
1052 uid_log_links = XCNEWVEC (rtx, max_uid_known + 1);
1053 uid_insn_cost = XCNEWVEC (int, max_uid_known + 1);
1055 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
1057 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1058 problems when, for example, we have j <<= 1 in a loop. */
1060 nonzero_sign_valid = 0;
1062 /* Scan all SETs and see if we can deduce anything about what
1063 bits are known to be zero for some registers and how many copies
1064 of the sign bit are known to exist for those registers.
1066 Also set any known values so that we can use it while searching
1067 for what bits are known to be set. */
1069 setup_incoming_promotions (first);
1071 create_log_links ();
1072 label_tick_ebb_start = ENTRY_BLOCK_PTR->index;
1073 FOR_EACH_BB (this_basic_block)
1075 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1078 label_tick = this_basic_block->index;
1079 if (!single_pred_p (this_basic_block)
1080 || single_pred (this_basic_block)->index != label_tick - 1)
1081 label_tick_ebb_start = label_tick;
1082 FOR_BB_INSNS (this_basic_block, insn)
1083 if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
1085 subst_low_luid = DF_INSN_LUID (insn);
1088 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
1090 record_dead_and_set_regs (insn);
1093 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
1094 if (REG_NOTE_KIND (links) == REG_INC)
1095 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
1099 /* Record the current insn_rtx_cost of this instruction. */
1100 if (NONJUMP_INSN_P (insn))
1101 INSN_COST (insn) = insn_rtx_cost (PATTERN (insn),
1102 optimize_this_for_speed_p);
1104 fprintf(dump_file, "insn_cost %d: %d\n",
1105 INSN_UID (insn), INSN_COST (insn));
1109 nonzero_sign_valid = 1;
1111 /* Now scan all the insns in forward order. */
1113 label_tick_ebb_start = ENTRY_BLOCK_PTR->index;
1115 setup_incoming_promotions (first);
1117 FOR_EACH_BB (this_basic_block)
1119 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1122 label_tick = this_basic_block->index;
1123 if (!single_pred_p (this_basic_block)
1124 || single_pred (this_basic_block)->index != label_tick - 1)
1125 label_tick_ebb_start = label_tick;
1126 rtl_profile_for_bb (this_basic_block);
1127 for (insn = BB_HEAD (this_basic_block);
1128 insn != NEXT_INSN (BB_END (this_basic_block));
1129 insn = next ? next : NEXT_INSN (insn))
1132 if (NONDEBUG_INSN_P (insn))
1134 /* See if we know about function return values before this
1135 insn based upon SUBREG flags. */
1136 check_promoted_subreg (insn, PATTERN (insn));
1138 /* See if we can find hardregs and subreg of pseudos in
1139 narrower modes. This could help turning TRUNCATEs
1141 note_uses (&PATTERN (insn), record_truncated_values, NULL);
1143 /* Try this insn with each insn it links back to. */
1145 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1146 if ((next = try_combine (insn, XEXP (links, 0),
1147 NULL_RTX, &new_direct_jump_p)) != 0)
1150 /* Try each sequence of three linked insns ending with this one. */
1152 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1154 rtx link = XEXP (links, 0);
1156 /* If the linked insn has been replaced by a note, then there
1157 is no point in pursuing this chain any further. */
1161 for (nextlinks = LOG_LINKS (link);
1163 nextlinks = XEXP (nextlinks, 1))
1164 if ((next = try_combine (insn, link,
1165 XEXP (nextlinks, 0),
1166 &new_direct_jump_p)) != 0)
1171 /* Try to combine a jump insn that uses CC0
1172 with a preceding insn that sets CC0, and maybe with its
1173 logical predecessor as well.
1174 This is how we make decrement-and-branch insns.
1175 We need this special code because data flow connections
1176 via CC0 do not get entered in LOG_LINKS. */
1179 && (prev = prev_nonnote_insn (insn)) != 0
1180 && NONJUMP_INSN_P (prev)
1181 && sets_cc0_p (PATTERN (prev)))
1183 if ((next = try_combine (insn, prev,
1184 NULL_RTX, &new_direct_jump_p)) != 0)
1187 for (nextlinks = LOG_LINKS (prev); nextlinks;
1188 nextlinks = XEXP (nextlinks, 1))
1189 if ((next = try_combine (insn, prev,
1190 XEXP (nextlinks, 0),
1191 &new_direct_jump_p)) != 0)
1195 /* Do the same for an insn that explicitly references CC0. */
1196 if (NONJUMP_INSN_P (insn)
1197 && (prev = prev_nonnote_insn (insn)) != 0
1198 && NONJUMP_INSN_P (prev)
1199 && sets_cc0_p (PATTERN (prev))
1200 && GET_CODE (PATTERN (insn)) == SET
1201 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
1203 if ((next = try_combine (insn, prev,
1204 NULL_RTX, &new_direct_jump_p)) != 0)
1207 for (nextlinks = LOG_LINKS (prev); nextlinks;
1208 nextlinks = XEXP (nextlinks, 1))
1209 if ((next = try_combine (insn, prev,
1210 XEXP (nextlinks, 0),
1211 &new_direct_jump_p)) != 0)
1215 /* Finally, see if any of the insns that this insn links to
1216 explicitly references CC0. If so, try this insn, that insn,
1217 and its predecessor if it sets CC0. */
1218 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1219 if (NONJUMP_INSN_P (XEXP (links, 0))
1220 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
1221 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
1222 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
1223 && NONJUMP_INSN_P (prev)
1224 && sets_cc0_p (PATTERN (prev))
1225 && (next = try_combine (insn, XEXP (links, 0),
1226 prev, &new_direct_jump_p)) != 0)
1230 /* Try combining an insn with two different insns whose results it
1232 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1233 for (nextlinks = XEXP (links, 1); nextlinks;
1234 nextlinks = XEXP (nextlinks, 1))
1235 if ((next = try_combine (insn, XEXP (links, 0),
1236 XEXP (nextlinks, 0),
1237 &new_direct_jump_p)) != 0)
1240 /* Try this insn with each REG_EQUAL note it links back to. */
1241 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1244 rtx temp = XEXP (links, 0);
1245 if ((set = single_set (temp)) != 0
1246 && (note = find_reg_equal_equiv_note (temp)) != 0
1247 && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
1248 /* Avoid using a register that may already been marked
1249 dead by an earlier instruction. */
1250 && ! unmentioned_reg_p (note, SET_SRC (set))
1251 && (GET_MODE (note) == VOIDmode
1252 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
1253 : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
1255 /* Temporarily replace the set's source with the
1256 contents of the REG_EQUAL note. The insn will
1257 be deleted or recognized by try_combine. */
1258 rtx orig = SET_SRC (set);
1259 SET_SRC (set) = note;
1261 i2mod_old_rhs = copy_rtx (orig);
1262 i2mod_new_rhs = copy_rtx (note);
1263 next = try_combine (insn, i2mod, NULL_RTX,
1264 &new_direct_jump_p);
1268 SET_SRC (set) = orig;
1273 record_dead_and_set_regs (insn);
1281 default_rtl_profile ();
1284 new_direct_jump_p |= purge_all_dead_edges ();
1285 delete_noop_moves ();
1288 free (uid_log_links);
1289 free (uid_insn_cost);
1290 VEC_free (reg_stat_type, heap, reg_stat);
1293 struct undo *undo, *next;
1294 for (undo = undobuf.frees; undo; undo = next)
1302 total_attempts += combine_attempts;
1303 total_merges += combine_merges;
1304 total_extras += combine_extras;
1305 total_successes += combine_successes;
1307 nonzero_sign_valid = 0;
1308 rtl_hooks = general_rtl_hooks;
1310 /* Make recognizer allow volatile MEMs again. */
1313 return new_direct_jump_p;
1316 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1319 init_reg_last (void)
1324 for (i = 0; VEC_iterate (reg_stat_type, reg_stat, i, p); ++i)
1325 memset (p, 0, offsetof (reg_stat_type, sign_bit_copies));
1328 /* Set up any promoted values for incoming argument registers. */
1331 setup_incoming_promotions (rtx first)
1334 bool strictly_local = false;
1336 for (arg = DECL_ARGUMENTS (current_function_decl); arg;
1337 arg = TREE_CHAIN (arg))
1339 rtx reg = DECL_INCOMING_RTL (arg);
1341 enum machine_mode mode1, mode2, mode3, mode4;
1343 /* Only continue if the incoming argument is in a register. */
1347 /* Determine, if possible, whether all call sites of the current
1348 function lie within the current compilation unit. (This does
1349 take into account the exporting of a function via taking its
1350 address, and so forth.) */
1351 strictly_local = cgraph_local_info (current_function_decl)->local;
1353 /* The mode and signedness of the argument before any promotions happen
1354 (equal to the mode of the pseudo holding it at that stage). */
1355 mode1 = TYPE_MODE (TREE_TYPE (arg));
1356 uns1 = TYPE_UNSIGNED (TREE_TYPE (arg));
1358 /* The mode and signedness of the argument after any source language and
1359 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1360 mode2 = TYPE_MODE (DECL_ARG_TYPE (arg));
1361 uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg));
1363 /* The mode and signedness of the argument as it is actually passed,
1364 after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */
1365 mode3 = promote_function_mode (DECL_ARG_TYPE (arg), mode2, &uns3,
1366 TREE_TYPE (cfun->decl), 0);
1368 /* The mode of the register in which the argument is being passed. */
1369 mode4 = GET_MODE (reg);
1371 /* Eliminate sign extensions in the callee when possible. Only
1373 (a) a mode promotion has occurred;
1374 (b) the mode of the register is the same as the mode of
1375 the argument as it is passed; and
1376 (c) the signedness does not change across any of the promotions; and
1377 (d) when no language-level promotions (which we cannot guarantee
1378 will have been done by an external caller) are necessary,
1379 unless we know that this function is only ever called from
1380 the current compilation unit -- all of whose call sites will
1381 do the mode1 --> mode2 promotion. */
1385 && (mode1 == mode2 || strictly_local))
1387 /* Record that the value was promoted from mode1 to mode3,
1388 so that any sign extension at the head of the current
1389 function may be eliminated. */
1391 x = gen_rtx_CLOBBER (mode1, const0_rtx);
1392 x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x);
1393 record_value_for_reg (reg, first, x);
1398 /* Called via note_stores. If X is a pseudo that is narrower than
1399 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1401 If we are setting only a portion of X and we can't figure out what
1402 portion, assume all bits will be used since we don't know what will
1405 Similarly, set how many bits of X are known to be copies of the sign bit
1406 at all locations in the function. This is the smallest number implied
1410 set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data)
1412 rtx insn = (rtx) data;
1416 && REGNO (x) >= FIRST_PSEUDO_REGISTER
1417 /* If this register is undefined at the start of the file, we can't
1418 say what its contents were. */
1419 && ! REGNO_REG_SET_P
1420 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x))
1421 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
1423 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
1425 if (set == 0 || GET_CODE (set) == CLOBBER)
1427 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1428 rsp->sign_bit_copies = 1;
1432 /* If this register is being initialized using itself, and the
1433 register is uninitialized in this basic block, and there are
1434 no LOG_LINKS which set the register, then part of the
1435 register is uninitialized. In that case we can't assume
1436 anything about the number of nonzero bits.
1438 ??? We could do better if we checked this in
1439 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1440 could avoid making assumptions about the insn which initially
1441 sets the register, while still using the information in other
1442 insns. We would have to be careful to check every insn
1443 involved in the combination. */
1446 && reg_referenced_p (x, PATTERN (insn))
1447 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)),
1452 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
1454 if (dead_or_set_p (XEXP (link, 0), x))
1459 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1460 rsp->sign_bit_copies = 1;
1465 /* If this is a complex assignment, see if we can convert it into a
1466 simple assignment. */
1467 set = expand_field_assignment (set);
1469 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1470 set what we know about X. */
1472 if (SET_DEST (set) == x
1473 || (GET_CODE (SET_DEST (set)) == SUBREG
1474 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
1475 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
1476 && SUBREG_REG (SET_DEST (set)) == x))
1478 rtx src = SET_SRC (set);
1480 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1481 /* If X is narrower than a word and SRC is a non-negative
1482 constant that would appear negative in the mode of X,
1483 sign-extend it for use in reg_stat[].nonzero_bits because some
1484 machines (maybe most) will actually do the sign-extension
1485 and this is the conservative approach.
1487 ??? For 2.5, try to tighten up the MD files in this regard
1488 instead of this kludge. */
1490 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
1491 && CONST_INT_P (src)
1493 && 0 != (INTVAL (src)
1494 & ((HOST_WIDE_INT) 1
1495 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
1496 src = GEN_INT (INTVAL (src)
1497 | ((HOST_WIDE_INT) (-1)
1498 << GET_MODE_BITSIZE (GET_MODE (x))));
1501 /* Don't call nonzero_bits if it cannot change anything. */
1502 if (rsp->nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1503 rsp->nonzero_bits |= nonzero_bits (src, nonzero_bits_mode);
1504 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1505 if (rsp->sign_bit_copies == 0
1506 || rsp->sign_bit_copies > num)
1507 rsp->sign_bit_copies = num;
1511 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1512 rsp->sign_bit_copies = 1;
1517 /* See if INSN can be combined into I3. PRED and SUCC are optionally
1518 insns that were previously combined into I3 or that will be combined
1519 into the merger of INSN and I3.
1521 Return 0 if the combination is not allowed for any reason.
1523 If the combination is allowed, *PDEST will be set to the single
1524 destination of INSN and *PSRC to the single source, and this function
1528 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ,
1529 rtx *pdest, rtx *psrc)
1538 int all_adjacent = (succ ? (next_active_insn (insn) == succ
1539 && next_active_insn (succ) == i3)
1540 : next_active_insn (insn) == i3);
1542 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1543 or a PARALLEL consisting of such a SET and CLOBBERs.
1545 If INSN has CLOBBER parallel parts, ignore them for our processing.
1546 By definition, these happen during the execution of the insn. When it
1547 is merged with another insn, all bets are off. If they are, in fact,
1548 needed and aren't also supplied in I3, they may be added by
1549 recog_for_combine. Otherwise, it won't match.
1551 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1554 Get the source and destination of INSN. If more than one, can't
1557 if (GET_CODE (PATTERN (insn)) == SET)
1558 set = PATTERN (insn);
1559 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1560 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1562 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1564 rtx elt = XVECEXP (PATTERN (insn), 0, i);
1566 switch (GET_CODE (elt))
1568 /* This is important to combine floating point insns
1569 for the SH4 port. */
1571 /* Combining an isolated USE doesn't make sense.
1572 We depend here on combinable_i3pat to reject them. */
1573 /* The code below this loop only verifies that the inputs of
1574 the SET in INSN do not change. We call reg_set_between_p
1575 to verify that the REG in the USE does not change between
1577 If the USE in INSN was for a pseudo register, the matching
1578 insn pattern will likely match any register; combining this
1579 with any other USE would only be safe if we knew that the
1580 used registers have identical values, or if there was
1581 something to tell them apart, e.g. different modes. For
1582 now, we forgo such complicated tests and simply disallow
1583 combining of USES of pseudo registers with any other USE. */
1584 if (REG_P (XEXP (elt, 0))
1585 && GET_CODE (PATTERN (i3)) == PARALLEL)
1587 rtx i3pat = PATTERN (i3);
1588 int i = XVECLEN (i3pat, 0) - 1;
1589 unsigned int regno = REGNO (XEXP (elt, 0));
1593 rtx i3elt = XVECEXP (i3pat, 0, i);
1595 if (GET_CODE (i3elt) == USE
1596 && REG_P (XEXP (i3elt, 0))
1597 && (REGNO (XEXP (i3elt, 0)) == regno
1598 ? reg_set_between_p (XEXP (elt, 0),
1599 PREV_INSN (insn), i3)
1600 : regno >= FIRST_PSEUDO_REGISTER))
1607 /* We can ignore CLOBBERs. */
1612 /* Ignore SETs whose result isn't used but not those that
1613 have side-effects. */
1614 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1615 && insn_nothrow_p (insn)
1616 && !side_effects_p (elt))
1619 /* If we have already found a SET, this is a second one and
1620 so we cannot combine with this insn. */
1628 /* Anything else means we can't combine. */
1634 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1635 so don't do anything with it. */
1636 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1645 set = expand_field_assignment (set);
1646 src = SET_SRC (set), dest = SET_DEST (set);
1648 /* Don't eliminate a store in the stack pointer. */
1649 if (dest == stack_pointer_rtx
1650 /* Don't combine with an insn that sets a register to itself if it has
1651 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1652 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1653 /* Can't merge an ASM_OPERANDS. */
1654 || GET_CODE (src) == ASM_OPERANDS
1655 /* Can't merge a function call. */
1656 || GET_CODE (src) == CALL
1657 /* Don't eliminate a function call argument. */
1659 && (find_reg_fusage (i3, USE, dest)
1661 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1662 && global_regs[REGNO (dest)])))
1663 /* Don't substitute into an incremented register. */
1664 || FIND_REG_INC_NOTE (i3, dest)
1665 || (succ && FIND_REG_INC_NOTE (succ, dest))
1666 /* Don't substitute into a non-local goto, this confuses CFG. */
1667 || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1668 /* Make sure that DEST is not used after SUCC but before I3. */
1669 || (succ && ! all_adjacent
1670 && reg_used_between_p (dest, succ, i3))
1671 /* Make sure that the value that is to be substituted for the register
1672 does not use any registers whose values alter in between. However,
1673 If the insns are adjacent, a use can't cross a set even though we
1674 think it might (this can happen for a sequence of insns each setting
1675 the same destination; last_set of that register might point to
1676 a NOTE). If INSN has a REG_EQUIV note, the register is always
1677 equivalent to the memory so the substitution is valid even if there
1678 are intervening stores. Also, don't move a volatile asm or
1679 UNSPEC_VOLATILE across any other insns. */
1682 || ! find_reg_note (insn, REG_EQUIV, src))
1683 && use_crosses_set_p (src, DF_INSN_LUID (insn)))
1684 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1685 || GET_CODE (src) == UNSPEC_VOLATILE))
1686 /* Don't combine across a CALL_INSN, because that would possibly
1687 change whether the life span of some REGs crosses calls or not,
1688 and it is a pain to update that information.
1689 Exception: if source is a constant, moving it later can't hurt.
1690 Accept that as a special case. */
1691 || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src)))
1694 /* DEST must either be a REG or CC0. */
1697 /* If register alignment is being enforced for multi-word items in all
1698 cases except for parameters, it is possible to have a register copy
1699 insn referencing a hard register that is not allowed to contain the
1700 mode being copied and which would not be valid as an operand of most
1701 insns. Eliminate this problem by not combining with such an insn.
1703 Also, on some machines we don't want to extend the life of a hard
1707 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1708 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1709 /* Don't extend the life of a hard register unless it is
1710 user variable (if we have few registers) or it can't
1711 fit into the desired register (meaning something special
1713 Also avoid substituting a return register into I3, because
1714 reload can't handle a conflict with constraints of other
1716 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1717 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1720 else if (GET_CODE (dest) != CC0)
1724 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1725 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1726 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1728 /* Don't substitute for a register intended as a clobberable
1730 rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1731 if (rtx_equal_p (reg, dest))
1734 /* If the clobber represents an earlyclobber operand, we must not
1735 substitute an expression containing the clobbered register.
1736 As we do not analyze the constraint strings here, we have to
1737 make the conservative assumption. However, if the register is
1738 a fixed hard reg, the clobber cannot represent any operand;
1739 we leave it up to the machine description to either accept or
1740 reject use-and-clobber patterns. */
1742 || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1743 || !fixed_regs[REGNO (reg)])
1744 if (reg_overlap_mentioned_p (reg, src))
1748 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1749 or not), reject, unless nothing volatile comes between it and I3 */
1751 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1753 /* Make sure succ doesn't contain a volatile reference. */
1754 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1757 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1758 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1762 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1763 to be an explicit register variable, and was chosen for a reason. */
1765 if (GET_CODE (src) == ASM_OPERANDS
1766 && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1769 /* If there are any volatile insns between INSN and I3, reject, because
1770 they might affect machine state. */
1772 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1773 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1776 /* If INSN contains an autoincrement or autodecrement, make sure that
1777 register is not used between there and I3, and not already used in
1778 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1779 Also insist that I3 not be a jump; if it were one
1780 and the incremented register were spilled, we would lose. */
1783 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1784 if (REG_NOTE_KIND (link) == REG_INC
1786 || reg_used_between_p (XEXP (link, 0), insn, i3)
1787 || (pred != NULL_RTX
1788 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1789 || (succ != NULL_RTX
1790 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1791 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1796 /* Don't combine an insn that follows a CC0-setting insn.
1797 An insn that uses CC0 must not be separated from the one that sets it.
1798 We do, however, allow I2 to follow a CC0-setting insn if that insn
1799 is passed as I1; in that case it will be deleted also.
1800 We also allow combining in this case if all the insns are adjacent
1801 because that would leave the two CC0 insns adjacent as well.
1802 It would be more logical to test whether CC0 occurs inside I1 or I2,
1803 but that would be much slower, and this ought to be equivalent. */
1805 p = prev_nonnote_insn (insn);
1806 if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
1811 /* If we get here, we have passed all the tests and the combination is
1820 /* LOC is the location within I3 that contains its pattern or the component
1821 of a PARALLEL of the pattern. We validate that it is valid for combining.
1823 One problem is if I3 modifies its output, as opposed to replacing it
1824 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1825 so would produce an insn that is not equivalent to the original insns.
1829 (set (reg:DI 101) (reg:DI 100))
1830 (set (subreg:SI (reg:DI 101) 0) <foo>)
1832 This is NOT equivalent to:
1834 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1835 (set (reg:DI 101) (reg:DI 100))])
1837 Not only does this modify 100 (in which case it might still be valid
1838 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1840 We can also run into a problem if I2 sets a register that I1
1841 uses and I1 gets directly substituted into I3 (not via I2). In that
1842 case, we would be getting the wrong value of I2DEST into I3, so we
1843 must reject the combination. This case occurs when I2 and I1 both
1844 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1845 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1846 of a SET must prevent combination from occurring.
1848 Before doing the above check, we first try to expand a field assignment
1849 into a set of logical operations.
1851 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1852 we place a register that is both set and used within I3. If more than one
1853 such register is detected, we fail.
1855 Return 1 if the combination is valid, zero otherwise. */
1858 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest,
1859 int i1_not_in_src, rtx *pi3dest_killed)
1863 if (GET_CODE (x) == SET)
1866 rtx dest = SET_DEST (set);
1867 rtx src = SET_SRC (set);
1868 rtx inner_dest = dest;
1871 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1872 || GET_CODE (inner_dest) == SUBREG
1873 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1874 inner_dest = XEXP (inner_dest, 0);
1876 /* Check for the case where I3 modifies its output, as discussed
1877 above. We don't want to prevent pseudos from being combined
1878 into the address of a MEM, so only prevent the combination if
1879 i1 or i2 set the same MEM. */
1880 if ((inner_dest != dest &&
1881 (!MEM_P (inner_dest)
1882 || rtx_equal_p (i2dest, inner_dest)
1883 || (i1dest && rtx_equal_p (i1dest, inner_dest)))
1884 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1885 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1887 /* This is the same test done in can_combine_p except we can't test
1888 all_adjacent; we don't have to, since this instruction will stay
1889 in place, thus we are not considering increasing the lifetime of
1892 Also, if this insn sets a function argument, combining it with
1893 something that might need a spill could clobber a previous
1894 function argument; the all_adjacent test in can_combine_p also
1895 checks this; here, we do a more specific test for this case. */
1897 || (REG_P (inner_dest)
1898 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1899 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1900 GET_MODE (inner_dest))))
1901 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1904 /* If DEST is used in I3, it is being killed in this insn, so
1905 record that for later. We have to consider paradoxical
1906 subregs here, since they kill the whole register, but we
1907 ignore partial subregs, STRICT_LOW_PART, etc.
1908 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1909 STACK_POINTER_REGNUM, since these are always considered to be
1910 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1912 if (GET_CODE (subdest) == SUBREG
1913 && (GET_MODE_SIZE (GET_MODE (subdest))
1914 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
1915 subdest = SUBREG_REG (subdest);
1918 && reg_referenced_p (subdest, PATTERN (i3))
1919 && REGNO (subdest) != FRAME_POINTER_REGNUM
1920 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1921 && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
1923 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1924 && (REGNO (subdest) != ARG_POINTER_REGNUM
1925 || ! fixed_regs [REGNO (subdest)])
1927 && REGNO (subdest) != STACK_POINTER_REGNUM)
1929 if (*pi3dest_killed)
1932 *pi3dest_killed = subdest;
1936 else if (GET_CODE (x) == PARALLEL)
1940 for (i = 0; i < XVECLEN (x, 0); i++)
1941 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1942 i1_not_in_src, pi3dest_killed))
1949 /* Return 1 if X is an arithmetic expression that contains a multiplication
1950 and division. We don't count multiplications by powers of two here. */
1953 contains_muldiv (rtx x)
1955 switch (GET_CODE (x))
1957 case MOD: case DIV: case UMOD: case UDIV:
1961 return ! (CONST_INT_P (XEXP (x, 1))
1962 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1965 return contains_muldiv (XEXP (x, 0))
1966 || contains_muldiv (XEXP (x, 1));
1969 return contains_muldiv (XEXP (x, 0));
1975 /* Determine whether INSN can be used in a combination. Return nonzero if
1976 not. This is used in try_combine to detect early some cases where we
1977 can't perform combinations. */
1980 cant_combine_insn_p (rtx insn)
1985 /* If this isn't really an insn, we can't do anything.
1986 This can occur when flow deletes an insn that it has merged into an
1987 auto-increment address. */
1988 if (! INSN_P (insn))
1991 /* Never combine loads and stores involving hard regs that are likely
1992 to be spilled. The register allocator can usually handle such
1993 reg-reg moves by tying. If we allow the combiner to make
1994 substitutions of likely-spilled regs, reload might die.
1995 As an exception, we allow combinations involving fixed regs; these are
1996 not available to the register allocator so there's no risk involved. */
1998 set = single_set (insn);
2001 src = SET_SRC (set);
2002 dest = SET_DEST (set);
2003 if (GET_CODE (src) == SUBREG)
2004 src = SUBREG_REG (src);
2005 if (GET_CODE (dest) == SUBREG)
2006 dest = SUBREG_REG (dest);
2007 if (REG_P (src) && REG_P (dest)
2008 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
2009 && ! fixed_regs[REGNO (src)]
2010 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src))))
2011 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
2012 && ! fixed_regs[REGNO (dest)]
2013 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest))))))
2019 struct likely_spilled_retval_info
2021 unsigned regno, nregs;
2025 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2026 hard registers that are known to be written to / clobbered in full. */
2028 likely_spilled_retval_1 (rtx x, const_rtx set, void *data)
2030 struct likely_spilled_retval_info *const info =
2031 (struct likely_spilled_retval_info *) data;
2032 unsigned regno, nregs;
2035 if (!REG_P (XEXP (set, 0)))
2038 if (regno >= info->regno + info->nregs)
2040 nregs = hard_regno_nregs[regno][GET_MODE (x)];
2041 if (regno + nregs <= info->regno)
2043 new_mask = (2U << (nregs - 1)) - 1;
2044 if (regno < info->regno)
2045 new_mask >>= info->regno - regno;
2047 new_mask <<= regno - info->regno;
2048 info->mask &= ~new_mask;
2051 /* Return nonzero iff part of the return value is live during INSN, and
2052 it is likely spilled. This can happen when more than one insn is needed
2053 to copy the return value, e.g. when we consider to combine into the
2054 second copy insn for a complex value. */
2057 likely_spilled_retval_p (rtx insn)
2059 rtx use = BB_END (this_basic_block);
2061 unsigned regno, nregs;
2062 /* We assume here that no machine mode needs more than
2063 32 hard registers when the value overlaps with a register
2064 for which FUNCTION_VALUE_REGNO_P is true. */
2066 struct likely_spilled_retval_info info;
2068 if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
2070 reg = XEXP (PATTERN (use), 0);
2071 if (!REG_P (reg) || !FUNCTION_VALUE_REGNO_P (REGNO (reg)))
2073 regno = REGNO (reg);
2074 nregs = hard_regno_nregs[regno][GET_MODE (reg)];
2077 mask = (2U << (nregs - 1)) - 1;
2079 /* Disregard parts of the return value that are set later. */
2083 for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
2085 note_stores (PATTERN (p), likely_spilled_retval_1, &info);
2088 /* Check if any of the (probably) live return value registers is
2093 if ((mask & 1 << nregs)
2094 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (regno + nregs)))
2100 /* Adjust INSN after we made a change to its destination.
2102 Changing the destination can invalidate notes that say something about
2103 the results of the insn and a LOG_LINK pointing to the insn. */
2106 adjust_for_new_dest (rtx insn)
2108 /* For notes, be conservative and simply remove them. */
2109 remove_reg_equal_equiv_notes (insn);
2111 /* The new insn will have a destination that was previously the destination
2112 of an insn just above it. Call distribute_links to make a LOG_LINK from
2113 the next use of that destination. */
2114 distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX));
2116 df_insn_rescan (insn);
2119 /* Return TRUE if combine can reuse reg X in mode MODE.
2120 ADDED_SETS is nonzero if the original set is still required. */
2122 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
2130 /* Allow hard registers if the new mode is legal, and occupies no more
2131 registers than the old mode. */
2132 if (regno < FIRST_PSEUDO_REGISTER)
2133 return (HARD_REGNO_MODE_OK (regno, mode)
2134 && (hard_regno_nregs[regno][GET_MODE (x)]
2135 >= hard_regno_nregs[regno][mode]));
2137 /* Or a pseudo that is only used once. */
2138 return (REG_N_SETS (regno) == 1 && !added_sets
2139 && !REG_USERVAR_P (x));
2143 /* Check whether X, the destination of a set, refers to part of
2144 the register specified by REG. */
2147 reg_subword_p (rtx x, rtx reg)
2149 /* Check that reg is an integer mode register. */
2150 if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
2153 if (GET_CODE (x) == STRICT_LOW_PART
2154 || GET_CODE (x) == ZERO_EXTRACT)
2157 return GET_CODE (x) == SUBREG
2158 && SUBREG_REG (x) == reg
2159 && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
2163 /* Replace auto-increment addressing modes with explicit operations to
2164 access the same addresses without modifying the corresponding
2165 registers. If AFTER holds, SRC is meant to be reused after the
2166 side effect, otherwise it is to be reused before that. */
2169 cleanup_auto_inc_dec (rtx src, bool after, enum machine_mode mem_mode)
2172 const RTX_CODE code = GET_CODE (x);
2188 /* SCRATCH must be shared because they represent distinct values. */
2191 if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
2196 if (shared_const_p (x))
2201 mem_mode = GET_MODE (x);
2208 gcc_assert (mem_mode != VOIDmode && mem_mode != BLKmode);
2209 if (after == (code == PRE_INC || code == PRE_DEC))
2210 x = cleanup_auto_inc_dec (XEXP (x, 0), after, mem_mode);
2212 x = gen_rtx_PLUS (GET_MODE (x),
2213 cleanup_auto_inc_dec (XEXP (x, 0), after, mem_mode),
2214 GEN_INT ((code == PRE_INC || code == POST_INC)
2215 ? GET_MODE_SIZE (mem_mode)
2216 : -GET_MODE_SIZE (mem_mode)));
2221 if (after == (code == PRE_MODIFY))
2225 return cleanup_auto_inc_dec (x, after, mem_mode);
2231 /* Copy the various flags, fields, and other information. We assume
2232 that all fields need copying, and then clear the fields that should
2233 not be copied. That is the sensible default behavior, and forces
2234 us to explicitly document why we are *not* copying a flag. */
2235 x = shallow_copy_rtx (x);
2237 /* We do not copy the USED flag, which is used as a mark bit during
2238 walks over the RTL. */
2239 RTX_FLAG (x, used) = 0;
2241 /* We do not copy FRAME_RELATED for INSNs. */
2243 RTX_FLAG (x, frame_related) = 0;
2245 fmt = GET_RTX_FORMAT (code);
2246 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2248 XEXP (x, i) = cleanup_auto_inc_dec (XEXP (x, i), after, mem_mode);
2249 else if (fmt[i] == 'E' || fmt[i] == 'V')
2252 XVEC (x, i) = rtvec_alloc (XVECLEN (x, i));
2253 for (j = 0; j < XVECLEN (x, i); j++)
2255 = cleanup_auto_inc_dec (XVECEXP (src, i, j), after, mem_mode);
2262 /* Auxiliary data structure for propagate_for_debug_stmt. */
2264 struct rtx_subst_pair
2274 /* Clean up any auto-updates in PAIR->to the first time it is called
2275 for a PAIR. PAIR->adjusted is used to tell whether we've cleaned
2279 auto_adjust_pair (struct rtx_subst_pair *pair ATTRIBUTE_UNUSED)
2282 if (!pair->adjusted)
2284 pair->adjusted = true;
2285 pair->to = cleanup_auto_inc_dec (pair->to, pair->after, VOIDmode);
2290 /* If *LOC is the same as FROM in the struct rtx_subst_pair passed as
2291 DATA, replace it with a copy of TO. Handle SUBREGs of *LOC as
2295 propagate_for_debug_subst (rtx *loc, void *data)
2297 struct rtx_subst_pair *pair = (struct rtx_subst_pair *)data;
2298 rtx from = pair->from, to = pair->to;
2299 rtx x = *loc, s = x;
2301 if (rtx_equal_p (x, from)
2302 || (GET_CODE (x) == SUBREG && rtx_equal_p ((s = SUBREG_REG (x)), from)))
2304 auto_adjust_pair (pair);
2311 gcc_assert (GET_CODE (x) == SUBREG && SUBREG_REG (x) == s);
2312 to = simplify_gen_subreg (GET_MODE (x), to,
2313 GET_MODE (from), SUBREG_BYTE (x));
2315 *loc = wrap_constant (GET_MODE (x), to);
2316 pair->changed = true;
2323 /* Replace occurrences of DEST with SRC in DEBUG_INSNs between INSN
2324 and LAST. If MOVE holds, debug insns must also be moved past
2328 propagate_for_debug (rtx insn, rtx last, rtx dest, rtx src, bool move)
2330 struct rtx_subst_pair p;
2331 rtx next, move_pos = move ? last : NULL_RTX;
2342 next = NEXT_INSN (insn);
2343 while (next != last)
2346 next = NEXT_INSN (insn);
2347 if (DEBUG_INSN_P (insn))
2349 for_each_rtx (&INSN_VAR_LOCATION_LOC (insn),
2350 propagate_for_debug_subst, &p);
2357 PREV_INSN (insn) = NEXT_INSN (insn) = NULL_RTX;
2358 move_pos = emit_debug_insn_after (insn, move_pos);
2361 df_insn_rescan (insn);
2366 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2367 Note that the INSN should be deleted *after* removing dead edges, so
2368 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2369 but not for a (set (pc) (label_ref FOO)). */
2372 update_cfg_for_uncondjump (rtx insn)
2374 basic_block bb = BLOCK_FOR_INSN (insn);
2375 bool at_end = (BB_END (bb) == insn);
2378 purge_dead_edges (bb);
2381 if (at_end && EDGE_COUNT (bb->succs) == 1)
2382 single_succ_edge (bb)->flags |= EDGE_FALLTHRU;
2386 /* Try to combine the insns I1 and I2 into I3.
2387 Here I1 and I2 appear earlier than I3.
2388 I1 can be zero; then we combine just I2 into I3.
2390 If we are combining three insns and the resulting insn is not recognized,
2391 try splitting it into two insns. If that happens, I2 and I3 are retained
2392 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
2395 Return 0 if the combination does not work. Then nothing is changed.
2396 If we did the combination, return the insn at which combine should
2399 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2400 new direct jump instruction. */
2403 try_combine (rtx i3, rtx i2, rtx i1, int *new_direct_jump_p)
2405 /* New patterns for I3 and I2, respectively. */
2406 rtx newpat, newi2pat = 0;
2407 rtvec newpat_vec_with_clobbers = 0;
2408 int substed_i2 = 0, substed_i1 = 0;
2409 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
2410 int added_sets_1, added_sets_2;
2411 /* Total number of SETs to put into I3. */
2413 /* Nonzero if I2's body now appears in I3. */
2415 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2416 int insn_code_number, i2_code_number = 0, other_code_number = 0;
2417 /* Contains I3 if the destination of I3 is used in its source, which means
2418 that the old life of I3 is being killed. If that usage is placed into
2419 I2 and not in I3, a REG_DEAD note must be made. */
2420 rtx i3dest_killed = 0;
2421 /* SET_DEST and SET_SRC of I2 and I1. */
2422 rtx i2dest = 0, i2src = 0, i1dest = 0, i1src = 0;
2423 /* Set if I2DEST was reused as a scratch register. */
2424 bool i2scratch = false;
2425 /* PATTERN (I1) and PATTERN (I2), or a copy of it in certain cases. */
2426 rtx i1pat = 0, i2pat = 0;
2427 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2428 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
2429 int i2dest_killed = 0, i1dest_killed = 0;
2430 int i1_feeds_i3 = 0;
2431 /* Notes that must be added to REG_NOTES in I3 and I2. */
2432 rtx new_i3_notes, new_i2_notes;
2433 /* Notes that we substituted I3 into I2 instead of the normal case. */
2434 int i3_subst_into_i2 = 0;
2435 /* Notes that I1, I2 or I3 is a MULT operation. */
2438 int changed_i3_dest = 0;
2444 rtx new_other_notes;
2447 /* Exit early if one of the insns involved can't be used for
2449 if (cant_combine_insn_p (i3)
2450 || cant_combine_insn_p (i2)
2451 || (i1 && cant_combine_insn_p (i1))
2452 || likely_spilled_retval_p (i3))
2456 undobuf.other_insn = 0;
2458 /* Reset the hard register usage information. */
2459 CLEAR_HARD_REG_SET (newpat_used_regs);
2461 if (dump_file && (dump_flags & TDF_DETAILS))
2464 fprintf (dump_file, "\nTrying %d, %d -> %d:\n",
2465 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2467 fprintf (dump_file, "\nTrying %d -> %d:\n",
2468 INSN_UID (i2), INSN_UID (i3));
2471 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
2472 code below, set I1 to be the earlier of the two insns. */
2473 if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2))
2474 temp = i1, i1 = i2, i2 = temp;
2476 added_links_insn = 0;
2478 /* First check for one important special-case that the code below will
2479 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2480 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2481 we may be able to replace that destination with the destination of I3.
2482 This occurs in the common code where we compute both a quotient and
2483 remainder into a structure, in which case we want to do the computation
2484 directly into the structure to avoid register-register copies.
2486 Note that this case handles both multiple sets in I2 and also
2487 cases where I2 has a number of CLOBBER or PARALLELs.
2489 We make very conservative checks below and only try to handle the
2490 most common cases of this. For example, we only handle the case
2491 where I2 and I3 are adjacent to avoid making difficult register
2494 if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
2495 && REG_P (SET_SRC (PATTERN (i3)))
2496 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
2497 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
2498 && GET_CODE (PATTERN (i2)) == PARALLEL
2499 && ! side_effects_p (SET_DEST (PATTERN (i3)))
2500 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2501 below would need to check what is inside (and reg_overlap_mentioned_p
2502 doesn't support those codes anyway). Don't allow those destinations;
2503 the resulting insn isn't likely to be recognized anyway. */
2504 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
2505 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
2506 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
2507 SET_DEST (PATTERN (i3)))
2508 && next_active_insn (i2) == i3)
2510 rtx p2 = PATTERN (i2);
2512 /* Make sure that the destination of I3,
2513 which we are going to substitute into one output of I2,
2514 is not used within another output of I2. We must avoid making this:
2515 (parallel [(set (mem (reg 69)) ...)
2516 (set (reg 69) ...)])
2517 which is not well-defined as to order of actions.
2518 (Besides, reload can't handle output reloads for this.)
2520 The problem can also happen if the dest of I3 is a memory ref,
2521 if another dest in I2 is an indirect memory ref. */
2522 for (i = 0; i < XVECLEN (p2, 0); i++)
2523 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2524 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2525 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
2526 SET_DEST (XVECEXP (p2, 0, i))))
2529 if (i == XVECLEN (p2, 0))
2530 for (i = 0; i < XVECLEN (p2, 0); i++)
2531 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2532 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2533 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
2538 subst_low_luid = DF_INSN_LUID (i2);
2540 added_sets_2 = added_sets_1 = 0;
2541 i2src = SET_DEST (PATTERN (i3));
2542 i2dest = SET_SRC (PATTERN (i3));
2543 i2dest_killed = dead_or_set_p (i2, i2dest);
2545 /* Replace the dest in I2 with our dest and make the resulting
2546 insn the new pattern for I3. Then skip to where we
2547 validate the pattern. Everything was set up above. */
2548 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
2549 SET_DEST (PATTERN (i3)));
2552 i3_subst_into_i2 = 1;
2553 goto validate_replacement;
2557 /* If I2 is setting a pseudo to a constant and I3 is setting some
2558 sub-part of it to another constant, merge them by making a new
2561 && (temp = single_set (i2)) != 0
2562 && (CONST_INT_P (SET_SRC (temp))
2563 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
2564 && GET_CODE (PATTERN (i3)) == SET
2565 && (CONST_INT_P (SET_SRC (PATTERN (i3)))
2566 || GET_CODE (SET_SRC (PATTERN (i3))) == CONST_DOUBLE)
2567 && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
2569 rtx dest = SET_DEST (PATTERN (i3));
2573 if (GET_CODE (dest) == ZERO_EXTRACT)
2575 if (CONST_INT_P (XEXP (dest, 1))
2576 && CONST_INT_P (XEXP (dest, 2)))
2578 width = INTVAL (XEXP (dest, 1));
2579 offset = INTVAL (XEXP (dest, 2));
2580 dest = XEXP (dest, 0);
2581 if (BITS_BIG_ENDIAN)
2582 offset = GET_MODE_BITSIZE (GET_MODE (dest)) - width - offset;
2587 if (GET_CODE (dest) == STRICT_LOW_PART)
2588 dest = XEXP (dest, 0);
2589 width = GET_MODE_BITSIZE (GET_MODE (dest));
2595 /* If this is the low part, we're done. */
2596 if (subreg_lowpart_p (dest))
2598 /* Handle the case where inner is twice the size of outer. */
2599 else if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2600 == 2 * GET_MODE_BITSIZE (GET_MODE (dest)))
2601 offset += GET_MODE_BITSIZE (GET_MODE (dest));
2602 /* Otherwise give up for now. */
2608 && (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2609 <= HOST_BITS_PER_WIDE_INT * 2))
2611 HOST_WIDE_INT mhi, ohi, ihi;
2612 HOST_WIDE_INT mlo, olo, ilo;
2613 rtx inner = SET_SRC (PATTERN (i3));
2614 rtx outer = SET_SRC (temp);
2616 if (CONST_INT_P (outer))
2618 olo = INTVAL (outer);
2619 ohi = olo < 0 ? -1 : 0;
2623 olo = CONST_DOUBLE_LOW (outer);
2624 ohi = CONST_DOUBLE_HIGH (outer);
2627 if (CONST_INT_P (inner))
2629 ilo = INTVAL (inner);
2630 ihi = ilo < 0 ? -1 : 0;
2634 ilo = CONST_DOUBLE_LOW (inner);
2635 ihi = CONST_DOUBLE_HIGH (inner);
2638 if (width < HOST_BITS_PER_WIDE_INT)
2640 mlo = ((unsigned HOST_WIDE_INT) 1 << width) - 1;
2643 else if (width < HOST_BITS_PER_WIDE_INT * 2)
2645 mhi = ((unsigned HOST_WIDE_INT) 1
2646 << (width - HOST_BITS_PER_WIDE_INT)) - 1;
2658 if (offset >= HOST_BITS_PER_WIDE_INT)
2660 mhi = mlo << (offset - HOST_BITS_PER_WIDE_INT);
2662 ihi = ilo << (offset - HOST_BITS_PER_WIDE_INT);
2665 else if (offset > 0)
2667 mhi = (mhi << offset) | ((unsigned HOST_WIDE_INT) mlo
2668 >> (HOST_BITS_PER_WIDE_INT - offset));
2669 mlo = mlo << offset;
2670 ihi = (ihi << offset) | ((unsigned HOST_WIDE_INT) ilo
2671 >> (HOST_BITS_PER_WIDE_INT - offset));
2672 ilo = ilo << offset;
2675 olo = (olo & ~mlo) | ilo;
2676 ohi = (ohi & ~mhi) | ihi;
2680 subst_low_luid = DF_INSN_LUID (i2);
2681 added_sets_2 = added_sets_1 = 0;
2682 i2dest = SET_DEST (temp);
2683 i2dest_killed = dead_or_set_p (i2, i2dest);
2685 SUBST (SET_SRC (temp),
2686 immed_double_const (olo, ohi, GET_MODE (SET_DEST (temp))));
2688 newpat = PATTERN (i2);
2689 goto validate_replacement;
2694 /* If we have no I1 and I2 looks like:
2695 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2697 make up a dummy I1 that is
2700 (set (reg:CC X) (compare:CC Y (const_int 0)))
2702 (We can ignore any trailing CLOBBERs.)
2704 This undoes a previous combination and allows us to match a branch-and-
2707 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2708 && XVECLEN (PATTERN (i2), 0) >= 2
2709 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2710 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2712 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2713 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2714 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2715 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2716 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2717 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2719 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2720 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2725 /* We make I1 with the same INSN_UID as I2. This gives it
2726 the same DF_INSN_LUID for value tracking. Our fake I1 will
2727 never appear in the insn stream so giving it the same INSN_UID
2728 as I2 will not cause a problem. */
2730 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
2731 BLOCK_FOR_INSN (i2), INSN_LOCATOR (i2),
2732 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX);
2734 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2735 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2736 SET_DEST (PATTERN (i1)));
2741 /* Verify that I2 and I1 are valid for combining. */
2742 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
2743 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
2749 /* Record whether I2DEST is used in I2SRC and similarly for the other
2750 cases. Knowing this will help in register status updating below. */
2751 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2752 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2753 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2754 i2dest_killed = dead_or_set_p (i2, i2dest);
2755 i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2757 /* See if I1 directly feeds into I3. It does if I1DEST is not used
2759 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
2761 /* Ensure that I3's pattern can be the destination of combines. */
2762 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
2763 i1 && i2dest_in_i1src && i1_feeds_i3,
2770 /* See if any of the insns is a MULT operation. Unless one is, we will
2771 reject a combination that is, since it must be slower. Be conservative
2773 if (GET_CODE (i2src) == MULT
2774 || (i1 != 0 && GET_CODE (i1src) == MULT)
2775 || (GET_CODE (PATTERN (i3)) == SET
2776 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2779 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2780 We used to do this EXCEPT in one case: I3 has a post-inc in an
2781 output operand. However, that exception can give rise to insns like
2783 which is a famous insn on the PDP-11 where the value of r3 used as the
2784 source was model-dependent. Avoid this sort of thing. */
2787 if (!(GET_CODE (PATTERN (i3)) == SET
2788 && REG_P (SET_SRC (PATTERN (i3)))
2789 && MEM_P (SET_DEST (PATTERN (i3)))
2790 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2791 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2792 /* It's not the exception. */
2795 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2796 if (REG_NOTE_KIND (link) == REG_INC
2797 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2799 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2806 /* See if the SETs in I1 or I2 need to be kept around in the merged
2807 instruction: whenever the value set there is still needed past I3.
2808 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2810 For the SET in I1, we have two cases: If I1 and I2 independently
2811 feed into I3, the set in I1 needs to be kept around if I1DEST dies
2812 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2813 in I1 needs to be kept around unless I1DEST dies or is set in either
2814 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
2815 I1DEST. If so, we know I1 feeds into I2. */
2817 added_sets_2 = ! dead_or_set_p (i3, i2dest);
2820 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
2821 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
2823 /* If the set in I2 needs to be kept around, we must make a copy of
2824 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2825 PATTERN (I2), we are only substituting for the original I1DEST, not into
2826 an already-substituted copy. This also prevents making self-referential
2827 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2832 if (GET_CODE (PATTERN (i2)) == PARALLEL)
2833 i2pat = gen_rtx_SET (VOIDmode, i2dest, copy_rtx (i2src));
2835 i2pat = copy_rtx (PATTERN (i2));
2840 if (GET_CODE (PATTERN (i1)) == PARALLEL)
2841 i1pat = gen_rtx_SET (VOIDmode, i1dest, copy_rtx (i1src));
2843 i1pat = copy_rtx (PATTERN (i1));
2848 /* Substitute in the latest insn for the regs set by the earlier ones. */
2850 maxreg = max_reg_num ();
2855 /* Many machines that don't use CC0 have insns that can both perform an
2856 arithmetic operation and set the condition code. These operations will
2857 be represented as a PARALLEL with the first element of the vector
2858 being a COMPARE of an arithmetic operation with the constant zero.
2859 The second element of the vector will set some pseudo to the result
2860 of the same arithmetic operation. If we simplify the COMPARE, we won't
2861 match such a pattern and so will generate an extra insn. Here we test
2862 for this case, where both the comparison and the operation result are
2863 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2864 I2SRC. Later we will make the PARALLEL that contains I2. */
2866 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
2867 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
2868 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
2869 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2871 #ifdef SELECT_CC_MODE
2873 enum machine_mode compare_mode;
2876 newpat = PATTERN (i3);
2877 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
2881 #ifdef SELECT_CC_MODE
2882 /* See if a COMPARE with the operand we substituted in should be done
2883 with the mode that is currently being used. If not, do the same
2884 processing we do in `subst' for a SET; namely, if the destination
2885 is used only once, try to replace it with a register of the proper
2886 mode and also replace the COMPARE. */
2887 if (undobuf.other_insn == 0
2888 && (cc_use = find_single_use (SET_DEST (newpat), i3,
2889 &undobuf.other_insn))
2890 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
2892 != GET_MODE (SET_DEST (newpat))))
2894 if (can_change_dest_mode(SET_DEST (newpat), added_sets_2,
2897 unsigned int regno = REGNO (SET_DEST (newpat));
2900 if (regno < FIRST_PSEUDO_REGISTER)
2901 new_dest = gen_rtx_REG (compare_mode, regno);
2904 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
2905 new_dest = regno_reg_rtx[regno];
2908 SUBST (SET_DEST (newpat), new_dest);
2909 SUBST (XEXP (*cc_use, 0), new_dest);
2910 SUBST (SET_SRC (newpat),
2911 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
2914 undobuf.other_insn = 0;
2921 /* It is possible that the source of I2 or I1 may be performing
2922 an unneeded operation, such as a ZERO_EXTEND of something
2923 that is known to have the high part zero. Handle that case
2924 by letting subst look at the innermost one of them.
2926 Another way to do this would be to have a function that tries
2927 to simplify a single insn instead of merging two or more
2928 insns. We don't do this because of the potential of infinite
2929 loops and because of the potential extra memory required.
2930 However, doing it the way we are is a bit of a kludge and
2931 doesn't catch all cases.
2933 But only do this if -fexpensive-optimizations since it slows
2934 things down and doesn't usually win.
2936 This is not done in the COMPARE case above because the
2937 unmodified I2PAT is used in the PARALLEL and so a pattern
2938 with a modified I2SRC would not match. */
2940 if (flag_expensive_optimizations)
2942 /* Pass pc_rtx so no substitutions are done, just
2946 subst_low_luid = DF_INSN_LUID (i1);
2947 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
2951 subst_low_luid = DF_INSN_LUID (i2);
2952 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
2956 n_occurrences = 0; /* `subst' counts here */
2958 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2959 need to make a unique copy of I2SRC each time we substitute it
2960 to avoid self-referential rtl. */
2962 subst_low_luid = DF_INSN_LUID (i2);
2963 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
2964 ! i1_feeds_i3 && i1dest_in_i1src);
2967 /* Record whether i2's body now appears within i3's body. */
2968 i2_is_used = n_occurrences;
2971 /* If we already got a failure, don't try to do more. Otherwise,
2972 try to substitute in I1 if we have it. */
2974 if (i1 && GET_CODE (newpat) != CLOBBER)
2976 /* Check that an autoincrement side-effect on I1 has not been lost.
2977 This happens if I1DEST is mentioned in I2 and dies there, and
2978 has disappeared from the new pattern. */
2979 if ((FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2981 && dead_or_set_p (i2, i1dest)
2982 && !reg_overlap_mentioned_p (i1dest, newpat))
2983 /* Before we can do this substitution, we must redo the test done
2984 above (see detailed comments there) that ensures that I1DEST
2985 isn't mentioned in any SETs in NEWPAT that are field assignments. */
2986 || !combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX, 0, 0))
2993 subst_low_luid = DF_INSN_LUID (i1);
2994 newpat = subst (newpat, i1dest, i1src, 0, 0);
2998 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2999 to count all the ways that I2SRC and I1SRC can be used. */
3000 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
3001 && i2_is_used + added_sets_2 > 1)
3002 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3003 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
3005 /* Fail if we tried to make a new register. */
3006 || max_reg_num () != maxreg
3007 /* Fail if we couldn't do something and have a CLOBBER. */
3008 || GET_CODE (newpat) == CLOBBER
3009 /* Fail if this new pattern is a MULT and we didn't have one before
3010 at the outer level. */
3011 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
3018 /* If the actions of the earlier insns must be kept
3019 in addition to substituting them into the latest one,
3020 we must make a new PARALLEL for the latest insn
3021 to hold additional the SETs. */
3023 if (added_sets_1 || added_sets_2)
3027 if (GET_CODE (newpat) == PARALLEL)
3029 rtvec old = XVEC (newpat, 0);
3030 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
3031 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3032 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
3033 sizeof (old->elem[0]) * old->num_elem);
3038 total_sets = 1 + added_sets_1 + added_sets_2;
3039 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3040 XVECEXP (newpat, 0, 0) = old;
3044 XVECEXP (newpat, 0, --total_sets) = i1pat;
3048 /* If there is no I1, use I2's body as is. We used to also not do
3049 the subst call below if I2 was substituted into I3,
3050 but that could lose a simplification. */
3052 XVECEXP (newpat, 0, --total_sets) = i2pat;
3054 /* See comment where i2pat is assigned. */
3055 XVECEXP (newpat, 0, --total_sets)
3056 = subst (i2pat, i1dest, i1src, 0, 0);
3060 /* We come here when we are replacing a destination in I2 with the
3061 destination of I3. */
3062 validate_replacement:
3064 /* Note which hard regs this insn has as inputs. */
3065 mark_used_regs_combine (newpat);
3067 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3068 consider splitting this pattern, we might need these clobbers. */
3069 if (i1 && GET_CODE (newpat) == PARALLEL
3070 && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
3072 int len = XVECLEN (newpat, 0);
3074 newpat_vec_with_clobbers = rtvec_alloc (len);
3075 for (i = 0; i < len; i++)
3076 RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
3079 /* Is the result of combination a valid instruction? */
3080 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3082 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
3083 the second SET's destination is a register that is unused and isn't
3084 marked as an instruction that might trap in an EH region. In that case,
3085 we just need the first SET. This can occur when simplifying a divmod
3086 insn. We *must* test for this case here because the code below that
3087 splits two independent SETs doesn't handle this case correctly when it
3088 updates the register status.
3090 It's pointless doing this if we originally had two sets, one from
3091 i3, and one from i2. Combining then splitting the parallel results
3092 in the original i2 again plus an invalid insn (which we delete).
3093 The net effect is only to move instructions around, which makes
3094 debug info less accurate.
3096 Also check the case where the first SET's destination is unused.
3097 That would not cause incorrect code, but does cause an unneeded
3100 if (insn_code_number < 0
3101 && !(added_sets_2 && i1 == 0)
3102 && GET_CODE (newpat) == PARALLEL
3103 && XVECLEN (newpat, 0) == 2
3104 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3105 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3106 && asm_noperands (newpat) < 0)
3108 rtx set0 = XVECEXP (newpat, 0, 0);
3109 rtx set1 = XVECEXP (newpat, 0, 1);
3111 if (((REG_P (SET_DEST (set1))
3112 && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
3113 || (GET_CODE (SET_DEST (set1)) == SUBREG
3114 && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
3115 && insn_nothrow_p (i3)
3116 && !side_effects_p (SET_SRC (set1)))
3119 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3122 else if (((REG_P (SET_DEST (set0))
3123 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
3124 || (GET_CODE (SET_DEST (set0)) == SUBREG
3125 && find_reg_note (i3, REG_UNUSED,
3126 SUBREG_REG (SET_DEST (set0)))))
3127 && insn_nothrow_p (i3)
3128 && !side_effects_p (SET_SRC (set0)))
3131 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3133 if (insn_code_number >= 0)
3134 changed_i3_dest = 1;
3138 /* If we were combining three insns and the result is a simple SET
3139 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3140 insns. There are two ways to do this. It can be split using a
3141 machine-specific method (like when you have an addition of a large
3142 constant) or by combine in the function find_split_point. */
3144 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
3145 && asm_noperands (newpat) < 0)
3147 rtx parallel, m_split, *split;
3149 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3150 use I2DEST as a scratch register will help. In the latter case,
3151 convert I2DEST to the mode of the source of NEWPAT if we can. */
3153 m_split = combine_split_insns (newpat, i3);
3155 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3156 inputs of NEWPAT. */
3158 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3159 possible to try that as a scratch reg. This would require adding
3160 more code to make it work though. */
3162 if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
3164 enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
3166 /* First try to split using the original register as a
3167 scratch register. */
3168 parallel = gen_rtx_PARALLEL (VOIDmode,
3169 gen_rtvec (2, newpat,
3170 gen_rtx_CLOBBER (VOIDmode,
3172 m_split = combine_split_insns (parallel, i3);
3174 /* If that didn't work, try changing the mode of I2DEST if
3177 && new_mode != GET_MODE (i2dest)
3178 && new_mode != VOIDmode
3179 && can_change_dest_mode (i2dest, added_sets_2, new_mode))
3181 enum machine_mode old_mode = GET_MODE (i2dest);
3184 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3185 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
3188 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
3189 ni2dest = regno_reg_rtx[REGNO (i2dest)];
3192 parallel = (gen_rtx_PARALLEL
3194 gen_rtvec (2, newpat,
3195 gen_rtx_CLOBBER (VOIDmode,
3197 m_split = combine_split_insns (parallel, i3);
3200 && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
3204 adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode);
3205 buf = undobuf.undos;
3206 undobuf.undos = buf->next;
3207 buf->next = undobuf.frees;
3208 undobuf.frees = buf;
3212 i2scratch = m_split != 0;
3215 /* If recog_for_combine has discarded clobbers, try to use them
3216 again for the split. */
3217 if (m_split == 0 && newpat_vec_with_clobbers)
3219 parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers);
3220 m_split = combine_split_insns (parallel, i3);
3223 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
3225 m_split = PATTERN (m_split);
3226 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
3227 if (insn_code_number >= 0)
3230 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
3231 && (next_real_insn (i2) == i3
3232 || ! use_crosses_set_p (PATTERN (m_split), DF_INSN_LUID (i2))))
3235 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
3236 newi2pat = PATTERN (m_split);
3238 i3set = single_set (NEXT_INSN (m_split));
3239 i2set = single_set (m_split);
3241 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3243 /* If I2 or I3 has multiple SETs, we won't know how to track
3244 register status, so don't use these insns. If I2's destination
3245 is used between I2 and I3, we also can't use these insns. */
3247 if (i2_code_number >= 0 && i2set && i3set
3248 && (next_real_insn (i2) == i3
3249 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
3250 insn_code_number = recog_for_combine (&newi3pat, i3,
3252 if (insn_code_number >= 0)
3255 /* It is possible that both insns now set the destination of I3.
3256 If so, we must show an extra use of it. */
3258 if (insn_code_number >= 0)
3260 rtx new_i3_dest = SET_DEST (i3set);
3261 rtx new_i2_dest = SET_DEST (i2set);
3263 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
3264 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
3265 || GET_CODE (new_i3_dest) == SUBREG)
3266 new_i3_dest = XEXP (new_i3_dest, 0);
3268 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
3269 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
3270 || GET_CODE (new_i2_dest) == SUBREG)
3271 new_i2_dest = XEXP (new_i2_dest, 0);
3273 if (REG_P (new_i3_dest)
3274 && REG_P (new_i2_dest)
3275 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
3276 INC_REG_N_SETS (REGNO (new_i2_dest), 1);
3280 /* If we can split it and use I2DEST, go ahead and see if that
3281 helps things be recognized. Verify that none of the registers
3282 are set between I2 and I3. */
3283 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
3287 /* We need I2DEST in the proper mode. If it is a hard register
3288 or the only use of a pseudo, we can change its mode.
3289 Make sure we don't change a hard register to have a mode that
3290 isn't valid for it, or change the number of registers. */
3291 && (GET_MODE (*split) == GET_MODE (i2dest)
3292 || GET_MODE (*split) == VOIDmode
3293 || can_change_dest_mode (i2dest, added_sets_2,
3295 && (next_real_insn (i2) == i3
3296 || ! use_crosses_set_p (*split, DF_INSN_LUID (i2)))
3297 /* We can't overwrite I2DEST if its value is still used by
3299 && ! reg_referenced_p (i2dest, newpat))
3301 rtx newdest = i2dest;
3302 enum rtx_code split_code = GET_CODE (*split);
3303 enum machine_mode split_mode = GET_MODE (*split);
3304 bool subst_done = false;
3305 newi2pat = NULL_RTX;
3309 /* Get NEWDEST as a register in the proper mode. We have already
3310 validated that we can do this. */
3311 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
3313 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3314 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
3317 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
3318 newdest = regno_reg_rtx[REGNO (i2dest)];
3322 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3323 an ASHIFT. This can occur if it was inside a PLUS and hence
3324 appeared to be a memory address. This is a kludge. */
3325 if (split_code == MULT
3326 && CONST_INT_P (XEXP (*split, 1))
3327 && INTVAL (XEXP (*split, 1)) > 0
3328 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
3330 SUBST (*split, gen_rtx_ASHIFT (split_mode,
3331 XEXP (*split, 0), GEN_INT (i)));
3332 /* Update split_code because we may not have a multiply
3334 split_code = GET_CODE (*split);
3337 #ifdef INSN_SCHEDULING
3338 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3339 be written as a ZERO_EXTEND. */
3340 if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
3342 #ifdef LOAD_EXTEND_OP
3343 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3344 what it really is. */
3345 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
3347 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
3348 SUBREG_REG (*split)));
3351 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
3352 SUBREG_REG (*split)));
3356 /* Attempt to split binary operators using arithmetic identities. */
3357 if (BINARY_P (SET_SRC (newpat))
3358 && split_mode == GET_MODE (SET_SRC (newpat))
3359 && ! side_effects_p (SET_SRC (newpat)))
3361 rtx setsrc = SET_SRC (newpat);
3362 enum machine_mode mode = GET_MODE (setsrc);
3363 enum rtx_code code = GET_CODE (setsrc);
3364 rtx src_op0 = XEXP (setsrc, 0);
3365 rtx src_op1 = XEXP (setsrc, 1);
3367 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3368 if (rtx_equal_p (src_op0, src_op1))
3370 newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
3371 SUBST (XEXP (setsrc, 0), newdest);
3372 SUBST (XEXP (setsrc, 1), newdest);
3375 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3376 else if ((code == PLUS || code == MULT)
3377 && GET_CODE (src_op0) == code
3378 && GET_CODE (XEXP (src_op0, 0)) == code
3379 && (INTEGRAL_MODE_P (mode)
3380 || (FLOAT_MODE_P (mode)
3381 && flag_unsafe_math_optimizations)))
3383 rtx p = XEXP (XEXP (src_op0, 0), 0);
3384 rtx q = XEXP (XEXP (src_op0, 0), 1);
3385 rtx r = XEXP (src_op0, 1);
3388 /* Split both "((X op Y) op X) op Y" and
3389 "((X op Y) op Y) op X" as "T op T" where T is
3391 if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
3392 || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
3394 newi2pat = gen_rtx_SET (VOIDmode, newdest,
3396 SUBST (XEXP (setsrc, 0), newdest);
3397 SUBST (XEXP (setsrc, 1), newdest);
3400 /* Split "((X op X) op Y) op Y)" as "T op T" where
3402 else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
3404 rtx tmp = simplify_gen_binary (code, mode, p, r);
3405 newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
3406 SUBST (XEXP (setsrc, 0), newdest);
3407 SUBST (XEXP (setsrc, 1), newdest);
3415 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
3416 SUBST (*split, newdest);
3419 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3421 /* recog_for_combine might have added CLOBBERs to newi2pat.
3422 Make sure NEWPAT does not depend on the clobbered regs. */
3423 if (GET_CODE (newi2pat) == PARALLEL)
3424 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3425 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3427 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3428 if (reg_overlap_mentioned_p (reg, newpat))
3435 /* If the split point was a MULT and we didn't have one before,
3436 don't use one now. */
3437 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
3438 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3442 /* Check for a case where we loaded from memory in a narrow mode and
3443 then sign extended it, but we need both registers. In that case,
3444 we have a PARALLEL with both loads from the same memory location.
3445 We can split this into a load from memory followed by a register-register
3446 copy. This saves at least one insn, more if register allocation can
3449 We cannot do this if the destination of the first assignment is a
3450 condition code register or cc0. We eliminate this case by making sure
3451 the SET_DEST and SET_SRC have the same mode.
3453 We cannot do this if the destination of the second assignment is
3454 a register that we have already assumed is zero-extended. Similarly
3455 for a SUBREG of such a register. */
3457 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3458 && GET_CODE (newpat) == PARALLEL
3459 && XVECLEN (newpat, 0) == 2
3460 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3461 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
3462 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
3463 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
3464 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3465 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3466 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
3467 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3469 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3470 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3471 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
3473 && VEC_index (reg_stat_type, reg_stat,
3474 REGNO (temp))->nonzero_bits != 0
3475 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3476 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3477 && (VEC_index (reg_stat_type, reg_stat,
3478 REGNO (temp))->nonzero_bits
3479 != GET_MODE_MASK (word_mode))))
3480 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
3481 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
3483 && VEC_index (reg_stat_type, reg_stat,
3484 REGNO (temp))->nonzero_bits != 0
3485 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3486 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3487 && (VEC_index (reg_stat_type, reg_stat,
3488 REGNO (temp))->nonzero_bits
3489 != GET_MODE_MASK (word_mode)))))
3490 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3491 SET_SRC (XVECEXP (newpat, 0, 1)))
3492 && ! find_reg_note (i3, REG_UNUSED,
3493 SET_DEST (XVECEXP (newpat, 0, 0))))
3497 newi2pat = XVECEXP (newpat, 0, 0);
3498 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
3499 newpat = XVECEXP (newpat, 0, 1);
3500 SUBST (SET_SRC (newpat),
3501 gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
3502 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3504 if (i2_code_number >= 0)
3505 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3507 if (insn_code_number >= 0)
3511 /* Similarly, check for a case where we have a PARALLEL of two independent
3512 SETs but we started with three insns. In this case, we can do the sets
3513 as two separate insns. This case occurs when some SET allows two
3514 other insns to combine, but the destination of that SET is still live. */
3516 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3517 && GET_CODE (newpat) == PARALLEL
3518 && XVECLEN (newpat, 0) == 2
3519 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3520 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
3521 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
3522 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3523 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3524 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3525 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3527 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3528 XVECEXP (newpat, 0, 0))
3529 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
3530 XVECEXP (newpat, 0, 1))
3531 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
3532 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1))))
3534 /* We cannot split the parallel into two sets if both sets
3536 && ! (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0))
3537 && reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 1)))
3541 /* Normally, it doesn't matter which of the two is done first,
3542 but it does if one references cc0. In that case, it has to
3545 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
3547 newi2pat = XVECEXP (newpat, 0, 0);
3548 newpat = XVECEXP (newpat, 0, 1);
3553 newi2pat = XVECEXP (newpat, 0, 1);
3554 newpat = XVECEXP (newpat, 0, 0);
3557 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3559 if (i2_code_number >= 0)
3560 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3563 /* If it still isn't recognized, fail and change things back the way they
3565 if ((insn_code_number < 0
3566 /* Is the result a reasonable ASM_OPERANDS? */
3567 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
3573 /* If we had to change another insn, make sure it is valid also. */
3574 if (undobuf.other_insn)
3576 CLEAR_HARD_REG_SET (newpat_used_regs);
3578 other_pat = PATTERN (undobuf.other_insn);
3579 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
3582 if (other_code_number < 0 && ! check_asm_operands (other_pat))
3590 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3591 they are adjacent to each other or not. */
3593 rtx p = prev_nonnote_insn (i3);
3594 if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
3595 && sets_cc0_p (newi2pat))
3603 /* Only allow this combination if insn_rtx_costs reports that the
3604 replacement instructions are cheaper than the originals. */
3605 if (!combine_validate_cost (i1, i2, i3, newpat, newi2pat, other_pat))
3611 if (MAY_HAVE_DEBUG_INSNS)
3615 for (undo = undobuf.undos; undo; undo = undo->next)
3616 if (undo->kind == UNDO_MODE)
3618 rtx reg = *undo->where.r;
3619 enum machine_mode new_mode = GET_MODE (reg);
3620 enum machine_mode old_mode = undo->old_contents.m;
3622 /* Temporarily revert mode back. */
3623 adjust_reg_mode (reg, old_mode);
3625 if (reg == i2dest && i2scratch)
3627 /* If we used i2dest as a scratch register with a
3628 different mode, substitute it for the original
3629 i2src while its original mode is temporarily
3630 restored, and then clear i2scratch so that we don't
3631 do it again later. */
3632 propagate_for_debug (i2, i3, reg, i2src, false);
3634 /* Put back the new mode. */
3635 adjust_reg_mode (reg, new_mode);
3639 rtx tempreg = gen_raw_REG (old_mode, REGNO (reg));
3650 last = undobuf.other_insn;
3654 /* We're dealing with a reg that changed mode but not
3655 meaning, so we want to turn it into a subreg for
3656 the new mode. However, because of REG sharing and
3657 because its mode had already changed, we have to do
3658 it in two steps. First, replace any debug uses of
3659 reg, with its original mode temporarily restored,
3660 with this copy we have created; then, replace the
3661 copy with the SUBREG of the original shared reg,
3662 once again changed to the new mode. */
3663 propagate_for_debug (first, last, reg, tempreg, false);
3664 adjust_reg_mode (reg, new_mode);
3665 propagate_for_debug (first, last, tempreg,
3666 lowpart_subreg (old_mode, reg, new_mode),
3672 /* If we will be able to accept this, we have made a
3673 change to the destination of I3. This requires us to
3674 do a few adjustments. */
3676 if (changed_i3_dest)
3678 PATTERN (i3) = newpat;
3679 adjust_for_new_dest (i3);
3682 /* We now know that we can do this combination. Merge the insns and
3683 update the status of registers and LOG_LINKS. */
3685 if (undobuf.other_insn)
3689 PATTERN (undobuf.other_insn) = other_pat;
3691 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
3692 are still valid. Then add any non-duplicate notes added by
3693 recog_for_combine. */
3694 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
3696 next = XEXP (note, 1);
3698 if (REG_NOTE_KIND (note) == REG_UNUSED
3699 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
3700 remove_note (undobuf.other_insn, note);
3703 distribute_notes (new_other_notes, undobuf.other_insn,
3704 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
3713 /* I3 now uses what used to be its destination and which is now
3714 I2's destination. This requires us to do a few adjustments. */
3715 PATTERN (i3) = newpat;
3716 adjust_for_new_dest (i3);
3718 /* We need a LOG_LINK from I3 to I2. But we used to have one,
3721 However, some later insn might be using I2's dest and have
3722 a LOG_LINK pointing at I3. We must remove this link.
3723 The simplest way to remove the link is to point it at I1,
3724 which we know will be a NOTE. */
3726 /* newi2pat is usually a SET here; however, recog_for_combine might
3727 have added some clobbers. */
3728 if (GET_CODE (newi2pat) == PARALLEL)
3729 ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
3731 ni2dest = SET_DEST (newi2pat);
3733 for (insn = NEXT_INSN (i3);
3734 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3735 || insn != BB_HEAD (this_basic_block->next_bb));
3736 insn = NEXT_INSN (insn))
3738 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
3740 for (link = LOG_LINKS (insn); link;
3741 link = XEXP (link, 1))
3742 if (XEXP (link, 0) == i3)
3743 XEXP (link, 0) = i1;
3751 rtx i3notes, i2notes, i1notes = 0;
3752 rtx i3links, i2links, i1links = 0;
3755 /* Compute which registers we expect to eliminate. newi2pat may be setting
3756 either i3dest or i2dest, so we must check it. Also, i1dest may be the
3757 same as i3dest, in which case newi2pat may be setting i1dest. */
3758 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
3759 || i2dest_in_i2src || i2dest_in_i1src
3762 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
3763 || (newi2pat && reg_set_p (i1dest, newi2pat))
3767 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3769 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
3770 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
3772 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
3774 /* Ensure that we do not have something that should not be shared but
3775 occurs multiple times in the new insns. Check this by first
3776 resetting all the `used' flags and then copying anything is shared. */
3778 reset_used_flags (i3notes);
3779 reset_used_flags (i2notes);
3780 reset_used_flags (i1notes);
3781 reset_used_flags (newpat);
3782 reset_used_flags (newi2pat);
3783 if (undobuf.other_insn)
3784 reset_used_flags (PATTERN (undobuf.other_insn));
3786 i3notes = copy_rtx_if_shared (i3notes);
3787 i2notes = copy_rtx_if_shared (i2notes);
3788 i1notes = copy_rtx_if_shared (i1notes);
3789 newpat = copy_rtx_if_shared (newpat);
3790 newi2pat = copy_rtx_if_shared (newi2pat);
3791 if (undobuf.other_insn)
3792 reset_used_flags (PATTERN (undobuf.other_insn));
3794 INSN_CODE (i3) = insn_code_number;
3795 PATTERN (i3) = newpat;
3797 if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
3799 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
3801 reset_used_flags (call_usage);
3802 call_usage = copy_rtx (call_usage);
3805 replace_rtx (call_usage, i2dest, i2src);
3808 replace_rtx (call_usage, i1dest, i1src);
3810 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
3813 if (undobuf.other_insn)
3814 INSN_CODE (undobuf.other_insn) = other_code_number;
3816 /* We had one special case above where I2 had more than one set and
3817 we replaced a destination of one of those sets with the destination
3818 of I3. In that case, we have to update LOG_LINKS of insns later
3819 in this basic block. Note that this (expensive) case is rare.
3821 Also, in this case, we must pretend that all REG_NOTEs for I2
3822 actually came from I3, so that REG_UNUSED notes from I2 will be
3823 properly handled. */
3825 if (i3_subst_into_i2)
3827 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
3828 if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
3829 || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
3830 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
3831 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
3832 && ! find_reg_note (i2, REG_UNUSED,
3833 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
3834 for (temp = NEXT_INSN (i2);
3835 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3836 || BB_HEAD (this_basic_block) != temp);
3837 temp = NEXT_INSN (temp))
3838 if (temp != i3 && INSN_P (temp))
3839 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
3840 if (XEXP (link, 0) == i2)
3841 XEXP (link, 0) = i3;
3846 while (XEXP (link, 1))
3847 link = XEXP (link, 1);
3848 XEXP (link, 1) = i2notes;
3862 if (MAY_HAVE_DEBUG_INSNS && i2scratch)
3863 propagate_for_debug (i2, i3, i2dest, i2src, false);
3864 INSN_CODE (i2) = i2_code_number;
3865 PATTERN (i2) = newi2pat;
3869 if (MAY_HAVE_DEBUG_INSNS && i2src)
3870 propagate_for_debug (i2, i3, i2dest, i2src, i3_subst_into_i2);
3871 SET_INSN_DELETED (i2);
3878 if (MAY_HAVE_DEBUG_INSNS)
3879 propagate_for_debug (i1, i3, i1dest, i1src, false);
3880 SET_INSN_DELETED (i1);
3883 /* Get death notes for everything that is now used in either I3 or
3884 I2 and used to die in a previous insn. If we built two new
3885 patterns, move from I1 to I2 then I2 to I3 so that we get the
3886 proper movement on registers that I2 modifies. */
3890 move_deaths (newi2pat, NULL_RTX, DF_INSN_LUID (i1), i2, &midnotes);
3891 move_deaths (newpat, newi2pat, DF_INSN_LUID (i1), i3, &midnotes);
3894 move_deaths (newpat, NULL_RTX, i1 ? DF_INSN_LUID (i1) : DF_INSN_LUID (i2),
3897 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
3899 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
3902 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
3905 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
3908 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3911 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
3912 know these are REG_UNUSED and want them to go to the desired insn,
3913 so we always pass it as i3. */
3915 if (newi2pat && new_i2_notes)
3916 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3919 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
3921 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
3922 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
3923 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
3924 in that case, it might delete I2. Similarly for I2 and I1.
3925 Show an additional death due to the REG_DEAD note we make here. If
3926 we discard it in distribute_notes, we will decrement it again. */
3930 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
3931 distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
3933 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
3935 distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
3937 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3941 if (i2dest_in_i2src)
3943 if (newi2pat && reg_set_p (i2dest, newi2pat))
3944 distribute_notes (alloc_reg_note (REG_DEAD, i2dest, NULL_RTX),
3945 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3947 distribute_notes (alloc_reg_note (REG_DEAD, i2dest, NULL_RTX),
3948 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3949 NULL_RTX, NULL_RTX);
3952 if (i1dest_in_i1src)
3954 if (newi2pat && reg_set_p (i1dest, newi2pat))
3955 distribute_notes (alloc_reg_note (REG_DEAD, i1dest, NULL_RTX),
3956 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3958 distribute_notes (alloc_reg_note (REG_DEAD, i1dest, NULL_RTX),
3959 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3960 NULL_RTX, NULL_RTX);
3963 distribute_links (i3links);
3964 distribute_links (i2links);
3965 distribute_links (i1links);
3970 rtx i2_insn = 0, i2_val = 0, set;
3972 /* The insn that used to set this register doesn't exist, and
3973 this life of the register may not exist either. See if one of
3974 I3's links points to an insn that sets I2DEST. If it does,
3975 that is now the last known value for I2DEST. If we don't update
3976 this and I2 set the register to a value that depended on its old
3977 contents, we will get confused. If this insn is used, thing
3978 will be set correctly in combine_instructions. */
3980 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3981 if ((set = single_set (XEXP (link, 0))) != 0
3982 && rtx_equal_p (i2dest, SET_DEST (set)))
3983 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
3985 record_value_for_reg (i2dest, i2_insn, i2_val);
3987 /* If the reg formerly set in I2 died only once and that was in I3,
3988 zero its use count so it won't make `reload' do any work. */
3990 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
3991 && ! i2dest_in_i2src)
3993 regno = REGNO (i2dest);
3994 INC_REG_N_SETS (regno, -1);
3998 if (i1 && REG_P (i1dest))
4001 rtx i1_insn = 0, i1_val = 0, set;
4003 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
4004 if ((set = single_set (XEXP (link, 0))) != 0
4005 && rtx_equal_p (i1dest, SET_DEST (set)))
4006 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
4008 record_value_for_reg (i1dest, i1_insn, i1_val);
4010 regno = REGNO (i1dest);
4011 if (! added_sets_1 && ! i1dest_in_i1src)
4012 INC_REG_N_SETS (regno, -1);
4015 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4016 been made to this insn. The order of
4017 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
4018 can affect nonzero_bits of newpat */
4020 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
4021 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
4024 if (undobuf.other_insn != NULL_RTX)
4028 fprintf (dump_file, "modifying other_insn ");
4029 dump_insn_slim (dump_file, undobuf.other_insn);
4031 df_insn_rescan (undobuf.other_insn);
4034 if (i1 && !(NOTE_P(i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED)))
4038 fprintf (dump_file, "modifying insn i1 ");
4039 dump_insn_slim (dump_file, i1);
4041 df_insn_rescan (i1);
4044 if (i2 && !(NOTE_P(i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED)))
4048 fprintf (dump_file, "modifying insn i2 ");
4049 dump_insn_slim (dump_file, i2);
4051 df_insn_rescan (i2);
4054 if (i3 && !(NOTE_P(i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED)))
4058 fprintf (dump_file, "modifying insn i3 ");
4059 dump_insn_slim (dump_file, i3);
4061 df_insn_rescan (i3);
4064 /* Set new_direct_jump_p if a new return or simple jump instruction
4065 has been created. Adjust the CFG accordingly. */
4067 if (returnjump_p (i3) || any_uncondjump_p (i3))
4069 *new_direct_jump_p = 1;
4070 mark_jump_label (PATTERN (i3), i3, 0);
4071 update_cfg_for_uncondjump (i3);
4074 if (undobuf.other_insn != NULL_RTX
4075 && (returnjump_p (undobuf.other_insn)
4076 || any_uncondjump_p (undobuf.other_insn)))
4078 *new_direct_jump_p = 1;
4079 update_cfg_for_uncondjump (undobuf.other_insn);
4082 /* A noop might also need cleaning up of CFG, if it comes from the
4083 simplification of a jump. */
4084 if (GET_CODE (newpat) == SET
4085 && SET_SRC (newpat) == pc_rtx
4086 && SET_DEST (newpat) == pc_rtx)
4088 *new_direct_jump_p = 1;
4089 update_cfg_for_uncondjump (i3);
4092 combine_successes++;
4095 if (added_links_insn
4096 && (newi2pat == 0 || DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i2))
4097 && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i3))
4098 return added_links_insn;
4100 return newi2pat ? i2 : i3;
4103 /* Undo all the modifications recorded in undobuf. */
4108 struct undo *undo, *next;
4110 for (undo = undobuf.undos; undo; undo = next)
4116 *undo->where.r = undo->old_contents.r;
4119 *undo->where.i = undo->old_contents.i;
4122 adjust_reg_mode (*undo->where.r, undo->old_contents.m);
4128 undo->next = undobuf.frees;
4129 undobuf.frees = undo;
4135 /* We've committed to accepting the changes we made. Move all
4136 of the undos to the free list. */
4141 struct undo *undo, *next;
4143 for (undo = undobuf.undos; undo; undo = next)
4146 undo->next = undobuf.frees;
4147 undobuf.frees = undo;
4152 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4153 where we have an arithmetic expression and return that point. LOC will
4156 try_combine will call this function to see if an insn can be split into
4160 find_split_point (rtx *loc, rtx insn)
4163 enum rtx_code code = GET_CODE (x);
4165 unsigned HOST_WIDE_INT len = 0;
4166 HOST_WIDE_INT pos = 0;
4168 rtx inner = NULL_RTX;
4170 /* First special-case some codes. */
4174 #ifdef INSN_SCHEDULING
4175 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4177 if (MEM_P (SUBREG_REG (x)))
4180 return find_split_point (&SUBREG_REG (x), insn);
4184 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4185 using LO_SUM and HIGH. */
4186 if (GET_CODE (XEXP (x, 0)) == CONST
4187 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
4190 gen_rtx_LO_SUM (Pmode,
4191 gen_rtx_HIGH (Pmode, XEXP (x, 0)),
4193 return &XEXP (XEXP (x, 0), 0);
4197 /* If we have a PLUS whose second operand is a constant and the
4198 address is not valid, perhaps will can split it up using
4199 the machine-specific way to split large constants. We use
4200 the first pseudo-reg (one of the virtual regs) as a placeholder;
4201 it will not remain in the result. */
4202 if (GET_CODE (XEXP (x, 0)) == PLUS
4203 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
4204 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
4206 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
4207 rtx seq = combine_split_insns (gen_rtx_SET (VOIDmode, reg,
4211 /* This should have produced two insns, each of which sets our
4212 placeholder. If the source of the second is a valid address,
4213 we can make put both sources together and make a split point
4217 && NEXT_INSN (seq) != NULL_RTX
4218 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
4219 && NONJUMP_INSN_P (seq)
4220 && GET_CODE (PATTERN (seq)) == SET
4221 && SET_DEST (PATTERN (seq)) == reg
4222 && ! reg_mentioned_p (reg,
4223 SET_SRC (PATTERN (seq)))
4224 && NONJUMP_INSN_P (NEXT_INSN (seq))
4225 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
4226 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
4227 && memory_address_p (GET_MODE (x),
4228 SET_SRC (PATTERN (NEXT_INSN (seq)))))
4230 rtx src1 = SET_SRC (PATTERN (seq));
4231 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
4233 /* Replace the placeholder in SRC2 with SRC1. If we can
4234 find where in SRC2 it was placed, that can become our
4235 split point and we can replace this address with SRC2.
4236 Just try two obvious places. */
4238 src2 = replace_rtx (src2, reg, src1);
4240 if (XEXP (src2, 0) == src1)
4241 split = &XEXP (src2, 0);
4242 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
4243 && XEXP (XEXP (src2, 0), 0) == src1)
4244 split = &XEXP (XEXP (src2, 0), 0);
4248 SUBST (XEXP (x, 0), src2);
4253 /* If that didn't work, perhaps the first operand is complex and
4254 needs to be computed separately, so make a split point there.
4255 This will occur on machines that just support REG + CONST
4256 and have a constant moved through some previous computation. */
4258 else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
4259 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4260 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4261 return &XEXP (XEXP (x, 0), 0);
4264 /* If we have a PLUS whose first operand is complex, try computing it
4265 separately by making a split there. */
4266 if (GET_CODE (XEXP (x, 0)) == PLUS
4267 && ! memory_address_p (GET_MODE (x), XEXP (x, 0))
4268 && ! OBJECT_P (XEXP (XEXP (x, 0), 0))
4269 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4270 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4271 return &XEXP (XEXP (x, 0), 0);
4276 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4277 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4278 we need to put the operand into a register. So split at that
4281 if (SET_DEST (x) == cc0_rtx
4282 && GET_CODE (SET_SRC (x)) != COMPARE
4283 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
4284 && !OBJECT_P (SET_SRC (x))
4285 && ! (GET_CODE (SET_SRC (x)) == SUBREG
4286 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
4287 return &SET_SRC (x);
4290 /* See if we can split SET_SRC as it stands. */
4291 split = find_split_point (&SET_SRC (x), insn);
4292 if (split && split != &SET_SRC (x))
4295 /* See if we can split SET_DEST as it stands. */
4296 split = find_split_point (&SET_DEST (x), insn);
4297 if (split && split != &SET_DEST (x))
4300 /* See if this is a bitfield assignment with everything constant. If
4301 so, this is an IOR of an AND, so split it into that. */
4302 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
4303 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
4304 <= HOST_BITS_PER_WIDE_INT)
4305 && CONST_INT_P (XEXP (SET_DEST (x), 1))
4306 && CONST_INT_P (XEXP (SET_DEST (x), 2))
4307 && CONST_INT_P (SET_SRC (x))
4308 && ((INTVAL (XEXP (SET_DEST (x), 1))
4309 + INTVAL (XEXP (SET_DEST (x), 2)))
4310 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
4311 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
4313 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
4314 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
4315 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
4316 rtx dest = XEXP (SET_DEST (x), 0);
4317 enum machine_mode mode = GET_MODE (dest);
4318 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
4321 if (BITS_BIG_ENDIAN)
4322 pos = GET_MODE_BITSIZE (mode) - len - pos;
4324 or_mask = gen_int_mode (src << pos, mode);
4327 simplify_gen_binary (IOR, mode, dest, or_mask));
4330 rtx negmask = gen_int_mode (~(mask << pos), mode);
4332 simplify_gen_binary (IOR, mode,
4333 simplify_gen_binary (AND, mode,
4338 SUBST (SET_DEST (x), dest);
4340 split = find_split_point (&SET_SRC (x), insn);
4341 if (split && split != &SET_SRC (x))
4345 /* Otherwise, see if this is an operation that we can split into two.
4346 If so, try to split that. */
4347 code = GET_CODE (SET_SRC (x));
4352 /* If we are AND'ing with a large constant that is only a single
4353 bit and the result is only being used in a context where we
4354 need to know if it is zero or nonzero, replace it with a bit
4355 extraction. This will avoid the large constant, which might
4356 have taken more than one insn to make. If the constant were
4357 not a valid argument to the AND but took only one insn to make,
4358 this is no worse, but if it took more than one insn, it will
4361 if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4362 && REG_P (XEXP (SET_SRC (x), 0))
4363 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
4364 && REG_P (SET_DEST (x))
4365 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
4366 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
4367 && XEXP (*split, 0) == SET_DEST (x)
4368 && XEXP (*split, 1) == const0_rtx)
4370 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
4371 XEXP (SET_SRC (x), 0),
4372 pos, NULL_RTX, 1, 1, 0, 0);
4373 if (extraction != 0)
4375 SUBST (SET_SRC (x), extraction);
4376 return find_split_point (loc, insn);
4382 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4383 is known to be on, this can be converted into a NEG of a shift. */
4384 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
4385 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
4386 && 1 <= (pos = exact_log2
4387 (nonzero_bits (XEXP (SET_SRC (x), 0),
4388 GET_MODE (XEXP (SET_SRC (x), 0))))))
4390 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
4394 gen_rtx_LSHIFTRT (mode,
4395 XEXP (SET_SRC (x), 0),
4398 split = find_split_point (&SET_SRC (x), insn);
4399 if (split && split != &SET_SRC (x))
4405 inner = XEXP (SET_SRC (x), 0);
4407 /* We can't optimize if either mode is a partial integer
4408 mode as we don't know how many bits are significant
4410 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
4411 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
4415 len = GET_MODE_BITSIZE (GET_MODE (inner));
4421 if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4422 && CONST_INT_P (XEXP (SET_SRC (x), 2)))
4424 inner = XEXP (SET_SRC (x), 0);
4425 len = INTVAL (XEXP (SET_SRC (x), 1));
4426 pos = INTVAL (XEXP (SET_SRC (x), 2));
4428 if (BITS_BIG_ENDIAN)
4429 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
4430 unsignedp = (code == ZERO_EXTRACT);
4438 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
4440 enum machine_mode mode = GET_MODE (SET_SRC (x));
4442 /* For unsigned, we have a choice of a shift followed by an
4443 AND or two shifts. Use two shifts for field sizes where the
4444 constant might be too large. We assume here that we can
4445 always at least get 8-bit constants in an AND insn, which is
4446 true for every current RISC. */
4448 if (unsignedp && len <= 8)
4453 (mode, gen_lowpart (mode, inner),
4455 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
4457 split = find_split_point (&SET_SRC (x), insn);
4458 if (split && split != &SET_SRC (x))
4465 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
4466 gen_rtx_ASHIFT (mode,
4467 gen_lowpart (mode, inner),
4468 GEN_INT (GET_MODE_BITSIZE (mode)
4470 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
4472 split = find_split_point (&SET_SRC (x), insn);
4473 if (split && split != &SET_SRC (x))
4478 /* See if this is a simple operation with a constant as the second
4479 operand. It might be that this constant is out of range and hence
4480 could be used as a split point. */
4481 if (BINARY_P (SET_SRC (x))
4482 && CONSTANT_P (XEXP (SET_SRC (x), 1))
4483 && (OBJECT_P (XEXP (SET_SRC (x), 0))
4484 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
4485 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
4486 return &XEXP (SET_SRC (x), 1);
4488 /* Finally, see if this is a simple operation with its first operand
4489 not in a register. The operation might require this operand in a
4490 register, so return it as a split point. We can always do this
4491 because if the first operand were another operation, we would have
4492 already found it as a split point. */
4493 if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
4494 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
4495 return &XEXP (SET_SRC (x), 0);
4501 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4502 it is better to write this as (not (ior A B)) so we can split it.
4503 Similarly for IOR. */
4504 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
4507 gen_rtx_NOT (GET_MODE (x),
4508 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
4510 XEXP (XEXP (x, 0), 0),
4511 XEXP (XEXP (x, 1), 0))));
4512 return find_split_point (loc, insn);
4515 /* Many RISC machines have a large set of logical insns. If the
4516 second operand is a NOT, put it first so we will try to split the
4517 other operand first. */
4518 if (GET_CODE (XEXP (x, 1)) == NOT)
4520 rtx tem = XEXP (x, 0);
4521 SUBST (XEXP (x, 0), XEXP (x, 1));
4522 SUBST (XEXP (x, 1), tem);
4530 /* Otherwise, select our actions depending on our rtx class. */
4531 switch (GET_RTX_CLASS (code))
4533 case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
4535 split = find_split_point (&XEXP (x, 2), insn);
4538 /* ... fall through ... */
4540 case RTX_COMM_ARITH:
4542 case RTX_COMM_COMPARE:
4543 split = find_split_point (&XEXP (x, 1), insn);
4546 /* ... fall through ... */
4548 /* Some machines have (and (shift ...) ...) insns. If X is not
4549 an AND, but XEXP (X, 0) is, use it as our split point. */
4550 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
4551 return &XEXP (x, 0);
4553 split = find_split_point (&XEXP (x, 0), insn);
4559 /* Otherwise, we don't have a split point. */
4564 /* Throughout X, replace FROM with TO, and return the result.
4565 The result is TO if X is FROM;
4566 otherwise the result is X, but its contents may have been modified.
4567 If they were modified, a record was made in undobuf so that
4568 undo_all will (among other things) return X to its original state.
4570 If the number of changes necessary is too much to record to undo,
4571 the excess changes are not made, so the result is invalid.
4572 The changes already made can still be undone.
4573 undobuf.num_undo is incremented for such changes, so by testing that
4574 the caller can tell whether the result is valid.
4576 `n_occurrences' is incremented each time FROM is replaced.
4578 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4580 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
4581 by copying if `n_occurrences' is nonzero. */
4584 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
4586 enum rtx_code code = GET_CODE (x);
4587 enum machine_mode op0_mode = VOIDmode;
4592 /* Two expressions are equal if they are identical copies of a shared
4593 RTX or if they are both registers with the same register number
4596 #define COMBINE_RTX_EQUAL_P(X,Y) \
4598 || (REG_P (X) && REG_P (Y) \
4599 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4601 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
4604 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
4607 /* If X and FROM are the same register but different modes, they
4608 will not have been seen as equal above. However, the log links code
4609 will make a LOG_LINKS entry for that case. If we do nothing, we
4610 will try to rerecognize our original insn and, when it succeeds,
4611 we will delete the feeding insn, which is incorrect.
4613 So force this insn not to match in this (rare) case. */
4614 if (! in_dest && code == REG && REG_P (from)
4615 && reg_overlap_mentioned_p (x, from))
4616 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
4618 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4619 of which may contain things that can be combined. */
4620 if (code != MEM && code != LO_SUM && OBJECT_P (x))
4623 /* It is possible to have a subexpression appear twice in the insn.
4624 Suppose that FROM is a register that appears within TO.
4625 Then, after that subexpression has been scanned once by `subst',
4626 the second time it is scanned, TO may be found. If we were
4627 to scan TO here, we would find FROM within it and create a
4628 self-referent rtl structure which is completely wrong. */
4629 if (COMBINE_RTX_EQUAL_P (x, to))
4632 /* Parallel asm_operands need special attention because all of the
4633 inputs are shared across the arms. Furthermore, unsharing the
4634 rtl results in recognition failures. Failure to handle this case
4635 specially can result in circular rtl.
4637 Solve this by doing a normal pass across the first entry of the
4638 parallel, and only processing the SET_DESTs of the subsequent
4641 if (code == PARALLEL
4642 && GET_CODE (XVECEXP (x, 0, 0)) == SET
4643 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
4645 new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
4647 /* If this substitution failed, this whole thing fails. */
4648 if (GET_CODE (new_rtx) == CLOBBER
4649 && XEXP (new_rtx, 0) == const0_rtx)
4652 SUBST (XVECEXP (x, 0, 0), new_rtx);
4654 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
4656 rtx dest = SET_DEST (XVECEXP (x, 0, i));
4659 && GET_CODE (dest) != CC0
4660 && GET_CODE (dest) != PC)
4662 new_rtx = subst (dest, from, to, 0, unique_copy);
4664 /* If this substitution failed, this whole thing fails. */
4665 if (GET_CODE (new_rtx) == CLOBBER
4666 && XEXP (new_rtx, 0) == const0_rtx)
4669 SUBST (SET_DEST (XVECEXP (x, 0, i)), new_rtx);
4675 len = GET_RTX_LENGTH (code);
4676 fmt = GET_RTX_FORMAT (code);
4678 /* We don't need to process a SET_DEST that is a register, CC0,
4679 or PC, so set up to skip this common case. All other cases
4680 where we want to suppress replacing something inside a
4681 SET_SRC are handled via the IN_DEST operand. */
4683 && (REG_P (SET_DEST (x))
4684 || GET_CODE (SET_DEST (x)) == CC0
4685 || GET_CODE (SET_DEST (x)) == PC))
4688 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
4691 op0_mode = GET_MODE (XEXP (x, 0));
4693 for (i = 0; i < len; i++)
4698 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4700 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
4702 new_rtx = (unique_copy && n_occurrences
4703 ? copy_rtx (to) : to);
4708 new_rtx = subst (XVECEXP (x, i, j), from, to, 0,
4711 /* If this substitution failed, this whole thing
4713 if (GET_CODE (new_rtx) == CLOBBER
4714 && XEXP (new_rtx, 0) == const0_rtx)
4718 SUBST (XVECEXP (x, i, j), new_rtx);
4721 else if (fmt[i] == 'e')
4723 /* If this is a register being set, ignore it. */
4724 new_rtx = XEXP (x, i);
4727 && (((code == SUBREG || code == ZERO_EXTRACT)
4729 || code == STRICT_LOW_PART))
4732 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
4734 /* In general, don't install a subreg involving two
4735 modes not tieable. It can worsen register
4736 allocation, and can even make invalid reload
4737 insns, since the reg inside may need to be copied
4738 from in the outside mode, and that may be invalid
4739 if it is an fp reg copied in integer mode.
4741 We allow two exceptions to this: It is valid if
4742 it is inside another SUBREG and the mode of that
4743 SUBREG and the mode of the inside of TO is
4744 tieable and it is valid if X is a SET that copies
4747 if (GET_CODE (to) == SUBREG
4748 && ! MODES_TIEABLE_P (GET_MODE (to),
4749 GET_MODE (SUBREG_REG (to)))
4750 && ! (code == SUBREG
4751 && MODES_TIEABLE_P (GET_MODE (x),
4752 GET_MODE (SUBREG_REG (to))))
4754 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
4757 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4759 #ifdef CANNOT_CHANGE_MODE_CLASS
4762 && REGNO (to) < FIRST_PSEUDO_REGISTER
4763 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
4766 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4769 new_rtx = (unique_copy && n_occurrences ? copy_rtx (to) : to);
4773 /* If we are in a SET_DEST, suppress most cases unless we
4774 have gone inside a MEM, in which case we want to
4775 simplify the address. We assume here that things that
4776 are actually part of the destination have their inner
4777 parts in the first expression. This is true for SUBREG,
4778 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
4779 things aside from REG and MEM that should appear in a
4781 new_rtx = subst (XEXP (x, i), from, to,
4783 && (code == SUBREG || code == STRICT_LOW_PART
4784 || code == ZERO_EXTRACT))
4786 && i == 0), unique_copy);
4788 /* If we found that we will have to reject this combination,
4789 indicate that by returning the CLOBBER ourselves, rather than
4790 an expression containing it. This will speed things up as
4791 well as prevent accidents where two CLOBBERs are considered
4792 to be equal, thus producing an incorrect simplification. */
4794 if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx)
4797 if (GET_CODE (x) == SUBREG
4798 && (CONST_INT_P (new_rtx)
4799 || GET_CODE (new_rtx) == CONST_DOUBLE))
4801 enum machine_mode mode = GET_MODE (x);
4803 x = simplify_subreg (GET_MODE (x), new_rtx,
4804 GET_MODE (SUBREG_REG (x)),
4807 x = gen_rtx_CLOBBER (mode, const0_rtx);
4809 else if (CONST_INT_P (new_rtx)
4810 && GET_CODE (x) == ZERO_EXTEND)
4812 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
4813 new_rtx, GET_MODE (XEXP (x, 0)));
4817 SUBST (XEXP (x, i), new_rtx);
4822 /* Check if we are loading something from the constant pool via float
4823 extension; in this case we would undo compress_float_constant
4824 optimization and degenerate constant load to an immediate value. */
4825 if (GET_CODE (x) == FLOAT_EXTEND
4826 && MEM_P (XEXP (x, 0))
4827 && MEM_READONLY_P (XEXP (x, 0)))
4829 rtx tmp = avoid_constant_pool_reference (x);
4834 /* Try to simplify X. If the simplification changed the code, it is likely
4835 that further simplification will help, so loop, but limit the number
4836 of repetitions that will be performed. */
4838 for (i = 0; i < 4; i++)
4840 /* If X is sufficiently simple, don't bother trying to do anything
4842 if (code != CONST_INT && code != REG && code != CLOBBER)
4843 x = combine_simplify_rtx (x, op0_mode, in_dest);
4845 if (GET_CODE (x) == code)
4848 code = GET_CODE (x);
4850 /* We no longer know the original mode of operand 0 since we
4851 have changed the form of X) */
4852 op0_mode = VOIDmode;
4858 /* Simplify X, a piece of RTL. We just operate on the expression at the
4859 outer level; call `subst' to simplify recursively. Return the new
4862 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
4863 if we are inside a SET_DEST. */
4866 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
4868 enum rtx_code code = GET_CODE (x);
4869 enum machine_mode mode = GET_MODE (x);
4873 /* If this is a commutative operation, put a constant last and a complex
4874 expression first. We don't need to do this for comparisons here. */
4875 if (COMMUTATIVE_ARITH_P (x)
4876 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
4879 SUBST (XEXP (x, 0), XEXP (x, 1));
4880 SUBST (XEXP (x, 1), temp);
4883 /* If this is a simple operation applied to an IF_THEN_ELSE, try
4884 applying it to the arms of the IF_THEN_ELSE. This often simplifies
4885 things. Check for cases where both arms are testing the same
4888 Don't do anything if all operands are very simple. */
4891 && ((!OBJECT_P (XEXP (x, 0))
4892 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4893 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
4894 || (!OBJECT_P (XEXP (x, 1))
4895 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
4896 && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
4898 && (!OBJECT_P (XEXP (x, 0))
4899 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4900 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
4902 rtx cond, true_rtx, false_rtx;
4904 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
4906 /* If everything is a comparison, what we have is highly unlikely
4907 to be simpler, so don't use it. */
4908 && ! (COMPARISON_P (x)
4909 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
4911 rtx cop1 = const0_rtx;
4912 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
4914 if (cond_code == NE && COMPARISON_P (cond))
4917 /* Simplify the alternative arms; this may collapse the true and
4918 false arms to store-flag values. Be careful to use copy_rtx
4919 here since true_rtx or false_rtx might share RTL with x as a
4920 result of the if_then_else_cond call above. */
4921 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
4922 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
4924 /* If true_rtx and false_rtx are not general_operands, an if_then_else
4925 is unlikely to be simpler. */
4926 if (general_operand (true_rtx, VOIDmode)
4927 && general_operand (false_rtx, VOIDmode))
4929 enum rtx_code reversed;
4931 /* Restarting if we generate a store-flag expression will cause
4932 us to loop. Just drop through in this case. */
4934 /* If the result values are STORE_FLAG_VALUE and zero, we can
4935 just make the comparison operation. */
4936 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
4937 x = simplify_gen_relational (cond_code, mode, VOIDmode,
4939 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
4940 && ((reversed = reversed_comparison_code_parts
4941 (cond_code, cond, cop1, NULL))
4943 x = simplify_gen_relational (reversed, mode, VOIDmode,
4946 /* Likewise, we can make the negate of a comparison operation
4947 if the result values are - STORE_FLAG_VALUE and zero. */
4948 else if (CONST_INT_P (true_rtx)
4949 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
4950 && false_rtx == const0_rtx)
4951 x = simplify_gen_unary (NEG, mode,
4952 simplify_gen_relational (cond_code,
4956 else if (CONST_INT_P (false_rtx)
4957 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
4958 && true_rtx == const0_rtx
4959 && ((reversed = reversed_comparison_code_parts
4960 (cond_code, cond, cop1, NULL))
4962 x = simplify_gen_unary (NEG, mode,
4963 simplify_gen_relational (reversed,
4968 return gen_rtx_IF_THEN_ELSE (mode,
4969 simplify_gen_relational (cond_code,
4974 true_rtx, false_rtx);
4976 code = GET_CODE (x);
4977 op0_mode = VOIDmode;
4982 /* Try to fold this expression in case we have constants that weren't
4985 switch (GET_RTX_CLASS (code))
4988 if (op0_mode == VOIDmode)
4989 op0_mode = GET_MODE (XEXP (x, 0));
4990 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
4993 case RTX_COMM_COMPARE:
4995 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
4996 if (cmp_mode == VOIDmode)
4998 cmp_mode = GET_MODE (XEXP (x, 1));
4999 if (cmp_mode == VOIDmode)
5000 cmp_mode = op0_mode;
5002 temp = simplify_relational_operation (code, mode, cmp_mode,
5003 XEXP (x, 0), XEXP (x, 1));
5006 case RTX_COMM_ARITH:
5008 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
5010 case RTX_BITFIELD_OPS:
5012 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
5013 XEXP (x, 1), XEXP (x, 2));
5022 code = GET_CODE (temp);
5023 op0_mode = VOIDmode;
5024 mode = GET_MODE (temp);
5027 /* First see if we can apply the inverse distributive law. */
5028 if (code == PLUS || code == MINUS
5029 || code == AND || code == IOR || code == XOR)
5031 x = apply_distributive_law (x);
5032 code = GET_CODE (x);
5033 op0_mode = VOIDmode;
5036 /* If CODE is an associative operation not otherwise handled, see if we
5037 can associate some operands. This can win if they are constants or
5038 if they are logically related (i.e. (a & b) & a). */
5039 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
5040 || code == AND || code == IOR || code == XOR
5041 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
5042 && ((INTEGRAL_MODE_P (mode) && code != DIV)
5043 || (flag_associative_math && FLOAT_MODE_P (mode))))
5045 if (GET_CODE (XEXP (x, 0)) == code)
5047 rtx other = XEXP (XEXP (x, 0), 0);
5048 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
5049 rtx inner_op1 = XEXP (x, 1);
5052 /* Make sure we pass the constant operand if any as the second
5053 one if this is a commutative operation. */
5054 if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
5056 rtx tem = inner_op0;
5057 inner_op0 = inner_op1;
5060 inner = simplify_binary_operation (code == MINUS ? PLUS
5061 : code == DIV ? MULT
5063 mode, inner_op0, inner_op1);
5065 /* For commutative operations, try the other pair if that one
5067 if (inner == 0 && COMMUTATIVE_ARITH_P (x))
5069 other = XEXP (XEXP (x, 0), 1);
5070 inner = simplify_binary_operation (code, mode,
5071 XEXP (XEXP (x, 0), 0),
5076 return simplify_gen_binary (code, mode, other, inner);
5080 /* A little bit of algebraic simplification here. */
5084 /* Ensure that our address has any ASHIFTs converted to MULT in case
5085 address-recognizing predicates are called later. */
5086 temp = make_compound_operation (XEXP (x, 0), MEM);
5087 SUBST (XEXP (x, 0), temp);
5091 if (op0_mode == VOIDmode)
5092 op0_mode = GET_MODE (SUBREG_REG (x));
5094 /* See if this can be moved to simplify_subreg. */
5095 if (CONSTANT_P (SUBREG_REG (x))
5096 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
5097 /* Don't call gen_lowpart if the inner mode
5098 is VOIDmode and we cannot simplify it, as SUBREG without
5099 inner mode is invalid. */
5100 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
5101 || gen_lowpart_common (mode, SUBREG_REG (x))))
5102 return gen_lowpart (mode, SUBREG_REG (x));
5104 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
5108 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
5114 /* Don't change the mode of the MEM if that would change the meaning
5116 if (MEM_P (SUBREG_REG (x))
5117 && (MEM_VOLATILE_P (SUBREG_REG (x))
5118 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
5119 return gen_rtx_CLOBBER (mode, const0_rtx);
5121 /* Note that we cannot do any narrowing for non-constants since
5122 we might have been counting on using the fact that some bits were
5123 zero. We now do this in the SET. */
5128 temp = expand_compound_operation (XEXP (x, 0));
5130 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5131 replaced by (lshiftrt X C). This will convert
5132 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5134 if (GET_CODE (temp) == ASHIFTRT
5135 && CONST_INT_P (XEXP (temp, 1))
5136 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
5137 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
5138 INTVAL (XEXP (temp, 1)));
5140 /* If X has only a single bit that might be nonzero, say, bit I, convert
5141 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5142 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5143 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5144 or a SUBREG of one since we'd be making the expression more
5145 complex if it was just a register. */
5148 && ! (GET_CODE (temp) == SUBREG
5149 && REG_P (SUBREG_REG (temp)))
5150 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
5152 rtx temp1 = simplify_shift_const
5153 (NULL_RTX, ASHIFTRT, mode,
5154 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
5155 GET_MODE_BITSIZE (mode) - 1 - i),
5156 GET_MODE_BITSIZE (mode) - 1 - i);
5158 /* If all we did was surround TEMP with the two shifts, we
5159 haven't improved anything, so don't use it. Otherwise,
5160 we are better off with TEMP1. */
5161 if (GET_CODE (temp1) != ASHIFTRT
5162 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
5163 || XEXP (XEXP (temp1, 0), 0) != temp)
5169 /* We can't handle truncation to a partial integer mode here
5170 because we don't know the real bitsize of the partial
5172 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
5175 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5177 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
5178 GET_MODE_MASK (mode), 0));
5180 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5181 whose value is a comparison can be replaced with a subreg if
5182 STORE_FLAG_VALUE permits. */
5183 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5184 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
5185 && (temp = get_last_value (XEXP (x, 0)))
5186 && COMPARISON_P (temp))
5187 return gen_lowpart (mode, XEXP (x, 0));
5191 /* (const (const X)) can become (const X). Do it this way rather than
5192 returning the inner CONST since CONST can be shared with a
5194 if (GET_CODE (XEXP (x, 0)) == CONST)
5195 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
5200 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5201 can add in an offset. find_split_point will split this address up
5202 again if it doesn't match. */
5203 if (GET_CODE (XEXP (x, 0)) == HIGH
5204 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
5210 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5211 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5212 bit-field and can be replaced by either a sign_extend or a
5213 sign_extract. The `and' may be a zero_extend and the two
5214 <c>, -<c> constants may be reversed. */
5215 if (GET_CODE (XEXP (x, 0)) == XOR
5216 && CONST_INT_P (XEXP (x, 1))
5217 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
5218 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
5219 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
5220 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
5221 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5222 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
5223 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
5224 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
5225 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
5226 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
5227 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
5228 == (unsigned int) i + 1))))
5229 return simplify_shift_const
5230 (NULL_RTX, ASHIFTRT, mode,
5231 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5232 XEXP (XEXP (XEXP (x, 0), 0), 0),
5233 GET_MODE_BITSIZE (mode) - (i + 1)),
5234 GET_MODE_BITSIZE (mode) - (i + 1));
5236 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5237 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5238 the bitsize of the mode - 1. This allows simplification of
5239 "a = (b & 8) == 0;" */
5240 if (XEXP (x, 1) == constm1_rtx
5241 && !REG_P (XEXP (x, 0))
5242 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5243 && REG_P (SUBREG_REG (XEXP (x, 0))))
5244 && nonzero_bits (XEXP (x, 0), mode) == 1)
5245 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
5246 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5247 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
5248 GET_MODE_BITSIZE (mode) - 1),
5249 GET_MODE_BITSIZE (mode) - 1);
5251 /* If we are adding two things that have no bits in common, convert
5252 the addition into an IOR. This will often be further simplified,
5253 for example in cases like ((a & 1) + (a & 2)), which can
5256 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5257 && (nonzero_bits (XEXP (x, 0), mode)
5258 & nonzero_bits (XEXP (x, 1), mode)) == 0)
5260 /* Try to simplify the expression further. */
5261 rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
5262 temp = combine_simplify_rtx (tor, mode, in_dest);
5264 /* If we could, great. If not, do not go ahead with the IOR
5265 replacement, since PLUS appears in many special purpose
5266 address arithmetic instructions. */
5267 if (GET_CODE (temp) != CLOBBER && temp != tor)
5273 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5274 (and <foo> (const_int pow2-1)) */
5275 if (GET_CODE (XEXP (x, 1)) == AND
5276 && CONST_INT_P (XEXP (XEXP (x, 1), 1))
5277 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
5278 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
5279 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
5280 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
5284 /* If we have (mult (plus A B) C), apply the distributive law and then
5285 the inverse distributive law to see if things simplify. This
5286 occurs mostly in addresses, often when unrolling loops. */
5288 if (GET_CODE (XEXP (x, 0)) == PLUS)
5290 rtx result = distribute_and_simplify_rtx (x, 0);
5295 /* Try simplify a*(b/c) as (a*b)/c. */
5296 if (FLOAT_MODE_P (mode) && flag_associative_math
5297 && GET_CODE (XEXP (x, 0)) == DIV)
5299 rtx tem = simplify_binary_operation (MULT, mode,
5300 XEXP (XEXP (x, 0), 0),
5303 return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
5308 /* If this is a divide by a power of two, treat it as a shift if
5309 its first operand is a shift. */
5310 if (CONST_INT_P (XEXP (x, 1))
5311 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
5312 && (GET_CODE (XEXP (x, 0)) == ASHIFT
5313 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
5314 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
5315 || GET_CODE (XEXP (x, 0)) == ROTATE
5316 || GET_CODE (XEXP (x, 0)) == ROTATERT))
5317 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
5321 case GT: case GTU: case GE: case GEU:
5322 case LT: case LTU: case LE: case LEU:
5323 case UNEQ: case LTGT:
5324 case UNGT: case UNGE:
5325 case UNLT: case UNLE:
5326 case UNORDERED: case ORDERED:
5327 /* If the first operand is a condition code, we can't do anything
5329 if (GET_CODE (XEXP (x, 0)) == COMPARE
5330 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
5331 && ! CC0_P (XEXP (x, 0))))
5333 rtx op0 = XEXP (x, 0);
5334 rtx op1 = XEXP (x, 1);
5335 enum rtx_code new_code;
5337 if (GET_CODE (op0) == COMPARE)
5338 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
5340 /* Simplify our comparison, if possible. */
5341 new_code = simplify_comparison (code, &op0, &op1);
5343 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5344 if only the low-order bit is possibly nonzero in X (such as when
5345 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5346 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5347 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5350 Remove any ZERO_EXTRACT we made when thinking this was a
5351 comparison. It may now be simpler to use, e.g., an AND. If a
5352 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5353 the call to make_compound_operation in the SET case. */
5355 if (STORE_FLAG_VALUE == 1
5356 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5357 && op1 == const0_rtx
5358 && mode == GET_MODE (op0)
5359 && nonzero_bits (op0, mode) == 1)
5360 return gen_lowpart (mode,
5361 expand_compound_operation (op0));
5363 else if (STORE_FLAG_VALUE == 1
5364 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5365 && op1 == const0_rtx
5366 && mode == GET_MODE (op0)
5367 && (num_sign_bit_copies (op0, mode)
5368 == GET_MODE_BITSIZE (mode)))
5370 op0 = expand_compound_operation (op0);
5371 return simplify_gen_unary (NEG, mode,
5372 gen_lowpart (mode, op0),
5376 else if (STORE_FLAG_VALUE == 1
5377 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5378 && op1 == const0_rtx
5379 && mode == GET_MODE (op0)
5380 && nonzero_bits (op0, mode) == 1)
5382 op0 = expand_compound_operation (op0);
5383 return simplify_gen_binary (XOR, mode,
5384 gen_lowpart (mode, op0),
5388 else if (STORE_FLAG_VALUE == 1
5389 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5390 && op1 == const0_rtx
5391 && mode == GET_MODE (op0)
5392 && (num_sign_bit_copies (op0, mode)
5393 == GET_MODE_BITSIZE (mode)))
5395 op0 = expand_compound_operation (op0);
5396 return plus_constant (gen_lowpart (mode, op0), 1);
5399 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5401 if (STORE_FLAG_VALUE == -1
5402 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5403 && op1 == const0_rtx
5404 && (num_sign_bit_copies (op0, mode)
5405 == GET_MODE_BITSIZE (mode)))
5406 return gen_lowpart (mode,
5407 expand_compound_operation (op0));
5409 else if (STORE_FLAG_VALUE == -1
5410 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5411 && op1 == const0_rtx
5412 && mode == GET_MODE (op0)
5413 && nonzero_bits (op0, mode) == 1)
5415 op0 = expand_compound_operation (op0);
5416 return simplify_gen_unary (NEG, mode,
5417 gen_lowpart (mode, op0),
5421 else if (STORE_FLAG_VALUE == -1
5422 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5423 && op1 == const0_rtx
5424 && mode == GET_MODE (op0)
5425 && (num_sign_bit_copies (op0, mode)
5426 == GET_MODE_BITSIZE (mode)))
5428 op0 = expand_compound_operation (op0);
5429 return simplify_gen_unary (NOT, mode,
5430 gen_lowpart (mode, op0),
5434 /* If X is 0/1, (eq X 0) is X-1. */
5435 else if (STORE_FLAG_VALUE == -1
5436 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5437 && op1 == const0_rtx
5438 && mode == GET_MODE (op0)
5439 && nonzero_bits (op0, mode) == 1)
5441 op0 = expand_compound_operation (op0);
5442 return plus_constant (gen_lowpart (mode, op0), -1);
5445 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5446 one bit that might be nonzero, we can convert (ne x 0) to
5447 (ashift x c) where C puts the bit in the sign bit. Remove any
5448 AND with STORE_FLAG_VALUE when we are done, since we are only
5449 going to test the sign bit. */
5450 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5451 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5452 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5453 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5454 && op1 == const0_rtx
5455 && mode == GET_MODE (op0)
5456 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
5458 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
5459 expand_compound_operation (op0),
5460 GET_MODE_BITSIZE (mode) - 1 - i);
5461 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
5467 /* If the code changed, return a whole new comparison. */
5468 if (new_code != code)
5469 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
5471 /* Otherwise, keep this operation, but maybe change its operands.
5472 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5473 SUBST (XEXP (x, 0), op0);
5474 SUBST (XEXP (x, 1), op1);
5479 return simplify_if_then_else (x);
5485 /* If we are processing SET_DEST, we are done. */
5489 return expand_compound_operation (x);
5492 return simplify_set (x);
5496 return simplify_logical (x);
5503 /* If this is a shift by a constant amount, simplify it. */
5504 if (CONST_INT_P (XEXP (x, 1)))
5505 return simplify_shift_const (x, code, mode, XEXP (x, 0),
5506 INTVAL (XEXP (x, 1)));
5508 else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
5510 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
5512 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
5524 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5527 simplify_if_then_else (rtx x)
5529 enum machine_mode mode = GET_MODE (x);
5530 rtx cond = XEXP (x, 0);
5531 rtx true_rtx = XEXP (x, 1);
5532 rtx false_rtx = XEXP (x, 2);
5533 enum rtx_code true_code = GET_CODE (cond);
5534 int comparison_p = COMPARISON_P (cond);
5537 enum rtx_code false_code;
5540 /* Simplify storing of the truth value. */
5541 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
5542 return simplify_gen_relational (true_code, mode, VOIDmode,
5543 XEXP (cond, 0), XEXP (cond, 1));
5545 /* Also when the truth value has to be reversed. */
5547 && true_rtx == const0_rtx && false_rtx == const_true_rtx
5548 && (reversed = reversed_comparison (cond, mode)))
5551 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5552 in it is being compared against certain values. Get the true and false
5553 comparisons and see if that says anything about the value of each arm. */
5556 && ((false_code = reversed_comparison_code (cond, NULL))
5558 && REG_P (XEXP (cond, 0)))
5561 rtx from = XEXP (cond, 0);
5562 rtx true_val = XEXP (cond, 1);
5563 rtx false_val = true_val;
5566 /* If FALSE_CODE is EQ, swap the codes and arms. */
5568 if (false_code == EQ)
5570 swapped = 1, true_code = EQ, false_code = NE;
5571 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5574 /* If we are comparing against zero and the expression being tested has
5575 only a single bit that might be nonzero, that is its value when it is
5576 not equal to zero. Similarly if it is known to be -1 or 0. */
5578 if (true_code == EQ && true_val == const0_rtx
5579 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
5582 false_val = GEN_INT (trunc_int_for_mode (nzb, GET_MODE (from)));
5584 else if (true_code == EQ && true_val == const0_rtx
5585 && (num_sign_bit_copies (from, GET_MODE (from))
5586 == GET_MODE_BITSIZE (GET_MODE (from))))
5589 false_val = constm1_rtx;
5592 /* Now simplify an arm if we know the value of the register in the
5593 branch and it is used in the arm. Be careful due to the potential
5594 of locally-shared RTL. */
5596 if (reg_mentioned_p (from, true_rtx))
5597 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
5599 pc_rtx, pc_rtx, 0, 0);
5600 if (reg_mentioned_p (from, false_rtx))
5601 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
5603 pc_rtx, pc_rtx, 0, 0);
5605 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
5606 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
5608 true_rtx = XEXP (x, 1);
5609 false_rtx = XEXP (x, 2);
5610 true_code = GET_CODE (cond);
5613 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
5614 reversed, do so to avoid needing two sets of patterns for
5615 subtract-and-branch insns. Similarly if we have a constant in the true
5616 arm, the false arm is the same as the first operand of the comparison, or
5617 the false arm is more complicated than the true arm. */
5620 && reversed_comparison_code (cond, NULL) != UNKNOWN
5621 && (true_rtx == pc_rtx
5622 || (CONSTANT_P (true_rtx)
5623 && !CONST_INT_P (false_rtx) && false_rtx != pc_rtx)
5624 || true_rtx == const0_rtx
5625 || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
5626 || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
5627 && !OBJECT_P (false_rtx))
5628 || reg_mentioned_p (true_rtx, false_rtx)
5629 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
5631 true_code = reversed_comparison_code (cond, NULL);
5632 SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
5633 SUBST (XEXP (x, 1), false_rtx);
5634 SUBST (XEXP (x, 2), true_rtx);
5636 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5639 /* It is possible that the conditional has been simplified out. */
5640 true_code = GET_CODE (cond);
5641 comparison_p = COMPARISON_P (cond);
5644 /* If the two arms are identical, we don't need the comparison. */
5646 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
5649 /* Convert a == b ? b : a to "a". */
5650 if (true_code == EQ && ! side_effects_p (cond)
5651 && !HONOR_NANS (mode)
5652 && rtx_equal_p (XEXP (cond, 0), false_rtx)
5653 && rtx_equal_p (XEXP (cond, 1), true_rtx))
5655 else if (true_code == NE && ! side_effects_p (cond)
5656 && !HONOR_NANS (mode)
5657 && rtx_equal_p (XEXP (cond, 0), true_rtx)
5658 && rtx_equal_p (XEXP (cond, 1), false_rtx))
5661 /* Look for cases where we have (abs x) or (neg (abs X)). */
5663 if (GET_MODE_CLASS (mode) == MODE_INT
5665 && XEXP (cond, 1) == const0_rtx
5666 && GET_CODE (false_rtx) == NEG
5667 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
5668 && rtx_equal_p (true_rtx, XEXP (cond, 0))
5669 && ! side_effects_p (true_rtx))
5674 return simplify_gen_unary (ABS, mode, true_rtx, mode);
5678 simplify_gen_unary (NEG, mode,
5679 simplify_gen_unary (ABS, mode, true_rtx, mode),
5685 /* Look for MIN or MAX. */
5687 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
5689 && rtx_equal_p (XEXP (cond, 0), true_rtx)
5690 && rtx_equal_p (XEXP (cond, 1), false_rtx)
5691 && ! side_effects_p (cond))
5696 return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
5699 return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
5702 return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
5705 return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
5710 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
5711 second operand is zero, this can be done as (OP Z (mult COND C2)) where
5712 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
5713 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
5714 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
5715 neither 1 or -1, but it isn't worth checking for. */
5717 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
5719 && GET_MODE_CLASS (mode) == MODE_INT
5720 && ! side_effects_p (x))
5722 rtx t = make_compound_operation (true_rtx, SET);
5723 rtx f = make_compound_operation (false_rtx, SET);
5724 rtx cond_op0 = XEXP (cond, 0);
5725 rtx cond_op1 = XEXP (cond, 1);
5726 enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
5727 enum machine_mode m = mode;
5728 rtx z = 0, c1 = NULL_RTX;
5730 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
5731 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
5732 || GET_CODE (t) == ASHIFT
5733 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
5734 && rtx_equal_p (XEXP (t, 0), f))
5735 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
5737 /* If an identity-zero op is commutative, check whether there
5738 would be a match if we swapped the operands. */
5739 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
5740 || GET_CODE (t) == XOR)
5741 && rtx_equal_p (XEXP (t, 1), f))
5742 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
5743 else if (GET_CODE (t) == SIGN_EXTEND
5744 && (GET_CODE (XEXP (t, 0)) == PLUS
5745 || GET_CODE (XEXP (t, 0)) == MINUS
5746 || GET_CODE (XEXP (t, 0)) == IOR
5747 || GET_CODE (XEXP (t, 0)) == XOR
5748 || GET_CODE (XEXP (t, 0)) == ASHIFT
5749 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5750 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5751 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5752 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5753 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5754 && (num_sign_bit_copies (f, GET_MODE (f))
5756 (GET_MODE_BITSIZE (mode)
5757 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
5759 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5760 extend_op = SIGN_EXTEND;
5761 m = GET_MODE (XEXP (t, 0));
5763 else if (GET_CODE (t) == SIGN_EXTEND
5764 && (GET_CODE (XEXP (t, 0)) == PLUS
5765 || GET_CODE (XEXP (t, 0)) == IOR
5766 || GET_CODE (XEXP (t, 0)) == XOR)
5767 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5768 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5769 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5770 && (num_sign_bit_copies (f, GET_MODE (f))
5772 (GET_MODE_BITSIZE (mode)
5773 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
5775 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5776 extend_op = SIGN_EXTEND;
5777 m = GET_MODE (XEXP (t, 0));
5779 else if (GET_CODE (t) == ZERO_EXTEND
5780 && (GET_CODE (XEXP (t, 0)) == PLUS
5781 || GET_CODE (XEXP (t, 0)) == MINUS
5782 || GET_CODE (XEXP (t, 0)) == IOR
5783 || GET_CODE (XEXP (t, 0)) == XOR
5784 || GET_CODE (XEXP (t, 0)) == ASHIFT
5785 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5786 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5787 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5788 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5789 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5790 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5791 && ((nonzero_bits (f, GET_MODE (f))
5792 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
5795 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5796 extend_op = ZERO_EXTEND;
5797 m = GET_MODE (XEXP (t, 0));
5799 else if (GET_CODE (t) == ZERO_EXTEND
5800 && (GET_CODE (XEXP (t, 0)) == PLUS
5801 || GET_CODE (XEXP (t, 0)) == IOR
5802 || GET_CODE (XEXP (t, 0)) == XOR)
5803 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5804 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5805 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5806 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5807 && ((nonzero_bits (f, GET_MODE (f))
5808 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
5811 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5812 extend_op = ZERO_EXTEND;
5813 m = GET_MODE (XEXP (t, 0));
5818 temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
5819 cond_op0, cond_op1),
5820 pc_rtx, pc_rtx, 0, 0);
5821 temp = simplify_gen_binary (MULT, m, temp,
5822 simplify_gen_binary (MULT, m, c1,
5824 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
5825 temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
5827 if (extend_op != UNKNOWN)
5828 temp = simplify_gen_unary (extend_op, mode, temp, m);
5834 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5835 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5836 negation of a single bit, we can convert this operation to a shift. We
5837 can actually do this more generally, but it doesn't seem worth it. */
5839 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5840 && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
5841 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
5842 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
5843 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
5844 == GET_MODE_BITSIZE (mode))
5845 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
5847 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5848 gen_lowpart (mode, XEXP (cond, 0)), i);
5850 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
5851 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5852 && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
5853 && GET_MODE (XEXP (cond, 0)) == mode
5854 && (INTVAL (true_rtx) & GET_MODE_MASK (mode))
5855 == nonzero_bits (XEXP (cond, 0), mode)
5856 && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
5857 return XEXP (cond, 0);
5862 /* Simplify X, a SET expression. Return the new expression. */
5865 simplify_set (rtx x)
5867 rtx src = SET_SRC (x);
5868 rtx dest = SET_DEST (x);
5869 enum machine_mode mode
5870 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
5874 /* (set (pc) (return)) gets written as (return). */
5875 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
5878 /* Now that we know for sure which bits of SRC we are using, see if we can
5879 simplify the expression for the object knowing that we only need the
5882 if (GET_MODE_CLASS (mode) == MODE_INT
5883 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5885 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, 0);
5886 SUBST (SET_SRC (x), src);
5889 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5890 the comparison result and try to simplify it unless we already have used
5891 undobuf.other_insn. */
5892 if ((GET_MODE_CLASS (mode) == MODE_CC
5893 || GET_CODE (src) == COMPARE
5895 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5896 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5897 && COMPARISON_P (*cc_use)
5898 && rtx_equal_p (XEXP (*cc_use, 0), dest))
5900 enum rtx_code old_code = GET_CODE (*cc_use);
5901 enum rtx_code new_code;
5903 int other_changed = 0;
5904 enum machine_mode compare_mode = GET_MODE (dest);
5906 if (GET_CODE (src) == COMPARE)
5907 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5909 op0 = src, op1 = CONST0_RTX (GET_MODE (src));
5911 tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
5914 new_code = old_code;
5915 else if (!CONSTANT_P (tmp))
5917 new_code = GET_CODE (tmp);
5918 op0 = XEXP (tmp, 0);
5919 op1 = XEXP (tmp, 1);
5923 rtx pat = PATTERN (other_insn);
5924 undobuf.other_insn = other_insn;
5925 SUBST (*cc_use, tmp);
5927 /* Attempt to simplify CC user. */
5928 if (GET_CODE (pat) == SET)
5930 rtx new_rtx = simplify_rtx (SET_SRC (pat));
5931 if (new_rtx != NULL_RTX)
5932 SUBST (SET_SRC (pat), new_rtx);
5935 /* Convert X into a no-op move. */
5936 SUBST (SET_DEST (x), pc_rtx);
5937 SUBST (SET_SRC (x), pc_rtx);
5941 /* Simplify our comparison, if possible. */
5942 new_code = simplify_comparison (new_code, &op0, &op1);
5944 #ifdef SELECT_CC_MODE
5945 /* If this machine has CC modes other than CCmode, check to see if we
5946 need to use a different CC mode here. */
5947 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
5948 compare_mode = GET_MODE (op0);
5950 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5953 /* If the mode changed, we have to change SET_DEST, the mode in the
5954 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5955 a hard register, just build new versions with the proper mode. If it
5956 is a pseudo, we lose unless it is only time we set the pseudo, in
5957 which case we can safely change its mode. */
5958 if (compare_mode != GET_MODE (dest))
5960 if (can_change_dest_mode (dest, 0, compare_mode))
5962 unsigned int regno = REGNO (dest);
5965 if (regno < FIRST_PSEUDO_REGISTER)
5966 new_dest = gen_rtx_REG (compare_mode, regno);
5969 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
5970 new_dest = regno_reg_rtx[regno];
5973 SUBST (SET_DEST (x), new_dest);
5974 SUBST (XEXP (*cc_use, 0), new_dest);
5981 #endif /* SELECT_CC_MODE */
5983 /* If the code changed, we have to build a new comparison in
5984 undobuf.other_insn. */
5985 if (new_code != old_code)
5987 int other_changed_previously = other_changed;
5988 unsigned HOST_WIDE_INT mask;
5989 rtx old_cc_use = *cc_use;
5991 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5995 /* If the only change we made was to change an EQ into an NE or
5996 vice versa, OP0 has only one bit that might be nonzero, and OP1
5997 is zero, check if changing the user of the condition code will
5998 produce a valid insn. If it won't, we can keep the original code
5999 in that insn by surrounding our operation with an XOR. */
6001 if (((old_code == NE && new_code == EQ)
6002 || (old_code == EQ && new_code == NE))
6003 && ! other_changed_previously && op1 == const0_rtx
6004 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
6005 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
6007 rtx pat = PATTERN (other_insn), note = 0;
6009 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
6010 && ! check_asm_operands (pat)))
6012 *cc_use = old_cc_use;
6015 op0 = simplify_gen_binary (XOR, GET_MODE (op0),
6016 op0, GEN_INT (mask));
6022 undobuf.other_insn = other_insn;
6024 /* Otherwise, if we didn't previously have a COMPARE in the
6025 correct mode, we need one. */
6026 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
6028 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6031 else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
6033 SUBST (SET_SRC (x), op0);
6036 /* Otherwise, update the COMPARE if needed. */
6037 else if (XEXP (src, 0) != op0 || XEXP (src, 1) != op1)
6039 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6045 /* Get SET_SRC in a form where we have placed back any
6046 compound expressions. Then do the checks below. */
6047 src = make_compound_operation (src, SET);
6048 SUBST (SET_SRC (x), src);
6051 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6052 and X being a REG or (subreg (reg)), we may be able to convert this to
6053 (set (subreg:m2 x) (op)).
6055 We can always do this if M1 is narrower than M2 because that means that
6056 we only care about the low bits of the result.
6058 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6059 perform a narrower operation than requested since the high-order bits will
6060 be undefined. On machine where it is defined, this transformation is safe
6061 as long as M1 and M2 have the same number of words. */
6063 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6064 && !OBJECT_P (SUBREG_REG (src))
6065 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
6067 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
6068 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
6069 #ifndef WORD_REGISTER_OPERATIONS
6070 && (GET_MODE_SIZE (GET_MODE (src))
6071 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
6073 #ifdef CANNOT_CHANGE_MODE_CLASS
6074 && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
6075 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
6076 GET_MODE (SUBREG_REG (src)),
6080 || (GET_CODE (dest) == SUBREG
6081 && REG_P (SUBREG_REG (dest)))))
6083 SUBST (SET_DEST (x),
6084 gen_lowpart (GET_MODE (SUBREG_REG (src)),
6086 SUBST (SET_SRC (x), SUBREG_REG (src));
6088 src = SET_SRC (x), dest = SET_DEST (x);
6092 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6095 && GET_CODE (src) == SUBREG
6096 && subreg_lowpart_p (src)
6097 && (GET_MODE_BITSIZE (GET_MODE (src))
6098 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
6100 rtx inner = SUBREG_REG (src);
6101 enum machine_mode inner_mode = GET_MODE (inner);
6103 /* Here we make sure that we don't have a sign bit on. */
6104 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
6105 && (nonzero_bits (inner, inner_mode)
6106 < ((unsigned HOST_WIDE_INT) 1
6107 << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
6109 SUBST (SET_SRC (x), inner);
6115 #ifdef LOAD_EXTEND_OP
6116 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6117 would require a paradoxical subreg. Replace the subreg with a
6118 zero_extend to avoid the reload that would otherwise be required. */
6120 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6121 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src)))
6122 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
6123 && SUBREG_BYTE (src) == 0
6124 && (GET_MODE_SIZE (GET_MODE (src))
6125 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
6126 && MEM_P (SUBREG_REG (src)))
6129 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
6130 GET_MODE (src), SUBREG_REG (src)));
6136 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6137 are comparing an item known to be 0 or -1 against 0, use a logical
6138 operation instead. Check for one of the arms being an IOR of the other
6139 arm with some value. We compute three terms to be IOR'ed together. In
6140 practice, at most two will be nonzero. Then we do the IOR's. */
6142 if (GET_CODE (dest) != PC
6143 && GET_CODE (src) == IF_THEN_ELSE
6144 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
6145 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
6146 && XEXP (XEXP (src, 0), 1) == const0_rtx
6147 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
6148 #ifdef HAVE_conditional_move
6149 && ! can_conditionally_move_p (GET_MODE (src))
6151 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
6152 GET_MODE (XEXP (XEXP (src, 0), 0)))
6153 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
6154 && ! side_effects_p (src))
6156 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
6157 ? XEXP (src, 1) : XEXP (src, 2));
6158 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
6159 ? XEXP (src, 2) : XEXP (src, 1));
6160 rtx term1 = const0_rtx, term2, term3;
6162 if (GET_CODE (true_rtx) == IOR
6163 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
6164 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
6165 else if (GET_CODE (true_rtx) == IOR
6166 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
6167 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
6168 else if (GET_CODE (false_rtx) == IOR
6169 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
6170 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
6171 else if (GET_CODE (false_rtx) == IOR
6172 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
6173 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
6175 term2 = simplify_gen_binary (AND, GET_MODE (src),
6176 XEXP (XEXP (src, 0), 0), true_rtx);
6177 term3 = simplify_gen_binary (AND, GET_MODE (src),
6178 simplify_gen_unary (NOT, GET_MODE (src),
6179 XEXP (XEXP (src, 0), 0),
6184 simplify_gen_binary (IOR, GET_MODE (src),
6185 simplify_gen_binary (IOR, GET_MODE (src),
6192 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6193 whole thing fail. */
6194 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
6196 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
6199 /* Convert this into a field assignment operation, if possible. */
6200 return make_field_assignment (x);
6203 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6207 simplify_logical (rtx x)
6209 enum machine_mode mode = GET_MODE (x);
6210 rtx op0 = XEXP (x, 0);
6211 rtx op1 = XEXP (x, 1);
6213 switch (GET_CODE (x))
6216 /* We can call simplify_and_const_int only if we don't lose
6217 any (sign) bits when converting INTVAL (op1) to
6218 "unsigned HOST_WIDE_INT". */
6219 if (CONST_INT_P (op1)
6220 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
6221 || INTVAL (op1) > 0))
6223 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
6224 if (GET_CODE (x) != AND)
6231 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6232 apply the distributive law and then the inverse distributive
6233 law to see if things simplify. */
6234 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
6236 rtx result = distribute_and_simplify_rtx (x, 0);
6240 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
6242 rtx result = distribute_and_simplify_rtx (x, 1);
6249 /* If we have (ior (and A B) C), apply the distributive law and then
6250 the inverse distributive law to see if things simplify. */
6252 if (GET_CODE (op0) == AND)
6254 rtx result = distribute_and_simplify_rtx (x, 0);
6259 if (GET_CODE (op1) == AND)
6261 rtx result = distribute_and_simplify_rtx (x, 1);
6274 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6275 operations" because they can be replaced with two more basic operations.
6276 ZERO_EXTEND is also considered "compound" because it can be replaced with
6277 an AND operation, which is simpler, though only one operation.
6279 The function expand_compound_operation is called with an rtx expression
6280 and will convert it to the appropriate shifts and AND operations,
6281 simplifying at each stage.
6283 The function make_compound_operation is called to convert an expression
6284 consisting of shifts and ANDs into the equivalent compound expression.
6285 It is the inverse of this function, loosely speaking. */
6288 expand_compound_operation (rtx x)
6290 unsigned HOST_WIDE_INT pos = 0, len;
6292 unsigned int modewidth;
6295 switch (GET_CODE (x))
6300 /* We can't necessarily use a const_int for a multiword mode;
6301 it depends on implicitly extending the value.
6302 Since we don't know the right way to extend it,
6303 we can't tell whether the implicit way is right.
6305 Even for a mode that is no wider than a const_int,
6306 we can't win, because we need to sign extend one of its bits through
6307 the rest of it, and we don't know which bit. */
6308 if (CONST_INT_P (XEXP (x, 0)))
6311 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6312 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6313 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6314 reloaded. If not for that, MEM's would very rarely be safe.
6316 Reject MODEs bigger than a word, because we might not be able
6317 to reference a two-register group starting with an arbitrary register
6318 (and currently gen_lowpart might crash for a SUBREG). */
6320 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
6323 /* Reject MODEs that aren't scalar integers because turning vector
6324 or complex modes into shifts causes problems. */
6326 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6329 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
6330 /* If the inner object has VOIDmode (the only way this can happen
6331 is if it is an ASM_OPERANDS), we can't do anything since we don't
6332 know how much masking to do. */
6341 /* ... fall through ... */
6344 /* If the operand is a CLOBBER, just return it. */
6345 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
6348 if (!CONST_INT_P (XEXP (x, 1))
6349 || !CONST_INT_P (XEXP (x, 2))
6350 || GET_MODE (XEXP (x, 0)) == VOIDmode)
6353 /* Reject MODEs that aren't scalar integers because turning vector
6354 or complex modes into shifts causes problems. */
6356 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6359 len = INTVAL (XEXP (x, 1));
6360 pos = INTVAL (XEXP (x, 2));
6362 /* This should stay within the object being extracted, fail otherwise. */
6363 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
6366 if (BITS_BIG_ENDIAN)
6367 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
6374 /* Convert sign extension to zero extension, if we know that the high
6375 bit is not set, as this is easier to optimize. It will be converted
6376 back to cheaper alternative in make_extraction. */
6377 if (GET_CODE (x) == SIGN_EXTEND
6378 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6379 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6380 & ~(((unsigned HOST_WIDE_INT)
6381 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
6385 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
6386 rtx temp2 = expand_compound_operation (temp);
6388 /* Make sure this is a profitable operation. */
6389 if (rtx_cost (x, SET, optimize_this_for_speed_p)
6390 > rtx_cost (temp2, SET, optimize_this_for_speed_p))
6392 else if (rtx_cost (x, SET, optimize_this_for_speed_p)
6393 > rtx_cost (temp, SET, optimize_this_for_speed_p))
6399 /* We can optimize some special cases of ZERO_EXTEND. */
6400 if (GET_CODE (x) == ZERO_EXTEND)
6402 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6403 know that the last value didn't have any inappropriate bits
6405 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6406 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6407 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6408 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
6409 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6410 return XEXP (XEXP (x, 0), 0);
6412 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6413 if (GET_CODE (XEXP (x, 0)) == SUBREG
6414 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6415 && subreg_lowpart_p (XEXP (x, 0))
6416 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6417 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
6418 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6419 return SUBREG_REG (XEXP (x, 0));
6421 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6422 is a comparison and STORE_FLAG_VALUE permits. This is like
6423 the first case, but it works even when GET_MODE (x) is larger
6424 than HOST_WIDE_INT. */
6425 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6426 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6427 && COMPARISON_P (XEXP (XEXP (x, 0), 0))
6428 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6429 <= HOST_BITS_PER_WIDE_INT)
6430 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
6431 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6432 return XEXP (XEXP (x, 0), 0);
6434 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6435 if (GET_CODE (XEXP (x, 0)) == SUBREG
6436 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6437 && subreg_lowpart_p (XEXP (x, 0))
6438 && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
6439 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6440 <= HOST_BITS_PER_WIDE_INT)
6441 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
6442 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6443 return SUBREG_REG (XEXP (x, 0));
6447 /* If we reach here, we want to return a pair of shifts. The inner
6448 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6449 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6450 logical depending on the value of UNSIGNEDP.
6452 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6453 converted into an AND of a shift.
6455 We must check for the case where the left shift would have a negative
6456 count. This can happen in a case like (x >> 31) & 255 on machines
6457 that can't shift by a constant. On those machines, we would first
6458 combine the shift with the AND to produce a variable-position
6459 extraction. Then the constant of 31 would be substituted in to produce
6460 a such a position. */
6462 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
6463 if (modewidth + len >= pos)
6465 enum machine_mode mode = GET_MODE (x);
6466 tem = gen_lowpart (mode, XEXP (x, 0));
6467 if (!tem || GET_CODE (tem) == CLOBBER)
6469 tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
6470 tem, modewidth - pos - len);
6471 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
6472 mode, tem, modewidth - len);
6474 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
6475 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
6476 simplify_shift_const (NULL_RTX, LSHIFTRT,
6479 ((HOST_WIDE_INT) 1 << len) - 1);
6481 /* Any other cases we can't handle. */
6484 /* If we couldn't do this for some reason, return the original
6486 if (GET_CODE (tem) == CLOBBER)
6492 /* X is a SET which contains an assignment of one object into
6493 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6494 or certain SUBREGS). If possible, convert it into a series of
6497 We half-heartedly support variable positions, but do not at all
6498 support variable lengths. */
6501 expand_field_assignment (const_rtx x)
6504 rtx pos; /* Always counts from low bit. */
6506 rtx mask, cleared, masked;
6507 enum machine_mode compute_mode;
6509 /* Loop until we find something we can't simplify. */
6512 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
6513 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
6515 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
6516 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
6517 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
6519 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
6520 && CONST_INT_P (XEXP (SET_DEST (x), 1)))
6522 inner = XEXP (SET_DEST (x), 0);
6523 len = INTVAL (XEXP (SET_DEST (x), 1));
6524 pos = XEXP (SET_DEST (x), 2);
6526 /* A constant position should stay within the width of INNER. */
6527 if (CONST_INT_P (pos)
6528 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
6531 if (BITS_BIG_ENDIAN)
6533 if (CONST_INT_P (pos))
6534 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
6536 else if (GET_CODE (pos) == MINUS
6537 && CONST_INT_P (XEXP (pos, 1))
6538 && (INTVAL (XEXP (pos, 1))
6539 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
6540 /* If position is ADJUST - X, new position is X. */
6541 pos = XEXP (pos, 0);
6543 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
6544 GEN_INT (GET_MODE_BITSIZE (
6551 /* A SUBREG between two modes that occupy the same numbers of words
6552 can be done by moving the SUBREG to the source. */
6553 else if (GET_CODE (SET_DEST (x)) == SUBREG
6554 /* We need SUBREGs to compute nonzero_bits properly. */
6555 && nonzero_sign_valid
6556 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
6557 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
6558 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
6559 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
6561 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
6563 (GET_MODE (SUBREG_REG (SET_DEST (x))),
6570 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6571 inner = SUBREG_REG (inner);
6573 compute_mode = GET_MODE (inner);
6575 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6576 if (! SCALAR_INT_MODE_P (compute_mode))
6578 enum machine_mode imode;
6580 /* Don't do anything for vector or complex integral types. */
6581 if (! FLOAT_MODE_P (compute_mode))
6584 /* Try to find an integral mode to pun with. */
6585 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
6586 if (imode == BLKmode)
6589 compute_mode = imode;
6590 inner = gen_lowpart (imode, inner);
6593 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6594 if (len >= HOST_BITS_PER_WIDE_INT)
6597 /* Now compute the equivalent expression. Make a copy of INNER
6598 for the SET_DEST in case it is a MEM into which we will substitute;
6599 we don't want shared RTL in that case. */
6600 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
6601 cleared = simplify_gen_binary (AND, compute_mode,
6602 simplify_gen_unary (NOT, compute_mode,
6603 simplify_gen_binary (ASHIFT,
6608 masked = simplify_gen_binary (ASHIFT, compute_mode,
6609 simplify_gen_binary (
6611 gen_lowpart (compute_mode, SET_SRC (x)),
6615 x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
6616 simplify_gen_binary (IOR, compute_mode,
6623 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6624 it is an RTX that represents a variable starting position; otherwise,
6625 POS is the (constant) starting bit position (counted from the LSB).
6627 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6630 IN_DEST is nonzero if this is a reference in the destination of a
6631 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6632 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6635 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6636 ZERO_EXTRACT should be built even for bits starting at bit 0.
6638 MODE is the desired mode of the result (if IN_DEST == 0).
6640 The result is an RTX for the extraction or NULL_RTX if the target
6644 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
6645 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
6646 int in_dest, int in_compare)
6648 /* This mode describes the size of the storage area
6649 to fetch the overall value from. Within that, we
6650 ignore the POS lowest bits, etc. */
6651 enum machine_mode is_mode = GET_MODE (inner);
6652 enum machine_mode inner_mode;
6653 enum machine_mode wanted_inner_mode;
6654 enum machine_mode wanted_inner_reg_mode = word_mode;
6655 enum machine_mode pos_mode = word_mode;
6656 enum machine_mode extraction_mode = word_mode;
6657 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
6659 rtx orig_pos_rtx = pos_rtx;
6660 HOST_WIDE_INT orig_pos;
6662 if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6664 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6665 consider just the QI as the memory to extract from.
6666 The subreg adds or removes high bits; its mode is
6667 irrelevant to the meaning of this extraction,
6668 since POS and LEN count from the lsb. */
6669 if (MEM_P (SUBREG_REG (inner)))
6670 is_mode = GET_MODE (SUBREG_REG (inner));
6671 inner = SUBREG_REG (inner);
6673 else if (GET_CODE (inner) == ASHIFT
6674 && CONST_INT_P (XEXP (inner, 1))
6675 && pos_rtx == 0 && pos == 0
6676 && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
6678 /* We're extracting the least significant bits of an rtx
6679 (ashift X (const_int C)), where LEN > C. Extract the
6680 least significant (LEN - C) bits of X, giving an rtx
6681 whose mode is MODE, then shift it left C times. */
6682 new_rtx = make_extraction (mode, XEXP (inner, 0),
6683 0, 0, len - INTVAL (XEXP (inner, 1)),
6684 unsignedp, in_dest, in_compare);
6686 return gen_rtx_ASHIFT (mode, new_rtx, XEXP (inner, 1));
6689 inner_mode = GET_MODE (inner);
6691 if (pos_rtx && CONST_INT_P (pos_rtx))
6692 pos = INTVAL (pos_rtx), pos_rtx = 0;
6694 /* See if this can be done without an extraction. We never can if the
6695 width of the field is not the same as that of some integer mode. For
6696 registers, we can only avoid the extraction if the position is at the
6697 low-order bit and this is either not in the destination or we have the
6698 appropriate STRICT_LOW_PART operation available.
6700 For MEM, we can avoid an extract if the field starts on an appropriate
6701 boundary and we can change the mode of the memory reference. */
6703 if (tmode != BLKmode
6704 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
6706 && (inner_mode == tmode
6708 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
6709 GET_MODE_BITSIZE (inner_mode))
6710 || reg_truncated_to_mode (tmode, inner))
6713 && have_insn_for (STRICT_LOW_PART, tmode))))
6714 || (MEM_P (inner) && pos_rtx == 0
6716 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
6717 : BITS_PER_UNIT)) == 0
6718 /* We can't do this if we are widening INNER_MODE (it
6719 may not be aligned, for one thing). */
6720 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
6721 && (inner_mode == tmode
6722 || (! mode_dependent_address_p (XEXP (inner, 0))
6723 && ! MEM_VOLATILE_P (inner))))))
6725 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6726 field. If the original and current mode are the same, we need not
6727 adjust the offset. Otherwise, we do if bytes big endian.
6729 If INNER is not a MEM, get a piece consisting of just the field
6730 of interest (in this case POS % BITS_PER_WORD must be 0). */
6734 HOST_WIDE_INT offset;
6736 /* POS counts from lsb, but make OFFSET count in memory order. */
6737 if (BYTES_BIG_ENDIAN)
6738 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6740 offset = pos / BITS_PER_UNIT;
6742 new_rtx = adjust_address_nv (inner, tmode, offset);
6744 else if (REG_P (inner))
6746 if (tmode != inner_mode)
6748 /* We can't call gen_lowpart in a DEST since we
6749 always want a SUBREG (see below) and it would sometimes
6750 return a new hard register. */
6753 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6755 if (WORDS_BIG_ENDIAN
6756 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6757 final_word = ((GET_MODE_SIZE (inner_mode)
6758 - GET_MODE_SIZE (tmode))
6759 / UNITS_PER_WORD) - final_word;
6761 final_word *= UNITS_PER_WORD;
6762 if (BYTES_BIG_ENDIAN &&
6763 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6764 final_word += (GET_MODE_SIZE (inner_mode)
6765 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6767 /* Avoid creating invalid subregs, for example when
6768 simplifying (x>>32)&255. */
6769 if (!validate_subreg (tmode, inner_mode, inner, final_word))
6772 new_rtx = gen_rtx_SUBREG (tmode, inner, final_word);
6775 new_rtx = gen_lowpart (tmode, inner);
6781 new_rtx = force_to_mode (inner, tmode,
6782 len >= HOST_BITS_PER_WIDE_INT
6783 ? ~(unsigned HOST_WIDE_INT) 0
6784 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6787 /* If this extraction is going into the destination of a SET,
6788 make a STRICT_LOW_PART unless we made a MEM. */
6791 return (MEM_P (new_rtx) ? new_rtx
6792 : (GET_CODE (new_rtx) != SUBREG
6793 ? gen_rtx_CLOBBER (tmode, const0_rtx)
6794 : gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx)));
6799 if (CONST_INT_P (new_rtx))
6800 return gen_int_mode (INTVAL (new_rtx), mode);
6802 /* If we know that no extraneous bits are set, and that the high
6803 bit is not set, convert the extraction to the cheaper of
6804 sign and zero extension, that are equivalent in these cases. */
6805 if (flag_expensive_optimizations
6806 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6807 && ((nonzero_bits (new_rtx, tmode)
6808 & ~(((unsigned HOST_WIDE_INT)
6809 GET_MODE_MASK (tmode))
6813 rtx temp = gen_rtx_ZERO_EXTEND (mode, new_rtx);
6814 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new_rtx);
6816 /* Prefer ZERO_EXTENSION, since it gives more information to
6818 if (rtx_cost (temp, SET, optimize_this_for_speed_p)
6819 <= rtx_cost (temp1, SET, optimize_this_for_speed_p))
6824 /* Otherwise, sign- or zero-extend unless we already are in the
6827 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6831 /* Unless this is a COMPARE or we have a funny memory reference,
6832 don't do anything with zero-extending field extracts starting at
6833 the low-order bit since they are simple AND operations. */
6834 if (pos_rtx == 0 && pos == 0 && ! in_dest
6835 && ! in_compare && unsignedp)
6838 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
6839 if the position is not a constant and the length is not 1. In all
6840 other cases, we would only be going outside our object in cases when
6841 an original shift would have been undefined. */
6843 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6844 || (pos_rtx != 0 && len != 1)))
6847 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6848 and the mode for the result. */
6849 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6851 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6852 pos_mode = mode_for_extraction (EP_insv, 2);
6853 extraction_mode = mode_for_extraction (EP_insv, 3);
6856 if (! in_dest && unsignedp
6857 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6859 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6860 pos_mode = mode_for_extraction (EP_extzv, 3);
6861 extraction_mode = mode_for_extraction (EP_extzv, 0);
6864 if (! in_dest && ! unsignedp
6865 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6867 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6868 pos_mode = mode_for_extraction (EP_extv, 3);
6869 extraction_mode = mode_for_extraction (EP_extv, 0);
6872 /* Never narrow an object, since that might not be safe. */
6874 if (mode != VOIDmode
6875 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6876 extraction_mode = mode;
6878 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6879 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6880 pos_mode = GET_MODE (pos_rtx);
6882 /* If this is not from memory, the desired mode is the preferred mode
6883 for an extraction pattern's first input operand, or word_mode if there
6886 wanted_inner_mode = wanted_inner_reg_mode;
6889 /* Be careful not to go beyond the extracted object and maintain the
6890 natural alignment of the memory. */
6891 wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
6892 while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
6893 > GET_MODE_BITSIZE (wanted_inner_mode))
6895 wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
6896 gcc_assert (wanted_inner_mode != VOIDmode);
6899 /* If we have to change the mode of memory and cannot, the desired mode
6900 is EXTRACTION_MODE. */
6901 if (inner_mode != wanted_inner_mode
6902 && (mode_dependent_address_p (XEXP (inner, 0))
6903 || MEM_VOLATILE_P (inner)
6905 wanted_inner_mode = extraction_mode;
6910 if (BITS_BIG_ENDIAN)
6912 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6913 BITS_BIG_ENDIAN style. If position is constant, compute new
6914 position. Otherwise, build subtraction.
6915 Note that POS is relative to the mode of the original argument.
6916 If it's a MEM we need to recompute POS relative to that.
6917 However, if we're extracting from (or inserting into) a register,
6918 we want to recompute POS relative to wanted_inner_mode. */
6919 int width = (MEM_P (inner)
6920 ? GET_MODE_BITSIZE (is_mode)
6921 : GET_MODE_BITSIZE (wanted_inner_mode));
6924 pos = width - len - pos;
6927 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6928 /* POS may be less than 0 now, but we check for that below.
6929 Note that it can only be less than 0 if !MEM_P (inner). */
6932 /* If INNER has a wider mode, and this is a constant extraction, try to
6933 make it smaller and adjust the byte to point to the byte containing
6935 if (wanted_inner_mode != VOIDmode
6936 && inner_mode != wanted_inner_mode
6938 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6940 && ! mode_dependent_address_p (XEXP (inner, 0))
6941 && ! MEM_VOLATILE_P (inner))
6945 /* The computations below will be correct if the machine is big
6946 endian in both bits and bytes or little endian in bits and bytes.
6947 If it is mixed, we must adjust. */
6949 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6950 adjust OFFSET to compensate. */
6951 if (BYTES_BIG_ENDIAN
6952 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6953 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6955 /* We can now move to the desired byte. */
6956 offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
6957 * GET_MODE_SIZE (wanted_inner_mode);
6958 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6960 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6961 && is_mode != wanted_inner_mode)
6962 offset = (GET_MODE_SIZE (is_mode)
6963 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6965 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6968 /* If INNER is not memory, get it into the proper mode. If we are changing
6969 its mode, POS must be a constant and smaller than the size of the new
6971 else if (!MEM_P (inner))
6973 /* On the LHS, don't create paradoxical subregs implicitely truncating
6974 the register unless TRULY_NOOP_TRUNCATION. */
6976 && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE (inner)),
6977 GET_MODE_BITSIZE (wanted_inner_mode)))
6980 if (GET_MODE (inner) != wanted_inner_mode
6982 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6988 inner = force_to_mode (inner, wanted_inner_mode,
6990 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6991 ? ~(unsigned HOST_WIDE_INT) 0
6992 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6997 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6998 have to zero extend. Otherwise, we can just use a SUBREG. */
7000 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
7002 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
7004 /* If we know that no extraneous bits are set, and that the high
7005 bit is not set, convert extraction to cheaper one - either
7006 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7008 if (flag_expensive_optimizations
7009 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
7010 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
7011 & ~(((unsigned HOST_WIDE_INT)
7012 GET_MODE_MASK (GET_MODE (pos_rtx)))
7016 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
7018 /* Prefer ZERO_EXTENSION, since it gives more information to
7020 if (rtx_cost (temp1, SET, optimize_this_for_speed_p)
7021 < rtx_cost (temp, SET, optimize_this_for_speed_p))
7026 else if (pos_rtx != 0
7027 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
7028 pos_rtx = gen_lowpart (pos_mode, pos_rtx);
7030 /* Make POS_RTX unless we already have it and it is correct. If we don't
7031 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7033 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
7034 pos_rtx = orig_pos_rtx;
7036 else if (pos_rtx == 0)
7037 pos_rtx = GEN_INT (pos);
7039 /* Make the required operation. See if we can use existing rtx. */
7040 new_rtx = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
7041 extraction_mode, inner, GEN_INT (len), pos_rtx);
7043 new_rtx = gen_lowpart (mode, new_rtx);
7048 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7049 with any other operations in X. Return X without that shift if so. */
7052 extract_left_shift (rtx x, int count)
7054 enum rtx_code code = GET_CODE (x);
7055 enum machine_mode mode = GET_MODE (x);
7061 /* This is the shift itself. If it is wide enough, we will return
7062 either the value being shifted if the shift count is equal to
7063 COUNT or a shift for the difference. */
7064 if (CONST_INT_P (XEXP (x, 1))
7065 && INTVAL (XEXP (x, 1)) >= count)
7066 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
7067 INTVAL (XEXP (x, 1)) - count);
7071 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7072 return simplify_gen_unary (code, mode, tem, mode);
7076 case PLUS: case IOR: case XOR: case AND:
7077 /* If we can safely shift this constant and we find the inner shift,
7078 make a new operation. */
7079 if (CONST_INT_P (XEXP (x, 1))
7080 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
7081 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7082 return simplify_gen_binary (code, mode, tem,
7083 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
7094 /* Look at the expression rooted at X. Look for expressions
7095 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7096 Form these expressions.
7098 Return the new rtx, usually just X.
7100 Also, for machines like the VAX that don't have logical shift insns,
7101 try to convert logical to arithmetic shift operations in cases where
7102 they are equivalent. This undoes the canonicalizations to logical
7103 shifts done elsewhere.
7105 We try, as much as possible, to re-use rtl expressions to save memory.
7107 IN_CODE says what kind of expression we are processing. Normally, it is
7108 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
7109 being kludges), it is MEM. When processing the arguments of a comparison
7110 or a COMPARE against zero, it is COMPARE. */
7113 make_compound_operation (rtx x, enum rtx_code in_code)
7115 enum rtx_code code = GET_CODE (x);
7116 enum machine_mode mode = GET_MODE (x);
7117 int mode_width = GET_MODE_BITSIZE (mode);
7119 enum rtx_code next_code;
7125 /* Select the code to be used in recursive calls. Once we are inside an
7126 address, we stay there. If we have a comparison, set to COMPARE,
7127 but once inside, go back to our default of SET. */
7129 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
7130 : ((code == COMPARE || COMPARISON_P (x))
7131 && XEXP (x, 1) == const0_rtx) ? COMPARE
7132 : in_code == COMPARE ? SET : in_code);
7134 /* Process depending on the code of this operation. If NEW is set
7135 nonzero, it will be returned. */
7140 /* Convert shifts by constants into multiplications if inside
7142 if (in_code == MEM && CONST_INT_P (XEXP (x, 1))
7143 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7144 && INTVAL (XEXP (x, 1)) >= 0)
7146 new_rtx = make_compound_operation (XEXP (x, 0), next_code);
7147 new_rtx = gen_rtx_MULT (mode, new_rtx,
7148 GEN_INT ((HOST_WIDE_INT) 1
7149 << INTVAL (XEXP (x, 1))));
7154 /* If the second operand is not a constant, we can't do anything
7156 if (!CONST_INT_P (XEXP (x, 1)))
7159 /* If the constant is a power of two minus one and the first operand
7160 is a logical right shift, make an extraction. */
7161 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7162 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
7164 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7165 new_rtx = make_extraction (mode, new_rtx, 0, XEXP (XEXP (x, 0), 1), i, 1,
7166 0, in_code == COMPARE);
7169 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7170 else if (GET_CODE (XEXP (x, 0)) == SUBREG
7171 && subreg_lowpart_p (XEXP (x, 0))
7172 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
7173 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
7175 new_rtx = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
7177 new_rtx = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new_rtx, 0,
7178 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
7179 0, in_code == COMPARE);
7181 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7182 else if ((GET_CODE (XEXP (x, 0)) == XOR
7183 || GET_CODE (XEXP (x, 0)) == IOR)
7184 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
7185 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
7186 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
7188 /* Apply the distributive law, and then try to make extractions. */
7189 new_rtx = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
7190 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
7192 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
7194 new_rtx = make_compound_operation (new_rtx, in_code);
7197 /* If we are have (and (rotate X C) M) and C is larger than the number
7198 of bits in M, this is an extraction. */
7200 else if (GET_CODE (XEXP (x, 0)) == ROTATE
7201 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7202 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
7203 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
7205 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7206 new_rtx = make_extraction (mode, new_rtx,
7207 (GET_MODE_BITSIZE (mode)
7208 - INTVAL (XEXP (XEXP (x, 0), 1))),
7209 NULL_RTX, i, 1, 0, in_code == COMPARE);
7212 /* On machines without logical shifts, if the operand of the AND is
7213 a logical shift and our mask turns off all the propagated sign
7214 bits, we can replace the logical shift with an arithmetic shift. */
7215 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7216 && !have_insn_for (LSHIFTRT, mode)
7217 && have_insn_for (ASHIFTRT, mode)
7218 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7219 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7220 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7221 && mode_width <= HOST_BITS_PER_WIDE_INT)
7223 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
7225 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
7226 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
7228 gen_rtx_ASHIFTRT (mode,
7229 make_compound_operation
7230 (XEXP (XEXP (x, 0), 0), next_code),
7231 XEXP (XEXP (x, 0), 1)));
7234 /* If the constant is one less than a power of two, this might be
7235 representable by an extraction even if no shift is present.
7236 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7237 we are in a COMPARE. */
7238 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
7239 new_rtx = make_extraction (mode,
7240 make_compound_operation (XEXP (x, 0),
7242 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
7244 /* If we are in a comparison and this is an AND with a power of two,
7245 convert this into the appropriate bit extract. */
7246 else if (in_code == COMPARE
7247 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
7248 new_rtx = make_extraction (mode,
7249 make_compound_operation (XEXP (x, 0),
7251 i, NULL_RTX, 1, 1, 0, 1);
7256 /* If the sign bit is known to be zero, replace this with an
7257 arithmetic shift. */
7258 if (have_insn_for (ASHIFTRT, mode)
7259 && ! have_insn_for (LSHIFTRT, mode)
7260 && mode_width <= HOST_BITS_PER_WIDE_INT
7261 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
7263 new_rtx = gen_rtx_ASHIFTRT (mode,
7264 make_compound_operation (XEXP (x, 0),
7270 /* ... fall through ... */
7276 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7277 this is a SIGN_EXTRACT. */
7278 if (CONST_INT_P (rhs)
7279 && GET_CODE (lhs) == ASHIFT
7280 && CONST_INT_P (XEXP (lhs, 1))
7281 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))
7282 && INTVAL (rhs) < mode_width)
7284 new_rtx = make_compound_operation (XEXP (lhs, 0), next_code);
7285 new_rtx = make_extraction (mode, new_rtx,
7286 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
7287 NULL_RTX, mode_width - INTVAL (rhs),
7288 code == LSHIFTRT, 0, in_code == COMPARE);
7292 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7293 If so, try to merge the shifts into a SIGN_EXTEND. We could
7294 also do this for some cases of SIGN_EXTRACT, but it doesn't
7295 seem worth the effort; the case checked for occurs on Alpha. */
7298 && ! (GET_CODE (lhs) == SUBREG
7299 && (OBJECT_P (SUBREG_REG (lhs))))
7300 && CONST_INT_P (rhs)
7301 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
7302 && INTVAL (rhs) < mode_width
7303 && (new_rtx = extract_left_shift (lhs, INTVAL (rhs))) != 0)
7304 new_rtx = make_extraction (mode, make_compound_operation (new_rtx, next_code),
7305 0, NULL_RTX, mode_width - INTVAL (rhs),
7306 code == LSHIFTRT, 0, in_code == COMPARE);
7311 /* Call ourselves recursively on the inner expression. If we are
7312 narrowing the object and it has a different RTL code from
7313 what it originally did, do this SUBREG as a force_to_mode. */
7315 tem = make_compound_operation (SUBREG_REG (x), in_code);
7319 simplified = simplify_subreg (GET_MODE (x), tem, GET_MODE (tem),
7325 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
7326 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
7327 && subreg_lowpart_p (x))
7329 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
7332 /* If we have something other than a SUBREG, we might have
7333 done an expansion, so rerun ourselves. */
7334 if (GET_CODE (newer) != SUBREG)
7335 newer = make_compound_operation (newer, in_code);
7337 /* force_to_mode can expand compounds. If it just re-expanded the
7338 compound use gen_lowpart instead to convert to the desired
7340 if (rtx_equal_p (newer, x))
7341 return gen_lowpart (GET_MODE (x), tem);
7357 x = gen_lowpart (mode, new_rtx);
7358 code = GET_CODE (x);
7361 /* Now recursively process each operand of this operation. */
7362 fmt = GET_RTX_FORMAT (code);
7363 for (i = 0; i < GET_RTX_LENGTH (code); i++)
7366 new_rtx = make_compound_operation (XEXP (x, i), next_code);
7367 SUBST (XEXP (x, i), new_rtx);
7369 else if (fmt[i] == 'E')
7370 for (j = 0; j < XVECLEN (x, i); j++)
7372 new_rtx = make_compound_operation (XVECEXP (x, i, j), next_code);
7373 SUBST (XVECEXP (x, i, j), new_rtx);
7376 /* If this is a commutative operation, the changes to the operands
7377 may have made it noncanonical. */
7378 if (COMMUTATIVE_ARITH_P (x)
7379 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
7382 SUBST (XEXP (x, 0), XEXP (x, 1));
7383 SUBST (XEXP (x, 1), tem);
7389 /* Given M see if it is a value that would select a field of bits
7390 within an item, but not the entire word. Return -1 if not.
7391 Otherwise, return the starting position of the field, where 0 is the
7394 *PLEN is set to the length of the field. */
7397 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
7399 /* Get the bit number of the first 1 bit from the right, -1 if none. */
7400 int pos = exact_log2 (m & -m);
7404 /* Now shift off the low-order zero bits and see if we have a
7405 power of two minus 1. */
7406 len = exact_log2 ((m >> pos) + 1);
7415 /* If X refers to a register that equals REG in value, replace these
7416 references with REG. */
7418 canon_reg_for_combine (rtx x, rtx reg)
7425 enum rtx_code code = GET_CODE (x);
7426 switch (GET_RTX_CLASS (code))
7429 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7430 if (op0 != XEXP (x, 0))
7431 return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
7436 case RTX_COMM_ARITH:
7437 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7438 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7439 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7440 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
7444 case RTX_COMM_COMPARE:
7445 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7446 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7447 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7448 return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
7449 GET_MODE (op0), op0, op1);
7453 case RTX_BITFIELD_OPS:
7454 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7455 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7456 op2 = canon_reg_for_combine (XEXP (x, 2), reg);
7457 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
7458 return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
7459 GET_MODE (op0), op0, op1, op2);
7464 if (rtx_equal_p (get_last_value (reg), x)
7465 || rtx_equal_p (reg, get_last_value (x)))
7474 fmt = GET_RTX_FORMAT (code);
7476 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7479 rtx op = canon_reg_for_combine (XEXP (x, i), reg);
7480 if (op != XEXP (x, i))
7490 else if (fmt[i] == 'E')
7493 for (j = 0; j < XVECLEN (x, i); j++)
7495 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
7496 if (op != XVECEXP (x, i, j))
7503 XVECEXP (x, i, j) = op;
7514 /* Return X converted to MODE. If the value is already truncated to
7515 MODE we can just return a subreg even though in the general case we
7516 would need an explicit truncation. */
7519 gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
7521 if (!CONST_INT_P (x)
7522 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
7523 && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
7524 GET_MODE_BITSIZE (GET_MODE (x)))
7525 && !(REG_P (x) && reg_truncated_to_mode (mode, x)))
7527 /* Bit-cast X into an integer mode. */
7528 if (!SCALAR_INT_MODE_P (GET_MODE (x)))
7529 x = gen_lowpart (int_mode_for_mode (GET_MODE (x)), x);
7530 x = simplify_gen_unary (TRUNCATE, int_mode_for_mode (mode),
7534 return gen_lowpart (mode, x);
7537 /* See if X can be simplified knowing that we will only refer to it in
7538 MODE and will only refer to those bits that are nonzero in MASK.
7539 If other bits are being computed or if masking operations are done
7540 that select a superset of the bits in MASK, they can sometimes be
7543 Return a possibly simplified expression, but always convert X to
7544 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
7546 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
7547 are all off in X. This is used when X will be complemented, by either
7548 NOT, NEG, or XOR. */
7551 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
7554 enum rtx_code code = GET_CODE (x);
7555 int next_select = just_select || code == XOR || code == NOT || code == NEG;
7556 enum machine_mode op_mode;
7557 unsigned HOST_WIDE_INT fuller_mask, nonzero;
7560 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
7561 code below will do the wrong thing since the mode of such an
7562 expression is VOIDmode.
7564 Also do nothing if X is a CLOBBER; this can happen if X was
7565 the return value from a call to gen_lowpart. */
7566 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
7569 /* We want to perform the operation is its present mode unless we know
7570 that the operation is valid in MODE, in which case we do the operation
7572 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
7573 && have_insn_for (code, mode))
7574 ? mode : GET_MODE (x));
7576 /* It is not valid to do a right-shift in a narrower mode
7577 than the one it came in with. */
7578 if ((code == LSHIFTRT || code == ASHIFTRT)
7579 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
7580 op_mode = GET_MODE (x);
7582 /* Truncate MASK to fit OP_MODE. */
7584 mask &= GET_MODE_MASK (op_mode);
7586 /* When we have an arithmetic operation, or a shift whose count we
7587 do not know, we need to assume that all bits up to the highest-order
7588 bit in MASK will be needed. This is how we form such a mask. */
7589 if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
7590 fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
7592 fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
7595 /* Determine what bits of X are guaranteed to be (non)zero. */
7596 nonzero = nonzero_bits (x, mode);
7598 /* If none of the bits in X are needed, return a zero. */
7599 if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
7602 /* If X is a CONST_INT, return a new one. Do this here since the
7603 test below will fail. */
7604 if (CONST_INT_P (x))
7606 if (SCALAR_INT_MODE_P (mode))
7607 return gen_int_mode (INTVAL (x) & mask, mode);
7610 x = GEN_INT (INTVAL (x) & mask);
7611 return gen_lowpart_common (mode, x);
7615 /* If X is narrower than MODE and we want all the bits in X's mode, just
7616 get X in the proper mode. */
7617 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
7618 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
7619 return gen_lowpart (mode, x);
7621 /* We can ignore the effect of a SUBREG if it narrows the mode or
7622 if the constant masks to zero all the bits the mode doesn't have. */
7623 if (GET_CODE (x) == SUBREG
7624 && subreg_lowpart_p (x)
7625 && ((GET_MODE_SIZE (GET_MODE (x))
7626 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7628 & GET_MODE_MASK (GET_MODE (x))
7629 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
7630 return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
7632 /* The arithmetic simplifications here only work for scalar integer modes. */
7633 if (!SCALAR_INT_MODE_P (mode) || !SCALAR_INT_MODE_P (GET_MODE (x)))
7634 return gen_lowpart_or_truncate (mode, x);
7639 /* If X is a (clobber (const_int)), return it since we know we are
7640 generating something that won't match. */
7647 x = expand_compound_operation (x);
7648 if (GET_CODE (x) != code)
7649 return force_to_mode (x, mode, mask, next_select);
7653 /* Similarly for a truncate. */
7654 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7657 /* If this is an AND with a constant, convert it into an AND
7658 whose constant is the AND of that constant with MASK. If it
7659 remains an AND of MASK, delete it since it is redundant. */
7661 if (CONST_INT_P (XEXP (x, 1)))
7663 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
7664 mask & INTVAL (XEXP (x, 1)));
7666 /* If X is still an AND, see if it is an AND with a mask that
7667 is just some low-order bits. If so, and it is MASK, we don't
7670 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
7671 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
7675 /* If it remains an AND, try making another AND with the bits
7676 in the mode mask that aren't in MASK turned on. If the
7677 constant in the AND is wide enough, this might make a
7678 cheaper constant. */
7680 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
7681 && GET_MODE_MASK (GET_MODE (x)) != mask
7682 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
7684 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
7685 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
7686 int width = GET_MODE_BITSIZE (GET_MODE (x));
7689 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
7690 number, sign extend it. */
7691 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
7692 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7693 cval |= (HOST_WIDE_INT) -1 << width;
7695 y = simplify_gen_binary (AND, GET_MODE (x),
7696 XEXP (x, 0), GEN_INT (cval));
7697 if (rtx_cost (y, SET, optimize_this_for_speed_p)
7698 < rtx_cost (x, SET, optimize_this_for_speed_p))
7708 /* In (and (plus FOO C1) M), if M is a mask that just turns off
7709 low-order bits (as in an alignment operation) and FOO is already
7710 aligned to that boundary, mask C1 to that boundary as well.
7711 This may eliminate that PLUS and, later, the AND. */
7714 unsigned int width = GET_MODE_BITSIZE (mode);
7715 unsigned HOST_WIDE_INT smask = mask;
7717 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
7718 number, sign extend it. */
7720 if (width < HOST_BITS_PER_WIDE_INT
7721 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7722 smask |= (HOST_WIDE_INT) -1 << width;
7724 if (CONST_INT_P (XEXP (x, 1))
7725 && exact_log2 (- smask) >= 0
7726 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
7727 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
7728 return force_to_mode (plus_constant (XEXP (x, 0),
7729 (INTVAL (XEXP (x, 1)) & smask)),
7730 mode, smask, next_select);
7733 /* ... fall through ... */
7736 /* For PLUS, MINUS and MULT, we need any bits less significant than the
7737 most significant bit in MASK since carries from those bits will
7738 affect the bits we are interested in. */
7743 /* If X is (minus C Y) where C's least set bit is larger than any bit
7744 in the mask, then we may replace with (neg Y). */
7745 if (CONST_INT_P (XEXP (x, 0))
7746 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
7747 & -INTVAL (XEXP (x, 0))))
7750 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
7752 return force_to_mode (x, mode, mask, next_select);
7755 /* Similarly, if C contains every bit in the fuller_mask, then we may
7756 replace with (not Y). */
7757 if (CONST_INT_P (XEXP (x, 0))
7758 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
7759 == INTVAL (XEXP (x, 0))))
7761 x = simplify_gen_unary (NOT, GET_MODE (x),
7762 XEXP (x, 1), GET_MODE (x));
7763 return force_to_mode (x, mode, mask, next_select);
7771 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7772 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7773 operation which may be a bitfield extraction. Ensure that the
7774 constant we form is not wider than the mode of X. */
7776 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7777 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7778 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7779 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7780 && CONST_INT_P (XEXP (x, 1))
7781 && ((INTVAL (XEXP (XEXP (x, 0), 1))
7782 + floor_log2 (INTVAL (XEXP (x, 1))))
7783 < GET_MODE_BITSIZE (GET_MODE (x)))
7784 && (INTVAL (XEXP (x, 1))
7785 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
7787 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
7788 << INTVAL (XEXP (XEXP (x, 0), 1)));
7789 temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
7790 XEXP (XEXP (x, 0), 0), temp);
7791 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
7792 XEXP (XEXP (x, 0), 1));
7793 return force_to_mode (x, mode, mask, next_select);
7797 /* For most binary operations, just propagate into the operation and
7798 change the mode if we have an operation of that mode. */
7800 op0 = force_to_mode (XEXP (x, 0), mode, mask, next_select);
7801 op1 = force_to_mode (XEXP (x, 1), mode, mask, next_select);
7803 /* If we ended up truncating both operands, truncate the result of the
7804 operation instead. */
7805 if (GET_CODE (op0) == TRUNCATE
7806 && GET_CODE (op1) == TRUNCATE)
7808 op0 = XEXP (op0, 0);
7809 op1 = XEXP (op1, 0);
7812 op0 = gen_lowpart_or_truncate (op_mode, op0);
7813 op1 = gen_lowpart_or_truncate (op_mode, op1);
7815 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7816 x = simplify_gen_binary (code, op_mode, op0, op1);
7820 /* For left shifts, do the same, but just for the first operand.
7821 However, we cannot do anything with shifts where we cannot
7822 guarantee that the counts are smaller than the size of the mode
7823 because such a count will have a different meaning in a
7826 if (! (CONST_INT_P (XEXP (x, 1))
7827 && INTVAL (XEXP (x, 1)) >= 0
7828 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
7829 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
7830 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
7831 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
7834 /* If the shift count is a constant and we can do arithmetic in
7835 the mode of the shift, refine which bits we need. Otherwise, use the
7836 conservative form of the mask. */
7837 if (CONST_INT_P (XEXP (x, 1))
7838 && INTVAL (XEXP (x, 1)) >= 0
7839 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
7840 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7841 mask >>= INTVAL (XEXP (x, 1));
7845 op0 = gen_lowpart_or_truncate (op_mode,
7846 force_to_mode (XEXP (x, 0), op_mode,
7847 mask, next_select));
7849 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7850 x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
7854 /* Here we can only do something if the shift count is a constant,
7855 this shift constant is valid for the host, and we can do arithmetic
7858 if (CONST_INT_P (XEXP (x, 1))
7859 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7860 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7862 rtx inner = XEXP (x, 0);
7863 unsigned HOST_WIDE_INT inner_mask;
7865 /* Select the mask of the bits we need for the shift operand. */
7866 inner_mask = mask << INTVAL (XEXP (x, 1));
7868 /* We can only change the mode of the shift if we can do arithmetic
7869 in the mode of the shift and INNER_MASK is no wider than the
7870 width of X's mode. */
7871 if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
7872 op_mode = GET_MODE (x);
7874 inner = force_to_mode (inner, op_mode, inner_mask, next_select);
7876 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7877 x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7880 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7881 shift and AND produces only copies of the sign bit (C2 is one less
7882 than a power of two), we can do this with just a shift. */
7884 if (GET_CODE (x) == LSHIFTRT
7885 && CONST_INT_P (XEXP (x, 1))
7886 /* The shift puts one of the sign bit copies in the least significant
7888 && ((INTVAL (XEXP (x, 1))
7889 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7890 >= GET_MODE_BITSIZE (GET_MODE (x)))
7891 && exact_log2 (mask + 1) >= 0
7892 /* Number of bits left after the shift must be more than the mask
7894 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7895 <= GET_MODE_BITSIZE (GET_MODE (x)))
7896 /* Must be more sign bit copies than the mask needs. */
7897 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7898 >= exact_log2 (mask + 1)))
7899 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7900 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7901 - exact_log2 (mask + 1)));
7906 /* If we are just looking for the sign bit, we don't need this shift at
7907 all, even if it has a variable count. */
7908 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7909 && (mask == ((unsigned HOST_WIDE_INT) 1
7910 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7911 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7913 /* If this is a shift by a constant, get a mask that contains those bits
7914 that are not copies of the sign bit. We then have two cases: If
7915 MASK only includes those bits, this can be a logical shift, which may
7916 allow simplifications. If MASK is a single-bit field not within
7917 those bits, we are requesting a copy of the sign bit and hence can
7918 shift the sign bit to the appropriate location. */
7920 if (CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) >= 0
7921 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7925 /* If the considered data is wider than HOST_WIDE_INT, we can't
7926 represent a mask for all its bits in a single scalar.
7927 But we only care about the lower bits, so calculate these. */
7929 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7931 nonzero = ~(HOST_WIDE_INT) 0;
7933 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7934 is the number of bits a full-width mask would have set.
7935 We need only shift if these are fewer than nonzero can
7936 hold. If not, we must keep all bits set in nonzero. */
7938 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7939 < HOST_BITS_PER_WIDE_INT)
7940 nonzero >>= INTVAL (XEXP (x, 1))
7941 + HOST_BITS_PER_WIDE_INT
7942 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7946 nonzero = GET_MODE_MASK (GET_MODE (x));
7947 nonzero >>= INTVAL (XEXP (x, 1));
7950 if ((mask & ~nonzero) == 0)
7952 x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
7953 XEXP (x, 0), INTVAL (XEXP (x, 1)));
7954 if (GET_CODE (x) != ASHIFTRT)
7955 return force_to_mode (x, mode, mask, next_select);
7958 else if ((i = exact_log2 (mask)) >= 0)
7960 x = simplify_shift_const
7961 (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7962 GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7964 if (GET_CODE (x) != ASHIFTRT)
7965 return force_to_mode (x, mode, mask, next_select);
7969 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7970 even if the shift count isn't a constant. */
7972 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7973 XEXP (x, 0), XEXP (x, 1));
7977 /* If this is a zero- or sign-extension operation that just affects bits
7978 we don't care about, remove it. Be sure the call above returned
7979 something that is still a shift. */
7981 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7982 && CONST_INT_P (XEXP (x, 1))
7983 && INTVAL (XEXP (x, 1)) >= 0
7984 && (INTVAL (XEXP (x, 1))
7985 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7986 && GET_CODE (XEXP (x, 0)) == ASHIFT
7987 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
7988 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7995 /* If the shift count is constant and we can do computations
7996 in the mode of X, compute where the bits we care about are.
7997 Otherwise, we can't do anything. Don't change the mode of
7998 the shift or propagate MODE into the shift, though. */
7999 if (CONST_INT_P (XEXP (x, 1))
8000 && INTVAL (XEXP (x, 1)) >= 0)
8002 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
8003 GET_MODE (x), GEN_INT (mask),
8005 if (temp && CONST_INT_P (temp))
8007 force_to_mode (XEXP (x, 0), GET_MODE (x),
8008 INTVAL (temp), next_select));
8013 /* If we just want the low-order bit, the NEG isn't needed since it
8014 won't change the low-order bit. */
8016 return force_to_mode (XEXP (x, 0), mode, mask, just_select);
8018 /* We need any bits less significant than the most significant bit in
8019 MASK since carries from those bits will affect the bits we are
8025 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8026 same as the XOR case above. Ensure that the constant we form is not
8027 wider than the mode of X. */
8029 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8030 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8031 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8032 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
8033 < GET_MODE_BITSIZE (GET_MODE (x)))
8034 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
8036 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
8038 temp = simplify_gen_binary (XOR, GET_MODE (x),
8039 XEXP (XEXP (x, 0), 0), temp);
8040 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8041 temp, XEXP (XEXP (x, 0), 1));
8043 return force_to_mode (x, mode, mask, next_select);
8046 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8047 use the full mask inside the NOT. */
8051 op0 = gen_lowpart_or_truncate (op_mode,
8052 force_to_mode (XEXP (x, 0), mode, mask,
8054 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8055 x = simplify_gen_unary (code, op_mode, op0, op_mode);
8059 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8060 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8061 which is equal to STORE_FLAG_VALUE. */
8062 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
8063 && GET_MODE (XEXP (x, 0)) == mode
8064 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
8065 && (nonzero_bits (XEXP (x, 0), mode)
8066 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
8067 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8072 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8073 written in a narrower mode. We play it safe and do not do so. */
8076 gen_lowpart_or_truncate (GET_MODE (x),
8077 force_to_mode (XEXP (x, 1), mode,
8078 mask, next_select)));
8080 gen_lowpart_or_truncate (GET_MODE (x),
8081 force_to_mode (XEXP (x, 2), mode,
8082 mask, next_select)));
8089 /* Ensure we return a value of the proper mode. */
8090 return gen_lowpart_or_truncate (mode, x);
8093 /* Return nonzero if X is an expression that has one of two values depending on
8094 whether some other value is zero or nonzero. In that case, we return the
8095 value that is being tested, *PTRUE is set to the value if the rtx being
8096 returned has a nonzero value, and *PFALSE is set to the other alternative.
8098 If we return zero, we set *PTRUE and *PFALSE to X. */
8101 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
8103 enum machine_mode mode = GET_MODE (x);
8104 enum rtx_code code = GET_CODE (x);
8105 rtx cond0, cond1, true0, true1, false0, false1;
8106 unsigned HOST_WIDE_INT nz;
8108 /* If we are comparing a value against zero, we are done. */
8109 if ((code == NE || code == EQ)
8110 && XEXP (x, 1) == const0_rtx)
8112 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
8113 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
8117 /* If this is a unary operation whose operand has one of two values, apply
8118 our opcode to compute those values. */
8119 else if (UNARY_P (x)
8120 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
8122 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
8123 *pfalse = simplify_gen_unary (code, mode, false0,
8124 GET_MODE (XEXP (x, 0)));
8128 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8129 make can't possibly match and would suppress other optimizations. */
8130 else if (code == COMPARE)
8133 /* If this is a binary operation, see if either side has only one of two
8134 values. If either one does or if both do and they are conditional on
8135 the same value, compute the new true and false values. */
8136 else if (BINARY_P (x))
8138 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
8139 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
8141 if ((cond0 != 0 || cond1 != 0)
8142 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
8144 /* If if_then_else_cond returned zero, then true/false are the
8145 same rtl. We must copy one of them to prevent invalid rtl
8148 true0 = copy_rtx (true0);
8149 else if (cond1 == 0)
8150 true1 = copy_rtx (true1);
8152 if (COMPARISON_P (x))
8154 *ptrue = simplify_gen_relational (code, mode, VOIDmode,
8156 *pfalse = simplify_gen_relational (code, mode, VOIDmode,
8161 *ptrue = simplify_gen_binary (code, mode, true0, true1);
8162 *pfalse = simplify_gen_binary (code, mode, false0, false1);
8165 return cond0 ? cond0 : cond1;
8168 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8169 operands is zero when the other is nonzero, and vice-versa,
8170 and STORE_FLAG_VALUE is 1 or -1. */
8172 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8173 && (code == PLUS || code == IOR || code == XOR || code == MINUS
8175 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8177 rtx op0 = XEXP (XEXP (x, 0), 1);
8178 rtx op1 = XEXP (XEXP (x, 1), 1);
8180 cond0 = XEXP (XEXP (x, 0), 0);
8181 cond1 = XEXP (XEXP (x, 1), 0);
8183 if (COMPARISON_P (cond0)
8184 && COMPARISON_P (cond1)
8185 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8186 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8187 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8188 || ((swap_condition (GET_CODE (cond0))
8189 == reversed_comparison_code (cond1, NULL))
8190 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8191 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8192 && ! side_effects_p (x))
8194 *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
8195 *pfalse = simplify_gen_binary (MULT, mode,
8197 ? simplify_gen_unary (NEG, mode,
8205 /* Similarly for MULT, AND and UMIN, except that for these the result
8207 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8208 && (code == MULT || code == AND || code == UMIN)
8209 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8211 cond0 = XEXP (XEXP (x, 0), 0);
8212 cond1 = XEXP (XEXP (x, 1), 0);
8214 if (COMPARISON_P (cond0)
8215 && COMPARISON_P (cond1)
8216 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8217 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8218 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8219 || ((swap_condition (GET_CODE (cond0))
8220 == reversed_comparison_code (cond1, NULL))
8221 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8222 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8223 && ! side_effects_p (x))
8225 *ptrue = *pfalse = const0_rtx;
8231 else if (code == IF_THEN_ELSE)
8233 /* If we have IF_THEN_ELSE already, extract the condition and
8234 canonicalize it if it is NE or EQ. */
8235 cond0 = XEXP (x, 0);
8236 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
8237 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
8238 return XEXP (cond0, 0);
8239 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
8241 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
8242 return XEXP (cond0, 0);
8248 /* If X is a SUBREG, we can narrow both the true and false values
8249 if the inner expression, if there is a condition. */
8250 else if (code == SUBREG
8251 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
8254 true0 = simplify_gen_subreg (mode, true0,
8255 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8256 false0 = simplify_gen_subreg (mode, false0,
8257 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8258 if (true0 && false0)
8266 /* If X is a constant, this isn't special and will cause confusions
8267 if we treat it as such. Likewise if it is equivalent to a constant. */
8268 else if (CONSTANT_P (x)
8269 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
8272 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8273 will be least confusing to the rest of the compiler. */
8274 else if (mode == BImode)
8276 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
8280 /* If X is known to be either 0 or -1, those are the true and
8281 false values when testing X. */
8282 else if (x == constm1_rtx || x == const0_rtx
8283 || (mode != VOIDmode
8284 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
8286 *ptrue = constm1_rtx, *pfalse = const0_rtx;
8290 /* Likewise for 0 or a single bit. */
8291 else if (SCALAR_INT_MODE_P (mode)
8292 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8293 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
8295 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
8299 /* Otherwise fail; show no condition with true and false values the same. */
8300 *ptrue = *pfalse = x;
8304 /* Return the value of expression X given the fact that condition COND
8305 is known to be true when applied to REG as its first operand and VAL
8306 as its second. X is known to not be shared and so can be modified in
8309 We only handle the simplest cases, and specifically those cases that
8310 arise with IF_THEN_ELSE expressions. */
8313 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
8315 enum rtx_code code = GET_CODE (x);
8320 if (side_effects_p (x))
8323 /* If either operand of the condition is a floating point value,
8324 then we have to avoid collapsing an EQ comparison. */
8326 && rtx_equal_p (x, reg)
8327 && ! FLOAT_MODE_P (GET_MODE (x))
8328 && ! FLOAT_MODE_P (GET_MODE (val)))
8331 if (cond == UNEQ && rtx_equal_p (x, reg))
8334 /* If X is (abs REG) and we know something about REG's relationship
8335 with zero, we may be able to simplify this. */
8337 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
8340 case GE: case GT: case EQ:
8343 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
8345 GET_MODE (XEXP (x, 0)));
8350 /* The only other cases we handle are MIN, MAX, and comparisons if the
8351 operands are the same as REG and VAL. */
8353 else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
8355 if (rtx_equal_p (XEXP (x, 0), val))
8356 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
8358 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
8360 if (COMPARISON_P (x))
8362 if (comparison_dominates_p (cond, code))
8363 return const_true_rtx;
8365 code = reversed_comparison_code (x, NULL);
8367 && comparison_dominates_p (cond, code))
8372 else if (code == SMAX || code == SMIN
8373 || code == UMIN || code == UMAX)
8375 int unsignedp = (code == UMIN || code == UMAX);
8377 /* Do not reverse the condition when it is NE or EQ.
8378 This is because we cannot conclude anything about
8379 the value of 'SMAX (x, y)' when x is not equal to y,
8380 but we can when x equals y. */
8381 if ((code == SMAX || code == UMAX)
8382 && ! (cond == EQ || cond == NE))
8383 cond = reverse_condition (cond);
8388 return unsignedp ? x : XEXP (x, 1);
8390 return unsignedp ? x : XEXP (x, 0);
8392 return unsignedp ? XEXP (x, 1) : x;
8394 return unsignedp ? XEXP (x, 0) : x;
8401 else if (code == SUBREG)
8403 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
8404 rtx new_rtx, r = known_cond (SUBREG_REG (x), cond, reg, val);
8406 if (SUBREG_REG (x) != r)
8408 /* We must simplify subreg here, before we lose track of the
8409 original inner_mode. */
8410 new_rtx = simplify_subreg (GET_MODE (x), r,
8411 inner_mode, SUBREG_BYTE (x));
8415 SUBST (SUBREG_REG (x), r);
8420 /* We don't have to handle SIGN_EXTEND here, because even in the
8421 case of replacing something with a modeless CONST_INT, a
8422 CONST_INT is already (supposed to be) a valid sign extension for
8423 its narrower mode, which implies it's already properly
8424 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
8425 story is different. */
8426 else if (code == ZERO_EXTEND)
8428 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
8429 rtx new_rtx, r = known_cond (XEXP (x, 0), cond, reg, val);
8431 if (XEXP (x, 0) != r)
8433 /* We must simplify the zero_extend here, before we lose
8434 track of the original inner_mode. */
8435 new_rtx = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
8440 SUBST (XEXP (x, 0), r);
8446 fmt = GET_RTX_FORMAT (code);
8447 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8450 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
8451 else if (fmt[i] == 'E')
8452 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8453 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
8460 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8461 assignment as a field assignment. */
8464 rtx_equal_for_field_assignment_p (rtx x, rtx y)
8466 if (x == y || rtx_equal_p (x, y))
8469 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
8472 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8473 Note that all SUBREGs of MEM are paradoxical; otherwise they
8474 would have been rewritten. */
8475 if (MEM_P (x) && GET_CODE (y) == SUBREG
8476 && MEM_P (SUBREG_REG (y))
8477 && rtx_equal_p (SUBREG_REG (y),
8478 gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
8481 if (MEM_P (y) && GET_CODE (x) == SUBREG
8482 && MEM_P (SUBREG_REG (x))
8483 && rtx_equal_p (SUBREG_REG (x),
8484 gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
8487 /* We used to see if get_last_value of X and Y were the same but that's
8488 not correct. In one direction, we'll cause the assignment to have
8489 the wrong destination and in the case, we'll import a register into this
8490 insn that might have already have been dead. So fail if none of the
8491 above cases are true. */
8495 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8496 Return that assignment if so.
8498 We only handle the most common cases. */
8501 make_field_assignment (rtx x)
8503 rtx dest = SET_DEST (x);
8504 rtx src = SET_SRC (x);
8509 unsigned HOST_WIDE_INT len;
8511 enum machine_mode mode;
8513 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
8514 a clear of a one-bit field. We will have changed it to
8515 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
8518 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
8519 && CONST_INT_P (XEXP (XEXP (src, 0), 0))
8520 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
8521 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8523 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8526 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8530 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
8531 && subreg_lowpart_p (XEXP (src, 0))
8532 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
8533 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
8534 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
8535 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src, 0)), 0))
8536 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
8537 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8539 assign = make_extraction (VOIDmode, dest, 0,
8540 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
8543 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8547 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
8549 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
8550 && XEXP (XEXP (src, 0), 0) == const1_rtx
8551 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8553 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8556 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
8560 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
8561 SRC is an AND with all bits of that field set, then we can discard
8563 if (GET_CODE (dest) == ZERO_EXTRACT
8564 && CONST_INT_P (XEXP (dest, 1))
8565 && GET_CODE (src) == AND
8566 && CONST_INT_P (XEXP (src, 1)))
8568 HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
8569 unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
8570 unsigned HOST_WIDE_INT ze_mask;
8572 if (width >= HOST_BITS_PER_WIDE_INT)
8575 ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
8577 /* Complete overlap. We can remove the source AND. */
8578 if ((and_mask & ze_mask) == ze_mask)
8579 return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
8581 /* Partial overlap. We can reduce the source AND. */
8582 if ((and_mask & ze_mask) != and_mask)
8584 mode = GET_MODE (src);
8585 src = gen_rtx_AND (mode, XEXP (src, 0),
8586 gen_int_mode (and_mask & ze_mask, mode));
8587 return gen_rtx_SET (VOIDmode, dest, src);
8591 /* The other case we handle is assignments into a constant-position
8592 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
8593 a mask that has all one bits except for a group of zero bits and
8594 OTHER is known to have zeros where C1 has ones, this is such an
8595 assignment. Compute the position and length from C1. Shift OTHER
8596 to the appropriate position, force it to the required mode, and
8597 make the extraction. Check for the AND in both operands. */
8599 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
8602 rhs = expand_compound_operation (XEXP (src, 0));
8603 lhs = expand_compound_operation (XEXP (src, 1));
8605 if (GET_CODE (rhs) == AND
8606 && CONST_INT_P (XEXP (rhs, 1))
8607 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
8608 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
8609 else if (GET_CODE (lhs) == AND
8610 && CONST_INT_P (XEXP (lhs, 1))
8611 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
8612 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
8616 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
8617 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
8618 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
8619 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
8622 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
8626 /* The mode to use for the source is the mode of the assignment, or of
8627 what is inside a possible STRICT_LOW_PART. */
8628 mode = (GET_CODE (assign) == STRICT_LOW_PART
8629 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
8631 /* Shift OTHER right POS places and make it the source, restricting it
8632 to the proper length and mode. */
8634 src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
8638 src = force_to_mode (src, mode,
8639 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
8640 ? ~(unsigned HOST_WIDE_INT) 0
8641 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
8644 /* If SRC is masked by an AND that does not make a difference in
8645 the value being stored, strip it. */
8646 if (GET_CODE (assign) == ZERO_EXTRACT
8647 && CONST_INT_P (XEXP (assign, 1))
8648 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
8649 && GET_CODE (src) == AND
8650 && CONST_INT_P (XEXP (src, 1))
8651 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
8652 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
8653 src = XEXP (src, 0);
8655 return gen_rtx_SET (VOIDmode, assign, src);
8658 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
8662 apply_distributive_law (rtx x)
8664 enum rtx_code code = GET_CODE (x);
8665 enum rtx_code inner_code;
8666 rtx lhs, rhs, other;
8669 /* Distributivity is not true for floating point as it can change the
8670 value. So we don't do it unless -funsafe-math-optimizations. */
8671 if (FLOAT_MODE_P (GET_MODE (x))
8672 && ! flag_unsafe_math_optimizations)
8675 /* The outer operation can only be one of the following: */
8676 if (code != IOR && code != AND && code != XOR
8677 && code != PLUS && code != MINUS)
8683 /* If either operand is a primitive we can't do anything, so get out
8685 if (OBJECT_P (lhs) || OBJECT_P (rhs))
8688 lhs = expand_compound_operation (lhs);
8689 rhs = expand_compound_operation (rhs);
8690 inner_code = GET_CODE (lhs);
8691 if (inner_code != GET_CODE (rhs))
8694 /* See if the inner and outer operations distribute. */
8701 /* These all distribute except over PLUS. */
8702 if (code == PLUS || code == MINUS)
8707 if (code != PLUS && code != MINUS)
8712 /* This is also a multiply, so it distributes over everything. */
8716 /* Non-paradoxical SUBREGs distributes over all operations,
8717 provided the inner modes and byte offsets are the same, this
8718 is an extraction of a low-order part, we don't convert an fp
8719 operation to int or vice versa, this is not a vector mode,
8720 and we would not be converting a single-word operation into a
8721 multi-word operation. The latter test is not required, but
8722 it prevents generating unneeded multi-word operations. Some
8723 of the previous tests are redundant given the latter test,
8724 but are retained because they are required for correctness.
8726 We produce the result slightly differently in this case. */
8728 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
8729 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
8730 || ! subreg_lowpart_p (lhs)
8731 || (GET_MODE_CLASS (GET_MODE (lhs))
8732 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
8733 || (GET_MODE_SIZE (GET_MODE (lhs))
8734 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
8735 || VECTOR_MODE_P (GET_MODE (lhs))
8736 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD
8737 /* Result might need to be truncated. Don't change mode if
8738 explicit truncation is needed. */
8739 || !TRULY_NOOP_TRUNCATION
8740 (GET_MODE_BITSIZE (GET_MODE (x)),
8741 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (lhs)))))
8744 tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
8745 SUBREG_REG (lhs), SUBREG_REG (rhs));
8746 return gen_lowpart (GET_MODE (x), tem);
8752 /* Set LHS and RHS to the inner operands (A and B in the example
8753 above) and set OTHER to the common operand (C in the example).
8754 There is only one way to do this unless the inner operation is
8756 if (COMMUTATIVE_ARITH_P (lhs)
8757 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
8758 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
8759 else if (COMMUTATIVE_ARITH_P (lhs)
8760 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
8761 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
8762 else if (COMMUTATIVE_ARITH_P (lhs)
8763 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
8764 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
8765 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
8766 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
8770 /* Form the new inner operation, seeing if it simplifies first. */
8771 tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
8773 /* There is one exception to the general way of distributing:
8774 (a | c) ^ (b | c) -> (a ^ b) & ~c */
8775 if (code == XOR && inner_code == IOR)
8778 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
8781 /* We may be able to continuing distributing the result, so call
8782 ourselves recursively on the inner operation before forming the
8783 outer operation, which we return. */
8784 return simplify_gen_binary (inner_code, GET_MODE (x),
8785 apply_distributive_law (tem), other);
8788 /* See if X is of the form (* (+ A B) C), and if so convert to
8789 (+ (* A C) (* B C)) and try to simplify.
8791 Most of the time, this results in no change. However, if some of
8792 the operands are the same or inverses of each other, simplifications
8795 For example, (and (ior A B) (not B)) can occur as the result of
8796 expanding a bit field assignment. When we apply the distributive
8797 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
8798 which then simplifies to (and (A (not B))).
8800 Note that no checks happen on the validity of applying the inverse
8801 distributive law. This is pointless since we can do it in the
8802 few places where this routine is called.
8804 N is the index of the term that is decomposed (the arithmetic operation,
8805 i.e. (+ A B) in the first example above). !N is the index of the term that
8806 is distributed, i.e. of C in the first example above. */
8808 distribute_and_simplify_rtx (rtx x, int n)
8810 enum machine_mode mode;
8811 enum rtx_code outer_code, inner_code;
8812 rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
8814 /* Distributivity is not true for floating point as it can change the
8815 value. So we don't do it unless -funsafe-math-optimizations. */
8816 if (FLOAT_MODE_P (GET_MODE (x))
8817 && ! flag_unsafe_math_optimizations)
8820 decomposed = XEXP (x, n);
8821 if (!ARITHMETIC_P (decomposed))
8824 mode = GET_MODE (x);
8825 outer_code = GET_CODE (x);
8826 distributed = XEXP (x, !n);
8828 inner_code = GET_CODE (decomposed);
8829 inner_op0 = XEXP (decomposed, 0);
8830 inner_op1 = XEXP (decomposed, 1);
8832 /* Special case (and (xor B C) (not A)), which is equivalent to
8833 (xor (ior A B) (ior A C)) */
8834 if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
8836 distributed = XEXP (distributed, 0);
8842 /* Distribute the second term. */
8843 new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
8844 new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
8848 /* Distribute the first term. */
8849 new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
8850 new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
8853 tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
8855 if (GET_CODE (tmp) != outer_code
8856 && rtx_cost (tmp, SET, optimize_this_for_speed_p)
8857 < rtx_cost (x, SET, optimize_this_for_speed_p))
8863 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
8864 in MODE. Return an equivalent form, if different from (and VAROP
8865 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
8868 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
8869 unsigned HOST_WIDE_INT constop)
8871 unsigned HOST_WIDE_INT nonzero;
8872 unsigned HOST_WIDE_INT orig_constop;
8877 orig_constop = constop;
8878 if (GET_CODE (varop) == CLOBBER)
8881 /* Simplify VAROP knowing that we will be only looking at some of the
8884 Note by passing in CONSTOP, we guarantee that the bits not set in
8885 CONSTOP are not significant and will never be examined. We must
8886 ensure that is the case by explicitly masking out those bits
8887 before returning. */
8888 varop = force_to_mode (varop, mode, constop, 0);
8890 /* If VAROP is a CLOBBER, we will fail so return it. */
8891 if (GET_CODE (varop) == CLOBBER)
8894 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8895 to VAROP and return the new constant. */
8896 if (CONST_INT_P (varop))
8897 return gen_int_mode (INTVAL (varop) & constop, mode);
8899 /* See what bits may be nonzero in VAROP. Unlike the general case of
8900 a call to nonzero_bits, here we don't care about bits outside
8903 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
8905 /* Turn off all bits in the constant that are known to already be zero.
8906 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8907 which is tested below. */
8911 /* If we don't have any bits left, return zero. */
8915 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8916 a power of two, we can replace this with an ASHIFT. */
8917 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
8918 && (i = exact_log2 (constop)) >= 0)
8919 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
8921 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8922 or XOR, then try to apply the distributive law. This may eliminate
8923 operations if either branch can be simplified because of the AND.
8924 It may also make some cases more complex, but those cases probably
8925 won't match a pattern either with or without this. */
8927 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
8931 apply_distributive_law
8932 (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
8933 simplify_and_const_int (NULL_RTX,
8937 simplify_and_const_int (NULL_RTX,
8942 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
8943 the AND and see if one of the operands simplifies to zero. If so, we
8944 may eliminate it. */
8946 if (GET_CODE (varop) == PLUS
8947 && exact_log2 (constop + 1) >= 0)
8951 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
8952 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
8953 if (o0 == const0_rtx)
8955 if (o1 == const0_rtx)
8959 /* Make a SUBREG if necessary. If we can't make it, fail. */
8960 varop = gen_lowpart (mode, varop);
8961 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
8964 /* If we are only masking insignificant bits, return VAROP. */
8965 if (constop == nonzero)
8968 if (varop == orig_varop && constop == orig_constop)
8971 /* Otherwise, return an AND. */
8972 return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
8976 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8979 Return an equivalent form, if different from X. Otherwise, return X. If
8980 X is zero, we are to always construct the equivalent form. */
8983 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
8984 unsigned HOST_WIDE_INT constop)
8986 rtx tem = simplify_and_const_int_1 (mode, varop, constop);
8991 x = simplify_gen_binary (AND, GET_MODE (varop), varop,
8992 gen_int_mode (constop, mode));
8993 if (GET_MODE (x) != mode)
8994 x = gen_lowpart (mode, x);
8998 /* Given a REG, X, compute which bits in X can be nonzero.
8999 We don't care about bits outside of those defined in MODE.
9001 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9002 a shift, AND, or zero_extract, we can do better. */
9005 reg_nonzero_bits_for_combine (const_rtx x, enum machine_mode mode,
9006 const_rtx known_x ATTRIBUTE_UNUSED,
9007 enum machine_mode known_mode ATTRIBUTE_UNUSED,
9008 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
9009 unsigned HOST_WIDE_INT *nonzero)
9014 /* If X is a register whose nonzero bits value is current, use it.
9015 Otherwise, if X is a register whose value we can find, use that
9016 value. Otherwise, use the previously-computed global nonzero bits
9017 for this register. */
9019 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
9020 if (rsp->last_set_value != 0
9021 && (rsp->last_set_mode == mode
9022 || (GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT
9023 && GET_MODE_CLASS (mode) == MODE_INT))
9024 && ((rsp->last_set_label >= label_tick_ebb_start
9025 && rsp->last_set_label < label_tick)
9026 || (rsp->last_set_label == label_tick
9027 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9028 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9029 && REG_N_SETS (REGNO (x)) == 1
9031 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9033 *nonzero &= rsp->last_set_nonzero_bits;
9037 tem = get_last_value (x);
9041 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9042 /* If X is narrower than MODE and TEM is a non-negative
9043 constant that would appear negative in the mode of X,
9044 sign-extend it for use in reg_nonzero_bits because some
9045 machines (maybe most) will actually do the sign-extension
9046 and this is the conservative approach.
9048 ??? For 2.5, try to tighten up the MD files in this regard
9049 instead of this kludge. */
9051 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)
9052 && CONST_INT_P (tem)
9054 && 0 != (INTVAL (tem)
9055 & ((HOST_WIDE_INT) 1
9056 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
9057 tem = GEN_INT (INTVAL (tem)
9058 | ((HOST_WIDE_INT) (-1)
9059 << GET_MODE_BITSIZE (GET_MODE (x))));
9063 else if (nonzero_sign_valid && rsp->nonzero_bits)
9065 unsigned HOST_WIDE_INT mask = rsp->nonzero_bits;
9067 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode))
9068 /* We don't know anything about the upper bits. */
9069 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
9076 /* Return the number of bits at the high-order end of X that are known to
9077 be equal to the sign bit. X will be used in mode MODE; if MODE is
9078 VOIDmode, X will be used in its own mode. The returned value will always
9079 be between 1 and the number of bits in MODE. */
9082 reg_num_sign_bit_copies_for_combine (const_rtx x, enum machine_mode mode,
9083 const_rtx known_x ATTRIBUTE_UNUSED,
9084 enum machine_mode known_mode
9086 unsigned int known_ret ATTRIBUTE_UNUSED,
9087 unsigned int *result)
9092 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
9093 if (rsp->last_set_value != 0
9094 && rsp->last_set_mode == mode
9095 && ((rsp->last_set_label >= label_tick_ebb_start
9096 && rsp->last_set_label < label_tick)
9097 || (rsp->last_set_label == label_tick
9098 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9099 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9100 && REG_N_SETS (REGNO (x)) == 1
9102 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9104 *result = rsp->last_set_sign_bit_copies;
9108 tem = get_last_value (x);
9112 if (nonzero_sign_valid && rsp->sign_bit_copies != 0
9113 && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode))
9114 *result = rsp->sign_bit_copies;
9119 /* Return the number of "extended" bits there are in X, when interpreted
9120 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9121 unsigned quantities, this is the number of high-order zero bits.
9122 For signed quantities, this is the number of copies of the sign bit
9123 minus 1. In both case, this function returns the number of "spare"
9124 bits. For example, if two quantities for which this function returns
9125 at least 1 are added, the addition is known not to overflow.
9127 This function will always return 0 unless called during combine, which
9128 implies that it must be called from a define_split. */
9131 extended_count (const_rtx x, enum machine_mode mode, int unsignedp)
9133 if (nonzero_sign_valid == 0)
9137 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9138 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
9139 - floor_log2 (nonzero_bits (x, mode)))
9141 : num_sign_bit_copies (x, mode) - 1);
9144 /* This function is called from `simplify_shift_const' to merge two
9145 outer operations. Specifically, we have already found that we need
9146 to perform operation *POP0 with constant *PCONST0 at the outermost
9147 position. We would now like to also perform OP1 with constant CONST1
9148 (with *POP0 being done last).
9150 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9151 the resulting operation. *PCOMP_P is set to 1 if we would need to
9152 complement the innermost operand, otherwise it is unchanged.
9154 MODE is the mode in which the operation will be done. No bits outside
9155 the width of this mode matter. It is assumed that the width of this mode
9156 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9158 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9159 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9160 result is simply *PCONST0.
9162 If the resulting operation cannot be expressed as one operation, we
9163 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9166 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
9168 enum rtx_code op0 = *pop0;
9169 HOST_WIDE_INT const0 = *pconst0;
9171 const0 &= GET_MODE_MASK (mode);
9172 const1 &= GET_MODE_MASK (mode);
9174 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9178 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9181 if (op1 == UNKNOWN || op0 == SET)
9184 else if (op0 == UNKNOWN)
9185 op0 = op1, const0 = const1;
9187 else if (op0 == op1)
9211 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9212 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
9215 /* If the two constants aren't the same, we can't do anything. The
9216 remaining six cases can all be done. */
9217 else if (const0 != const1)
9225 /* (a & b) | b == b */
9227 else /* op1 == XOR */
9228 /* (a ^ b) | b == a | b */
9234 /* (a & b) ^ b == (~a) & b */
9235 op0 = AND, *pcomp_p = 1;
9236 else /* op1 == IOR */
9237 /* (a | b) ^ b == a & ~b */
9238 op0 = AND, const0 = ~const0;
9243 /* (a | b) & b == b */
9245 else /* op1 == XOR */
9246 /* (a ^ b) & b) == (~a) & b */
9253 /* Check for NO-OP cases. */
9254 const0 &= GET_MODE_MASK (mode);
9256 && (op0 == IOR || op0 == XOR || op0 == PLUS))
9258 else if (const0 == 0 && op0 == AND)
9260 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
9266 /* ??? Slightly redundant with the above mask, but not entirely.
9267 Moving this above means we'd have to sign-extend the mode mask
9268 for the final test. */
9269 if (op0 != UNKNOWN && op0 != NEG)
9270 *pconst0 = trunc_int_for_mode (const0, mode);
9275 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9276 the shift in. The original shift operation CODE is performed on OP in
9277 ORIG_MODE. Return the wider mode MODE if we can perform the operation
9278 in that mode. Return ORIG_MODE otherwise. We can also assume that the
9279 result of the shift is subject to operation OUTER_CODE with operand
9282 static enum machine_mode
9283 try_widen_shift_mode (enum rtx_code code, rtx op, int count,
9284 enum machine_mode orig_mode, enum machine_mode mode,
9285 enum rtx_code outer_code, HOST_WIDE_INT outer_const)
9287 if (orig_mode == mode)
9289 gcc_assert (GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (orig_mode));
9291 /* In general we can't perform in wider mode for right shift and rotate. */
9295 /* We can still widen if the bits brought in from the left are identical
9296 to the sign bit of ORIG_MODE. */
9297 if (num_sign_bit_copies (op, mode)
9298 > (unsigned) (GET_MODE_BITSIZE (mode)
9299 - GET_MODE_BITSIZE (orig_mode)))
9304 /* Similarly here but with zero bits. */
9305 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9306 && (nonzero_bits (op, mode) & ~GET_MODE_MASK (orig_mode)) == 0)
9309 /* We can also widen if the bits brought in will be masked off. This
9310 operation is performed in ORIG_MODE. */
9311 if (outer_code == AND)
9313 int care_bits = low_bitmask_len (orig_mode, outer_const);
9316 && GET_MODE_BITSIZE (orig_mode) - care_bits >= count)
9332 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9333 The result of the shift is RESULT_MODE. Return NULL_RTX if we cannot
9334 simplify it. Otherwise, return a simplified value.
9336 The shift is normally computed in the widest mode we find in VAROP, as
9337 long as it isn't a different number of words than RESULT_MODE. Exceptions
9338 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9341 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
9342 rtx varop, int orig_count)
9344 enum rtx_code orig_code = code;
9345 rtx orig_varop = varop;
9347 enum machine_mode mode = result_mode;
9348 enum machine_mode shift_mode, tmode;
9349 unsigned int mode_words
9350 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
9351 /* We form (outer_op (code varop count) (outer_const)). */
9352 enum rtx_code outer_op = UNKNOWN;
9353 HOST_WIDE_INT outer_const = 0;
9354 int complement_p = 0;
9357 /* Make sure and truncate the "natural" shift on the way in. We don't
9358 want to do this inside the loop as it makes it more difficult to
9360 if (SHIFT_COUNT_TRUNCATED)
9361 orig_count &= GET_MODE_BITSIZE (mode) - 1;
9363 /* If we were given an invalid count, don't do anything except exactly
9364 what was requested. */
9366 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
9371 /* Unless one of the branches of the `if' in this loop does a `continue',
9372 we will `break' the loop after the `if'. */
9376 /* If we have an operand of (clobber (const_int 0)), fail. */
9377 if (GET_CODE (varop) == CLOBBER)
9380 /* Convert ROTATERT to ROTATE. */
9381 if (code == ROTATERT)
9383 unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
9385 if (VECTOR_MODE_P (result_mode))
9386 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
9388 count = bitsize - count;
9391 shift_mode = try_widen_shift_mode (code, varop, count, result_mode,
9392 mode, outer_op, outer_const);
9394 /* Handle cases where the count is greater than the size of the mode
9395 minus 1. For ASHIFT, use the size minus one as the count (this can
9396 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9397 take the count modulo the size. For other shifts, the result is
9400 Since these shifts are being produced by the compiler by combining
9401 multiple operations, each of which are defined, we know what the
9402 result is supposed to be. */
9404 if (count > (GET_MODE_BITSIZE (shift_mode) - 1))
9406 if (code == ASHIFTRT)
9407 count = GET_MODE_BITSIZE (shift_mode) - 1;
9408 else if (code == ROTATE || code == ROTATERT)
9409 count %= GET_MODE_BITSIZE (shift_mode);
9412 /* We can't simply return zero because there may be an
9420 /* If we discovered we had to complement VAROP, leave. Making a NOT
9421 here would cause an infinite loop. */
9425 /* An arithmetic right shift of a quantity known to be -1 or 0
9427 if (code == ASHIFTRT
9428 && (num_sign_bit_copies (varop, shift_mode)
9429 == GET_MODE_BITSIZE (shift_mode)))
9435 /* If we are doing an arithmetic right shift and discarding all but
9436 the sign bit copies, this is equivalent to doing a shift by the
9437 bitsize minus one. Convert it into that shift because it will often
9438 allow other simplifications. */
9440 if (code == ASHIFTRT
9441 && (count + num_sign_bit_copies (varop, shift_mode)
9442 >= GET_MODE_BITSIZE (shift_mode)))
9443 count = GET_MODE_BITSIZE (shift_mode) - 1;
9445 /* We simplify the tests below and elsewhere by converting
9446 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9447 `make_compound_operation' will convert it to an ASHIFTRT for
9448 those machines (such as VAX) that don't have an LSHIFTRT. */
9449 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9451 && ((nonzero_bits (varop, shift_mode)
9452 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
9456 if (((code == LSHIFTRT
9457 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9458 && !(nonzero_bits (varop, shift_mode) >> count))
9460 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9461 && !((nonzero_bits (varop, shift_mode) << count)
9462 & GET_MODE_MASK (shift_mode))))
9463 && !side_effects_p (varop))
9466 switch (GET_CODE (varop))
9472 new_rtx = expand_compound_operation (varop);
9473 if (new_rtx != varop)
9481 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9482 minus the width of a smaller mode, we can do this with a
9483 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9484 if ((code == ASHIFTRT || code == LSHIFTRT)
9485 && ! mode_dependent_address_p (XEXP (varop, 0))
9486 && ! MEM_VOLATILE_P (varop)
9487 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9488 MODE_INT, 1)) != BLKmode)
9490 new_rtx = adjust_address_nv (varop, tmode,
9491 BYTES_BIG_ENDIAN ? 0
9492 : count / BITS_PER_UNIT);
9494 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9495 : ZERO_EXTEND, mode, new_rtx);
9502 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9503 the same number of words as what we've seen so far. Then store
9504 the widest mode in MODE. */
9505 if (subreg_lowpart_p (varop)
9506 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9507 > GET_MODE_SIZE (GET_MODE (varop)))
9508 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9509 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9512 varop = SUBREG_REG (varop);
9513 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9514 mode = GET_MODE (varop);
9520 /* Some machines use MULT instead of ASHIFT because MULT
9521 is cheaper. But it is still better on those machines to
9522 merge two shifts into one. */
9523 if (CONST_INT_P (XEXP (varop, 1))
9524 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9527 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
9529 GEN_INT (exact_log2 (
9530 INTVAL (XEXP (varop, 1)))));
9536 /* Similar, for when divides are cheaper. */
9537 if (CONST_INT_P (XEXP (varop, 1))
9538 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9541 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
9543 GEN_INT (exact_log2 (
9544 INTVAL (XEXP (varop, 1)))));
9550 /* If we are extracting just the sign bit of an arithmetic
9551 right shift, that shift is not needed. However, the sign
9552 bit of a wider mode may be different from what would be
9553 interpreted as the sign bit in a narrower mode, so, if
9554 the result is narrower, don't discard the shift. */
9555 if (code == LSHIFTRT
9556 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9557 && (GET_MODE_BITSIZE (result_mode)
9558 >= GET_MODE_BITSIZE (GET_MODE (varop))))
9560 varop = XEXP (varop, 0);
9564 /* ... fall through ... */
9569 /* Here we have two nested shifts. The result is usually the
9570 AND of a new shift with a mask. We compute the result below. */
9571 if (CONST_INT_P (XEXP (varop, 1))
9572 && INTVAL (XEXP (varop, 1)) >= 0
9573 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
9574 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9575 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9576 && !VECTOR_MODE_P (result_mode))
9578 enum rtx_code first_code = GET_CODE (varop);
9579 unsigned int first_count = INTVAL (XEXP (varop, 1));
9580 unsigned HOST_WIDE_INT mask;
9583 /* We have one common special case. We can't do any merging if
9584 the inner code is an ASHIFTRT of a smaller mode. However, if
9585 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9586 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9587 we can convert it to
9588 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9589 This simplifies certain SIGN_EXTEND operations. */
9590 if (code == ASHIFT && first_code == ASHIFTRT
9591 && count == (GET_MODE_BITSIZE (result_mode)
9592 - GET_MODE_BITSIZE (GET_MODE (varop))))
9594 /* C3 has the low-order C1 bits zero. */
9596 mask = (GET_MODE_MASK (mode)
9597 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
9599 varop = simplify_and_const_int (NULL_RTX, result_mode,
9600 XEXP (varop, 0), mask);
9601 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
9603 count = first_count;
9608 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9609 than C1 high-order bits equal to the sign bit, we can convert
9610 this to either an ASHIFT or an ASHIFTRT depending on the
9613 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9615 if (code == ASHIFTRT && first_code == ASHIFT
9616 && GET_MODE (varop) == shift_mode
9617 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
9620 varop = XEXP (varop, 0);
9621 count -= first_count;
9631 /* There are some cases we can't do. If CODE is ASHIFTRT,
9632 we can only do this if FIRST_CODE is also ASHIFTRT.
9634 We can't do the case when CODE is ROTATE and FIRST_CODE is
9637 If the mode of this shift is not the mode of the outer shift,
9638 we can't do this if either shift is a right shift or ROTATE.
9640 Finally, we can't do any of these if the mode is too wide
9641 unless the codes are the same.
9643 Handle the case where the shift codes are the same
9646 if (code == first_code)
9648 if (GET_MODE (varop) != result_mode
9649 && (code == ASHIFTRT || code == LSHIFTRT
9653 count += first_count;
9654 varop = XEXP (varop, 0);
9658 if (code == ASHIFTRT
9659 || (code == ROTATE && first_code == ASHIFTRT)
9660 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
9661 || (GET_MODE (varop) != result_mode
9662 && (first_code == ASHIFTRT || first_code == LSHIFTRT
9663 || first_code == ROTATE
9664 || code == ROTATE)))
9667 /* To compute the mask to apply after the shift, shift the
9668 nonzero bits of the inner shift the same way the
9669 outer shift will. */
9671 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
9674 = simplify_const_binary_operation (code, result_mode, mask_rtx,
9677 /* Give up if we can't compute an outer operation to use. */
9679 || !CONST_INT_P (mask_rtx)
9680 || ! merge_outer_ops (&outer_op, &outer_const, AND,
9682 result_mode, &complement_p))
9685 /* If the shifts are in the same direction, we add the
9686 counts. Otherwise, we subtract them. */
9687 if ((code == ASHIFTRT || code == LSHIFTRT)
9688 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
9689 count += first_count;
9691 count -= first_count;
9693 /* If COUNT is positive, the new shift is usually CODE,
9694 except for the two exceptions below, in which case it is
9695 FIRST_CODE. If the count is negative, FIRST_CODE should
9698 && ((first_code == ROTATE && code == ASHIFT)
9699 || (first_code == ASHIFTRT && code == LSHIFTRT)))
9702 code = first_code, count = -count;
9704 varop = XEXP (varop, 0);
9708 /* If we have (A << B << C) for any shift, we can convert this to
9709 (A << C << B). This wins if A is a constant. Only try this if
9710 B is not a constant. */
9712 else if (GET_CODE (varop) == code
9713 && CONST_INT_P (XEXP (varop, 0))
9714 && !CONST_INT_P (XEXP (varop, 1)))
9716 rtx new_rtx = simplify_const_binary_operation (code, mode,
9719 varop = gen_rtx_fmt_ee (code, mode, new_rtx, XEXP (varop, 1));
9726 if (VECTOR_MODE_P (mode))
9729 /* Make this fit the case below. */
9730 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
9731 GEN_INT (GET_MODE_MASK (mode)));
9737 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9738 with C the size of VAROP - 1 and the shift is logical if
9739 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9740 we have an (le X 0) operation. If we have an arithmetic shift
9741 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9742 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9744 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9745 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9746 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9747 && (code == LSHIFTRT || code == ASHIFTRT)
9748 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9749 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9752 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
9755 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9756 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9761 /* If we have (shift (logical)), move the logical to the outside
9762 to allow it to possibly combine with another logical and the
9763 shift to combine with another shift. This also canonicalizes to
9764 what a ZERO_EXTRACT looks like. Also, some machines have
9765 (and (shift)) insns. */
9767 if (CONST_INT_P (XEXP (varop, 1))
9768 /* We can't do this if we have (ashiftrt (xor)) and the
9769 constant has its sign bit set in shift_mode. */
9770 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
9771 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
9773 && (new_rtx = simplify_const_binary_operation (code, result_mode,
9775 GEN_INT (count))) != 0
9776 && CONST_INT_P (new_rtx)
9777 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9778 INTVAL (new_rtx), result_mode, &complement_p))
9780 varop = XEXP (varop, 0);
9784 /* If we can't do that, try to simplify the shift in each arm of the
9785 logical expression, make a new logical expression, and apply
9786 the inverse distributive law. This also can't be done
9787 for some (ashiftrt (xor)). */
9788 if (CONST_INT_P (XEXP (varop, 1))
9789 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
9790 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
9793 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9794 XEXP (varop, 0), count);
9795 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9796 XEXP (varop, 1), count);
9798 varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
9800 varop = apply_distributive_law (varop);
9808 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9809 says that the sign bit can be tested, FOO has mode MODE, C is
9810 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9811 that may be nonzero. */
9812 if (code == LSHIFTRT
9813 && XEXP (varop, 1) == const0_rtx
9814 && GET_MODE (XEXP (varop, 0)) == result_mode
9815 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9816 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9817 && STORE_FLAG_VALUE == -1
9818 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9819 && merge_outer_ops (&outer_op, &outer_const, XOR,
9820 (HOST_WIDE_INT) 1, result_mode,
9823 varop = XEXP (varop, 0);
9830 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9831 than the number of bits in the mode is equivalent to A. */
9832 if (code == LSHIFTRT
9833 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9834 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9836 varop = XEXP (varop, 0);
9841 /* NEG commutes with ASHIFT since it is multiplication. Move the
9842 NEG outside to allow shifts to combine. */
9844 && merge_outer_ops (&outer_op, &outer_const, NEG,
9845 (HOST_WIDE_INT) 0, result_mode,
9848 varop = XEXP (varop, 0);
9854 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9855 is one less than the number of bits in the mode is
9856 equivalent to (xor A 1). */
9857 if (code == LSHIFTRT
9858 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9859 && XEXP (varop, 1) == constm1_rtx
9860 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9861 && merge_outer_ops (&outer_op, &outer_const, XOR,
9862 (HOST_WIDE_INT) 1, result_mode,
9866 varop = XEXP (varop, 0);
9870 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9871 that might be nonzero in BAR are those being shifted out and those
9872 bits are known zero in FOO, we can replace the PLUS with FOO.
9873 Similarly in the other operand order. This code occurs when
9874 we are computing the size of a variable-size array. */
9876 if ((code == ASHIFTRT || code == LSHIFTRT)
9877 && count < HOST_BITS_PER_WIDE_INT
9878 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9879 && (nonzero_bits (XEXP (varop, 1), result_mode)
9880 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9882 varop = XEXP (varop, 0);
9885 else if ((code == ASHIFTRT || code == LSHIFTRT)
9886 && count < HOST_BITS_PER_WIDE_INT
9887 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9888 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9890 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9891 & nonzero_bits (XEXP (varop, 1),
9894 varop = XEXP (varop, 1);
9898 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9900 && CONST_INT_P (XEXP (varop, 1))
9901 && (new_rtx = simplify_const_binary_operation (ASHIFT, result_mode,
9903 GEN_INT (count))) != 0
9904 && CONST_INT_P (new_rtx)
9905 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9906 INTVAL (new_rtx), result_mode, &complement_p))
9908 varop = XEXP (varop, 0);
9912 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
9913 signbit', and attempt to change the PLUS to an XOR and move it to
9914 the outer operation as is done above in the AND/IOR/XOR case
9915 leg for shift(logical). See details in logical handling above
9916 for reasoning in doing so. */
9917 if (code == LSHIFTRT
9918 && CONST_INT_P (XEXP (varop, 1))
9919 && mode_signbit_p (result_mode, XEXP (varop, 1))
9920 && (new_rtx = simplify_const_binary_operation (code, result_mode,
9922 GEN_INT (count))) != 0
9923 && CONST_INT_P (new_rtx)
9924 && merge_outer_ops (&outer_op, &outer_const, XOR,
9925 INTVAL (new_rtx), result_mode, &complement_p))
9927 varop = XEXP (varop, 0);
9934 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9935 with C the size of VAROP - 1 and the shift is logical if
9936 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9937 we have a (gt X 0) operation. If the shift is arithmetic with
9938 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9939 we have a (neg (gt X 0)) operation. */
9941 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9942 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9943 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9944 && (code == LSHIFTRT || code == ASHIFTRT)
9945 && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
9946 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
9947 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9950 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9953 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9954 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9961 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9962 if the truncate does not affect the value. */
9963 if (code == LSHIFTRT
9964 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9965 && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
9966 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9967 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9968 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9970 rtx varop_inner = XEXP (varop, 0);
9973 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9974 XEXP (varop_inner, 0),
9976 (count + INTVAL (XEXP (varop_inner, 1))));
9977 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9990 shift_mode = try_widen_shift_mode (code, varop, count, result_mode, mode,
9991 outer_op, outer_const);
9993 /* We have now finished analyzing the shift. The result should be
9994 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9995 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
9996 to the result of the shift. OUTER_CONST is the relevant constant,
9997 but we must turn off all bits turned off in the shift. */
9999 if (outer_op == UNKNOWN
10000 && orig_code == code && orig_count == count
10001 && varop == orig_varop
10002 && shift_mode == GET_MODE (varop))
10005 /* Make a SUBREG if necessary. If we can't make it, fail. */
10006 varop = gen_lowpart (shift_mode, varop);
10007 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
10010 /* If we have an outer operation and we just made a shift, it is
10011 possible that we could have simplified the shift were it not
10012 for the outer operation. So try to do the simplification
10015 if (outer_op != UNKNOWN)
10016 x = simplify_shift_const_1 (code, shift_mode, varop, count);
10021 x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
10023 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10024 turn off all the bits that the shift would have turned off. */
10025 if (orig_code == LSHIFTRT && result_mode != shift_mode)
10026 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
10027 GET_MODE_MASK (result_mode) >> orig_count);
10029 /* Do the remainder of the processing in RESULT_MODE. */
10030 x = gen_lowpart_or_truncate (result_mode, x);
10032 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10035 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
10037 if (outer_op != UNKNOWN)
10039 if (GET_RTX_CLASS (outer_op) != RTX_UNARY
10040 && GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
10041 outer_const = trunc_int_for_mode (outer_const, result_mode);
10043 if (outer_op == AND)
10044 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
10045 else if (outer_op == SET)
10047 /* This means that we have determined that the result is
10048 equivalent to a constant. This should be rare. */
10049 if (!side_effects_p (x))
10050 x = GEN_INT (outer_const);
10052 else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
10053 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
10055 x = simplify_gen_binary (outer_op, result_mode, x,
10056 GEN_INT (outer_const));
10062 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10063 The result of the shift is RESULT_MODE. If we cannot simplify it,
10064 return X or, if it is NULL, synthesize the expression with
10065 simplify_gen_binary. Otherwise, return a simplified value.
10067 The shift is normally computed in the widest mode we find in VAROP, as
10068 long as it isn't a different number of words than RESULT_MODE. Exceptions
10069 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10072 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
10073 rtx varop, int count)
10075 rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
10080 x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
10081 if (GET_MODE (x) != result_mode)
10082 x = gen_lowpart (result_mode, x);
10087 /* Like recog, but we receive the address of a pointer to a new pattern.
10088 We try to match the rtx that the pointer points to.
10089 If that fails, we may try to modify or replace the pattern,
10090 storing the replacement into the same pointer object.
10092 Modifications include deletion or addition of CLOBBERs.
10094 PNOTES is a pointer to a location where any REG_UNUSED notes added for
10095 the CLOBBERs are placed.
10097 The value is the final insn code from the pattern ultimately matched,
10101 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
10103 rtx pat = *pnewpat;
10104 int insn_code_number;
10105 int num_clobbers_to_add = 0;
10108 rtx old_notes, old_pat;
10110 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10111 we use to indicate that something didn't match. If we find such a
10112 thing, force rejection. */
10113 if (GET_CODE (pat) == PARALLEL)
10114 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
10115 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
10116 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
10119 old_pat = PATTERN (insn);
10120 old_notes = REG_NOTES (insn);
10121 PATTERN (insn) = pat;
10122 REG_NOTES (insn) = 0;
10124 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10125 if (dump_file && (dump_flags & TDF_DETAILS))
10127 if (insn_code_number < 0)
10128 fputs ("Failed to match this instruction:\n", dump_file);
10130 fputs ("Successfully matched this instruction:\n", dump_file);
10131 print_rtl_single (dump_file, pat);
10134 /* If it isn't, there is the possibility that we previously had an insn
10135 that clobbered some register as a side effect, but the combined
10136 insn doesn't need to do that. So try once more without the clobbers
10137 unless this represents an ASM insn. */
10139 if (insn_code_number < 0 && ! check_asm_operands (pat)
10140 && GET_CODE (pat) == PARALLEL)
10144 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
10145 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
10148 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
10152 SUBST_INT (XVECLEN (pat, 0), pos);
10155 pat = XVECEXP (pat, 0, 0);
10157 PATTERN (insn) = pat;
10158 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10159 if (dump_file && (dump_flags & TDF_DETAILS))
10161 if (insn_code_number < 0)
10162 fputs ("Failed to match this instruction:\n", dump_file);
10164 fputs ("Successfully matched this instruction:\n", dump_file);
10165 print_rtl_single (dump_file, pat);
10168 PATTERN (insn) = old_pat;
10169 REG_NOTES (insn) = old_notes;
10171 /* Recognize all noop sets, these will be killed by followup pass. */
10172 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
10173 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
10175 /* If we had any clobbers to add, make a new pattern than contains
10176 them. Then check to make sure that all of them are dead. */
10177 if (num_clobbers_to_add)
10179 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
10180 rtvec_alloc (GET_CODE (pat) == PARALLEL
10181 ? (XVECLEN (pat, 0)
10182 + num_clobbers_to_add)
10183 : num_clobbers_to_add + 1));
10185 if (GET_CODE (pat) == PARALLEL)
10186 for (i = 0; i < XVECLEN (pat, 0); i++)
10187 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
10189 XVECEXP (newpat, 0, 0) = pat;
10191 add_clobbers (newpat, insn_code_number);
10193 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
10194 i < XVECLEN (newpat, 0); i++)
10196 if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
10197 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
10199 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH)
10201 gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)));
10202 notes = alloc_reg_note (REG_UNUSED,
10203 XEXP (XVECEXP (newpat, 0, i), 0), notes);
10212 return insn_code_number;
10215 /* Like gen_lowpart_general but for use by combine. In combine it
10216 is not possible to create any new pseudoregs. However, it is
10217 safe to create invalid memory addresses, because combine will
10218 try to recognize them and all they will do is make the combine
10221 If for some reason this cannot do its job, an rtx
10222 (clobber (const_int 0)) is returned.
10223 An insn containing that will not be recognized. */
10226 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
10228 enum machine_mode imode = GET_MODE (x);
10229 unsigned int osize = GET_MODE_SIZE (omode);
10230 unsigned int isize = GET_MODE_SIZE (imode);
10233 if (omode == imode)
10236 /* Return identity if this is a CONST or symbolic reference. */
10238 && (GET_CODE (x) == CONST
10239 || GET_CODE (x) == SYMBOL_REF
10240 || GET_CODE (x) == LABEL_REF))
10243 /* We can only support MODE being wider than a word if X is a
10244 constant integer or has a mode the same size. */
10245 if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
10246 && ! ((imode == VOIDmode
10247 && (CONST_INT_P (x)
10248 || GET_CODE (x) == CONST_DOUBLE))
10249 || isize == osize))
10252 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10253 won't know what to do. So we will strip off the SUBREG here and
10254 process normally. */
10255 if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
10257 x = SUBREG_REG (x);
10259 /* For use in case we fall down into the address adjustments
10260 further below, we need to adjust the known mode and size of
10261 x; imode and isize, since we just adjusted x. */
10262 imode = GET_MODE (x);
10264 if (imode == omode)
10267 isize = GET_MODE_SIZE (imode);
10270 result = gen_lowpart_common (omode, x);
10279 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10281 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
10284 /* If we want to refer to something bigger than the original memref,
10285 generate a paradoxical subreg instead. That will force a reload
10286 of the original memref X. */
10288 return gen_rtx_SUBREG (omode, x, 0);
10290 if (WORDS_BIG_ENDIAN)
10291 offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
10293 /* Adjust the address so that the address-after-the-data is
10295 if (BYTES_BIG_ENDIAN)
10296 offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
10298 return adjust_address_nv (x, omode, offset);
10301 /* If X is a comparison operator, rewrite it in a new mode. This
10302 probably won't match, but may allow further simplifications. */
10303 else if (COMPARISON_P (x))
10304 return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
10306 /* If we couldn't simplify X any other way, just enclose it in a
10307 SUBREG. Normally, this SUBREG won't match, but some patterns may
10308 include an explicit SUBREG or we may simplify it further in combine. */
10314 offset = subreg_lowpart_offset (omode, imode);
10315 if (imode == VOIDmode)
10317 imode = int_mode_for_mode (omode);
10318 x = gen_lowpart_common (imode, x);
10322 res = simplify_gen_subreg (omode, x, imode, offset);
10328 return gen_rtx_CLOBBER (omode, const0_rtx);
10331 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10332 comparison code that will be tested.
10334 The result is a possibly different comparison code to use. *POP0 and
10335 *POP1 may be updated.
10337 It is possible that we might detect that a comparison is either always
10338 true or always false. However, we do not perform general constant
10339 folding in combine, so this knowledge isn't useful. Such tautologies
10340 should have been detected earlier. Hence we ignore all such cases. */
10342 static enum rtx_code
10343 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
10349 enum machine_mode mode, tmode;
10351 /* Try a few ways of applying the same transformation to both operands. */
10354 #ifndef WORD_REGISTER_OPERATIONS
10355 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10356 so check specially. */
10357 if (code != GTU && code != GEU && code != LTU && code != LEU
10358 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
10359 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10360 && GET_CODE (XEXP (op1, 0)) == ASHIFT
10361 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
10362 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
10363 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
10364 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
10365 && CONST_INT_P (XEXP (op0, 1))
10366 && XEXP (op0, 1) == XEXP (op1, 1)
10367 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10368 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
10369 && (INTVAL (XEXP (op0, 1))
10370 == (GET_MODE_BITSIZE (GET_MODE (op0))
10371 - (GET_MODE_BITSIZE
10372 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
10374 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
10375 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
10379 /* If both operands are the same constant shift, see if we can ignore the
10380 shift. We can if the shift is a rotate or if the bits shifted out of
10381 this shift are known to be zero for both inputs and if the type of
10382 comparison is compatible with the shift. */
10383 if (GET_CODE (op0) == GET_CODE (op1)
10384 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10385 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
10386 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
10387 && (code != GT && code != LT && code != GE && code != LE))
10388 || (GET_CODE (op0) == ASHIFTRT
10389 && (code != GTU && code != LTU
10390 && code != GEU && code != LEU)))
10391 && CONST_INT_P (XEXP (op0, 1))
10392 && INTVAL (XEXP (op0, 1)) >= 0
10393 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10394 && XEXP (op0, 1) == XEXP (op1, 1))
10396 enum machine_mode mode = GET_MODE (op0);
10397 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10398 int shift_count = INTVAL (XEXP (op0, 1));
10400 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
10401 mask &= (mask >> shift_count) << shift_count;
10402 else if (GET_CODE (op0) == ASHIFT)
10403 mask = (mask & (mask << shift_count)) >> shift_count;
10405 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
10406 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
10407 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
10412 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10413 SUBREGs are of the same mode, and, in both cases, the AND would
10414 be redundant if the comparison was done in the narrower mode,
10415 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10416 and the operand's possibly nonzero bits are 0xffffff01; in that case
10417 if we only care about QImode, we don't need the AND). This case
10418 occurs if the output mode of an scc insn is not SImode and
10419 STORE_FLAG_VALUE == 1 (e.g., the 386).
10421 Similarly, check for a case where the AND's are ZERO_EXTEND
10422 operations from some narrower mode even though a SUBREG is not
10425 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
10426 && CONST_INT_P (XEXP (op0, 1))
10427 && CONST_INT_P (XEXP (op1, 1)))
10429 rtx inner_op0 = XEXP (op0, 0);
10430 rtx inner_op1 = XEXP (op1, 0);
10431 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
10432 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
10435 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
10436 && (GET_MODE_SIZE (GET_MODE (inner_op0))
10437 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
10438 && (GET_MODE (SUBREG_REG (inner_op0))
10439 == GET_MODE (SUBREG_REG (inner_op1)))
10440 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
10441 <= HOST_BITS_PER_WIDE_INT)
10442 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
10443 GET_MODE (SUBREG_REG (inner_op0)))))
10444 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
10445 GET_MODE (SUBREG_REG (inner_op1))))))
10447 op0 = SUBREG_REG (inner_op0);
10448 op1 = SUBREG_REG (inner_op1);
10450 /* The resulting comparison is always unsigned since we masked
10451 off the original sign bit. */
10452 code = unsigned_condition (code);
10458 for (tmode = GET_CLASS_NARROWEST_MODE
10459 (GET_MODE_CLASS (GET_MODE (op0)));
10460 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
10461 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
10463 op0 = gen_lowpart (tmode, inner_op0);
10464 op1 = gen_lowpart (tmode, inner_op1);
10465 code = unsigned_condition (code);
10474 /* If both operands are NOT, we can strip off the outer operation
10475 and adjust the comparison code for swapped operands; similarly for
10476 NEG, except that this must be an equality comparison. */
10477 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
10478 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
10479 && (code == EQ || code == NE)))
10480 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
10486 /* If the first operand is a constant, swap the operands and adjust the
10487 comparison code appropriately, but don't do this if the second operand
10488 is already a constant integer. */
10489 if (swap_commutative_operands_p (op0, op1))
10491 tem = op0, op0 = op1, op1 = tem;
10492 code = swap_condition (code);
10495 /* We now enter a loop during which we will try to simplify the comparison.
10496 For the most part, we only are concerned with comparisons with zero,
10497 but some things may really be comparisons with zero but not start
10498 out looking that way. */
10500 while (CONST_INT_P (op1))
10502 enum machine_mode mode = GET_MODE (op0);
10503 unsigned int mode_width = GET_MODE_BITSIZE (mode);
10504 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10505 int equality_comparison_p;
10506 int sign_bit_comparison_p;
10507 int unsigned_comparison_p;
10508 HOST_WIDE_INT const_op;
10510 /* We only want to handle integral modes. This catches VOIDmode,
10511 CCmode, and the floating-point modes. An exception is that we
10512 can handle VOIDmode if OP0 is a COMPARE or a comparison
10515 if (GET_MODE_CLASS (mode) != MODE_INT
10516 && ! (mode == VOIDmode
10517 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
10520 /* Get the constant we are comparing against and turn off all bits
10521 not on in our mode. */
10522 const_op = INTVAL (op1);
10523 if (mode != VOIDmode)
10524 const_op = trunc_int_for_mode (const_op, mode);
10525 op1 = GEN_INT (const_op);
10527 /* If we are comparing against a constant power of two and the value
10528 being compared can only have that single bit nonzero (e.g., it was
10529 `and'ed with that bit), we can replace this with a comparison
10532 && (code == EQ || code == NE || code == GE || code == GEU
10533 || code == LT || code == LTU)
10534 && mode_width <= HOST_BITS_PER_WIDE_INT
10535 && exact_log2 (const_op) >= 0
10536 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10538 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10539 op1 = const0_rtx, const_op = 0;
10542 /* Similarly, if we are comparing a value known to be either -1 or
10543 0 with -1, change it to the opposite comparison against zero. */
10546 && (code == EQ || code == NE || code == GT || code == LE
10547 || code == GEU || code == LTU)
10548 && num_sign_bit_copies (op0, mode) == mode_width)
10550 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10551 op1 = const0_rtx, const_op = 0;
10554 /* Do some canonicalizations based on the comparison code. We prefer
10555 comparisons against zero and then prefer equality comparisons.
10556 If we can reduce the size of a constant, we will do that too. */
10561 /* < C is equivalent to <= (C - 1) */
10565 op1 = GEN_INT (const_op);
10567 /* ... fall through to LE case below. */
10573 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10577 op1 = GEN_INT (const_op);
10581 /* If we are doing a <= 0 comparison on a value known to have
10582 a zero sign bit, we can replace this with == 0. */
10583 else if (const_op == 0
10584 && mode_width <= HOST_BITS_PER_WIDE_INT
10585 && (nonzero_bits (op0, mode)
10586 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10591 /* >= C is equivalent to > (C - 1). */
10595 op1 = GEN_INT (const_op);
10597 /* ... fall through to GT below. */
10603 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10607 op1 = GEN_INT (const_op);
10611 /* If we are doing a > 0 comparison on a value known to have
10612 a zero sign bit, we can replace this with != 0. */
10613 else if (const_op == 0
10614 && mode_width <= HOST_BITS_PER_WIDE_INT
10615 && (nonzero_bits (op0, mode)
10616 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10621 /* < C is equivalent to <= (C - 1). */
10625 op1 = GEN_INT (const_op);
10627 /* ... fall through ... */
10630 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10631 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10632 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10634 const_op = 0, op1 = const0_rtx;
10642 /* unsigned <= 0 is equivalent to == 0 */
10646 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10647 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10648 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10650 const_op = 0, op1 = const0_rtx;
10656 /* >= C is equivalent to > (C - 1). */
10660 op1 = GEN_INT (const_op);
10662 /* ... fall through ... */
10665 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10666 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10667 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10669 const_op = 0, op1 = const0_rtx;
10677 /* unsigned > 0 is equivalent to != 0 */
10681 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10682 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10683 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10685 const_op = 0, op1 = const0_rtx;
10694 /* Compute some predicates to simplify code below. */
10696 equality_comparison_p = (code == EQ || code == NE);
10697 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
10698 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
10701 /* If this is a sign bit comparison and we can do arithmetic in
10702 MODE, say that we will only be needing the sign bit of OP0. */
10703 if (sign_bit_comparison_p
10704 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10705 op0 = force_to_mode (op0, mode,
10707 << (GET_MODE_BITSIZE (mode) - 1)),
10710 /* Now try cases based on the opcode of OP0. If none of the cases
10711 does a "continue", we exit this loop immediately after the
10714 switch (GET_CODE (op0))
10717 /* If we are extracting a single bit from a variable position in
10718 a constant that has only a single bit set and are comparing it
10719 with zero, we can convert this into an equality comparison
10720 between the position and the location of the single bit. */
10721 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
10722 have already reduced the shift count modulo the word size. */
10723 if (!SHIFT_COUNT_TRUNCATED
10724 && CONST_INT_P (XEXP (op0, 0))
10725 && XEXP (op0, 1) == const1_rtx
10726 && equality_comparison_p && const_op == 0
10727 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
10729 if (BITS_BIG_ENDIAN)
10731 enum machine_mode new_mode
10732 = mode_for_extraction (EP_extzv, 1);
10733 if (new_mode == MAX_MACHINE_MODE)
10734 i = BITS_PER_WORD - 1 - i;
10738 i = (GET_MODE_BITSIZE (mode) - 1 - i);
10742 op0 = XEXP (op0, 2);
10746 /* Result is nonzero iff shift count is equal to I. */
10747 code = reverse_condition (code);
10751 /* ... fall through ... */
10754 tem = expand_compound_operation (op0);
10763 /* If testing for equality, we can take the NOT of the constant. */
10764 if (equality_comparison_p
10765 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10767 op0 = XEXP (op0, 0);
10772 /* If just looking at the sign bit, reverse the sense of the
10774 if (sign_bit_comparison_p)
10776 op0 = XEXP (op0, 0);
10777 code = (code == GE ? LT : GE);
10783 /* If testing for equality, we can take the NEG of the constant. */
10784 if (equality_comparison_p
10785 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10787 op0 = XEXP (op0, 0);
10792 /* The remaining cases only apply to comparisons with zero. */
10796 /* When X is ABS or is known positive,
10797 (neg X) is < 0 if and only if X != 0. */
10799 if (sign_bit_comparison_p
10800 && (GET_CODE (XEXP (op0, 0)) == ABS
10801 || (mode_width <= HOST_BITS_PER_WIDE_INT
10802 && (nonzero_bits (XEXP (op0, 0), mode)
10803 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10805 op0 = XEXP (op0, 0);
10806 code = (code == LT ? NE : EQ);
10810 /* If we have NEG of something whose two high-order bits are the
10811 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10812 if (num_sign_bit_copies (op0, mode) >= 2)
10814 op0 = XEXP (op0, 0);
10815 code = swap_condition (code);
10821 /* If we are testing equality and our count is a constant, we
10822 can perform the inverse operation on our RHS. */
10823 if (equality_comparison_p && CONST_INT_P (XEXP (op0, 1))
10824 && (tem = simplify_binary_operation (ROTATERT, mode,
10825 op1, XEXP (op0, 1))) != 0)
10827 op0 = XEXP (op0, 0);
10832 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10833 a particular bit. Convert it to an AND of a constant of that
10834 bit. This will be converted into a ZERO_EXTRACT. */
10835 if (const_op == 0 && sign_bit_comparison_p
10836 && CONST_INT_P (XEXP (op0, 1))
10837 && mode_width <= HOST_BITS_PER_WIDE_INT)
10839 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10842 - INTVAL (XEXP (op0, 1)))));
10843 code = (code == LT ? NE : EQ);
10847 /* Fall through. */
10850 /* ABS is ignorable inside an equality comparison with zero. */
10851 if (const_op == 0 && equality_comparison_p)
10853 op0 = XEXP (op0, 0);
10859 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
10860 (compare FOO CONST) if CONST fits in FOO's mode and we
10861 are either testing inequality or have an unsigned
10862 comparison with ZERO_EXTEND or a signed comparison with
10863 SIGN_EXTEND. But don't do it if we don't have a compare
10864 insn of the given mode, since we'd have to revert it
10865 later on, and then we wouldn't know whether to sign- or
10867 mode = GET_MODE (XEXP (op0, 0));
10868 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10869 && ! unsigned_comparison_p
10870 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10871 && ((unsigned HOST_WIDE_INT) const_op
10872 < (((unsigned HOST_WIDE_INT) 1
10873 << (GET_MODE_BITSIZE (mode) - 1))))
10874 && have_insn_for (COMPARE, mode))
10876 op0 = XEXP (op0, 0);
10882 /* Check for the case where we are comparing A - C1 with C2, that is
10884 (subreg:MODE (plus (A) (-C1))) op (C2)
10886 with C1 a constant, and try to lift the SUBREG, i.e. to do the
10887 comparison in the wider mode. One of the following two conditions
10888 must be true in order for this to be valid:
10890 1. The mode extension results in the same bit pattern being added
10891 on both sides and the comparison is equality or unsigned. As
10892 C2 has been truncated to fit in MODE, the pattern can only be
10895 2. The mode extension results in the sign bit being copied on
10898 The difficulty here is that we have predicates for A but not for
10899 (A - C1) so we need to check that C1 is within proper bounds so
10900 as to perturbate A as little as possible. */
10902 if (mode_width <= HOST_BITS_PER_WIDE_INT
10903 && subreg_lowpart_p (op0)
10904 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) > mode_width
10905 && GET_CODE (SUBREG_REG (op0)) == PLUS
10906 && CONST_INT_P (XEXP (SUBREG_REG (op0), 1)))
10908 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
10909 rtx a = XEXP (SUBREG_REG (op0), 0);
10910 HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
10913 && (unsigned HOST_WIDE_INT) c1
10914 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
10915 && (equality_comparison_p || unsigned_comparison_p)
10916 /* (A - C1) zero-extends if it is positive and sign-extends
10917 if it is negative, C2 both zero- and sign-extends. */
10918 && ((0 == (nonzero_bits (a, inner_mode)
10919 & ~GET_MODE_MASK (mode))
10921 /* (A - C1) sign-extends if it is positive and 1-extends
10922 if it is negative, C2 both sign- and 1-extends. */
10923 || (num_sign_bit_copies (a, inner_mode)
10924 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10927 || ((unsigned HOST_WIDE_INT) c1
10928 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
10929 /* (A - C1) always sign-extends, like C2. */
10930 && num_sign_bit_copies (a, inner_mode)
10931 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10932 - (mode_width - 1))))
10934 op0 = SUBREG_REG (op0);
10939 /* If the inner mode is narrower and we are extracting the low part,
10940 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10941 if (subreg_lowpart_p (op0)
10942 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10943 /* Fall through */ ;
10947 /* ... fall through ... */
10950 mode = GET_MODE (XEXP (op0, 0));
10951 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10952 && (unsigned_comparison_p || equality_comparison_p)
10953 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10954 && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode))
10955 && have_insn_for (COMPARE, mode))
10957 op0 = XEXP (op0, 0);
10963 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10964 this for equality comparisons due to pathological cases involving
10966 if (equality_comparison_p
10967 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10968 op1, XEXP (op0, 1))))
10970 op0 = XEXP (op0, 0);
10975 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10976 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10977 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10979 op0 = XEXP (XEXP (op0, 0), 0);
10980 code = (code == LT ? EQ : NE);
10986 /* We used to optimize signed comparisons against zero, but that
10987 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10988 arrive here as equality comparisons, or (GEU, LTU) are
10989 optimized away. No need to special-case them. */
10991 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10992 (eq B (minus A C)), whichever simplifies. We can only do
10993 this for equality comparisons due to pathological cases involving
10995 if (equality_comparison_p
10996 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10997 XEXP (op0, 1), op1)))
10999 op0 = XEXP (op0, 0);
11004 if (equality_comparison_p
11005 && 0 != (tem = simplify_binary_operation (MINUS, mode,
11006 XEXP (op0, 0), op1)))
11008 op0 = XEXP (op0, 1);
11013 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11014 of bits in X minus 1, is one iff X > 0. */
11015 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
11016 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11017 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
11019 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11021 op0 = XEXP (op0, 1);
11022 code = (code == GE ? LE : GT);
11028 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11029 if C is zero or B is a constant. */
11030 if (equality_comparison_p
11031 && 0 != (tem = simplify_binary_operation (XOR, mode,
11032 XEXP (op0, 1), op1)))
11034 op0 = XEXP (op0, 0);
11041 case UNEQ: case LTGT:
11042 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
11043 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
11044 case UNORDERED: case ORDERED:
11045 /* We can't do anything if OP0 is a condition code value, rather
11046 than an actual data value. */
11048 || CC0_P (XEXP (op0, 0))
11049 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
11052 /* Get the two operands being compared. */
11053 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
11054 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
11056 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
11058 /* Check for the cases where we simply want the result of the
11059 earlier test or the opposite of that result. */
11060 if (code == NE || code == EQ
11061 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
11062 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11063 && (STORE_FLAG_VALUE
11064 & (((HOST_WIDE_INT) 1
11065 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
11066 && (code == LT || code == GE)))
11068 enum rtx_code new_code;
11069 if (code == LT || code == NE)
11070 new_code = GET_CODE (op0);
11072 new_code = reversed_comparison_code (op0, NULL);
11074 if (new_code != UNKNOWN)
11085 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11087 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
11088 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
11089 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11091 op0 = XEXP (op0, 1);
11092 code = (code == GE ? GT : LE);
11098 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11099 will be converted to a ZERO_EXTRACT later. */
11100 if (const_op == 0 && equality_comparison_p
11101 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11102 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
11104 op0 = simplify_and_const_int
11105 (NULL_RTX, mode, gen_rtx_LSHIFTRT (mode,
11107 XEXP (XEXP (op0, 0), 1)),
11108 (HOST_WIDE_INT) 1);
11112 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11113 zero and X is a comparison and C1 and C2 describe only bits set
11114 in STORE_FLAG_VALUE, we can compare with X. */
11115 if (const_op == 0 && equality_comparison_p
11116 && mode_width <= HOST_BITS_PER_WIDE_INT
11117 && CONST_INT_P (XEXP (op0, 1))
11118 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
11119 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11120 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
11121 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
11123 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11124 << INTVAL (XEXP (XEXP (op0, 0), 1)));
11125 if ((~STORE_FLAG_VALUE & mask) == 0
11126 && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
11127 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
11128 && COMPARISON_P (tem))))
11130 op0 = XEXP (XEXP (op0, 0), 0);
11135 /* If we are doing an equality comparison of an AND of a bit equal
11136 to the sign bit, replace this with a LT or GE comparison of
11137 the underlying value. */
11138 if (equality_comparison_p
11140 && CONST_INT_P (XEXP (op0, 1))
11141 && mode_width <= HOST_BITS_PER_WIDE_INT
11142 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11143 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11145 op0 = XEXP (op0, 0);
11146 code = (code == EQ ? GE : LT);
11150 /* If this AND operation is really a ZERO_EXTEND from a narrower
11151 mode, the constant fits within that mode, and this is either an
11152 equality or unsigned comparison, try to do this comparison in
11157 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11158 -> (ne:DI (reg:SI 4) (const_int 0))
11160 unless TRULY_NOOP_TRUNCATION allows it or the register is
11161 known to hold a value of the required mode the
11162 transformation is invalid. */
11163 if ((equality_comparison_p || unsigned_comparison_p)
11164 && CONST_INT_P (XEXP (op0, 1))
11165 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
11166 & GET_MODE_MASK (mode))
11168 && const_op >> i == 0
11169 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode
11170 && (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
11171 GET_MODE_BITSIZE (GET_MODE (op0)))
11172 || (REG_P (XEXP (op0, 0))
11173 && reg_truncated_to_mode (tmode, XEXP (op0, 0)))))
11175 op0 = gen_lowpart (tmode, XEXP (op0, 0));
11179 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11180 fits in both M1 and M2 and the SUBREG is either paradoxical
11181 or represents the low part, permute the SUBREG and the AND
11183 if (GET_CODE (XEXP (op0, 0)) == SUBREG)
11185 unsigned HOST_WIDE_INT c1;
11186 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
11187 /* Require an integral mode, to avoid creating something like
11189 if (SCALAR_INT_MODE_P (tmode)
11190 /* It is unsafe to commute the AND into the SUBREG if the
11191 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11192 not defined. As originally written the upper bits
11193 have a defined value due to the AND operation.
11194 However, if we commute the AND inside the SUBREG then
11195 they no longer have defined values and the meaning of
11196 the code has been changed. */
11198 #ifdef WORD_REGISTER_OPERATIONS
11199 || (mode_width > GET_MODE_BITSIZE (tmode)
11200 && mode_width <= BITS_PER_WORD)
11202 || (mode_width <= GET_MODE_BITSIZE (tmode)
11203 && subreg_lowpart_p (XEXP (op0, 0))))
11204 && CONST_INT_P (XEXP (op0, 1))
11205 && mode_width <= HOST_BITS_PER_WIDE_INT
11206 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
11207 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
11208 && (c1 & ~GET_MODE_MASK (tmode)) == 0
11210 && c1 != GET_MODE_MASK (tmode))
11212 op0 = simplify_gen_binary (AND, tmode,
11213 SUBREG_REG (XEXP (op0, 0)),
11214 gen_int_mode (c1, tmode));
11215 op0 = gen_lowpart (mode, op0);
11220 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
11221 if (const_op == 0 && equality_comparison_p
11222 && XEXP (op0, 1) == const1_rtx
11223 && GET_CODE (XEXP (op0, 0)) == NOT)
11225 op0 = simplify_and_const_int
11226 (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1);
11227 code = (code == NE ? EQ : NE);
11231 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11232 (eq (and (lshiftrt X) 1) 0).
11233 Also handle the case where (not X) is expressed using xor. */
11234 if (const_op == 0 && equality_comparison_p
11235 && XEXP (op0, 1) == const1_rtx
11236 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
11238 rtx shift_op = XEXP (XEXP (op0, 0), 0);
11239 rtx shift_count = XEXP (XEXP (op0, 0), 1);
11241 if (GET_CODE (shift_op) == NOT
11242 || (GET_CODE (shift_op) == XOR
11243 && CONST_INT_P (XEXP (shift_op, 1))
11244 && CONST_INT_P (shift_count)
11245 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
11246 && (INTVAL (XEXP (shift_op, 1))
11247 == (HOST_WIDE_INT) 1 << INTVAL (shift_count))))
11249 op0 = simplify_and_const_int
11251 gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count),
11252 (HOST_WIDE_INT) 1);
11253 code = (code == NE ? EQ : NE);
11260 /* If we have (compare (ashift FOO N) (const_int C)) and
11261 the high order N bits of FOO (N+1 if an inequality comparison)
11262 are known to be zero, we can do this by comparing FOO with C
11263 shifted right N bits so long as the low-order N bits of C are
11265 if (CONST_INT_P (XEXP (op0, 1))
11266 && INTVAL (XEXP (op0, 1)) >= 0
11267 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
11268 < HOST_BITS_PER_WIDE_INT)
11270 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
11271 && mode_width <= HOST_BITS_PER_WIDE_INT
11272 && (nonzero_bits (XEXP (op0, 0), mode)
11273 & ~(mask >> (INTVAL (XEXP (op0, 1))
11274 + ! equality_comparison_p))) == 0)
11276 /* We must perform a logical shift, not an arithmetic one,
11277 as we want the top N bits of C to be zero. */
11278 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
11280 temp >>= INTVAL (XEXP (op0, 1));
11281 op1 = gen_int_mode (temp, mode);
11282 op0 = XEXP (op0, 0);
11286 /* If we are doing a sign bit comparison, it means we are testing
11287 a particular bit. Convert it to the appropriate AND. */
11288 if (sign_bit_comparison_p && CONST_INT_P (XEXP (op0, 1))
11289 && mode_width <= HOST_BITS_PER_WIDE_INT)
11291 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11294 - INTVAL (XEXP (op0, 1)))));
11295 code = (code == LT ? NE : EQ);
11299 /* If this an equality comparison with zero and we are shifting
11300 the low bit to the sign bit, we can convert this to an AND of the
11302 if (const_op == 0 && equality_comparison_p
11303 && CONST_INT_P (XEXP (op0, 1))
11304 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11307 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11308 (HOST_WIDE_INT) 1);
11314 /* If this is an equality comparison with zero, we can do this
11315 as a logical shift, which might be much simpler. */
11316 if (equality_comparison_p && const_op == 0
11317 && CONST_INT_P (XEXP (op0, 1)))
11319 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
11321 INTVAL (XEXP (op0, 1)));
11325 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11326 do the comparison in a narrower mode. */
11327 if (! unsigned_comparison_p
11328 && CONST_INT_P (XEXP (op0, 1))
11329 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11330 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11331 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11332 MODE_INT, 1)) != BLKmode
11333 && (((unsigned HOST_WIDE_INT) const_op
11334 + (GET_MODE_MASK (tmode) >> 1) + 1)
11335 <= GET_MODE_MASK (tmode)))
11337 op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
11341 /* Likewise if OP0 is a PLUS of a sign extension with a
11342 constant, which is usually represented with the PLUS
11343 between the shifts. */
11344 if (! unsigned_comparison_p
11345 && CONST_INT_P (XEXP (op0, 1))
11346 && GET_CODE (XEXP (op0, 0)) == PLUS
11347 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11348 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
11349 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
11350 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11351 MODE_INT, 1)) != BLKmode
11352 && (((unsigned HOST_WIDE_INT) const_op
11353 + (GET_MODE_MASK (tmode) >> 1) + 1)
11354 <= GET_MODE_MASK (tmode)))
11356 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
11357 rtx add_const = XEXP (XEXP (op0, 0), 1);
11358 rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
11359 add_const, XEXP (op0, 1));
11361 op0 = simplify_gen_binary (PLUS, tmode,
11362 gen_lowpart (tmode, inner),
11367 /* ... fall through ... */
11369 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11370 the low order N bits of FOO are known to be zero, we can do this
11371 by comparing FOO with C shifted left N bits so long as no
11372 overflow occurs. */
11373 if (CONST_INT_P (XEXP (op0, 1))
11374 && INTVAL (XEXP (op0, 1)) >= 0
11375 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11376 && mode_width <= HOST_BITS_PER_WIDE_INT
11377 && (nonzero_bits (XEXP (op0, 0), mode)
11378 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
11379 && (((unsigned HOST_WIDE_INT) const_op
11380 + (GET_CODE (op0) != LSHIFTRT
11381 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
11384 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
11386 /* If the shift was logical, then we must make the condition
11388 if (GET_CODE (op0) == LSHIFTRT)
11389 code = unsigned_condition (code);
11391 const_op <<= INTVAL (XEXP (op0, 1));
11392 op1 = GEN_INT (const_op);
11393 op0 = XEXP (op0, 0);
11397 /* If we are using this shift to extract just the sign bit, we
11398 can replace this with an LT or GE comparison. */
11400 && (equality_comparison_p || sign_bit_comparison_p)
11401 && CONST_INT_P (XEXP (op0, 1))
11402 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11405 op0 = XEXP (op0, 0);
11406 code = (code == NE || code == GT ? LT : GE);
11418 /* Now make any compound operations involved in this comparison. Then,
11419 check for an outmost SUBREG on OP0 that is not doing anything or is
11420 paradoxical. The latter transformation must only be performed when
11421 it is known that the "extra" bits will be the same in op0 and op1 or
11422 that they don't matter. There are three cases to consider:
11424 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11425 care bits and we can assume they have any convenient value. So
11426 making the transformation is safe.
11428 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11429 In this case the upper bits of op0 are undefined. We should not make
11430 the simplification in that case as we do not know the contents of
11433 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11434 UNKNOWN. In that case we know those bits are zeros or ones. We must
11435 also be sure that they are the same as the upper bits of op1.
11437 We can never remove a SUBREG for a non-equality comparison because
11438 the sign bit is in a different place in the underlying object. */
11440 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
11441 op1 = make_compound_operation (op1, SET);
11443 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11444 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11445 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
11446 && (code == NE || code == EQ))
11448 if (GET_MODE_SIZE (GET_MODE (op0))
11449 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
11451 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11453 if (REG_P (SUBREG_REG (op0)))
11455 op0 = SUBREG_REG (op0);
11456 op1 = gen_lowpart (GET_MODE (op0), op1);
11459 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
11460 <= HOST_BITS_PER_WIDE_INT)
11461 && (nonzero_bits (SUBREG_REG (op0),
11462 GET_MODE (SUBREG_REG (op0)))
11463 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11465 tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
11467 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11468 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11469 op0 = SUBREG_REG (op0), op1 = tem;
11473 /* We now do the opposite procedure: Some machines don't have compare
11474 insns in all modes. If OP0's mode is an integer mode smaller than a
11475 word and we can't do a compare in that mode, see if there is a larger
11476 mode for which we can do the compare. There are a number of cases in
11477 which we can use the wider mode. */
11479 mode = GET_MODE (op0);
11480 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11481 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11482 && ! have_insn_for (COMPARE, mode))
11483 for (tmode = GET_MODE_WIDER_MODE (mode);
11485 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
11486 tmode = GET_MODE_WIDER_MODE (tmode))
11487 if (have_insn_for (COMPARE, tmode))
11491 /* If the only nonzero bits in OP0 and OP1 are those in the
11492 narrower mode and this is an equality or unsigned comparison,
11493 we can use the wider mode. Similarly for sign-extended
11494 values, in which case it is true for all comparisons. */
11495 zero_extended = ((code == EQ || code == NE
11496 || code == GEU || code == GTU
11497 || code == LEU || code == LTU)
11498 && (nonzero_bits (op0, tmode)
11499 & ~GET_MODE_MASK (mode)) == 0
11500 && ((CONST_INT_P (op1)
11501 || (nonzero_bits (op1, tmode)
11502 & ~GET_MODE_MASK (mode)) == 0)));
11505 || ((num_sign_bit_copies (op0, tmode)
11506 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11507 - GET_MODE_BITSIZE (mode)))
11508 && (num_sign_bit_copies (op1, tmode)
11509 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11510 - GET_MODE_BITSIZE (mode)))))
11512 /* If OP0 is an AND and we don't have an AND in MODE either,
11513 make a new AND in the proper mode. */
11514 if (GET_CODE (op0) == AND
11515 && !have_insn_for (AND, mode))
11516 op0 = simplify_gen_binary (AND, tmode,
11517 gen_lowpart (tmode,
11519 gen_lowpart (tmode,
11522 op0 = gen_lowpart (tmode, op0);
11523 if (zero_extended && CONST_INT_P (op1))
11524 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
11525 op1 = gen_lowpart (tmode, op1);
11529 /* If this is a test for negative, we can make an explicit
11530 test of the sign bit. */
11532 if (op1 == const0_rtx && (code == LT || code == GE)
11533 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11535 op0 = simplify_gen_binary (AND, tmode,
11536 gen_lowpart (tmode, op0),
11537 GEN_INT ((HOST_WIDE_INT) 1
11538 << (GET_MODE_BITSIZE (mode)
11540 code = (code == LT) ? NE : EQ;
11545 #ifdef CANONICALIZE_COMPARISON
11546 /* If this machine only supports a subset of valid comparisons, see if we
11547 can convert an unsupported one into a supported one. */
11548 CANONICALIZE_COMPARISON (code, op0, op1);
11557 /* Utility function for record_value_for_reg. Count number of
11562 enum rtx_code code = GET_CODE (x);
11566 if (GET_RTX_CLASS (code) == '2'
11567 || GET_RTX_CLASS (code) == 'c')
11569 rtx x0 = XEXP (x, 0);
11570 rtx x1 = XEXP (x, 1);
11573 return 1 + 2 * count_rtxs (x0);
11575 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
11576 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
11577 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11578 return 2 + 2 * count_rtxs (x0)
11579 + count_rtxs (x == XEXP (x1, 0)
11580 ? XEXP (x1, 1) : XEXP (x1, 0));
11582 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
11583 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
11584 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11585 return 2 + 2 * count_rtxs (x1)
11586 + count_rtxs (x == XEXP (x0, 0)
11587 ? XEXP (x0, 1) : XEXP (x0, 0));
11590 fmt = GET_RTX_FORMAT (code);
11591 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11593 ret += count_rtxs (XEXP (x, i));
11594 else if (fmt[i] == 'E')
11595 for (j = 0; j < XVECLEN (x, i); j++)
11596 ret += count_rtxs (XVECEXP (x, i, j));
11601 /* Utility function for following routine. Called when X is part of a value
11602 being stored into last_set_value. Sets last_set_table_tick
11603 for each register mentioned. Similar to mention_regs in cse.c */
11606 update_table_tick (rtx x)
11608 enum rtx_code code = GET_CODE (x);
11609 const char *fmt = GET_RTX_FORMAT (code);
11614 unsigned int regno = REGNO (x);
11615 unsigned int endregno = END_REGNO (x);
11618 for (r = regno; r < endregno; r++)
11620 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, r);
11621 rsp->last_set_table_tick = label_tick;
11627 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11630 /* Check for identical subexpressions. If x contains
11631 identical subexpression we only have to traverse one of
11633 if (i == 0 && ARITHMETIC_P (x))
11635 /* Note that at this point x1 has already been
11637 rtx x0 = XEXP (x, 0);
11638 rtx x1 = XEXP (x, 1);
11640 /* If x0 and x1 are identical then there is no need to
11645 /* If x0 is identical to a subexpression of x1 then while
11646 processing x1, x0 has already been processed. Thus we
11647 are done with x. */
11648 if (ARITHMETIC_P (x1)
11649 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11652 /* If x1 is identical to a subexpression of x0 then we
11653 still have to process the rest of x0. */
11654 if (ARITHMETIC_P (x0)
11655 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11657 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
11662 update_table_tick (XEXP (x, i));
11664 else if (fmt[i] == 'E')
11665 for (j = 0; j < XVECLEN (x, i); j++)
11666 update_table_tick (XVECEXP (x, i, j));
11669 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11670 are saying that the register is clobbered and we no longer know its
11671 value. If INSN is zero, don't update reg_stat[].last_set; this is
11672 only permitted with VALUE also zero and is used to invalidate the
11676 record_value_for_reg (rtx reg, rtx insn, rtx value)
11678 unsigned int regno = REGNO (reg);
11679 unsigned int endregno = END_REGNO (reg);
11681 reg_stat_type *rsp;
11683 /* If VALUE contains REG and we have a previous value for REG, substitute
11684 the previous value. */
11685 if (value && insn && reg_overlap_mentioned_p (reg, value))
11689 /* Set things up so get_last_value is allowed to see anything set up to
11691 subst_low_luid = DF_INSN_LUID (insn);
11692 tem = get_last_value (reg);
11694 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11695 it isn't going to be useful and will take a lot of time to process,
11696 so just use the CLOBBER. */
11700 if (ARITHMETIC_P (tem)
11701 && GET_CODE (XEXP (tem, 0)) == CLOBBER
11702 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
11703 tem = XEXP (tem, 0);
11704 else if (count_occurrences (value, reg, 1) >= 2)
11706 /* If there are two or more occurrences of REG in VALUE,
11707 prevent the value from growing too much. */
11708 if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
11709 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
11712 value = replace_rtx (copy_rtx (value), reg, tem);
11716 /* For each register modified, show we don't know its value, that
11717 we don't know about its bitwise content, that its value has been
11718 updated, and that we don't know the location of the death of the
11720 for (i = regno; i < endregno; i++)
11722 rsp = VEC_index (reg_stat_type, reg_stat, i);
11725 rsp->last_set = insn;
11727 rsp->last_set_value = 0;
11728 rsp->last_set_mode = VOIDmode;
11729 rsp->last_set_nonzero_bits = 0;
11730 rsp->last_set_sign_bit_copies = 0;
11731 rsp->last_death = 0;
11732 rsp->truncated_to_mode = VOIDmode;
11735 /* Mark registers that are being referenced in this value. */
11737 update_table_tick (value);
11739 /* Now update the status of each register being set.
11740 If someone is using this register in this block, set this register
11741 to invalid since we will get confused between the two lives in this
11742 basic block. This makes using this register always invalid. In cse, we
11743 scan the table to invalidate all entries using this register, but this
11744 is too much work for us. */
11746 for (i = regno; i < endregno; i++)
11748 rsp = VEC_index (reg_stat_type, reg_stat, i);
11749 rsp->last_set_label = label_tick;
11751 || (value && rsp->last_set_table_tick >= label_tick_ebb_start))
11752 rsp->last_set_invalid = 1;
11754 rsp->last_set_invalid = 0;
11757 /* The value being assigned might refer to X (like in "x++;"). In that
11758 case, we must replace it with (clobber (const_int 0)) to prevent
11760 rsp = VEC_index (reg_stat_type, reg_stat, regno);
11761 if (value && ! get_last_value_validate (&value, insn,
11762 rsp->last_set_label, 0))
11764 value = copy_rtx (value);
11765 if (! get_last_value_validate (&value, insn,
11766 rsp->last_set_label, 1))
11770 /* For the main register being modified, update the value, the mode, the
11771 nonzero bits, and the number of sign bit copies. */
11773 rsp->last_set_value = value;
11777 enum machine_mode mode = GET_MODE (reg);
11778 subst_low_luid = DF_INSN_LUID (insn);
11779 rsp->last_set_mode = mode;
11780 if (GET_MODE_CLASS (mode) == MODE_INT
11781 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11782 mode = nonzero_bits_mode;
11783 rsp->last_set_nonzero_bits = nonzero_bits (value, mode);
11784 rsp->last_set_sign_bit_copies
11785 = num_sign_bit_copies (value, GET_MODE (reg));
11789 /* Called via note_stores from record_dead_and_set_regs to handle one
11790 SET or CLOBBER in an insn. DATA is the instruction in which the
11791 set is occurring. */
11794 record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
11796 rtx record_dead_insn = (rtx) data;
11798 if (GET_CODE (dest) == SUBREG)
11799 dest = SUBREG_REG (dest);
11801 if (!record_dead_insn)
11804 record_value_for_reg (dest, NULL_RTX, NULL_RTX);
11810 /* If we are setting the whole register, we know its value. Otherwise
11811 show that we don't know the value. We can handle SUBREG in
11813 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11814 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11815 else if (GET_CODE (setter) == SET
11816 && GET_CODE (SET_DEST (setter)) == SUBREG
11817 && SUBREG_REG (SET_DEST (setter)) == dest
11818 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11819 && subreg_lowpart_p (SET_DEST (setter)))
11820 record_value_for_reg (dest, record_dead_insn,
11821 gen_lowpart (GET_MODE (dest),
11822 SET_SRC (setter)));
11824 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11826 else if (MEM_P (dest)
11827 /* Ignore pushes, they clobber nothing. */
11828 && ! push_operand (dest, GET_MODE (dest)))
11829 mem_last_set = DF_INSN_LUID (record_dead_insn);
11832 /* Update the records of when each REG was most recently set or killed
11833 for the things done by INSN. This is the last thing done in processing
11834 INSN in the combiner loop.
11836 We update reg_stat[], in particular fields last_set, last_set_value,
11837 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
11838 last_death, and also the similar information mem_last_set (which insn
11839 most recently modified memory) and last_call_luid (which insn was the
11840 most recent subroutine call). */
11843 record_dead_and_set_regs (rtx insn)
11848 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11850 if (REG_NOTE_KIND (link) == REG_DEAD
11851 && REG_P (XEXP (link, 0)))
11853 unsigned int regno = REGNO (XEXP (link, 0));
11854 unsigned int endregno = END_REGNO (XEXP (link, 0));
11856 for (i = regno; i < endregno; i++)
11858 reg_stat_type *rsp;
11860 rsp = VEC_index (reg_stat_type, reg_stat, i);
11861 rsp->last_death = insn;
11864 else if (REG_NOTE_KIND (link) == REG_INC)
11865 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11870 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11871 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11873 reg_stat_type *rsp;
11875 rsp = VEC_index (reg_stat_type, reg_stat, i);
11876 rsp->last_set_invalid = 1;
11877 rsp->last_set = insn;
11878 rsp->last_set_value = 0;
11879 rsp->last_set_mode = VOIDmode;
11880 rsp->last_set_nonzero_bits = 0;
11881 rsp->last_set_sign_bit_copies = 0;
11882 rsp->last_death = 0;
11883 rsp->truncated_to_mode = VOIDmode;
11886 last_call_luid = mem_last_set = DF_INSN_LUID (insn);
11888 /* We can't combine into a call pattern. Remember, though, that
11889 the return value register is set at this LUID. We could
11890 still replace a register with the return value from the
11891 wrong subroutine call! */
11892 note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
11895 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11898 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11899 register present in the SUBREG, so for each such SUBREG go back and
11900 adjust nonzero and sign bit information of the registers that are
11901 known to have some zero/sign bits set.
11903 This is needed because when combine blows the SUBREGs away, the
11904 information on zero/sign bits is lost and further combines can be
11905 missed because of that. */
11908 record_promoted_value (rtx insn, rtx subreg)
11911 unsigned int regno = REGNO (SUBREG_REG (subreg));
11912 enum machine_mode mode = GET_MODE (subreg);
11914 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11917 for (links = LOG_LINKS (insn); links;)
11919 reg_stat_type *rsp;
11921 insn = XEXP (links, 0);
11922 set = single_set (insn);
11924 if (! set || !REG_P (SET_DEST (set))
11925 || REGNO (SET_DEST (set)) != regno
11926 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11928 links = XEXP (links, 1);
11932 rsp = VEC_index (reg_stat_type, reg_stat, regno);
11933 if (rsp->last_set == insn)
11935 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11936 rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode);
11939 if (REG_P (SET_SRC (set)))
11941 regno = REGNO (SET_SRC (set));
11942 links = LOG_LINKS (insn);
11949 /* Check if X, a register, is known to contain a value already
11950 truncated to MODE. In this case we can use a subreg to refer to
11951 the truncated value even though in the generic case we would need
11952 an explicit truncation. */
11955 reg_truncated_to_mode (enum machine_mode mode, const_rtx x)
11957 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
11958 enum machine_mode truncated = rsp->truncated_to_mode;
11961 || rsp->truncation_label < label_tick_ebb_start)
11963 if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
11965 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
11966 GET_MODE_BITSIZE (truncated)))
11971 /* Callback for for_each_rtx. If *P is a hard reg or a subreg record the mode
11972 that the register is accessed in. For non-TRULY_NOOP_TRUNCATION targets we
11973 might be able to turn a truncate into a subreg using this information.
11974 Return -1 if traversing *P is complete or 0 otherwise. */
11977 record_truncated_value (rtx *p, void *data ATTRIBUTE_UNUSED)
11980 enum machine_mode truncated_mode;
11981 reg_stat_type *rsp;
11983 if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
11985 enum machine_mode original_mode = GET_MODE (SUBREG_REG (x));
11986 truncated_mode = GET_MODE (x);
11988 if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
11991 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (truncated_mode),
11992 GET_MODE_BITSIZE (original_mode)))
11995 x = SUBREG_REG (x);
11997 /* ??? For hard-regs we now record everything. We might be able to
11998 optimize this using last_set_mode. */
11999 else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
12000 truncated_mode = GET_MODE (x);
12004 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
12005 if (rsp->truncated_to_mode == 0
12006 || rsp->truncation_label < label_tick_ebb_start
12007 || (GET_MODE_SIZE (truncated_mode)
12008 < GET_MODE_SIZE (rsp->truncated_to_mode)))
12010 rsp->truncated_to_mode = truncated_mode;
12011 rsp->truncation_label = label_tick;
12017 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12018 the modes they are used in. This can help truning TRUNCATEs into
12022 record_truncated_values (rtx *x, void *data ATTRIBUTE_UNUSED)
12024 for_each_rtx (x, record_truncated_value, NULL);
12027 /* Scan X for promoted SUBREGs. For each one found,
12028 note what it implies to the registers used in it. */
12031 check_promoted_subreg (rtx insn, rtx x)
12033 if (GET_CODE (x) == SUBREG
12034 && SUBREG_PROMOTED_VAR_P (x)
12035 && REG_P (SUBREG_REG (x)))
12036 record_promoted_value (insn, x);
12039 const char *format = GET_RTX_FORMAT (GET_CODE (x));
12042 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
12046 check_promoted_subreg (insn, XEXP (x, i));
12050 if (XVEC (x, i) != 0)
12051 for (j = 0; j < XVECLEN (x, i); j++)
12052 check_promoted_subreg (insn, XVECEXP (x, i, j));
12058 /* Utility routine for the following function. Verify that all the registers
12059 mentioned in *LOC are valid when *LOC was part of a value set when
12060 label_tick == TICK. Return 0 if some are not.
12062 If REPLACE is nonzero, replace the invalid reference with
12063 (clobber (const_int 0)) and return 1. This replacement is useful because
12064 we often can get useful information about the form of a value (e.g., if
12065 it was produced by a shift that always produces -1 or 0) even though
12066 we don't know exactly what registers it was produced from. */
12069 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
12072 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
12073 int len = GET_RTX_LENGTH (GET_CODE (x));
12078 unsigned int regno = REGNO (x);
12079 unsigned int endregno = END_REGNO (x);
12082 for (j = regno; j < endregno; j++)
12084 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, j);
12085 if (rsp->last_set_invalid
12086 /* If this is a pseudo-register that was only set once and not
12087 live at the beginning of the function, it is always valid. */
12088 || (! (regno >= FIRST_PSEUDO_REGISTER
12089 && REG_N_SETS (regno) == 1
12090 && (!REGNO_REG_SET_P
12091 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno)))
12092 && rsp->last_set_label > tick))
12095 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12102 /* If this is a memory reference, make sure that there were
12103 no stores after it that might have clobbered the value. We don't
12104 have alias info, so we assume any store invalidates it. */
12105 else if (MEM_P (x) && !MEM_READONLY_P (x)
12106 && DF_INSN_LUID (insn) <= mem_last_set)
12109 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12113 for (i = 0; i < len; i++)
12117 /* Check for identical subexpressions. If x contains
12118 identical subexpression we only have to traverse one of
12120 if (i == 1 && ARITHMETIC_P (x))
12122 /* Note that at this point x0 has already been checked
12123 and found valid. */
12124 rtx x0 = XEXP (x, 0);
12125 rtx x1 = XEXP (x, 1);
12127 /* If x0 and x1 are identical then x is also valid. */
12131 /* If x1 is identical to a subexpression of x0 then
12132 while checking x0, x1 has already been checked. Thus
12133 it is valid and so as x. */
12134 if (ARITHMETIC_P (x0)
12135 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12138 /* If x0 is identical to a subexpression of x1 then x is
12139 valid iff the rest of x1 is valid. */
12140 if (ARITHMETIC_P (x1)
12141 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12143 get_last_value_validate (&XEXP (x1,
12144 x0 == XEXP (x1, 0) ? 1 : 0),
12145 insn, tick, replace);
12148 if (get_last_value_validate (&XEXP (x, i), insn, tick,
12152 else if (fmt[i] == 'E')
12153 for (j = 0; j < XVECLEN (x, i); j++)
12154 if (get_last_value_validate (&XVECEXP (x, i, j),
12155 insn, tick, replace) == 0)
12159 /* If we haven't found a reason for it to be invalid, it is valid. */
12163 /* Get the last value assigned to X, if known. Some registers
12164 in the value may be replaced with (clobber (const_int 0)) if their value
12165 is known longer known reliably. */
12168 get_last_value (const_rtx x)
12170 unsigned int regno;
12172 reg_stat_type *rsp;
12174 /* If this is a non-paradoxical SUBREG, get the value of its operand and
12175 then convert it to the desired mode. If this is a paradoxical SUBREG,
12176 we cannot predict what values the "extra" bits might have. */
12177 if (GET_CODE (x) == SUBREG
12178 && subreg_lowpart_p (x)
12179 && (GET_MODE_SIZE (GET_MODE (x))
12180 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
12181 && (value = get_last_value (SUBREG_REG (x))) != 0)
12182 return gen_lowpart (GET_MODE (x), value);
12188 rsp = VEC_index (reg_stat_type, reg_stat, regno);
12189 value = rsp->last_set_value;
12191 /* If we don't have a value, or if it isn't for this basic block and
12192 it's either a hard register, set more than once, or it's a live
12193 at the beginning of the function, return 0.
12195 Because if it's not live at the beginning of the function then the reg
12196 is always set before being used (is never used without being set).
12197 And, if it's set only once, and it's always set before use, then all
12198 uses must have the same last value, even if it's not from this basic
12202 || (rsp->last_set_label < label_tick_ebb_start
12203 && (regno < FIRST_PSEUDO_REGISTER
12204 || REG_N_SETS (regno) != 1
12206 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno))))
12209 /* If the value was set in a later insn than the ones we are processing,
12210 we can't use it even if the register was only set once. */
12211 if (rsp->last_set_label == label_tick
12212 && DF_INSN_LUID (rsp->last_set) >= subst_low_luid)
12215 /* If the value has all its registers valid, return it. */
12216 if (get_last_value_validate (&value, rsp->last_set,
12217 rsp->last_set_label, 0))
12220 /* Otherwise, make a copy and replace any invalid register with
12221 (clobber (const_int 0)). If that fails for some reason, return 0. */
12223 value = copy_rtx (value);
12224 if (get_last_value_validate (&value, rsp->last_set,
12225 rsp->last_set_label, 1))
12231 /* Return nonzero if expression X refers to a REG or to memory
12232 that is set in an instruction more recent than FROM_LUID. */
12235 use_crosses_set_p (const_rtx x, int from_luid)
12239 enum rtx_code code = GET_CODE (x);
12243 unsigned int regno = REGNO (x);
12244 unsigned endreg = END_REGNO (x);
12246 #ifdef PUSH_ROUNDING
12247 /* Don't allow uses of the stack pointer to be moved,
12248 because we don't know whether the move crosses a push insn. */
12249 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
12252 for (; regno < endreg; regno++)
12254 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
12256 && rsp->last_set_label == label_tick
12257 && DF_INSN_LUID (rsp->last_set) > from_luid)
12263 if (code == MEM && mem_last_set > from_luid)
12266 fmt = GET_RTX_FORMAT (code);
12268 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12273 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12274 if (use_crosses_set_p (XVECEXP (x, i, j), from_luid))
12277 else if (fmt[i] == 'e'
12278 && use_crosses_set_p (XEXP (x, i), from_luid))
12284 /* Define three variables used for communication between the following
12287 static unsigned int reg_dead_regno, reg_dead_endregno;
12288 static int reg_dead_flag;
12290 /* Function called via note_stores from reg_dead_at_p.
12292 If DEST is within [reg_dead_regno, reg_dead_endregno), set
12293 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
12296 reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
12298 unsigned int regno, endregno;
12303 regno = REGNO (dest);
12304 endregno = END_REGNO (dest);
12305 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
12306 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
12309 /* Return nonzero if REG is known to be dead at INSN.
12311 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12312 referencing REG, it is dead. If we hit a SET referencing REG, it is
12313 live. Otherwise, see if it is live or dead at the start of the basic
12314 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12315 must be assumed to be always live. */
12318 reg_dead_at_p (rtx reg, rtx insn)
12323 /* Set variables for reg_dead_at_p_1. */
12324 reg_dead_regno = REGNO (reg);
12325 reg_dead_endregno = END_REGNO (reg);
12329 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
12330 we allow the machine description to decide whether use-and-clobber
12331 patterns are OK. */
12332 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
12334 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12335 if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
12339 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12340 beginning of basic block. */
12341 block = BLOCK_FOR_INSN (insn);
12346 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
12348 return reg_dead_flag == 1 ? 1 : 0;
12350 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
12354 if (insn == BB_HEAD (block))
12357 insn = PREV_INSN (insn);
12360 /* Look at live-in sets for the basic block that we were in. */
12361 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12362 if (REGNO_REG_SET_P (df_get_live_in (block), i))
12368 /* Note hard registers in X that are used. */
12371 mark_used_regs_combine (rtx x)
12373 RTX_CODE code = GET_CODE (x);
12374 unsigned int regno;
12387 case ADDR_DIFF_VEC:
12390 /* CC0 must die in the insn after it is set, so we don't need to take
12391 special note of it here. */
12397 /* If we are clobbering a MEM, mark any hard registers inside the
12398 address as used. */
12399 if (MEM_P (XEXP (x, 0)))
12400 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
12405 /* A hard reg in a wide mode may really be multiple registers.
12406 If so, mark all of them just like the first. */
12407 if (regno < FIRST_PSEUDO_REGISTER)
12409 /* None of this applies to the stack, frame or arg pointers. */
12410 if (regno == STACK_POINTER_REGNUM
12411 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
12412 || regno == HARD_FRAME_POINTER_REGNUM
12414 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12415 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
12417 || regno == FRAME_POINTER_REGNUM)
12420 add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno);
12426 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12428 rtx testreg = SET_DEST (x);
12430 while (GET_CODE (testreg) == SUBREG
12431 || GET_CODE (testreg) == ZERO_EXTRACT
12432 || GET_CODE (testreg) == STRICT_LOW_PART)
12433 testreg = XEXP (testreg, 0);
12435 if (MEM_P (testreg))
12436 mark_used_regs_combine (XEXP (testreg, 0));
12438 mark_used_regs_combine (SET_SRC (x));
12446 /* Recursively scan the operands of this expression. */
12449 const char *fmt = GET_RTX_FORMAT (code);
12451 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12454 mark_used_regs_combine (XEXP (x, i));
12455 else if (fmt[i] == 'E')
12459 for (j = 0; j < XVECLEN (x, i); j++)
12460 mark_used_regs_combine (XVECEXP (x, i, j));
12466 /* Remove register number REGNO from the dead registers list of INSN.
12468 Return the note used to record the death, if there was one. */
12471 remove_death (unsigned int regno, rtx insn)
12473 rtx note = find_regno_note (insn, REG_DEAD, regno);
12476 remove_note (insn, note);
12481 /* For each register (hardware or pseudo) used within expression X, if its
12482 death is in an instruction with luid between FROM_LUID (inclusive) and
12483 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12484 list headed by PNOTES.
12486 That said, don't move registers killed by maybe_kill_insn.
12488 This is done when X is being merged by combination into TO_INSN. These
12489 notes will then be distributed as needed. */
12492 move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx to_insn,
12497 enum rtx_code code = GET_CODE (x);
12501 unsigned int regno = REGNO (x);
12502 rtx where_dead = VEC_index (reg_stat_type, reg_stat, regno)->last_death;
12504 /* Don't move the register if it gets killed in between from and to. */
12505 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
12506 && ! reg_referenced_p (x, maybe_kill_insn))
12510 && BLOCK_FOR_INSN (where_dead) == BLOCK_FOR_INSN (to_insn)
12511 && DF_INSN_LUID (where_dead) >= from_luid
12512 && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn))
12514 rtx note = remove_death (regno, where_dead);
12516 /* It is possible for the call above to return 0. This can occur
12517 when last_death points to I2 or I1 that we combined with.
12518 In that case make a new note.
12520 We must also check for the case where X is a hard register
12521 and NOTE is a death note for a range of hard registers
12522 including X. In that case, we must put REG_DEAD notes for
12523 the remaining registers in place of NOTE. */
12525 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
12526 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12527 > GET_MODE_SIZE (GET_MODE (x))))
12529 unsigned int deadregno = REGNO (XEXP (note, 0));
12530 unsigned int deadend = END_HARD_REGNO (XEXP (note, 0));
12531 unsigned int ourend = END_HARD_REGNO (x);
12534 for (i = deadregno; i < deadend; i++)
12535 if (i < regno || i >= ourend)
12536 add_reg_note (where_dead, REG_DEAD, regno_reg_rtx[i]);
12539 /* If we didn't find any note, or if we found a REG_DEAD note that
12540 covers only part of the given reg, and we have a multi-reg hard
12541 register, then to be safe we must check for REG_DEAD notes
12542 for each register other than the first. They could have
12543 their own REG_DEAD notes lying around. */
12544 else if ((note == 0
12546 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12547 < GET_MODE_SIZE (GET_MODE (x)))))
12548 && regno < FIRST_PSEUDO_REGISTER
12549 && hard_regno_nregs[regno][GET_MODE (x)] > 1)
12551 unsigned int ourend = END_HARD_REGNO (x);
12552 unsigned int i, offset;
12556 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
12560 for (i = regno + offset; i < ourend; i++)
12561 move_deaths (regno_reg_rtx[i],
12562 maybe_kill_insn, from_luid, to_insn, &oldnotes);
12565 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
12567 XEXP (note, 1) = *pnotes;
12571 *pnotes = alloc_reg_note (REG_DEAD, x, *pnotes);
12577 else if (GET_CODE (x) == SET)
12579 rtx dest = SET_DEST (x);
12581 move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes);
12583 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12584 that accesses one word of a multi-word item, some
12585 piece of everything register in the expression is used by
12586 this insn, so remove any old death. */
12587 /* ??? So why do we test for equality of the sizes? */
12589 if (GET_CODE (dest) == ZERO_EXTRACT
12590 || GET_CODE (dest) == STRICT_LOW_PART
12591 || (GET_CODE (dest) == SUBREG
12592 && (((GET_MODE_SIZE (GET_MODE (dest))
12593 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
12594 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
12595 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
12597 move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes);
12601 /* If this is some other SUBREG, we know it replaces the entire
12602 value, so use that as the destination. */
12603 if (GET_CODE (dest) == SUBREG)
12604 dest = SUBREG_REG (dest);
12606 /* If this is a MEM, adjust deaths of anything used in the address.
12607 For a REG (the only other possibility), the entire value is
12608 being replaced so the old value is not used in this insn. */
12611 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid,
12616 else if (GET_CODE (x) == CLOBBER)
12619 len = GET_RTX_LENGTH (code);
12620 fmt = GET_RTX_FORMAT (code);
12622 for (i = 0; i < len; i++)
12627 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12628 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid,
12631 else if (fmt[i] == 'e')
12632 move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes);
12636 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12637 pattern of an insn. X must be a REG. */
12640 reg_bitfield_target_p (rtx x, rtx body)
12644 if (GET_CODE (body) == SET)
12646 rtx dest = SET_DEST (body);
12648 unsigned int regno, tregno, endregno, endtregno;
12650 if (GET_CODE (dest) == ZERO_EXTRACT)
12651 target = XEXP (dest, 0);
12652 else if (GET_CODE (dest) == STRICT_LOW_PART)
12653 target = SUBREG_REG (XEXP (dest, 0));
12657 if (GET_CODE (target) == SUBREG)
12658 target = SUBREG_REG (target);
12660 if (!REG_P (target))
12663 tregno = REGNO (target), regno = REGNO (x);
12664 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
12665 return target == x;
12667 endtregno = end_hard_regno (GET_MODE (target), tregno);
12668 endregno = end_hard_regno (GET_MODE (x), regno);
12670 return endregno > tregno && regno < endtregno;
12673 else if (GET_CODE (body) == PARALLEL)
12674 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
12675 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
12681 /* Return the next insn after INSN that is neither a NOTE nor a
12682 DEBUG_INSN. This routine does not look inside SEQUENCEs. */
12685 next_nonnote_nondebug_insn (rtx insn)
12689 insn = NEXT_INSN (insn);
12694 if (DEBUG_INSN_P (insn))
12704 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12705 as appropriate. I3 and I2 are the insns resulting from the combination
12706 insns including FROM (I2 may be zero).
12708 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
12709 not need REG_DEAD notes because they are being substituted for. This
12710 saves searching in the most common cases.
12712 Each note in the list is either ignored or placed on some insns, depending
12713 on the type of note. */
12716 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
12719 rtx note, next_note;
12722 for (note = notes; note; note = next_note)
12724 rtx place = 0, place2 = 0;
12726 next_note = XEXP (note, 1);
12727 switch (REG_NOTE_KIND (note))
12731 /* Doesn't matter much where we put this, as long as it's somewhere.
12732 It is preferable to keep these notes on branches, which is most
12733 likely to be i3. */
12737 case REG_VALUE_PROFILE:
12738 /* Just get rid of this note, as it is unused later anyway. */
12741 case REG_NON_LOCAL_GOTO:
12746 gcc_assert (i2 && JUMP_P (i2));
12751 case REG_EH_REGION:
12752 /* These notes must remain with the call or trapping instruction. */
12755 else if (i2 && CALL_P (i2))
12759 gcc_assert (flag_non_call_exceptions);
12760 if (may_trap_p (i3))
12762 else if (i2 && may_trap_p (i2))
12764 /* ??? Otherwise assume we've combined things such that we
12765 can now prove that the instructions can't trap. Drop the
12766 note in this case. */
12772 /* These notes must remain with the call. It should not be
12773 possible for both I2 and I3 to be a call. */
12778 gcc_assert (i2 && CALL_P (i2));
12784 /* Any clobbers for i3 may still exist, and so we must process
12785 REG_UNUSED notes from that insn.
12787 Any clobbers from i2 or i1 can only exist if they were added by
12788 recog_for_combine. In that case, recog_for_combine created the
12789 necessary REG_UNUSED notes. Trying to keep any original
12790 REG_UNUSED notes from these insns can cause incorrect output
12791 if it is for the same register as the original i3 dest.
12792 In that case, we will notice that the register is set in i3,
12793 and then add a REG_UNUSED note for the destination of i3, which
12794 is wrong. However, it is possible to have REG_UNUSED notes from
12795 i2 or i1 for register which were both used and clobbered, so
12796 we keep notes from i2 or i1 if they will turn into REG_DEAD
12799 /* If this register is set or clobbered in I3, put the note there
12800 unless there is one already. */
12801 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
12803 if (from_insn != i3)
12806 if (! (REG_P (XEXP (note, 0))
12807 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
12808 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
12811 /* Otherwise, if this register is used by I3, then this register
12812 now dies here, so we must put a REG_DEAD note here unless there
12814 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
12815 && ! (REG_P (XEXP (note, 0))
12816 ? find_regno_note (i3, REG_DEAD,
12817 REGNO (XEXP (note, 0)))
12818 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
12820 PUT_REG_NOTE_KIND (note, REG_DEAD);
12828 /* These notes say something about results of an insn. We can
12829 only support them if they used to be on I3 in which case they
12830 remain on I3. Otherwise they are ignored.
12832 If the note refers to an expression that is not a constant, we
12833 must also ignore the note since we cannot tell whether the
12834 equivalence is still true. It might be possible to do
12835 slightly better than this (we only have a problem if I2DEST
12836 or I1DEST is present in the expression), but it doesn't
12837 seem worth the trouble. */
12839 if (from_insn == i3
12840 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
12845 /* These notes say something about how a register is used. They must
12846 be present on any use of the register in I2 or I3. */
12847 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12850 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12859 case REG_LABEL_TARGET:
12860 case REG_LABEL_OPERAND:
12861 /* This can show up in several ways -- either directly in the
12862 pattern, or hidden off in the constant pool with (or without?)
12863 a REG_EQUAL note. */
12864 /* ??? Ignore the without-reg_equal-note problem for now. */
12865 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12866 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12867 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12868 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12872 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12873 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12874 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12875 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12883 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
12884 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
12886 if (place && JUMP_P (place)
12887 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
12888 && (JUMP_LABEL (place) == NULL
12889 || JUMP_LABEL (place) == XEXP (note, 0)))
12891 rtx label = JUMP_LABEL (place);
12894 JUMP_LABEL (place) = XEXP (note, 0);
12895 else if (LABEL_P (label))
12896 LABEL_NUSES (label)--;
12899 if (place2 && JUMP_P (place2)
12900 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
12901 && (JUMP_LABEL (place2) == NULL
12902 || JUMP_LABEL (place2) == XEXP (note, 0)))
12904 rtx label = JUMP_LABEL (place2);
12907 JUMP_LABEL (place2) = XEXP (note, 0);
12908 else if (LABEL_P (label))
12909 LABEL_NUSES (label)--;
12915 /* This note says something about the value of a register prior
12916 to the execution of an insn. It is too much trouble to see
12917 if the note is still correct in all situations. It is better
12918 to simply delete it. */
12922 /* If we replaced the right hand side of FROM_INSN with a
12923 REG_EQUAL note, the original use of the dying register
12924 will not have been combined into I3 and I2. In such cases,
12925 FROM_INSN is guaranteed to be the first of the combined
12926 instructions, so we simply need to search back before
12927 FROM_INSN for the previous use or set of this register,
12928 then alter the notes there appropriately.
12930 If the register is used as an input in I3, it dies there.
12931 Similarly for I2, if it is nonzero and adjacent to I3.
12933 If the register is not used as an input in either I3 or I2
12934 and it is not one of the registers we were supposed to eliminate,
12935 there are two possibilities. We might have a non-adjacent I2
12936 or we might have somehow eliminated an additional register
12937 from a computation. For example, we might have had A & B where
12938 we discover that B will always be zero. In this case we will
12939 eliminate the reference to A.
12941 In both cases, we must search to see if we can find a previous
12942 use of A and put the death note there. */
12945 && from_insn == i2mod
12946 && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
12951 && CALL_P (from_insn)
12952 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12954 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12956 else if (i2 != 0 && next_nonnote_nondebug_insn (i2) == i3
12957 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12959 else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
12961 && reg_overlap_mentioned_p (XEXP (note, 0),
12963 || rtx_equal_p (XEXP (note, 0), elim_i1))
12970 basic_block bb = this_basic_block;
12972 for (tem = PREV_INSN (tem); place == 0; tem = PREV_INSN (tem))
12974 if (!NONDEBUG_INSN_P (tem))
12976 if (tem == BB_HEAD (bb))
12981 /* If the register is being set at TEM, see if that is all
12982 TEM is doing. If so, delete TEM. Otherwise, make this
12983 into a REG_UNUSED note instead. Don't delete sets to
12984 global register vars. */
12985 if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
12986 || !global_regs[REGNO (XEXP (note, 0))])
12987 && reg_set_p (XEXP (note, 0), PATTERN (tem)))
12989 rtx set = single_set (tem);
12990 rtx inner_dest = 0;
12992 rtx cc0_setter = NULL_RTX;
12996 for (inner_dest = SET_DEST (set);
12997 (GET_CODE (inner_dest) == STRICT_LOW_PART
12998 || GET_CODE (inner_dest) == SUBREG
12999 || GET_CODE (inner_dest) == ZERO_EXTRACT);
13000 inner_dest = XEXP (inner_dest, 0))
13003 /* Verify that it was the set, and not a clobber that
13004 modified the register.
13006 CC0 targets must be careful to maintain setter/user
13007 pairs. If we cannot delete the setter due to side
13008 effects, mark the user with an UNUSED note instead
13011 if (set != 0 && ! side_effects_p (SET_SRC (set))
13012 && rtx_equal_p (XEXP (note, 0), inner_dest)
13014 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
13015 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
13016 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
13020 /* Move the notes and links of TEM elsewhere.
13021 This might delete other dead insns recursively.
13022 First set the pattern to something that won't use
13024 rtx old_notes = REG_NOTES (tem);
13026 PATTERN (tem) = pc_rtx;
13027 REG_NOTES (tem) = NULL;
13029 distribute_notes (old_notes, tem, tem, NULL_RTX,
13030 NULL_RTX, NULL_RTX);
13031 distribute_links (LOG_LINKS (tem));
13033 SET_INSN_DELETED (tem);
13038 /* Delete the setter too. */
13041 PATTERN (cc0_setter) = pc_rtx;
13042 old_notes = REG_NOTES (cc0_setter);
13043 REG_NOTES (cc0_setter) = NULL;
13045 distribute_notes (old_notes, cc0_setter,
13046 cc0_setter, NULL_RTX,
13047 NULL_RTX, NULL_RTX);
13048 distribute_links (LOG_LINKS (cc0_setter));
13050 SET_INSN_DELETED (cc0_setter);
13051 if (cc0_setter == i2)
13058 PUT_REG_NOTE_KIND (note, REG_UNUSED);
13060 /* If there isn't already a REG_UNUSED note, put one
13061 here. Do not place a REG_DEAD note, even if
13062 the register is also used here; that would not
13063 match the algorithm used in lifetime analysis
13064 and can cause the consistency check in the
13065 scheduler to fail. */
13066 if (! find_regno_note (tem, REG_UNUSED,
13067 REGNO (XEXP (note, 0))))
13072 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
13074 && find_reg_fusage (tem, USE, XEXP (note, 0))))
13078 /* If we are doing a 3->2 combination, and we have a
13079 register which formerly died in i3 and was not used
13080 by i2, which now no longer dies in i3 and is used in
13081 i2 but does not die in i2, and place is between i2
13082 and i3, then we may need to move a link from place to
13084 if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2)
13086 && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2)
13087 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13089 rtx links = LOG_LINKS (place);
13090 LOG_LINKS (place) = 0;
13091 distribute_links (links);
13096 if (tem == BB_HEAD (bb))
13102 /* If the register is set or already dead at PLACE, we needn't do
13103 anything with this note if it is still a REG_DEAD note.
13104 We check here if it is set at all, not if is it totally replaced,
13105 which is what `dead_or_set_p' checks, so also check for it being
13108 if (place && REG_NOTE_KIND (note) == REG_DEAD)
13110 unsigned int regno = REGNO (XEXP (note, 0));
13111 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
13113 if (dead_or_set_p (place, XEXP (note, 0))
13114 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
13116 /* Unless the register previously died in PLACE, clear
13117 last_death. [I no longer understand why this is
13119 if (rsp->last_death != place)
13120 rsp->last_death = 0;
13124 rsp->last_death = place;
13126 /* If this is a death note for a hard reg that is occupying
13127 multiple registers, ensure that we are still using all
13128 parts of the object. If we find a piece of the object
13129 that is unused, we must arrange for an appropriate REG_DEAD
13130 note to be added for it. However, we can't just emit a USE
13131 and tag the note to it, since the register might actually
13132 be dead; so we recourse, and the recursive call then finds
13133 the previous insn that used this register. */
13135 if (place && regno < FIRST_PSEUDO_REGISTER
13136 && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
13138 unsigned int endregno = END_HARD_REGNO (XEXP (note, 0));
13142 for (i = regno; i < endregno; i++)
13143 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
13144 && ! find_regno_fusage (place, USE, i))
13145 || dead_or_set_regno_p (place, i))
13150 /* Put only REG_DEAD notes for pieces that are
13151 not already dead or set. */
13153 for (i = regno; i < endregno;
13154 i += hard_regno_nregs[i][reg_raw_mode[i]])
13156 rtx piece = regno_reg_rtx[i];
13157 basic_block bb = this_basic_block;
13159 if (! dead_or_set_p (place, piece)
13160 && ! reg_bitfield_target_p (piece,
13163 rtx new_note = alloc_reg_note (REG_DEAD, piece,
13166 distribute_notes (new_note, place, place,
13167 NULL_RTX, NULL_RTX, NULL_RTX);
13169 else if (! refers_to_regno_p (i, i + 1,
13170 PATTERN (place), 0)
13171 && ! find_regno_fusage (place, USE, i))
13172 for (tem = PREV_INSN (place); ;
13173 tem = PREV_INSN (tem))
13175 if (!NONDEBUG_INSN_P (tem))
13177 if (tem == BB_HEAD (bb))
13181 if (dead_or_set_p (tem, piece)
13182 || reg_bitfield_target_p (piece,
13185 add_reg_note (tem, REG_UNUSED, piece);
13199 /* Any other notes should not be present at this point in the
13201 gcc_unreachable ();
13206 XEXP (note, 1) = REG_NOTES (place);
13207 REG_NOTES (place) = note;
13211 add_reg_note (place2, REG_NOTE_KIND (note), XEXP (note, 0));
13215 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13216 I3, I2, and I1 to new locations. This is also called to add a link
13217 pointing at I3 when I3's destination is changed. */
13220 distribute_links (rtx links)
13222 rtx link, next_link;
13224 for (link = links; link; link = next_link)
13230 next_link = XEXP (link, 1);
13232 /* If the insn that this link points to is a NOTE or isn't a single
13233 set, ignore it. In the latter case, it isn't clear what we
13234 can do other than ignore the link, since we can't tell which
13235 register it was for. Such links wouldn't be used by combine
13238 It is not possible for the destination of the target of the link to
13239 have been changed by combine. The only potential of this is if we
13240 replace I3, I2, and I1 by I3 and I2. But in that case the
13241 destination of I2 also remains unchanged. */
13243 if (NOTE_P (XEXP (link, 0))
13244 || (set = single_set (XEXP (link, 0))) == 0)
13247 reg = SET_DEST (set);
13248 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
13249 || GET_CODE (reg) == STRICT_LOW_PART)
13250 reg = XEXP (reg, 0);
13252 /* A LOG_LINK is defined as being placed on the first insn that uses
13253 a register and points to the insn that sets the register. Start
13254 searching at the next insn after the target of the link and stop
13255 when we reach a set of the register or the end of the basic block.
13257 Note that this correctly handles the link that used to point from
13258 I3 to I2. Also note that not much searching is typically done here
13259 since most links don't point very far away. */
13261 for (insn = NEXT_INSN (XEXP (link, 0));
13262 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
13263 || BB_HEAD (this_basic_block->next_bb) != insn));
13264 insn = NEXT_INSN (insn))
13265 if (DEBUG_INSN_P (insn))
13267 else if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
13269 if (reg_referenced_p (reg, PATTERN (insn)))
13273 else if (CALL_P (insn)
13274 && find_reg_fusage (insn, USE, reg))
13279 else if (INSN_P (insn) && reg_set_p (reg, insn))
13282 /* If we found a place to put the link, place it there unless there
13283 is already a link to the same insn as LINK at that point. */
13289 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
13290 if (XEXP (link2, 0) == XEXP (link, 0))
13295 XEXP (link, 1) = LOG_LINKS (place);
13296 LOG_LINKS (place) = link;
13298 /* Set added_links_insn to the earliest insn we added a
13300 if (added_links_insn == 0
13301 || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place))
13302 added_links_insn = place;
13308 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
13309 Check whether the expression pointer to by LOC is a register or
13310 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
13311 Otherwise return zero. */
13314 unmentioned_reg_p_1 (rtx *loc, void *expr)
13319 && (REG_P (x) || MEM_P (x))
13320 && ! reg_mentioned_p (x, (rtx) expr))
13325 /* Check for any register or memory mentioned in EQUIV that is not
13326 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
13327 of EXPR where some registers may have been replaced by constants. */
13330 unmentioned_reg_p (rtx equiv, rtx expr)
13332 return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
13336 dump_combine_stats (FILE *file)
13340 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13341 combine_attempts, combine_merges, combine_extras, combine_successes);
13345 dump_combine_total_stats (FILE *file)
13349 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13350 total_attempts, total_merges, total_extras, total_successes);
13354 gate_handle_combine (void)
13356 return (optimize > 0);
13359 /* Try combining insns through substitution. */
13360 static unsigned int
13361 rest_of_handle_combine (void)
13363 int rebuild_jump_labels_after_combine;
13365 df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN);
13366 df_note_add_problem ();
13369 regstat_init_n_sets_and_refs ();
13371 rebuild_jump_labels_after_combine
13372 = combine_instructions (get_insns (), max_reg_num ());
13374 /* Combining insns may have turned an indirect jump into a
13375 direct jump. Rebuild the JUMP_LABEL fields of jumping
13377 if (rebuild_jump_labels_after_combine)
13379 timevar_push (TV_JUMP);
13380 rebuild_jump_labels (get_insns ());
13382 timevar_pop (TV_JUMP);
13385 regstat_free_n_sets_and_refs ();
13389 struct rtl_opt_pass pass_combine =
13393 "combine", /* name */
13394 gate_handle_combine, /* gate */
13395 rest_of_handle_combine, /* execute */
13398 0, /* static_pass_number */
13399 TV_COMBINE, /* tv_id */
13400 PROP_cfglayout, /* properties_required */
13401 0, /* properties_provided */
13402 0, /* properties_destroyed */
13403 0, /* todo_flags_start */
13405 TODO_df_finish | TODO_verify_rtl_sharing |
13406 TODO_ggc_collect, /* todo_flags_finish */