1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 88, 92, 93, 94, 95, 1996 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_regnotes) when a
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
84 /* Must precede rtl.h for FFS. */
90 #include "hard-reg-set.h"
92 #include "basic-block.h"
93 #include "insn-config.h"
94 #include "insn-flags.h"
95 #include "insn-codes.h"
96 #include "insn-attr.h"
100 /* It is not safe to use ordinary gen_lowpart in combine.
101 Use gen_lowpart_for_combine instead. See comments there. */
102 #define gen_lowpart dont_use_gen_lowpart_you_dummy
104 /* Number of attempts to combine instructions in this function. */
106 static int combine_attempts;
108 /* Number of attempts that got as far as substitution in this function. */
110 static int combine_merges;
112 /* Number of instructions combined with added SETs in this function. */
114 static int combine_extras;
116 /* Number of instructions combined in this function. */
118 static int combine_successes;
120 /* Totals over entire compilation. */
122 static int total_attempts, total_merges, total_extras, total_successes;
124 /* Define a default value for REVERSIBLE_CC_MODE.
125 We can never assume that a condition code mode is safe to reverse unless
126 the md tells us so. */
127 #ifndef REVERSIBLE_CC_MODE
128 #define REVERSIBLE_CC_MODE(MODE) 0
131 /* Vector mapping INSN_UIDs to cuids.
132 The cuids are like uids but increase monotonically always.
133 Combine always uses cuids so that it can compare them.
134 But actually renumbering the uids, which we used to do,
135 proves to be a bad idea because it makes it hard to compare
136 the dumps produced by earlier passes with those from later passes. */
138 static int *uid_cuid;
139 static int max_uid_cuid;
141 /* Get the cuid of an insn. */
143 #define INSN_CUID(INSN) \
144 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
146 /* Maximum register number, which is the size of the tables below. */
148 static int combine_max_regno;
150 /* Record last point of death of (hard or pseudo) register n. */
152 static rtx *reg_last_death;
154 /* Record last point of modification of (hard or pseudo) register n. */
156 static rtx *reg_last_set;
158 /* Record the cuid of the last insn that invalidated memory
159 (anything that writes memory, and subroutine calls, but not pushes). */
161 static int mem_last_set;
163 /* Record the cuid of the last CALL_INSN
164 so we can tell whether a potential combination crosses any calls. */
166 static int last_call_cuid;
168 /* When `subst' is called, this is the insn that is being modified
169 (by combining in a previous insn). The PATTERN of this insn
170 is still the old pattern partially modified and it should not be
171 looked at, but this may be used to examine the successors of the insn
172 to judge whether a simplification is valid. */
174 static rtx subst_insn;
176 /* This is an insn that belongs before subst_insn, but is not currently
177 on the insn chain. */
179 static rtx subst_prev_insn;
181 /* This is the lowest CUID that `subst' is currently dealing with.
182 get_last_value will not return a value if the register was set at or
183 after this CUID. If not for this mechanism, we could get confused if
184 I2 or I1 in try_combine were an insn that used the old value of a register
185 to obtain a new value. In that case, we might erroneously get the
186 new value of the register when we wanted the old one. */
188 static int subst_low_cuid;
190 /* This contains any hard registers that are used in newpat; reg_dead_at_p
191 must consider all these registers to be always live. */
193 static HARD_REG_SET newpat_used_regs;
195 /* This is an insn to which a LOG_LINKS entry has been added. If this
196 insn is the earlier than I2 or I3, combine should rescan starting at
199 static rtx added_links_insn;
201 /* Basic block number of the block in which we are performing combines. */
202 static int this_basic_block;
204 /* The next group of arrays allows the recording of the last value assigned
205 to (hard or pseudo) register n. We use this information to see if a
206 operation being processed is redundant given a prior operation performed
207 on the register. For example, an `and' with a constant is redundant if
208 all the zero bits are already known to be turned off.
210 We use an approach similar to that used by cse, but change it in the
213 (1) We do not want to reinitialize at each label.
214 (2) It is useful, but not critical, to know the actual value assigned
215 to a register. Often just its form is helpful.
217 Therefore, we maintain the following arrays:
219 reg_last_set_value the last value assigned
220 reg_last_set_label records the value of label_tick when the
221 register was assigned
222 reg_last_set_table_tick records the value of label_tick when a
223 value using the register is assigned
224 reg_last_set_invalid set to non-zero when it is not valid
225 to use the value of this register in some
228 To understand the usage of these tables, it is important to understand
229 the distinction between the value in reg_last_set_value being valid
230 and the register being validly contained in some other expression in the
233 Entry I in reg_last_set_value is valid if it is non-zero, and either
234 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
236 Register I may validly appear in any expression returned for the value
237 of another register if reg_n_sets[i] is 1. It may also appear in the
238 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
239 reg_last_set_invalid[j] is zero.
241 If an expression is found in the table containing a register which may
242 not validly appear in an expression, the register is replaced by
243 something that won't match, (clobber (const_int 0)).
245 reg_last_set_invalid[i] is set non-zero when register I is being assigned
246 to and reg_last_set_table_tick[i] == label_tick. */
248 /* Record last value assigned to (hard or pseudo) register n. */
250 static rtx *reg_last_set_value;
252 /* Record the value of label_tick when the value for register n is placed in
253 reg_last_set_value[n]. */
255 static int *reg_last_set_label;
257 /* Record the value of label_tick when an expression involving register n
258 is placed in reg_last_set_value. */
260 static int *reg_last_set_table_tick;
262 /* Set non-zero if references to register n in expressions should not be
265 static char *reg_last_set_invalid;
267 /* Incremented for each label. */
269 static int label_tick;
271 /* Some registers that are set more than once and used in more than one
272 basic block are nevertheless always set in similar ways. For example,
273 a QImode register may be loaded from memory in two places on a machine
274 where byte loads zero extend.
276 We record in the following array what we know about the nonzero
277 bits of a register, specifically which bits are known to be zero.
279 If an entry is zero, it means that we don't know anything special. */
281 static unsigned HOST_WIDE_INT *reg_nonzero_bits;
283 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
284 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
286 static enum machine_mode nonzero_bits_mode;
288 /* Nonzero if we know that a register has some leading bits that are always
289 equal to the sign bit. */
291 static char *reg_sign_bit_copies;
293 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
294 It is zero while computing them and after combine has completed. This
295 former test prevents propagating values based on previously set values,
296 which can be incorrect if a variable is modified in a loop. */
298 static int nonzero_sign_valid;
300 /* These arrays are maintained in parallel with reg_last_set_value
301 and are used to store the mode in which the register was last set,
302 the bits that were known to be zero when it was last set, and the
303 number of sign bits copies it was known to have when it was last set. */
305 static enum machine_mode *reg_last_set_mode;
306 static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
307 static char *reg_last_set_sign_bit_copies;
309 /* Record one modification to rtl structure
310 to be undone by storing old_contents into *where.
311 is_int is 1 if the contents are an int. */
317 union {rtx r; int i;} old_contents;
318 union {rtx *r; int *i;} where;
321 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
322 num_undo says how many are currently recorded.
324 storage is nonzero if we must undo the allocation of new storage.
325 The value of storage is what to pass to obfree.
327 other_insn is nonzero if we have modified some other insn in the process
328 of working on subst_insn. It must be verified too.
330 previous_undos is the value of undobuf.undos when we started processing
331 this substitution. This will prevent gen_rtx_combine from re-used a piece
332 from the previous expression. Doing so can produce circular rtl
340 struct undo *previous_undos;
344 static struct undobuf undobuf;
346 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
347 insn. The substitution can be undone by undo_all. If INTO is already
348 set to NEWVAL, do not record this change. Because computing NEWVAL might
349 also call SUBST, we have to compute it before we put anything into
352 #define SUBST(INTO, NEWVAL) \
353 do { rtx _new = (NEWVAL); \
357 _buf = undobuf.frees, undobuf.frees = _buf->next; \
359 _buf = (struct undo *) xmalloc (sizeof (struct undo)); \
362 _buf->where.r = &INTO; \
363 _buf->old_contents.r = INTO; \
365 if (_buf->old_contents.r == INTO) \
366 _buf->next = undobuf.frees, undobuf.frees = _buf; \
368 _buf->next = undobuf.undos, undobuf.undos = _buf; \
371 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
372 for the value of a HOST_WIDE_INT value (including CONST_INT) is
375 #define SUBST_INT(INTO, NEWVAL) \
376 do { struct undo *_buf; \
379 _buf = undobuf.frees, undobuf.frees = _buf->next; \
381 _buf = (struct undo *) xmalloc (sizeof (struct undo)); \
384 _buf->where.i = (int *) &INTO; \
385 _buf->old_contents.i = INTO; \
387 if (_buf->old_contents.i == INTO) \
388 _buf->next = undobuf.frees, undobuf.frees = _buf; \
390 _buf->next = undobuf.undos, undobuf.undos = _buf; \
393 /* Number of times the pseudo being substituted for
394 was found and replaced. */
396 static int n_occurrences;
398 static void init_reg_last_arrays PROTO((void));
399 static void setup_incoming_promotions PROTO((void));
400 static void set_nonzero_bits_and_sign_copies PROTO((rtx, rtx));
401 static int can_combine_p PROTO((rtx, rtx, rtx, rtx, rtx *, rtx *));
402 static int combinable_i3pat PROTO((rtx, rtx *, rtx, rtx, int, rtx *));
403 static rtx try_combine PROTO((rtx, rtx, rtx));
404 static void undo_all PROTO((void));
405 static rtx *find_split_point PROTO((rtx *, rtx));
406 static rtx subst PROTO((rtx, rtx, rtx, int, int));
407 static rtx simplify_rtx PROTO((rtx, enum machine_mode, int, int));
408 static rtx simplify_if_then_else PROTO((rtx));
409 static rtx simplify_set PROTO((rtx));
410 static rtx simplify_logical PROTO((rtx, int));
411 static rtx expand_compound_operation PROTO((rtx));
412 static rtx expand_field_assignment PROTO((rtx));
413 static rtx make_extraction PROTO((enum machine_mode, rtx, int, rtx, int,
415 static rtx extract_left_shift PROTO((rtx, int));
416 static rtx make_compound_operation PROTO((rtx, enum rtx_code));
417 static int get_pos_from_mask PROTO((unsigned HOST_WIDE_INT, int *));
418 static rtx force_to_mode PROTO((rtx, enum machine_mode,
419 unsigned HOST_WIDE_INT, rtx, int));
420 static rtx if_then_else_cond PROTO((rtx, rtx *, rtx *));
421 static rtx known_cond PROTO((rtx, enum rtx_code, rtx, rtx));
422 static int rtx_equal_for_field_assignment_p PROTO((rtx, rtx));
423 static rtx make_field_assignment PROTO((rtx));
424 static rtx apply_distributive_law PROTO((rtx));
425 static rtx simplify_and_const_int PROTO((rtx, enum machine_mode, rtx,
426 unsigned HOST_WIDE_INT));
427 static unsigned HOST_WIDE_INT nonzero_bits PROTO((rtx, enum machine_mode));
428 static int num_sign_bit_copies PROTO((rtx, enum machine_mode));
429 static int merge_outer_ops PROTO((enum rtx_code *, HOST_WIDE_INT *,
430 enum rtx_code, HOST_WIDE_INT,
431 enum machine_mode, int *));
432 static rtx simplify_shift_const PROTO((rtx, enum rtx_code, enum machine_mode,
434 static int recog_for_combine PROTO((rtx *, rtx, rtx *, int *));
435 static rtx gen_lowpart_for_combine PROTO((enum machine_mode, rtx));
436 static rtx gen_rtx_combine PVPROTO((enum rtx_code code, enum machine_mode mode,
438 static rtx gen_binary PROTO((enum rtx_code, enum machine_mode,
440 static rtx gen_unary PROTO((enum rtx_code, enum machine_mode,
441 enum machine_mode, rtx));
442 static enum rtx_code simplify_comparison PROTO((enum rtx_code, rtx *, rtx *));
443 static int reversible_comparison_p PROTO((rtx));
444 static void update_table_tick PROTO((rtx));
445 static void record_value_for_reg PROTO((rtx, rtx, rtx));
446 static void record_dead_and_set_regs_1 PROTO((rtx, rtx));
447 static void record_dead_and_set_regs PROTO((rtx));
448 static int get_last_value_validate PROTO((rtx *, int, int));
449 static rtx get_last_value PROTO((rtx));
450 static int use_crosses_set_p PROTO((rtx, int));
451 static void reg_dead_at_p_1 PROTO((rtx, rtx));
452 static int reg_dead_at_p PROTO((rtx, rtx));
453 static void move_deaths PROTO((rtx, rtx, int, rtx, rtx *));
454 static int reg_bitfield_target_p PROTO((rtx, rtx));
455 static void distribute_notes PROTO((rtx, rtx, rtx, rtx, rtx, rtx));
456 static void distribute_links PROTO((rtx));
457 static void mark_used_regs_combine PROTO((rtx));
458 static int insn_cuid PROTO((rtx));
460 /* Main entry point for combiner. F is the first insn of the function.
461 NREGS is the first unused pseudo-reg number. */
464 combine_instructions (f, nregs)
468 register rtx insn, next, prev;
470 register rtx links, nextlinks;
472 combine_attempts = 0;
475 combine_successes = 0;
476 undobuf.undos = undobuf.previous_undos = 0;
478 combine_max_regno = nregs;
481 = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT));
482 reg_sign_bit_copies = (char *) alloca (nregs * sizeof (char));
484 bzero ((char *) reg_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
485 bzero (reg_sign_bit_copies, nregs * sizeof (char));
487 reg_last_death = (rtx *) alloca (nregs * sizeof (rtx));
488 reg_last_set = (rtx *) alloca (nregs * sizeof (rtx));
489 reg_last_set_value = (rtx *) alloca (nregs * sizeof (rtx));
490 reg_last_set_table_tick = (int *) alloca (nregs * sizeof (int));
491 reg_last_set_label = (int *) alloca (nregs * sizeof (int));
492 reg_last_set_invalid = (char *) alloca (nregs * sizeof (char));
494 = (enum machine_mode *) alloca (nregs * sizeof (enum machine_mode));
495 reg_last_set_nonzero_bits
496 = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT));
497 reg_last_set_sign_bit_copies
498 = (char *) alloca (nregs * sizeof (char));
500 init_reg_last_arrays ();
502 init_recog_no_volatile ();
504 /* Compute maximum uid value so uid_cuid can be allocated. */
506 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
507 if (INSN_UID (insn) > i)
510 uid_cuid = (int *) alloca ((i + 1) * sizeof (int));
513 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
515 /* Don't use reg_nonzero_bits when computing it. This can cause problems
516 when, for example, we have j <<= 1 in a loop. */
518 nonzero_sign_valid = 0;
520 /* Compute the mapping from uids to cuids.
521 Cuids are numbers assigned to insns, like uids,
522 except that cuids increase monotonically through the code.
524 Scan all SETs and see if we can deduce anything about what
525 bits are known to be zero for some registers and how many copies
526 of the sign bit are known to exist for those registers.
528 Also set any known values so that we can use it while searching
529 for what bits are known to be set. */
533 /* We need to initialize it here, because record_dead_and_set_regs may call
535 subst_prev_insn = NULL_RTX;
537 setup_incoming_promotions ();
539 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
541 uid_cuid[INSN_UID (insn)] = ++i;
545 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
547 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies);
548 record_dead_and_set_regs (insn);
551 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
552 if (REG_NOTE_KIND (links) == REG_INC)
553 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX);
557 if (GET_CODE (insn) == CODE_LABEL)
561 nonzero_sign_valid = 1;
563 /* Now scan all the insns in forward order. */
565 this_basic_block = -1;
569 init_reg_last_arrays ();
570 setup_incoming_promotions ();
572 for (insn = f; insn; insn = next ? next : NEXT_INSN (insn))
576 /* If INSN starts a new basic block, update our basic block number. */
577 if (this_basic_block + 1 < n_basic_blocks
578 && basic_block_head[this_basic_block + 1] == insn)
581 if (GET_CODE (insn) == CODE_LABEL)
584 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
586 /* Try this insn with each insn it links back to. */
588 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
589 if ((next = try_combine (insn, XEXP (links, 0), NULL_RTX)) != 0)
592 /* Try each sequence of three linked insns ending with this one. */
594 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
595 for (nextlinks = LOG_LINKS (XEXP (links, 0)); nextlinks;
596 nextlinks = XEXP (nextlinks, 1))
597 if ((next = try_combine (insn, XEXP (links, 0),
598 XEXP (nextlinks, 0))) != 0)
602 /* Try to combine a jump insn that uses CC0
603 with a preceding insn that sets CC0, and maybe with its
604 logical predecessor as well.
605 This is how we make decrement-and-branch insns.
606 We need this special code because data flow connections
607 via CC0 do not get entered in LOG_LINKS. */
609 if (GET_CODE (insn) == JUMP_INSN
610 && (prev = prev_nonnote_insn (insn)) != 0
611 && GET_CODE (prev) == INSN
612 && sets_cc0_p (PATTERN (prev)))
614 if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
617 for (nextlinks = LOG_LINKS (prev); nextlinks;
618 nextlinks = XEXP (nextlinks, 1))
619 if ((next = try_combine (insn, prev,
620 XEXP (nextlinks, 0))) != 0)
624 /* Do the same for an insn that explicitly references CC0. */
625 if (GET_CODE (insn) == INSN
626 && (prev = prev_nonnote_insn (insn)) != 0
627 && GET_CODE (prev) == INSN
628 && sets_cc0_p (PATTERN (prev))
629 && GET_CODE (PATTERN (insn)) == SET
630 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
632 if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
635 for (nextlinks = LOG_LINKS (prev); nextlinks;
636 nextlinks = XEXP (nextlinks, 1))
637 if ((next = try_combine (insn, prev,
638 XEXP (nextlinks, 0))) != 0)
642 /* Finally, see if any of the insns that this insn links to
643 explicitly references CC0. If so, try this insn, that insn,
644 and its predecessor if it sets CC0. */
645 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
646 if (GET_CODE (XEXP (links, 0)) == INSN
647 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
648 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
649 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
650 && GET_CODE (prev) == INSN
651 && sets_cc0_p (PATTERN (prev))
652 && (next = try_combine (insn, XEXP (links, 0), prev)) != 0)
656 /* Try combining an insn with two different insns whose results it
658 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
659 for (nextlinks = XEXP (links, 1); nextlinks;
660 nextlinks = XEXP (nextlinks, 1))
661 if ((next = try_combine (insn, XEXP (links, 0),
662 XEXP (nextlinks, 0))) != 0)
665 if (GET_CODE (insn) != NOTE)
666 record_dead_and_set_regs (insn);
673 total_attempts += combine_attempts;
674 total_merges += combine_merges;
675 total_extras += combine_extras;
676 total_successes += combine_successes;
678 nonzero_sign_valid = 0;
681 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
684 init_reg_last_arrays ()
686 int nregs = combine_max_regno;
688 bzero ((char *) reg_last_death, nregs * sizeof (rtx));
689 bzero ((char *) reg_last_set, nregs * sizeof (rtx));
690 bzero ((char *) reg_last_set_value, nregs * sizeof (rtx));
691 bzero ((char *) reg_last_set_table_tick, nregs * sizeof (int));
692 bzero ((char *) reg_last_set_label, nregs * sizeof (int));
693 bzero (reg_last_set_invalid, nregs * sizeof (char));
694 bzero ((char *) reg_last_set_mode, nregs * sizeof (enum machine_mode));
695 bzero ((char *) reg_last_set_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
696 bzero (reg_last_set_sign_bit_copies, nregs * sizeof (char));
699 /* Set up any promoted values for incoming argument registers. */
702 setup_incoming_promotions ()
704 #ifdef PROMOTE_FUNCTION_ARGS
707 enum machine_mode mode;
709 rtx first = get_insns ();
711 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
712 if (FUNCTION_ARG_REGNO_P (regno)
713 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
714 record_value_for_reg (reg, first,
715 gen_rtx (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
717 gen_rtx (CLOBBER, mode, const0_rtx)));
721 /* Called via note_stores. If X is a pseudo that is narrower than
722 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
724 If we are setting only a portion of X and we can't figure out what
725 portion, assume all bits will be used since we don't know what will
728 Similarly, set how many bits of X are known to be copies of the sign bit
729 at all locations in the function. This is the smallest number implied
733 set_nonzero_bits_and_sign_copies (x, set)
739 if (GET_CODE (x) == REG
740 && REGNO (x) >= FIRST_PSEUDO_REGISTER
741 /* If this register is undefined at the start of the file, we can't
742 say what its contents were. */
743 && ! (basic_block_live_at_start[0][REGNO (x) / REGSET_ELT_BITS]
744 & ((REGSET_ELT_TYPE) 1 << (REGNO (x) % REGSET_ELT_BITS)))
745 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
747 if (set == 0 || GET_CODE (set) == CLOBBER)
749 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
750 reg_sign_bit_copies[REGNO (x)] = 1;
754 /* If this is a complex assignment, see if we can convert it into a
755 simple assignment. */
756 set = expand_field_assignment (set);
758 /* If this is a simple assignment, or we have a paradoxical SUBREG,
759 set what we know about X. */
761 if (SET_DEST (set) == x
762 || (GET_CODE (SET_DEST (set)) == SUBREG
763 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
764 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
765 && SUBREG_REG (SET_DEST (set)) == x))
767 rtx src = SET_SRC (set);
769 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
770 /* If X is narrower than a word and SRC is a non-negative
771 constant that would appear negative in the mode of X,
772 sign-extend it for use in reg_nonzero_bits because some
773 machines (maybe most) will actually do the sign-extension
774 and this is the conservative approach.
776 ??? For 2.5, try to tighten up the MD files in this regard
777 instead of this kludge. */
779 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
780 && GET_CODE (src) == CONST_INT
782 && 0 != (INTVAL (src)
784 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
785 src = GEN_INT (INTVAL (src)
786 | ((HOST_WIDE_INT) (-1)
787 << GET_MODE_BITSIZE (GET_MODE (x))));
790 reg_nonzero_bits[REGNO (x)]
791 |= nonzero_bits (src, nonzero_bits_mode);
792 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
793 if (reg_sign_bit_copies[REGNO (x)] == 0
794 || reg_sign_bit_copies[REGNO (x)] > num)
795 reg_sign_bit_copies[REGNO (x)] = num;
799 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
800 reg_sign_bit_copies[REGNO (x)] = 1;
805 /* See if INSN can be combined into I3. PRED and SUCC are optionally
806 insns that were previously combined into I3 or that will be combined
807 into the merger of INSN and I3.
809 Return 0 if the combination is not allowed for any reason.
811 If the combination is allowed, *PDEST will be set to the single
812 destination of INSN and *PSRC to the single source, and this function
816 can_combine_p (insn, i3, pred, succ, pdest, psrc)
823 rtx set = 0, src, dest;
825 int all_adjacent = (succ ? (next_active_insn (insn) == succ
826 && next_active_insn (succ) == i3)
827 : next_active_insn (insn) == i3);
829 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
830 or a PARALLEL consisting of such a SET and CLOBBERs.
832 If INSN has CLOBBER parallel parts, ignore them for our processing.
833 By definition, these happen during the execution of the insn. When it
834 is merged with another insn, all bets are off. If they are, in fact,
835 needed and aren't also supplied in I3, they may be added by
836 recog_for_combine. Otherwise, it won't match.
838 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
841 Get the source and destination of INSN. If more than one, can't
844 if (GET_CODE (PATTERN (insn)) == SET)
845 set = PATTERN (insn);
846 else if (GET_CODE (PATTERN (insn)) == PARALLEL
847 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
849 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
851 rtx elt = XVECEXP (PATTERN (insn), 0, i);
853 switch (GET_CODE (elt))
855 /* We can ignore CLOBBERs. */
860 /* Ignore SETs whose result isn't used but not those that
861 have side-effects. */
862 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
863 && ! side_effects_p (elt))
866 /* If we have already found a SET, this is a second one and
867 so we cannot combine with this insn. */
875 /* Anything else means we can't combine. */
881 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
882 so don't do anything with it. */
883 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
892 set = expand_field_assignment (set);
893 src = SET_SRC (set), dest = SET_DEST (set);
895 /* Don't eliminate a store in the stack pointer. */
896 if (dest == stack_pointer_rtx
897 /* If we couldn't eliminate a field assignment, we can't combine. */
898 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
899 /* Don't combine with an insn that sets a register to itself if it has
900 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
901 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
902 /* Can't merge a function call. */
903 || GET_CODE (src) == CALL
904 /* Don't eliminate a function call argument. */
905 || (GET_CODE (i3) == CALL_INSN
906 && (find_reg_fusage (i3, USE, dest)
907 || (GET_CODE (dest) == REG
908 && REGNO (dest) < FIRST_PSEUDO_REGISTER
909 && global_regs[REGNO (dest)])))
910 /* Don't substitute into an incremented register. */
911 || FIND_REG_INC_NOTE (i3, dest)
912 || (succ && FIND_REG_INC_NOTE (succ, dest))
913 /* Don't combine the end of a libcall into anything. */
914 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
915 /* Make sure that DEST is not used after SUCC but before I3. */
916 || (succ && ! all_adjacent
917 && reg_used_between_p (dest, succ, i3))
918 /* Make sure that the value that is to be substituted for the register
919 does not use any registers whose values alter in between. However,
920 If the insns are adjacent, a use can't cross a set even though we
921 think it might (this can happen for a sequence of insns each setting
922 the same destination; reg_last_set of that register might point to
923 a NOTE). If INSN has a REG_EQUIV note, the register is always
924 equivalent to the memory so the substitution is valid even if there
925 are intervening stores. Also, don't move a volatile asm or
926 UNSPEC_VOLATILE across any other insns. */
928 && (((GET_CODE (src) != MEM
929 || ! find_reg_note (insn, REG_EQUIV, src))
930 && use_crosses_set_p (src, INSN_CUID (insn)))
931 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
932 || GET_CODE (src) == UNSPEC_VOLATILE))
933 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
934 better register allocation by not doing the combine. */
935 || find_reg_note (i3, REG_NO_CONFLICT, dest)
936 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
937 /* Don't combine across a CALL_INSN, because that would possibly
938 change whether the life span of some REGs crosses calls or not,
939 and it is a pain to update that information.
940 Exception: if source is a constant, moving it later can't hurt.
941 Accept that special case, because it helps -fforce-addr a lot. */
942 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
945 /* DEST must either be a REG or CC0. */
946 if (GET_CODE (dest) == REG)
948 /* If register alignment is being enforced for multi-word items in all
949 cases except for parameters, it is possible to have a register copy
950 insn referencing a hard register that is not allowed to contain the
951 mode being copied and which would not be valid as an operand of most
952 insns. Eliminate this problem by not combining with such an insn.
954 Also, on some machines we don't want to extend the life of a hard
957 if (GET_CODE (src) == REG
958 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
959 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
960 /* Don't extend the life of a hard register unless it is
961 user variable (if we have few registers) or it can't
962 fit into the desired register (meaning something special
964 || (REGNO (src) < FIRST_PSEUDO_REGISTER
965 && (! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src))
966 #ifdef SMALL_REGISTER_CLASSES
967 || (! all_adjacent && ! REG_USERVAR_P (src))
972 else if (GET_CODE (dest) != CC0)
975 /* Don't substitute for a register intended as a clobberable operand.
976 Similarly, don't substitute an expression containing a register that
977 will be clobbered in I3. */
978 if (GET_CODE (PATTERN (i3)) == PARALLEL)
979 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
980 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
981 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
983 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
986 /* If INSN contains anything volatile, or is an `asm' (whether volatile
987 or not), reject, unless nothing volatile comes between it and I3,
988 with the exception of SUCC. */
990 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
991 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
992 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
993 && p != succ && volatile_refs_p (PATTERN (p)))
996 /* If there are any volatile insns between INSN and I3, reject, because
997 they might affect machine state. */
999 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1000 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
1001 && p != succ && volatile_insn_p (PATTERN (p)))
1004 /* If INSN or I2 contains an autoincrement or autodecrement,
1005 make sure that register is not used between there and I3,
1006 and not already used in I3 either.
1007 Also insist that I3 not be a jump; if it were one
1008 and the incremented register were spilled, we would lose. */
1011 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1012 if (REG_NOTE_KIND (link) == REG_INC
1013 && (GET_CODE (i3) == JUMP_INSN
1014 || reg_used_between_p (XEXP (link, 0), insn, i3)
1015 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1020 /* Don't combine an insn that follows a CC0-setting insn.
1021 An insn that uses CC0 must not be separated from the one that sets it.
1022 We do, however, allow I2 to follow a CC0-setting insn if that insn
1023 is passed as I1; in that case it will be deleted also.
1024 We also allow combining in this case if all the insns are adjacent
1025 because that would leave the two CC0 insns adjacent as well.
1026 It would be more logical to test whether CC0 occurs inside I1 or I2,
1027 but that would be much slower, and this ought to be equivalent. */
1029 p = prev_nonnote_insn (insn);
1030 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
1035 /* If we get here, we have passed all the tests and the combination is
1044 /* LOC is the location within I3 that contains its pattern or the component
1045 of a PARALLEL of the pattern. We validate that it is valid for combining.
1047 One problem is if I3 modifies its output, as opposed to replacing it
1048 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1049 so would produce an insn that is not equivalent to the original insns.
1053 (set (reg:DI 101) (reg:DI 100))
1054 (set (subreg:SI (reg:DI 101) 0) <foo>)
1056 This is NOT equivalent to:
1058 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1059 (set (reg:DI 101) (reg:DI 100))])
1061 Not only does this modify 100 (in which case it might still be valid
1062 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1064 We can also run into a problem if I2 sets a register that I1
1065 uses and I1 gets directly substituted into I3 (not via I2). In that
1066 case, we would be getting the wrong value of I2DEST into I3, so we
1067 must reject the combination. This case occurs when I2 and I1 both
1068 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1069 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1070 of a SET must prevent combination from occurring.
1072 On machines where SMALL_REGISTER_CLASSES is defined, we don't combine
1073 if the destination of a SET is a hard register that isn't a user
1076 Before doing the above check, we first try to expand a field assignment
1077 into a set of logical operations.
1079 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1080 we place a register that is both set and used within I3. If more than one
1081 such register is detected, we fail.
1083 Return 1 if the combination is valid, zero otherwise. */
1086 combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
1092 rtx *pi3dest_killed;
1096 if (GET_CODE (x) == SET)
1098 rtx set = expand_field_assignment (x);
1099 rtx dest = SET_DEST (set);
1100 rtx src = SET_SRC (set);
1101 rtx inner_dest = dest, inner_src = src;
1105 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1106 || GET_CODE (inner_dest) == SUBREG
1107 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1108 inner_dest = XEXP (inner_dest, 0);
1110 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1113 while (GET_CODE (inner_src) == STRICT_LOW_PART
1114 || GET_CODE (inner_src) == SUBREG
1115 || GET_CODE (inner_src) == ZERO_EXTRACT)
1116 inner_src = XEXP (inner_src, 0);
1118 /* If it is better that two different modes keep two different pseudos,
1119 avoid combining them. This avoids producing the following pattern
1121 (set (subreg:SI (reg/v:QI 21) 0)
1122 (lshiftrt:SI (reg/v:SI 20)
1124 If that were made, reload could not handle the pair of
1125 reg 20/21, since it would try to get any GENERAL_REGS
1126 but some of them don't handle QImode. */
1128 if (rtx_equal_p (inner_src, i2dest)
1129 && GET_CODE (inner_dest) == REG
1130 && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
1134 /* Check for the case where I3 modifies its output, as
1136 if ((inner_dest != dest
1137 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1138 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1139 /* This is the same test done in can_combine_p except that we
1140 allow a hard register with SMALL_REGISTER_CLASSES if SRC is a
1142 || (GET_CODE (inner_dest) == REG
1143 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1144 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1145 GET_MODE (inner_dest))
1146 #ifdef SMALL_REGISTER_CLASSES
1147 || (GET_CODE (src) != CALL && ! REG_USERVAR_P (inner_dest))
1150 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1153 /* If DEST is used in I3, it is being killed in this insn,
1154 so record that for later.
1155 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1156 STACK_POINTER_REGNUM, since these are always considered to be
1157 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1158 if (pi3dest_killed && GET_CODE (dest) == REG
1159 && reg_referenced_p (dest, PATTERN (i3))
1160 && REGNO (dest) != FRAME_POINTER_REGNUM
1161 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1162 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1164 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1165 && (REGNO (dest) != ARG_POINTER_REGNUM
1166 || ! fixed_regs [REGNO (dest)])
1168 && REGNO (dest) != STACK_POINTER_REGNUM)
1170 if (*pi3dest_killed)
1173 *pi3dest_killed = dest;
1177 else if (GET_CODE (x) == PARALLEL)
1181 for (i = 0; i < XVECLEN (x, 0); i++)
1182 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1183 i1_not_in_src, pi3dest_killed))
1190 /* Try to combine the insns I1 and I2 into I3.
1191 Here I1 and I2 appear earlier than I3.
1192 I1 can be zero; then we combine just I2 into I3.
1194 It we are combining three insns and the resulting insn is not recognized,
1195 try splitting it into two insns. If that happens, I2 and I3 are retained
1196 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1199 Return 0 if the combination does not work. Then nothing is changed.
1200 If we did the combination, return the insn at which combine should
1204 try_combine (i3, i2, i1)
1205 register rtx i3, i2, i1;
1207 /* New patterns for I3 and I3, respectively. */
1208 rtx newpat, newi2pat = 0;
1209 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1210 int added_sets_1, added_sets_2;
1211 /* Total number of SETs to put into I3. */
1213 /* Nonzero is I2's body now appears in I3. */
1215 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1216 int insn_code_number, i2_code_number, other_code_number;
1217 /* Contains I3 if the destination of I3 is used in its source, which means
1218 that the old life of I3 is being killed. If that usage is placed into
1219 I2 and not in I3, a REG_DEAD note must be made. */
1220 rtx i3dest_killed = 0;
1221 /* SET_DEST and SET_SRC of I2 and I1. */
1222 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1223 /* PATTERN (I2), or a copy of it in certain cases. */
1225 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1226 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1227 int i1_feeds_i3 = 0;
1228 /* Notes that must be added to REG_NOTES in I3 and I2. */
1229 rtx new_i3_notes, new_i2_notes;
1230 /* Notes that we substituted I3 into I2 instead of the normal case. */
1231 int i3_subst_into_i2 = 0;
1232 /* Notes that I1, I2 or I3 is a MULT operation. */
1234 /* Number of clobbers of SCRATCH we had to add. */
1235 int i3_scratches = 0, i2_scratches = 0, other_scratches = 0;
1242 /* If any of I1, I2, and I3 isn't really an insn, we can't do anything.
1243 This can occur when flow deletes an insn that it has merged into an
1244 auto-increment address. We also can't do anything if I3 has a
1245 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1248 if (GET_RTX_CLASS (GET_CODE (i3)) != 'i'
1249 || GET_RTX_CLASS (GET_CODE (i2)) != 'i'
1250 || (i1 && GET_RTX_CLASS (GET_CODE (i1)) != 'i')
1251 || find_reg_note (i3, REG_LIBCALL, NULL_RTX))
1256 undobuf.undos = undobuf.previous_undos = 0;
1257 undobuf.other_insn = 0;
1259 /* Save the current high-water-mark so we can free storage if we didn't
1260 accept this combination. */
1261 undobuf.storage = (char *) oballoc (0);
1263 /* Reset the hard register usage information. */
1264 CLEAR_HARD_REG_SET (newpat_used_regs);
1266 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1267 code below, set I1 to be the earlier of the two insns. */
1268 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1269 temp = i1, i1 = i2, i2 = temp;
1271 added_links_insn = 0;
1273 /* First check for one important special-case that the code below will
1274 not handle. Namely, the case where I1 is zero, I2 has multiple sets,
1275 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1276 we may be able to replace that destination with the destination of I3.
1277 This occurs in the common code where we compute both a quotient and
1278 remainder into a structure, in which case we want to do the computation
1279 directly into the structure to avoid register-register copies.
1281 We make very conservative checks below and only try to handle the
1282 most common cases of this. For example, we only handle the case
1283 where I2 and I3 are adjacent to avoid making difficult register
1286 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1287 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1288 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1289 #ifdef SMALL_REGISTER_CLASSES
1290 && (GET_CODE (SET_DEST (PATTERN (i3))) != REG
1291 || REGNO (SET_DEST (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1292 || REG_USERVAR_P (SET_DEST (PATTERN (i3))))
1294 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1295 && GET_CODE (PATTERN (i2)) == PARALLEL
1296 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1297 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1298 below would need to check what is inside (and reg_overlap_mentioned_p
1299 doesn't support those codes anyway). Don't allow those destinations;
1300 the resulting insn isn't likely to be recognized anyway. */
1301 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1302 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1303 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1304 SET_DEST (PATTERN (i3)))
1305 && next_real_insn (i2) == i3)
1307 rtx p2 = PATTERN (i2);
1309 /* Make sure that the destination of I3,
1310 which we are going to substitute into one output of I2,
1311 is not used within another output of I2. We must avoid making this:
1312 (parallel [(set (mem (reg 69)) ...)
1313 (set (reg 69) ...)])
1314 which is not well-defined as to order of actions.
1315 (Besides, reload can't handle output reloads for this.)
1317 The problem can also happen if the dest of I3 is a memory ref,
1318 if another dest in I2 is an indirect memory ref. */
1319 for (i = 0; i < XVECLEN (p2, 0); i++)
1320 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1321 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1322 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1323 SET_DEST (XVECEXP (p2, 0, i))))
1326 if (i == XVECLEN (p2, 0))
1327 for (i = 0; i < XVECLEN (p2, 0); i++)
1328 if (SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1333 subst_low_cuid = INSN_CUID (i2);
1335 added_sets_2 = added_sets_1 = 0;
1336 i2dest = SET_SRC (PATTERN (i3));
1338 /* Replace the dest in I2 with our dest and make the resulting
1339 insn the new pattern for I3. Then skip to where we
1340 validate the pattern. Everything was set up above. */
1341 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1342 SET_DEST (PATTERN (i3)));
1345 i3_subst_into_i2 = 1;
1346 goto validate_replacement;
1351 /* If we have no I1 and I2 looks like:
1352 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1354 make up a dummy I1 that is
1357 (set (reg:CC X) (compare:CC Y (const_int 0)))
1359 (We can ignore any trailing CLOBBERs.)
1361 This undoes a previous combination and allows us to match a branch-and-
1364 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1365 && XVECLEN (PATTERN (i2), 0) >= 2
1366 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1367 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1369 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1370 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1371 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1372 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1373 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1374 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1376 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1377 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1382 /* We make I1 with the same INSN_UID as I2. This gives it
1383 the same INSN_CUID for value tracking. Our fake I1 will
1384 never appear in the insn stream so giving it the same INSN_UID
1385 as I2 will not cause a problem. */
1387 subst_prev_insn = i1
1388 = gen_rtx (INSN, VOIDmode, INSN_UID (i2), 0, i2,
1389 XVECEXP (PATTERN (i2), 0, 1), -1, 0, 0);
1391 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1392 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1393 SET_DEST (PATTERN (i1)));
1398 /* Verify that I2 and I1 are valid for combining. */
1399 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1400 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1406 /* Record whether I2DEST is used in I2SRC and similarly for the other
1407 cases. Knowing this will help in register status updating below. */
1408 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1409 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1410 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1412 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1414 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1416 /* Ensure that I3's pattern can be the destination of combines. */
1417 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1418 i1 && i2dest_in_i1src && i1_feeds_i3,
1425 /* See if any of the insns is a MULT operation. Unless one is, we will
1426 reject a combination that is, since it must be slower. Be conservative
1428 if (GET_CODE (i2src) == MULT
1429 || (i1 != 0 && GET_CODE (i1src) == MULT)
1430 || (GET_CODE (PATTERN (i3)) == SET
1431 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1434 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1435 We used to do this EXCEPT in one case: I3 has a post-inc in an
1436 output operand. However, that exception can give rise to insns like
1438 which is a famous insn on the PDP-11 where the value of r3 used as the
1439 source was model-dependent. Avoid this sort of thing. */
1442 if (!(GET_CODE (PATTERN (i3)) == SET
1443 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1444 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1445 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1446 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1447 /* It's not the exception. */
1450 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1451 if (REG_NOTE_KIND (link) == REG_INC
1452 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1454 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1461 /* See if the SETs in I1 or I2 need to be kept around in the merged
1462 instruction: whenever the value set there is still needed past I3.
1463 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1465 For the SET in I1, we have two cases: If I1 and I2 independently
1466 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1467 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1468 in I1 needs to be kept around unless I1DEST dies or is set in either
1469 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1470 I1DEST. If so, we know I1 feeds into I2. */
1472 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1475 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1476 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1478 /* If the set in I2 needs to be kept around, we must make a copy of
1479 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1480 PATTERN (I2), we are only substituting for the original I1DEST, not into
1481 an already-substituted copy. This also prevents making self-referential
1482 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1485 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1486 ? gen_rtx (SET, VOIDmode, i2dest, i2src)
1490 i2pat = copy_rtx (i2pat);
1494 /* Substitute in the latest insn for the regs set by the earlier ones. */
1496 maxreg = max_reg_num ();
1500 /* It is possible that the source of I2 or I1 may be performing an
1501 unneeded operation, such as a ZERO_EXTEND of something that is known
1502 to have the high part zero. Handle that case by letting subst look at
1503 the innermost one of them.
1505 Another way to do this would be to have a function that tries to
1506 simplify a single insn instead of merging two or more insns. We don't
1507 do this because of the potential of infinite loops and because
1508 of the potential extra memory required. However, doing it the way
1509 we are is a bit of a kludge and doesn't catch all cases.
1511 But only do this if -fexpensive-optimizations since it slows things down
1512 and doesn't usually win. */
1514 if (flag_expensive_optimizations)
1516 /* Pass pc_rtx so no substitutions are done, just simplifications.
1517 The cases that we are interested in here do not involve the few
1518 cases were is_replaced is checked. */
1521 subst_low_cuid = INSN_CUID (i1);
1522 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1526 subst_low_cuid = INSN_CUID (i2);
1527 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1530 undobuf.previous_undos = undobuf.undos;
1534 /* Many machines that don't use CC0 have insns that can both perform an
1535 arithmetic operation and set the condition code. These operations will
1536 be represented as a PARALLEL with the first element of the vector
1537 being a COMPARE of an arithmetic operation with the constant zero.
1538 The second element of the vector will set some pseudo to the result
1539 of the same arithmetic operation. If we simplify the COMPARE, we won't
1540 match such a pattern and so will generate an extra insn. Here we test
1541 for this case, where both the comparison and the operation result are
1542 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1543 I2SRC. Later we will make the PARALLEL that contains I2. */
1545 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1546 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1547 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1548 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1551 enum machine_mode compare_mode;
1553 newpat = PATTERN (i3);
1554 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1558 #ifdef EXTRA_CC_MODES
1559 /* See if a COMPARE with the operand we substituted in should be done
1560 with the mode that is currently being used. If not, do the same
1561 processing we do in `subst' for a SET; namely, if the destination
1562 is used only once, try to replace it with a register of the proper
1563 mode and also replace the COMPARE. */
1564 if (undobuf.other_insn == 0
1565 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1566 &undobuf.other_insn))
1567 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1569 != GET_MODE (SET_DEST (newpat))))
1571 int regno = REGNO (SET_DEST (newpat));
1572 rtx new_dest = gen_rtx (REG, compare_mode, regno);
1574 if (regno < FIRST_PSEUDO_REGISTER
1575 || (reg_n_sets[regno] == 1 && ! added_sets_2
1576 && ! REG_USERVAR_P (SET_DEST (newpat))))
1578 if (regno >= FIRST_PSEUDO_REGISTER)
1579 SUBST (regno_reg_rtx[regno], new_dest);
1581 SUBST (SET_DEST (newpat), new_dest);
1582 SUBST (XEXP (*cc_use, 0), new_dest);
1583 SUBST (SET_SRC (newpat),
1584 gen_rtx_combine (COMPARE, compare_mode,
1585 i2src, const0_rtx));
1588 undobuf.other_insn = 0;
1595 n_occurrences = 0; /* `subst' counts here */
1597 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1598 need to make a unique copy of I2SRC each time we substitute it
1599 to avoid self-referential rtl. */
1601 subst_low_cuid = INSN_CUID (i2);
1602 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1603 ! i1_feeds_i3 && i1dest_in_i1src);
1604 undobuf.previous_undos = undobuf.undos;
1606 /* Record whether i2's body now appears within i3's body. */
1607 i2_is_used = n_occurrences;
1610 /* If we already got a failure, don't try to do more. Otherwise,
1611 try to substitute in I1 if we have it. */
1613 if (i1 && GET_CODE (newpat) != CLOBBER)
1615 /* Before we can do this substitution, we must redo the test done
1616 above (see detailed comments there) that ensures that I1DEST
1617 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1619 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1627 subst_low_cuid = INSN_CUID (i1);
1628 newpat = subst (newpat, i1dest, i1src, 0, 0);
1629 undobuf.previous_undos = undobuf.undos;
1632 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1633 to count all the ways that I2SRC and I1SRC can be used. */
1634 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
1635 && i2_is_used + added_sets_2 > 1)
1636 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
1637 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
1639 /* Fail if we tried to make a new register (we used to abort, but there's
1640 really no reason to). */
1641 || max_reg_num () != maxreg
1642 /* Fail if we couldn't do something and have a CLOBBER. */
1643 || GET_CODE (newpat) == CLOBBER
1644 /* Fail if this new pattern is a MULT and we didn't have one before
1645 at the outer level. */
1646 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
1653 /* If the actions of the earlier insns must be kept
1654 in addition to substituting them into the latest one,
1655 we must make a new PARALLEL for the latest insn
1656 to hold additional the SETs. */
1658 if (added_sets_1 || added_sets_2)
1662 if (GET_CODE (newpat) == PARALLEL)
1664 rtvec old = XVEC (newpat, 0);
1665 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
1666 newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets));
1667 bcopy ((char *) &old->elem[0], (char *) &XVECEXP (newpat, 0, 0),
1668 sizeof (old->elem[0]) * old->num_elem);
1673 total_sets = 1 + added_sets_1 + added_sets_2;
1674 newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets));
1675 XVECEXP (newpat, 0, 0) = old;
1679 XVECEXP (newpat, 0, --total_sets)
1680 = (GET_CODE (PATTERN (i1)) == PARALLEL
1681 ? gen_rtx (SET, VOIDmode, i1dest, i1src) : PATTERN (i1));
1685 /* If there is no I1, use I2's body as is. We used to also not do
1686 the subst call below if I2 was substituted into I3,
1687 but that could lose a simplification. */
1689 XVECEXP (newpat, 0, --total_sets) = i2pat;
1691 /* See comment where i2pat is assigned. */
1692 XVECEXP (newpat, 0, --total_sets)
1693 = subst (i2pat, i1dest, i1src, 0, 0);
1697 /* We come here when we are replacing a destination in I2 with the
1698 destination of I3. */
1699 validate_replacement:
1701 /* Note which hard regs this insn has as inputs. */
1702 mark_used_regs_combine (newpat);
1704 /* Is the result of combination a valid instruction? */
1706 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
1708 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
1709 the second SET's destination is a register that is unused. In that case,
1710 we just need the first SET. This can occur when simplifying a divmod
1711 insn. We *must* test for this case here because the code below that
1712 splits two independent SETs doesn't handle this case correctly when it
1713 updates the register status. Also check the case where the first
1714 SET's destination is unused. That would not cause incorrect code, but
1715 does cause an unneeded insn to remain. */
1717 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1718 && XVECLEN (newpat, 0) == 2
1719 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1720 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1721 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
1722 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
1723 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
1724 && asm_noperands (newpat) < 0)
1726 newpat = XVECEXP (newpat, 0, 0);
1728 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
1731 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1732 && XVECLEN (newpat, 0) == 2
1733 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1734 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1735 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
1736 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
1737 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
1738 && asm_noperands (newpat) < 0)
1740 newpat = XVECEXP (newpat, 0, 1);
1742 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
1745 /* If we were combining three insns and the result is a simple SET
1746 with no ASM_OPERANDS that wasn't recognized, try to split it into two
1747 insns. There are two ways to do this. It can be split using a
1748 machine-specific method (like when you have an addition of a large
1749 constant) or by combine in the function find_split_point. */
1751 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
1752 && asm_noperands (newpat) < 0)
1754 rtx m_split, *split;
1755 rtx ni2dest = i2dest;
1757 /* See if the MD file can split NEWPAT. If it can't, see if letting it
1758 use I2DEST as a scratch register will help. In the latter case,
1759 convert I2DEST to the mode of the source of NEWPAT if we can. */
1761 m_split = split_insns (newpat, i3);
1763 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
1764 inputs of NEWPAT. */
1766 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
1767 possible to try that as a scratch reg. This would require adding
1768 more code to make it work though. */
1770 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
1772 /* If I2DEST is a hard register or the only use of a pseudo,
1773 we can change its mode. */
1774 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
1775 && GET_MODE (SET_DEST (newpat)) != VOIDmode
1776 && GET_CODE (i2dest) == REG
1777 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
1778 || (reg_n_sets[REGNO (i2dest)] == 1 && ! added_sets_2
1779 && ! REG_USERVAR_P (i2dest))))
1780 ni2dest = gen_rtx (REG, GET_MODE (SET_DEST (newpat)),
1783 m_split = split_insns (gen_rtx (PARALLEL, VOIDmode,
1784 gen_rtvec (2, newpat,
1791 if (m_split && GET_CODE (m_split) == SEQUENCE
1792 && XVECLEN (m_split, 0) == 2
1793 && (next_real_insn (i2) == i3
1794 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)),
1798 rtx newi3pat = PATTERN (XVECEXP (m_split, 0, 1));
1799 newi2pat = PATTERN (XVECEXP (m_split, 0, 0));
1801 i3set = single_set (XVECEXP (m_split, 0, 1));
1802 i2set = single_set (XVECEXP (m_split, 0, 0));
1804 /* In case we changed the mode of I2DEST, replace it in the
1805 pseudo-register table here. We can't do it above in case this
1806 code doesn't get executed and we do a split the other way. */
1808 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
1809 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
1811 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes,
1814 /* If I2 or I3 has multiple SETs, we won't know how to track
1815 register status, so don't use these insns. If I2's destination
1816 is used between I2 and I3, we also can't use these insns. */
1818 if (i2_code_number >= 0 && i2set && i3set
1819 && (next_real_insn (i2) == i3
1820 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
1821 insn_code_number = recog_for_combine (&newi3pat, i3, &new_i3_notes,
1823 if (insn_code_number >= 0)
1826 /* It is possible that both insns now set the destination of I3.
1827 If so, we must show an extra use of it. */
1829 if (insn_code_number >= 0)
1831 rtx new_i3_dest = SET_DEST (i3set);
1832 rtx new_i2_dest = SET_DEST (i2set);
1834 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
1835 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
1836 || GET_CODE (new_i3_dest) == SUBREG)
1837 new_i3_dest = XEXP (new_i3_dest, 0);
1839 if (GET_CODE (new_i3_dest) == REG
1840 && GET_CODE (new_i2_dest) == REG
1841 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
1842 reg_n_sets[REGNO (SET_DEST (i2set))]++;
1846 /* If we can split it and use I2DEST, go ahead and see if that
1847 helps things be recognized. Verify that none of the registers
1848 are set between I2 and I3. */
1849 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
1851 && GET_CODE (i2dest) == REG
1853 /* We need I2DEST in the proper mode. If it is a hard register
1854 or the only use of a pseudo, we can change its mode. */
1855 && (GET_MODE (*split) == GET_MODE (i2dest)
1856 || GET_MODE (*split) == VOIDmode
1857 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
1858 || (reg_n_sets[REGNO (i2dest)] == 1 && ! added_sets_2
1859 && ! REG_USERVAR_P (i2dest)))
1860 && (next_real_insn (i2) == i3
1861 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
1862 /* We can't overwrite I2DEST if its value is still used by
1864 && ! reg_referenced_p (i2dest, newpat))
1866 rtx newdest = i2dest;
1867 enum rtx_code split_code = GET_CODE (*split);
1868 enum machine_mode split_mode = GET_MODE (*split);
1870 /* Get NEWDEST as a register in the proper mode. We have already
1871 validated that we can do this. */
1872 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
1874 newdest = gen_rtx (REG, split_mode, REGNO (i2dest));
1876 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
1877 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
1880 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
1881 an ASHIFT. This can occur if it was inside a PLUS and hence
1882 appeared to be a memory address. This is a kludge. */
1883 if (split_code == MULT
1884 && GET_CODE (XEXP (*split, 1)) == CONST_INT
1885 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
1887 SUBST (*split, gen_rtx_combine (ASHIFT, split_mode,
1888 XEXP (*split, 0), GEN_INT (i)));
1889 /* Update split_code because we may not have a multiply
1891 split_code = GET_CODE (*split);
1894 #ifdef INSN_SCHEDULING
1895 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
1896 be written as a ZERO_EXTEND. */
1897 if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM)
1898 SUBST (*split, gen_rtx_combine (ZERO_EXTEND, split_mode,
1902 newi2pat = gen_rtx_combine (SET, VOIDmode, newdest, *split);
1903 SUBST (*split, newdest);
1905 = recog_for_combine (&newi2pat, i2, &new_i2_notes, &i2_scratches);
1907 /* If the split point was a MULT and we didn't have one before,
1908 don't use one now. */
1909 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
1911 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
1915 /* Check for a case where we loaded from memory in a narrow mode and
1916 then sign extended it, but we need both registers. In that case,
1917 we have a PARALLEL with both loads from the same memory location.
1918 We can split this into a load from memory followed by a register-register
1919 copy. This saves at least one insn, more if register allocation can
1922 We cannot do this if the destination of the second assignment is
1923 a register that we have already assumed is zero-extended. Similarly
1924 for a SUBREG of such a register. */
1926 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
1927 && GET_CODE (newpat) == PARALLEL
1928 && XVECLEN (newpat, 0) == 2
1929 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1930 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
1931 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1932 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1933 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
1934 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1936 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
1937 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
1938 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
1939 (GET_CODE (temp) == REG
1940 && reg_nonzero_bits[REGNO (temp)] != 0
1941 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
1942 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
1943 && (reg_nonzero_bits[REGNO (temp)]
1944 != GET_MODE_MASK (word_mode))))
1945 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
1946 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
1947 (GET_CODE (temp) == REG
1948 && reg_nonzero_bits[REGNO (temp)] != 0
1949 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
1950 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
1951 && (reg_nonzero_bits[REGNO (temp)]
1952 != GET_MODE_MASK (word_mode)))))
1953 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
1954 SET_SRC (XVECEXP (newpat, 0, 1)))
1955 && ! find_reg_note (i3, REG_UNUSED,
1956 SET_DEST (XVECEXP (newpat, 0, 0))))
1960 newi2pat = XVECEXP (newpat, 0, 0);
1961 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
1962 newpat = XVECEXP (newpat, 0, 1);
1963 SUBST (SET_SRC (newpat),
1964 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
1966 = recog_for_combine (&newi2pat, i2, &new_i2_notes, &i2_scratches);
1968 if (i2_code_number >= 0)
1970 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
1972 if (insn_code_number >= 0)
1977 /* If we will be able to accept this, we have made a change to the
1978 destination of I3. This can invalidate a LOG_LINKS pointing
1979 to I3. No other part of combine.c makes such a transformation.
1981 The new I3 will have a destination that was previously the
1982 destination of I1 or I2 and which was used in i2 or I3. Call
1983 distribute_links to make a LOG_LINK from the next use of
1984 that destination. */
1986 PATTERN (i3) = newpat;
1987 distribute_links (gen_rtx (INSN_LIST, VOIDmode, i3, NULL_RTX));
1989 /* I3 now uses what used to be its destination and which is
1990 now I2's destination. That means we need a LOG_LINK from
1991 I3 to I2. But we used to have one, so we still will.
1993 However, some later insn might be using I2's dest and have
1994 a LOG_LINK pointing at I3. We must remove this link.
1995 The simplest way to remove the link is to point it at I1,
1996 which we know will be a NOTE. */
1998 for (insn = NEXT_INSN (i3);
1999 insn && (this_basic_block == n_basic_blocks - 1
2000 || insn != basic_block_head[this_basic_block + 1]);
2001 insn = NEXT_INSN (insn))
2003 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
2004 && reg_referenced_p (ni2dest, PATTERN (insn)))
2006 for (link = LOG_LINKS (insn); link;
2007 link = XEXP (link, 1))
2008 if (XEXP (link, 0) == i3)
2009 XEXP (link, 0) = i1;
2017 /* Similarly, check for a case where we have a PARALLEL of two independent
2018 SETs but we started with three insns. In this case, we can do the sets
2019 as two separate insns. This case occurs when some SET allows two
2020 other insns to combine, but the destination of that SET is still live. */
2022 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2023 && GET_CODE (newpat) == PARALLEL
2024 && XVECLEN (newpat, 0) == 2
2025 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2026 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2027 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2028 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2029 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2030 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2031 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2033 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2034 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2035 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2036 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2037 XVECEXP (newpat, 0, 0))
2038 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2039 XVECEXP (newpat, 0, 1)))
2041 newi2pat = XVECEXP (newpat, 0, 1);
2042 newpat = XVECEXP (newpat, 0, 0);
2045 = recog_for_combine (&newi2pat, i2, &new_i2_notes, &i2_scratches);
2047 if (i2_code_number >= 0)
2049 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
2052 /* If it still isn't recognized, fail and change things back the way they
2054 if ((insn_code_number < 0
2055 /* Is the result a reasonable ASM_OPERANDS? */
2056 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2062 /* If we had to change another insn, make sure it is valid also. */
2063 if (undobuf.other_insn)
2065 rtx other_pat = PATTERN (undobuf.other_insn);
2066 rtx new_other_notes;
2069 CLEAR_HARD_REG_SET (newpat_used_regs);
2072 = recog_for_combine (&other_pat, undobuf.other_insn,
2073 &new_other_notes, &other_scratches);
2075 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2081 PATTERN (undobuf.other_insn) = other_pat;
2083 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2084 are still valid. Then add any non-duplicate notes added by
2085 recog_for_combine. */
2086 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2088 next = XEXP (note, 1);
2090 if (REG_NOTE_KIND (note) == REG_UNUSED
2091 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2093 if (GET_CODE (XEXP (note, 0)) == REG)
2094 reg_n_deaths[REGNO (XEXP (note, 0))]--;
2096 remove_note (undobuf.other_insn, note);
2100 for (note = new_other_notes; note; note = XEXP (note, 1))
2101 if (GET_CODE (XEXP (note, 0)) == REG)
2102 reg_n_deaths[REGNO (XEXP (note, 0))]++;
2104 distribute_notes (new_other_notes, undobuf.other_insn,
2105 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2108 /* We now know that we can do this combination. Merge the insns and
2109 update the status of registers and LOG_LINKS. */
2112 rtx i3notes, i2notes, i1notes = 0;
2113 rtx i3links, i2links, i1links = 0;
2116 /* Compute which registers we expect to eliminate. */
2117 rtx elim_i2 = (newi2pat || i2dest_in_i2src || i2dest_in_i1src
2119 rtx elim_i1 = i1 == 0 || i1dest_in_i1src ? 0 : i1dest;
2121 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2123 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2124 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2126 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2128 /* Ensure that we do not have something that should not be shared but
2129 occurs multiple times in the new insns. Check this by first
2130 resetting all the `used' flags and then copying anything is shared. */
2132 reset_used_flags (i3notes);
2133 reset_used_flags (i2notes);
2134 reset_used_flags (i1notes);
2135 reset_used_flags (newpat);
2136 reset_used_flags (newi2pat);
2137 if (undobuf.other_insn)
2138 reset_used_flags (PATTERN (undobuf.other_insn));
2140 i3notes = copy_rtx_if_shared (i3notes);
2141 i2notes = copy_rtx_if_shared (i2notes);
2142 i1notes = copy_rtx_if_shared (i1notes);
2143 newpat = copy_rtx_if_shared (newpat);
2144 newi2pat = copy_rtx_if_shared (newi2pat);
2145 if (undobuf.other_insn)
2146 reset_used_flags (PATTERN (undobuf.other_insn));
2148 INSN_CODE (i3) = insn_code_number;
2149 PATTERN (i3) = newpat;
2150 if (undobuf.other_insn)
2151 INSN_CODE (undobuf.other_insn) = other_code_number;
2153 /* We had one special case above where I2 had more than one set and
2154 we replaced a destination of one of those sets with the destination
2155 of I3. In that case, we have to update LOG_LINKS of insns later
2156 in this basic block. Note that this (expensive) case is rare.
2158 Also, in this case, we must pretend that all REG_NOTEs for I2
2159 actually came from I3, so that REG_UNUSED notes from I2 will be
2160 properly handled. */
2162 if (i3_subst_into_i2)
2164 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2165 if (GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
2166 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2167 && ! find_reg_note (i2, REG_UNUSED,
2168 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2169 for (temp = NEXT_INSN (i2);
2170 temp && (this_basic_block == n_basic_blocks - 1
2171 || basic_block_head[this_basic_block] != temp);
2172 temp = NEXT_INSN (temp))
2173 if (temp != i3 && GET_RTX_CLASS (GET_CODE (temp)) == 'i')
2174 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2175 if (XEXP (link, 0) == i2)
2176 XEXP (link, 0) = i3;
2181 while (XEXP (link, 1))
2182 link = XEXP (link, 1);
2183 XEXP (link, 1) = i2notes;
2197 INSN_CODE (i2) = i2_code_number;
2198 PATTERN (i2) = newi2pat;
2202 PUT_CODE (i2, NOTE);
2203 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2204 NOTE_SOURCE_FILE (i2) = 0;
2211 PUT_CODE (i1, NOTE);
2212 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2213 NOTE_SOURCE_FILE (i1) = 0;
2216 /* Get death notes for everything that is now used in either I3 or
2217 I2 and used to die in a previous insn. If we built two new
2218 patterns, move from I1 to I2 then I2 to I3 so that we get the
2219 proper movement on registers that I2 modifies. */
2223 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2224 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2227 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2230 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2232 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
2235 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
2238 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
2241 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2244 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2245 know these are REG_UNUSED and want them to go to the desired insn,
2246 so we always pass it as i3. We have not counted the notes in
2247 reg_n_deaths yet, so we need to do so now. */
2249 if (newi2pat && new_i2_notes)
2251 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2252 if (GET_CODE (XEXP (temp, 0)) == REG)
2253 reg_n_deaths[REGNO (XEXP (temp, 0))]++;
2255 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2260 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2261 if (GET_CODE (XEXP (temp, 0)) == REG)
2262 reg_n_deaths[REGNO (XEXP (temp, 0))]++;
2264 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
2267 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2268 put a REG_DEAD note for it somewhere. Similarly for I2 and I1.
2269 Show an additional death due to the REG_DEAD note we make here. If
2270 we discard it in distribute_notes, we will decrement it again. */
2274 if (GET_CODE (i3dest_killed) == REG)
2275 reg_n_deaths[REGNO (i3dest_killed)]++;
2277 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i3dest_killed,
2279 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2280 NULL_RTX, NULL_RTX);
2283 /* For I2 and I1, we have to be careful. If NEWI2PAT exists and sets
2284 I2DEST or I1DEST, the death must be somewhere before I2, not I3. If
2285 we passed I3 in that case, it might delete I2. */
2287 if (i2dest_in_i2src)
2289 if (GET_CODE (i2dest) == REG)
2290 reg_n_deaths[REGNO (i2dest)]++;
2292 if (newi2pat && reg_set_p (i2dest, newi2pat))
2293 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i2dest, NULL_RTX),
2294 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2296 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i2dest, NULL_RTX),
2297 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2298 NULL_RTX, NULL_RTX);
2301 if (i1dest_in_i1src)
2303 if (GET_CODE (i1dest) == REG)
2304 reg_n_deaths[REGNO (i1dest)]++;
2306 if (newi2pat && reg_set_p (i1dest, newi2pat))
2307 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i1dest, NULL_RTX),
2308 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2310 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i1dest, NULL_RTX),
2311 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2312 NULL_RTX, NULL_RTX);
2315 distribute_links (i3links);
2316 distribute_links (i2links);
2317 distribute_links (i1links);
2319 if (GET_CODE (i2dest) == REG)
2322 rtx i2_insn = 0, i2_val = 0, set;
2324 /* The insn that used to set this register doesn't exist, and
2325 this life of the register may not exist either. See if one of
2326 I3's links points to an insn that sets I2DEST. If it does,
2327 that is now the last known value for I2DEST. If we don't update
2328 this and I2 set the register to a value that depended on its old
2329 contents, we will get confused. If this insn is used, thing
2330 will be set correctly in combine_instructions. */
2332 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2333 if ((set = single_set (XEXP (link, 0))) != 0
2334 && rtx_equal_p (i2dest, SET_DEST (set)))
2335 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2337 record_value_for_reg (i2dest, i2_insn, i2_val);
2339 /* If the reg formerly set in I2 died only once and that was in I3,
2340 zero its use count so it won't make `reload' do any work. */
2341 if (! added_sets_2 && newi2pat == 0 && ! i2dest_in_i2src)
2343 regno = REGNO (i2dest);
2344 reg_n_sets[regno]--;
2345 if (reg_n_sets[regno] == 0
2346 && ! (basic_block_live_at_start[0][regno / REGSET_ELT_BITS]
2347 & ((REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS))))
2348 reg_n_refs[regno] = 0;
2352 if (i1 && GET_CODE (i1dest) == REG)
2355 rtx i1_insn = 0, i1_val = 0, set;
2357 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2358 if ((set = single_set (XEXP (link, 0))) != 0
2359 && rtx_equal_p (i1dest, SET_DEST (set)))
2360 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2362 record_value_for_reg (i1dest, i1_insn, i1_val);
2364 regno = REGNO (i1dest);
2365 if (! added_sets_1 && ! i1dest_in_i1src)
2367 reg_n_sets[regno]--;
2368 if (reg_n_sets[regno] == 0
2369 && ! (basic_block_live_at_start[0][regno / REGSET_ELT_BITS]
2370 & ((REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS))))
2371 reg_n_refs[regno] = 0;
2375 /* Update reg_nonzero_bits et al for any changes that may have been made
2378 note_stores (newpat, set_nonzero_bits_and_sign_copies);
2380 note_stores (newi2pat, set_nonzero_bits_and_sign_copies);
2382 /* If we added any (clobber (scratch)), add them to the max for a
2383 block. This is a very pessimistic calculation, since we might
2384 have had them already and this might not be the worst block, but
2385 it's not worth doing any better. */
2386 max_scratch += i3_scratches + i2_scratches + other_scratches;
2388 /* If I3 is now an unconditional jump, ensure that it has a
2389 BARRIER following it since it may have initially been a
2390 conditional jump. It may also be the last nonnote insn. */
2392 if ((GET_CODE (newpat) == RETURN || simplejump_p (i3))
2393 && ((temp = next_nonnote_insn (i3)) == NULL_RTX
2394 || GET_CODE (temp) != BARRIER))
2395 emit_barrier_after (i3);
2398 combine_successes++;
2400 /* Clear this here, so that subsequent get_last_value calls are not
2402 subst_prev_insn = NULL_RTX;
2404 if (added_links_insn
2405 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2406 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2407 return added_links_insn;
2409 return newi2pat ? i2 : i3;
2412 /* Undo all the modifications recorded in undobuf. */
2417 struct undo *undo, *next;
2419 for (undo = undobuf.undos; undo; undo = next)
2423 *undo->where.i = undo->old_contents.i;
2425 *undo->where.r = undo->old_contents.r;
2427 undo->next = undobuf.frees;
2428 undobuf.frees = undo;
2431 obfree (undobuf.storage);
2432 undobuf.undos = undobuf.previous_undos = 0;
2434 /* Clear this here, so that subsequent get_last_value calls are not
2436 subst_prev_insn = NULL_RTX;
2439 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2440 where we have an arithmetic expression and return that point. LOC will
2443 try_combine will call this function to see if an insn can be split into
2447 find_split_point (loc, insn)
2452 enum rtx_code code = GET_CODE (x);
2454 int len = 0, pos, unsignedp;
2457 /* First special-case some codes. */
2461 #ifdef INSN_SCHEDULING
2462 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2464 if (GET_CODE (SUBREG_REG (x)) == MEM)
2467 return find_split_point (&SUBREG_REG (x), insn);
2471 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2472 using LO_SUM and HIGH. */
2473 if (GET_CODE (XEXP (x, 0)) == CONST
2474 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2477 gen_rtx_combine (LO_SUM, Pmode,
2478 gen_rtx_combine (HIGH, Pmode, XEXP (x, 0)),
2480 return &XEXP (XEXP (x, 0), 0);
2484 /* If we have a PLUS whose second operand is a constant and the
2485 address is not valid, perhaps will can split it up using
2486 the machine-specific way to split large constants. We use
2487 the first pseudo-reg (one of the virtual regs) as a placeholder;
2488 it will not remain in the result. */
2489 if (GET_CODE (XEXP (x, 0)) == PLUS
2490 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2491 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2493 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2494 rtx seq = split_insns (gen_rtx (SET, VOIDmode, reg, XEXP (x, 0)),
2497 /* This should have produced two insns, each of which sets our
2498 placeholder. If the source of the second is a valid address,
2499 we can make put both sources together and make a split point
2502 if (seq && XVECLEN (seq, 0) == 2
2503 && GET_CODE (XVECEXP (seq, 0, 0)) == INSN
2504 && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET
2505 && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg
2506 && ! reg_mentioned_p (reg,
2507 SET_SRC (PATTERN (XVECEXP (seq, 0, 0))))
2508 && GET_CODE (XVECEXP (seq, 0, 1)) == INSN
2509 && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET
2510 && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg
2511 && memory_address_p (GET_MODE (x),
2512 SET_SRC (PATTERN (XVECEXP (seq, 0, 1)))))
2514 rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0)));
2515 rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1)));
2517 /* Replace the placeholder in SRC2 with SRC1. If we can
2518 find where in SRC2 it was placed, that can become our
2519 split point and we can replace this address with SRC2.
2520 Just try two obvious places. */
2522 src2 = replace_rtx (src2, reg, src1);
2524 if (XEXP (src2, 0) == src1)
2525 split = &XEXP (src2, 0);
2526 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2527 && XEXP (XEXP (src2, 0), 0) == src1)
2528 split = &XEXP (XEXP (src2, 0), 0);
2532 SUBST (XEXP (x, 0), src2);
2537 /* If that didn't work, perhaps the first operand is complex and
2538 needs to be computed separately, so make a split point there.
2539 This will occur on machines that just support REG + CONST
2540 and have a constant moved through some previous computation. */
2542 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
2543 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
2544 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
2546 return &XEXP (XEXP (x, 0), 0);
2552 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2553 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2554 we need to put the operand into a register. So split at that
2557 if (SET_DEST (x) == cc0_rtx
2558 && GET_CODE (SET_SRC (x)) != COMPARE
2559 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
2560 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
2561 && ! (GET_CODE (SET_SRC (x)) == SUBREG
2562 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
2563 return &SET_SRC (x);
2566 /* See if we can split SET_SRC as it stands. */
2567 split = find_split_point (&SET_SRC (x), insn);
2568 if (split && split != &SET_SRC (x))
2571 /* See if we can split SET_DEST as it stands. */
2572 split = find_split_point (&SET_DEST (x), insn);
2573 if (split && split != &SET_DEST (x))
2576 /* See if this is a bitfield assignment with everything constant. If
2577 so, this is an IOR of an AND, so split it into that. */
2578 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
2579 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
2580 <= HOST_BITS_PER_WIDE_INT)
2581 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
2582 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
2583 && GET_CODE (SET_SRC (x)) == CONST_INT
2584 && ((INTVAL (XEXP (SET_DEST (x), 1))
2585 + INTVAL (XEXP (SET_DEST (x), 2)))
2586 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
2587 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
2589 int pos = INTVAL (XEXP (SET_DEST (x), 2));
2590 int len = INTVAL (XEXP (SET_DEST (x), 1));
2591 int src = INTVAL (SET_SRC (x));
2592 rtx dest = XEXP (SET_DEST (x), 0);
2593 enum machine_mode mode = GET_MODE (dest);
2594 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
2596 if (BITS_BIG_ENDIAN)
2597 pos = GET_MODE_BITSIZE (mode) - len - pos;
2601 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
2604 gen_binary (IOR, mode,
2605 gen_binary (AND, mode, dest,
2606 GEN_INT (~ (mask << pos)
2607 & GET_MODE_MASK (mode))),
2608 GEN_INT (src << pos)));
2610 SUBST (SET_DEST (x), dest);
2612 split = find_split_point (&SET_SRC (x), insn);
2613 if (split && split != &SET_SRC (x))
2617 /* Otherwise, see if this is an operation that we can split into two.
2618 If so, try to split that. */
2619 code = GET_CODE (SET_SRC (x));
2624 /* If we are AND'ing with a large constant that is only a single
2625 bit and the result is only being used in a context where we
2626 need to know if it is zero or non-zero, replace it with a bit
2627 extraction. This will avoid the large constant, which might
2628 have taken more than one insn to make. If the constant were
2629 not a valid argument to the AND but took only one insn to make,
2630 this is no worse, but if it took more than one insn, it will
2633 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2634 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
2635 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
2636 && GET_CODE (SET_DEST (x)) == REG
2637 && (split = find_single_use (SET_DEST (x), insn, NULL_PTR)) != 0
2638 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
2639 && XEXP (*split, 0) == SET_DEST (x)
2640 && XEXP (*split, 1) == const0_rtx)
2642 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
2643 XEXP (SET_SRC (x), 0),
2644 pos, NULL_RTX, 1, 1, 0, 0);
2645 if (extraction != 0)
2647 SUBST (SET_SRC (x), extraction);
2648 return find_split_point (loc, insn);
2654 inner = XEXP (SET_SRC (x), 0);
2656 len = GET_MODE_BITSIZE (GET_MODE (inner));
2662 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2663 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
2665 inner = XEXP (SET_SRC (x), 0);
2666 len = INTVAL (XEXP (SET_SRC (x), 1));
2667 pos = INTVAL (XEXP (SET_SRC (x), 2));
2669 if (BITS_BIG_ENDIAN)
2670 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
2671 unsignedp = (code == ZERO_EXTRACT);
2676 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
2678 enum machine_mode mode = GET_MODE (SET_SRC (x));
2680 /* For unsigned, we have a choice of a shift followed by an
2681 AND or two shifts. Use two shifts for field sizes where the
2682 constant might be too large. We assume here that we can
2683 always at least get 8-bit constants in an AND insn, which is
2684 true for every current RISC. */
2686 if (unsignedp && len <= 8)
2691 gen_rtx_combine (LSHIFTRT, mode,
2692 gen_lowpart_for_combine (mode, inner),
2694 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
2696 split = find_split_point (&SET_SRC (x), insn);
2697 if (split && split != &SET_SRC (x))
2704 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
2705 gen_rtx_combine (ASHIFT, mode,
2706 gen_lowpart_for_combine (mode, inner),
2707 GEN_INT (GET_MODE_BITSIZE (mode)
2709 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
2711 split = find_split_point (&SET_SRC (x), insn);
2712 if (split && split != &SET_SRC (x))
2717 /* See if this is a simple operation with a constant as the second
2718 operand. It might be that this constant is out of range and hence
2719 could be used as a split point. */
2720 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2721 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2722 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
2723 && CONSTANT_P (XEXP (SET_SRC (x), 1))
2724 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
2725 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
2726 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
2728 return &XEXP (SET_SRC (x), 1);
2730 /* Finally, see if this is a simple operation with its first operand
2731 not in a register. The operation might require this operand in a
2732 register, so return it as a split point. We can always do this
2733 because if the first operand were another operation, we would have
2734 already found it as a split point. */
2735 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2736 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2737 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
2738 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
2739 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
2740 return &XEXP (SET_SRC (x), 0);
2746 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
2747 it is better to write this as (not (ior A B)) so we can split it.
2748 Similarly for IOR. */
2749 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
2752 gen_rtx_combine (NOT, GET_MODE (x),
2753 gen_rtx_combine (code == IOR ? AND : IOR,
2755 XEXP (XEXP (x, 0), 0),
2756 XEXP (XEXP (x, 1), 0))));
2757 return find_split_point (loc, insn);
2760 /* Many RISC machines have a large set of logical insns. If the
2761 second operand is a NOT, put it first so we will try to split the
2762 other operand first. */
2763 if (GET_CODE (XEXP (x, 1)) == NOT)
2765 rtx tem = XEXP (x, 0);
2766 SUBST (XEXP (x, 0), XEXP (x, 1));
2767 SUBST (XEXP (x, 1), tem);
2772 /* Otherwise, select our actions depending on our rtx class. */
2773 switch (GET_RTX_CLASS (code))
2775 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
2777 split = find_split_point (&XEXP (x, 2), insn);
2780 /* ... fall through ... */
2784 split = find_split_point (&XEXP (x, 1), insn);
2787 /* ... fall through ... */
2789 /* Some machines have (and (shift ...) ...) insns. If X is not
2790 an AND, but XEXP (X, 0) is, use it as our split point. */
2791 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
2792 return &XEXP (x, 0);
2794 split = find_split_point (&XEXP (x, 0), insn);
2800 /* Otherwise, we don't have a split point. */
2804 /* Throughout X, replace FROM with TO, and return the result.
2805 The result is TO if X is FROM;
2806 otherwise the result is X, but its contents may have been modified.
2807 If they were modified, a record was made in undobuf so that
2808 undo_all will (among other things) return X to its original state.
2810 If the number of changes necessary is too much to record to undo,
2811 the excess changes are not made, so the result is invalid.
2812 The changes already made can still be undone.
2813 undobuf.num_undo is incremented for such changes, so by testing that
2814 the caller can tell whether the result is valid.
2816 `n_occurrences' is incremented each time FROM is replaced.
2818 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
2820 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
2821 by copying if `n_occurrences' is non-zero. */
2824 subst (x, from, to, in_dest, unique_copy)
2825 register rtx x, from, to;
2829 register enum rtx_code code = GET_CODE (x);
2830 enum machine_mode op0_mode = VOIDmode;
2832 register int len, i;
2835 /* Two expressions are equal if they are identical copies of a shared
2836 RTX or if they are both registers with the same register number
2839 #define COMBINE_RTX_EQUAL_P(X,Y) \
2841 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
2842 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
2844 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
2847 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
2850 /* If X and FROM are the same register but different modes, they will
2851 not have been seen as equal above. However, flow.c will make a
2852 LOG_LINKS entry for that case. If we do nothing, we will try to
2853 rerecognize our original insn and, when it succeeds, we will
2854 delete the feeding insn, which is incorrect.
2856 So force this insn not to match in this (rare) case. */
2857 if (! in_dest && code == REG && GET_CODE (from) == REG
2858 && REGNO (x) == REGNO (from))
2859 return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
2861 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
2862 of which may contain things that can be combined. */
2863 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
2866 /* It is possible to have a subexpression appear twice in the insn.
2867 Suppose that FROM is a register that appears within TO.
2868 Then, after that subexpression has been scanned once by `subst',
2869 the second time it is scanned, TO may be found. If we were
2870 to scan TO here, we would find FROM within it and create a
2871 self-referent rtl structure which is completely wrong. */
2872 if (COMBINE_RTX_EQUAL_P (x, to))
2875 len = GET_RTX_LENGTH (code);
2876 fmt = GET_RTX_FORMAT (code);
2878 /* We don't need to process a SET_DEST that is a register, CC0, or PC, so
2879 set up to skip this common case. All other cases where we want to
2880 suppress replacing something inside a SET_SRC are handled via the
2883 && (GET_CODE (SET_DEST (x)) == REG
2884 || GET_CODE (SET_DEST (x)) == CC0
2885 || GET_CODE (SET_DEST (x)) == PC))
2888 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
2891 op0_mode = GET_MODE (XEXP (x, 0));
2893 for (i = 0; i < len; i++)
2898 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2900 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
2902 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
2907 new = subst (XVECEXP (x, i, j), from, to, 0, unique_copy);
2909 /* If this substitution failed, this whole thing fails. */
2910 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
2914 SUBST (XVECEXP (x, i, j), new);
2917 else if (fmt[i] == 'e')
2919 if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
2921 /* In general, don't install a subreg involving two modes not
2922 tieable. It can worsen register allocation, and can even
2923 make invalid reload insns, since the reg inside may need to
2924 be copied from in the outside mode, and that may be invalid
2925 if it is an fp reg copied in integer mode.
2927 We allow two exceptions to this: It is valid if it is inside
2928 another SUBREG and the mode of that SUBREG and the mode of
2929 the inside of TO is tieable and it is valid if X is a SET
2930 that copies FROM to CC0. */
2931 if (GET_CODE (to) == SUBREG
2932 && ! MODES_TIEABLE_P (GET_MODE (to),
2933 GET_MODE (SUBREG_REG (to)))
2934 && ! (code == SUBREG
2935 && MODES_TIEABLE_P (GET_MODE (x),
2936 GET_MODE (SUBREG_REG (to))))
2938 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
2941 return gen_rtx (CLOBBER, VOIDmode, const0_rtx);
2943 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
2947 /* If we are in a SET_DEST, suppress most cases unless we
2948 have gone inside a MEM, in which case we want to
2949 simplify the address. We assume here that things that
2950 are actually part of the destination have their inner
2951 parts in the first expression. This is true for SUBREG,
2952 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
2953 things aside from REG and MEM that should appear in a
2955 new = subst (XEXP (x, i), from, to,
2957 && (code == SUBREG || code == STRICT_LOW_PART
2958 || code == ZERO_EXTRACT))
2960 && i == 0), unique_copy);
2962 /* If we found that we will have to reject this combination,
2963 indicate that by returning the CLOBBER ourselves, rather than
2964 an expression containing it. This will speed things up as
2965 well as prevent accidents where two CLOBBERs are considered
2966 to be equal, thus producing an incorrect simplification. */
2968 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
2971 SUBST (XEXP (x, i), new);
2975 /* Try to simplify X. If the simplification changed the code, it is likely
2976 that further simplification will help, so loop, but limit the number
2977 of repetitions that will be performed. */
2979 for (i = 0; i < 4; i++)
2981 /* If X is sufficiently simple, don't bother trying to do anything
2983 if (code != CONST_INT && code != REG && code != CLOBBER)
2984 x = simplify_rtx (x, op0_mode, i == 3, in_dest);
2986 if (GET_CODE (x) == code)
2989 code = GET_CODE (x);
2991 /* We no longer know the original mode of operand 0 since we
2992 have changed the form of X) */
2993 op0_mode = VOIDmode;
2999 /* Simplify X, a piece of RTL. We just operate on the expression at the
3000 outer level; call `subst' to simplify recursively. Return the new
3003 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3004 will be the iteration even if an expression with a code different from
3005 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3008 simplify_rtx (x, op0_mode, last, in_dest)
3010 enum machine_mode op0_mode;
3014 enum rtx_code code = GET_CODE (x);
3015 enum machine_mode mode = GET_MODE (x);
3019 /* If this is a commutative operation, put a constant last and a complex
3020 expression first. We don't need to do this for comparisons here. */
3021 if (GET_RTX_CLASS (code) == 'c'
3022 && ((CONSTANT_P (XEXP (x, 0)) && GET_CODE (XEXP (x, 1)) != CONST_INT)
3023 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == 'o'
3024 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')
3025 || (GET_CODE (XEXP (x, 0)) == SUBREG
3026 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o'
3027 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')))
3030 SUBST (XEXP (x, 0), XEXP (x, 1));
3031 SUBST (XEXP (x, 1), temp);
3034 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3035 sign extension of a PLUS with a constant, reverse the order of the sign
3036 extension and the addition. Note that this not the same as the original
3037 code, but overflow is undefined for signed values. Also note that the
3038 PLUS will have been partially moved "inside" the sign-extension, so that
3039 the first operand of X will really look like:
3040 (ashiftrt (plus (ashift A C4) C5) C4).
3042 (plus (ashiftrt (ashift A C4) C2) C4)
3043 and replace the first operand of X with that expression. Later parts
3044 of this function may simplify the expression further.
3046 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3047 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3048 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3050 We do this to simplify address expressions. */
3052 if ((code == PLUS || code == MINUS || code == MULT)
3053 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3054 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3055 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3056 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3057 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3058 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3059 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3060 && (temp = simplify_binary_operation (ASHIFTRT, mode,
3061 XEXP (XEXP (XEXP (x, 0), 0), 1),
3062 XEXP (XEXP (x, 0), 1))) != 0)
3065 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3066 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3067 INTVAL (XEXP (XEXP (x, 0), 1)));
3069 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3070 INTVAL (XEXP (XEXP (x, 0), 1)));
3072 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3075 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3076 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3077 things. Check for cases where both arms are testing the same
3080 Don't do anything if all operands are very simple. */
3082 if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c'
3083 || GET_RTX_CLASS (code) == '<')
3084 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3085 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3086 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3088 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'
3089 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3090 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1))))
3092 || (GET_RTX_CLASS (code) == '1'
3093 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3094 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3095 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3098 rtx cond, true, false;
3100 cond = if_then_else_cond (x, &true, &false);
3103 rtx cop1 = const0_rtx;
3104 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3106 if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<')
3109 /* Simplify the alternative arms; this may collapse the true and
3110 false arms to store-flag values. */
3111 true = subst (true, pc_rtx, pc_rtx, 0, 0);
3112 false = subst (false, pc_rtx, pc_rtx, 0, 0);
3114 /* Restarting if we generate a store-flag expression will cause
3115 us to loop. Just drop through in this case. */
3117 /* If the result values are STORE_FLAG_VALUE and zero, we can
3118 just make the comparison operation. */
3119 if (true == const_true_rtx && false == const0_rtx)
3120 x = gen_binary (cond_code, mode, cond, cop1);
3121 else if (true == const0_rtx && false == const_true_rtx)
3122 x = gen_binary (reverse_condition (cond_code), mode, cond, cop1);
3124 /* Likewise, we can make the negate of a comparison operation
3125 if the result values are - STORE_FLAG_VALUE and zero. */
3126 else if (GET_CODE (true) == CONST_INT
3127 && INTVAL (true) == - STORE_FLAG_VALUE
3128 && false == const0_rtx)
3129 x = gen_unary (NEG, mode, mode,
3130 gen_binary (cond_code, mode, cond, cop1));
3131 else if (GET_CODE (false) == CONST_INT
3132 && INTVAL (false) == - STORE_FLAG_VALUE
3133 && true == const0_rtx)
3134 x = gen_unary (NEG, mode, mode,
3135 gen_binary (reverse_condition (cond_code),
3138 return gen_rtx (IF_THEN_ELSE, mode,
3139 gen_binary (cond_code, VOIDmode, cond, cop1),
3142 code = GET_CODE (x);
3143 op0_mode = VOIDmode;
3147 /* Try to fold this expression in case we have constants that weren't
3150 switch (GET_RTX_CLASS (code))
3153 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3156 temp = simplify_relational_operation (code, op0_mode,
3157 XEXP (x, 0), XEXP (x, 1));
3158 #ifdef FLOAT_STORE_FLAG_VALUE
3159 if (temp != 0 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
3160 temp = ((temp == const0_rtx) ? CONST0_RTX (GET_MODE (x))
3161 : immed_real_const_1 (FLOAT_STORE_FLAG_VALUE, GET_MODE (x)));
3166 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3170 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3171 XEXP (x, 1), XEXP (x, 2));
3176 x = temp, code = GET_CODE (temp);
3178 /* First see if we can apply the inverse distributive law. */
3179 if (code == PLUS || code == MINUS
3180 || code == AND || code == IOR || code == XOR)
3182 x = apply_distributive_law (x);
3183 code = GET_CODE (x);
3186 /* If CODE is an associative operation not otherwise handled, see if we
3187 can associate some operands. This can win if they are constants or
3188 if they are logically related (i.e. (a & b) & a. */
3189 if ((code == PLUS || code == MINUS
3190 || code == MULT || code == AND || code == IOR || code == XOR
3191 || code == DIV || code == UDIV
3192 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3193 && INTEGRAL_MODE_P (mode))
3195 if (GET_CODE (XEXP (x, 0)) == code)
3197 rtx other = XEXP (XEXP (x, 0), 0);
3198 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3199 rtx inner_op1 = XEXP (x, 1);
3202 /* Make sure we pass the constant operand if any as the second
3203 one if this is a commutative operation. */
3204 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
3206 rtx tem = inner_op0;
3207 inner_op0 = inner_op1;
3210 inner = simplify_binary_operation (code == MINUS ? PLUS
3211 : code == DIV ? MULT
3212 : code == UDIV ? MULT
3214 mode, inner_op0, inner_op1);
3216 /* For commutative operations, try the other pair if that one
3218 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
3220 other = XEXP (XEXP (x, 0), 1);
3221 inner = simplify_binary_operation (code, mode,
3222 XEXP (XEXP (x, 0), 0),
3227 return gen_binary (code, mode, other, inner);
3231 /* A little bit of algebraic simplification here. */
3235 /* Ensure that our address has any ASHIFTs converted to MULT in case
3236 address-recognizing predicates are called later. */
3237 temp = make_compound_operation (XEXP (x, 0), MEM);
3238 SUBST (XEXP (x, 0), temp);
3242 /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG
3243 is paradoxical. If we can't do that safely, then it becomes
3244 something nonsensical so that this combination won't take place. */
3246 if (GET_CODE (SUBREG_REG (x)) == MEM
3247 && (GET_MODE_SIZE (mode)
3248 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
3250 rtx inner = SUBREG_REG (x);
3251 int endian_offset = 0;
3252 /* Don't change the mode of the MEM
3253 if that would change the meaning of the address. */
3254 if (MEM_VOLATILE_P (SUBREG_REG (x))
3255 || mode_dependent_address_p (XEXP (inner, 0)))
3256 return gen_rtx (CLOBBER, mode, const0_rtx);
3258 if (BYTES_BIG_ENDIAN)
3260 if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
3261 endian_offset += UNITS_PER_WORD - GET_MODE_SIZE (mode);
3262 if (GET_MODE_SIZE (GET_MODE (inner)) < UNITS_PER_WORD)
3263 endian_offset -= (UNITS_PER_WORD
3264 - GET_MODE_SIZE (GET_MODE (inner)));
3266 /* Note if the plus_constant doesn't make a valid address
3267 then this combination won't be accepted. */
3268 x = gen_rtx (MEM, mode,
3269 plus_constant (XEXP (inner, 0),
3270 (SUBREG_WORD (x) * UNITS_PER_WORD
3272 MEM_VOLATILE_P (x) = MEM_VOLATILE_P (inner);
3273 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (inner);
3274 MEM_IN_STRUCT_P (x) = MEM_IN_STRUCT_P (inner);
3278 /* If we are in a SET_DEST, these other cases can't apply. */
3282 /* Changing mode twice with SUBREG => just change it once,
3283 or not at all if changing back to starting mode. */
3284 if (GET_CODE (SUBREG_REG (x)) == SUBREG)
3286 if (mode == GET_MODE (SUBREG_REG (SUBREG_REG (x)))
3287 && SUBREG_WORD (x) == 0 && SUBREG_WORD (SUBREG_REG (x)) == 0)
3288 return SUBREG_REG (SUBREG_REG (x));
3290 SUBST_INT (SUBREG_WORD (x),
3291 SUBREG_WORD (x) + SUBREG_WORD (SUBREG_REG (x)));
3292 SUBST (SUBREG_REG (x), SUBREG_REG (SUBREG_REG (x)));
3295 /* SUBREG of a hard register => just change the register number
3296 and/or mode. If the hard register is not valid in that mode,
3297 suppress this combination. If the hard register is the stack,
3298 frame, or argument pointer, leave this as a SUBREG. */
3300 if (GET_CODE (SUBREG_REG (x)) == REG
3301 && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER
3302 && REGNO (SUBREG_REG (x)) != FRAME_POINTER_REGNUM
3303 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3304 && REGNO (SUBREG_REG (x)) != HARD_FRAME_POINTER_REGNUM
3306 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3307 && REGNO (SUBREG_REG (x)) != ARG_POINTER_REGNUM
3309 && REGNO (SUBREG_REG (x)) != STACK_POINTER_REGNUM)
3311 if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x)) + SUBREG_WORD (x),
3313 return gen_rtx (REG, mode,
3314 REGNO (SUBREG_REG (x)) + SUBREG_WORD (x));
3316 return gen_rtx (CLOBBER, mode, const0_rtx);
3319 /* For a constant, try to pick up the part we want. Handle a full
3320 word and low-order part. Only do this if we are narrowing
3321 the constant; if it is being widened, we have no idea what
3322 the extra bits will have been set to. */
3324 if (CONSTANT_P (SUBREG_REG (x)) && op0_mode != VOIDmode
3325 && GET_MODE_SIZE (mode) == UNITS_PER_WORD
3326 && GET_MODE_SIZE (op0_mode) < UNITS_PER_WORD
3327 && GET_MODE_CLASS (mode) == MODE_INT)
3329 temp = operand_subword (SUBREG_REG (x), SUBREG_WORD (x),
3335 /* If we want a subreg of a constant, at offset 0,
3336 take the low bits. On a little-endian machine, that's
3337 always valid. On a big-endian machine, it's valid
3338 only if the constant's mode fits in one word. */
3339 if (CONSTANT_P (SUBREG_REG (x)) && subreg_lowpart_p (x)
3340 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (op0_mode)
3341 && (! WORDS_BIG_ENDIAN
3342 || GET_MODE_BITSIZE (op0_mode) <= BITS_PER_WORD))
3343 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3345 /* A paradoxical SUBREG of a VOIDmode constant is the same constant,
3346 since we are saying that the high bits don't matter. */
3347 if (CONSTANT_P (SUBREG_REG (x)) && GET_MODE (SUBREG_REG (x)) == VOIDmode
3348 && GET_MODE_SIZE (mode) > GET_MODE_SIZE (op0_mode))
3349 return SUBREG_REG (x);
3351 /* Note that we cannot do any narrowing for non-constants since
3352 we might have been counting on using the fact that some bits were
3353 zero. We now do this in the SET. */
3358 /* (not (plus X -1)) can become (neg X). */
3359 if (GET_CODE (XEXP (x, 0)) == PLUS
3360 && XEXP (XEXP (x, 0), 1) == constm1_rtx)
3361 return gen_rtx_combine (NEG, mode, XEXP (XEXP (x, 0), 0));
3363 /* Similarly, (not (neg X)) is (plus X -1). */
3364 if (GET_CODE (XEXP (x, 0)) == NEG)
3365 return gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0),
3368 /* (not (xor X C)) for C constant is (xor X D) with D = ~ C. */
3369 if (GET_CODE (XEXP (x, 0)) == XOR
3370 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3371 && (temp = simplify_unary_operation (NOT, mode,
3372 XEXP (XEXP (x, 0), 1),
3374 return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp);
3376 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3377 other than 1, but that is not valid. We could do a similar
3378 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3379 but this doesn't seem common enough to bother with. */
3380 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3381 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3382 return gen_rtx (ROTATE, mode, gen_unary (NOT, mode, mode, const1_rtx),
3383 XEXP (XEXP (x, 0), 1));
3385 if (GET_CODE (XEXP (x, 0)) == SUBREG
3386 && subreg_lowpart_p (XEXP (x, 0))
3387 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3388 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3389 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3390 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3392 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3394 x = gen_rtx (ROTATE, inner_mode,
3395 gen_unary (NOT, inner_mode, inner_mode, const1_rtx),
3396 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3397 return gen_lowpart_for_combine (mode, x);
3400 #if STORE_FLAG_VALUE == -1
3401 /* (not (comparison foo bar)) can be done by reversing the comparison
3403 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3404 && reversible_comparison_p (XEXP (x, 0)))
3405 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
3406 mode, XEXP (XEXP (x, 0), 0),
3407 XEXP (XEXP (x, 0), 1));
3409 /* (ashiftrt foo C) where C is the number of bits in FOO minus 1
3410 is (lt foo (const_int 0)), so we can perform the above
3413 if (XEXP (x, 1) == const1_rtx
3414 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3415 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3416 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3417 return gen_rtx_combine (GE, mode, XEXP (XEXP (x, 0), 0), const0_rtx);
3420 /* Apply De Morgan's laws to reduce number of patterns for machines
3421 with negating logical insns (and-not, nand, etc.). If result has
3422 only one NOT, put it first, since that is how the patterns are
3425 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3427 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3429 if (GET_CODE (in1) == NOT)
3430 in1 = XEXP (in1, 0);
3432 in1 = gen_rtx_combine (NOT, GET_MODE (in1), in1);
3434 if (GET_CODE (in2) == NOT)
3435 in2 = XEXP (in2, 0);
3436 else if (GET_CODE (in2) == CONST_INT
3437 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3438 in2 = GEN_INT (GET_MODE_MASK (mode) & ~ INTVAL (in2));
3440 in2 = gen_rtx_combine (NOT, GET_MODE (in2), in2);
3442 if (GET_CODE (in2) == NOT)
3445 in2 = in1; in1 = tem;
3448 return gen_rtx_combine (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3454 /* (neg (plus X 1)) can become (not X). */
3455 if (GET_CODE (XEXP (x, 0)) == PLUS
3456 && XEXP (XEXP (x, 0), 1) == const1_rtx)
3457 return gen_rtx_combine (NOT, mode, XEXP (XEXP (x, 0), 0));
3459 /* Similarly, (neg (not X)) is (plus X 1). */
3460 if (GET_CODE (XEXP (x, 0)) == NOT)
3461 return plus_constant (XEXP (XEXP (x, 0), 0), 1);
3463 /* (neg (minus X Y)) can become (minus Y X). */
3464 if (GET_CODE (XEXP (x, 0)) == MINUS
3465 && (! FLOAT_MODE_P (mode)
3466 /* x-y != -(y-x) with IEEE floating point. */
3467 || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3469 return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
3470 XEXP (XEXP (x, 0), 0));
3472 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3473 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
3474 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
3475 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3477 /* NEG commutes with ASHIFT since it is multiplication. Only do this
3478 if we can then eliminate the NEG (e.g.,
3479 if the operand is a constant). */
3481 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
3483 temp = simplify_unary_operation (NEG, mode,
3484 XEXP (XEXP (x, 0), 0), mode);
3487 SUBST (XEXP (XEXP (x, 0), 0), temp);
3492 temp = expand_compound_operation (XEXP (x, 0));
3494 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3495 replaced by (lshiftrt X C). This will convert
3496 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3498 if (GET_CODE (temp) == ASHIFTRT
3499 && GET_CODE (XEXP (temp, 1)) == CONST_INT
3500 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
3501 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
3502 INTVAL (XEXP (temp, 1)));
3504 /* If X has only a single bit that might be nonzero, say, bit I, convert
3505 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3506 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
3507 (sign_extract X 1 Y). But only do this if TEMP isn't a register
3508 or a SUBREG of one since we'd be making the expression more
3509 complex if it was just a register. */
3511 if (GET_CODE (temp) != REG
3512 && ! (GET_CODE (temp) == SUBREG
3513 && GET_CODE (SUBREG_REG (temp)) == REG)
3514 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
3516 rtx temp1 = simplify_shift_const
3517 (NULL_RTX, ASHIFTRT, mode,
3518 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
3519 GET_MODE_BITSIZE (mode) - 1 - i),
3520 GET_MODE_BITSIZE (mode) - 1 - i);
3522 /* If all we did was surround TEMP with the two shifts, we
3523 haven't improved anything, so don't use it. Otherwise,
3524 we are better off with TEMP1. */
3525 if (GET_CODE (temp1) != ASHIFTRT
3526 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
3527 || XEXP (XEXP (temp1, 0), 0) != temp)
3533 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3535 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
3536 GET_MODE_MASK (mode), NULL_RTX, 0));
3539 case FLOAT_TRUNCATE:
3540 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
3541 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
3542 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
3543 return XEXP (XEXP (x, 0), 0);
3545 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
3546 (OP:SF foo:SF) if OP is NEG or ABS. */
3547 if ((GET_CODE (XEXP (x, 0)) == ABS
3548 || GET_CODE (XEXP (x, 0)) == NEG)
3549 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
3550 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
3551 return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
3552 XEXP (XEXP (XEXP (x, 0), 0), 0));
3554 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
3555 is (float_truncate:SF x). */
3556 if (GET_CODE (XEXP (x, 0)) == SUBREG
3557 && subreg_lowpart_p (XEXP (x, 0))
3558 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
3559 return SUBREG_REG (XEXP (x, 0));
3564 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
3565 using cc0, in which case we want to leave it as a COMPARE
3566 so we can distinguish it from a register-register-copy. */
3567 if (XEXP (x, 1) == const0_rtx)
3570 /* In IEEE floating point, x-0 is not the same as x. */
3571 if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3572 || ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0)))
3574 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
3580 /* (const (const X)) can become (const X). Do it this way rather than
3581 returning the inner CONST since CONST can be shared with a
3583 if (GET_CODE (XEXP (x, 0)) == CONST)
3584 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
3589 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
3590 can add in an offset. find_split_point will split this address up
3591 again if it doesn't match. */
3592 if (GET_CODE (XEXP (x, 0)) == HIGH
3593 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
3599 /* If we have (plus (plus (A const) B)), associate it so that CONST is
3600 outermost. That's because that's the way indexed addresses are
3601 supposed to appear. This code used to check many more cases, but
3602 they are now checked elsewhere. */
3603 if (GET_CODE (XEXP (x, 0)) == PLUS
3604 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
3605 return gen_binary (PLUS, mode,
3606 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
3608 XEXP (XEXP (x, 0), 1));
3610 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
3611 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
3612 bit-field and can be replaced by either a sign_extend or a
3613 sign_extract. The `and' may be a zero_extend. */
3614 if (GET_CODE (XEXP (x, 0)) == XOR
3615 && GET_CODE (XEXP (x, 1)) == CONST_INT
3616 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3617 && INTVAL (XEXP (x, 1)) == - INTVAL (XEXP (XEXP (x, 0), 1))
3618 && (i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
3619 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3620 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
3621 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3622 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
3623 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
3624 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
3625 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
3627 return simplify_shift_const
3628 (NULL_RTX, ASHIFTRT, mode,
3629 simplify_shift_const (NULL_RTX, ASHIFT, mode,
3630 XEXP (XEXP (XEXP (x, 0), 0), 0),
3631 GET_MODE_BITSIZE (mode) - (i + 1)),
3632 GET_MODE_BITSIZE (mode) - (i + 1));
3634 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
3635 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
3636 is 1. This produces better code than the alternative immediately
3638 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3639 && reversible_comparison_p (XEXP (x, 0))
3640 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
3641 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx)))
3643 gen_unary (NEG, mode, mode,
3644 gen_binary (reverse_condition (GET_CODE (XEXP (x, 0))),
3645 mode, XEXP (XEXP (x, 0), 0),
3646 XEXP (XEXP (x, 0), 1)));
3648 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
3649 can become (ashiftrt (ashift (xor x 1) C) C) where C is
3650 the bitsize of the mode - 1. This allows simplification of
3651 "a = (b & 8) == 0;" */
3652 if (XEXP (x, 1) == constm1_rtx
3653 && GET_CODE (XEXP (x, 0)) != REG
3654 && ! (GET_CODE (XEXP (x,0)) == SUBREG
3655 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
3656 && nonzero_bits (XEXP (x, 0), mode) == 1)
3657 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
3658 simplify_shift_const (NULL_RTX, ASHIFT, mode,
3659 gen_rtx_combine (XOR, mode,
3660 XEXP (x, 0), const1_rtx),
3661 GET_MODE_BITSIZE (mode) - 1),
3662 GET_MODE_BITSIZE (mode) - 1);
3664 /* If we are adding two things that have no bits in common, convert
3665 the addition into an IOR. This will often be further simplified,
3666 for example in cases like ((a & 1) + (a & 2)), which can
3669 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3670 && (nonzero_bits (XEXP (x, 0), mode)
3671 & nonzero_bits (XEXP (x, 1), mode)) == 0)
3672 return gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
3676 #if STORE_FLAG_VALUE == 1
3677 /* (minus 1 (comparison foo bar)) can be done by reversing the comparison
3679 if (XEXP (x, 0) == const1_rtx
3680 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
3681 && reversible_comparison_p (XEXP (x, 1)))
3682 return gen_binary (reverse_condition (GET_CODE (XEXP (x, 1))),
3683 mode, XEXP (XEXP (x, 1), 0),
3684 XEXP (XEXP (x, 1), 1));
3687 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
3688 (and <foo> (const_int pow2-1)) */
3689 if (GET_CODE (XEXP (x, 1)) == AND
3690 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
3691 && exact_log2 (- INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
3692 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
3693 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
3694 - INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
3696 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
3698 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
3699 return gen_binary (MINUS, mode,
3700 gen_binary (MINUS, mode, XEXP (x, 0),
3701 XEXP (XEXP (x, 1), 0)),
3702 XEXP (XEXP (x, 1), 1));
3706 /* If we have (mult (plus A B) C), apply the distributive law and then
3707 the inverse distributive law to see if things simplify. This
3708 occurs mostly in addresses, often when unrolling loops. */
3710 if (GET_CODE (XEXP (x, 0)) == PLUS)
3712 x = apply_distributive_law
3713 (gen_binary (PLUS, mode,
3714 gen_binary (MULT, mode,
3715 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
3716 gen_binary (MULT, mode,
3717 XEXP (XEXP (x, 0), 1), XEXP (x, 1))));
3719 if (GET_CODE (x) != MULT)
3725 /* If this is a divide by a power of two, treat it as a shift if
3726 its first operand is a shift. */
3727 if (GET_CODE (XEXP (x, 1)) == CONST_INT
3728 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
3729 && (GET_CODE (XEXP (x, 0)) == ASHIFT
3730 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
3731 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
3732 || GET_CODE (XEXP (x, 0)) == ROTATE
3733 || GET_CODE (XEXP (x, 0)) == ROTATERT))
3734 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
3738 case GT: case GTU: case GE: case GEU:
3739 case LT: case LTU: case LE: case LEU:
3740 /* If the first operand is a condition code, we can't do anything
3742 if (GET_CODE (XEXP (x, 0)) == COMPARE
3743 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
3745 && XEXP (x, 0) != cc0_rtx
3749 rtx op0 = XEXP (x, 0);
3750 rtx op1 = XEXP (x, 1);
3751 enum rtx_code new_code;
3753 if (GET_CODE (op0) == COMPARE)
3754 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
3756 /* Simplify our comparison, if possible. */
3757 new_code = simplify_comparison (code, &op0, &op1);
3759 #if STORE_FLAG_VALUE == 1
3760 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
3761 if only the low-order bit is possibly nonzero in X (such as when
3762 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
3763 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
3764 known to be either 0 or -1, NE becomes a NEG and EQ becomes
3767 Remove any ZERO_EXTRACT we made when thinking this was a
3768 comparison. It may now be simpler to use, e.g., an AND. If a
3769 ZERO_EXTRACT is indeed appropriate, it will be placed back by
3770 the call to make_compound_operation in the SET case. */
3772 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3773 && op1 == const0_rtx
3774 && nonzero_bits (op0, mode) == 1)
3775 return gen_lowpart_for_combine (mode,
3776 expand_compound_operation (op0));
3778 else if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3779 && op1 == const0_rtx
3780 && (num_sign_bit_copies (op0, mode)
3781 == GET_MODE_BITSIZE (mode)))
3783 op0 = expand_compound_operation (op0);
3784 return gen_unary (NEG, mode, mode,
3785 gen_lowpart_for_combine (mode, op0));
3788 else if (new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3789 && op1 == const0_rtx
3790 && nonzero_bits (op0, mode) == 1)
3792 op0 = expand_compound_operation (op0);
3793 return gen_binary (XOR, mode,
3794 gen_lowpart_for_combine (mode, op0),
3798 else if (new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3799 && op1 == const0_rtx
3800 && (num_sign_bit_copies (op0, mode)
3801 == GET_MODE_BITSIZE (mode)))
3803 op0 = expand_compound_operation (op0);
3804 return plus_constant (gen_lowpart_for_combine (mode, op0), 1);
3808 #if STORE_FLAG_VALUE == -1
3809 /* If STORE_FLAG_VALUE is -1, we have cases similar to
3811 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3812 && op1 == const0_rtx
3813 && (num_sign_bit_copies (op0, mode)
3814 == GET_MODE_BITSIZE (mode)))
3815 return gen_lowpart_for_combine (mode,
3816 expand_compound_operation (op0));
3818 else if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3819 && op1 == const0_rtx
3820 && nonzero_bits (op0, mode) == 1)
3822 op0 = expand_compound_operation (op0);
3823 return gen_unary (NEG, mode, mode,
3824 gen_lowpart_for_combine (mode, op0));
3827 else if (new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3828 && op1 == const0_rtx
3829 && (num_sign_bit_copies (op0, mode)
3830 == GET_MODE_BITSIZE (mode)))
3832 op0 = expand_compound_operation (op0);
3833 return gen_unary (NOT, mode, mode,
3834 gen_lowpart_for_combine (mode, op0));
3837 /* If X is 0/1, (eq X 0) is X-1. */
3838 else if (new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3839 && op1 == const0_rtx
3840 && nonzero_bits (op0, mode) == 1)
3842 op0 = expand_compound_operation (op0);
3843 return plus_constant (gen_lowpart_for_combine (mode, op0), -1);
3847 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
3848 one bit that might be nonzero, we can convert (ne x 0) to
3849 (ashift x c) where C puts the bit in the sign bit. Remove any
3850 AND with STORE_FLAG_VALUE when we are done, since we are only
3851 going to test the sign bit. */
3852 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3853 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3854 && (STORE_FLAG_VALUE
3855 == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
3856 && op1 == const0_rtx
3857 && mode == GET_MODE (op0)
3858 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
3860 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3861 expand_compound_operation (op0),
3862 GET_MODE_BITSIZE (mode) - 1 - i);
3863 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
3869 /* If the code changed, return a whole new comparison. */
3870 if (new_code != code)
3871 return gen_rtx_combine (new_code, mode, op0, op1);
3873 /* Otherwise, keep this operation, but maybe change its operands.
3874 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
3875 SUBST (XEXP (x, 0), op0);
3876 SUBST (XEXP (x, 1), op1);
3881 return simplify_if_then_else (x);
3887 /* If we are processing SET_DEST, we are done. */
3891 return expand_compound_operation (x);
3894 return simplify_set (x);
3899 return simplify_logical (x, last);
3902 /* (abs (neg <foo>)) -> (abs <foo>) */
3903 if (GET_CODE (XEXP (x, 0)) == NEG)
3904 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
3906 /* If operand is something known to be positive, ignore the ABS. */
3907 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
3908 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
3909 <= HOST_BITS_PER_WIDE_INT)
3910 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
3911 & ((HOST_WIDE_INT) 1
3912 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
3917 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
3918 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
3919 return gen_rtx_combine (NEG, mode, XEXP (x, 0));
3924 /* (ffs (*_extend <X>)) = (ffs <X>) */
3925 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
3926 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
3927 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
3931 /* (float (sign_extend <X>)) = (float <X>). */
3932 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
3933 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
3941 /* If this is a shift by a constant amount, simplify it. */
3942 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3943 return simplify_shift_const (x, code, mode, XEXP (x, 0),
3944 INTVAL (XEXP (x, 1)));
3946 #ifdef SHIFT_COUNT_TRUNCATED
3947 else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG)
3949 force_to_mode (XEXP (x, 1), GET_MODE (x),
3951 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
3962 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
3965 simplify_if_then_else (x)
3968 enum machine_mode mode = GET_MODE (x);
3969 rtx cond = XEXP (x, 0);
3970 rtx true = XEXP (x, 1);
3971 rtx false = XEXP (x, 2);
3972 enum rtx_code true_code = GET_CODE (cond);
3973 int comparison_p = GET_RTX_CLASS (true_code) == '<';
3977 /* Simplify storing of the truth value. */
3978 if (comparison_p && true == const_true_rtx && false == const0_rtx)
3979 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
3981 /* Also when the truth value has to be reversed. */
3982 if (comparison_p && reversible_comparison_p (cond)
3983 && true == const0_rtx && false == const_true_rtx)
3984 return gen_binary (reverse_condition (true_code),
3985 mode, XEXP (cond, 0), XEXP (cond, 1));
3987 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
3988 in it is being compared against certain values. Get the true and false
3989 comparisons and see if that says anything about the value of each arm. */
3991 if (comparison_p && reversible_comparison_p (cond)
3992 && GET_CODE (XEXP (cond, 0)) == REG)
3995 rtx from = XEXP (cond, 0);
3996 enum rtx_code false_code = reverse_condition (true_code);
3997 rtx true_val = XEXP (cond, 1);
3998 rtx false_val = true_val;
4001 /* If FALSE_CODE is EQ, swap the codes and arms. */
4003 if (false_code == EQ)
4005 swapped = 1, true_code = EQ, false_code = NE;
4006 temp = true, true = false, false = temp;
4009 /* If we are comparing against zero and the expression being tested has
4010 only a single bit that might be nonzero, that is its value when it is
4011 not equal to zero. Similarly if it is known to be -1 or 0. */
4013 if (true_code == EQ && true_val == const0_rtx
4014 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4015 false_code = EQ, false_val = GEN_INT (nzb);
4016 else if (true_code == EQ && true_val == const0_rtx
4017 && (num_sign_bit_copies (from, GET_MODE (from))
4018 == GET_MODE_BITSIZE (GET_MODE (from))))
4019 false_code = EQ, false_val = constm1_rtx;
4021 /* Now simplify an arm if we know the value of the register in the
4022 branch and it is used in the arm. Be careful due to the potential
4023 of locally-shared RTL. */
4025 if (reg_mentioned_p (from, true))
4026 true = subst (known_cond (copy_rtx (true), true_code, from, true_val),
4027 pc_rtx, pc_rtx, 0, 0);
4028 if (reg_mentioned_p (from, false))
4029 false = subst (known_cond (copy_rtx (false), false_code,
4031 pc_rtx, pc_rtx, 0, 0);
4033 SUBST (XEXP (x, 1), swapped ? false : true);
4034 SUBST (XEXP (x, 2), swapped ? true : false);
4036 true = XEXP (x, 1), false = XEXP (x, 2), true_code = GET_CODE (cond);
4039 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4040 reversed, do so to avoid needing two sets of patterns for
4041 subtract-and-branch insns. Similarly if we have a constant in the true
4042 arm, the false arm is the same as the first operand of the comparison, or
4043 the false arm is more complicated than the true arm. */
4045 if (comparison_p && reversible_comparison_p (cond)
4047 || (CONSTANT_P (true)
4048 && GET_CODE (false) != CONST_INT && false != pc_rtx)
4049 || true == const0_rtx
4050 || (GET_RTX_CLASS (GET_CODE (true)) == 'o'
4051 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4052 || (GET_CODE (true) == SUBREG
4053 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true))) == 'o'
4054 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4055 || reg_mentioned_p (true, false)
4056 || rtx_equal_p (false, XEXP (cond, 0))))
4058 true_code = reverse_condition (true_code);
4060 gen_binary (true_code, GET_MODE (cond), XEXP (cond, 0),
4063 SUBST (XEXP (x, 1), false);
4064 SUBST (XEXP (x, 2), true);
4066 temp = true, true = false, false = temp, cond = XEXP (x, 0);
4068 /* It is possible that the conditional has been simplified out. */
4069 true_code = GET_CODE (cond);
4070 comparison_p = GET_RTX_CLASS (true_code) == '<';
4073 /* If the two arms are identical, we don't need the comparison. */
4075 if (rtx_equal_p (true, false) && ! side_effects_p (cond))
4078 /* Convert a == b ? b : a to "a". */
4079 if (true_code == EQ && ! side_effects_p (cond)
4080 && rtx_equal_p (XEXP (cond, 0), false)
4081 && rtx_equal_p (XEXP (cond, 1), true))
4083 else if (true_code == NE && ! side_effects_p (cond)
4084 && rtx_equal_p (XEXP (cond, 0), true)
4085 && rtx_equal_p (XEXP (cond, 1), false))
4088 /* Look for cases where we have (abs x) or (neg (abs X)). */
4090 if (GET_MODE_CLASS (mode) == MODE_INT
4091 && GET_CODE (false) == NEG
4092 && rtx_equal_p (true, XEXP (false, 0))
4094 && rtx_equal_p (true, XEXP (cond, 0))
4095 && ! side_effects_p (true))
4100 return gen_unary (ABS, mode, mode, true);
4103 return gen_unary (NEG, mode, mode, gen_unary (ABS, mode, mode, true));
4106 /* Look for MIN or MAX. */
4108 if ((! FLOAT_MODE_P (mode) || flag_fast_math)
4110 && rtx_equal_p (XEXP (cond, 0), true)
4111 && rtx_equal_p (XEXP (cond, 1), false)
4112 && ! side_effects_p (cond))
4117 return gen_binary (SMAX, mode, true, false);
4120 return gen_binary (SMIN, mode, true, false);
4123 return gen_binary (UMAX, mode, true, false);
4126 return gen_binary (UMIN, mode, true, false);
4129 #if STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1
4131 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4132 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4133 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4134 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4135 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4136 neither of the above, but it isn't worth checking for. */
4138 if (comparison_p && mode != VOIDmode && ! side_effects_p (x))
4140 rtx t = make_compound_operation (true, SET);
4141 rtx f = make_compound_operation (false, SET);
4142 rtx cond_op0 = XEXP (cond, 0);
4143 rtx cond_op1 = XEXP (cond, 1);
4144 enum rtx_code op, extend_op = NIL;
4145 enum machine_mode m = mode;
4148 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4149 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4150 || GET_CODE (t) == ASHIFT
4151 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4152 && rtx_equal_p (XEXP (t, 0), f))
4153 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4155 /* If an identity-zero op is commutative, check whether there
4156 would be a match if we swapped the operands. */
4157 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4158 || GET_CODE (t) == XOR)
4159 && rtx_equal_p (XEXP (t, 1), f))
4160 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4161 else if (GET_CODE (t) == SIGN_EXTEND
4162 && (GET_CODE (XEXP (t, 0)) == PLUS
4163 || GET_CODE (XEXP (t, 0)) == MINUS
4164 || GET_CODE (XEXP (t, 0)) == IOR
4165 || GET_CODE (XEXP (t, 0)) == XOR
4166 || GET_CODE (XEXP (t, 0)) == ASHIFT
4167 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4168 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4169 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4170 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4171 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4172 && (num_sign_bit_copies (f, GET_MODE (f))
4173 > (GET_MODE_BITSIZE (mode)
4174 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4176 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4177 extend_op = SIGN_EXTEND;
4178 m = GET_MODE (XEXP (t, 0));
4180 else if (GET_CODE (t) == SIGN_EXTEND
4181 && (GET_CODE (XEXP (t, 0)) == PLUS
4182 || GET_CODE (XEXP (t, 0)) == IOR
4183 || GET_CODE (XEXP (t, 0)) == XOR)
4184 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4185 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4186 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4187 && (num_sign_bit_copies (f, GET_MODE (f))
4188 > (GET_MODE_BITSIZE (mode)
4189 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4191 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4192 extend_op = SIGN_EXTEND;
4193 m = GET_MODE (XEXP (t, 0));
4195 else if (GET_CODE (t) == ZERO_EXTEND
4196 && (GET_CODE (XEXP (t, 0)) == PLUS
4197 || GET_CODE (XEXP (t, 0)) == MINUS
4198 || GET_CODE (XEXP (t, 0)) == IOR
4199 || GET_CODE (XEXP (t, 0)) == XOR
4200 || GET_CODE (XEXP (t, 0)) == ASHIFT
4201 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4202 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4203 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4204 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4205 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4206 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4207 && ((nonzero_bits (f, GET_MODE (f))
4208 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
4211 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4212 extend_op = ZERO_EXTEND;
4213 m = GET_MODE (XEXP (t, 0));
4215 else if (GET_CODE (t) == ZERO_EXTEND
4216 && (GET_CODE (XEXP (t, 0)) == PLUS
4217 || GET_CODE (XEXP (t, 0)) == IOR
4218 || GET_CODE (XEXP (t, 0)) == XOR)
4219 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4220 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4221 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4222 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4223 && ((nonzero_bits (f, GET_MODE (f))
4224 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
4227 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4228 extend_op = ZERO_EXTEND;
4229 m = GET_MODE (XEXP (t, 0));
4234 temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
4235 pc_rtx, pc_rtx, 0, 0);
4236 temp = gen_binary (MULT, m, temp,
4237 gen_binary (MULT, m, c1, const_true_rtx));
4238 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
4239 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
4241 if (extend_op != NIL)
4242 temp = gen_unary (extend_op, mode, m, temp);
4249 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4250 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4251 negation of a single bit, we can convert this operation to a shift. We
4252 can actually do this more generally, but it doesn't seem worth it. */
4254 if (true_code == NE && XEXP (cond, 1) == const0_rtx
4255 && false == const0_rtx && GET_CODE (true) == CONST_INT
4256 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
4257 && (i = exact_log2 (INTVAL (true))) >= 0)
4258 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
4259 == GET_MODE_BITSIZE (mode))
4260 && (i = exact_log2 (- INTVAL (true))) >= 0)))
4262 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4263 gen_lowpart_for_combine (mode, XEXP (cond, 0)), i);
4268 /* Simplify X, a SET expression. Return the new expression. */
4274 rtx src = SET_SRC (x);
4275 rtx dest = SET_DEST (x);
4276 enum machine_mode mode
4277 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
4281 /* (set (pc) (return)) gets written as (return). */
4282 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
4285 /* Now that we know for sure which bits of SRC we are using, see if we can
4286 simplify the expression for the object knowing that we only need the
4289 if (GET_MODE_CLASS (mode) == MODE_INT)
4290 src = force_to_mode (src, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
4292 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4293 the comparison result and try to simplify it unless we already have used
4294 undobuf.other_insn. */
4295 if ((GET_CODE (src) == COMPARE
4300 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
4301 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
4302 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
4303 && rtx_equal_p (XEXP (*cc_use, 0), dest))
4305 enum rtx_code old_code = GET_CODE (*cc_use);
4306 enum rtx_code new_code;
4308 int other_changed = 0;
4309 enum machine_mode compare_mode = GET_MODE (dest);
4311 if (GET_CODE (src) == COMPARE)
4312 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
4314 op0 = src, op1 = const0_rtx;
4316 /* Simplify our comparison, if possible. */
4317 new_code = simplify_comparison (old_code, &op0, &op1);
4319 #ifdef EXTRA_CC_MODES
4320 /* If this machine has CC modes other than CCmode, check to see if we
4321 need to use a different CC mode here. */
4322 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
4323 #endif /* EXTRA_CC_MODES */
4325 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
4326 /* If the mode changed, we have to change SET_DEST, the mode in the
4327 compare, and the mode in the place SET_DEST is used. If SET_DEST is
4328 a hard register, just build new versions with the proper mode. If it
4329 is a pseudo, we lose unless it is only time we set the pseudo, in
4330 which case we can safely change its mode. */
4331 if (compare_mode != GET_MODE (dest))
4333 int regno = REGNO (dest);
4334 rtx new_dest = gen_rtx (REG, compare_mode, regno);
4336 if (regno < FIRST_PSEUDO_REGISTER
4337 || (reg_n_sets[regno] == 1 && ! REG_USERVAR_P (dest)))
4339 if (regno >= FIRST_PSEUDO_REGISTER)
4340 SUBST (regno_reg_rtx[regno], new_dest);
4342 SUBST (SET_DEST (x), new_dest);
4343 SUBST (XEXP (*cc_use, 0), new_dest);
4351 /* If the code changed, we have to build a new comparison in
4352 undobuf.other_insn. */
4353 if (new_code != old_code)
4355 unsigned HOST_WIDE_INT mask;
4357 SUBST (*cc_use, gen_rtx_combine (new_code, GET_MODE (*cc_use),
4360 /* If the only change we made was to change an EQ into an NE or
4361 vice versa, OP0 has only one bit that might be nonzero, and OP1
4362 is zero, check if changing the user of the condition code will
4363 produce a valid insn. If it won't, we can keep the original code
4364 in that insn by surrounding our operation with an XOR. */
4366 if (((old_code == NE && new_code == EQ)
4367 || (old_code == EQ && new_code == NE))
4368 && ! other_changed && op1 == const0_rtx
4369 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
4370 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
4372 rtx pat = PATTERN (other_insn), note = 0;
4375 if ((recog_for_combine (&pat, other_insn, ¬e, &scratches) < 0
4376 && ! check_asm_operands (pat)))
4378 PUT_CODE (*cc_use, old_code);
4381 op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
4389 undobuf.other_insn = other_insn;
4392 /* If we are now comparing against zero, change our source if
4393 needed. If we do not use cc0, we always have a COMPARE. */
4394 if (op1 == const0_rtx && dest == cc0_rtx)
4396 SUBST (SET_SRC (x), op0);
4402 /* Otherwise, if we didn't previously have a COMPARE in the
4403 correct mode, we need one. */
4404 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
4407 gen_rtx_combine (COMPARE, compare_mode, op0, op1));
4412 /* Otherwise, update the COMPARE if needed. */
4413 SUBST (XEXP (src, 0), op0);
4414 SUBST (XEXP (src, 1), op1);
4419 /* Get SET_SRC in a form where we have placed back any
4420 compound expressions. Then do the checks below. */
4421 src = make_compound_operation (src, SET);
4422 SUBST (SET_SRC (x), src);
4425 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
4426 and X being a REG or (subreg (reg)), we may be able to convert this to
4427 (set (subreg:m2 x) (op)).
4429 We can always do this if M1 is narrower than M2 because that means that
4430 we only care about the low bits of the result.
4432 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
4433 perform a narrower operation that requested since the high-order bits will
4434 be undefined. On machine where it is defined, this transformation is safe
4435 as long as M1 and M2 have the same number of words. */
4437 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
4438 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o'
4439 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
4441 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
4442 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
4443 #ifndef WORD_REGISTER_OPERATIONS
4444 && (GET_MODE_SIZE (GET_MODE (src))
4445 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
4447 #ifdef CLASS_CANNOT_CHANGE_SIZE
4448 && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER
4449 && (TEST_HARD_REG_BIT
4450 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE],
4452 && (GET_MODE_SIZE (GET_MODE (src))
4453 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))))
4455 && (GET_CODE (dest) == REG
4456 || (GET_CODE (dest) == SUBREG
4457 && GET_CODE (SUBREG_REG (dest)) == REG)))
4459 SUBST (SET_DEST (x),
4460 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)),
4462 SUBST (SET_SRC (x), SUBREG_REG (src));
4464 src = SET_SRC (x), dest = SET_DEST (x);
4467 #ifdef LOAD_EXTEND_OP
4468 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
4469 would require a paradoxical subreg. Replace the subreg with a
4470 zero_extend to avoid the reload that would otherwise be required. */
4472 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
4473 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
4474 && SUBREG_WORD (src) == 0
4475 && (GET_MODE_SIZE (GET_MODE (src))
4476 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
4477 && GET_CODE (SUBREG_REG (src)) == MEM)
4480 gen_rtx_combine (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
4481 GET_MODE (src), XEXP (src, 0)));
4487 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
4488 are comparing an item known to be 0 or -1 against 0, use a logical
4489 operation instead. Check for one of the arms being an IOR of the other
4490 arm with some value. We compute three terms to be IOR'ed together. In
4491 practice, at most two will be nonzero. Then we do the IOR's. */
4493 if (GET_CODE (dest) != PC
4494 && GET_CODE (src) == IF_THEN_ELSE
4495 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
4496 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
4497 && XEXP (XEXP (src, 0), 1) == const0_rtx
4498 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
4499 #ifdef HAVE_conditional_move
4500 && ! can_conditionally_move_p (GET_MODE (src))
4502 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
4503 GET_MODE (XEXP (XEXP (src, 0), 0)))
4504 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
4505 && ! side_effects_p (src))
4507 rtx true = (GET_CODE (XEXP (src, 0)) == NE
4508 ? XEXP (src, 1) : XEXP (src, 2));
4509 rtx false = (GET_CODE (XEXP (src, 0)) == NE
4510 ? XEXP (src, 2) : XEXP (src, 1));
4511 rtx term1 = const0_rtx, term2, term3;
4513 if (GET_CODE (true) == IOR && rtx_equal_p (XEXP (true, 0), false))
4514 term1 = false, true = XEXP (true, 1), false = const0_rtx;
4515 else if (GET_CODE (true) == IOR
4516 && rtx_equal_p (XEXP (true, 1), false))
4517 term1 = false, true = XEXP (true, 0), false = const0_rtx;
4518 else if (GET_CODE (false) == IOR
4519 && rtx_equal_p (XEXP (false, 0), true))
4520 term1 = true, false = XEXP (false, 1), true = const0_rtx;
4521 else if (GET_CODE (false) == IOR
4522 && rtx_equal_p (XEXP (false, 1), true))
4523 term1 = true, false = XEXP (false, 0), true = const0_rtx;
4525 term2 = gen_binary (AND, GET_MODE (src), XEXP (XEXP (src, 0), 0), true);
4526 term3 = gen_binary (AND, GET_MODE (src),
4527 gen_unary (NOT, GET_MODE (src), GET_MODE (src),
4528 XEXP (XEXP (src, 0), 0)),
4532 gen_binary (IOR, GET_MODE (src),
4533 gen_binary (IOR, GET_MODE (src), term1, term2),
4539 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
4540 whole thing fail. */
4541 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
4543 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
4546 /* Convert this into a field assignment operation, if possible. */
4547 return make_field_assignment (x);
4550 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
4551 result. LAST is nonzero if this is the last retry. */
4554 simplify_logical (x, last)
4558 enum machine_mode mode = GET_MODE (x);
4559 rtx op0 = XEXP (x, 0);
4560 rtx op1 = XEXP (x, 1);
4562 switch (GET_CODE (x))
4565 /* Convert (A ^ B) & A to A & (~ B) since the latter is often a single
4566 insn (and may simplify more). */
4567 if (GET_CODE (op0) == XOR
4568 && rtx_equal_p (XEXP (op0, 0), op1)
4569 && ! side_effects_p (op1))
4570 x = gen_binary (AND, mode,
4571 gen_unary (NOT, mode, mode, XEXP (op0, 1)), op1);
4573 if (GET_CODE (op0) == XOR
4574 && rtx_equal_p (XEXP (op0, 1), op1)
4575 && ! side_effects_p (op1))
4576 x = gen_binary (AND, mode,
4577 gen_unary (NOT, mode, mode, XEXP (op0, 0)), op1);
4579 /* Similarly for (~ (A ^ B)) & A. */
4580 if (GET_CODE (op0) == NOT
4581 && GET_CODE (XEXP (op0, 0)) == XOR
4582 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
4583 && ! side_effects_p (op1))
4584 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
4586 if (GET_CODE (op0) == NOT
4587 && GET_CODE (XEXP (op0, 0)) == XOR
4588 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
4589 && ! side_effects_p (op1))
4590 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
4592 if (GET_CODE (op1) == CONST_INT)
4594 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
4596 /* If we have (ior (and (X C1) C2)) and the next restart would be
4597 the last, simplify this by making C1 as small as possible
4600 && GET_CODE (x) == IOR && GET_CODE (op0) == AND
4601 && GET_CODE (XEXP (op0, 1)) == CONST_INT
4602 && GET_CODE (op1) == CONST_INT)
4603 return gen_binary (IOR, mode,
4604 gen_binary (AND, mode, XEXP (op0, 0),
4605 GEN_INT (INTVAL (XEXP (op0, 1))
4606 & ~ INTVAL (op1))), op1);
4608 if (GET_CODE (x) != AND)
4611 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
4612 || GET_RTX_CLASS (GET_CODE (x)) == '2')
4613 op0 = XEXP (x, 0), op1 = XEXP (x, 1);
4616 /* Convert (A | B) & A to A. */
4617 if (GET_CODE (op0) == IOR
4618 && (rtx_equal_p (XEXP (op0, 0), op1)
4619 || rtx_equal_p (XEXP (op0, 1), op1))
4620 && ! side_effects_p (XEXP (op0, 0))
4621 && ! side_effects_p (XEXP (op0, 1)))
4624 /* In the following group of tests (and those in case IOR below),
4625 we start with some combination of logical operations and apply
4626 the distributive law followed by the inverse distributive law.
4627 Most of the time, this results in no change. However, if some of
4628 the operands are the same or inverses of each other, simplifications
4631 For example, (and (ior A B) (not B)) can occur as the result of
4632 expanding a bit field assignment. When we apply the distributive
4633 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
4634 which then simplifies to (and (A (not B))).
4636 If we have (and (ior A B) C), apply the distributive law and then
4637 the inverse distributive law to see if things simplify. */
4639 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
4641 x = apply_distributive_law
4642 (gen_binary (GET_CODE (op0), mode,
4643 gen_binary (AND, mode, XEXP (op0, 0), op1),
4644 gen_binary (AND, mode, XEXP (op0, 1), op1)));
4645 if (GET_CODE (x) != AND)
4649 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
4650 return apply_distributive_law
4651 (gen_binary (GET_CODE (op1), mode,
4652 gen_binary (AND, mode, XEXP (op1, 0), op0),
4653 gen_binary (AND, mode, XEXP (op1, 1), op0)));
4655 /* Similarly, taking advantage of the fact that
4656 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
4658 if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
4659 return apply_distributive_law
4660 (gen_binary (XOR, mode,
4661 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
4662 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 1))));
4664 else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
4665 return apply_distributive_law
4666 (gen_binary (XOR, mode,
4667 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
4668 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 1))));
4672 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
4673 if (GET_CODE (op1) == CONST_INT
4674 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4675 && (nonzero_bits (op0, mode) & ~ INTVAL (op1)) == 0)
4678 /* Convert (A & B) | A to A. */
4679 if (GET_CODE (op0) == AND
4680 && (rtx_equal_p (XEXP (op0, 0), op1)
4681 || rtx_equal_p (XEXP (op0, 1), op1))
4682 && ! side_effects_p (XEXP (op0, 0))
4683 && ! side_effects_p (XEXP (op0, 1)))
4686 /* If we have (ior (and A B) C), apply the distributive law and then
4687 the inverse distributive law to see if things simplify. */
4689 if (GET_CODE (op0) == AND)
4691 x = apply_distributive_law
4692 (gen_binary (AND, mode,
4693 gen_binary (IOR, mode, XEXP (op0, 0), op1),
4694 gen_binary (IOR, mode, XEXP (op0, 1), op1)));
4696 if (GET_CODE (x) != IOR)
4700 if (GET_CODE (op1) == AND)
4702 x = apply_distributive_law
4703 (gen_binary (AND, mode,
4704 gen_binary (IOR, mode, XEXP (op1, 0), op0),
4705 gen_binary (IOR, mode, XEXP (op1, 1), op0)));
4707 if (GET_CODE (x) != IOR)
4711 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
4712 mode size to (rotate A CX). */
4714 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
4715 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
4716 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
4717 && GET_CODE (XEXP (op0, 1)) == CONST_INT
4718 && GET_CODE (XEXP (op1, 1)) == CONST_INT
4719 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
4720 == GET_MODE_BITSIZE (mode)))
4721 return gen_rtx (ROTATE, mode, XEXP (op0, 0),
4722 (GET_CODE (op0) == ASHIFT
4723 ? XEXP (op0, 1) : XEXP (op1, 1)));
4725 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
4726 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
4727 does not affect any of the bits in OP1, it can really be done
4728 as a PLUS and we can associate. We do this by seeing if OP1
4729 can be safely shifted left C bits. */
4730 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
4731 && GET_CODE (XEXP (op0, 0)) == PLUS
4732 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
4733 && GET_CODE (XEXP (op0, 1)) == CONST_INT
4734 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
4736 int count = INTVAL (XEXP (op0, 1));
4737 HOST_WIDE_INT mask = INTVAL (op1) << count;
4739 if (mask >> count == INTVAL (op1)
4740 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
4742 SUBST (XEXP (XEXP (op0, 0), 1),
4743 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
4750 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
4751 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
4754 int num_negated = 0;
4756 if (GET_CODE (op0) == NOT)
4757 num_negated++, op0 = XEXP (op0, 0);
4758 if (GET_CODE (op1) == NOT)
4759 num_negated++, op1 = XEXP (op1, 0);
4761 if (num_negated == 2)
4763 SUBST (XEXP (x, 0), op0);
4764 SUBST (XEXP (x, 1), op1);
4766 else if (num_negated == 1)
4767 return gen_unary (NOT, mode, mode, gen_binary (XOR, mode, op0, op1));
4770 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
4771 correspond to a machine insn or result in further simplifications
4772 if B is a constant. */
4774 if (GET_CODE (op0) == AND
4775 && rtx_equal_p (XEXP (op0, 1), op1)
4776 && ! side_effects_p (op1))
4777 return gen_binary (AND, mode,
4778 gen_unary (NOT, mode, mode, XEXP (op0, 0)),
4781 else if (GET_CODE (op0) == AND
4782 && rtx_equal_p (XEXP (op0, 0), op1)
4783 && ! side_effects_p (op1))
4784 return gen_binary (AND, mode,
4785 gen_unary (NOT, mode, mode, XEXP (op0, 1)),
4788 #if STORE_FLAG_VALUE == 1
4789 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
4791 if (op1 == const1_rtx
4792 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
4793 && reversible_comparison_p (op0))
4794 return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
4795 mode, XEXP (op0, 0), XEXP (op0, 1));
4797 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
4798 is (lt foo (const_int 0)), so we can perform the above
4801 if (op1 == const1_rtx
4802 && GET_CODE (op0) == LSHIFTRT
4803 && GET_CODE (XEXP (op0, 1)) == CONST_INT
4804 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
4805 return gen_rtx_combine (GE, mode, XEXP (op0, 0), const0_rtx);
4808 /* (xor (comparison foo bar) (const_int sign-bit))
4809 when STORE_FLAG_VALUE is the sign bit. */
4810 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4811 && (STORE_FLAG_VALUE
4812 == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4813 && op1 == const_true_rtx
4814 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
4815 && reversible_comparison_p (op0))
4816 return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
4817 mode, XEXP (op0, 0), XEXP (op0, 1));
4824 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
4825 operations" because they can be replaced with two more basic operations.
4826 ZERO_EXTEND is also considered "compound" because it can be replaced with
4827 an AND operation, which is simpler, though only one operation.
4829 The function expand_compound_operation is called with an rtx expression
4830 and will convert it to the appropriate shifts and AND operations,
4831 simplifying at each stage.
4833 The function make_compound_operation is called to convert an expression
4834 consisting of shifts and ANDs into the equivalent compound expression.
4835 It is the inverse of this function, loosely speaking. */
4838 expand_compound_operation (x)
4846 switch (GET_CODE (x))
4851 /* We can't necessarily use a const_int for a multiword mode;
4852 it depends on implicitly extending the value.
4853 Since we don't know the right way to extend it,
4854 we can't tell whether the implicit way is right.
4856 Even for a mode that is no wider than a const_int,
4857 we can't win, because we need to sign extend one of its bits through
4858 the rest of it, and we don't know which bit. */
4859 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
4862 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
4863 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
4864 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
4865 reloaded. If not for that, MEM's would very rarely be safe.
4867 Reject MODEs bigger than a word, because we might not be able
4868 to reference a two-register group starting with an arbitrary register
4869 (and currently gen_lowpart might crash for a SUBREG). */
4871 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
4874 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
4875 /* If the inner object has VOIDmode (the only way this can happen
4876 is if it is a ASM_OPERANDS), we can't do anything since we don't
4877 know how much masking to do. */
4886 /* If the operand is a CLOBBER, just return it. */
4887 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
4890 if (GET_CODE (XEXP (x, 1)) != CONST_INT
4891 || GET_CODE (XEXP (x, 2)) != CONST_INT
4892 || GET_MODE (XEXP (x, 0)) == VOIDmode)
4895 len = INTVAL (XEXP (x, 1));
4896 pos = INTVAL (XEXP (x, 2));
4898 /* If this goes outside the object being extracted, replace the object
4899 with a (use (mem ...)) construct that only combine understands
4900 and is used only for this purpose. */
4901 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
4902 SUBST (XEXP (x, 0), gen_rtx (USE, GET_MODE (x), XEXP (x, 0)));
4904 if (BITS_BIG_ENDIAN)
4905 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
4913 /* If we reach here, we want to return a pair of shifts. The inner
4914 shift is a left shift of BITSIZE - POS - LEN bits. The outer
4915 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
4916 logical depending on the value of UNSIGNEDP.
4918 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
4919 converted into an AND of a shift.
4921 We must check for the case where the left shift would have a negative
4922 count. This can happen in a case like (x >> 31) & 255 on machines
4923 that can't shift by a constant. On those machines, we would first
4924 combine the shift with the AND to produce a variable-position
4925 extraction. Then the constant of 31 would be substituted in to produce
4926 a such a position. */
4928 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
4929 if (modewidth >= pos - len)
4930 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
4932 simplify_shift_const (NULL_RTX, ASHIFT,
4935 modewidth - pos - len),
4938 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
4939 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
4940 simplify_shift_const (NULL_RTX, LSHIFTRT,
4943 ((HOST_WIDE_INT) 1 << len) - 1);
4945 /* Any other cases we can't handle. */
4949 /* If we couldn't do this for some reason, return the original
4951 if (GET_CODE (tem) == CLOBBER)
4957 /* X is a SET which contains an assignment of one object into
4958 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
4959 or certain SUBREGS). If possible, convert it into a series of
4962 We half-heartedly support variable positions, but do not at all
4963 support variable lengths. */
4966 expand_field_assignment (x)
4970 rtx pos; /* Always counts from low bit. */
4973 enum machine_mode compute_mode;
4975 /* Loop until we find something we can't simplify. */
4978 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
4979 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
4981 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
4982 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
4983 pos = GEN_INT (BITS_PER_WORD * SUBREG_WORD (XEXP (SET_DEST (x), 0)));
4985 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
4986 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
4988 inner = XEXP (SET_DEST (x), 0);
4989 len = INTVAL (XEXP (SET_DEST (x), 1));
4990 pos = XEXP (SET_DEST (x), 2);
4992 /* If the position is constant and spans the width of INNER,
4993 surround INNER with a USE to indicate this. */
4994 if (GET_CODE (pos) == CONST_INT
4995 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
4996 inner = gen_rtx (USE, GET_MODE (SET_DEST (x)), inner);
4998 if (BITS_BIG_ENDIAN)
5000 if (GET_CODE (pos) == CONST_INT)
5001 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5003 else if (GET_CODE (pos) == MINUS
5004 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5005 && (INTVAL (XEXP (pos, 1))
5006 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5007 /* If position is ADJUST - X, new position is X. */
5008 pos = XEXP (pos, 0);
5010 pos = gen_binary (MINUS, GET_MODE (pos),
5011 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
5017 /* A SUBREG between two modes that occupy the same numbers of words
5018 can be done by moving the SUBREG to the source. */
5019 else if (GET_CODE (SET_DEST (x)) == SUBREG
5020 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5021 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5022 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5023 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5025 x = gen_rtx (SET, VOIDmode, SUBREG_REG (SET_DEST (x)),
5026 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (SET_DEST (x))),
5033 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5034 inner = SUBREG_REG (inner);
5036 compute_mode = GET_MODE (inner);
5038 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5039 if (len < HOST_BITS_PER_WIDE_INT)
5040 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5044 /* Now compute the equivalent expression. Make a copy of INNER
5045 for the SET_DEST in case it is a MEM into which we will substitute;
5046 we don't want shared RTL in that case. */
5047 x = gen_rtx (SET, VOIDmode, copy_rtx (inner),
5048 gen_binary (IOR, compute_mode,
5049 gen_binary (AND, compute_mode,
5050 gen_unary (NOT, compute_mode,
5056 gen_binary (ASHIFT, compute_mode,
5057 gen_binary (AND, compute_mode,
5058 gen_lowpart_for_combine
5068 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5069 it is an RTX that represents a variable starting position; otherwise,
5070 POS is the (constant) starting bit position (counted from the LSB).
5072 INNER may be a USE. This will occur when we started with a bitfield
5073 that went outside the boundary of the object in memory, which is
5074 allowed on most machines. To isolate this case, we produce a USE
5075 whose mode is wide enough and surround the MEM with it. The only
5076 code that understands the USE is this routine. If it is not removed,
5077 it will cause the resulting insn not to match.
5079 UNSIGNEDP is non-zero for an unsigned reference and zero for a
5082 IN_DEST is non-zero if this is a reference in the destination of a
5083 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
5084 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5087 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
5088 ZERO_EXTRACT should be built even for bits starting at bit 0.
5090 MODE is the desired mode of the result (if IN_DEST == 0).
5092 The result is an RTX for the extraction or NULL_RTX if the target
5096 make_extraction (mode, inner, pos, pos_rtx, len,
5097 unsignedp, in_dest, in_compare)
5098 enum machine_mode mode;
5104 int in_dest, in_compare;
5106 /* This mode describes the size of the storage area
5107 to fetch the overall value from. Within that, we
5108 ignore the POS lowest bits, etc. */
5109 enum machine_mode is_mode = GET_MODE (inner);
5110 enum machine_mode inner_mode;
5111 enum machine_mode wanted_inner_mode = byte_mode;
5112 enum machine_mode wanted_inner_reg_mode = word_mode;
5113 enum machine_mode pos_mode = word_mode;
5114 enum machine_mode extraction_mode = word_mode;
5115 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5118 rtx orig_pos_rtx = pos_rtx;
5121 /* Get some information about INNER and get the innermost object. */
5122 if (GET_CODE (inner) == USE)
5123 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5124 /* We don't need to adjust the position because we set up the USE
5125 to pretend that it was a full-word object. */
5126 spans_byte = 1, inner = XEXP (inner, 0);
5127 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5129 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5130 consider just the QI as the memory to extract from.
5131 The subreg adds or removes high bits; its mode is
5132 irrelevant to the meaning of this extraction,
5133 since POS and LEN count from the lsb. */
5134 if (GET_CODE (SUBREG_REG (inner)) == MEM)
5135 is_mode = GET_MODE (SUBREG_REG (inner));
5136 inner = SUBREG_REG (inner);
5139 inner_mode = GET_MODE (inner);
5141 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
5142 pos = INTVAL (pos_rtx), pos_rtx = 0;
5144 /* See if this can be done without an extraction. We never can if the
5145 width of the field is not the same as that of some integer mode. For
5146 registers, we can only avoid the extraction if the position is at the
5147 low-order bit and this is either not in the destination or we have the
5148 appropriate STRICT_LOW_PART operation available.
5150 For MEM, we can avoid an extract if the field starts on an appropriate
5151 boundary and we can change the mode of the memory reference. However,
5152 we cannot directly access the MEM if we have a USE and the underlying
5153 MEM is not TMODE. This combination means that MEM was being used in a
5154 context where bits outside its mode were being referenced; that is only
5155 valid in bit-field insns. */
5157 if (tmode != BLKmode
5158 && ! (spans_byte && inner_mode != tmode)
5159 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
5160 && GET_CODE (inner) != MEM
5162 || (GET_CODE (inner) == REG
5163 && (movstrict_optab->handlers[(int) tmode].insn_code
5164 != CODE_FOR_nothing))))
5165 || (GET_CODE (inner) == MEM && pos_rtx == 0
5167 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
5168 : BITS_PER_UNIT)) == 0
5169 /* We can't do this if we are widening INNER_MODE (it
5170 may not be aligned, for one thing). */
5171 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
5172 && (inner_mode == tmode
5173 || (! mode_dependent_address_p (XEXP (inner, 0))
5174 && ! MEM_VOLATILE_P (inner))))))
5176 /* If INNER is a MEM, make a new MEM that encompasses just the desired
5177 field. If the original and current mode are the same, we need not
5178 adjust the offset. Otherwise, we do if bytes big endian.
5180 If INNER is not a MEM, get a piece consisting of just the field
5181 of interest (in this case POS % BITS_PER_WORD must be 0). */
5183 if (GET_CODE (inner) == MEM)
5186 /* POS counts from lsb, but make OFFSET count in memory order. */
5187 if (BYTES_BIG_ENDIAN)
5188 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
5190 offset = pos / BITS_PER_UNIT;
5192 new = gen_rtx (MEM, tmode, plus_constant (XEXP (inner, 0), offset));
5193 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (inner);
5194 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (inner);
5195 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (inner);
5197 else if (GET_CODE (inner) == REG)
5199 /* We can't call gen_lowpart_for_combine here since we always want
5200 a SUBREG and it would sometimes return a new hard register. */
5201 if (tmode != inner_mode)
5202 new = gen_rtx (SUBREG, tmode, inner,
5204 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD
5205 ? (((GET_MODE_SIZE (inner_mode)
5206 - GET_MODE_SIZE (tmode))
5208 - pos / BITS_PER_WORD)
5209 : pos / BITS_PER_WORD));
5214 new = force_to_mode (inner, tmode,
5215 len >= HOST_BITS_PER_WIDE_INT
5216 ? GET_MODE_MASK (tmode)
5217 : ((HOST_WIDE_INT) 1 << len) - 1,
5220 /* If this extraction is going into the destination of a SET,
5221 make a STRICT_LOW_PART unless we made a MEM. */
5224 return (GET_CODE (new) == MEM ? new
5225 : (GET_CODE (new) != SUBREG
5226 ? gen_rtx (CLOBBER, tmode, const0_rtx)
5227 : gen_rtx_combine (STRICT_LOW_PART, VOIDmode, new)));
5229 /* Otherwise, sign- or zero-extend unless we already are in the
5232 return (mode == tmode ? new
5233 : gen_rtx_combine (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
5237 /* Unless this is a COMPARE or we have a funny memory reference,
5238 don't do anything with zero-extending field extracts starting at
5239 the low-order bit since they are simple AND operations. */
5240 if (pos_rtx == 0 && pos == 0 && ! in_dest
5241 && ! in_compare && ! spans_byte && unsignedp)
5244 /* Unless we are allowed to span bytes, reject this if we would be
5245 spanning bytes or if the position is not a constant and the length
5246 is not 1. In all other cases, we would only be going outside
5247 out object in cases when an original shift would have been
5250 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
5251 || (pos_rtx != 0 && len != 1)))
5254 /* Get the mode to use should INNER not be a MEM, the mode for the position,
5255 and the mode for the result. */
5259 wanted_inner_reg_mode = insn_operand_mode[(int) CODE_FOR_insv][0];
5260 pos_mode = insn_operand_mode[(int) CODE_FOR_insv][2];
5261 extraction_mode = insn_operand_mode[(int) CODE_FOR_insv][3];
5266 if (! in_dest && unsignedp)
5268 wanted_inner_reg_mode = insn_operand_mode[(int) CODE_FOR_extzv][1];
5269 pos_mode = insn_operand_mode[(int) CODE_FOR_extzv][3];
5270 extraction_mode = insn_operand_mode[(int) CODE_FOR_extzv][0];
5275 if (! in_dest && ! unsignedp)
5277 wanted_inner_reg_mode = insn_operand_mode[(int) CODE_FOR_extv][1];
5278 pos_mode = insn_operand_mode[(int) CODE_FOR_extv][3];
5279 extraction_mode = insn_operand_mode[(int) CODE_FOR_extv][0];
5283 /* Never narrow an object, since that might not be safe. */
5285 if (mode != VOIDmode
5286 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
5287 extraction_mode = mode;
5289 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
5290 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
5291 pos_mode = GET_MODE (pos_rtx);
5293 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
5294 if we have to change the mode of memory and cannot, the desired mode is
5296 if (GET_CODE (inner) != MEM)
5297 wanted_inner_mode = wanted_inner_reg_mode;
5298 else if (inner_mode != wanted_inner_mode
5299 && (mode_dependent_address_p (XEXP (inner, 0))
5300 || MEM_VOLATILE_P (inner)))
5301 wanted_inner_mode = extraction_mode;
5305 if (BITS_BIG_ENDIAN)
5307 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
5308 BITS_BIG_ENDIAN style. If position is constant, compute new
5309 position. Otherwise, build subtraction.
5310 Note that POS is relative to the mode of the original argument.
5311 If it's a MEM we need to recompute POS relative to that.
5312 However, if we're extracting from (or inserting into) a register,
5313 we want to recompute POS relative to wanted_inner_mode. */
5314 int width = (GET_CODE (inner) == MEM
5315 ? GET_MODE_BITSIZE (is_mode)
5316 : GET_MODE_BITSIZE (wanted_inner_mode));
5319 pos = width - len - pos;
5322 = gen_rtx_combine (MINUS, GET_MODE (pos_rtx),
5323 GEN_INT (width - len), pos_rtx);
5324 /* POS may be less than 0 now, but we check for that below.
5325 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
5328 /* If INNER has a wider mode, make it smaller. If this is a constant
5329 extract, try to adjust the byte to point to the byte containing
5331 if (wanted_inner_mode != VOIDmode
5332 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
5333 && ((GET_CODE (inner) == MEM
5334 && (inner_mode == wanted_inner_mode
5335 || (! mode_dependent_address_p (XEXP (inner, 0))
5336 && ! MEM_VOLATILE_P (inner))))))
5340 /* The computations below will be correct if the machine is big
5341 endian in both bits and bytes or little endian in bits and bytes.
5342 If it is mixed, we must adjust. */
5344 /* If bytes are big endian and we had a paradoxical SUBREG, we must
5345 adjust OFFSET to compensate. */
5346 if (BYTES_BIG_ENDIAN
5348 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
5349 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
5351 /* If this is a constant position, we can move to the desired byte. */
5354 offset += pos / BITS_PER_UNIT;
5355 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
5358 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
5360 && is_mode != wanted_inner_mode)
5361 offset = (GET_MODE_SIZE (is_mode)
5362 - GET_MODE_SIZE (wanted_inner_mode) - offset);
5364 if (offset != 0 || inner_mode != wanted_inner_mode)
5366 rtx newmem = gen_rtx (MEM, wanted_inner_mode,
5367 plus_constant (XEXP (inner, 0), offset));
5368 RTX_UNCHANGING_P (newmem) = RTX_UNCHANGING_P (inner);
5369 MEM_VOLATILE_P (newmem) = MEM_VOLATILE_P (inner);
5370 MEM_IN_STRUCT_P (newmem) = MEM_IN_STRUCT_P (inner);
5375 /* If INNER is not memory, we can always get it into the proper mode. If we
5376 are changing its mode, POS must be a constant and smaller than the size
5378 else if (GET_CODE (inner) != MEM)
5380 if (GET_MODE (inner) != wanted_inner_mode
5382 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
5385 inner = force_to_mode (inner, wanted_inner_mode,
5387 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
5388 ? GET_MODE_MASK (wanted_inner_mode)
5389 : (((HOST_WIDE_INT) 1 << len) - 1) << orig_pos,
5393 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
5394 have to zero extend. Otherwise, we can just use a SUBREG. */
5396 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
5397 pos_rtx = gen_rtx_combine (ZERO_EXTEND, pos_mode, pos_rtx);
5398 else if (pos_rtx != 0
5399 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
5400 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
5402 /* Make POS_RTX unless we already have it and it is correct. If we don't
5403 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
5405 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
5406 pos_rtx = orig_pos_rtx;
5408 else if (pos_rtx == 0)
5409 pos_rtx = GEN_INT (pos);
5411 /* Make the required operation. See if we can use existing rtx. */
5412 new = gen_rtx_combine (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
5413 extraction_mode, inner, GEN_INT (len), pos_rtx);
5415 new = gen_lowpart_for_combine (mode, new);
5420 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
5421 with any other operations in X. Return X without that shift if so. */
5424 extract_left_shift (x, count)
5428 enum rtx_code code = GET_CODE (x);
5429 enum machine_mode mode = GET_MODE (x);
5435 /* This is the shift itself. If it is wide enough, we will return
5436 either the value being shifted if the shift count is equal to
5437 COUNT or a shift for the difference. */
5438 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5439 && INTVAL (XEXP (x, 1)) >= count)
5440 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
5441 INTVAL (XEXP (x, 1)) - count);
5445 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
5446 return gen_unary (code, mode, mode, tem);
5450 case PLUS: case IOR: case XOR: case AND:
5451 /* If we can safely shift this constant and we find the inner shift,
5452 make a new operation. */
5453 if (GET_CODE (XEXP (x,1)) == CONST_INT
5454 && (INTVAL (XEXP (x, 1)) & (((HOST_WIDE_INT) 1 << count)) - 1) == 0
5455 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
5456 return gen_binary (code, mode, tem,
5457 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
5465 /* Look at the expression rooted at X. Look for expressions
5466 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
5467 Form these expressions.
5469 Return the new rtx, usually just X.
5471 Also, for machines like the Vax that don't have logical shift insns,
5472 try to convert logical to arithmetic shift operations in cases where
5473 they are equivalent. This undoes the canonicalizations to logical
5474 shifts done elsewhere.
5476 We try, as much as possible, to re-use rtl expressions to save memory.
5478 IN_CODE says what kind of expression we are processing. Normally, it is
5479 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
5480 being kludges), it is MEM. When processing the arguments of a comparison
5481 or a COMPARE against zero, it is COMPARE. */
5484 make_compound_operation (x, in_code)
5486 enum rtx_code in_code;
5488 enum rtx_code code = GET_CODE (x);
5489 enum machine_mode mode = GET_MODE (x);
5490 int mode_width = GET_MODE_BITSIZE (mode);
5492 enum rtx_code next_code;
5498 /* Select the code to be used in recursive calls. Once we are inside an
5499 address, we stay there. If we have a comparison, set to COMPARE,
5500 but once inside, go back to our default of SET. */
5502 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
5503 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
5504 && XEXP (x, 1) == const0_rtx) ? COMPARE
5505 : in_code == COMPARE ? SET : in_code);
5507 /* Process depending on the code of this operation. If NEW is set
5508 non-zero, it will be returned. */
5513 /* Convert shifts by constants into multiplications if inside
5515 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
5516 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
5517 && INTVAL (XEXP (x, 1)) >= 0)
5519 new = make_compound_operation (XEXP (x, 0), next_code);
5520 new = gen_rtx_combine (MULT, mode, new,
5521 GEN_INT ((HOST_WIDE_INT) 1
5522 << INTVAL (XEXP (x, 1))));
5527 /* If the second operand is not a constant, we can't do anything
5529 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
5532 /* If the constant is a power of two minus one and the first operand
5533 is a logical right shift, make an extraction. */
5534 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
5535 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5537 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
5538 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
5539 0, in_code == COMPARE);
5542 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
5543 else if (GET_CODE (XEXP (x, 0)) == SUBREG
5544 && subreg_lowpart_p (XEXP (x, 0))
5545 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
5546 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5548 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
5550 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
5551 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
5552 0, in_code == COMPARE);
5554 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
5555 else if ((GET_CODE (XEXP (x, 0)) == XOR
5556 || GET_CODE (XEXP (x, 0)) == IOR)
5557 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
5558 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
5559 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5561 /* Apply the distributive law, and then try to make extractions. */
5562 new = gen_rtx_combine (GET_CODE (XEXP (x, 0)), mode,
5563 gen_rtx (AND, mode, XEXP (XEXP (x, 0), 0),
5565 gen_rtx (AND, mode, XEXP (XEXP (x, 0), 1),
5567 new = make_compound_operation (new, in_code);
5570 /* If we are have (and (rotate X C) M) and C is larger than the number
5571 of bits in M, this is an extraction. */
5573 else if (GET_CODE (XEXP (x, 0)) == ROTATE
5574 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5575 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
5576 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
5578 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
5579 new = make_extraction (mode, new,
5580 (GET_MODE_BITSIZE (mode)
5581 - INTVAL (XEXP (XEXP (x, 0), 1))),
5582 NULL_RTX, i, 1, 0, in_code == COMPARE);
5585 /* On machines without logical shifts, if the operand of the AND is
5586 a logical shift and our mask turns off all the propagated sign
5587 bits, we can replace the logical shift with an arithmetic shift. */
5588 else if (ashr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
5589 && (lshr_optab->handlers[(int) mode].insn_code
5590 == CODE_FOR_nothing)
5591 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
5592 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5593 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
5594 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
5595 && mode_width <= HOST_BITS_PER_WIDE_INT)
5597 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
5599 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
5600 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
5602 gen_rtx_combine (ASHIFTRT, mode,
5603 make_compound_operation (XEXP (XEXP (x, 0), 0),
5605 XEXP (XEXP (x, 0), 1)));
5608 /* If the constant is one less than a power of two, this might be
5609 representable by an extraction even if no shift is present.
5610 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
5611 we are in a COMPARE. */
5612 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5613 new = make_extraction (mode,
5614 make_compound_operation (XEXP (x, 0),
5616 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
5618 /* If we are in a comparison and this is an AND with a power of two,
5619 convert this into the appropriate bit extract. */
5620 else if (in_code == COMPARE
5621 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
5622 new = make_extraction (mode,
5623 make_compound_operation (XEXP (x, 0),
5625 i, NULL_RTX, 1, 1, 0, 1);
5630 /* If the sign bit is known to be zero, replace this with an
5631 arithmetic shift. */
5632 if (ashr_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing
5633 && lshr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
5634 && mode_width <= HOST_BITS_PER_WIDE_INT
5635 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
5637 new = gen_rtx_combine (ASHIFTRT, mode,
5638 make_compound_operation (XEXP (x, 0),
5644 /* ... fall through ... */
5650 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
5651 this is a SIGN_EXTRACT. */
5652 if (GET_CODE (rhs) == CONST_INT
5653 && GET_CODE (lhs) == ASHIFT
5654 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
5655 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
5657 new = make_compound_operation (XEXP (lhs, 0), next_code);
5658 new = make_extraction (mode, new,
5659 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
5660 NULL_RTX, mode_width - INTVAL (rhs),
5661 code == LSHIFTRT, 0, in_code == COMPARE);
5664 /* See if we have operations between an ASHIFTRT and an ASHIFT.
5665 If so, try to merge the shifts into a SIGN_EXTEND. We could
5666 also do this for some cases of SIGN_EXTRACT, but it doesn't
5667 seem worth the effort; the case checked for occurs on Alpha. */
5669 if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o'
5670 && ! (GET_CODE (lhs) == SUBREG
5671 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o'))
5672 && GET_CODE (rhs) == CONST_INT
5673 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
5674 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
5675 new = make_extraction (mode, make_compound_operation (new, next_code),
5676 0, NULL_RTX, mode_width - INTVAL (rhs),
5677 code == LSHIFTRT, 0, in_code == COMPARE);
5682 /* Call ourselves recursively on the inner expression. If we are
5683 narrowing the object and it has a different RTL code from
5684 what it originally did, do this SUBREG as a force_to_mode. */
5686 tem = make_compound_operation (SUBREG_REG (x), in_code);
5687 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
5688 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
5689 && subreg_lowpart_p (x))
5691 rtx newer = force_to_mode (tem, mode,
5692 GET_MODE_MASK (mode), NULL_RTX, 0);
5694 /* If we have something other than a SUBREG, we might have
5695 done an expansion, so rerun outselves. */
5696 if (GET_CODE (newer) != SUBREG)
5697 newer = make_compound_operation (newer, in_code);
5705 x = gen_lowpart_for_combine (mode, new);
5706 code = GET_CODE (x);
5709 /* Now recursively process each operand of this operation. */
5710 fmt = GET_RTX_FORMAT (code);
5711 for (i = 0; i < GET_RTX_LENGTH (code); i++)
5714 new = make_compound_operation (XEXP (x, i), next_code);
5715 SUBST (XEXP (x, i), new);
5721 /* Given M see if it is a value that would select a field of bits
5722 within an item, but not the entire word. Return -1 if not.
5723 Otherwise, return the starting position of the field, where 0 is the
5726 *PLEN is set to the length of the field. */
5729 get_pos_from_mask (m, plen)
5730 unsigned HOST_WIDE_INT m;
5733 /* Get the bit number of the first 1 bit from the right, -1 if none. */
5734 int pos = exact_log2 (m & - m);
5739 /* Now shift off the low-order zero bits and see if we have a power of
5741 *plen = exact_log2 ((m >> pos) + 1);
5749 /* See if X can be simplified knowing that we will only refer to it in
5750 MODE and will only refer to those bits that are nonzero in MASK.
5751 If other bits are being computed or if masking operations are done
5752 that select a superset of the bits in MASK, they can sometimes be
5755 Return a possibly simplified expression, but always convert X to
5756 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
5758 Also, if REG is non-zero and X is a register equal in value to REG,
5761 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
5762 are all off in X. This is used when X will be complemented, by either
5763 NOT, NEG, or XOR. */
5766 force_to_mode (x, mode, mask, reg, just_select)
5768 enum machine_mode mode;
5769 unsigned HOST_WIDE_INT mask;
5773 enum rtx_code code = GET_CODE (x);
5774 int next_select = just_select || code == XOR || code == NOT || code == NEG;
5775 enum machine_mode op_mode;
5776 unsigned HOST_WIDE_INT fuller_mask, nonzero;
5779 /* If this is a CALL, don't do anything. Some of the code below
5780 will do the wrong thing since the mode of a CALL is VOIDmode. */
5784 /* We want to perform the operation is its present mode unless we know
5785 that the operation is valid in MODE, in which case we do the operation
5787 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
5788 && code_to_optab[(int) code] != 0
5789 && (code_to_optab[(int) code]->handlers[(int) mode].insn_code
5790 != CODE_FOR_nothing))
5791 ? mode : GET_MODE (x));
5793 /* It is not valid to do a right-shift in a narrower mode
5794 than the one it came in with. */
5795 if ((code == LSHIFTRT || code == ASHIFTRT)
5796 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
5797 op_mode = GET_MODE (x);
5799 /* Truncate MASK to fit OP_MODE. */
5801 mask &= GET_MODE_MASK (op_mode);
5803 /* When we have an arithmetic operation, or a shift whose count we
5804 do not know, we need to assume that all bit the up to the highest-order
5805 bit in MASK will be needed. This is how we form such a mask. */
5807 fuller_mask = (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT
5808 ? GET_MODE_MASK (op_mode)
5809 : ((HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1)) - 1);
5811 fuller_mask = ~ (HOST_WIDE_INT) 0;
5813 /* Determine what bits of X are guaranteed to be (non)zero. */
5814 nonzero = nonzero_bits (x, mode);
5816 /* If none of the bits in X are needed, return a zero. */
5817 if (! just_select && (nonzero & mask) == 0)
5820 /* If X is a CONST_INT, return a new one. Do this here since the
5821 test below will fail. */
5822 if (GET_CODE (x) == CONST_INT)
5824 HOST_WIDE_INT cval = INTVAL (x) & mask;
5825 int width = GET_MODE_BITSIZE (mode);
5827 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
5828 number, sign extend it. */
5829 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
5830 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
5831 cval |= (HOST_WIDE_INT) -1 << width;
5833 return GEN_INT (cval);
5836 /* If X is narrower than MODE and we want all the bits in X's mode, just
5837 get X in the proper mode. */
5838 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
5839 && (GET_MODE_MASK (GET_MODE (x)) & ~ mask) == 0)
5840 return gen_lowpart_for_combine (mode, x);
5842 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
5843 MASK are already known to be zero in X, we need not do anything. */
5844 if (GET_MODE (x) == mode && code != SUBREG && (~ mask & nonzero) == 0)
5850 /* If X is a (clobber (const_int)), return it since we know we are
5851 generating something that won't match. */
5855 /* X is a (use (mem ..)) that was made from a bit-field extraction that
5856 spanned the boundary of the MEM. If we are now masking so it is
5857 within that boundary, we don't need the USE any more. */
5858 if (! BITS_BIG_ENDIAN
5859 && (mask & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5860 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
5867 x = expand_compound_operation (x);
5868 if (GET_CODE (x) != code)
5869 return force_to_mode (x, mode, mask, reg, next_select);
5873 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
5874 || rtx_equal_p (reg, get_last_value (x))))
5879 if (subreg_lowpart_p (x)
5880 /* We can ignore the effect of this SUBREG if it narrows the mode or
5881 if the constant masks to zero all the bits the mode doesn't
5883 && ((GET_MODE_SIZE (GET_MODE (x))
5884 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
5886 & GET_MODE_MASK (GET_MODE (x))
5887 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
5888 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
5892 /* If this is an AND with a constant, convert it into an AND
5893 whose constant is the AND of that constant with MASK. If it
5894 remains an AND of MASK, delete it since it is redundant. */
5896 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
5898 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
5899 mask & INTVAL (XEXP (x, 1)));
5901 /* If X is still an AND, see if it is an AND with a mask that
5902 is just some low-order bits. If so, and it is MASK, we don't
5905 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
5906 && INTVAL (XEXP (x, 1)) == mask)
5909 /* If it remains an AND, try making another AND with the bits
5910 in the mode mask that aren't in MASK turned on. If the
5911 constant in the AND is wide enough, this might make a
5912 cheaper constant. */
5914 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
5915 && GET_MODE_MASK (GET_MODE (x)) != mask
5916 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
5918 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
5919 | (GET_MODE_MASK (GET_MODE (x)) & ~ mask));
5920 int width = GET_MODE_BITSIZE (GET_MODE (x));
5923 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
5924 number, sign extend it. */
5925 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
5926 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
5927 cval |= (HOST_WIDE_INT) -1 << width;
5929 y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
5930 if (rtx_cost (y, SET) < rtx_cost (x, SET))
5940 /* In (and (plus FOO C1) M), if M is a mask that just turns off
5941 low-order bits (as in an alignment operation) and FOO is already
5942 aligned to that boundary, mask C1 to that boundary as well.
5943 This may eliminate that PLUS and, later, the AND. */
5946 int width = GET_MODE_BITSIZE (mode);
5947 unsigned HOST_WIDE_INT smask = mask;
5949 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
5950 number, sign extend it. */
5952 if (width < HOST_BITS_PER_WIDE_INT
5953 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
5954 smask |= (HOST_WIDE_INT) -1 << width;
5956 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5957 && exact_log2 (- smask) >= 0
5958 && (nonzero_bits (XEXP (x, 0), mode) & ~ mask) == 0
5959 && (INTVAL (XEXP (x, 1)) & ~ mask) != 0)
5960 return force_to_mode (plus_constant (XEXP (x, 0),
5961 INTVAL (XEXP (x, 1)) & mask),
5962 mode, mask, reg, next_select);
5965 /* ... fall through ... */
5969 /* For PLUS, MINUS and MULT, we need any bits less significant than the
5970 most significant bit in MASK since carries from those bits will
5971 affect the bits we are interested in. */
5977 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
5978 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
5979 operation which may be a bitfield extraction. Ensure that the
5980 constant we form is not wider than the mode of X. */
5982 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
5983 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5984 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
5985 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
5986 && GET_CODE (XEXP (x, 1)) == CONST_INT
5987 && ((INTVAL (XEXP (XEXP (x, 0), 1))
5988 + floor_log2 (INTVAL (XEXP (x, 1))))
5989 < GET_MODE_BITSIZE (GET_MODE (x)))
5990 && (INTVAL (XEXP (x, 1))
5991 & ~ nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
5993 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
5994 << INTVAL (XEXP (XEXP (x, 0), 1)));
5995 temp = gen_binary (GET_CODE (x), GET_MODE (x),
5996 XEXP (XEXP (x, 0), 0), temp);
5997 x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
5998 XEXP (XEXP (x, 0), 1));
5999 return force_to_mode (x, mode, mask, reg, next_select);
6003 /* For most binary operations, just propagate into the operation and
6004 change the mode if we have an operation of that mode. */
6006 op0 = gen_lowpart_for_combine (op_mode,
6007 force_to_mode (XEXP (x, 0), mode, mask,
6009 op1 = gen_lowpart_for_combine (op_mode,
6010 force_to_mode (XEXP (x, 1), mode, mask,
6013 /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside
6014 MASK since OP1 might have been sign-extended but we never want
6015 to turn on extra bits, since combine might have previously relied
6016 on them being off. */
6017 if (GET_CODE (op1) == CONST_INT && (code == IOR || code == XOR)
6018 && (INTVAL (op1) & mask) != 0)
6019 op1 = GEN_INT (INTVAL (op1) & mask);
6021 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6022 x = gen_binary (code, op_mode, op0, op1);
6026 /* For left shifts, do the same, but just for the first operand.
6027 However, we cannot do anything with shifts where we cannot
6028 guarantee that the counts are smaller than the size of the mode
6029 because such a count will have a different meaning in a
6032 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
6033 && INTVAL (XEXP (x, 1)) >= 0
6034 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
6035 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
6036 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
6037 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
6040 /* If the shift count is a constant and we can do arithmetic in
6041 the mode of the shift, refine which bits we need. Otherwise, use the
6042 conservative form of the mask. */
6043 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6044 && INTVAL (XEXP (x, 1)) >= 0
6045 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
6046 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6047 mask >>= INTVAL (XEXP (x, 1));
6051 op0 = gen_lowpart_for_combine (op_mode,
6052 force_to_mode (XEXP (x, 0), op_mode,
6053 mask, reg, next_select));
6055 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6056 x = gen_binary (code, op_mode, op0, XEXP (x, 1));
6060 /* Here we can only do something if the shift count is a constant,
6061 this shift constant is valid for the host, and we can do arithmetic
6064 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6065 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6066 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6068 rtx inner = XEXP (x, 0);
6070 /* Select the mask of the bits we need for the shift operand. */
6071 mask <<= INTVAL (XEXP (x, 1));
6073 /* We can only change the mode of the shift if we can do arithmetic
6074 in the mode of the shift and MASK is no wider than the width of
6076 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT
6077 || (mask & ~ GET_MODE_MASK (op_mode)) != 0)
6078 op_mode = GET_MODE (x);
6080 inner = force_to_mode (inner, op_mode, mask, reg, next_select);
6082 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
6083 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
6086 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
6087 shift and AND produces only copies of the sign bit (C2 is one less
6088 than a power of two), we can do this with just a shift. */
6090 if (GET_CODE (x) == LSHIFTRT
6091 && GET_CODE (XEXP (x, 1)) == CONST_INT
6092 && ((INTVAL (XEXP (x, 1))
6093 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
6094 >= GET_MODE_BITSIZE (GET_MODE (x)))
6095 && exact_log2 (mask + 1) >= 0
6096 && (num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6097 >= exact_log2 (mask + 1)))
6098 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
6099 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
6100 - exact_log2 (mask + 1)));
6104 /* If we are just looking for the sign bit, we don't need this shift at
6105 all, even if it has a variable count. */
6106 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6107 && (mask == ((HOST_WIDE_INT) 1
6108 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
6109 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6111 /* If this is a shift by a constant, get a mask that contains those bits
6112 that are not copies of the sign bit. We then have two cases: If
6113 MASK only includes those bits, this can be a logical shift, which may
6114 allow simplifications. If MASK is a single-bit field not within
6115 those bits, we are requesting a copy of the sign bit and hence can
6116 shift the sign bit to the appropriate location. */
6118 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
6119 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
6123 /* If the considered data is wider then HOST_WIDE_INT, we can't
6124 represent a mask for all its bits in a single scalar.
6125 But we only care about the lower bits, so calculate these. */
6127 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
6129 nonzero = ~ (HOST_WIDE_INT) 0;
6131 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6132 is the number of bits a full-width mask would have set.
6133 We need only shift if these are fewer than nonzero can
6134 hold. If not, we must keep all bits set in nonzero. */
6136 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6137 < HOST_BITS_PER_WIDE_INT)
6138 nonzero >>= INTVAL (XEXP (x, 1))
6139 + HOST_BITS_PER_WIDE_INT
6140 - GET_MODE_BITSIZE (GET_MODE (x)) ;
6144 nonzero = GET_MODE_MASK (GET_MODE (x));
6145 nonzero >>= INTVAL (XEXP (x, 1));
6148 if ((mask & ~ nonzero) == 0
6149 || (i = exact_log2 (mask)) >= 0)
6151 x = simplify_shift_const
6152 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
6153 i < 0 ? INTVAL (XEXP (x, 1))
6154 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
6156 if (GET_CODE (x) != ASHIFTRT)
6157 return force_to_mode (x, mode, mask, reg, next_select);
6161 /* If MASK is 1, convert this to a LSHIFTRT. This can be done
6162 even if the shift count isn't a constant. */
6164 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
6166 /* If this is a sign-extension operation that just affects bits
6167 we don't care about, remove it. Be sure the call above returned
6168 something that is still a shift. */
6170 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
6171 && GET_CODE (XEXP (x, 1)) == CONST_INT
6172 && INTVAL (XEXP (x, 1)) >= 0
6173 && (INTVAL (XEXP (x, 1))
6174 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
6175 && GET_CODE (XEXP (x, 0)) == ASHIFT
6176 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6177 && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1)))
6178 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
6185 /* If the shift count is constant and we can do computations
6186 in the mode of X, compute where the bits we care about are.
6187 Otherwise, we can't do anything. Don't change the mode of
6188 the shift or propagate MODE into the shift, though. */
6189 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6190 && INTVAL (XEXP (x, 1)) >= 0)
6192 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
6193 GET_MODE (x), GEN_INT (mask),
6195 if (temp && GET_CODE(temp) == CONST_INT)
6197 force_to_mode (XEXP (x, 0), GET_MODE (x),
6198 INTVAL (temp), reg, next_select));
6203 /* If we just want the low-order bit, the NEG isn't needed since it
6204 won't change the low-order bit. */
6206 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
6208 /* We need any bits less significant than the most significant bit in
6209 MASK since carries from those bits will affect the bits we are
6215 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
6216 same as the XOR case above. Ensure that the constant we form is not
6217 wider than the mode of X. */
6219 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6220 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6221 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6222 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
6223 < GET_MODE_BITSIZE (GET_MODE (x)))
6224 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
6226 temp = GEN_INT (mask << INTVAL (XEXP (XEXP (x, 0), 1)));
6227 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
6228 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
6230 return force_to_mode (x, mode, mask, reg, next_select);
6233 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
6234 use the full mask inside the NOT. */
6238 op0 = gen_lowpart_for_combine (op_mode,
6239 force_to_mode (XEXP (x, 0), mode, mask,
6241 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6242 x = gen_unary (code, op_mode, op_mode, op0);
6246 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
6247 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
6248 which is in CONST. */
6249 if ((mask & ~ STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
6250 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
6251 && (nonzero_bits (XEXP (x, 0), mode) & ~ mask) == 0)
6252 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6257 /* We have no way of knowing if the IF_THEN_ELSE can itself be
6258 written in a narrower mode. We play it safe and do not do so. */
6261 gen_lowpart_for_combine (GET_MODE (x),
6262 force_to_mode (XEXP (x, 1), mode,
6263 mask, reg, next_select)));
6265 gen_lowpart_for_combine (GET_MODE (x),
6266 force_to_mode (XEXP (x, 2), mode,
6267 mask, reg,next_select)));
6271 /* Ensure we return a value of the proper mode. */
6272 return gen_lowpart_for_combine (mode, x);
6275 /* Return nonzero if X is an expression that has one of two values depending on
6276 whether some other value is zero or nonzero. In that case, we return the
6277 value that is being tested, *PTRUE is set to the value if the rtx being
6278 returned has a nonzero value, and *PFALSE is set to the other alternative.
6280 If we return zero, we set *PTRUE and *PFALSE to X. */
6283 if_then_else_cond (x, ptrue, pfalse)
6285 rtx *ptrue, *pfalse;
6287 enum machine_mode mode = GET_MODE (x);
6288 enum rtx_code code = GET_CODE (x);
6289 int size = GET_MODE_BITSIZE (mode);
6290 rtx cond0, cond1, true0, true1, false0, false1;
6291 unsigned HOST_WIDE_INT nz;
6293 /* If this is a unary operation whose operand has one of two values, apply
6294 our opcode to compute those values. */
6295 if (GET_RTX_CLASS (code) == '1'
6296 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
6298 *ptrue = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), true0);
6299 *pfalse = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), false0);
6303 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
6304 make can't possibly match and would suppress other optimizations. */
6305 else if (code == COMPARE)
6308 /* If this is a binary operation, see if either side has only one of two
6309 values. If either one does or if both do and they are conditional on
6310 the same value, compute the new true and false values. */
6311 else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2'
6312 || GET_RTX_CLASS (code) == '<')
6314 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
6315 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
6317 if ((cond0 != 0 || cond1 != 0)
6318 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
6320 *ptrue = gen_binary (code, mode, true0, true1);
6321 *pfalse = gen_binary (code, mode, false0, false1);
6322 return cond0 ? cond0 : cond1;
6325 #if STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1
6327 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
6328 operands is zero when the other is non-zero, and vice-versa. */
6330 if ((code == PLUS || code == IOR || code == XOR || code == MINUS
6332 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
6334 rtx op0 = XEXP (XEXP (x, 0), 1);
6335 rtx op1 = XEXP (XEXP (x, 1), 1);
6337 cond0 = XEXP (XEXP (x, 0), 0);
6338 cond1 = XEXP (XEXP (x, 1), 0);
6340 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
6341 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
6342 && reversible_comparison_p (cond1)
6343 && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
6344 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
6345 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
6346 || ((swap_condition (GET_CODE (cond0))
6347 == reverse_condition (GET_CODE (cond1)))
6348 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
6349 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
6350 && ! side_effects_p (x))
6352 *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
6353 *pfalse = gen_binary (MULT, mode,
6355 ? gen_unary (NEG, mode, mode, op1) : op1),
6361 /* Similarly for MULT, AND and UMIN, execpt that for these the result
6363 if ((code == MULT || code == AND || code == UMIN)
6364 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
6366 cond0 = XEXP (XEXP (x, 0), 0);
6367 cond1 = XEXP (XEXP (x, 1), 0);
6369 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
6370 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
6371 && reversible_comparison_p (cond1)
6372 && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
6373 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
6374 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
6375 || ((swap_condition (GET_CODE (cond0))
6376 == reverse_condition (GET_CODE (cond1)))
6377 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
6378 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
6379 && ! side_effects_p (x))
6381 *ptrue = *pfalse = const0_rtx;
6388 else if (code == IF_THEN_ELSE)
6390 /* If we have IF_THEN_ELSE already, extract the condition and
6391 canonicalize it if it is NE or EQ. */
6392 cond0 = XEXP (x, 0);
6393 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
6394 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
6395 return XEXP (cond0, 0);
6396 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
6398 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
6399 return XEXP (cond0, 0);
6405 /* If X is a normal SUBREG with both inner and outer modes integral,
6406 we can narrow both the true and false values of the inner expression,
6407 if there is a condition. */
6408 else if (code == SUBREG && GET_MODE_CLASS (mode) == MODE_INT
6409 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_INT
6410 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))
6411 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
6414 *ptrue = force_to_mode (true0, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
6416 = force_to_mode (false0, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
6421 /* If X is a constant, this isn't special and will cause confusions
6422 if we treat it as such. Likewise if it is equivalent to a constant. */
6423 else if (CONSTANT_P (x)
6424 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
6427 /* If X is known to be either 0 or -1, those are the true and
6428 false values when testing X. */
6429 else if (num_sign_bit_copies (x, mode) == size)
6431 *ptrue = constm1_rtx, *pfalse = const0_rtx;
6435 /* Likewise for 0 or a single bit. */
6436 else if (exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
6438 *ptrue = GEN_INT (nz), *pfalse = const0_rtx;
6442 /* Otherwise fail; show no condition with true and false values the same. */
6443 *ptrue = *pfalse = x;
6447 /* Return the value of expression X given the fact that condition COND
6448 is known to be true when applied to REG as its first operand and VAL
6449 as its second. X is known to not be shared and so can be modified in
6452 We only handle the simplest cases, and specifically those cases that
6453 arise with IF_THEN_ELSE expressions. */
6456 known_cond (x, cond, reg, val)
6461 enum rtx_code code = GET_CODE (x);
6466 if (side_effects_p (x))
6469 if (cond == EQ && rtx_equal_p (x, reg))
6472 /* If X is (abs REG) and we know something about REG's relationship
6473 with zero, we may be able to simplify this. */
6475 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
6478 case GE: case GT: case EQ:
6481 return gen_unary (NEG, GET_MODE (XEXP (x, 0)), GET_MODE (XEXP (x, 0)),
6485 /* The only other cases we handle are MIN, MAX, and comparisons if the
6486 operands are the same as REG and VAL. */
6488 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
6490 if (rtx_equal_p (XEXP (x, 0), val))
6491 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
6493 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
6495 if (GET_RTX_CLASS (code) == '<')
6496 return (comparison_dominates_p (cond, code) ? const_true_rtx
6497 : (comparison_dominates_p (cond,
6498 reverse_condition (code))
6501 else if (code == SMAX || code == SMIN
6502 || code == UMIN || code == UMAX)
6504 int unsignedp = (code == UMIN || code == UMAX);
6506 if (code == SMAX || code == UMAX)
6507 cond = reverse_condition (cond);
6512 return unsignedp ? x : XEXP (x, 1);
6514 return unsignedp ? x : XEXP (x, 0);
6516 return unsignedp ? XEXP (x, 1) : x;
6518 return unsignedp ? XEXP (x, 0) : x;
6524 fmt = GET_RTX_FORMAT (code);
6525 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6528 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
6529 else if (fmt[i] == 'E')
6530 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
6531 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
6538 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
6539 assignment as a field assignment. */
6542 rtx_equal_for_field_assignment_p (x, y)
6548 if (x == y || rtx_equal_p (x, y))
6551 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
6554 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
6555 Note that all SUBREGs of MEM are paradoxical; otherwise they
6556 would have been rewritten. */
6557 if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG
6558 && GET_CODE (SUBREG_REG (y)) == MEM
6559 && rtx_equal_p (SUBREG_REG (y),
6560 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x)))
6563 if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG
6564 && GET_CODE (SUBREG_REG (x)) == MEM
6565 && rtx_equal_p (SUBREG_REG (x),
6566 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y)))
6569 last_x = get_last_value (x);
6570 last_y = get_last_value (y);
6572 return ((last_x != 0
6573 && GET_CODE (last_x) != CLOBBER
6574 && rtx_equal_for_field_assignment_p (last_x, y))
6576 && GET_CODE (last_y) != CLOBBER
6577 && rtx_equal_for_field_assignment_p (x, last_y))
6578 || (last_x != 0 && last_y != 0
6579 && GET_CODE (last_x) != CLOBBER
6580 && GET_CODE (last_y) != CLOBBER
6581 && rtx_equal_for_field_assignment_p (last_x, last_y)));
6584 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
6585 Return that assignment if so.
6587 We only handle the most common cases. */
6590 make_field_assignment (x)
6593 rtx dest = SET_DEST (x);
6594 rtx src = SET_SRC (x);
6600 enum machine_mode mode;
6602 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
6603 a clear of a one-bit field. We will have changed it to
6604 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
6607 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
6608 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
6609 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
6610 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
6612 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
6615 return gen_rtx (SET, VOIDmode, assign, const0_rtx);
6619 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
6620 && subreg_lowpart_p (XEXP (src, 0))
6621 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
6622 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
6623 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
6624 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
6625 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
6627 assign = make_extraction (VOIDmode, dest, 0,
6628 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
6631 return gen_rtx (SET, VOIDmode, assign, const0_rtx);
6635 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
6637 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
6638 && XEXP (XEXP (src, 0), 0) == const1_rtx
6639 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
6641 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
6644 return gen_rtx (SET, VOIDmode, assign, const1_rtx);
6648 /* The other case we handle is assignments into a constant-position
6649 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
6650 a mask that has all one bits except for a group of zero bits and
6651 OTHER is known to have zeros where C1 has ones, this is such an
6652 assignment. Compute the position and length from C1. Shift OTHER
6653 to the appropriate position, force it to the required mode, and
6654 make the extraction. Check for the AND in both operands. */
6656 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
6659 rhs = expand_compound_operation (XEXP (src, 0));
6660 lhs = expand_compound_operation (XEXP (src, 1));
6662 if (GET_CODE (rhs) == AND
6663 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
6664 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
6665 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
6666 else if (GET_CODE (lhs) == AND
6667 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6668 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
6669 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
6673 pos = get_pos_from_mask ((~ c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
6674 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
6675 || (GET_MODE_BITSIZE (GET_MODE (other)) <= HOST_BITS_PER_WIDE_INT
6676 && (c1 & nonzero_bits (other, GET_MODE (other))) != 0))
6679 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
6683 /* The mode to use for the source is the mode of the assignment, or of
6684 what is inside a possible STRICT_LOW_PART. */
6685 mode = (GET_CODE (assign) == STRICT_LOW_PART
6686 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
6688 /* Shift OTHER right POS places and make it the source, restricting it
6689 to the proper length and mode. */
6691 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
6692 GET_MODE (src), other, pos),
6694 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
6695 ? GET_MODE_MASK (mode)
6696 : ((HOST_WIDE_INT) 1 << len) - 1,
6699 return gen_rtx_combine (SET, VOIDmode, assign, src);
6702 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
6706 apply_distributive_law (x)
6709 enum rtx_code code = GET_CODE (x);
6710 rtx lhs, rhs, other;
6712 enum rtx_code inner_code;
6714 /* Distributivity is not true for floating point.
6715 It can change the value. So don't do it.
6716 -- rms and moshier@world.std.com. */
6717 if (FLOAT_MODE_P (GET_MODE (x)))
6720 /* The outer operation can only be one of the following: */
6721 if (code != IOR && code != AND && code != XOR
6722 && code != PLUS && code != MINUS)
6725 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
6727 /* If either operand is a primitive we can't do anything, so get out
6729 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
6730 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
6733 lhs = expand_compound_operation (lhs);
6734 rhs = expand_compound_operation (rhs);
6735 inner_code = GET_CODE (lhs);
6736 if (inner_code != GET_CODE (rhs))
6739 /* See if the inner and outer operations distribute. */
6746 /* These all distribute except over PLUS. */
6747 if (code == PLUS || code == MINUS)
6752 if (code != PLUS && code != MINUS)
6757 /* This is also a multiply, so it distributes over everything. */
6761 /* Non-paradoxical SUBREGs distributes over all operations, provided
6762 the inner modes and word numbers are the same, this is an extraction
6763 of a low-order part, we don't convert an fp operation to int or
6764 vice versa, and we would not be converting a single-word
6765 operation into a multi-word operation. The latter test is not
6766 required, but it prevents generating unneeded multi-word operations.
6767 Some of the previous tests are redundant given the latter test, but
6768 are retained because they are required for correctness.
6770 We produce the result slightly differently in this case. */
6772 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
6773 || SUBREG_WORD (lhs) != SUBREG_WORD (rhs)
6774 || ! subreg_lowpart_p (lhs)
6775 || (GET_MODE_CLASS (GET_MODE (lhs))
6776 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
6777 || (GET_MODE_SIZE (GET_MODE (lhs))
6778 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
6779 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
6782 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
6783 SUBREG_REG (lhs), SUBREG_REG (rhs));
6784 return gen_lowpart_for_combine (GET_MODE (x), tem);
6790 /* Set LHS and RHS to the inner operands (A and B in the example
6791 above) and set OTHER to the common operand (C in the example).
6792 These is only one way to do this unless the inner operation is
6794 if (GET_RTX_CLASS (inner_code) == 'c'
6795 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
6796 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
6797 else if (GET_RTX_CLASS (inner_code) == 'c'
6798 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
6799 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
6800 else if (GET_RTX_CLASS (inner_code) == 'c'
6801 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
6802 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
6803 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
6804 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
6808 /* Form the new inner operation, seeing if it simplifies first. */
6809 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
6811 /* There is one exception to the general way of distributing:
6812 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
6813 if (code == XOR && inner_code == IOR)
6816 other = gen_unary (NOT, GET_MODE (x), GET_MODE (x), other);
6819 /* We may be able to continuing distributing the result, so call
6820 ourselves recursively on the inner operation before forming the
6821 outer operation, which we return. */
6822 return gen_binary (inner_code, GET_MODE (x),
6823 apply_distributive_law (tem), other);
6826 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
6829 Return an equivalent form, if different from X. Otherwise, return X. If
6830 X is zero, we are to always construct the equivalent form. */
6833 simplify_and_const_int (x, mode, varop, constop)
6835 enum machine_mode mode;
6837 unsigned HOST_WIDE_INT constop;
6839 unsigned HOST_WIDE_INT nonzero;
6840 int width = GET_MODE_BITSIZE (mode);
6843 /* Simplify VAROP knowing that we will be only looking at some of the
6845 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
6847 /* If VAROP is a CLOBBER, we will fail so return it; if it is a
6848 CONST_INT, we are done. */
6849 if (GET_CODE (varop) == CLOBBER || GET_CODE (varop) == CONST_INT)
6852 /* See what bits may be nonzero in VAROP. Unlike the general case of
6853 a call to nonzero_bits, here we don't care about bits outside
6856 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
6858 /* If this would be an entire word for the target, but is not for
6859 the host, then sign-extend on the host so that the number will look
6860 the same way on the host that it would on the target.
6862 For example, when building a 64 bit alpha hosted 32 bit sparc
6863 targeted compiler, then we want the 32 bit unsigned value -1 to be
6864 represented as a 64 bit value -1, and not as 0x00000000ffffffff.
6865 The later confuses the sparc backend. */
6867 if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT && BITS_PER_WORD == width
6868 && (nonzero & ((HOST_WIDE_INT) 1 << (width - 1))))
6869 nonzero |= ((HOST_WIDE_INT) (-1) << width);
6871 /* Turn off all bits in the constant that are known to already be zero.
6872 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
6873 which is tested below. */
6877 /* If we don't have any bits left, return zero. */
6881 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
6882 a power of two, we can replace this with a ASHIFT. */
6883 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
6884 && (i = exact_log2 (constop)) >= 0)
6885 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
6887 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
6888 or XOR, then try to apply the distributive law. This may eliminate
6889 operations if either branch can be simplified because of the AND.
6890 It may also make some cases more complex, but those cases probably
6891 won't match a pattern either with or without this. */
6893 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
6895 gen_lowpart_for_combine
6897 apply_distributive_law
6898 (gen_binary (GET_CODE (varop), GET_MODE (varop),
6899 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
6900 XEXP (varop, 0), constop),
6901 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
6902 XEXP (varop, 1), constop))));
6904 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
6905 if we already had one (just check for the simplest cases). */
6906 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
6907 && GET_MODE (XEXP (x, 0)) == mode
6908 && SUBREG_REG (XEXP (x, 0)) == varop)
6909 varop = XEXP (x, 0);
6911 varop = gen_lowpart_for_combine (mode, varop);
6913 /* If we can't make the SUBREG, try to return what we were given. */
6914 if (GET_CODE (varop) == CLOBBER)
6915 return x ? x : varop;
6917 /* If we are only masking insignificant bits, return VAROP. */
6918 if (constop == nonzero)
6921 /* Otherwise, return an AND. See how much, if any, of X we can use. */
6922 else if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
6923 x = gen_binary (AND, mode, varop, GEN_INT (constop));
6927 if (GET_CODE (XEXP (x, 1)) != CONST_INT
6928 || INTVAL (XEXP (x, 1)) != constop)
6929 SUBST (XEXP (x, 1), GEN_INT (constop));
6931 SUBST (XEXP (x, 0), varop);
6937 /* Given an expression, X, compute which bits in X can be non-zero.
6938 We don't care about bits outside of those defined in MODE.
6940 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
6941 a shift, AND, or zero_extract, we can do better. */
6943 static unsigned HOST_WIDE_INT
6944 nonzero_bits (x, mode)
6946 enum machine_mode mode;
6948 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
6949 unsigned HOST_WIDE_INT inner_nz;
6951 int mode_width = GET_MODE_BITSIZE (mode);
6954 /* For floating-point values, assume all bits are needed. */
6955 if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode))
6958 /* If X is wider than MODE, use its mode instead. */
6959 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
6961 mode = GET_MODE (x);
6962 nonzero = GET_MODE_MASK (mode);
6963 mode_width = GET_MODE_BITSIZE (mode);
6966 if (mode_width > HOST_BITS_PER_WIDE_INT)
6967 /* Our only callers in this case look for single bit values. So
6968 just return the mode mask. Those tests will then be false. */
6971 #ifndef WORD_REGISTER_OPERATIONS
6972 /* If MODE is wider than X, but both are a single word for both the host
6973 and target machines, we can compute this from which bits of the
6974 object might be nonzero in its own mode, taking into account the fact
6975 that on many CISC machines, accessing an object in a wider mode
6976 causes the high-order bits to become undefined. So they are
6977 not known to be zero. */
6979 if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
6980 && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD
6981 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6982 && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x)))
6984 nonzero &= nonzero_bits (x, GET_MODE (x));
6985 nonzero |= GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x));
6990 code = GET_CODE (x);
6994 #ifdef POINTERS_EXTEND_UNSIGNED
6995 /* If pointers extend unsigned and this is a pointer in Pmode, say that
6996 all the bits above ptr_mode are known to be zero. */
6997 if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
6998 && REGNO_POINTER_FLAG (REGNO (x)))
6999 nonzero &= GET_MODE_MASK (ptr_mode);
7002 #ifdef STACK_BOUNDARY
7003 /* If this is the stack pointer, we may know something about its
7004 alignment. If PUSH_ROUNDING is defined, it is possible for the
7005 stack to be momentarily aligned only to that amount, so we pick
7006 the least alignment. */
7008 /* We can't check for arg_pointer_rtx here, because it is not
7009 guaranteed to have as much alignment as the stack pointer.
7010 In particular, in the Irix6 n64 ABI, the stack has 128 bit
7011 alignment but the argument pointer has only 64 bit alignment. */
7013 if (x == stack_pointer_rtx || x == frame_pointer_rtx
7014 || x == hard_frame_pointer_rtx
7015 || (REGNO (x) >= FIRST_VIRTUAL_REGISTER
7016 && REGNO (x) <= LAST_VIRTUAL_REGISTER))
7018 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
7020 #ifdef PUSH_ROUNDING
7021 if (REGNO (x) == STACK_POINTER_REGNUM)
7022 sp_alignment = MIN (PUSH_ROUNDING (1), sp_alignment);
7025 /* We must return here, otherwise we may get a worse result from
7026 one of the choices below. There is nothing useful below as
7027 far as the stack pointer is concerned. */
7028 return nonzero &= ~ (sp_alignment - 1);
7032 /* If X is a register whose nonzero bits value is current, use it.
7033 Otherwise, if X is a register whose value we can find, use that
7034 value. Otherwise, use the previously-computed global nonzero bits
7035 for this register. */
7037 if (reg_last_set_value[REGNO (x)] != 0
7038 && reg_last_set_mode[REGNO (x)] == mode
7039 && (reg_n_sets[REGNO (x)] == 1
7040 || reg_last_set_label[REGNO (x)] == label_tick)
7041 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
7042 return reg_last_set_nonzero_bits[REGNO (x)];
7044 tem = get_last_value (x);
7048 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7049 /* If X is narrower than MODE and TEM is a non-negative
7050 constant that would appear negative in the mode of X,
7051 sign-extend it for use in reg_nonzero_bits because some
7052 machines (maybe most) will actually do the sign-extension
7053 and this is the conservative approach.
7055 ??? For 2.5, try to tighten up the MD files in this regard
7056 instead of this kludge. */
7058 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width
7059 && GET_CODE (tem) == CONST_INT
7061 && 0 != (INTVAL (tem)
7062 & ((HOST_WIDE_INT) 1
7063 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7064 tem = GEN_INT (INTVAL (tem)
7065 | ((HOST_WIDE_INT) (-1)
7066 << GET_MODE_BITSIZE (GET_MODE (x))));
7068 return nonzero_bits (tem, mode);
7070 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
7071 return reg_nonzero_bits[REGNO (x)] & nonzero;
7076 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7077 /* If X is negative in MODE, sign-extend the value. */
7078 if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD
7079 && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1))))
7080 return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width));
7086 #ifdef LOAD_EXTEND_OP
7087 /* In many, if not most, RISC machines, reading a byte from memory
7088 zeros the rest of the register. Noticing that fact saves a lot
7089 of extra zero-extends. */
7090 if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND)
7091 nonzero &= GET_MODE_MASK (GET_MODE (x));
7101 /* If this produces an integer result, we know which bits are set.
7102 Code here used to clear bits outside the mode of X, but that is
7105 if (GET_MODE_CLASS (mode) == MODE_INT
7106 && mode_width <= HOST_BITS_PER_WIDE_INT)
7107 nonzero = STORE_FLAG_VALUE;
7111 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
7112 == GET_MODE_BITSIZE (GET_MODE (x)))
7115 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
7116 nonzero |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x)));
7120 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
7121 == GET_MODE_BITSIZE (GET_MODE (x)))
7126 nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode));
7130 nonzero &= nonzero_bits (XEXP (x, 0), mode);
7131 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
7132 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
7136 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
7137 Otherwise, show all the bits in the outer mode but not the inner
7139 inner_nz = nonzero_bits (XEXP (x, 0), mode);
7140 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
7142 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
7145 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
7146 inner_nz |= (GET_MODE_MASK (mode)
7147 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
7150 nonzero &= inner_nz;
7154 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
7155 & nonzero_bits (XEXP (x, 1), mode));
7159 case UMIN: case UMAX: case SMIN: case SMAX:
7160 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
7161 | nonzero_bits (XEXP (x, 1), mode));
7164 case PLUS: case MINUS:
7166 case DIV: case UDIV:
7167 case MOD: case UMOD:
7168 /* We can apply the rules of arithmetic to compute the number of
7169 high- and low-order zero bits of these operations. We start by
7170 computing the width (position of the highest-order non-zero bit)
7171 and the number of low-order zero bits for each value. */
7173 unsigned HOST_WIDE_INT nz0 = nonzero_bits (XEXP (x, 0), mode);
7174 unsigned HOST_WIDE_INT nz1 = nonzero_bits (XEXP (x, 1), mode);
7175 int width0 = floor_log2 (nz0) + 1;
7176 int width1 = floor_log2 (nz1) + 1;
7177 int low0 = floor_log2 (nz0 & -nz0);
7178 int low1 = floor_log2 (nz1 & -nz1);
7179 HOST_WIDE_INT op0_maybe_minusp
7180 = (nz0 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
7181 HOST_WIDE_INT op1_maybe_minusp
7182 = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
7183 int result_width = mode_width;
7189 result_width = MAX (width0, width1) + 1;
7190 result_low = MIN (low0, low1);
7193 result_low = MIN (low0, low1);
7196 result_width = width0 + width1;
7197 result_low = low0 + low1;
7200 if (! op0_maybe_minusp && ! op1_maybe_minusp)
7201 result_width = width0;
7204 result_width = width0;
7207 if (! op0_maybe_minusp && ! op1_maybe_minusp)
7208 result_width = MIN (width0, width1);
7209 result_low = MIN (low0, low1);
7212 result_width = MIN (width0, width1);
7213 result_low = MIN (low0, low1);
7217 if (result_width < mode_width)
7218 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
7221 nonzero &= ~ (((HOST_WIDE_INT) 1 << result_low) - 1);
7226 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7227 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7228 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
7232 /* If this is a SUBREG formed for a promoted variable that has
7233 been zero-extended, we know that at least the high-order bits
7234 are zero, though others might be too. */
7236 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x))
7237 nonzero = (GET_MODE_MASK (GET_MODE (x))
7238 & nonzero_bits (SUBREG_REG (x), GET_MODE (x)));
7240 /* If the inner mode is a single word for both the host and target
7241 machines, we can compute this from which bits of the inner
7242 object might be nonzero. */
7243 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
7244 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
7245 <= HOST_BITS_PER_WIDE_INT))
7247 nonzero &= nonzero_bits (SUBREG_REG (x), mode);
7249 #ifndef WORD_REGISTER_OPERATIONS
7250 /* On many CISC machines, accessing an object in a wider mode
7251 causes the high-order bits to become undefined. So they are
7252 not known to be zero. */
7253 if (GET_MODE_SIZE (GET_MODE (x))
7254 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7255 nonzero |= (GET_MODE_MASK (GET_MODE (x))
7256 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
7265 /* The nonzero bits are in two classes: any bits within MODE
7266 that aren't in GET_MODE (x) are always significant. The rest of the
7267 nonzero bits are those that are significant in the operand of
7268 the shift when shifted the appropriate number of bits. This
7269 shows that high-order bits are cleared by the right shift and
7270 low-order bits by left shifts. */
7271 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7272 && INTVAL (XEXP (x, 1)) >= 0
7273 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7275 enum machine_mode inner_mode = GET_MODE (x);
7276 int width = GET_MODE_BITSIZE (inner_mode);
7277 int count = INTVAL (XEXP (x, 1));
7278 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
7279 unsigned HOST_WIDE_INT op_nonzero = nonzero_bits (XEXP (x, 0), mode);
7280 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
7281 unsigned HOST_WIDE_INT outer = 0;
7283 if (mode_width > width)
7284 outer = (op_nonzero & nonzero & ~ mode_mask);
7286 if (code == LSHIFTRT)
7288 else if (code == ASHIFTRT)
7292 /* If the sign bit may have been nonzero before the shift, we
7293 need to mark all the places it could have been copied to
7294 by the shift as possibly nonzero. */
7295 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
7296 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
7298 else if (code == ASHIFT)
7301 inner = ((inner << (count % width)
7302 | (inner >> (width - (count % width)))) & mode_mask);
7304 nonzero &= (outer | inner);
7309 /* This is at most the number of bits in the mode. */
7310 nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1;
7314 nonzero &= (nonzero_bits (XEXP (x, 1), mode)
7315 | nonzero_bits (XEXP (x, 2), mode));
7322 /* Return the number of bits at the high-order end of X that are known to
7323 be equal to the sign bit. X will be used in mode MODE; if MODE is
7324 VOIDmode, X will be used in its own mode. The returned value will always
7325 be between 1 and the number of bits in MODE. */
7328 num_sign_bit_copies (x, mode)
7330 enum machine_mode mode;
7332 enum rtx_code code = GET_CODE (x);
7334 int num0, num1, result;
7335 unsigned HOST_WIDE_INT nonzero;
7338 /* If we weren't given a mode, use the mode of X. If the mode is still
7339 VOIDmode, we don't know anything. Likewise if one of the modes is
7342 if (mode == VOIDmode)
7343 mode = GET_MODE (x);
7345 if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)))
7348 bitwidth = GET_MODE_BITSIZE (mode);
7350 /* For a smaller object, just ignore the high bits. */
7351 if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
7352 return MAX (1, (num_sign_bit_copies (x, GET_MODE (x))
7353 - (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth)));
7355 #ifndef WORD_REGISTER_OPERATIONS
7356 /* If this machine does not do all register operations on the entire
7357 register and MODE is wider than the mode of X, we can say nothing
7358 at all about the high-order bits. */
7359 if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x)))
7367 #ifdef POINTERS_EXTEND_UNSIGNED
7368 /* If pointers extend signed and this is a pointer in Pmode, say that
7369 all the bits above ptr_mode are known to be sign bit copies. */
7370 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
7371 && REGNO_POINTER_FLAG (REGNO (x)))
7372 return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1;
7375 if (reg_last_set_value[REGNO (x)] != 0
7376 && reg_last_set_mode[REGNO (x)] == mode
7377 && (reg_n_sets[REGNO (x)] == 1
7378 || reg_last_set_label[REGNO (x)] == label_tick)
7379 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
7380 return reg_last_set_sign_bit_copies[REGNO (x)];
7382 tem = get_last_value (x);
7384 return num_sign_bit_copies (tem, mode);
7386 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0)
7387 return reg_sign_bit_copies[REGNO (x)];
7391 #ifdef LOAD_EXTEND_OP
7392 /* Some RISC machines sign-extend all loads of smaller than a word. */
7393 if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
7394 return MAX (1, bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1);
7399 /* If the constant is negative, take its 1's complement and remask.
7400 Then see how many zero bits we have. */
7401 nonzero = INTVAL (x) & GET_MODE_MASK (mode);
7402 if (bitwidth <= HOST_BITS_PER_WIDE_INT
7403 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7404 nonzero = (~ nonzero) & GET_MODE_MASK (mode);
7406 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
7409 /* If this is a SUBREG for a promoted object that is sign-extended
7410 and we are looking at it in a wider mode, we know that at least the
7411 high-order bits are known to be sign bit copies. */
7413 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
7414 return MAX (bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1,
7415 num_sign_bit_copies (SUBREG_REG (x), mode));
7417 /* For a smaller object, just ignore the high bits. */
7418 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
7420 num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode);
7421 return MAX (1, (num0
7422 - (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
7426 #ifdef WORD_REGISTER_OPERATIONS
7427 #ifdef LOAD_EXTEND_OP
7428 /* For paradoxical SUBREGs on machines where all register operations
7429 affect the entire register, just look inside. Note that we are
7430 passing MODE to the recursive call, so the number of sign bit copies
7431 will remain relative to that mode, not the inner mode. */
7433 /* This works only if loads sign extend. Otherwise, if we get a
7434 reload for the inner part, it may be loaded from the stack, and
7435 then we lose all sign bit copies that existed before the store
7438 if ((GET_MODE_SIZE (GET_MODE (x))
7439 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7440 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND)
7441 return num_sign_bit_copies (SUBREG_REG (x), mode);
7447 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
7448 return MAX (1, bitwidth - INTVAL (XEXP (x, 1)));
7452 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
7453 + num_sign_bit_copies (XEXP (x, 0), VOIDmode));
7456 /* For a smaller object, just ignore the high bits. */
7457 num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode);
7458 return MAX (1, (num0 - (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
7462 return num_sign_bit_copies (XEXP (x, 0), mode);
7464 case ROTATE: case ROTATERT:
7465 /* If we are rotating left by a number of bits less than the number
7466 of sign bit copies, we can just subtract that amount from the
7468 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7469 && INTVAL (XEXP (x, 1)) >= 0 && INTVAL (XEXP (x, 1)) < bitwidth)
7471 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7472 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
7473 : bitwidth - INTVAL (XEXP (x, 1))));
7478 /* In general, this subtracts one sign bit copy. But if the value
7479 is known to be positive, the number of sign bit copies is the
7480 same as that of the input. Finally, if the input has just one bit
7481 that might be nonzero, all the bits are copies of the sign bit. */
7482 nonzero = nonzero_bits (XEXP (x, 0), mode);
7486 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7488 && bitwidth <= HOST_BITS_PER_WIDE_INT
7489 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
7494 case IOR: case AND: case XOR:
7495 case SMIN: case SMAX: case UMIN: case UMAX:
7496 /* Logical operations will preserve the number of sign-bit copies.
7497 MIN and MAX operations always return one of the operands. */
7498 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7499 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
7500 return MIN (num0, num1);
7502 case PLUS: case MINUS:
7503 /* For addition and subtraction, we can have a 1-bit carry. However,
7504 if we are subtracting 1 from a positive number, there will not
7505 be such a carry. Furthermore, if the positive number is known to
7506 be 0 or 1, we know the result is either -1 or 0. */
7508 if (code == PLUS && XEXP (x, 1) == constm1_rtx
7509 && bitwidth <= HOST_BITS_PER_WIDE_INT)
7511 nonzero = nonzero_bits (XEXP (x, 0), mode);
7512 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
7513 return (nonzero == 1 || nonzero == 0 ? bitwidth
7514 : bitwidth - floor_log2 (nonzero) - 1);
7517 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7518 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
7519 return MAX (1, MIN (num0, num1) - 1);
7522 /* The number of bits of the product is the sum of the number of
7523 bits of both terms. However, unless one of the terms if known
7524 to be positive, we must allow for an additional bit since negating
7525 a negative number can remove one sign bit copy. */
7527 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7528 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
7530 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
7532 && bitwidth <= HOST_BITS_PER_WIDE_INT
7533 && ((nonzero_bits (XEXP (x, 0), mode)
7534 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7535 && ((nonzero_bits (XEXP (x, 1), mode)
7536 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
7539 return MAX (1, result);
7542 /* The result must be <= the first operand. */
7543 return num_sign_bit_copies (XEXP (x, 0), mode);
7546 /* The result must be <= the scond operand. */
7547 return num_sign_bit_copies (XEXP (x, 1), mode);
7550 /* Similar to unsigned division, except that we have to worry about
7551 the case where the divisor is negative, in which case we have
7553 result = num_sign_bit_copies (XEXP (x, 0), mode);
7555 && bitwidth <= HOST_BITS_PER_WIDE_INT
7556 && (nonzero_bits (XEXP (x, 1), mode)
7557 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7563 result = num_sign_bit_copies (XEXP (x, 1), mode);
7565 && bitwidth <= HOST_BITS_PER_WIDE_INT
7566 && (nonzero_bits (XEXP (x, 1), mode)
7567 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7573 /* Shifts by a constant add to the number of bits equal to the
7575 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7576 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7577 && INTVAL (XEXP (x, 1)) > 0)
7578 num0 = MIN (bitwidth, num0 + INTVAL (XEXP (x, 1)));
7583 /* Left shifts destroy copies. */
7584 if (GET_CODE (XEXP (x, 1)) != CONST_INT
7585 || INTVAL (XEXP (x, 1)) < 0
7586 || INTVAL (XEXP (x, 1)) >= bitwidth)
7589 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7590 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
7593 num0 = num_sign_bit_copies (XEXP (x, 1), mode);
7594 num1 = num_sign_bit_copies (XEXP (x, 2), mode);
7595 return MIN (num0, num1);
7597 #if STORE_FLAG_VALUE == -1
7598 case EQ: case NE: case GE: case GT: case LE: case LT:
7599 case GEU: case GTU: case LEU: case LTU:
7604 /* If we haven't been able to figure it out by one of the above rules,
7605 see if some of the high-order bits are known to be zero. If so,
7606 count those bits and return one less than that amount. If we can't
7607 safely compute the mask for this mode, always return BITWIDTH. */
7609 if (bitwidth > HOST_BITS_PER_WIDE_INT)
7612 nonzero = nonzero_bits (x, mode);
7613 return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
7614 ? 1 : bitwidth - floor_log2 (nonzero) - 1);
7617 /* Return the number of "extended" bits there are in X, when interpreted
7618 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
7619 unsigned quantities, this is the number of high-order zero bits.
7620 For signed quantities, this is the number of copies of the sign bit
7621 minus 1. In both case, this function returns the number of "spare"
7622 bits. For example, if two quantities for which this function returns
7623 at least 1 are added, the addition is known not to overflow.
7625 This function will always return 0 unless called during combine, which
7626 implies that it must be called from a define_split. */
7629 extended_count (x, mode, unsignedp)
7631 enum machine_mode mode;
7634 if (nonzero_sign_valid == 0)
7638 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7639 && (GET_MODE_BITSIZE (mode) - 1
7640 - floor_log2 (nonzero_bits (x, mode))))
7641 : num_sign_bit_copies (x, mode) - 1);
7644 /* This function is called from `simplify_shift_const' to merge two
7645 outer operations. Specifically, we have already found that we need
7646 to perform operation *POP0 with constant *PCONST0 at the outermost
7647 position. We would now like to also perform OP1 with constant CONST1
7648 (with *POP0 being done last).
7650 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
7651 the resulting operation. *PCOMP_P is set to 1 if we would need to
7652 complement the innermost operand, otherwise it is unchanged.
7654 MODE is the mode in which the operation will be done. No bits outside
7655 the width of this mode matter. It is assumed that the width of this mode
7656 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
7658 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
7659 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
7660 result is simply *PCONST0.
7662 If the resulting operation cannot be expressed as one operation, we
7663 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
7666 merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
7667 enum rtx_code *pop0;
7668 HOST_WIDE_INT *pconst0;
7670 HOST_WIDE_INT const1;
7671 enum machine_mode mode;
7674 enum rtx_code op0 = *pop0;
7675 HOST_WIDE_INT const0 = *pconst0;
7676 int width = GET_MODE_BITSIZE (mode);
7678 const0 &= GET_MODE_MASK (mode);
7679 const1 &= GET_MODE_MASK (mode);
7681 /* If OP0 is an AND, clear unimportant bits in CONST1. */
7685 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
7688 if (op1 == NIL || op0 == SET)
7691 else if (op0 == NIL)
7692 op0 = op1, const0 = const1;
7694 else if (op0 == op1)
7716 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
7717 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
7720 /* If the two constants aren't the same, we can't do anything. The
7721 remaining six cases can all be done. */
7722 else if (const0 != const1)
7730 /* (a & b) | b == b */
7732 else /* op1 == XOR */
7733 /* (a ^ b) | b == a | b */
7739 /* (a & b) ^ b == (~a) & b */
7740 op0 = AND, *pcomp_p = 1;
7741 else /* op1 == IOR */
7742 /* (a | b) ^ b == a & ~b */
7743 op0 = AND, *pconst0 = ~ const0;
7748 /* (a | b) & b == b */
7750 else /* op1 == XOR */
7751 /* (a ^ b) & b) == (~a) & b */
7756 /* Check for NO-OP cases. */
7757 const0 &= GET_MODE_MASK (mode);
7759 && (op0 == IOR || op0 == XOR || op0 == PLUS))
7761 else if (const0 == 0 && op0 == AND)
7763 else if (const0 == GET_MODE_MASK (mode) && op0 == AND)
7766 /* If this would be an entire word for the target, but is not for
7767 the host, then sign-extend on the host so that the number will look
7768 the same way on the host that it would on the target.
7770 For example, when building a 64 bit alpha hosted 32 bit sparc
7771 targeted compiler, then we want the 32 bit unsigned value -1 to be
7772 represented as a 64 bit value -1, and not as 0x00000000ffffffff.
7773 The later confuses the sparc backend. */
7775 if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT && BITS_PER_WORD == width
7776 && (const0 & ((HOST_WIDE_INT) 1 << (width - 1))))
7777 const0 |= ((HOST_WIDE_INT) (-1) << width);
7785 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
7786 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
7787 that we started with.
7789 The shift is normally computed in the widest mode we find in VAROP, as
7790 long as it isn't a different number of words than RESULT_MODE. Exceptions
7791 are ASHIFTRT and ROTATE, which are always done in their original mode, */
7794 simplify_shift_const (x, code, result_mode, varop, count)
7797 enum machine_mode result_mode;
7801 enum rtx_code orig_code = code;
7802 int orig_count = count;
7803 enum machine_mode mode = result_mode;
7804 enum machine_mode shift_mode, tmode;
7806 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
7807 /* We form (outer_op (code varop count) (outer_const)). */
7808 enum rtx_code outer_op = NIL;
7809 HOST_WIDE_INT outer_const = 0;
7811 int complement_p = 0;
7814 /* If we were given an invalid count, don't do anything except exactly
7815 what was requested. */
7817 if (count < 0 || count > GET_MODE_BITSIZE (mode))
7822 return gen_rtx (code, mode, varop, GEN_INT (count));
7825 /* Unless one of the branches of the `if' in this loop does a `continue',
7826 we will `break' the loop after the `if'. */
7830 /* If we have an operand of (clobber (const_int 0)), just return that
7832 if (GET_CODE (varop) == CLOBBER)
7835 /* If we discovered we had to complement VAROP, leave. Making a NOT
7836 here would cause an infinite loop. */
7840 /* Convert ROTATERT to ROTATE. */
7841 if (code == ROTATERT)
7842 code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count;
7844 /* We need to determine what mode we will do the shift in. If the
7845 shift is a right shift or a ROTATE, we must always do it in the mode
7846 it was originally done in. Otherwise, we can do it in MODE, the
7847 widest mode encountered. */
7849 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
7850 ? result_mode : mode);
7852 /* Handle cases where the count is greater than the size of the mode
7853 minus 1. For ASHIFT, use the size minus one as the count (this can
7854 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
7855 take the count modulo the size. For other shifts, the result is
7858 Since these shifts are being produced by the compiler by combining
7859 multiple operations, each of which are defined, we know what the
7860 result is supposed to be. */
7862 if (count > GET_MODE_BITSIZE (shift_mode) - 1)
7864 if (code == ASHIFTRT)
7865 count = GET_MODE_BITSIZE (shift_mode) - 1;
7866 else if (code == ROTATE || code == ROTATERT)
7867 count %= GET_MODE_BITSIZE (shift_mode);
7870 /* We can't simply return zero because there may be an
7878 /* Negative counts are invalid and should not have been made (a
7879 programmer-specified negative count should have been handled
7884 /* An arithmetic right shift of a quantity known to be -1 or 0
7886 if (code == ASHIFTRT
7887 && (num_sign_bit_copies (varop, shift_mode)
7888 == GET_MODE_BITSIZE (shift_mode)))
7894 /* If we are doing an arithmetic right shift and discarding all but
7895 the sign bit copies, this is equivalent to doing a shift by the
7896 bitsize minus one. Convert it into that shift because it will often
7897 allow other simplifications. */
7899 if (code == ASHIFTRT
7900 && (count + num_sign_bit_copies (varop, shift_mode)
7901 >= GET_MODE_BITSIZE (shift_mode)))
7902 count = GET_MODE_BITSIZE (shift_mode) - 1;
7904 /* We simplify the tests below and elsewhere by converting
7905 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
7906 `make_compound_operation' will convert it to a ASHIFTRT for
7907 those machines (such as Vax) that don't have a LSHIFTRT. */
7908 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
7910 && ((nonzero_bits (varop, shift_mode)
7911 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
7915 switch (GET_CODE (varop))
7921 new = expand_compound_operation (varop);
7930 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
7931 minus the width of a smaller mode, we can do this with a
7932 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
7933 if ((code == ASHIFTRT || code == LSHIFTRT)
7934 && ! mode_dependent_address_p (XEXP (varop, 0))
7935 && ! MEM_VOLATILE_P (varop)
7936 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
7937 MODE_INT, 1)) != BLKmode)
7939 if (BYTES_BIG_ENDIAN)
7940 new = gen_rtx (MEM, tmode, XEXP (varop, 0));
7942 new = gen_rtx (MEM, tmode,
7943 plus_constant (XEXP (varop, 0),
7944 count / BITS_PER_UNIT));
7945 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (varop);
7946 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (varop);
7947 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (varop);
7948 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
7949 : ZERO_EXTEND, mode, new);
7956 /* Similar to the case above, except that we can only do this if
7957 the resulting mode is the same as that of the underlying
7958 MEM and adjust the address depending on the *bits* endianness
7959 because of the way that bit-field extract insns are defined. */
7960 if ((code == ASHIFTRT || code == LSHIFTRT)
7961 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
7962 MODE_INT, 1)) != BLKmode
7963 && tmode == GET_MODE (XEXP (varop, 0)))
7965 if (BITS_BIG_ENDIAN)
7966 new = XEXP (varop, 0);
7969 new = copy_rtx (XEXP (varop, 0));
7970 SUBST (XEXP (new, 0),
7971 plus_constant (XEXP (new, 0),
7972 count / BITS_PER_UNIT));
7975 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
7976 : ZERO_EXTEND, mode, new);
7983 /* If VAROP is a SUBREG, strip it as long as the inner operand has
7984 the same number of words as what we've seen so far. Then store
7985 the widest mode in MODE. */
7986 if (subreg_lowpart_p (varop)
7987 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
7988 > GET_MODE_SIZE (GET_MODE (varop)))
7989 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
7990 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
7993 varop = SUBREG_REG (varop);
7994 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
7995 mode = GET_MODE (varop);
8001 /* Some machines use MULT instead of ASHIFT because MULT
8002 is cheaper. But it is still better on those machines to
8003 merge two shifts into one. */
8004 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8005 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8007 varop = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
8008 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));;
8014 /* Similar, for when divides are cheaper. */
8015 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8016 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8018 varop = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
8019 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
8025 /* If we are extracting just the sign bit of an arithmetic right
8026 shift, that shift is not needed. */
8027 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1)
8029 varop = XEXP (varop, 0);
8033 /* ... fall through ... */
8038 /* Here we have two nested shifts. The result is usually the
8039 AND of a new shift with a mask. We compute the result below. */
8040 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8041 && INTVAL (XEXP (varop, 1)) >= 0
8042 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
8043 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8044 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
8046 enum rtx_code first_code = GET_CODE (varop);
8047 int first_count = INTVAL (XEXP (varop, 1));
8048 unsigned HOST_WIDE_INT mask;
8051 /* We have one common special case. We can't do any merging if
8052 the inner code is an ASHIFTRT of a smaller mode. However, if
8053 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8054 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8055 we can convert it to
8056 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8057 This simplifies certain SIGN_EXTEND operations. */
8058 if (code == ASHIFT && first_code == ASHIFTRT
8059 && (GET_MODE_BITSIZE (result_mode)
8060 - GET_MODE_BITSIZE (GET_MODE (varop))) == count)
8062 /* C3 has the low-order C1 bits zero. */
8064 mask = (GET_MODE_MASK (mode)
8065 & ~ (((HOST_WIDE_INT) 1 << first_count) - 1));
8067 varop = simplify_and_const_int (NULL_RTX, result_mode,
8068 XEXP (varop, 0), mask);
8069 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
8071 count = first_count;
8076 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8077 than C1 high-order bits equal to the sign bit, we can convert
8078 this to either an ASHIFT or a ASHIFTRT depending on the
8081 We cannot do this if VAROP's mode is not SHIFT_MODE. */
8083 if (code == ASHIFTRT && first_code == ASHIFT
8084 && GET_MODE (varop) == shift_mode
8085 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
8088 count -= first_count;
8090 count = - count, code = ASHIFT;
8091 varop = XEXP (varop, 0);
8095 /* There are some cases we can't do. If CODE is ASHIFTRT,
8096 we can only do this if FIRST_CODE is also ASHIFTRT.
8098 We can't do the case when CODE is ROTATE and FIRST_CODE is
8101 If the mode of this shift is not the mode of the outer shift,
8102 we can't do this if either shift is a right shift or ROTATE.
8104 Finally, we can't do any of these if the mode is too wide
8105 unless the codes are the same.
8107 Handle the case where the shift codes are the same
8110 if (code == first_code)
8112 if (GET_MODE (varop) != result_mode
8113 && (code == ASHIFTRT || code == LSHIFTRT
8117 count += first_count;
8118 varop = XEXP (varop, 0);
8122 if (code == ASHIFTRT
8123 || (code == ROTATE && first_code == ASHIFTRT)
8124 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
8125 || (GET_MODE (varop) != result_mode
8126 && (first_code == ASHIFTRT || first_code == LSHIFTRT
8127 || first_code == ROTATE
8128 || code == ROTATE)))
8131 /* To compute the mask to apply after the shift, shift the
8132 nonzero bits of the inner shift the same way the
8133 outer shift will. */
8135 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
8138 = simplify_binary_operation (code, result_mode, mask_rtx,
8141 /* Give up if we can't compute an outer operation to use. */
8143 || GET_CODE (mask_rtx) != CONST_INT
8144 || ! merge_outer_ops (&outer_op, &outer_const, AND,
8146 result_mode, &complement_p))
8149 /* If the shifts are in the same direction, we add the
8150 counts. Otherwise, we subtract them. */
8151 if ((code == ASHIFTRT || code == LSHIFTRT)
8152 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
8153 count += first_count;
8155 count -= first_count;
8157 /* If COUNT is positive, the new shift is usually CODE,
8158 except for the two exceptions below, in which case it is
8159 FIRST_CODE. If the count is negative, FIRST_CODE should
8162 && ((first_code == ROTATE && code == ASHIFT)
8163 || (first_code == ASHIFTRT && code == LSHIFTRT)))
8166 code = first_code, count = - count;
8168 varop = XEXP (varop, 0);
8172 /* If we have (A << B << C) for any shift, we can convert this to
8173 (A << C << B). This wins if A is a constant. Only try this if
8174 B is not a constant. */
8176 else if (GET_CODE (varop) == code
8177 && GET_CODE (XEXP (varop, 1)) != CONST_INT
8179 = simplify_binary_operation (code, mode,
8183 varop = gen_rtx_combine (code, mode, new, XEXP (varop, 1));
8190 /* Make this fit the case below. */
8191 varop = gen_rtx_combine (XOR, mode, XEXP (varop, 0),
8192 GEN_INT (GET_MODE_MASK (mode)));
8198 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
8199 with C the size of VAROP - 1 and the shift is logical if
8200 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8201 we have an (le X 0) operation. If we have an arithmetic shift
8202 and STORE_FLAG_VALUE is 1 or we have a logical shift with
8203 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
8205 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
8206 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
8207 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8208 && (code == LSHIFTRT || code == ASHIFTRT)
8209 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
8210 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8213 varop = gen_rtx_combine (LE, GET_MODE (varop), XEXP (varop, 1),
8216 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8217 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
8222 /* If we have (shift (logical)), move the logical to the outside
8223 to allow it to possibly combine with another logical and the
8224 shift to combine with another shift. This also canonicalizes to
8225 what a ZERO_EXTRACT looks like. Also, some machines have
8226 (and (shift)) insns. */
8228 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8229 && (new = simplify_binary_operation (code, result_mode,
8231 GEN_INT (count))) != 0
8232 && GET_CODE(new) == CONST_INT
8233 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
8234 INTVAL (new), result_mode, &complement_p))
8236 varop = XEXP (varop, 0);
8240 /* If we can't do that, try to simplify the shift in each arm of the
8241 logical expression, make a new logical expression, and apply
8242 the inverse distributive law. */
8244 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8245 XEXP (varop, 0), count);
8246 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8247 XEXP (varop, 1), count);
8249 varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
8250 varop = apply_distributive_law (varop);
8257 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
8258 says that the sign bit can be tested, FOO has mode MODE, C is
8259 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
8260 that may be nonzero. */
8261 if (code == LSHIFTRT
8262 && XEXP (varop, 1) == const0_rtx
8263 && GET_MODE (XEXP (varop, 0)) == result_mode
8264 && count == GET_MODE_BITSIZE (result_mode) - 1
8265 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8266 && ((STORE_FLAG_VALUE
8267 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (result_mode) - 1))))
8268 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
8269 && merge_outer_ops (&outer_op, &outer_const, XOR,
8270 (HOST_WIDE_INT) 1, result_mode,
8273 varop = XEXP (varop, 0);
8280 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
8281 than the number of bits in the mode is equivalent to A. */
8282 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
8283 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
8285 varop = XEXP (varop, 0);
8290 /* NEG commutes with ASHIFT since it is multiplication. Move the
8291 NEG outside to allow shifts to combine. */
8293 && merge_outer_ops (&outer_op, &outer_const, NEG,
8294 (HOST_WIDE_INT) 0, result_mode,
8297 varop = XEXP (varop, 0);
8303 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
8304 is one less than the number of bits in the mode is
8305 equivalent to (xor A 1). */
8306 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
8307 && XEXP (varop, 1) == constm1_rtx
8308 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
8309 && merge_outer_ops (&outer_op, &outer_const, XOR,
8310 (HOST_WIDE_INT) 1, result_mode,
8314 varop = XEXP (varop, 0);
8318 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
8319 that might be nonzero in BAR are those being shifted out and those
8320 bits are known zero in FOO, we can replace the PLUS with FOO.
8321 Similarly in the other operand order. This code occurs when
8322 we are computing the size of a variable-size array. */
8324 if ((code == ASHIFTRT || code == LSHIFTRT)
8325 && count < HOST_BITS_PER_WIDE_INT
8326 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
8327 && (nonzero_bits (XEXP (varop, 1), result_mode)
8328 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
8330 varop = XEXP (varop, 0);
8333 else if ((code == ASHIFTRT || code == LSHIFTRT)
8334 && count < HOST_BITS_PER_WIDE_INT
8335 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8336 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
8338 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
8339 & nonzero_bits (XEXP (varop, 1),
8342 varop = XEXP (varop, 1);
8346 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
8348 && GET_CODE (XEXP (varop, 1)) == CONST_INT
8349 && (new = simplify_binary_operation (ASHIFT, result_mode,
8351 GEN_INT (count))) != 0
8352 && GET_CODE(new) == CONST_INT
8353 && merge_outer_ops (&outer_op, &outer_const, PLUS,
8354 INTVAL (new), result_mode, &complement_p))
8356 varop = XEXP (varop, 0);
8362 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
8363 with C the size of VAROP - 1 and the shift is logical if
8364 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8365 we have a (gt X 0) operation. If the shift is arithmetic with
8366 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
8367 we have a (neg (gt X 0)) operation. */
8369 if (GET_CODE (XEXP (varop, 0)) == ASHIFTRT
8370 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
8371 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8372 && (code == LSHIFTRT || code == ASHIFTRT)
8373 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
8374 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
8375 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8378 varop = gen_rtx_combine (GT, GET_MODE (varop), XEXP (varop, 1),
8381 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8382 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
8392 /* We need to determine what mode to do the shift in. If the shift is
8393 a right shift or ROTATE, we must always do it in the mode it was
8394 originally done in. Otherwise, we can do it in MODE, the widest mode
8395 encountered. The code we care about is that of the shift that will
8396 actually be done, not the shift that was originally requested. */
8398 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8399 ? result_mode : mode);
8401 /* We have now finished analyzing the shift. The result should be
8402 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
8403 OUTER_OP is non-NIL, it is an operation that needs to be applied
8404 to the result of the shift. OUTER_CONST is the relevant constant,
8405 but we must turn off all bits turned off in the shift.
8407 If we were passed a value for X, see if we can use any pieces of
8408 it. If not, make new rtx. */
8410 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
8411 && GET_CODE (XEXP (x, 1)) == CONST_INT
8412 && INTVAL (XEXP (x, 1)) == count)
8413 const_rtx = XEXP (x, 1);
8415 const_rtx = GEN_INT (count);
8417 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
8418 && GET_MODE (XEXP (x, 0)) == shift_mode
8419 && SUBREG_REG (XEXP (x, 0)) == varop)
8420 varop = XEXP (x, 0);
8421 else if (GET_MODE (varop) != shift_mode)
8422 varop = gen_lowpart_for_combine (shift_mode, varop);
8424 /* If we can't make the SUBREG, try to return what we were given. */
8425 if (GET_CODE (varop) == CLOBBER)
8426 return x ? x : varop;
8428 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
8433 if (x == 0 || GET_CODE (x) != code || GET_MODE (x) != shift_mode)
8434 x = gen_rtx_combine (code, shift_mode, varop, const_rtx);
8436 SUBST (XEXP (x, 0), varop);
8437 SUBST (XEXP (x, 1), const_rtx);
8440 /* If we have an outer operation and we just made a shift, it is
8441 possible that we could have simplified the shift were it not
8442 for the outer operation. So try to do the simplification
8445 if (outer_op != NIL && GET_CODE (x) == code
8446 && GET_CODE (XEXP (x, 1)) == CONST_INT)
8447 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
8448 INTVAL (XEXP (x, 1)));
8450 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
8451 turn off all the bits that the shift would have turned off. */
8452 if (orig_code == LSHIFTRT && result_mode != shift_mode)
8453 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
8454 GET_MODE_MASK (result_mode) >> orig_count);
8456 /* Do the remainder of the processing in RESULT_MODE. */
8457 x = gen_lowpart_for_combine (result_mode, x);
8459 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
8462 x = gen_unary (NOT, result_mode, result_mode, x);
8464 if (outer_op != NIL)
8466 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
8468 int width = GET_MODE_BITSIZE (result_mode);
8470 outer_const &= GET_MODE_MASK (result_mode);
8472 /* If this would be an entire word for the target, but is not for
8473 the host, then sign-extend on the host so that the number will
8474 look the same way on the host that it would on the target.
8476 For example, when building a 64 bit alpha hosted 32 bit sparc
8477 targeted compiler, then we want the 32 bit unsigned value -1 to be
8478 represented as a 64 bit value -1, and not as 0x00000000ffffffff.
8479 The later confuses the sparc backend. */
8481 if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT && BITS_PER_WORD == width
8482 && (outer_const & ((HOST_WIDE_INT) 1 << (width - 1))))
8483 outer_const |= ((HOST_WIDE_INT) (-1) << width);
8486 if (outer_op == AND)
8487 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
8488 else if (outer_op == SET)
8489 /* This means that we have determined that the result is
8490 equivalent to a constant. This should be rare. */
8491 x = GEN_INT (outer_const);
8492 else if (GET_RTX_CLASS (outer_op) == '1')
8493 x = gen_unary (outer_op, result_mode, result_mode, x);
8495 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
8501 /* Like recog, but we receive the address of a pointer to a new pattern.
8502 We try to match the rtx that the pointer points to.
8503 If that fails, we may try to modify or replace the pattern,
8504 storing the replacement into the same pointer object.
8506 Modifications include deletion or addition of CLOBBERs.
8508 PNOTES is a pointer to a location where any REG_UNUSED notes added for
8509 the CLOBBERs are placed.
8511 PADDED_SCRATCHES is set to the number of (clobber (scratch)) patterns
8514 The value is the final insn code from the pattern ultimately matched,
8518 recog_for_combine (pnewpat, insn, pnotes, padded_scratches)
8522 int *padded_scratches;
8524 register rtx pat = *pnewpat;
8525 int insn_code_number;
8526 int num_clobbers_to_add = 0;
8530 *padded_scratches = 0;
8532 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
8533 we use to indicate that something didn't match. If we find such a
8534 thing, force rejection. */
8535 if (GET_CODE (pat) == PARALLEL)
8536 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
8537 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
8538 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
8541 /* Is the result of combination a valid instruction? */
8542 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
8544 /* If it isn't, there is the possibility that we previously had an insn
8545 that clobbered some register as a side effect, but the combined
8546 insn doesn't need to do that. So try once more without the clobbers
8547 unless this represents an ASM insn. */
8549 if (insn_code_number < 0 && ! check_asm_operands (pat)
8550 && GET_CODE (pat) == PARALLEL)
8554 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
8555 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
8558 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
8562 SUBST_INT (XVECLEN (pat, 0), pos);
8565 pat = XVECEXP (pat, 0, 0);
8567 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
8570 /* If we had any clobbers to add, make a new pattern than contains
8571 them. Then check to make sure that all of them are dead. */
8572 if (num_clobbers_to_add)
8574 rtx newpat = gen_rtx (PARALLEL, VOIDmode,
8575 gen_rtvec (GET_CODE (pat) == PARALLEL
8576 ? XVECLEN (pat, 0) + num_clobbers_to_add
8577 : num_clobbers_to_add + 1));
8579 if (GET_CODE (pat) == PARALLEL)
8580 for (i = 0; i < XVECLEN (pat, 0); i++)
8581 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
8583 XVECEXP (newpat, 0, 0) = pat;
8585 add_clobbers (newpat, insn_code_number);
8587 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
8588 i < XVECLEN (newpat, 0); i++)
8590 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
8591 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
8593 else if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == SCRATCH)
8594 (*padded_scratches)++;
8595 notes = gen_rtx (EXPR_LIST, REG_UNUSED,
8596 XEXP (XVECEXP (newpat, 0, i), 0), notes);
8604 return insn_code_number;
8607 /* Like gen_lowpart but for use by combine. In combine it is not possible
8608 to create any new pseudoregs. However, it is safe to create
8609 invalid memory addresses, because combine will try to recognize
8610 them and all they will do is make the combine attempt fail.
8612 If for some reason this cannot do its job, an rtx
8613 (clobber (const_int 0)) is returned.
8614 An insn containing that will not be recognized. */
8619 gen_lowpart_for_combine (mode, x)
8620 enum machine_mode mode;
8625 if (GET_MODE (x) == mode)
8628 /* We can only support MODE being wider than a word if X is a
8629 constant integer or has a mode the same size. */
8631 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
8632 && ! ((GET_MODE (x) == VOIDmode
8633 && (GET_CODE (x) == CONST_INT
8634 || GET_CODE (x) == CONST_DOUBLE))
8635 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
8636 return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
8638 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
8639 won't know what to do. So we will strip off the SUBREG here and
8640 process normally. */
8641 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
8644 if (GET_MODE (x) == mode)
8648 result = gen_lowpart_common (mode, x);
8650 && GET_CODE (result) == SUBREG
8651 && GET_CODE (SUBREG_REG (result)) == REG
8652 && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER
8653 && (GET_MODE_SIZE (GET_MODE (result))
8654 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (result)))))
8655 reg_changes_size[REGNO (SUBREG_REG (result))] = 1;
8660 if (GET_CODE (x) == MEM)
8662 register int offset = 0;
8665 /* Refuse to work on a volatile memory ref or one with a mode-dependent
8667 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
8668 return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
8670 /* If we want to refer to something bigger than the original memref,
8671 generate a perverse subreg instead. That will force a reload
8672 of the original memref X. */
8673 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
8674 return gen_rtx (SUBREG, mode, x, 0);
8676 if (WORDS_BIG_ENDIAN)
8677 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
8678 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
8679 if (BYTES_BIG_ENDIAN)
8681 /* Adjust the address so that the address-after-the-data is
8683 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
8684 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
8686 new = gen_rtx (MEM, mode, plus_constant (XEXP (x, 0), offset));
8687 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (x);
8688 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (x);
8689 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (x);
8693 /* If X is a comparison operator, rewrite it in a new mode. This
8694 probably won't match, but may allow further simplifications. */
8695 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
8696 return gen_rtx_combine (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
8698 /* If we couldn't simplify X any other way, just enclose it in a
8699 SUBREG. Normally, this SUBREG won't match, but some patterns may
8700 include an explicit SUBREG or we may simplify it further in combine. */
8705 if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
8706 word = ((GET_MODE_SIZE (GET_MODE (x))
8707 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
8709 return gen_rtx (SUBREG, mode, x, word);
8713 /* Make an rtx expression. This is a subset of gen_rtx and only supports
8714 expressions of 1, 2, or 3 operands, each of which are rtx expressions.
8716 If the identical expression was previously in the insn (in the undobuf),
8717 it will be returned. Only if it is not found will a new expression
8722 gen_rtx_combine VPROTO((enum rtx_code code, enum machine_mode mode, ...))
8726 enum machine_mode mode;
8739 code = va_arg (p, enum rtx_code);
8740 mode = va_arg (p, enum machine_mode);
8743 n_args = GET_RTX_LENGTH (code);
8744 fmt = GET_RTX_FORMAT (code);
8746 if (n_args == 0 || n_args > 3)
8749 /* Get each arg and verify that it is supposed to be an expression. */
8750 for (j = 0; j < n_args; j++)
8755 args[j] = va_arg (p, rtx);
8758 /* See if this is in undobuf. Be sure we don't use objects that came
8759 from another insn; this could produce circular rtl structures. */
8761 for (undo = undobuf.undos; undo != undobuf.previous_undos; undo = undo->next)
8763 && GET_CODE (undo->old_contents.r) == code
8764 && GET_MODE (undo->old_contents.r) == mode)
8766 for (j = 0; j < n_args; j++)
8767 if (XEXP (undo->old_contents.r, j) != args[j])
8771 return undo->old_contents.r;
8774 /* Otherwise make a new rtx. We know we have 1, 2, or 3 args.
8775 Use rtx_alloc instead of gen_rtx because it's faster on RISC. */
8776 rt = rtx_alloc (code);
8777 PUT_MODE (rt, mode);
8778 XEXP (rt, 0) = args[0];
8781 XEXP (rt, 1) = args[1];
8783 XEXP (rt, 2) = args[2];
8788 /* These routines make binary and unary operations by first seeing if they
8789 fold; if not, a new expression is allocated. */
8792 gen_binary (code, mode, op0, op1)
8794 enum machine_mode mode;
8800 if (GET_RTX_CLASS (code) == 'c'
8801 && (GET_CODE (op0) == CONST_INT
8802 || (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)))
8803 tem = op0, op0 = op1, op1 = tem;
8805 if (GET_RTX_CLASS (code) == '<')
8807 enum machine_mode op_mode = GET_MODE (op0);
8809 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
8810 just (REL_OP X Y). */
8811 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
8813 op1 = XEXP (op0, 1);
8814 op0 = XEXP (op0, 0);
8815 op_mode = GET_MODE (op0);
8818 if (op_mode == VOIDmode)
8819 op_mode = GET_MODE (op1);
8820 result = simplify_relational_operation (code, op_mode, op0, op1);
8823 result = simplify_binary_operation (code, mode, op0, op1);
8828 /* Put complex operands first and constants second. */
8829 if (GET_RTX_CLASS (code) == 'c'
8830 && ((CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
8831 || (GET_RTX_CLASS (GET_CODE (op0)) == 'o'
8832 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')
8833 || (GET_CODE (op0) == SUBREG
8834 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0))) == 'o'
8835 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')))
8836 return gen_rtx_combine (code, mode, op1, op0);
8838 return gen_rtx_combine (code, mode, op0, op1);
8842 gen_unary (code, mode, op0_mode, op0)
8844 enum machine_mode mode, op0_mode;
8847 rtx result = simplify_unary_operation (code, mode, op0, op0_mode);
8852 return gen_rtx_combine (code, mode, op0);
8855 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
8856 comparison code that will be tested.
8858 The result is a possibly different comparison code to use. *POP0 and
8859 *POP1 may be updated.
8861 It is possible that we might detect that a comparison is either always
8862 true or always false. However, we do not perform general constant
8863 folding in combine, so this knowledge isn't useful. Such tautologies
8864 should have been detected earlier. Hence we ignore all such cases. */
8866 static enum rtx_code
8867 simplify_comparison (code, pop0, pop1)
8876 enum machine_mode mode, tmode;
8878 /* Try a few ways of applying the same transformation to both operands. */
8881 #ifndef WORD_REGISTER_OPERATIONS
8882 /* The test below this one won't handle SIGN_EXTENDs on these machines,
8883 so check specially. */
8884 if (code != GTU && code != GEU && code != LTU && code != LEU
8885 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
8886 && GET_CODE (XEXP (op0, 0)) == ASHIFT
8887 && GET_CODE (XEXP (op1, 0)) == ASHIFT
8888 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
8889 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
8890 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
8891 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
8892 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8893 && GET_CODE (XEXP (op1, 1)) == CONST_INT
8894 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
8895 && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT
8896 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (op1, 1))
8897 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op0, 0), 1))
8898 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op1, 0), 1))
8899 && (INTVAL (XEXP (op0, 1))
8900 == (GET_MODE_BITSIZE (GET_MODE (op0))
8902 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
8904 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
8905 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
8909 /* If both operands are the same constant shift, see if we can ignore the
8910 shift. We can if the shift is a rotate or if the bits shifted out of
8911 this shift are known to be zero for both inputs and if the type of
8912 comparison is compatible with the shift. */
8913 if (GET_CODE (op0) == GET_CODE (op1)
8914 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
8915 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
8916 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
8917 && (code != GT && code != LT && code != GE && code != LE))
8918 || (GET_CODE (op0) == ASHIFTRT
8919 && (code != GTU && code != LTU
8920 && code != GEU && code != GEU)))
8921 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8922 && INTVAL (XEXP (op0, 1)) >= 0
8923 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
8924 && XEXP (op0, 1) == XEXP (op1, 1))
8926 enum machine_mode mode = GET_MODE (op0);
8927 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
8928 int shift_count = INTVAL (XEXP (op0, 1));
8930 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
8931 mask &= (mask >> shift_count) << shift_count;
8932 else if (GET_CODE (op0) == ASHIFT)
8933 mask = (mask & (mask << shift_count)) >> shift_count;
8935 if ((nonzero_bits (XEXP (op0, 0), mode) & ~ mask) == 0
8936 && (nonzero_bits (XEXP (op1, 0), mode) & ~ mask) == 0)
8937 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
8942 /* If both operands are AND's of a paradoxical SUBREG by constant, the
8943 SUBREGs are of the same mode, and, in both cases, the AND would
8944 be redundant if the comparison was done in the narrower mode,
8945 do the comparison in the narrower mode (e.g., we are AND'ing with 1
8946 and the operand's possibly nonzero bits are 0xffffff01; in that case
8947 if we only care about QImode, we don't need the AND). This case
8948 occurs if the output mode of an scc insn is not SImode and
8949 STORE_FLAG_VALUE == 1 (e.g., the 386).
8951 Similarly, check for a case where the AND's are ZERO_EXTEND
8952 operations from some narrower mode even though a SUBREG is not
8955 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
8956 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8957 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
8959 rtx inner_op0 = XEXP (op0, 0);
8960 rtx inner_op1 = XEXP (op1, 0);
8961 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
8962 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
8965 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
8966 && (GET_MODE_SIZE (GET_MODE (inner_op0))
8967 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
8968 && (GET_MODE (SUBREG_REG (inner_op0))
8969 == GET_MODE (SUBREG_REG (inner_op1)))
8970 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
8971 <= HOST_BITS_PER_WIDE_INT)
8972 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
8973 GET_MODE (SUBREG_REG (op0)))))
8974 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
8975 GET_MODE (SUBREG_REG (inner_op1))))))
8977 op0 = SUBREG_REG (inner_op0);
8978 op1 = SUBREG_REG (inner_op1);
8980 /* The resulting comparison is always unsigned since we masked
8981 off the original sign bit. */
8982 code = unsigned_condition (code);
8988 for (tmode = GET_CLASS_NARROWEST_MODE
8989 (GET_MODE_CLASS (GET_MODE (op0)));
8990 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
8991 if (c0 == GET_MODE_MASK (tmode))
8993 op0 = gen_lowpart_for_combine (tmode, inner_op0);
8994 op1 = gen_lowpart_for_combine (tmode, inner_op1);
8995 code = unsigned_condition (code);
9004 /* If both operands are NOT, we can strip off the outer operation
9005 and adjust the comparison code for swapped operands; similarly for
9006 NEG, except that this must be an equality comparison. */
9007 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
9008 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
9009 && (code == EQ || code == NE)))
9010 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
9016 /* If the first operand is a constant, swap the operands and adjust the
9017 comparison code appropriately, but don't do this if the second operand
9018 is already a constant integer. */
9019 if (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
9021 tem = op0, op0 = op1, op1 = tem;
9022 code = swap_condition (code);
9025 /* We now enter a loop during which we will try to simplify the comparison.
9026 For the most part, we only are concerned with comparisons with zero,
9027 but some things may really be comparisons with zero but not start
9028 out looking that way. */
9030 while (GET_CODE (op1) == CONST_INT)
9032 enum machine_mode mode = GET_MODE (op0);
9033 int mode_width = GET_MODE_BITSIZE (mode);
9034 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9035 int equality_comparison_p;
9036 int sign_bit_comparison_p;
9037 int unsigned_comparison_p;
9038 HOST_WIDE_INT const_op;
9040 /* We only want to handle integral modes. This catches VOIDmode,
9041 CCmode, and the floating-point modes. An exception is that we
9042 can handle VOIDmode if OP0 is a COMPARE or a comparison
9045 if (GET_MODE_CLASS (mode) != MODE_INT
9046 && ! (mode == VOIDmode
9047 && (GET_CODE (op0) == COMPARE
9048 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
9051 /* Get the constant we are comparing against and turn off all bits
9052 not on in our mode. */
9053 const_op = INTVAL (op1);
9054 if (mode_width <= HOST_BITS_PER_WIDE_INT)
9057 /* If we are comparing against a constant power of two and the value
9058 being compared can only have that single bit nonzero (e.g., it was
9059 `and'ed with that bit), we can replace this with a comparison
9062 && (code == EQ || code == NE || code == GE || code == GEU
9063 || code == LT || code == LTU)
9064 && mode_width <= HOST_BITS_PER_WIDE_INT
9065 && exact_log2 (const_op) >= 0
9066 && nonzero_bits (op0, mode) == const_op)
9068 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
9069 op1 = const0_rtx, const_op = 0;
9072 /* Similarly, if we are comparing a value known to be either -1 or
9073 0 with -1, change it to the opposite comparison against zero. */
9076 && (code == EQ || code == NE || code == GT || code == LE
9077 || code == GEU || code == LTU)
9078 && num_sign_bit_copies (op0, mode) == mode_width)
9080 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
9081 op1 = const0_rtx, const_op = 0;
9084 /* Do some canonicalizations based on the comparison code. We prefer
9085 comparisons against zero and then prefer equality comparisons.
9086 If we can reduce the size of a constant, we will do that too. */
9091 /* < C is equivalent to <= (C - 1) */
9095 op1 = GEN_INT (const_op);
9097 /* ... fall through to LE case below. */
9103 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
9107 op1 = GEN_INT (const_op);
9111 /* If we are doing a <= 0 comparison on a value known to have
9112 a zero sign bit, we can replace this with == 0. */
9113 else if (const_op == 0
9114 && mode_width <= HOST_BITS_PER_WIDE_INT
9115 && (nonzero_bits (op0, mode)
9116 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9121 /* >= C is equivalent to > (C - 1). */
9125 op1 = GEN_INT (const_op);
9127 /* ... fall through to GT below. */
9133 /* > C is equivalent to >= (C + 1); we do this for C < 0*/
9137 op1 = GEN_INT (const_op);
9141 /* If we are doing a > 0 comparison on a value known to have
9142 a zero sign bit, we can replace this with != 0. */
9143 else if (const_op == 0
9144 && mode_width <= HOST_BITS_PER_WIDE_INT
9145 && (nonzero_bits (op0, mode)
9146 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9151 /* < C is equivalent to <= (C - 1). */
9155 op1 = GEN_INT (const_op);
9157 /* ... fall through ... */
9160 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
9161 else if (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1))
9163 const_op = 0, op1 = const0_rtx;
9171 /* unsigned <= 0 is equivalent to == 0 */
9175 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
9176 else if (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
9178 const_op = 0, op1 = const0_rtx;
9184 /* >= C is equivalent to < (C - 1). */
9188 op1 = GEN_INT (const_op);
9190 /* ... fall through ... */
9193 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
9194 else if (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1))
9196 const_op = 0, op1 = const0_rtx;
9204 /* unsigned > 0 is equivalent to != 0 */
9208 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
9209 else if (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
9211 const_op = 0, op1 = const0_rtx;
9217 /* Compute some predicates to simplify code below. */
9219 equality_comparison_p = (code == EQ || code == NE);
9220 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
9221 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
9224 /* If this is a sign bit comparison and we can do arithmetic in
9225 MODE, say that we will only be needing the sign bit of OP0. */
9226 if (sign_bit_comparison_p
9227 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9228 op0 = force_to_mode (op0, mode,
9230 << (GET_MODE_BITSIZE (mode) - 1)),
9233 /* Now try cases based on the opcode of OP0. If none of the cases
9234 does a "continue", we exit this loop immediately after the
9237 switch (GET_CODE (op0))
9240 /* If we are extracting a single bit from a variable position in
9241 a constant that has only a single bit set and are comparing it
9242 with zero, we can convert this into an equality comparison
9243 between the position and the location of the single bit. */
9245 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
9246 && XEXP (op0, 1) == const1_rtx
9247 && equality_comparison_p && const_op == 0
9248 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
9250 if (BITS_BIG_ENDIAN)
9252 i = (GET_MODE_BITSIZE
9253 (insn_operand_mode[(int) CODE_FOR_extzv][1]) - 1 - i);
9255 i = BITS_PER_WORD - 1 - i;
9258 op0 = XEXP (op0, 2);
9262 /* Result is nonzero iff shift count is equal to I. */
9263 code = reverse_condition (code);
9267 /* ... fall through ... */
9270 tem = expand_compound_operation (op0);
9279 /* If testing for equality, we can take the NOT of the constant. */
9280 if (equality_comparison_p
9281 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
9283 op0 = XEXP (op0, 0);
9288 /* If just looking at the sign bit, reverse the sense of the
9290 if (sign_bit_comparison_p)
9292 op0 = XEXP (op0, 0);
9293 code = (code == GE ? LT : GE);
9299 /* If testing for equality, we can take the NEG of the constant. */
9300 if (equality_comparison_p
9301 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
9303 op0 = XEXP (op0, 0);
9308 /* The remaining cases only apply to comparisons with zero. */
9312 /* When X is ABS or is known positive,
9313 (neg X) is < 0 if and only if X != 0. */
9315 if (sign_bit_comparison_p
9316 && (GET_CODE (XEXP (op0, 0)) == ABS
9317 || (mode_width <= HOST_BITS_PER_WIDE_INT
9318 && (nonzero_bits (XEXP (op0, 0), mode)
9319 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
9321 op0 = XEXP (op0, 0);
9322 code = (code == LT ? NE : EQ);
9326 /* If we have NEG of something whose two high-order bits are the
9327 same, we know that "(-a) < 0" is equivalent to "a > 0". */
9328 if (num_sign_bit_copies (op0, mode) >= 2)
9330 op0 = XEXP (op0, 0);
9331 code = swap_condition (code);
9337 /* If we are testing equality and our count is a constant, we
9338 can perform the inverse operation on our RHS. */
9339 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
9340 && (tem = simplify_binary_operation (ROTATERT, mode,
9341 op1, XEXP (op0, 1))) != 0)
9343 op0 = XEXP (op0, 0);
9348 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
9349 a particular bit. Convert it to an AND of a constant of that
9350 bit. This will be converted into a ZERO_EXTRACT. */
9351 if (const_op == 0 && sign_bit_comparison_p
9352 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9353 && mode_width <= HOST_BITS_PER_WIDE_INT)
9355 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
9358 - INTVAL (XEXP (op0, 1)))));
9359 code = (code == LT ? NE : EQ);
9363 /* ... fall through ... */
9366 /* ABS is ignorable inside an equality comparison with zero. */
9367 if (const_op == 0 && equality_comparison_p)
9369 op0 = XEXP (op0, 0);
9376 /* Can simplify (compare (zero/sign_extend FOO) CONST)
9377 to (compare FOO CONST) if CONST fits in FOO's mode and we
9378 are either testing inequality or have an unsigned comparison
9379 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
9380 if (! unsigned_comparison_p
9381 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
9382 <= HOST_BITS_PER_WIDE_INT)
9383 && ((unsigned HOST_WIDE_INT) const_op
9384 < (((HOST_WIDE_INT) 1
9385 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
9387 op0 = XEXP (op0, 0);
9393 /* Check for the case where we are comparing A - C1 with C2,
9394 both constants are smaller than 1/2 the maximum positive
9395 value in MODE, and the comparison is equality or unsigned.
9396 In that case, if A is either zero-extended to MODE or has
9397 sufficient sign bits so that the high-order bit in MODE
9398 is a copy of the sign in the inner mode, we can prove that it is
9399 safe to do the operation in the wider mode. This simplifies
9400 many range checks. */
9402 if (mode_width <= HOST_BITS_PER_WIDE_INT
9403 && subreg_lowpart_p (op0)
9404 && GET_CODE (SUBREG_REG (op0)) == PLUS
9405 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
9406 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
9407 && (- INTVAL (XEXP (SUBREG_REG (op0), 1))
9408 < GET_MODE_MASK (mode) / 2)
9409 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
9410 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
9411 GET_MODE (SUBREG_REG (op0)))
9412 & ~ GET_MODE_MASK (mode))
9413 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
9414 GET_MODE (SUBREG_REG (op0)))
9415 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
9416 - GET_MODE_BITSIZE (mode)))))
9418 op0 = SUBREG_REG (op0);
9422 /* If the inner mode is narrower and we are extracting the low part,
9423 we can treat the SUBREG as if it were a ZERO_EXTEND. */
9424 if (subreg_lowpart_p (op0)
9425 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
9426 /* Fall through */ ;
9430 /* ... fall through ... */
9433 if ((unsigned_comparison_p || equality_comparison_p)
9434 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
9435 <= HOST_BITS_PER_WIDE_INT)
9436 && ((unsigned HOST_WIDE_INT) const_op
9437 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
9439 op0 = XEXP (op0, 0);
9445 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
9446 this for equality comparisons due to pathological cases involving
9448 if (equality_comparison_p
9449 && 0 != (tem = simplify_binary_operation (MINUS, mode,
9450 op1, XEXP (op0, 1))))
9452 op0 = XEXP (op0, 0);
9457 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
9458 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
9459 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
9461 op0 = XEXP (XEXP (op0, 0), 0);
9462 code = (code == LT ? EQ : NE);
9468 /* (eq (minus A B) C) -> (eq A (plus B C)) or
9469 (eq B (minus A C)), whichever simplifies. We can only do
9470 this for equality comparisons due to pathological cases involving
9472 if (equality_comparison_p
9473 && 0 != (tem = simplify_binary_operation (PLUS, mode,
9474 XEXP (op0, 1), op1)))
9476 op0 = XEXP (op0, 0);
9481 if (equality_comparison_p
9482 && 0 != (tem = simplify_binary_operation (MINUS, mode,
9483 XEXP (op0, 0), op1)))
9485 op0 = XEXP (op0, 1);
9490 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
9491 of bits in X minus 1, is one iff X > 0. */
9492 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
9493 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9494 && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
9495 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
9497 op0 = XEXP (op0, 1);
9498 code = (code == GE ? LE : GT);
9504 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
9505 if C is zero or B is a constant. */
9506 if (equality_comparison_p
9507 && 0 != (tem = simplify_binary_operation (XOR, mode,
9508 XEXP (op0, 1), op1)))
9510 op0 = XEXP (op0, 0);
9517 case LT: case LTU: case LE: case LEU:
9518 case GT: case GTU: case GE: case GEU:
9519 /* We can't do anything if OP0 is a condition code value, rather
9520 than an actual data value. */
9523 || XEXP (op0, 0) == cc0_rtx
9525 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
9528 /* Get the two operands being compared. */
9529 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
9530 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
9532 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
9534 /* Check for the cases where we simply want the result of the
9535 earlier test or the opposite of that result. */
9537 || (code == EQ && reversible_comparison_p (op0))
9538 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9539 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
9540 && (STORE_FLAG_VALUE
9541 & (((HOST_WIDE_INT) 1
9542 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
9544 || (code == GE && reversible_comparison_p (op0)))))
9546 code = (code == LT || code == NE
9547 ? GET_CODE (op0) : reverse_condition (GET_CODE (op0)));
9548 op0 = tem, op1 = tem1;
9554 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
9556 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
9557 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
9558 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
9560 op0 = XEXP (op0, 1);
9561 code = (code == GE ? GT : LE);
9567 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
9568 will be converted to a ZERO_EXTRACT later. */
9569 if (const_op == 0 && equality_comparison_p
9570 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9571 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
9573 op0 = simplify_and_const_int
9574 (op0, mode, gen_rtx_combine (LSHIFTRT, mode,
9576 XEXP (XEXP (op0, 0), 1)),
9581 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
9582 zero and X is a comparison and C1 and C2 describe only bits set
9583 in STORE_FLAG_VALUE, we can compare with X. */
9584 if (const_op == 0 && equality_comparison_p
9585 && mode_width <= HOST_BITS_PER_WIDE_INT
9586 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9587 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
9588 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9589 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
9590 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
9592 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
9593 << INTVAL (XEXP (XEXP (op0, 0), 1)));
9594 if ((~ STORE_FLAG_VALUE & mask) == 0
9595 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
9596 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
9597 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
9599 op0 = XEXP (XEXP (op0, 0), 0);
9604 /* If we are doing an equality comparison of an AND of a bit equal
9605 to the sign bit, replace this with a LT or GE comparison of
9606 the underlying value. */
9607 if (equality_comparison_p
9609 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9610 && mode_width <= HOST_BITS_PER_WIDE_INT
9611 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
9612 == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9614 op0 = XEXP (op0, 0);
9615 code = (code == EQ ? GE : LT);
9619 /* If this AND operation is really a ZERO_EXTEND from a narrower
9620 mode, the constant fits within that mode, and this is either an
9621 equality or unsigned comparison, try to do this comparison in
9622 the narrower mode. */
9623 if ((equality_comparison_p || unsigned_comparison_p)
9624 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9625 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
9626 & GET_MODE_MASK (mode))
9628 && const_op >> i == 0
9629 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
9631 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
9637 /* If we have (compare (ashift FOO N) (const_int C)) and
9638 the high order N bits of FOO (N+1 if an inequality comparison)
9639 are known to be zero, we can do this by comparing FOO with C
9640 shifted right N bits so long as the low-order N bits of C are
9642 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
9643 && INTVAL (XEXP (op0, 1)) >= 0
9644 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
9645 < HOST_BITS_PER_WIDE_INT)
9647 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
9648 && mode_width <= HOST_BITS_PER_WIDE_INT
9649 && (nonzero_bits (XEXP (op0, 0), mode)
9650 & ~ (mask >> (INTVAL (XEXP (op0, 1))
9651 + ! equality_comparison_p))) == 0)
9653 const_op >>= INTVAL (XEXP (op0, 1));
9654 op1 = GEN_INT (const_op);
9655 op0 = XEXP (op0, 0);
9659 /* If we are doing a sign bit comparison, it means we are testing
9660 a particular bit. Convert it to the appropriate AND. */
9661 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
9662 && mode_width <= HOST_BITS_PER_WIDE_INT)
9664 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
9667 - INTVAL (XEXP (op0, 1)))));
9668 code = (code == LT ? NE : EQ);
9672 /* If this an equality comparison with zero and we are shifting
9673 the low bit to the sign bit, we can convert this to an AND of the
9675 if (const_op == 0 && equality_comparison_p
9676 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9677 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
9679 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
9686 /* If this is an equality comparison with zero, we can do this
9687 as a logical shift, which might be much simpler. */
9688 if (equality_comparison_p && const_op == 0
9689 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
9691 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
9693 INTVAL (XEXP (op0, 1)));
9697 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
9698 do the comparison in a narrower mode. */
9699 if (! unsigned_comparison_p
9700 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9701 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9702 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
9703 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
9704 MODE_INT, 1)) != BLKmode
9705 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
9706 || ((unsigned HOST_WIDE_INT) - const_op
9707 <= GET_MODE_MASK (tmode))))
9709 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
9713 /* ... fall through ... */
9715 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
9716 the low order N bits of FOO are known to be zero, we can do this
9717 by comparing FOO with C shifted left N bits so long as no
9719 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
9720 && INTVAL (XEXP (op0, 1)) >= 0
9721 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9722 && mode_width <= HOST_BITS_PER_WIDE_INT
9723 && (nonzero_bits (XEXP (op0, 0), mode)
9724 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
9726 || (floor_log2 (const_op) + INTVAL (XEXP (op0, 1))
9729 const_op <<= INTVAL (XEXP (op0, 1));
9730 op1 = GEN_INT (const_op);
9731 op0 = XEXP (op0, 0);
9735 /* If we are using this shift to extract just the sign bit, we
9736 can replace this with an LT or GE comparison. */
9738 && (equality_comparison_p || sign_bit_comparison_p)
9739 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9740 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
9742 op0 = XEXP (op0, 0);
9743 code = (code == NE || code == GT ? LT : GE);
9752 /* Now make any compound operations involved in this comparison. Then,
9753 check for an outmost SUBREG on OP0 that isn't doing anything or is
9754 paradoxical. The latter case can only occur when it is known that the
9755 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
9756 We can never remove a SUBREG for a non-equality comparison because the
9757 sign bit is in a different place in the underlying object. */
9759 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
9760 op1 = make_compound_operation (op1, SET);
9762 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
9763 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
9764 && (code == NE || code == EQ)
9765 && ((GET_MODE_SIZE (GET_MODE (op0))
9766 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))))
9768 op0 = SUBREG_REG (op0);
9769 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
9772 else if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
9773 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
9774 && (code == NE || code == EQ)
9775 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
9776 <= HOST_BITS_PER_WIDE_INT)
9777 && (nonzero_bits (SUBREG_REG (op0), GET_MODE (SUBREG_REG (op0)))
9778 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0
9779 && (tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)),
9781 (nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
9782 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0))
9783 op0 = SUBREG_REG (op0), op1 = tem;
9785 /* We now do the opposite procedure: Some machines don't have compare
9786 insns in all modes. If OP0's mode is an integer mode smaller than a
9787 word and we can't do a compare in that mode, see if there is a larger
9788 mode for which we can do the compare. There are a number of cases in
9789 which we can use the wider mode. */
9791 mode = GET_MODE (op0);
9792 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
9793 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
9794 && cmp_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
9795 for (tmode = GET_MODE_WIDER_MODE (mode);
9797 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
9798 tmode = GET_MODE_WIDER_MODE (tmode))
9799 if (cmp_optab->handlers[(int) tmode].insn_code != CODE_FOR_nothing)
9801 /* If the only nonzero bits in OP0 and OP1 are those in the
9802 narrower mode and this is an equality or unsigned comparison,
9803 we can use the wider mode. Similarly for sign-extended
9804 values, in which case it is true for all comparisons. */
9805 if (((code == EQ || code == NE
9806 || code == GEU || code == GTU || code == LEU || code == LTU)
9807 && (nonzero_bits (op0, tmode) & ~ GET_MODE_MASK (mode)) == 0
9808 && (nonzero_bits (op1, tmode) & ~ GET_MODE_MASK (mode)) == 0)
9809 || ((num_sign_bit_copies (op0, tmode)
9810 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))
9811 && (num_sign_bit_copies (op1, tmode)
9812 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))))
9814 op0 = gen_lowpart_for_combine (tmode, op0);
9815 op1 = gen_lowpart_for_combine (tmode, op1);
9819 /* If this is a test for negative, we can make an explicit
9820 test of the sign bit. */
9822 if (op1 == const0_rtx && (code == LT || code == GE)
9823 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9825 op0 = gen_binary (AND, tmode,
9826 gen_lowpart_for_combine (tmode, op0),
9827 GEN_INT ((HOST_WIDE_INT) 1
9828 << (GET_MODE_BITSIZE (mode) - 1)));
9829 code = (code == LT) ? NE : EQ;
9834 #ifdef CANONICALIZE_COMPARISON
9835 /* If this machine only supports a subset of valid comparisons, see if we
9836 can convert an unsupported one into a supported one. */
9837 CANONICALIZE_COMPARISON (code, op0, op1);
9846 /* Return 1 if we know that X, a comparison operation, is not operating
9847 on a floating-point value or is EQ or NE, meaning that we can safely
9851 reversible_comparison_p (x)
9854 if (TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
9856 || GET_CODE (x) == NE || GET_CODE (x) == EQ)
9859 switch (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))))
9862 case MODE_PARTIAL_INT:
9863 case MODE_COMPLEX_INT:
9867 /* If the mode of the condition codes tells us that this is safe,
9868 we need look no further. */
9869 if (REVERSIBLE_CC_MODE (GET_MODE (XEXP (x, 0))))
9872 /* Otherwise try and find where the condition codes were last set and
9874 x = get_last_value (XEXP (x, 0));
9875 return (x && GET_CODE (x) == COMPARE
9876 && ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0))));
9882 /* Utility function for following routine. Called when X is part of a value
9883 being stored into reg_last_set_value. Sets reg_last_set_table_tick
9884 for each register mentioned. Similar to mention_regs in cse.c */
9887 update_table_tick (x)
9890 register enum rtx_code code = GET_CODE (x);
9891 register char *fmt = GET_RTX_FORMAT (code);
9896 int regno = REGNO (x);
9897 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
9898 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
9900 for (i = regno; i < endregno; i++)
9901 reg_last_set_table_tick[i] = label_tick;
9906 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9907 /* Note that we can't have an "E" in values stored; see
9908 get_last_value_validate. */
9910 update_table_tick (XEXP (x, i));
9913 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
9914 are saying that the register is clobbered and we no longer know its
9915 value. If INSN is zero, don't update reg_last_set; this is only permitted
9916 with VALUE also zero and is used to invalidate the register. */
9919 record_value_for_reg (reg, insn, value)
9924 int regno = REGNO (reg);
9925 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
9926 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
9929 /* If VALUE contains REG and we have a previous value for REG, substitute
9930 the previous value. */
9931 if (value && insn && reg_overlap_mentioned_p (reg, value))
9935 /* Set things up so get_last_value is allowed to see anything set up to
9937 subst_low_cuid = INSN_CUID (insn);
9938 tem = get_last_value (reg);
9941 value = replace_rtx (copy_rtx (value), reg, tem);
9944 /* For each register modified, show we don't know its value, that
9945 we don't know about its bitwise content, that its value has been
9946 updated, and that we don't know the location of the death of the
9948 for (i = regno; i < endregno; i ++)
9951 reg_last_set[i] = insn;
9952 reg_last_set_value[i] = 0;
9953 reg_last_set_mode[i] = 0;
9954 reg_last_set_nonzero_bits[i] = 0;
9955 reg_last_set_sign_bit_copies[i] = 0;
9956 reg_last_death[i] = 0;
9959 /* Mark registers that are being referenced in this value. */
9961 update_table_tick (value);
9963 /* Now update the status of each register being set.
9964 If someone is using this register in this block, set this register
9965 to invalid since we will get confused between the two lives in this
9966 basic block. This makes using this register always invalid. In cse, we
9967 scan the table to invalidate all entries using this register, but this
9968 is too much work for us. */
9970 for (i = regno; i < endregno; i++)
9972 reg_last_set_label[i] = label_tick;
9973 if (value && reg_last_set_table_tick[i] == label_tick)
9974 reg_last_set_invalid[i] = 1;
9976 reg_last_set_invalid[i] = 0;
9979 /* The value being assigned might refer to X (like in "x++;"). In that
9980 case, we must replace it with (clobber (const_int 0)) to prevent
9982 if (value && ! get_last_value_validate (&value,
9983 reg_last_set_label[regno], 0))
9985 value = copy_rtx (value);
9986 if (! get_last_value_validate (&value, reg_last_set_label[regno], 1))
9990 /* For the main register being modified, update the value, the mode, the
9991 nonzero bits, and the number of sign bit copies. */
9993 reg_last_set_value[regno] = value;
9997 subst_low_cuid = INSN_CUID (insn);
9998 reg_last_set_mode[regno] = GET_MODE (reg);
9999 reg_last_set_nonzero_bits[regno] = nonzero_bits (value, GET_MODE (reg));
10000 reg_last_set_sign_bit_copies[regno]
10001 = num_sign_bit_copies (value, GET_MODE (reg));
10005 /* Used for communication between the following two routines. */
10006 static rtx record_dead_insn;
10008 /* Called via note_stores from record_dead_and_set_regs to handle one
10009 SET or CLOBBER in an insn. */
10012 record_dead_and_set_regs_1 (dest, setter)
10015 if (GET_CODE (dest) == SUBREG)
10016 dest = SUBREG_REG (dest);
10018 if (GET_CODE (dest) == REG)
10020 /* If we are setting the whole register, we know its value. Otherwise
10021 show that we don't know the value. We can handle SUBREG in
10023 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
10024 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
10025 else if (GET_CODE (setter) == SET
10026 && GET_CODE (SET_DEST (setter)) == SUBREG
10027 && SUBREG_REG (SET_DEST (setter)) == dest
10028 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
10029 && subreg_lowpart_p (SET_DEST (setter)))
10030 record_value_for_reg (dest, record_dead_insn,
10031 gen_lowpart_for_combine (GET_MODE (dest),
10032 SET_SRC (setter)));
10034 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
10036 else if (GET_CODE (dest) == MEM
10037 /* Ignore pushes, they clobber nothing. */
10038 && ! push_operand (dest, GET_MODE (dest)))
10039 mem_last_set = INSN_CUID (record_dead_insn);
10042 /* Update the records of when each REG was most recently set or killed
10043 for the things done by INSN. This is the last thing done in processing
10044 INSN in the combiner loop.
10046 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
10047 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
10048 and also the similar information mem_last_set (which insn most recently
10049 modified memory) and last_call_cuid (which insn was the most recent
10050 subroutine call). */
10053 record_dead_and_set_regs (insn)
10059 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
10061 if (REG_NOTE_KIND (link) == REG_DEAD
10062 && GET_CODE (XEXP (link, 0)) == REG)
10064 int regno = REGNO (XEXP (link, 0));
10066 = regno + (regno < FIRST_PSEUDO_REGISTER
10067 ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0)))
10070 for (i = regno; i < endregno; i++)
10071 reg_last_death[i] = insn;
10073 else if (REG_NOTE_KIND (link) == REG_INC)
10074 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
10077 if (GET_CODE (insn) == CALL_INSN)
10079 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
10080 if (call_used_regs[i])
10082 reg_last_set_value[i] = 0;
10083 reg_last_set_mode[i] = 0;
10084 reg_last_set_nonzero_bits[i] = 0;
10085 reg_last_set_sign_bit_copies[i] = 0;
10086 reg_last_death[i] = 0;
10089 last_call_cuid = mem_last_set = INSN_CUID (insn);
10092 record_dead_insn = insn;
10093 note_stores (PATTERN (insn), record_dead_and_set_regs_1);
10096 /* Utility routine for the following function. Verify that all the registers
10097 mentioned in *LOC are valid when *LOC was part of a value set when
10098 label_tick == TICK. Return 0 if some are not.
10100 If REPLACE is non-zero, replace the invalid reference with
10101 (clobber (const_int 0)) and return 1. This replacement is useful because
10102 we often can get useful information about the form of a value (e.g., if
10103 it was produced by a shift that always produces -1 or 0) even though
10104 we don't know exactly what registers it was produced from. */
10107 get_last_value_validate (loc, tick, replace)
10113 char *fmt = GET_RTX_FORMAT (GET_CODE (x));
10114 int len = GET_RTX_LENGTH (GET_CODE (x));
10117 if (GET_CODE (x) == REG)
10119 int regno = REGNO (x);
10120 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10121 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10124 for (j = regno; j < endregno; j++)
10125 if (reg_last_set_invalid[j]
10126 /* If this is a pseudo-register that was only set once, it is
10128 || (! (regno >= FIRST_PSEUDO_REGISTER && reg_n_sets[regno] == 1)
10129 && reg_last_set_label[j] > tick))
10132 *loc = gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
10139 for (i = 0; i < len; i++)
10141 && get_last_value_validate (&XEXP (x, i), tick, replace) == 0)
10142 /* Don't bother with these. They shouldn't occur anyway. */
10146 /* If we haven't found a reason for it to be invalid, it is valid. */
10150 /* Get the last value assigned to X, if known. Some registers
10151 in the value may be replaced with (clobber (const_int 0)) if their value
10152 is known longer known reliably. */
10161 /* If this is a non-paradoxical SUBREG, get the value of its operand and
10162 then convert it to the desired mode. If this is a paradoxical SUBREG,
10163 we cannot predict what values the "extra" bits might have. */
10164 if (GET_CODE (x) == SUBREG
10165 && subreg_lowpart_p (x)
10166 && (GET_MODE_SIZE (GET_MODE (x))
10167 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
10168 && (value = get_last_value (SUBREG_REG (x))) != 0)
10169 return gen_lowpart_for_combine (GET_MODE (x), value);
10171 if (GET_CODE (x) != REG)
10175 value = reg_last_set_value[regno];
10177 /* If we don't have a value or if it isn't for this basic block,
10181 || (reg_n_sets[regno] != 1
10182 && reg_last_set_label[regno] != label_tick))
10185 /* If the value was set in a later insn than the ones we are processing,
10186 we can't use it even if the register was only set once, but make a quick
10187 check to see if the previous insn set it to something. This is commonly
10188 the case when the same pseudo is used by repeated insns.
10190 This does not work if there exists an instruction which is temporarily
10191 not on the insn chain. */
10193 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
10197 /* We can not do anything useful in this case, because there is
10198 an instruction which is not on the insn chain. */
10199 if (subst_prev_insn)
10202 /* Skip over USE insns. They are not useful here, and they may have
10203 been made by combine, in which case they do not have a INSN_CUID
10204 value. We can't use prev_real_insn, because that would incorrectly
10205 take us backwards across labels. Skip over BARRIERs also, since
10206 they could have been made by combine. If we see one, we must be
10207 optimizing dead code, so it doesn't matter what we do. */
10208 for (insn = prev_nonnote_insn (subst_insn);
10209 insn && ((GET_CODE (insn) == INSN
10210 && GET_CODE (PATTERN (insn)) == USE)
10211 || GET_CODE (insn) == BARRIER
10212 || INSN_CUID (insn) >= subst_low_cuid);
10213 insn = prev_nonnote_insn (insn))
10217 && (set = single_set (insn)) != 0
10218 && rtx_equal_p (SET_DEST (set), x))
10220 value = SET_SRC (set);
10222 /* Make sure that VALUE doesn't reference X. Replace any
10223 explicit references with a CLOBBER. If there are any remaining
10224 references (rare), don't use the value. */
10226 if (reg_mentioned_p (x, value))
10227 value = replace_rtx (copy_rtx (value), x,
10228 gen_rtx (CLOBBER, GET_MODE (x), const0_rtx));
10230 if (reg_overlap_mentioned_p (x, value))
10237 /* If the value has all its registers valid, return it. */
10238 if (get_last_value_validate (&value, reg_last_set_label[regno], 0))
10241 /* Otherwise, make a copy and replace any invalid register with
10242 (clobber (const_int 0)). If that fails for some reason, return 0. */
10244 value = copy_rtx (value);
10245 if (get_last_value_validate (&value, reg_last_set_label[regno], 1))
10251 /* Return nonzero if expression X refers to a REG or to memory
10252 that is set in an instruction more recent than FROM_CUID. */
10255 use_crosses_set_p (x, from_cuid)
10259 register char *fmt;
10261 register enum rtx_code code = GET_CODE (x);
10265 register int regno = REGNO (x);
10266 int endreg = regno + (regno < FIRST_PSEUDO_REGISTER
10267 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10269 #ifdef PUSH_ROUNDING
10270 /* Don't allow uses of the stack pointer to be moved,
10271 because we don't know whether the move crosses a push insn. */
10272 if (regno == STACK_POINTER_REGNUM)
10275 for (;regno < endreg; regno++)
10276 if (reg_last_set[regno]
10277 && INSN_CUID (reg_last_set[regno]) > from_cuid)
10282 if (code == MEM && mem_last_set > from_cuid)
10285 fmt = GET_RTX_FORMAT (code);
10287 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10292 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
10293 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
10296 else if (fmt[i] == 'e'
10297 && use_crosses_set_p (XEXP (x, i), from_cuid))
10303 /* Define three variables used for communication between the following
10306 static int reg_dead_regno, reg_dead_endregno;
10307 static int reg_dead_flag;
10309 /* Function called via note_stores from reg_dead_at_p.
10311 If DEST is within [reg_dead_regno, reg_dead_endregno), set
10312 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
10315 reg_dead_at_p_1 (dest, x)
10319 int regno, endregno;
10321 if (GET_CODE (dest) != REG)
10324 regno = REGNO (dest);
10325 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10326 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
10328 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
10329 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
10332 /* Return non-zero if REG is known to be dead at INSN.
10334 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
10335 referencing REG, it is dead. If we hit a SET referencing REG, it is
10336 live. Otherwise, see if it is live or dead at the start of the basic
10337 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
10338 must be assumed to be always live. */
10341 reg_dead_at_p (reg, insn)
10347 /* Set variables for reg_dead_at_p_1. */
10348 reg_dead_regno = REGNO (reg);
10349 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
10350 ? HARD_REGNO_NREGS (reg_dead_regno,
10356 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
10357 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
10359 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
10360 if (TEST_HARD_REG_BIT (newpat_used_regs, i))
10364 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
10365 beginning of function. */
10366 for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER;
10367 insn = prev_nonnote_insn (insn))
10369 note_stores (PATTERN (insn), reg_dead_at_p_1);
10371 return reg_dead_flag == 1 ? 1 : 0;
10373 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
10377 /* Get the basic block number that we were in. */
10382 for (block = 0; block < n_basic_blocks; block++)
10383 if (insn == basic_block_head[block])
10386 if (block == n_basic_blocks)
10390 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
10391 if (basic_block_live_at_start[block][i / REGSET_ELT_BITS]
10392 & ((REGSET_ELT_TYPE) 1 << (i % REGSET_ELT_BITS)))
10398 /* Note hard registers in X that are used. This code is similar to
10399 that in flow.c, but much simpler since we don't care about pseudos. */
10402 mark_used_regs_combine (x)
10405 register RTX_CODE code = GET_CODE (x);
10406 register int regno;
10418 case ADDR_DIFF_VEC:
10421 /* CC0 must die in the insn after it is set, so we don't need to take
10422 special note of it here. */
10428 /* If we are clobbering a MEM, mark any hard registers inside the
10429 address as used. */
10430 if (GET_CODE (XEXP (x, 0)) == MEM)
10431 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
10436 /* A hard reg in a wide mode may really be multiple registers.
10437 If so, mark all of them just like the first. */
10438 if (regno < FIRST_PSEUDO_REGISTER)
10440 /* None of this applies to the stack, frame or arg pointers */
10441 if (regno == STACK_POINTER_REGNUM
10442 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
10443 || regno == HARD_FRAME_POINTER_REGNUM
10445 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
10446 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
10448 || regno == FRAME_POINTER_REGNUM)
10451 i = HARD_REGNO_NREGS (regno, GET_MODE (x));
10453 SET_HARD_REG_BIT (newpat_used_regs, regno + i);
10459 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
10461 register rtx testreg = SET_DEST (x);
10463 while (GET_CODE (testreg) == SUBREG
10464 || GET_CODE (testreg) == ZERO_EXTRACT
10465 || GET_CODE (testreg) == SIGN_EXTRACT
10466 || GET_CODE (testreg) == STRICT_LOW_PART)
10467 testreg = XEXP (testreg, 0);
10469 if (GET_CODE (testreg) == MEM)
10470 mark_used_regs_combine (XEXP (testreg, 0));
10472 mark_used_regs_combine (SET_SRC (x));
10477 /* Recursively scan the operands of this expression. */
10480 register char *fmt = GET_RTX_FORMAT (code);
10482 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10485 mark_used_regs_combine (XEXP (x, i));
10486 else if (fmt[i] == 'E')
10490 for (j = 0; j < XVECLEN (x, i); j++)
10491 mark_used_regs_combine (XVECEXP (x, i, j));
10498 /* Remove register number REGNO from the dead registers list of INSN.
10500 Return the note used to record the death, if there was one. */
10503 remove_death (regno, insn)
10507 register rtx note = find_regno_note (insn, REG_DEAD, regno);
10511 reg_n_deaths[regno]--;
10512 remove_note (insn, note);
10518 /* For each register (hardware or pseudo) used within expression X, if its
10519 death is in an instruction with cuid between FROM_CUID (inclusive) and
10520 TO_INSN (exclusive), put a REG_DEAD note for that register in the
10521 list headed by PNOTES.
10523 That said, don't move registers killed by maybe_kill_insn.
10525 This is done when X is being merged by combination into TO_INSN. These
10526 notes will then be distributed as needed. */
10529 move_deaths (x, maybe_kill_insn, from_cuid, to_insn, pnotes)
10531 rtx maybe_kill_insn;
10536 register char *fmt;
10537 register int len, i;
10538 register enum rtx_code code = GET_CODE (x);
10542 register int regno = REGNO (x);
10543 register rtx where_dead = reg_last_death[regno];
10544 register rtx before_dead, after_dead;
10546 /* Don't move the register if it gets killed in between from and to */
10547 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
10548 && !reg_referenced_p (x, maybe_kill_insn))
10551 /* WHERE_DEAD could be a USE insn made by combine, so first we
10552 make sure that we have insns with valid INSN_CUID values. */
10553 before_dead = where_dead;
10554 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
10555 before_dead = PREV_INSN (before_dead);
10556 after_dead = where_dead;
10557 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
10558 after_dead = NEXT_INSN (after_dead);
10560 if (before_dead && after_dead
10561 && INSN_CUID (before_dead) >= from_cuid
10562 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
10563 || (where_dead != after_dead
10564 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
10566 rtx note = remove_death (regno, where_dead);
10568 /* It is possible for the call above to return 0. This can occur
10569 when reg_last_death points to I2 or I1 that we combined with.
10570 In that case make a new note.
10572 We must also check for the case where X is a hard register
10573 and NOTE is a death note for a range of hard registers
10574 including X. In that case, we must put REG_DEAD notes for
10575 the remaining registers in place of NOTE. */
10577 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
10578 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
10579 != GET_MODE_SIZE (GET_MODE (x))))
10581 int deadregno = REGNO (XEXP (note, 0));
10583 = (deadregno + HARD_REGNO_NREGS (deadregno,
10584 GET_MODE (XEXP (note, 0))));
10585 int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
10588 for (i = deadregno; i < deadend; i++)
10589 if (i < regno || i >= ourend)
10590 REG_NOTES (where_dead)
10591 = gen_rtx (EXPR_LIST, REG_DEAD,
10592 gen_rtx (REG, reg_raw_mode[i], i),
10593 REG_NOTES (where_dead));
10595 /* If we didn't find any note, and we have a multi-reg hard
10596 register, then to be safe we must check for REG_DEAD notes
10597 for each register other than the first. They could have
10598 their own REG_DEAD notes lying around. */
10599 else if (note == 0 && regno < FIRST_PSEUDO_REGISTER
10600 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
10602 int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
10606 for (i = regno + 1; i < ourend; i++)
10607 move_deaths (gen_rtx (REG, reg_raw_mode[i], i),
10608 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
10611 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
10613 XEXP (note, 1) = *pnotes;
10617 *pnotes = gen_rtx (EXPR_LIST, REG_DEAD, x, *pnotes);
10619 reg_n_deaths[regno]++;
10625 else if (GET_CODE (x) == SET)
10627 rtx dest = SET_DEST (x);
10629 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
10631 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
10632 that accesses one word of a multi-word item, some
10633 piece of everything register in the expression is used by
10634 this insn, so remove any old death. */
10636 if (GET_CODE (dest) == ZERO_EXTRACT
10637 || GET_CODE (dest) == STRICT_LOW_PART
10638 || (GET_CODE (dest) == SUBREG
10639 && (((GET_MODE_SIZE (GET_MODE (dest))
10640 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
10641 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
10642 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
10644 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
10648 /* If this is some other SUBREG, we know it replaces the entire
10649 value, so use that as the destination. */
10650 if (GET_CODE (dest) == SUBREG)
10651 dest = SUBREG_REG (dest);
10653 /* If this is a MEM, adjust deaths of anything used in the address.
10654 For a REG (the only other possibility), the entire value is
10655 being replaced so the old value is not used in this insn. */
10657 if (GET_CODE (dest) == MEM)
10658 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
10663 else if (GET_CODE (x) == CLOBBER)
10666 len = GET_RTX_LENGTH (code);
10667 fmt = GET_RTX_FORMAT (code);
10669 for (i = 0; i < len; i++)
10674 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
10675 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
10678 else if (fmt[i] == 'e')
10679 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
10683 /* Return 1 if X is the target of a bit-field assignment in BODY, the
10684 pattern of an insn. X must be a REG. */
10687 reg_bitfield_target_p (x, body)
10693 if (GET_CODE (body) == SET)
10695 rtx dest = SET_DEST (body);
10697 int regno, tregno, endregno, endtregno;
10699 if (GET_CODE (dest) == ZERO_EXTRACT)
10700 target = XEXP (dest, 0);
10701 else if (GET_CODE (dest) == STRICT_LOW_PART)
10702 target = SUBREG_REG (XEXP (dest, 0));
10706 if (GET_CODE (target) == SUBREG)
10707 target = SUBREG_REG (target);
10709 if (GET_CODE (target) != REG)
10712 tregno = REGNO (target), regno = REGNO (x);
10713 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
10714 return target == x;
10716 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
10717 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
10719 return endregno > tregno && regno < endtregno;
10722 else if (GET_CODE (body) == PARALLEL)
10723 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
10724 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
10730 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
10731 as appropriate. I3 and I2 are the insns resulting from the combination
10732 insns including FROM (I2 may be zero).
10734 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
10735 not need REG_DEAD notes because they are being substituted for. This
10736 saves searching in the most common cases.
10738 Each note in the list is either ignored or placed on some insns, depending
10739 on the type of note. */
10742 distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
10746 rtx elim_i2, elim_i1;
10748 rtx note, next_note;
10751 for (note = notes; note; note = next_note)
10753 rtx place = 0, place2 = 0;
10755 /* If this NOTE references a pseudo register, ensure it references
10756 the latest copy of that register. */
10757 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
10758 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
10759 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
10761 next_note = XEXP (note, 1);
10762 switch (REG_NOTE_KIND (note))
10765 /* Any clobbers for i3 may still exist, and so we must process
10766 REG_UNUSED notes from that insn.
10768 Any clobbers from i2 or i1 can only exist if they were added by
10769 recog_for_combine. In that case, recog_for_combine created the
10770 necessary REG_UNUSED notes. Trying to keep any original
10771 REG_UNUSED notes from these insns can cause incorrect output
10772 if it is for the same register as the original i3 dest.
10773 In that case, we will notice that the register is set in i3,
10774 and then add a REG_UNUSED note for the destination of i3, which
10775 is wrong. However, it is possible to have REG_UNUSED notes from
10776 i2 or i1 for register which were both used and clobbered, so
10777 we keep notes from i2 or i1 if they will turn into REG_DEAD
10780 /* If this register is set or clobbered in I3, put the note there
10781 unless there is one already. */
10782 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
10784 if (from_insn != i3)
10787 if (! (GET_CODE (XEXP (note, 0)) == REG
10788 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
10789 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
10792 /* Otherwise, if this register is used by I3, then this register
10793 now dies here, so we must put a REG_DEAD note here unless there
10795 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
10796 && ! (GET_CODE (XEXP (note, 0)) == REG
10797 ? find_regno_note (i3, REG_DEAD, REGNO (XEXP (note, 0)))
10798 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
10800 PUT_REG_NOTE_KIND (note, REG_DEAD);
10808 /* These notes say something about results of an insn. We can
10809 only support them if they used to be on I3 in which case they
10810 remain on I3. Otherwise they are ignored.
10812 If the note refers to an expression that is not a constant, we
10813 must also ignore the note since we cannot tell whether the
10814 equivalence is still true. It might be possible to do
10815 slightly better than this (we only have a problem if I2DEST
10816 or I1DEST is present in the expression), but it doesn't
10817 seem worth the trouble. */
10819 if (from_insn == i3
10820 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
10825 case REG_NO_CONFLICT:
10827 /* These notes say something about how a register is used. They must
10828 be present on any use of the register in I2 or I3. */
10829 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
10832 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
10842 /* It is too much trouble to try to see if this note is still
10843 correct in all situations. It is better to simply delete it. */
10847 /* If the insn previously containing this note still exists,
10848 put it back where it was. Otherwise move it to the previous
10849 insn. Adjust the corresponding REG_LIBCALL note. */
10850 if (GET_CODE (from_insn) != NOTE)
10854 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
10855 place = prev_real_insn (from_insn);
10857 XEXP (tem, 0) = place;
10862 /* This is handled similarly to REG_RETVAL. */
10863 if (GET_CODE (from_insn) != NOTE)
10867 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
10868 place = next_real_insn (from_insn);
10870 XEXP (tem, 0) = place;
10875 /* If the register is used as an input in I3, it dies there.
10876 Similarly for I2, if it is non-zero and adjacent to I3.
10878 If the register is not used as an input in either I3 or I2
10879 and it is not one of the registers we were supposed to eliminate,
10880 there are two possibilities. We might have a non-adjacent I2
10881 or we might have somehow eliminated an additional register
10882 from a computation. For example, we might have had A & B where
10883 we discover that B will always be zero. In this case we will
10884 eliminate the reference to A.
10886 In both cases, we must search to see if we can find a previous
10887 use of A and put the death note there. */
10890 && GET_CODE (from_insn) == CALL_INSN
10891 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
10893 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
10895 else if (i2 != 0 && next_nonnote_insn (i2) == i3
10896 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
10899 if (XEXP (note, 0) == elim_i2 || XEXP (note, 0) == elim_i1)
10902 /* If the register is used in both I2 and I3 and it dies in I3,
10903 we might have added another reference to it. If reg_n_refs
10904 was 2, bump it to 3. This has to be correct since the
10905 register must have been set somewhere. The reason this is
10906 done is because local-alloc.c treats 2 references as a
10909 if (place == i3 && i2 != 0 && GET_CODE (XEXP (note, 0)) == REG
10910 && reg_n_refs[REGNO (XEXP (note, 0))]== 2
10911 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
10912 reg_n_refs[REGNO (XEXP (note, 0))] = 3;
10916 for (tem = prev_nonnote_insn (i3);
10918 && (GET_CODE (tem) == INSN || GET_CODE (tem) == CALL_INSN);
10919 tem = prev_nonnote_insn (tem))
10921 /* If the register is being set at TEM, see if that is all
10922 TEM is doing. If so, delete TEM. Otherwise, make this
10923 into a REG_UNUSED note instead. */
10924 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
10926 rtx set = single_set (tem);
10928 /* Verify that it was the set, and not a clobber that
10929 modified the register. */
10931 if (set != 0 && ! side_effects_p (SET_SRC (set))
10932 && (rtx_equal_p (XEXP (note, 0), SET_DEST (set))
10933 || (GET_CODE (SET_DEST (set)) == SUBREG
10934 && rtx_equal_p (XEXP (note, 0),
10935 XEXP (SET_DEST (set), 0)))))
10937 /* Move the notes and links of TEM elsewhere.
10938 This might delete other dead insns recursively.
10939 First set the pattern to something that won't use
10942 PATTERN (tem) = pc_rtx;
10944 distribute_notes (REG_NOTES (tem), tem, tem,
10945 NULL_RTX, NULL_RTX, NULL_RTX);
10946 distribute_links (LOG_LINKS (tem));
10948 PUT_CODE (tem, NOTE);
10949 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
10950 NOTE_SOURCE_FILE (tem) = 0;
10954 PUT_REG_NOTE_KIND (note, REG_UNUSED);
10956 /* If there isn't already a REG_UNUSED note, put one
10958 if (! find_regno_note (tem, REG_UNUSED,
10959 REGNO (XEXP (note, 0))))
10964 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
10965 || (GET_CODE (tem) == CALL_INSN
10966 && find_reg_fusage (tem, USE, XEXP (note, 0))))
10970 /* If we are doing a 3->2 combination, and we have a
10971 register which formerly died in i3 and was not used
10972 by i2, which now no longer dies in i3 and is used in
10973 i2 but does not die in i2, and place is between i2
10974 and i3, then we may need to move a link from place to
10976 if (i2 && INSN_UID (place) <= max_uid_cuid
10977 && INSN_CUID (place) > INSN_CUID (i2)
10978 && from_insn && INSN_CUID (from_insn) > INSN_CUID (i2)
10979 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
10981 rtx links = LOG_LINKS (place);
10982 LOG_LINKS (place) = 0;
10983 distribute_links (links);
10989 /* If we haven't found an insn for the death note and it
10990 is still a REG_DEAD note, but we have hit a CODE_LABEL,
10991 insert a USE insn for the register at that label and
10992 put the death node there. This prevents problems with
10993 call-state tracking in caller-save.c. */
10994 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0 && tem != 0)
10997 = emit_insn_after (gen_rtx (USE, VOIDmode, XEXP (note, 0)),
11000 /* If this insn was emitted between blocks, then update
11001 basic_block_head of the current block to include it. */
11002 if (basic_block_end[this_basic_block - 1] == tem)
11003 basic_block_head[this_basic_block] = place;
11007 /* If the register is set or already dead at PLACE, we needn't do
11008 anything with this note if it is still a REG_DEAD note.
11010 Note that we cannot use just `dead_or_set_p' here since we can
11011 convert an assignment to a register into a bit-field assignment.
11012 Therefore, we must also omit the note if the register is the
11013 target of a bitfield assignment. */
11015 if (place && REG_NOTE_KIND (note) == REG_DEAD)
11017 int regno = REGNO (XEXP (note, 0));
11019 if (dead_or_set_p (place, XEXP (note, 0))
11020 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
11022 /* Unless the register previously died in PLACE, clear
11023 reg_last_death. [I no longer understand why this is
11025 if (reg_last_death[regno] != place)
11026 reg_last_death[regno] = 0;
11030 reg_last_death[regno] = place;
11032 /* If this is a death note for a hard reg that is occupying
11033 multiple registers, ensure that we are still using all
11034 parts of the object. If we find a piece of the object
11035 that is unused, we must add a USE for that piece before
11036 PLACE and put the appropriate REG_DEAD note on it.
11038 An alternative would be to put a REG_UNUSED for the pieces
11039 on the insn that set the register, but that can't be done if
11040 it is not in the same block. It is simpler, though less
11041 efficient, to add the USE insns. */
11043 if (place && regno < FIRST_PSEUDO_REGISTER
11044 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
11047 = regno + HARD_REGNO_NREGS (regno,
11048 GET_MODE (XEXP (note, 0)));
11052 for (i = regno; i < endregno; i++)
11053 if (! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
11054 && ! find_regno_fusage (place, USE, i))
11056 rtx piece = gen_rtx (REG, reg_raw_mode[i], i);
11059 /* See if we already placed a USE note for this
11060 register in front of PLACE. */
11062 GET_CODE (PREV_INSN (p)) == INSN
11063 && GET_CODE (PATTERN (PREV_INSN (p))) == USE;
11065 if (rtx_equal_p (piece,
11066 XEXP (PATTERN (PREV_INSN (p)), 0)))
11075 = emit_insn_before (gen_rtx (USE, VOIDmode,
11078 REG_NOTES (use_insn)
11079 = gen_rtx (EXPR_LIST, REG_DEAD, piece,
11080 REG_NOTES (use_insn));
11086 /* Check for the case where the register dying partially
11087 overlaps the register set by this insn. */
11089 for (i = regno; i < endregno; i++)
11090 if (dead_or_set_regno_p (place, i))
11098 /* Put only REG_DEAD notes for pieces that are
11099 still used and that are not already dead or set. */
11101 for (i = regno; i < endregno; i++)
11103 rtx piece = gen_rtx (REG, reg_raw_mode[i], i);
11105 if ((reg_referenced_p (piece, PATTERN (place))
11106 || (GET_CODE (place) == CALL_INSN
11107 && find_reg_fusage (place, USE, piece)))
11108 && ! dead_or_set_p (place, piece)
11109 && ! reg_bitfield_target_p (piece,
11111 REG_NOTES (place) = gen_rtx (EXPR_LIST, REG_DEAD,
11113 REG_NOTES (place));
11123 /* Any other notes should not be present at this point in the
11130 XEXP (note, 1) = REG_NOTES (place);
11131 REG_NOTES (place) = note;
11133 else if ((REG_NOTE_KIND (note) == REG_DEAD
11134 || REG_NOTE_KIND (note) == REG_UNUSED)
11135 && GET_CODE (XEXP (note, 0)) == REG)
11136 reg_n_deaths[REGNO (XEXP (note, 0))]--;
11140 if ((REG_NOTE_KIND (note) == REG_DEAD
11141 || REG_NOTE_KIND (note) == REG_UNUSED)
11142 && GET_CODE (XEXP (note, 0)) == REG)
11143 reg_n_deaths[REGNO (XEXP (note, 0))]++;
11145 REG_NOTES (place2) = gen_rtx (GET_CODE (note), REG_NOTE_KIND (note),
11146 XEXP (note, 0), REG_NOTES (place2));
11151 /* Similarly to above, distribute the LOG_LINKS that used to be present on
11152 I3, I2, and I1 to new locations. This is also called in one case to
11153 add a link pointing at I3 when I3's destination is changed. */
11156 distribute_links (links)
11159 rtx link, next_link;
11161 for (link = links; link; link = next_link)
11167 next_link = XEXP (link, 1);
11169 /* If the insn that this link points to is a NOTE or isn't a single
11170 set, ignore it. In the latter case, it isn't clear what we
11171 can do other than ignore the link, since we can't tell which
11172 register it was for. Such links wouldn't be used by combine
11175 It is not possible for the destination of the target of the link to
11176 have been changed by combine. The only potential of this is if we
11177 replace I3, I2, and I1 by I3 and I2. But in that case the
11178 destination of I2 also remains unchanged. */
11180 if (GET_CODE (XEXP (link, 0)) == NOTE
11181 || (set = single_set (XEXP (link, 0))) == 0)
11184 reg = SET_DEST (set);
11185 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
11186 || GET_CODE (reg) == SIGN_EXTRACT
11187 || GET_CODE (reg) == STRICT_LOW_PART)
11188 reg = XEXP (reg, 0);
11190 /* A LOG_LINK is defined as being placed on the first insn that uses
11191 a register and points to the insn that sets the register. Start
11192 searching at the next insn after the target of the link and stop
11193 when we reach a set of the register or the end of the basic block.
11195 Note that this correctly handles the link that used to point from
11196 I3 to I2. Also note that not much searching is typically done here
11197 since most links don't point very far away. */
11199 for (insn = NEXT_INSN (XEXP (link, 0));
11200 (insn && (this_basic_block == n_basic_blocks - 1
11201 || basic_block_head[this_basic_block + 1] != insn));
11202 insn = NEXT_INSN (insn))
11203 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
11204 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
11206 if (reg_referenced_p (reg, PATTERN (insn)))
11210 else if (GET_CODE (insn) == CALL_INSN
11211 && find_reg_fusage (insn, USE, reg))
11217 /* If we found a place to put the link, place it there unless there
11218 is already a link to the same insn as LINK at that point. */
11224 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
11225 if (XEXP (link2, 0) == XEXP (link, 0))
11230 XEXP (link, 1) = LOG_LINKS (place);
11231 LOG_LINKS (place) = link;
11233 /* Set added_links_insn to the earliest insn we added a
11235 if (added_links_insn == 0
11236 || INSN_CUID (added_links_insn) > INSN_CUID (place))
11237 added_links_insn = place;
11243 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
11249 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
11250 && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE)
11251 insn = NEXT_INSN (insn);
11253 if (INSN_UID (insn) > max_uid_cuid)
11256 return INSN_CUID (insn);
11260 dump_combine_stats (file)
11265 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
11266 combine_attempts, combine_merges, combine_extras, combine_successes);
11270 dump_combine_total_stats (file)
11275 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
11276 total_attempts, total_merges, total_extras, total_successes);