1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 88, 92-97, 1998 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_regnotes) when a
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
84 /* stdio.h must precede rtl.h for FFS. */
90 #include "hard-reg-set.h"
91 #include "basic-block.h"
92 #include "insn-config.h"
93 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
95 #include "insn-flags.h"
96 #include "insn-codes.h"
97 #include "insn-attr.h"
102 /* It is not safe to use ordinary gen_lowpart in combine.
103 Use gen_lowpart_for_combine instead. See comments there. */
104 #define gen_lowpart dont_use_gen_lowpart_you_dummy
106 /* Number of attempts to combine instructions in this function. */
108 static int combine_attempts;
110 /* Number of attempts that got as far as substitution in this function. */
112 static int combine_merges;
114 /* Number of instructions combined with added SETs in this function. */
116 static int combine_extras;
118 /* Number of instructions combined in this function. */
120 static int combine_successes;
122 /* Totals over entire compilation. */
124 static int total_attempts, total_merges, total_extras, total_successes;
126 /* Define a default value for REVERSIBLE_CC_MODE.
127 We can never assume that a condition code mode is safe to reverse unless
128 the md tells us so. */
129 #ifndef REVERSIBLE_CC_MODE
130 #define REVERSIBLE_CC_MODE(MODE) 0
133 /* Vector mapping INSN_UIDs to cuids.
134 The cuids are like uids but increase monotonically always.
135 Combine always uses cuids so that it can compare them.
136 But actually renumbering the uids, which we used to do,
137 proves to be a bad idea because it makes it hard to compare
138 the dumps produced by earlier passes with those from later passes. */
140 static int *uid_cuid;
141 static int max_uid_cuid;
143 /* Get the cuid of an insn. */
145 #define INSN_CUID(INSN) \
146 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
148 /* Maximum register number, which is the size of the tables below. */
150 static int combine_max_regno;
152 /* Record last point of death of (hard or pseudo) register n. */
154 static rtx *reg_last_death;
156 /* Record last point of modification of (hard or pseudo) register n. */
158 static rtx *reg_last_set;
160 /* Record the cuid of the last insn that invalidated memory
161 (anything that writes memory, and subroutine calls, but not pushes). */
163 static int mem_last_set;
165 /* Record the cuid of the last CALL_INSN
166 so we can tell whether a potential combination crosses any calls. */
168 static int last_call_cuid;
170 /* When `subst' is called, this is the insn that is being modified
171 (by combining in a previous insn). The PATTERN of this insn
172 is still the old pattern partially modified and it should not be
173 looked at, but this may be used to examine the successors of the insn
174 to judge whether a simplification is valid. */
176 static rtx subst_insn;
178 /* This is an insn that belongs before subst_insn, but is not currently
179 on the insn chain. */
181 static rtx subst_prev_insn;
183 /* This is the lowest CUID that `subst' is currently dealing with.
184 get_last_value will not return a value if the register was set at or
185 after this CUID. If not for this mechanism, we could get confused if
186 I2 or I1 in try_combine were an insn that used the old value of a register
187 to obtain a new value. In that case, we might erroneously get the
188 new value of the register when we wanted the old one. */
190 static int subst_low_cuid;
192 /* This contains any hard registers that are used in newpat; reg_dead_at_p
193 must consider all these registers to be always live. */
195 static HARD_REG_SET newpat_used_regs;
197 /* This is an insn to which a LOG_LINKS entry has been added. If this
198 insn is the earlier than I2 or I3, combine should rescan starting at
201 static rtx added_links_insn;
203 /* Basic block number of the block in which we are performing combines. */
204 static int this_basic_block;
206 /* The next group of arrays allows the recording of the last value assigned
207 to (hard or pseudo) register n. We use this information to see if a
208 operation being processed is redundant given a prior operation performed
209 on the register. For example, an `and' with a constant is redundant if
210 all the zero bits are already known to be turned off.
212 We use an approach similar to that used by cse, but change it in the
215 (1) We do not want to reinitialize at each label.
216 (2) It is useful, but not critical, to know the actual value assigned
217 to a register. Often just its form is helpful.
219 Therefore, we maintain the following arrays:
221 reg_last_set_value the last value assigned
222 reg_last_set_label records the value of label_tick when the
223 register was assigned
224 reg_last_set_table_tick records the value of label_tick when a
225 value using the register is assigned
226 reg_last_set_invalid set to non-zero when it is not valid
227 to use the value of this register in some
230 To understand the usage of these tables, it is important to understand
231 the distinction between the value in reg_last_set_value being valid
232 and the register being validly contained in some other expression in the
235 Entry I in reg_last_set_value is valid if it is non-zero, and either
236 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
238 Register I may validly appear in any expression returned for the value
239 of another register if reg_n_sets[i] is 1. It may also appear in the
240 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
241 reg_last_set_invalid[j] is zero.
243 If an expression is found in the table containing a register which may
244 not validly appear in an expression, the register is replaced by
245 something that won't match, (clobber (const_int 0)).
247 reg_last_set_invalid[i] is set non-zero when register I is being assigned
248 to and reg_last_set_table_tick[i] == label_tick. */
250 /* Record last value assigned to (hard or pseudo) register n. */
252 static rtx *reg_last_set_value;
254 /* Record the value of label_tick when the value for register n is placed in
255 reg_last_set_value[n]. */
257 static int *reg_last_set_label;
259 /* Record the value of label_tick when an expression involving register n
260 is placed in reg_last_set_value. */
262 static int *reg_last_set_table_tick;
264 /* Set non-zero if references to register n in expressions should not be
267 static char *reg_last_set_invalid;
269 /* Incremented for each label. */
271 static int label_tick;
273 /* Some registers that are set more than once and used in more than one
274 basic block are nevertheless always set in similar ways. For example,
275 a QImode register may be loaded from memory in two places on a machine
276 where byte loads zero extend.
278 We record in the following array what we know about the nonzero
279 bits of a register, specifically which bits are known to be zero.
281 If an entry is zero, it means that we don't know anything special. */
283 static unsigned HOST_WIDE_INT *reg_nonzero_bits;
285 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
286 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
288 static enum machine_mode nonzero_bits_mode;
290 /* Nonzero if we know that a register has some leading bits that are always
291 equal to the sign bit. */
293 static char *reg_sign_bit_copies;
295 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
296 It is zero while computing them and after combine has completed. This
297 former test prevents propagating values based on previously set values,
298 which can be incorrect if a variable is modified in a loop. */
300 static int nonzero_sign_valid;
302 /* These arrays are maintained in parallel with reg_last_set_value
303 and are used to store the mode in which the register was last set,
304 the bits that were known to be zero when it was last set, and the
305 number of sign bits copies it was known to have when it was last set. */
307 static enum machine_mode *reg_last_set_mode;
308 static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
309 static char *reg_last_set_sign_bit_copies;
311 /* Record one modification to rtl structure
312 to be undone by storing old_contents into *where.
313 is_int is 1 if the contents are an int. */
319 union {rtx r; int i;} old_contents;
320 union {rtx *r; int *i;} where;
323 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
324 num_undo says how many are currently recorded.
326 storage is nonzero if we must undo the allocation of new storage.
327 The value of storage is what to pass to obfree.
329 other_insn is nonzero if we have modified some other insn in the process
330 of working on subst_insn. It must be verified too.
332 previous_undos is the value of undobuf.undos when we started processing
333 this substitution. This will prevent gen_rtx_combine from re-used a piece
334 from the previous expression. Doing so can produce circular rtl
342 struct undo *previous_undos;
346 static struct undobuf undobuf;
348 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
349 insn. The substitution can be undone by undo_all. If INTO is already
350 set to NEWVAL, do not record this change. Because computing NEWVAL might
351 also call SUBST, we have to compute it before we put anything into
354 #define SUBST(INTO, NEWVAL) \
355 do { rtx _new = (NEWVAL); \
359 _buf = undobuf.frees, undobuf.frees = _buf->next; \
361 _buf = (struct undo *) xmalloc (sizeof (struct undo)); \
364 _buf->where.r = &INTO; \
365 _buf->old_contents.r = INTO; \
367 if (_buf->old_contents.r == INTO) \
368 _buf->next = undobuf.frees, undobuf.frees = _buf; \
370 _buf->next = undobuf.undos, undobuf.undos = _buf; \
373 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
374 for the value of a HOST_WIDE_INT value (including CONST_INT) is
377 #define SUBST_INT(INTO, NEWVAL) \
378 do { struct undo *_buf; \
381 _buf = undobuf.frees, undobuf.frees = _buf->next; \
383 _buf = (struct undo *) xmalloc (sizeof (struct undo)); \
386 _buf->where.i = (int *) &INTO; \
387 _buf->old_contents.i = INTO; \
389 if (_buf->old_contents.i == INTO) \
390 _buf->next = undobuf.frees, undobuf.frees = _buf; \
392 _buf->next = undobuf.undos, undobuf.undos = _buf; \
395 /* Number of times the pseudo being substituted for
396 was found and replaced. */
398 static int n_occurrences;
400 static void init_reg_last_arrays PROTO((void));
401 static void setup_incoming_promotions PROTO((void));
402 static void set_nonzero_bits_and_sign_copies PROTO((rtx, rtx));
403 static int can_combine_p PROTO((rtx, rtx, rtx, rtx, rtx *, rtx *));
404 static int sets_function_arg_p PROTO((rtx));
405 static int combinable_i3pat PROTO((rtx, rtx *, rtx, rtx, int, rtx *));
406 static rtx try_combine PROTO((rtx, rtx, rtx));
407 static void undo_all PROTO((void));
408 static rtx *find_split_point PROTO((rtx *, rtx));
409 static rtx subst PROTO((rtx, rtx, rtx, int, int));
410 static rtx simplify_rtx PROTO((rtx, enum machine_mode, int, int));
411 static rtx simplify_if_then_else PROTO((rtx));
412 static rtx simplify_set PROTO((rtx));
413 static rtx simplify_logical PROTO((rtx, int));
414 static rtx expand_compound_operation PROTO((rtx));
415 static rtx expand_field_assignment PROTO((rtx));
416 static rtx make_extraction PROTO((enum machine_mode, rtx, int, rtx, int,
418 static rtx extract_left_shift PROTO((rtx, int));
419 static rtx make_compound_operation PROTO((rtx, enum rtx_code));
420 static int get_pos_from_mask PROTO((unsigned HOST_WIDE_INT, int *));
421 static rtx force_to_mode PROTO((rtx, enum machine_mode,
422 unsigned HOST_WIDE_INT, rtx, int));
423 static rtx if_then_else_cond PROTO((rtx, rtx *, rtx *));
424 static rtx known_cond PROTO((rtx, enum rtx_code, rtx, rtx));
425 static int rtx_equal_for_field_assignment_p PROTO((rtx, rtx));
426 static rtx make_field_assignment PROTO((rtx));
427 static rtx apply_distributive_law PROTO((rtx));
428 static rtx simplify_and_const_int PROTO((rtx, enum machine_mode, rtx,
429 unsigned HOST_WIDE_INT));
430 static unsigned HOST_WIDE_INT nonzero_bits PROTO((rtx, enum machine_mode));
431 static int num_sign_bit_copies PROTO((rtx, enum machine_mode));
432 static int merge_outer_ops PROTO((enum rtx_code *, HOST_WIDE_INT *,
433 enum rtx_code, HOST_WIDE_INT,
434 enum machine_mode, int *));
435 static rtx simplify_shift_const PROTO((rtx, enum rtx_code, enum machine_mode,
437 static int recog_for_combine PROTO((rtx *, rtx, rtx *, int *));
438 static rtx gen_lowpart_for_combine PROTO((enum machine_mode, rtx));
439 static rtx gen_rtx_combine PVPROTO((enum rtx_code code, enum machine_mode mode,
441 static rtx gen_binary PROTO((enum rtx_code, enum machine_mode,
443 static rtx gen_unary PROTO((enum rtx_code, enum machine_mode,
444 enum machine_mode, rtx));
445 static enum rtx_code simplify_comparison PROTO((enum rtx_code, rtx *, rtx *));
446 static int reversible_comparison_p PROTO((rtx));
447 static void update_table_tick PROTO((rtx));
448 static void record_value_for_reg PROTO((rtx, rtx, rtx));
449 static void record_dead_and_set_regs_1 PROTO((rtx, rtx));
450 static void record_dead_and_set_regs PROTO((rtx));
451 static int get_last_value_validate PROTO((rtx *, rtx, int, int));
452 static rtx get_last_value PROTO((rtx));
453 static int use_crosses_set_p PROTO((rtx, int));
454 static void reg_dead_at_p_1 PROTO((rtx, rtx));
455 static int reg_dead_at_p PROTO((rtx, rtx));
456 static void move_deaths PROTO((rtx, rtx, int, rtx, rtx *));
457 static int reg_bitfield_target_p PROTO((rtx, rtx));
458 static void distribute_notes PROTO((rtx, rtx, rtx, rtx, rtx, rtx));
459 static void distribute_links PROTO((rtx));
460 static void mark_used_regs_combine PROTO((rtx));
461 static int insn_cuid PROTO((rtx));
463 /* Main entry point for combiner. F is the first insn of the function.
464 NREGS is the first unused pseudo-reg number. */
467 combine_instructions (f, nregs)
471 register rtx insn, next;
476 register rtx links, nextlinks;
478 combine_attempts = 0;
481 combine_successes = 0;
482 undobuf.undos = undobuf.previous_undos = 0;
484 combine_max_regno = nregs;
487 = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT));
488 reg_sign_bit_copies = (char *) alloca (nregs * sizeof (char));
490 bzero ((char *) reg_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
491 bzero (reg_sign_bit_copies, nregs * sizeof (char));
493 reg_last_death = (rtx *) alloca (nregs * sizeof (rtx));
494 reg_last_set = (rtx *) alloca (nregs * sizeof (rtx));
495 reg_last_set_value = (rtx *) alloca (nregs * sizeof (rtx));
496 reg_last_set_table_tick = (int *) alloca (nregs * sizeof (int));
497 reg_last_set_label = (int *) alloca (nregs * sizeof (int));
498 reg_last_set_invalid = (char *) alloca (nregs * sizeof (char));
500 = (enum machine_mode *) alloca (nregs * sizeof (enum machine_mode));
501 reg_last_set_nonzero_bits
502 = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT));
503 reg_last_set_sign_bit_copies
504 = (char *) alloca (nregs * sizeof (char));
506 init_reg_last_arrays ();
508 init_recog_no_volatile ();
510 /* Compute maximum uid value so uid_cuid can be allocated. */
512 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
513 if (INSN_UID (insn) > i)
516 uid_cuid = (int *) alloca ((i + 1) * sizeof (int));
519 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
521 /* Don't use reg_nonzero_bits when computing it. This can cause problems
522 when, for example, we have j <<= 1 in a loop. */
524 nonzero_sign_valid = 0;
526 /* Compute the mapping from uids to cuids.
527 Cuids are numbers assigned to insns, like uids,
528 except that cuids increase monotonically through the code.
530 Scan all SETs and see if we can deduce anything about what
531 bits are known to be zero for some registers and how many copies
532 of the sign bit are known to exist for those registers.
534 Also set any known values so that we can use it while searching
535 for what bits are known to be set. */
539 /* We need to initialize it here, because record_dead_and_set_regs may call
541 subst_prev_insn = NULL_RTX;
543 setup_incoming_promotions ();
545 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
547 uid_cuid[INSN_UID (insn)] = ++i;
551 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
553 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies);
554 record_dead_and_set_regs (insn);
557 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
558 if (REG_NOTE_KIND (links) == REG_INC)
559 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX);
563 if (GET_CODE (insn) == CODE_LABEL)
567 nonzero_sign_valid = 1;
569 /* Now scan all the insns in forward order. */
571 this_basic_block = -1;
575 init_reg_last_arrays ();
576 setup_incoming_promotions ();
578 for (insn = f; insn; insn = next ? next : NEXT_INSN (insn))
582 /* If INSN starts a new basic block, update our basic block number. */
583 if (this_basic_block + 1 < n_basic_blocks
584 && basic_block_head[this_basic_block + 1] == insn)
587 if (GET_CODE (insn) == CODE_LABEL)
590 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
592 /* Try this insn with each insn it links back to. */
594 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
595 if ((next = try_combine (insn, XEXP (links, 0), NULL_RTX)) != 0)
598 /* Try each sequence of three linked insns ending with this one. */
600 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
601 for (nextlinks = LOG_LINKS (XEXP (links, 0)); nextlinks;
602 nextlinks = XEXP (nextlinks, 1))
603 if ((next = try_combine (insn, XEXP (links, 0),
604 XEXP (nextlinks, 0))) != 0)
608 /* Try to combine a jump insn that uses CC0
609 with a preceding insn that sets CC0, and maybe with its
610 logical predecessor as well.
611 This is how we make decrement-and-branch insns.
612 We need this special code because data flow connections
613 via CC0 do not get entered in LOG_LINKS. */
615 if (GET_CODE (insn) == JUMP_INSN
616 && (prev = prev_nonnote_insn (insn)) != 0
617 && GET_CODE (prev) == INSN
618 && sets_cc0_p (PATTERN (prev)))
620 if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
623 for (nextlinks = LOG_LINKS (prev); nextlinks;
624 nextlinks = XEXP (nextlinks, 1))
625 if ((next = try_combine (insn, prev,
626 XEXP (nextlinks, 0))) != 0)
630 /* Do the same for an insn that explicitly references CC0. */
631 if (GET_CODE (insn) == INSN
632 && (prev = prev_nonnote_insn (insn)) != 0
633 && GET_CODE (prev) == INSN
634 && sets_cc0_p (PATTERN (prev))
635 && GET_CODE (PATTERN (insn)) == SET
636 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
638 if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
641 for (nextlinks = LOG_LINKS (prev); nextlinks;
642 nextlinks = XEXP (nextlinks, 1))
643 if ((next = try_combine (insn, prev,
644 XEXP (nextlinks, 0))) != 0)
648 /* Finally, see if any of the insns that this insn links to
649 explicitly references CC0. If so, try this insn, that insn,
650 and its predecessor if it sets CC0. */
651 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
652 if (GET_CODE (XEXP (links, 0)) == INSN
653 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
654 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
655 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
656 && GET_CODE (prev) == INSN
657 && sets_cc0_p (PATTERN (prev))
658 && (next = try_combine (insn, XEXP (links, 0), prev)) != 0)
662 /* Try combining an insn with two different insns whose results it
664 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
665 for (nextlinks = XEXP (links, 1); nextlinks;
666 nextlinks = XEXP (nextlinks, 1))
667 if ((next = try_combine (insn, XEXP (links, 0),
668 XEXP (nextlinks, 0))) != 0)
671 if (GET_CODE (insn) != NOTE)
672 record_dead_and_set_regs (insn);
679 total_attempts += combine_attempts;
680 total_merges += combine_merges;
681 total_extras += combine_extras;
682 total_successes += combine_successes;
684 nonzero_sign_valid = 0;
687 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
690 init_reg_last_arrays ()
692 int nregs = combine_max_regno;
694 bzero ((char *) reg_last_death, nregs * sizeof (rtx));
695 bzero ((char *) reg_last_set, nregs * sizeof (rtx));
696 bzero ((char *) reg_last_set_value, nregs * sizeof (rtx));
697 bzero ((char *) reg_last_set_table_tick, nregs * sizeof (int));
698 bzero ((char *) reg_last_set_label, nregs * sizeof (int));
699 bzero (reg_last_set_invalid, nregs * sizeof (char));
700 bzero ((char *) reg_last_set_mode, nregs * sizeof (enum machine_mode));
701 bzero ((char *) reg_last_set_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
702 bzero (reg_last_set_sign_bit_copies, nregs * sizeof (char));
705 /* Set up any promoted values for incoming argument registers. */
708 setup_incoming_promotions ()
710 #ifdef PROMOTE_FUNCTION_ARGS
713 enum machine_mode mode;
715 rtx first = get_insns ();
717 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
718 if (FUNCTION_ARG_REGNO_P (regno)
719 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
722 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
725 gen_rtx_CLOBBER (mode, const0_rtx)));
730 /* Called via note_stores. If X is a pseudo that is narrower than
731 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
733 If we are setting only a portion of X and we can't figure out what
734 portion, assume all bits will be used since we don't know what will
737 Similarly, set how many bits of X are known to be copies of the sign bit
738 at all locations in the function. This is the smallest number implied
742 set_nonzero_bits_and_sign_copies (x, set)
748 if (GET_CODE (x) == REG
749 && REGNO (x) >= FIRST_PSEUDO_REGISTER
750 /* If this register is undefined at the start of the file, we can't
751 say what its contents were. */
752 && ! REGNO_REG_SET_P (basic_block_live_at_start[0], REGNO (x))
753 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
755 if (set == 0 || GET_CODE (set) == CLOBBER)
757 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
758 reg_sign_bit_copies[REGNO (x)] = 1;
762 /* If this is a complex assignment, see if we can convert it into a
763 simple assignment. */
764 set = expand_field_assignment (set);
766 /* If this is a simple assignment, or we have a paradoxical SUBREG,
767 set what we know about X. */
769 if (SET_DEST (set) == x
770 || (GET_CODE (SET_DEST (set)) == SUBREG
771 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
772 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
773 && SUBREG_REG (SET_DEST (set)) == x))
775 rtx src = SET_SRC (set);
777 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
778 /* If X is narrower than a word and SRC is a non-negative
779 constant that would appear negative in the mode of X,
780 sign-extend it for use in reg_nonzero_bits because some
781 machines (maybe most) will actually do the sign-extension
782 and this is the conservative approach.
784 ??? For 2.5, try to tighten up the MD files in this regard
785 instead of this kludge. */
787 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
788 && GET_CODE (src) == CONST_INT
790 && 0 != (INTVAL (src)
792 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
793 src = GEN_INT (INTVAL (src)
794 | ((HOST_WIDE_INT) (-1)
795 << GET_MODE_BITSIZE (GET_MODE (x))));
798 reg_nonzero_bits[REGNO (x)]
799 |= nonzero_bits (src, nonzero_bits_mode);
800 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
801 if (reg_sign_bit_copies[REGNO (x)] == 0
802 || reg_sign_bit_copies[REGNO (x)] > num)
803 reg_sign_bit_copies[REGNO (x)] = num;
807 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
808 reg_sign_bit_copies[REGNO (x)] = 1;
813 /* See if INSN can be combined into I3. PRED and SUCC are optionally
814 insns that were previously combined into I3 or that will be combined
815 into the merger of INSN and I3.
817 Return 0 if the combination is not allowed for any reason.
819 If the combination is allowed, *PDEST will be set to the single
820 destination of INSN and *PSRC to the single source, and this function
824 can_combine_p (insn, i3, pred, succ, pdest, psrc)
831 rtx set = 0, src, dest;
836 int all_adjacent = (succ ? (next_active_insn (insn) == succ
837 && next_active_insn (succ) == i3)
838 : next_active_insn (insn) == i3);
840 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
841 or a PARALLEL consisting of such a SET and CLOBBERs.
843 If INSN has CLOBBER parallel parts, ignore them for our processing.
844 By definition, these happen during the execution of the insn. When it
845 is merged with another insn, all bets are off. If they are, in fact,
846 needed and aren't also supplied in I3, they may be added by
847 recog_for_combine. Otherwise, it won't match.
849 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
852 Get the source and destination of INSN. If more than one, can't
855 if (GET_CODE (PATTERN (insn)) == SET)
856 set = PATTERN (insn);
857 else if (GET_CODE (PATTERN (insn)) == PARALLEL
858 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
860 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
862 rtx elt = XVECEXP (PATTERN (insn), 0, i);
864 switch (GET_CODE (elt))
866 /* This is important to combine floating point insns
869 /* Combining an isolated USE doesn't make sense.
870 We depend here on combinable_i3_pat to reject them. */
871 /* The code below this loop only verifies that the inputs of
872 the SET in INSN do not change. We call reg_set_between_p
873 to verify that the REG in the USE does not change betweeen
875 If the USE in INSN was for a pseudo register, the matching
876 insn pattern will likely match any register; combining this
877 with any other USE would only be safe if we knew that the
878 used registers have identical values, or if there was
879 something to tell them apart, e.g. different modes. For
880 now, we forgo such compilcated tests and simply disallow
881 combining of USES of pseudo registers with any other USE. */
882 if (GET_CODE (XEXP (elt, 0)) == REG
883 && GET_CODE (PATTERN (i3)) == PARALLEL)
885 rtx i3pat = PATTERN (i3);
886 int i = XVECLEN (i3pat, 0) - 1;
887 int regno = REGNO (XEXP (elt, 0));
890 rtx i3elt = XVECEXP (i3pat, 0, i);
891 if (GET_CODE (i3elt) == USE
892 && GET_CODE (XEXP (i3elt, 0)) == REG
893 && (REGNO (XEXP (i3elt, 0)) == regno
894 ? reg_set_between_p (XEXP (elt, 0),
895 PREV_INSN (insn), i3)
896 : regno >= FIRST_PSEUDO_REGISTER))
903 /* We can ignore CLOBBERs. */
908 /* Ignore SETs whose result isn't used but not those that
909 have side-effects. */
910 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
911 && ! side_effects_p (elt))
914 /* If we have already found a SET, this is a second one and
915 so we cannot combine with this insn. */
923 /* Anything else means we can't combine. */
929 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
930 so don't do anything with it. */
931 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
940 set = expand_field_assignment (set);
941 src = SET_SRC (set), dest = SET_DEST (set);
943 /* Don't eliminate a store in the stack pointer. */
944 if (dest == stack_pointer_rtx
945 /* If we couldn't eliminate a field assignment, we can't combine. */
946 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
947 /* Don't combine with an insn that sets a register to itself if it has
948 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
949 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
950 /* Can't merge a function call. */
951 || GET_CODE (src) == CALL
952 /* Don't eliminate a function call argument. */
953 || (GET_CODE (i3) == CALL_INSN
954 && (find_reg_fusage (i3, USE, dest)
955 || (GET_CODE (dest) == REG
956 && REGNO (dest) < FIRST_PSEUDO_REGISTER
957 && global_regs[REGNO (dest)])))
958 /* Don't substitute into an incremented register. */
959 || FIND_REG_INC_NOTE (i3, dest)
960 || (succ && FIND_REG_INC_NOTE (succ, dest))
962 /* Don't combine the end of a libcall into anything. */
963 /* ??? This gives worse code, and appears to be unnecessary, since no
964 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
965 use REG_RETVAL notes for noconflict blocks, but other code here
966 makes sure that those insns don't disappear. */
967 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
969 /* Make sure that DEST is not used after SUCC but before I3. */
970 || (succ && ! all_adjacent
971 && reg_used_between_p (dest, succ, i3))
972 /* Make sure that the value that is to be substituted for the register
973 does not use any registers whose values alter in between. However,
974 If the insns are adjacent, a use can't cross a set even though we
975 think it might (this can happen for a sequence of insns each setting
976 the same destination; reg_last_set of that register might point to
977 a NOTE). If INSN has a REG_EQUIV note, the register is always
978 equivalent to the memory so the substitution is valid even if there
979 are intervening stores. Also, don't move a volatile asm or
980 UNSPEC_VOLATILE across any other insns. */
982 && (((GET_CODE (src) != MEM
983 || ! find_reg_note (insn, REG_EQUIV, src))
984 && use_crosses_set_p (src, INSN_CUID (insn)))
985 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
986 || GET_CODE (src) == UNSPEC_VOLATILE))
987 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
988 better register allocation by not doing the combine. */
989 || find_reg_note (i3, REG_NO_CONFLICT, dest)
990 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
991 /* Don't combine across a CALL_INSN, because that would possibly
992 change whether the life span of some REGs crosses calls or not,
993 and it is a pain to update that information.
994 Exception: if source is a constant, moving it later can't hurt.
995 Accept that special case, because it helps -fforce-addr a lot. */
996 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
999 /* DEST must either be a REG or CC0. */
1000 if (GET_CODE (dest) == REG)
1002 /* If register alignment is being enforced for multi-word items in all
1003 cases except for parameters, it is possible to have a register copy
1004 insn referencing a hard register that is not allowed to contain the
1005 mode being copied and which would not be valid as an operand of most
1006 insns. Eliminate this problem by not combining with such an insn.
1008 Also, on some machines we don't want to extend the life of a hard
1011 This is the same test done in can_combine except that we don't test
1012 if SRC is a CALL operation to permit a hard register with
1013 SMALL_REGISTER_CLASSES, and that we have to take all_adjacent
1016 if (GET_CODE (src) == REG
1017 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1018 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1019 /* Don't extend the life of a hard register unless it is
1020 user variable (if we have few registers) or it can't
1021 fit into the desired register (meaning something special
1023 Also avoid substituting a return register into I3, because
1024 reload can't handle a conflict with constraints of other
1026 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1027 && (! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src))
1028 || (SMALL_REGISTER_CLASSES
1029 && ((! all_adjacent && ! REG_USERVAR_P (src))
1030 || (FUNCTION_VALUE_REGNO_P (REGNO (src))
1031 && ! REG_USERVAR_P (src))))))))
1034 else if (GET_CODE (dest) != CC0)
1037 /* Don't substitute for a register intended as a clobberable operand.
1038 Similarly, don't substitute an expression containing a register that
1039 will be clobbered in I3. */
1040 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1041 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1042 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
1043 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
1045 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
1048 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1049 or not), reject, unless nothing volatile comes between it and I3 */
1051 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1053 /* Make sure succ doesn't contain a volatile reference. */
1054 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1057 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1058 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
1059 && p != succ && volatile_refs_p (PATTERN (p)))
1063 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1064 to be an explicit register variable, and was chosen for a reason. */
1066 if (GET_CODE (src) == ASM_OPERANDS
1067 && GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1070 /* If there are any volatile insns between INSN and I3, reject, because
1071 they might affect machine state. */
1073 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1074 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
1075 && p != succ && volatile_insn_p (PATTERN (p)))
1078 /* If INSN or I2 contains an autoincrement or autodecrement,
1079 make sure that register is not used between there and I3,
1080 and not already used in I3 either.
1081 Also insist that I3 not be a jump; if it were one
1082 and the incremented register were spilled, we would lose. */
1085 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1086 if (REG_NOTE_KIND (link) == REG_INC
1087 && (GET_CODE (i3) == JUMP_INSN
1088 || reg_used_between_p (XEXP (link, 0), insn, i3)
1089 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1094 /* Don't combine an insn that follows a CC0-setting insn.
1095 An insn that uses CC0 must not be separated from the one that sets it.
1096 We do, however, allow I2 to follow a CC0-setting insn if that insn
1097 is passed as I1; in that case it will be deleted also.
1098 We also allow combining in this case if all the insns are adjacent
1099 because that would leave the two CC0 insns adjacent as well.
1100 It would be more logical to test whether CC0 occurs inside I1 or I2,
1101 but that would be much slower, and this ought to be equivalent. */
1103 p = prev_nonnote_insn (insn);
1104 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
1109 /* If we get here, we have passed all the tests and the combination is
1118 /* Check if PAT is an insn - or a part of it - used to set up an
1119 argument for a function in a hard register. */
1122 sets_function_arg_p (pat)
1128 switch (GET_CODE (pat))
1131 return sets_function_arg_p (PATTERN (pat));
1134 for (i = XVECLEN (pat, 0); --i >= 0;)
1135 if (sets_function_arg_p (XVECEXP (pat, 0, i)))
1141 inner_dest = SET_DEST (pat);
1142 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1143 || GET_CODE (inner_dest) == SUBREG
1144 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1145 inner_dest = XEXP (inner_dest, 0);
1147 return (GET_CODE (inner_dest) == REG
1148 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1149 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest)));
1158 /* LOC is the location within I3 that contains its pattern or the component
1159 of a PARALLEL of the pattern. We validate that it is valid for combining.
1161 One problem is if I3 modifies its output, as opposed to replacing it
1162 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1163 so would produce an insn that is not equivalent to the original insns.
1167 (set (reg:DI 101) (reg:DI 100))
1168 (set (subreg:SI (reg:DI 101) 0) <foo>)
1170 This is NOT equivalent to:
1172 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1173 (set (reg:DI 101) (reg:DI 100))])
1175 Not only does this modify 100 (in which case it might still be valid
1176 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1178 We can also run into a problem if I2 sets a register that I1
1179 uses and I1 gets directly substituted into I3 (not via I2). In that
1180 case, we would be getting the wrong value of I2DEST into I3, so we
1181 must reject the combination. This case occurs when I2 and I1 both
1182 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1183 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1184 of a SET must prevent combination from occurring.
1186 On machines where SMALL_REGISTER_CLASSES is non-zero, we don't combine
1187 if the destination of a SET is a hard register that isn't a user
1190 Before doing the above check, we first try to expand a field assignment
1191 into a set of logical operations.
1193 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1194 we place a register that is both set and used within I3. If more than one
1195 such register is detected, we fail.
1197 Return 1 if the combination is valid, zero otherwise. */
1200 combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
1206 rtx *pi3dest_killed;
1210 if (GET_CODE (x) == SET)
1212 rtx set = expand_field_assignment (x);
1213 rtx dest = SET_DEST (set);
1214 rtx src = SET_SRC (set);
1215 rtx inner_dest = dest;
1218 rtx inner_src = src;
1223 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1224 || GET_CODE (inner_dest) == SUBREG
1225 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1226 inner_dest = XEXP (inner_dest, 0);
1228 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1231 while (GET_CODE (inner_src) == STRICT_LOW_PART
1232 || GET_CODE (inner_src) == SUBREG
1233 || GET_CODE (inner_src) == ZERO_EXTRACT)
1234 inner_src = XEXP (inner_src, 0);
1236 /* If it is better that two different modes keep two different pseudos,
1237 avoid combining them. This avoids producing the following pattern
1239 (set (subreg:SI (reg/v:QI 21) 0)
1240 (lshiftrt:SI (reg/v:SI 20)
1242 If that were made, reload could not handle the pair of
1243 reg 20/21, since it would try to get any GENERAL_REGS
1244 but some of them don't handle QImode. */
1246 if (rtx_equal_p (inner_src, i2dest)
1247 && GET_CODE (inner_dest) == REG
1248 && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
1252 /* Check for the case where I3 modifies its output, as
1254 if ((inner_dest != dest
1255 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1256 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1258 /* This is the same test done in can_combine_p except that we
1259 allow a hard register with SMALL_REGISTER_CLASSES if SRC is a
1260 CALL operation. Moreover, we can't test all_adjacent; we don't
1261 have to, since this instruction will stay in place, thus we are
1262 not considering increasing the lifetime of INNER_DEST.
1264 Also, if this insn sets a function argument, combining it with
1265 something that might need a spill could clobber a previous
1266 function argument; the all_adjacent test in can_combine_p also
1267 checks this; here, we do a more specific test for this case. */
1269 || (GET_CODE (inner_dest) == REG
1270 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1271 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1272 GET_MODE (inner_dest))
1273 || (SMALL_REGISTER_CLASSES && GET_CODE (src) != CALL
1274 && ! REG_USERVAR_P (inner_dest)
1275 && (FUNCTION_VALUE_REGNO_P (REGNO (inner_dest))
1276 || (FUNCTION_ARG_REGNO_P (REGNO (inner_dest))
1278 && sets_function_arg_p (prev_nonnote_insn (i3)))))))
1279 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1282 /* If DEST is used in I3, it is being killed in this insn,
1283 so record that for later.
1284 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1285 STACK_POINTER_REGNUM, since these are always considered to be
1286 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1287 if (pi3dest_killed && GET_CODE (dest) == REG
1288 && reg_referenced_p (dest, PATTERN (i3))
1289 && REGNO (dest) != FRAME_POINTER_REGNUM
1290 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1291 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1293 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1294 && (REGNO (dest) != ARG_POINTER_REGNUM
1295 || ! fixed_regs [REGNO (dest)])
1297 && REGNO (dest) != STACK_POINTER_REGNUM)
1299 if (*pi3dest_killed)
1302 *pi3dest_killed = dest;
1306 else if (GET_CODE (x) == PARALLEL)
1310 for (i = 0; i < XVECLEN (x, 0); i++)
1311 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1312 i1_not_in_src, pi3dest_killed))
1319 /* Try to combine the insns I1 and I2 into I3.
1320 Here I1 and I2 appear earlier than I3.
1321 I1 can be zero; then we combine just I2 into I3.
1323 It we are combining three insns and the resulting insn is not recognized,
1324 try splitting it into two insns. If that happens, I2 and I3 are retained
1325 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1328 Return 0 if the combination does not work. Then nothing is changed.
1329 If we did the combination, return the insn at which combine should
1333 try_combine (i3, i2, i1)
1334 register rtx i3, i2, i1;
1336 /* New patterns for I3 and I3, respectively. */
1337 rtx newpat, newi2pat = 0;
1338 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1339 int added_sets_1, added_sets_2;
1340 /* Total number of SETs to put into I3. */
1342 /* Nonzero is I2's body now appears in I3. */
1344 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1345 int insn_code_number, i2_code_number, other_code_number;
1346 /* Contains I3 if the destination of I3 is used in its source, which means
1347 that the old life of I3 is being killed. If that usage is placed into
1348 I2 and not in I3, a REG_DEAD note must be made. */
1349 rtx i3dest_killed = 0;
1350 /* SET_DEST and SET_SRC of I2 and I1. */
1351 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1352 /* PATTERN (I2), or a copy of it in certain cases. */
1354 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1355 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1356 int i1_feeds_i3 = 0;
1357 /* Notes that must be added to REG_NOTES in I3 and I2. */
1358 rtx new_i3_notes, new_i2_notes;
1359 /* Notes that we substituted I3 into I2 instead of the normal case. */
1360 int i3_subst_into_i2 = 0;
1361 /* Notes that I1, I2 or I3 is a MULT operation. */
1363 /* Number of clobbers of SCRATCH we had to add. */
1364 int i3_scratches = 0, i2_scratches = 0, other_scratches = 0;
1371 /* If any of I1, I2, and I3 isn't really an insn, we can't do anything.
1372 This can occur when flow deletes an insn that it has merged into an
1373 auto-increment address. We also can't do anything if I3 has a
1374 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1377 if (GET_RTX_CLASS (GET_CODE (i3)) != 'i'
1378 || GET_RTX_CLASS (GET_CODE (i2)) != 'i'
1379 || (i1 && GET_RTX_CLASS (GET_CODE (i1)) != 'i')
1381 /* ??? This gives worse code, and appears to be unnecessary, since no
1382 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1383 || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1390 undobuf.undos = undobuf.previous_undos = 0;
1391 undobuf.other_insn = 0;
1393 /* Save the current high-water-mark so we can free storage if we didn't
1394 accept this combination. */
1395 undobuf.storage = (char *) oballoc (0);
1397 /* Reset the hard register usage information. */
1398 CLEAR_HARD_REG_SET (newpat_used_regs);
1400 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1401 code below, set I1 to be the earlier of the two insns. */
1402 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1403 temp = i1, i1 = i2, i2 = temp;
1405 added_links_insn = 0;
1407 /* First check for one important special-case that the code below will
1408 not handle. Namely, the case where I1 is zero, I2 has multiple sets,
1409 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1410 we may be able to replace that destination with the destination of I3.
1411 This occurs in the common code where we compute both a quotient and
1412 remainder into a structure, in which case we want to do the computation
1413 directly into the structure to avoid register-register copies.
1415 We make very conservative checks below and only try to handle the
1416 most common cases of this. For example, we only handle the case
1417 where I2 and I3 are adjacent to avoid making difficult register
1420 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1421 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1422 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1423 && (! SMALL_REGISTER_CLASSES
1424 || (GET_CODE (SET_DEST (PATTERN (i3))) != REG
1425 || REGNO (SET_DEST (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1426 || REG_USERVAR_P (SET_DEST (PATTERN (i3)))))
1427 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1428 && GET_CODE (PATTERN (i2)) == PARALLEL
1429 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1430 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1431 below would need to check what is inside (and reg_overlap_mentioned_p
1432 doesn't support those codes anyway). Don't allow those destinations;
1433 the resulting insn isn't likely to be recognized anyway. */
1434 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1435 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1436 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1437 SET_DEST (PATTERN (i3)))
1438 && next_real_insn (i2) == i3)
1440 rtx p2 = PATTERN (i2);
1442 /* Make sure that the destination of I3,
1443 which we are going to substitute into one output of I2,
1444 is not used within another output of I2. We must avoid making this:
1445 (parallel [(set (mem (reg 69)) ...)
1446 (set (reg 69) ...)])
1447 which is not well-defined as to order of actions.
1448 (Besides, reload can't handle output reloads for this.)
1450 The problem can also happen if the dest of I3 is a memory ref,
1451 if another dest in I2 is an indirect memory ref. */
1452 for (i = 0; i < XVECLEN (p2, 0); i++)
1453 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1454 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1455 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1456 SET_DEST (XVECEXP (p2, 0, i))))
1459 if (i == XVECLEN (p2, 0))
1460 for (i = 0; i < XVECLEN (p2, 0); i++)
1461 if (SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1466 subst_low_cuid = INSN_CUID (i2);
1468 added_sets_2 = added_sets_1 = 0;
1469 i2dest = SET_SRC (PATTERN (i3));
1471 /* Replace the dest in I2 with our dest and make the resulting
1472 insn the new pattern for I3. Then skip to where we
1473 validate the pattern. Everything was set up above. */
1474 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1475 SET_DEST (PATTERN (i3)));
1478 i3_subst_into_i2 = 1;
1479 goto validate_replacement;
1484 /* If we have no I1 and I2 looks like:
1485 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1487 make up a dummy I1 that is
1490 (set (reg:CC X) (compare:CC Y (const_int 0)))
1492 (We can ignore any trailing CLOBBERs.)
1494 This undoes a previous combination and allows us to match a branch-and-
1497 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1498 && XVECLEN (PATTERN (i2), 0) >= 2
1499 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1500 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1502 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1503 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1504 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1505 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1506 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1507 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1509 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1510 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1515 /* We make I1 with the same INSN_UID as I2. This gives it
1516 the same INSN_CUID for value tracking. Our fake I1 will
1517 never appear in the insn stream so giving it the same INSN_UID
1518 as I2 will not cause a problem. */
1520 subst_prev_insn = i1
1521 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1522 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
1525 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1526 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1527 SET_DEST (PATTERN (i1)));
1532 /* Verify that I2 and I1 are valid for combining. */
1533 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1534 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1540 /* Record whether I2DEST is used in I2SRC and similarly for the other
1541 cases. Knowing this will help in register status updating below. */
1542 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1543 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1544 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1546 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1548 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1550 /* Ensure that I3's pattern can be the destination of combines. */
1551 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1552 i1 && i2dest_in_i1src && i1_feeds_i3,
1559 /* See if any of the insns is a MULT operation. Unless one is, we will
1560 reject a combination that is, since it must be slower. Be conservative
1562 if (GET_CODE (i2src) == MULT
1563 || (i1 != 0 && GET_CODE (i1src) == MULT)
1564 || (GET_CODE (PATTERN (i3)) == SET
1565 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1568 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1569 We used to do this EXCEPT in one case: I3 has a post-inc in an
1570 output operand. However, that exception can give rise to insns like
1572 which is a famous insn on the PDP-11 where the value of r3 used as the
1573 source was model-dependent. Avoid this sort of thing. */
1576 if (!(GET_CODE (PATTERN (i3)) == SET
1577 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1578 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1579 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1580 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1581 /* It's not the exception. */
1584 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1585 if (REG_NOTE_KIND (link) == REG_INC
1586 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1588 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1595 /* See if the SETs in I1 or I2 need to be kept around in the merged
1596 instruction: whenever the value set there is still needed past I3.
1597 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1599 For the SET in I1, we have two cases: If I1 and I2 independently
1600 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1601 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1602 in I1 needs to be kept around unless I1DEST dies or is set in either
1603 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1604 I1DEST. If so, we know I1 feeds into I2. */
1606 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1609 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1610 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1612 /* If the set in I2 needs to be kept around, we must make a copy of
1613 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1614 PATTERN (I2), we are only substituting for the original I1DEST, not into
1615 an already-substituted copy. This also prevents making self-referential
1616 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1619 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1620 ? gen_rtx_SET (VOIDmode, i2dest, i2src)
1624 i2pat = copy_rtx (i2pat);
1628 /* Substitute in the latest insn for the regs set by the earlier ones. */
1630 maxreg = max_reg_num ();
1634 /* It is possible that the source of I2 or I1 may be performing an
1635 unneeded operation, such as a ZERO_EXTEND of something that is known
1636 to have the high part zero. Handle that case by letting subst look at
1637 the innermost one of them.
1639 Another way to do this would be to have a function that tries to
1640 simplify a single insn instead of merging two or more insns. We don't
1641 do this because of the potential of infinite loops and because
1642 of the potential extra memory required. However, doing it the way
1643 we are is a bit of a kludge and doesn't catch all cases.
1645 But only do this if -fexpensive-optimizations since it slows things down
1646 and doesn't usually win. */
1648 if (flag_expensive_optimizations)
1650 /* Pass pc_rtx so no substitutions are done, just simplifications.
1651 The cases that we are interested in here do not involve the few
1652 cases were is_replaced is checked. */
1655 subst_low_cuid = INSN_CUID (i1);
1656 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1660 subst_low_cuid = INSN_CUID (i2);
1661 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1664 undobuf.previous_undos = undobuf.undos;
1668 /* Many machines that don't use CC0 have insns that can both perform an
1669 arithmetic operation and set the condition code. These operations will
1670 be represented as a PARALLEL with the first element of the vector
1671 being a COMPARE of an arithmetic operation with the constant zero.
1672 The second element of the vector will set some pseudo to the result
1673 of the same arithmetic operation. If we simplify the COMPARE, we won't
1674 match such a pattern and so will generate an extra insn. Here we test
1675 for this case, where both the comparison and the operation result are
1676 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1677 I2SRC. Later we will make the PARALLEL that contains I2. */
1679 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1680 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1681 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1682 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1684 #ifdef EXTRA_CC_MODES
1686 enum machine_mode compare_mode;
1689 newpat = PATTERN (i3);
1690 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1694 #ifdef EXTRA_CC_MODES
1695 /* See if a COMPARE with the operand we substituted in should be done
1696 with the mode that is currently being used. If not, do the same
1697 processing we do in `subst' for a SET; namely, if the destination
1698 is used only once, try to replace it with a register of the proper
1699 mode and also replace the COMPARE. */
1700 if (undobuf.other_insn == 0
1701 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1702 &undobuf.other_insn))
1703 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1705 != GET_MODE (SET_DEST (newpat))))
1707 int regno = REGNO (SET_DEST (newpat));
1708 rtx new_dest = gen_rtx_REG (compare_mode, regno);
1710 if (regno < FIRST_PSEUDO_REGISTER
1711 || (REG_N_SETS (regno) == 1 && ! added_sets_2
1712 && ! REG_USERVAR_P (SET_DEST (newpat))))
1714 if (regno >= FIRST_PSEUDO_REGISTER)
1715 SUBST (regno_reg_rtx[regno], new_dest);
1717 SUBST (SET_DEST (newpat), new_dest);
1718 SUBST (XEXP (*cc_use, 0), new_dest);
1719 SUBST (SET_SRC (newpat),
1720 gen_rtx_combine (COMPARE, compare_mode,
1721 i2src, const0_rtx));
1724 undobuf.other_insn = 0;
1731 n_occurrences = 0; /* `subst' counts here */
1733 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1734 need to make a unique copy of I2SRC each time we substitute it
1735 to avoid self-referential rtl. */
1737 subst_low_cuid = INSN_CUID (i2);
1738 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1739 ! i1_feeds_i3 && i1dest_in_i1src);
1740 undobuf.previous_undos = undobuf.undos;
1742 /* Record whether i2's body now appears within i3's body. */
1743 i2_is_used = n_occurrences;
1746 /* If we already got a failure, don't try to do more. Otherwise,
1747 try to substitute in I1 if we have it. */
1749 if (i1 && GET_CODE (newpat) != CLOBBER)
1751 /* Before we can do this substitution, we must redo the test done
1752 above (see detailed comments there) that ensures that I1DEST
1753 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1755 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1763 subst_low_cuid = INSN_CUID (i1);
1764 newpat = subst (newpat, i1dest, i1src, 0, 0);
1765 undobuf.previous_undos = undobuf.undos;
1768 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1769 to count all the ways that I2SRC and I1SRC can be used. */
1770 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
1771 && i2_is_used + added_sets_2 > 1)
1772 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
1773 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
1775 /* Fail if we tried to make a new register (we used to abort, but there's
1776 really no reason to). */
1777 || max_reg_num () != maxreg
1778 /* Fail if we couldn't do something and have a CLOBBER. */
1779 || GET_CODE (newpat) == CLOBBER
1780 /* Fail if this new pattern is a MULT and we didn't have one before
1781 at the outer level. */
1782 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
1789 /* If the actions of the earlier insns must be kept
1790 in addition to substituting them into the latest one,
1791 we must make a new PARALLEL for the latest insn
1792 to hold additional the SETs. */
1794 if (added_sets_1 || added_sets_2)
1798 if (GET_CODE (newpat) == PARALLEL)
1800 rtvec old = XVEC (newpat, 0);
1801 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
1802 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
1803 bcopy ((char *) &old->elem[0], (char *) XVEC (newpat, 0)->elem,
1804 sizeof (old->elem[0]) * old->num_elem);
1809 total_sets = 1 + added_sets_1 + added_sets_2;
1810 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
1811 XVECEXP (newpat, 0, 0) = old;
1815 XVECEXP (newpat, 0, --total_sets)
1816 = (GET_CODE (PATTERN (i1)) == PARALLEL
1817 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
1821 /* If there is no I1, use I2's body as is. We used to also not do
1822 the subst call below if I2 was substituted into I3,
1823 but that could lose a simplification. */
1825 XVECEXP (newpat, 0, --total_sets) = i2pat;
1827 /* See comment where i2pat is assigned. */
1828 XVECEXP (newpat, 0, --total_sets)
1829 = subst (i2pat, i1dest, i1src, 0, 0);
1833 /* We come here when we are replacing a destination in I2 with the
1834 destination of I3. */
1835 validate_replacement:
1837 /* Note which hard regs this insn has as inputs. */
1838 mark_used_regs_combine (newpat);
1840 /* Is the result of combination a valid instruction? */
1842 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
1844 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
1845 the second SET's destination is a register that is unused. In that case,
1846 we just need the first SET. This can occur when simplifying a divmod
1847 insn. We *must* test for this case here because the code below that
1848 splits two independent SETs doesn't handle this case correctly when it
1849 updates the register status. Also check the case where the first
1850 SET's destination is unused. That would not cause incorrect code, but
1851 does cause an unneeded insn to remain. */
1853 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1854 && XVECLEN (newpat, 0) == 2
1855 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1856 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1857 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
1858 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
1859 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
1860 && asm_noperands (newpat) < 0)
1862 newpat = XVECEXP (newpat, 0, 0);
1864 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
1867 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1868 && XVECLEN (newpat, 0) == 2
1869 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1870 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1871 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
1872 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
1873 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
1874 && asm_noperands (newpat) < 0)
1876 newpat = XVECEXP (newpat, 0, 1);
1878 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
1881 /* If we were combining three insns and the result is a simple SET
1882 with no ASM_OPERANDS that wasn't recognized, try to split it into two
1883 insns. There are two ways to do this. It can be split using a
1884 machine-specific method (like when you have an addition of a large
1885 constant) or by combine in the function find_split_point. */
1887 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
1888 && asm_noperands (newpat) < 0)
1890 rtx m_split, *split;
1891 rtx ni2dest = i2dest;
1893 /* See if the MD file can split NEWPAT. If it can't, see if letting it
1894 use I2DEST as a scratch register will help. In the latter case,
1895 convert I2DEST to the mode of the source of NEWPAT if we can. */
1897 m_split = split_insns (newpat, i3);
1899 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
1900 inputs of NEWPAT. */
1902 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
1903 possible to try that as a scratch reg. This would require adding
1904 more code to make it work though. */
1906 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
1908 /* If I2DEST is a hard register or the only use of a pseudo,
1909 we can change its mode. */
1910 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
1911 && GET_MODE (SET_DEST (newpat)) != VOIDmode
1912 && GET_CODE (i2dest) == REG
1913 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
1914 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
1915 && ! REG_USERVAR_P (i2dest))))
1916 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
1919 m_split = split_insns
1920 (gen_rtx_PARALLEL (VOIDmode,
1921 gen_rtvec (2, newpat,
1922 gen_rtx_CLOBBER (VOIDmode,
1927 if (m_split && GET_CODE (m_split) == SEQUENCE
1928 && XVECLEN (m_split, 0) == 2
1929 && (next_real_insn (i2) == i3
1930 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)),
1934 rtx newi3pat = PATTERN (XVECEXP (m_split, 0, 1));
1935 newi2pat = PATTERN (XVECEXP (m_split, 0, 0));
1937 i3set = single_set (XVECEXP (m_split, 0, 1));
1938 i2set = single_set (XVECEXP (m_split, 0, 0));
1940 /* In case we changed the mode of I2DEST, replace it in the
1941 pseudo-register table here. We can't do it above in case this
1942 code doesn't get executed and we do a split the other way. */
1944 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
1945 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
1947 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes,
1950 /* If I2 or I3 has multiple SETs, we won't know how to track
1951 register status, so don't use these insns. If I2's destination
1952 is used between I2 and I3, we also can't use these insns. */
1954 if (i2_code_number >= 0 && i2set && i3set
1955 && (next_real_insn (i2) == i3
1956 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
1957 insn_code_number = recog_for_combine (&newi3pat, i3, &new_i3_notes,
1959 if (insn_code_number >= 0)
1962 /* It is possible that both insns now set the destination of I3.
1963 If so, we must show an extra use of it. */
1965 if (insn_code_number >= 0)
1967 rtx new_i3_dest = SET_DEST (i3set);
1968 rtx new_i2_dest = SET_DEST (i2set);
1970 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
1971 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
1972 || GET_CODE (new_i3_dest) == SUBREG)
1973 new_i3_dest = XEXP (new_i3_dest, 0);
1975 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
1976 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
1977 || GET_CODE (new_i2_dest) == SUBREG)
1978 new_i2_dest = XEXP (new_i2_dest, 0);
1980 if (GET_CODE (new_i3_dest) == REG
1981 && GET_CODE (new_i2_dest) == REG
1982 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
1983 REG_N_SETS (REGNO (new_i2_dest))++;
1987 /* If we can split it and use I2DEST, go ahead and see if that
1988 helps things be recognized. Verify that none of the registers
1989 are set between I2 and I3. */
1990 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
1992 && GET_CODE (i2dest) == REG
1994 /* We need I2DEST in the proper mode. If it is a hard register
1995 or the only use of a pseudo, we can change its mode. */
1996 && (GET_MODE (*split) == GET_MODE (i2dest)
1997 || GET_MODE (*split) == VOIDmode
1998 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
1999 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2000 && ! REG_USERVAR_P (i2dest)))
2001 && (next_real_insn (i2) == i3
2002 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2003 /* We can't overwrite I2DEST if its value is still used by
2005 && ! reg_referenced_p (i2dest, newpat))
2007 rtx newdest = i2dest;
2008 enum rtx_code split_code = GET_CODE (*split);
2009 enum machine_mode split_mode = GET_MODE (*split);
2011 /* Get NEWDEST as a register in the proper mode. We have already
2012 validated that we can do this. */
2013 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2015 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2017 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2018 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
2021 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2022 an ASHIFT. This can occur if it was inside a PLUS and hence
2023 appeared to be a memory address. This is a kludge. */
2024 if (split_code == MULT
2025 && GET_CODE (XEXP (*split, 1)) == CONST_INT
2026 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2028 SUBST (*split, gen_rtx_combine (ASHIFT, split_mode,
2029 XEXP (*split, 0), GEN_INT (i)));
2030 /* Update split_code because we may not have a multiply
2032 split_code = GET_CODE (*split);
2035 #ifdef INSN_SCHEDULING
2036 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2037 be written as a ZERO_EXTEND. */
2038 if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM)
2039 SUBST (*split, gen_rtx_combine (ZERO_EXTEND, split_mode,
2043 newi2pat = gen_rtx_combine (SET, VOIDmode, newdest, *split);
2044 SUBST (*split, newdest);
2046 = recog_for_combine (&newi2pat, i2, &new_i2_notes, &i2_scratches);
2048 /* If the split point was a MULT and we didn't have one before,
2049 don't use one now. */
2050 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2052 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
2056 /* Check for a case where we loaded from memory in a narrow mode and
2057 then sign extended it, but we need both registers. In that case,
2058 we have a PARALLEL with both loads from the same memory location.
2059 We can split this into a load from memory followed by a register-register
2060 copy. This saves at least one insn, more if register allocation can
2063 We cannot do this if the destination of the second assignment is
2064 a register that we have already assumed is zero-extended. Similarly
2065 for a SUBREG of such a register. */
2067 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2068 && GET_CODE (newpat) == PARALLEL
2069 && XVECLEN (newpat, 0) == 2
2070 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2071 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2072 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2073 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2074 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2075 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2077 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2078 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2079 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2080 (GET_CODE (temp) == REG
2081 && reg_nonzero_bits[REGNO (temp)] != 0
2082 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2083 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2084 && (reg_nonzero_bits[REGNO (temp)]
2085 != GET_MODE_MASK (word_mode))))
2086 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2087 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2088 (GET_CODE (temp) == REG
2089 && reg_nonzero_bits[REGNO (temp)] != 0
2090 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2091 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2092 && (reg_nonzero_bits[REGNO (temp)]
2093 != GET_MODE_MASK (word_mode)))))
2094 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2095 SET_SRC (XVECEXP (newpat, 0, 1)))
2096 && ! find_reg_note (i3, REG_UNUSED,
2097 SET_DEST (XVECEXP (newpat, 0, 0))))
2101 newi2pat = XVECEXP (newpat, 0, 0);
2102 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2103 newpat = XVECEXP (newpat, 0, 1);
2104 SUBST (SET_SRC (newpat),
2105 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
2107 = recog_for_combine (&newi2pat, i2, &new_i2_notes, &i2_scratches);
2109 if (i2_code_number >= 0)
2111 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
2113 if (insn_code_number >= 0)
2118 /* If we will be able to accept this, we have made a change to the
2119 destination of I3. This can invalidate a LOG_LINKS pointing
2120 to I3. No other part of combine.c makes such a transformation.
2122 The new I3 will have a destination that was previously the
2123 destination of I1 or I2 and which was used in i2 or I3. Call
2124 distribute_links to make a LOG_LINK from the next use of
2125 that destination. */
2127 PATTERN (i3) = newpat;
2128 distribute_links (gen_rtx_INSN_LIST (VOIDmode, i3, NULL_RTX));
2130 /* I3 now uses what used to be its destination and which is
2131 now I2's destination. That means we need a LOG_LINK from
2132 I3 to I2. But we used to have one, so we still will.
2134 However, some later insn might be using I2's dest and have
2135 a LOG_LINK pointing at I3. We must remove this link.
2136 The simplest way to remove the link is to point it at I1,
2137 which we know will be a NOTE. */
2139 for (insn = NEXT_INSN (i3);
2140 insn && (this_basic_block == n_basic_blocks - 1
2141 || insn != basic_block_head[this_basic_block + 1]);
2142 insn = NEXT_INSN (insn))
2144 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
2145 && reg_referenced_p (ni2dest, PATTERN (insn)))
2147 for (link = LOG_LINKS (insn); link;
2148 link = XEXP (link, 1))
2149 if (XEXP (link, 0) == i3)
2150 XEXP (link, 0) = i1;
2158 /* Similarly, check for a case where we have a PARALLEL of two independent
2159 SETs but we started with three insns. In this case, we can do the sets
2160 as two separate insns. This case occurs when some SET allows two
2161 other insns to combine, but the destination of that SET is still live. */
2163 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2164 && GET_CODE (newpat) == PARALLEL
2165 && XVECLEN (newpat, 0) == 2
2166 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2167 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2168 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2169 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2170 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2171 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2172 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2174 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2175 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2176 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2177 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2178 XVECEXP (newpat, 0, 0))
2179 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2180 XVECEXP (newpat, 0, 1)))
2182 /* Normally, it doesn't matter which of the two is done first,
2183 but it does if one references cc0. In that case, it has to
2186 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2188 newi2pat = XVECEXP (newpat, 0, 0);
2189 newpat = XVECEXP (newpat, 0, 1);
2194 newi2pat = XVECEXP (newpat, 0, 1);
2195 newpat = XVECEXP (newpat, 0, 0);
2199 = recog_for_combine (&newi2pat, i2, &new_i2_notes, &i2_scratches);
2201 if (i2_code_number >= 0)
2203 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
2206 /* If it still isn't recognized, fail and change things back the way they
2208 if ((insn_code_number < 0
2209 /* Is the result a reasonable ASM_OPERANDS? */
2210 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2216 /* If we had to change another insn, make sure it is valid also. */
2217 if (undobuf.other_insn)
2219 rtx other_pat = PATTERN (undobuf.other_insn);
2220 rtx new_other_notes;
2223 CLEAR_HARD_REG_SET (newpat_used_regs);
2226 = recog_for_combine (&other_pat, undobuf.other_insn,
2227 &new_other_notes, &other_scratches);
2229 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2235 PATTERN (undobuf.other_insn) = other_pat;
2237 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2238 are still valid. Then add any non-duplicate notes added by
2239 recog_for_combine. */
2240 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2242 next = XEXP (note, 1);
2244 if (REG_NOTE_KIND (note) == REG_UNUSED
2245 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2247 if (GET_CODE (XEXP (note, 0)) == REG)
2248 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2250 remove_note (undobuf.other_insn, note);
2254 for (note = new_other_notes; note; note = XEXP (note, 1))
2255 if (GET_CODE (XEXP (note, 0)) == REG)
2256 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2258 distribute_notes (new_other_notes, undobuf.other_insn,
2259 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2262 /* We now know that we can do this combination. Merge the insns and
2263 update the status of registers and LOG_LINKS. */
2266 rtx i3notes, i2notes, i1notes = 0;
2267 rtx i3links, i2links, i1links = 0;
2270 /* Compute which registers we expect to eliminate. newi2pat may be setting
2271 either i3dest or i2dest, so we must check it. Also, i1dest may be the
2272 same as i3dest, in which case newi2pat may be setting i1dest. */
2273 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
2274 || i2dest_in_i2src || i2dest_in_i1src
2276 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
2277 || (newi2pat && reg_set_p (i1dest, newi2pat))
2280 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2282 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2283 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2285 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2287 /* Ensure that we do not have something that should not be shared but
2288 occurs multiple times in the new insns. Check this by first
2289 resetting all the `used' flags and then copying anything is shared. */
2291 reset_used_flags (i3notes);
2292 reset_used_flags (i2notes);
2293 reset_used_flags (i1notes);
2294 reset_used_flags (newpat);
2295 reset_used_flags (newi2pat);
2296 if (undobuf.other_insn)
2297 reset_used_flags (PATTERN (undobuf.other_insn));
2299 i3notes = copy_rtx_if_shared (i3notes);
2300 i2notes = copy_rtx_if_shared (i2notes);
2301 i1notes = copy_rtx_if_shared (i1notes);
2302 newpat = copy_rtx_if_shared (newpat);
2303 newi2pat = copy_rtx_if_shared (newi2pat);
2304 if (undobuf.other_insn)
2305 reset_used_flags (PATTERN (undobuf.other_insn));
2307 INSN_CODE (i3) = insn_code_number;
2308 PATTERN (i3) = newpat;
2309 if (undobuf.other_insn)
2310 INSN_CODE (undobuf.other_insn) = other_code_number;
2312 /* We had one special case above where I2 had more than one set and
2313 we replaced a destination of one of those sets with the destination
2314 of I3. In that case, we have to update LOG_LINKS of insns later
2315 in this basic block. Note that this (expensive) case is rare.
2317 Also, in this case, we must pretend that all REG_NOTEs for I2
2318 actually came from I3, so that REG_UNUSED notes from I2 will be
2319 properly handled. */
2321 if (i3_subst_into_i2)
2323 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2324 if (GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
2325 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2326 && ! find_reg_note (i2, REG_UNUSED,
2327 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2328 for (temp = NEXT_INSN (i2);
2329 temp && (this_basic_block == n_basic_blocks - 1
2330 || basic_block_head[this_basic_block] != temp);
2331 temp = NEXT_INSN (temp))
2332 if (temp != i3 && GET_RTX_CLASS (GET_CODE (temp)) == 'i')
2333 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2334 if (XEXP (link, 0) == i2)
2335 XEXP (link, 0) = i3;
2340 while (XEXP (link, 1))
2341 link = XEXP (link, 1);
2342 XEXP (link, 1) = i2notes;
2356 INSN_CODE (i2) = i2_code_number;
2357 PATTERN (i2) = newi2pat;
2361 PUT_CODE (i2, NOTE);
2362 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2363 NOTE_SOURCE_FILE (i2) = 0;
2370 PUT_CODE (i1, NOTE);
2371 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2372 NOTE_SOURCE_FILE (i1) = 0;
2375 /* Get death notes for everything that is now used in either I3 or
2376 I2 and used to die in a previous insn. If we built two new
2377 patterns, move from I1 to I2 then I2 to I3 so that we get the
2378 proper movement on registers that I2 modifies. */
2382 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2383 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2386 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2389 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2391 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
2394 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
2397 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
2400 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2403 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2404 know these are REG_UNUSED and want them to go to the desired insn,
2405 so we always pass it as i3. We have not counted the notes in
2406 reg_n_deaths yet, so we need to do so now. */
2408 if (newi2pat && new_i2_notes)
2410 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2411 if (GET_CODE (XEXP (temp, 0)) == REG)
2412 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2414 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2419 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2420 if (GET_CODE (XEXP (temp, 0)) == REG)
2421 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2423 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
2426 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2427 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2428 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2429 in that case, it might delete I2. Similarly for I2 and I1.
2430 Show an additional death due to the REG_DEAD note we make here. If
2431 we discard it in distribute_notes, we will decrement it again. */
2435 if (GET_CODE (i3dest_killed) == REG)
2436 REG_N_DEATHS (REGNO (i3dest_killed))++;
2438 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
2439 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2441 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
2443 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2445 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2449 if (i2dest_in_i2src)
2451 if (GET_CODE (i2dest) == REG)
2452 REG_N_DEATHS (REGNO (i2dest))++;
2454 if (newi2pat && reg_set_p (i2dest, newi2pat))
2455 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2456 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2458 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2459 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2460 NULL_RTX, NULL_RTX);
2463 if (i1dest_in_i1src)
2465 if (GET_CODE (i1dest) == REG)
2466 REG_N_DEATHS (REGNO (i1dest))++;
2468 if (newi2pat && reg_set_p (i1dest, newi2pat))
2469 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2470 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2472 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2473 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2474 NULL_RTX, NULL_RTX);
2477 distribute_links (i3links);
2478 distribute_links (i2links);
2479 distribute_links (i1links);
2481 if (GET_CODE (i2dest) == REG)
2484 rtx i2_insn = 0, i2_val = 0, set;
2486 /* The insn that used to set this register doesn't exist, and
2487 this life of the register may not exist either. See if one of
2488 I3's links points to an insn that sets I2DEST. If it does,
2489 that is now the last known value for I2DEST. If we don't update
2490 this and I2 set the register to a value that depended on its old
2491 contents, we will get confused. If this insn is used, thing
2492 will be set correctly in combine_instructions. */
2494 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2495 if ((set = single_set (XEXP (link, 0))) != 0
2496 && rtx_equal_p (i2dest, SET_DEST (set)))
2497 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2499 record_value_for_reg (i2dest, i2_insn, i2_val);
2501 /* If the reg formerly set in I2 died only once and that was in I3,
2502 zero its use count so it won't make `reload' do any work. */
2504 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2505 && ! i2dest_in_i2src)
2507 regno = REGNO (i2dest);
2508 REG_N_SETS (regno)--;
2509 if (REG_N_SETS (regno) == 0
2510 && ! REGNO_REG_SET_P (basic_block_live_at_start[0], regno))
2511 REG_N_REFS (regno) = 0;
2515 if (i1 && GET_CODE (i1dest) == REG)
2518 rtx i1_insn = 0, i1_val = 0, set;
2520 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2521 if ((set = single_set (XEXP (link, 0))) != 0
2522 && rtx_equal_p (i1dest, SET_DEST (set)))
2523 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2525 record_value_for_reg (i1dest, i1_insn, i1_val);
2527 regno = REGNO (i1dest);
2528 if (! added_sets_1 && ! i1dest_in_i1src)
2530 REG_N_SETS (regno)--;
2531 if (REG_N_SETS (regno) == 0
2532 && ! REGNO_REG_SET_P (basic_block_live_at_start[0], regno))
2533 REG_N_REFS (regno) = 0;
2537 /* Update reg_nonzero_bits et al for any changes that may have been made
2540 note_stores (newpat, set_nonzero_bits_and_sign_copies);
2542 note_stores (newi2pat, set_nonzero_bits_and_sign_copies);
2544 /* If we added any (clobber (scratch)), add them to the max for a
2545 block. This is a very pessimistic calculation, since we might
2546 have had them already and this might not be the worst block, but
2547 it's not worth doing any better. */
2548 max_scratch += i3_scratches + i2_scratches + other_scratches;
2550 /* If I3 is now an unconditional jump, ensure that it has a
2551 BARRIER following it since it may have initially been a
2552 conditional jump. It may also be the last nonnote insn. */
2554 if ((GET_CODE (newpat) == RETURN || simplejump_p (i3))
2555 && ((temp = next_nonnote_insn (i3)) == NULL_RTX
2556 || GET_CODE (temp) != BARRIER))
2557 emit_barrier_after (i3);
2560 combine_successes++;
2562 /* Clear this here, so that subsequent get_last_value calls are not
2564 subst_prev_insn = NULL_RTX;
2566 if (added_links_insn
2567 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2568 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2569 return added_links_insn;
2571 return newi2pat ? i2 : i3;
2574 /* Undo all the modifications recorded in undobuf. */
2579 struct undo *undo, *next;
2581 for (undo = undobuf.undos; undo; undo = next)
2585 *undo->where.i = undo->old_contents.i;
2587 *undo->where.r = undo->old_contents.r;
2589 undo->next = undobuf.frees;
2590 undobuf.frees = undo;
2593 obfree (undobuf.storage);
2594 undobuf.undos = undobuf.previous_undos = 0;
2596 /* Clear this here, so that subsequent get_last_value calls are not
2598 subst_prev_insn = NULL_RTX;
2601 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2602 where we have an arithmetic expression and return that point. LOC will
2605 try_combine will call this function to see if an insn can be split into
2609 find_split_point (loc, insn)
2614 enum rtx_code code = GET_CODE (x);
2616 int len = 0, pos, unsignedp;
2619 /* First special-case some codes. */
2623 #ifdef INSN_SCHEDULING
2624 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2626 if (GET_CODE (SUBREG_REG (x)) == MEM)
2629 return find_split_point (&SUBREG_REG (x), insn);
2633 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2634 using LO_SUM and HIGH. */
2635 if (GET_CODE (XEXP (x, 0)) == CONST
2636 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2639 gen_rtx_combine (LO_SUM, Pmode,
2640 gen_rtx_combine (HIGH, Pmode, XEXP (x, 0)),
2642 return &XEXP (XEXP (x, 0), 0);
2646 /* If we have a PLUS whose second operand is a constant and the
2647 address is not valid, perhaps will can split it up using
2648 the machine-specific way to split large constants. We use
2649 the first pseudo-reg (one of the virtual regs) as a placeholder;
2650 it will not remain in the result. */
2651 if (GET_CODE (XEXP (x, 0)) == PLUS
2652 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2653 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2655 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2656 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
2659 /* This should have produced two insns, each of which sets our
2660 placeholder. If the source of the second is a valid address,
2661 we can make put both sources together and make a split point
2664 if (seq && XVECLEN (seq, 0) == 2
2665 && GET_CODE (XVECEXP (seq, 0, 0)) == INSN
2666 && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET
2667 && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg
2668 && ! reg_mentioned_p (reg,
2669 SET_SRC (PATTERN (XVECEXP (seq, 0, 0))))
2670 && GET_CODE (XVECEXP (seq, 0, 1)) == INSN
2671 && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET
2672 && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg
2673 && memory_address_p (GET_MODE (x),
2674 SET_SRC (PATTERN (XVECEXP (seq, 0, 1)))))
2676 rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0)));
2677 rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1)));
2679 /* Replace the placeholder in SRC2 with SRC1. If we can
2680 find where in SRC2 it was placed, that can become our
2681 split point and we can replace this address with SRC2.
2682 Just try two obvious places. */
2684 src2 = replace_rtx (src2, reg, src1);
2686 if (XEXP (src2, 0) == src1)
2687 split = &XEXP (src2, 0);
2688 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2689 && XEXP (XEXP (src2, 0), 0) == src1)
2690 split = &XEXP (XEXP (src2, 0), 0);
2694 SUBST (XEXP (x, 0), src2);
2699 /* If that didn't work, perhaps the first operand is complex and
2700 needs to be computed separately, so make a split point there.
2701 This will occur on machines that just support REG + CONST
2702 and have a constant moved through some previous computation. */
2704 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
2705 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
2706 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
2708 return &XEXP (XEXP (x, 0), 0);
2714 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2715 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2716 we need to put the operand into a register. So split at that
2719 if (SET_DEST (x) == cc0_rtx
2720 && GET_CODE (SET_SRC (x)) != COMPARE
2721 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
2722 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
2723 && ! (GET_CODE (SET_SRC (x)) == SUBREG
2724 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
2725 return &SET_SRC (x);
2728 /* See if we can split SET_SRC as it stands. */
2729 split = find_split_point (&SET_SRC (x), insn);
2730 if (split && split != &SET_SRC (x))
2733 /* See if we can split SET_DEST as it stands. */
2734 split = find_split_point (&SET_DEST (x), insn);
2735 if (split && split != &SET_DEST (x))
2738 /* See if this is a bitfield assignment with everything constant. If
2739 so, this is an IOR of an AND, so split it into that. */
2740 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
2741 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
2742 <= HOST_BITS_PER_WIDE_INT)
2743 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
2744 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
2745 && GET_CODE (SET_SRC (x)) == CONST_INT
2746 && ((INTVAL (XEXP (SET_DEST (x), 1))
2747 + INTVAL (XEXP (SET_DEST (x), 2)))
2748 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
2749 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
2751 int pos = INTVAL (XEXP (SET_DEST (x), 2));
2752 int len = INTVAL (XEXP (SET_DEST (x), 1));
2753 int src = INTVAL (SET_SRC (x));
2754 rtx dest = XEXP (SET_DEST (x), 0);
2755 enum machine_mode mode = GET_MODE (dest);
2756 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
2758 if (BITS_BIG_ENDIAN)
2759 pos = GET_MODE_BITSIZE (mode) - len - pos;
2763 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
2766 gen_binary (IOR, mode,
2767 gen_binary (AND, mode, dest,
2768 GEN_INT (~ (mask << pos)
2769 & GET_MODE_MASK (mode))),
2770 GEN_INT (src << pos)));
2772 SUBST (SET_DEST (x), dest);
2774 split = find_split_point (&SET_SRC (x), insn);
2775 if (split && split != &SET_SRC (x))
2779 /* Otherwise, see if this is an operation that we can split into two.
2780 If so, try to split that. */
2781 code = GET_CODE (SET_SRC (x));
2786 /* If we are AND'ing with a large constant that is only a single
2787 bit and the result is only being used in a context where we
2788 need to know if it is zero or non-zero, replace it with a bit
2789 extraction. This will avoid the large constant, which might
2790 have taken more than one insn to make. If the constant were
2791 not a valid argument to the AND but took only one insn to make,
2792 this is no worse, but if it took more than one insn, it will
2795 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2796 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
2797 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
2798 && GET_CODE (SET_DEST (x)) == REG
2799 && (split = find_single_use (SET_DEST (x), insn, NULL_PTR)) != 0
2800 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
2801 && XEXP (*split, 0) == SET_DEST (x)
2802 && XEXP (*split, 1) == const0_rtx)
2804 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
2805 XEXP (SET_SRC (x), 0),
2806 pos, NULL_RTX, 1, 1, 0, 0);
2807 if (extraction != 0)
2809 SUBST (SET_SRC (x), extraction);
2810 return find_split_point (loc, insn);
2816 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
2817 is known to be on, this can be converted into a NEG of a shift. */
2818 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
2819 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
2820 && 1 <= (pos = exact_log2
2821 (nonzero_bits (XEXP (SET_SRC (x), 0),
2822 GET_MODE (XEXP (SET_SRC (x), 0))))))
2824 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
2827 gen_rtx_combine (NEG, mode,
2828 gen_rtx_combine (LSHIFTRT, mode,
2829 XEXP (SET_SRC (x), 0),
2832 split = find_split_point (&SET_SRC (x), insn);
2833 if (split && split != &SET_SRC (x))
2839 inner = XEXP (SET_SRC (x), 0);
2841 /* We can't optimize if either mode is a partial integer
2842 mode as we don't know how many bits are significant
2844 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
2845 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
2849 len = GET_MODE_BITSIZE (GET_MODE (inner));
2855 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2856 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
2858 inner = XEXP (SET_SRC (x), 0);
2859 len = INTVAL (XEXP (SET_SRC (x), 1));
2860 pos = INTVAL (XEXP (SET_SRC (x), 2));
2862 if (BITS_BIG_ENDIAN)
2863 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
2864 unsignedp = (code == ZERO_EXTRACT);
2872 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
2874 enum machine_mode mode = GET_MODE (SET_SRC (x));
2876 /* For unsigned, we have a choice of a shift followed by an
2877 AND or two shifts. Use two shifts for field sizes where the
2878 constant might be too large. We assume here that we can
2879 always at least get 8-bit constants in an AND insn, which is
2880 true for every current RISC. */
2882 if (unsignedp && len <= 8)
2887 gen_rtx_combine (LSHIFTRT, mode,
2888 gen_lowpart_for_combine (mode, inner),
2890 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
2892 split = find_split_point (&SET_SRC (x), insn);
2893 if (split && split != &SET_SRC (x))
2900 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
2901 gen_rtx_combine (ASHIFT, mode,
2902 gen_lowpart_for_combine (mode, inner),
2903 GEN_INT (GET_MODE_BITSIZE (mode)
2905 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
2907 split = find_split_point (&SET_SRC (x), insn);
2908 if (split && split != &SET_SRC (x))
2913 /* See if this is a simple operation with a constant as the second
2914 operand. It might be that this constant is out of range and hence
2915 could be used as a split point. */
2916 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2917 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2918 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
2919 && CONSTANT_P (XEXP (SET_SRC (x), 1))
2920 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
2921 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
2922 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
2924 return &XEXP (SET_SRC (x), 1);
2926 /* Finally, see if this is a simple operation with its first operand
2927 not in a register. The operation might require this operand in a
2928 register, so return it as a split point. We can always do this
2929 because if the first operand were another operation, we would have
2930 already found it as a split point. */
2931 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2932 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2933 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
2934 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
2935 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
2936 return &XEXP (SET_SRC (x), 0);
2942 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
2943 it is better to write this as (not (ior A B)) so we can split it.
2944 Similarly for IOR. */
2945 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
2948 gen_rtx_combine (NOT, GET_MODE (x),
2949 gen_rtx_combine (code == IOR ? AND : IOR,
2951 XEXP (XEXP (x, 0), 0),
2952 XEXP (XEXP (x, 1), 0))));
2953 return find_split_point (loc, insn);
2956 /* Many RISC machines have a large set of logical insns. If the
2957 second operand is a NOT, put it first so we will try to split the
2958 other operand first. */
2959 if (GET_CODE (XEXP (x, 1)) == NOT)
2961 rtx tem = XEXP (x, 0);
2962 SUBST (XEXP (x, 0), XEXP (x, 1));
2963 SUBST (XEXP (x, 1), tem);
2971 /* Otherwise, select our actions depending on our rtx class. */
2972 switch (GET_RTX_CLASS (code))
2974 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
2976 split = find_split_point (&XEXP (x, 2), insn);
2979 /* ... fall through ... */
2983 split = find_split_point (&XEXP (x, 1), insn);
2986 /* ... fall through ... */
2988 /* Some machines have (and (shift ...) ...) insns. If X is not
2989 an AND, but XEXP (X, 0) is, use it as our split point. */
2990 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
2991 return &XEXP (x, 0);
2993 split = find_split_point (&XEXP (x, 0), insn);
2999 /* Otherwise, we don't have a split point. */
3003 /* Throughout X, replace FROM with TO, and return the result.
3004 The result is TO if X is FROM;
3005 otherwise the result is X, but its contents may have been modified.
3006 If they were modified, a record was made in undobuf so that
3007 undo_all will (among other things) return X to its original state.
3009 If the number of changes necessary is too much to record to undo,
3010 the excess changes are not made, so the result is invalid.
3011 The changes already made can still be undone.
3012 undobuf.num_undo is incremented for such changes, so by testing that
3013 the caller can tell whether the result is valid.
3015 `n_occurrences' is incremented each time FROM is replaced.
3017 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
3019 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
3020 by copying if `n_occurrences' is non-zero. */
3023 subst (x, from, to, in_dest, unique_copy)
3024 register rtx x, from, to;
3028 register enum rtx_code code = GET_CODE (x);
3029 enum machine_mode op0_mode = VOIDmode;
3031 register int len, i;
3034 /* Two expressions are equal if they are identical copies of a shared
3035 RTX or if they are both registers with the same register number
3038 #define COMBINE_RTX_EQUAL_P(X,Y) \
3040 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3041 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3043 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3046 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3049 /* If X and FROM are the same register but different modes, they will
3050 not have been seen as equal above. However, flow.c will make a
3051 LOG_LINKS entry for that case. If we do nothing, we will try to
3052 rerecognize our original insn and, when it succeeds, we will
3053 delete the feeding insn, which is incorrect.
3055 So force this insn not to match in this (rare) case. */
3056 if (! in_dest && code == REG && GET_CODE (from) == REG
3057 && REGNO (x) == REGNO (from))
3058 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3060 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3061 of which may contain things that can be combined. */
3062 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
3065 /* It is possible to have a subexpression appear twice in the insn.
3066 Suppose that FROM is a register that appears within TO.
3067 Then, after that subexpression has been scanned once by `subst',
3068 the second time it is scanned, TO may be found. If we were
3069 to scan TO here, we would find FROM within it and create a
3070 self-referent rtl structure which is completely wrong. */
3071 if (COMBINE_RTX_EQUAL_P (x, to))
3074 len = GET_RTX_LENGTH (code);
3075 fmt = GET_RTX_FORMAT (code);
3077 /* We don't need to process a SET_DEST that is a register, CC0, or PC, so
3078 set up to skip this common case. All other cases where we want to
3079 suppress replacing something inside a SET_SRC are handled via the
3082 && (GET_CODE (SET_DEST (x)) == REG
3083 || GET_CODE (SET_DEST (x)) == CC0
3084 || GET_CODE (SET_DEST (x)) == PC))
3087 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3090 op0_mode = GET_MODE (XEXP (x, 0));
3092 for (i = 0; i < len; i++)
3097 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3099 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3101 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3106 new = subst (XVECEXP (x, i, j), from, to, 0, unique_copy);
3108 /* If this substitution failed, this whole thing fails. */
3109 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3113 SUBST (XVECEXP (x, i, j), new);
3116 else if (fmt[i] == 'e')
3118 if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3120 /* In general, don't install a subreg involving two modes not
3121 tieable. It can worsen register allocation, and can even
3122 make invalid reload insns, since the reg inside may need to
3123 be copied from in the outside mode, and that may be invalid
3124 if it is an fp reg copied in integer mode.
3126 We allow two exceptions to this: It is valid if it is inside
3127 another SUBREG and the mode of that SUBREG and the mode of
3128 the inside of TO is tieable and it is valid if X is a SET
3129 that copies FROM to CC0. */
3130 if (GET_CODE (to) == SUBREG
3131 && ! MODES_TIEABLE_P (GET_MODE (to),
3132 GET_MODE (SUBREG_REG (to)))
3133 && ! (code == SUBREG
3134 && MODES_TIEABLE_P (GET_MODE (x),
3135 GET_MODE (SUBREG_REG (to))))
3137 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3140 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3142 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3146 /* If we are in a SET_DEST, suppress most cases unless we
3147 have gone inside a MEM, in which case we want to
3148 simplify the address. We assume here that things that
3149 are actually part of the destination have their inner
3150 parts in the first expression. This is true for SUBREG,
3151 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3152 things aside from REG and MEM that should appear in a
3154 new = subst (XEXP (x, i), from, to,
3156 && (code == SUBREG || code == STRICT_LOW_PART
3157 || code == ZERO_EXTRACT))
3159 && i == 0), unique_copy);
3161 /* If we found that we will have to reject this combination,
3162 indicate that by returning the CLOBBER ourselves, rather than
3163 an expression containing it. This will speed things up as
3164 well as prevent accidents where two CLOBBERs are considered
3165 to be equal, thus producing an incorrect simplification. */
3167 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3170 SUBST (XEXP (x, i), new);
3174 /* Try to simplify X. If the simplification changed the code, it is likely
3175 that further simplification will help, so loop, but limit the number
3176 of repetitions that will be performed. */
3178 for (i = 0; i < 4; i++)
3180 /* If X is sufficiently simple, don't bother trying to do anything
3182 if (code != CONST_INT && code != REG && code != CLOBBER)
3183 x = simplify_rtx (x, op0_mode, i == 3, in_dest);
3185 if (GET_CODE (x) == code)
3188 code = GET_CODE (x);
3190 /* We no longer know the original mode of operand 0 since we
3191 have changed the form of X) */
3192 op0_mode = VOIDmode;
3198 /* Simplify X, a piece of RTL. We just operate on the expression at the
3199 outer level; call `subst' to simplify recursively. Return the new
3202 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3203 will be the iteration even if an expression with a code different from
3204 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3207 simplify_rtx (x, op0_mode, last, in_dest)
3209 enum machine_mode op0_mode;
3213 enum rtx_code code = GET_CODE (x);
3214 enum machine_mode mode = GET_MODE (x);
3218 /* If this is a commutative operation, put a constant last and a complex
3219 expression first. We don't need to do this for comparisons here. */
3220 if (GET_RTX_CLASS (code) == 'c'
3221 && ((CONSTANT_P (XEXP (x, 0)) && GET_CODE (XEXP (x, 1)) != CONST_INT)
3222 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == 'o'
3223 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')
3224 || (GET_CODE (XEXP (x, 0)) == SUBREG
3225 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o'
3226 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')))
3229 SUBST (XEXP (x, 0), XEXP (x, 1));
3230 SUBST (XEXP (x, 1), temp);
3233 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3234 sign extension of a PLUS with a constant, reverse the order of the sign
3235 extension and the addition. Note that this not the same as the original
3236 code, but overflow is undefined for signed values. Also note that the
3237 PLUS will have been partially moved "inside" the sign-extension, so that
3238 the first operand of X will really look like:
3239 (ashiftrt (plus (ashift A C4) C5) C4).
3241 (plus (ashiftrt (ashift A C4) C2) C4)
3242 and replace the first operand of X with that expression. Later parts
3243 of this function may simplify the expression further.
3245 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3246 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3247 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3249 We do this to simplify address expressions. */
3251 if ((code == PLUS || code == MINUS || code == MULT)
3252 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3253 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3254 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3255 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3256 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3257 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3258 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3259 && (temp = simplify_binary_operation (ASHIFTRT, mode,
3260 XEXP (XEXP (XEXP (x, 0), 0), 1),
3261 XEXP (XEXP (x, 0), 1))) != 0)
3264 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3265 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3266 INTVAL (XEXP (XEXP (x, 0), 1)));
3268 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3269 INTVAL (XEXP (XEXP (x, 0), 1)));
3271 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3274 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3275 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3276 things. Check for cases where both arms are testing the same
3279 Don't do anything if all operands are very simple. */
3281 if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c'
3282 || GET_RTX_CLASS (code) == '<')
3283 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3284 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3285 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3287 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'
3288 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3289 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1))))
3291 || (GET_RTX_CLASS (code) == '1'
3292 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3293 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3294 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3297 rtx cond, true, false;
3299 cond = if_then_else_cond (x, &true, &false);
3301 /* If everything is a comparison, what we have is highly unlikely
3302 to be simpler, so don't use it. */
3303 && ! (GET_RTX_CLASS (code) == '<'
3304 && (GET_RTX_CLASS (GET_CODE (true)) == '<'
3305 || GET_RTX_CLASS (GET_CODE (false)) == '<')))
3307 rtx cop1 = const0_rtx;
3308 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3310 if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<')
3313 /* Simplify the alternative arms; this may collapse the true and
3314 false arms to store-flag values. */
3315 true = subst (true, pc_rtx, pc_rtx, 0, 0);
3316 false = subst (false, pc_rtx, pc_rtx, 0, 0);
3318 /* Restarting if we generate a store-flag expression will cause
3319 us to loop. Just drop through in this case. */
3321 /* If the result values are STORE_FLAG_VALUE and zero, we can
3322 just make the comparison operation. */
3323 if (true == const_true_rtx && false == const0_rtx)
3324 x = gen_binary (cond_code, mode, cond, cop1);
3325 else if (true == const0_rtx && false == const_true_rtx)
3326 x = gen_binary (reverse_condition (cond_code), mode, cond, cop1);
3328 /* Likewise, we can make the negate of a comparison operation
3329 if the result values are - STORE_FLAG_VALUE and zero. */
3330 else if (GET_CODE (true) == CONST_INT
3331 && INTVAL (true) == - STORE_FLAG_VALUE
3332 && false == const0_rtx)
3333 x = gen_unary (NEG, mode, mode,
3334 gen_binary (cond_code, mode, cond, cop1));
3335 else if (GET_CODE (false) == CONST_INT
3336 && INTVAL (false) == - STORE_FLAG_VALUE
3337 && true == const0_rtx)
3338 x = gen_unary (NEG, mode, mode,
3339 gen_binary (reverse_condition (cond_code),
3342 return gen_rtx_IF_THEN_ELSE (mode,
3343 gen_binary (cond_code, VOIDmode,
3347 code = GET_CODE (x);
3348 op0_mode = VOIDmode;
3352 /* Try to fold this expression in case we have constants that weren't
3355 switch (GET_RTX_CLASS (code))
3358 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3361 temp = simplify_relational_operation (code, op0_mode,
3362 XEXP (x, 0), XEXP (x, 1));
3363 #ifdef FLOAT_STORE_FLAG_VALUE
3364 if (temp != 0 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
3365 temp = ((temp == const0_rtx) ? CONST0_RTX (GET_MODE (x))
3366 : immed_real_const_1 (FLOAT_STORE_FLAG_VALUE, GET_MODE (x)));
3371 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3375 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3376 XEXP (x, 1), XEXP (x, 2));
3381 x = temp, code = GET_CODE (temp);
3383 /* First see if we can apply the inverse distributive law. */
3384 if (code == PLUS || code == MINUS
3385 || code == AND || code == IOR || code == XOR)
3387 x = apply_distributive_law (x);
3388 code = GET_CODE (x);
3391 /* If CODE is an associative operation not otherwise handled, see if we
3392 can associate some operands. This can win if they are constants or
3393 if they are logically related (i.e. (a & b) & a. */
3394 if ((code == PLUS || code == MINUS
3395 || code == MULT || code == AND || code == IOR || code == XOR
3396 || code == DIV || code == UDIV
3397 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3398 && INTEGRAL_MODE_P (mode))
3400 if (GET_CODE (XEXP (x, 0)) == code)
3402 rtx other = XEXP (XEXP (x, 0), 0);
3403 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3404 rtx inner_op1 = XEXP (x, 1);
3407 /* Make sure we pass the constant operand if any as the second
3408 one if this is a commutative operation. */
3409 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
3411 rtx tem = inner_op0;
3412 inner_op0 = inner_op1;
3415 inner = simplify_binary_operation (code == MINUS ? PLUS
3416 : code == DIV ? MULT
3417 : code == UDIV ? MULT
3419 mode, inner_op0, inner_op1);
3421 /* For commutative operations, try the other pair if that one
3423 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
3425 other = XEXP (XEXP (x, 0), 1);
3426 inner = simplify_binary_operation (code, mode,
3427 XEXP (XEXP (x, 0), 0),
3432 return gen_binary (code, mode, other, inner);
3436 /* A little bit of algebraic simplification here. */
3440 /* Ensure that our address has any ASHIFTs converted to MULT in case
3441 address-recognizing predicates are called later. */
3442 temp = make_compound_operation (XEXP (x, 0), MEM);
3443 SUBST (XEXP (x, 0), temp);
3447 /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG
3448 is paradoxical. If we can't do that safely, then it becomes
3449 something nonsensical so that this combination won't take place. */
3451 if (GET_CODE (SUBREG_REG (x)) == MEM
3452 && (GET_MODE_SIZE (mode)
3453 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
3455 rtx inner = SUBREG_REG (x);
3456 int endian_offset = 0;
3457 /* Don't change the mode of the MEM
3458 if that would change the meaning of the address. */
3459 if (MEM_VOLATILE_P (SUBREG_REG (x))
3460 || mode_dependent_address_p (XEXP (inner, 0)))
3461 return gen_rtx_CLOBBER (mode, const0_rtx);
3463 if (BYTES_BIG_ENDIAN)
3465 if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
3466 endian_offset += UNITS_PER_WORD - GET_MODE_SIZE (mode);
3467 if (GET_MODE_SIZE (GET_MODE (inner)) < UNITS_PER_WORD)
3468 endian_offset -= (UNITS_PER_WORD
3469 - GET_MODE_SIZE (GET_MODE (inner)));
3471 /* Note if the plus_constant doesn't make a valid address
3472 then this combination won't be accepted. */
3473 x = gen_rtx_MEM (mode,
3474 plus_constant (XEXP (inner, 0),
3475 (SUBREG_WORD (x) * UNITS_PER_WORD
3477 MEM_VOLATILE_P (x) = MEM_VOLATILE_P (inner);
3478 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (inner);
3479 MEM_IN_STRUCT_P (x) = MEM_IN_STRUCT_P (inner);
3483 /* If we are in a SET_DEST, these other cases can't apply. */
3487 /* Changing mode twice with SUBREG => just change it once,
3488 or not at all if changing back to starting mode. */
3489 if (GET_CODE (SUBREG_REG (x)) == SUBREG)
3491 if (mode == GET_MODE (SUBREG_REG (SUBREG_REG (x)))
3492 && SUBREG_WORD (x) == 0 && SUBREG_WORD (SUBREG_REG (x)) == 0)
3493 return SUBREG_REG (SUBREG_REG (x));
3495 SUBST_INT (SUBREG_WORD (x),
3496 SUBREG_WORD (x) + SUBREG_WORD (SUBREG_REG (x)));
3497 SUBST (SUBREG_REG (x), SUBREG_REG (SUBREG_REG (x)));
3500 /* SUBREG of a hard register => just change the register number
3501 and/or mode. If the hard register is not valid in that mode,
3502 suppress this combination. If the hard register is the stack,
3503 frame, or argument pointer, leave this as a SUBREG. */
3505 if (GET_CODE (SUBREG_REG (x)) == REG
3506 && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER
3507 && REGNO (SUBREG_REG (x)) != FRAME_POINTER_REGNUM
3508 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3509 && REGNO (SUBREG_REG (x)) != HARD_FRAME_POINTER_REGNUM
3511 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3512 && REGNO (SUBREG_REG (x)) != ARG_POINTER_REGNUM
3514 && REGNO (SUBREG_REG (x)) != STACK_POINTER_REGNUM)
3516 if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x)) + SUBREG_WORD (x),
3518 return gen_rtx_REG (mode,
3519 REGNO (SUBREG_REG (x)) + SUBREG_WORD (x));
3521 return gen_rtx_CLOBBER (mode, const0_rtx);
3524 /* For a constant, try to pick up the part we want. Handle a full
3525 word and low-order part. Only do this if we are narrowing
3526 the constant; if it is being widened, we have no idea what
3527 the extra bits will have been set to. */
3529 if (CONSTANT_P (SUBREG_REG (x)) && op0_mode != VOIDmode
3530 && GET_MODE_SIZE (mode) == UNITS_PER_WORD
3531 && GET_MODE_SIZE (op0_mode) > UNITS_PER_WORD
3532 && GET_MODE_CLASS (mode) == MODE_INT)
3534 temp = operand_subword (SUBREG_REG (x), SUBREG_WORD (x),
3540 /* If we want a subreg of a constant, at offset 0,
3541 take the low bits. On a little-endian machine, that's
3542 always valid. On a big-endian machine, it's valid
3543 only if the constant's mode fits in one word. Note that we
3544 cannot use subreg_lowpart_p since SUBREG_REG may be VOIDmode. */
3545 if (CONSTANT_P (SUBREG_REG (x))
3546 && ((GET_MODE_SIZE (op0_mode) <= UNITS_PER_WORD
3547 || ! WORDS_BIG_ENDIAN)
3548 ? SUBREG_WORD (x) == 0
3550 == ((GET_MODE_SIZE (op0_mode)
3551 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
3553 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (op0_mode)
3554 && (! WORDS_BIG_ENDIAN
3555 || GET_MODE_BITSIZE (op0_mode) <= BITS_PER_WORD))
3556 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3558 /* A paradoxical SUBREG of a VOIDmode constant is the same constant,
3559 since we are saying that the high bits don't matter. */
3560 if (CONSTANT_P (SUBREG_REG (x)) && GET_MODE (SUBREG_REG (x)) == VOIDmode
3561 && GET_MODE_SIZE (mode) > GET_MODE_SIZE (op0_mode))
3562 return SUBREG_REG (x);
3564 /* Note that we cannot do any narrowing for non-constants since
3565 we might have been counting on using the fact that some bits were
3566 zero. We now do this in the SET. */
3571 /* (not (plus X -1)) can become (neg X). */
3572 if (GET_CODE (XEXP (x, 0)) == PLUS
3573 && XEXP (XEXP (x, 0), 1) == constm1_rtx)
3574 return gen_rtx_combine (NEG, mode, XEXP (XEXP (x, 0), 0));
3576 /* Similarly, (not (neg X)) is (plus X -1). */
3577 if (GET_CODE (XEXP (x, 0)) == NEG)
3578 return gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0),
3581 /* (not (xor X C)) for C constant is (xor X D) with D = ~ C. */
3582 if (GET_CODE (XEXP (x, 0)) == XOR
3583 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3584 && (temp = simplify_unary_operation (NOT, mode,
3585 XEXP (XEXP (x, 0), 1),
3587 return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp);
3589 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3590 other than 1, but that is not valid. We could do a similar
3591 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3592 but this doesn't seem common enough to bother with. */
3593 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3594 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3595 return gen_rtx_ROTATE (mode, gen_unary (NOT, mode, mode, const1_rtx),
3596 XEXP (XEXP (x, 0), 1));
3598 if (GET_CODE (XEXP (x, 0)) == SUBREG
3599 && subreg_lowpart_p (XEXP (x, 0))
3600 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3601 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3602 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3603 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3605 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3607 x = gen_rtx_ROTATE (inner_mode,
3608 gen_unary (NOT, inner_mode, inner_mode,
3610 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3611 return gen_lowpart_for_combine (mode, x);
3614 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3615 reversing the comparison code if valid. */
3616 if (STORE_FLAG_VALUE == -1
3617 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3618 && reversible_comparison_p (XEXP (x, 0)))
3619 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
3620 mode, XEXP (XEXP (x, 0), 0),
3621 XEXP (XEXP (x, 0), 1));
3623 /* (ashiftrt foo C) where C is the number of bits in FOO minus 1
3624 is (lt foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3625 perform the above simplification. */
3627 if (STORE_FLAG_VALUE == -1
3628 && XEXP (x, 1) == const1_rtx
3629 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3630 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3631 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3632 return gen_rtx_combine (GE, mode, XEXP (XEXP (x, 0), 0), const0_rtx);
3634 /* Apply De Morgan's laws to reduce number of patterns for machines
3635 with negating logical insns (and-not, nand, etc.). If result has
3636 only one NOT, put it first, since that is how the patterns are
3639 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3641 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3643 if (GET_CODE (in1) == NOT)
3644 in1 = XEXP (in1, 0);
3646 in1 = gen_rtx_combine (NOT, GET_MODE (in1), in1);
3648 if (GET_CODE (in2) == NOT)
3649 in2 = XEXP (in2, 0);
3650 else if (GET_CODE (in2) == CONST_INT
3651 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3652 in2 = GEN_INT (GET_MODE_MASK (mode) & ~ INTVAL (in2));
3654 in2 = gen_rtx_combine (NOT, GET_MODE (in2), in2);
3656 if (GET_CODE (in2) == NOT)
3659 in2 = in1; in1 = tem;
3662 return gen_rtx_combine (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3668 /* (neg (plus X 1)) can become (not X). */
3669 if (GET_CODE (XEXP (x, 0)) == PLUS
3670 && XEXP (XEXP (x, 0), 1) == const1_rtx)
3671 return gen_rtx_combine (NOT, mode, XEXP (XEXP (x, 0), 0));
3673 /* Similarly, (neg (not X)) is (plus X 1). */
3674 if (GET_CODE (XEXP (x, 0)) == NOT)
3675 return plus_constant (XEXP (XEXP (x, 0), 0), 1);
3677 /* (neg (minus X Y)) can become (minus Y X). */
3678 if (GET_CODE (XEXP (x, 0)) == MINUS
3679 && (! FLOAT_MODE_P (mode)
3680 /* x-y != -(y-x) with IEEE floating point. */
3681 || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3683 return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
3684 XEXP (XEXP (x, 0), 0));
3686 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3687 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
3688 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
3689 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3691 /* NEG commutes with ASHIFT since it is multiplication. Only do this
3692 if we can then eliminate the NEG (e.g.,
3693 if the operand is a constant). */
3695 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
3697 temp = simplify_unary_operation (NEG, mode,
3698 XEXP (XEXP (x, 0), 0), mode);
3701 SUBST (XEXP (XEXP (x, 0), 0), temp);
3706 temp = expand_compound_operation (XEXP (x, 0));
3708 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3709 replaced by (lshiftrt X C). This will convert
3710 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3712 if (GET_CODE (temp) == ASHIFTRT
3713 && GET_CODE (XEXP (temp, 1)) == CONST_INT
3714 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
3715 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
3716 INTVAL (XEXP (temp, 1)));
3718 /* If X has only a single bit that might be nonzero, say, bit I, convert
3719 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3720 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
3721 (sign_extract X 1 Y). But only do this if TEMP isn't a register
3722 or a SUBREG of one since we'd be making the expression more
3723 complex if it was just a register. */
3725 if (GET_CODE (temp) != REG
3726 && ! (GET_CODE (temp) == SUBREG
3727 && GET_CODE (SUBREG_REG (temp)) == REG)
3728 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
3730 rtx temp1 = simplify_shift_const
3731 (NULL_RTX, ASHIFTRT, mode,
3732 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
3733 GET_MODE_BITSIZE (mode) - 1 - i),
3734 GET_MODE_BITSIZE (mode) - 1 - i);
3736 /* If all we did was surround TEMP with the two shifts, we
3737 haven't improved anything, so don't use it. Otherwise,
3738 we are better off with TEMP1. */
3739 if (GET_CODE (temp1) != ASHIFTRT
3740 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
3741 || XEXP (XEXP (temp1, 0), 0) != temp)
3747 /* We can't handle truncation to a partial integer mode here
3748 because we don't know the real bitsize of the partial
3750 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
3753 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3754 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
3755 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
3757 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
3758 GET_MODE_MASK (mode), NULL_RTX, 0));
3760 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
3761 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
3762 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
3763 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
3764 return XEXP (XEXP (x, 0), 0);
3766 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
3767 (OP:SI foo:SI) if OP is NEG or ABS. */
3768 if ((GET_CODE (XEXP (x, 0)) == ABS
3769 || GET_CODE (XEXP (x, 0)) == NEG)
3770 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
3771 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
3772 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
3773 return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
3774 XEXP (XEXP (XEXP (x, 0), 0), 0));
3776 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
3778 if (GET_CODE (XEXP (x, 0)) == SUBREG
3779 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
3780 && subreg_lowpart_p (XEXP (x, 0)))
3781 return SUBREG_REG (XEXP (x, 0));
3783 /* If we know that the value is already truncated, we can
3784 replace the TRUNCATE with a SUBREG. */
3785 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
3786 >= GET_MODE_BITSIZE (mode) + 1)
3787 return gen_lowpart_for_combine (mode, XEXP (x, 0));
3789 /* A truncate of a comparison can be replaced with a subreg if
3790 STORE_FLAG_VALUE permits. This is like the previous test,
3791 but it works even if the comparison is done in a mode larger
3792 than HOST_BITS_PER_WIDE_INT. */
3793 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3794 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3795 && ((HOST_WIDE_INT) STORE_FLAG_VALUE &~ GET_MODE_MASK (mode)) == 0)
3796 return gen_lowpart_for_combine (mode, XEXP (x, 0));
3798 /* Similarly, a truncate of a register whose value is a
3799 comparison can be replaced with a subreg if STORE_FLAG_VALUE
3801 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3802 && ((HOST_WIDE_INT) STORE_FLAG_VALUE &~ GET_MODE_MASK (mode)) == 0
3803 && (temp = get_last_value (XEXP (x, 0)))
3804 && GET_RTX_CLASS (GET_CODE (temp)) == '<')
3805 return gen_lowpart_for_combine (mode, XEXP (x, 0));
3809 case FLOAT_TRUNCATE:
3810 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
3811 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
3812 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
3813 return XEXP (XEXP (x, 0), 0);
3815 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
3816 (OP:SF foo:SF) if OP is NEG or ABS. */
3817 if ((GET_CODE (XEXP (x, 0)) == ABS
3818 || GET_CODE (XEXP (x, 0)) == NEG)
3819 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
3820 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
3821 return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
3822 XEXP (XEXP (XEXP (x, 0), 0), 0));
3824 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
3825 is (float_truncate:SF x). */
3826 if (GET_CODE (XEXP (x, 0)) == SUBREG
3827 && subreg_lowpart_p (XEXP (x, 0))
3828 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
3829 return SUBREG_REG (XEXP (x, 0));
3834 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
3835 using cc0, in which case we want to leave it as a COMPARE
3836 so we can distinguish it from a register-register-copy. */
3837 if (XEXP (x, 1) == const0_rtx)
3840 /* In IEEE floating point, x-0 is not the same as x. */
3841 if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3842 || ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0)))
3844 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
3850 /* (const (const X)) can become (const X). Do it this way rather than
3851 returning the inner CONST since CONST can be shared with a
3853 if (GET_CODE (XEXP (x, 0)) == CONST)
3854 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
3859 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
3860 can add in an offset. find_split_point will split this address up
3861 again if it doesn't match. */
3862 if (GET_CODE (XEXP (x, 0)) == HIGH
3863 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
3869 /* If we have (plus (plus (A const) B)), associate it so that CONST is
3870 outermost. That's because that's the way indexed addresses are
3871 supposed to appear. This code used to check many more cases, but
3872 they are now checked elsewhere. */
3873 if (GET_CODE (XEXP (x, 0)) == PLUS
3874 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
3875 return gen_binary (PLUS, mode,
3876 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
3878 XEXP (XEXP (x, 0), 1));
3880 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
3881 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
3882 bit-field and can be replaced by either a sign_extend or a
3883 sign_extract. The `and' may be a zero_extend. */
3884 if (GET_CODE (XEXP (x, 0)) == XOR
3885 && GET_CODE (XEXP (x, 1)) == CONST_INT
3886 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3887 && INTVAL (XEXP (x, 1)) == - INTVAL (XEXP (XEXP (x, 0), 1))
3888 && (i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
3889 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3890 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
3891 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3892 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
3893 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
3894 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
3895 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
3897 return simplify_shift_const
3898 (NULL_RTX, ASHIFTRT, mode,
3899 simplify_shift_const (NULL_RTX, ASHIFT, mode,
3900 XEXP (XEXP (XEXP (x, 0), 0), 0),
3901 GET_MODE_BITSIZE (mode) - (i + 1)),
3902 GET_MODE_BITSIZE (mode) - (i + 1));
3904 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
3905 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
3906 is 1. This produces better code than the alternative immediately
3908 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3909 && reversible_comparison_p (XEXP (x, 0))
3910 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
3911 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx)))
3913 gen_unary (NEG, mode, mode,
3914 gen_binary (reverse_condition (GET_CODE (XEXP (x, 0))),
3915 mode, XEXP (XEXP (x, 0), 0),
3916 XEXP (XEXP (x, 0), 1)));
3918 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
3919 can become (ashiftrt (ashift (xor x 1) C) C) where C is
3920 the bitsize of the mode - 1. This allows simplification of
3921 "a = (b & 8) == 0;" */
3922 if (XEXP (x, 1) == constm1_rtx
3923 && GET_CODE (XEXP (x, 0)) != REG
3924 && ! (GET_CODE (XEXP (x,0)) == SUBREG
3925 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
3926 && nonzero_bits (XEXP (x, 0), mode) == 1)
3927 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
3928 simplify_shift_const (NULL_RTX, ASHIFT, mode,
3929 gen_rtx_combine (XOR, mode,
3930 XEXP (x, 0), const1_rtx),
3931 GET_MODE_BITSIZE (mode) - 1),
3932 GET_MODE_BITSIZE (mode) - 1);
3934 /* If we are adding two things that have no bits in common, convert
3935 the addition into an IOR. This will often be further simplified,
3936 for example in cases like ((a & 1) + (a & 2)), which can
3939 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3940 && (nonzero_bits (XEXP (x, 0), mode)
3941 & nonzero_bits (XEXP (x, 1), mode)) == 0)
3942 return gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
3946 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
3947 by reversing the comparison code if valid. */
3948 if (STORE_FLAG_VALUE == 1
3949 && XEXP (x, 0) == const1_rtx
3950 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
3951 && reversible_comparison_p (XEXP (x, 1)))
3952 return gen_binary (reverse_condition (GET_CODE (XEXP (x, 1))),
3953 mode, XEXP (XEXP (x, 1), 0),
3954 XEXP (XEXP (x, 1), 1));
3956 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
3957 (and <foo> (const_int pow2-1)) */
3958 if (GET_CODE (XEXP (x, 1)) == AND
3959 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
3960 && exact_log2 (- INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
3961 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
3962 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
3963 - INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
3965 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
3967 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
3968 return gen_binary (MINUS, mode,
3969 gen_binary (MINUS, mode, XEXP (x, 0),
3970 XEXP (XEXP (x, 1), 0)),
3971 XEXP (XEXP (x, 1), 1));
3975 /* If we have (mult (plus A B) C), apply the distributive law and then
3976 the inverse distributive law to see if things simplify. This
3977 occurs mostly in addresses, often when unrolling loops. */
3979 if (GET_CODE (XEXP (x, 0)) == PLUS)
3981 x = apply_distributive_law
3982 (gen_binary (PLUS, mode,
3983 gen_binary (MULT, mode,
3984 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
3985 gen_binary (MULT, mode,
3986 XEXP (XEXP (x, 0), 1), XEXP (x, 1))));
3988 if (GET_CODE (x) != MULT)
3994 /* If this is a divide by a power of two, treat it as a shift if
3995 its first operand is a shift. */
3996 if (GET_CODE (XEXP (x, 1)) == CONST_INT
3997 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
3998 && (GET_CODE (XEXP (x, 0)) == ASHIFT
3999 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4000 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4001 || GET_CODE (XEXP (x, 0)) == ROTATE
4002 || GET_CODE (XEXP (x, 0)) == ROTATERT))
4003 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4007 case GT: case GTU: case GE: case GEU:
4008 case LT: case LTU: case LE: case LEU:
4009 /* If the first operand is a condition code, we can't do anything
4011 if (GET_CODE (XEXP (x, 0)) == COMPARE
4012 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4014 && XEXP (x, 0) != cc0_rtx
4018 rtx op0 = XEXP (x, 0);
4019 rtx op1 = XEXP (x, 1);
4020 enum rtx_code new_code;
4022 if (GET_CODE (op0) == COMPARE)
4023 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4025 /* Simplify our comparison, if possible. */
4026 new_code = simplify_comparison (code, &op0, &op1);
4028 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4029 if only the low-order bit is possibly nonzero in X (such as when
4030 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4031 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4032 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4035 Remove any ZERO_EXTRACT we made when thinking this was a
4036 comparison. It may now be simpler to use, e.g., an AND. If a
4037 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4038 the call to make_compound_operation in the SET case. */
4040 if (STORE_FLAG_VALUE == 1
4041 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4042 && op1 == const0_rtx && nonzero_bits (op0, mode) == 1)
4043 return gen_lowpart_for_combine (mode,
4044 expand_compound_operation (op0));
4046 else if (STORE_FLAG_VALUE == 1
4047 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4048 && op1 == const0_rtx
4049 && (num_sign_bit_copies (op0, mode)
4050 == GET_MODE_BITSIZE (mode)))
4052 op0 = expand_compound_operation (op0);
4053 return gen_unary (NEG, mode, mode,
4054 gen_lowpart_for_combine (mode, op0));
4057 else if (STORE_FLAG_VALUE == 1
4058 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4059 && op1 == const0_rtx
4060 && nonzero_bits (op0, mode) == 1)
4062 op0 = expand_compound_operation (op0);
4063 return gen_binary (XOR, mode,
4064 gen_lowpart_for_combine (mode, op0),
4068 else if (STORE_FLAG_VALUE == 1
4069 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4070 && op1 == const0_rtx
4071 && (num_sign_bit_copies (op0, mode)
4072 == GET_MODE_BITSIZE (mode)))
4074 op0 = expand_compound_operation (op0);
4075 return plus_constant (gen_lowpart_for_combine (mode, op0), 1);
4078 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4080 if (STORE_FLAG_VALUE == -1
4081 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4082 && op1 == const0_rtx
4083 && (num_sign_bit_copies (op0, mode)
4084 == GET_MODE_BITSIZE (mode)))
4085 return gen_lowpart_for_combine (mode,
4086 expand_compound_operation (op0));
4088 else if (STORE_FLAG_VALUE == -1
4089 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4090 && op1 == const0_rtx
4091 && nonzero_bits (op0, mode) == 1)
4093 op0 = expand_compound_operation (op0);
4094 return gen_unary (NEG, mode, mode,
4095 gen_lowpart_for_combine (mode, op0));
4098 else if (STORE_FLAG_VALUE == -1
4099 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4100 && op1 == const0_rtx
4101 && (num_sign_bit_copies (op0, mode)
4102 == GET_MODE_BITSIZE (mode)))
4104 op0 = expand_compound_operation (op0);
4105 return gen_unary (NOT, mode, mode,
4106 gen_lowpart_for_combine (mode, op0));
4109 /* If X is 0/1, (eq X 0) is X-1. */
4110 else if (STORE_FLAG_VALUE == -1
4111 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4112 && op1 == const0_rtx
4113 && nonzero_bits (op0, mode) == 1)
4115 op0 = expand_compound_operation (op0);
4116 return plus_constant (gen_lowpart_for_combine (mode, op0), -1);
4119 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4120 one bit that might be nonzero, we can convert (ne x 0) to
4121 (ashift x c) where C puts the bit in the sign bit. Remove any
4122 AND with STORE_FLAG_VALUE when we are done, since we are only
4123 going to test the sign bit. */
4124 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4125 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4126 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4127 == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4128 && op1 == const0_rtx
4129 && mode == GET_MODE (op0)
4130 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4132 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4133 expand_compound_operation (op0),
4134 GET_MODE_BITSIZE (mode) - 1 - i);
4135 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4141 /* If the code changed, return a whole new comparison. */
4142 if (new_code != code)
4143 return gen_rtx_combine (new_code, mode, op0, op1);
4145 /* Otherwise, keep this operation, but maybe change its operands.
4146 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4147 SUBST (XEXP (x, 0), op0);
4148 SUBST (XEXP (x, 1), op1);
4153 return simplify_if_then_else (x);
4159 /* If we are processing SET_DEST, we are done. */
4163 return expand_compound_operation (x);
4166 return simplify_set (x);
4171 return simplify_logical (x, last);
4174 /* (abs (neg <foo>)) -> (abs <foo>) */
4175 if (GET_CODE (XEXP (x, 0)) == NEG)
4176 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4178 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4180 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
4183 /* If operand is something known to be positive, ignore the ABS. */
4184 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4185 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4186 <= HOST_BITS_PER_WIDE_INT)
4187 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4188 & ((HOST_WIDE_INT) 1
4189 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4194 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4195 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4196 return gen_rtx_combine (NEG, mode, XEXP (x, 0));
4201 /* (ffs (*_extend <X>)) = (ffs <X>) */
4202 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4203 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4204 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4208 /* (float (sign_extend <X>)) = (float <X>). */
4209 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4210 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4218 /* If this is a shift by a constant amount, simplify it. */
4219 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4220 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4221 INTVAL (XEXP (x, 1)));
4223 #ifdef SHIFT_COUNT_TRUNCATED
4224 else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG)
4226 force_to_mode (XEXP (x, 1), GET_MODE (x),
4228 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4242 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4245 simplify_if_then_else (x)
4248 enum machine_mode mode = GET_MODE (x);
4249 rtx cond = XEXP (x, 0);
4250 rtx true = XEXP (x, 1);
4251 rtx false = XEXP (x, 2);
4252 enum rtx_code true_code = GET_CODE (cond);
4253 int comparison_p = GET_RTX_CLASS (true_code) == '<';
4257 /* Simplify storing of the truth value. */
4258 if (comparison_p && true == const_true_rtx && false == const0_rtx)
4259 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
4261 /* Also when the truth value has to be reversed. */
4262 if (comparison_p && reversible_comparison_p (cond)
4263 && true == const0_rtx && false == const_true_rtx)
4264 return gen_binary (reverse_condition (true_code),
4265 mode, XEXP (cond, 0), XEXP (cond, 1));
4267 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4268 in it is being compared against certain values. Get the true and false
4269 comparisons and see if that says anything about the value of each arm. */
4271 if (comparison_p && reversible_comparison_p (cond)
4272 && GET_CODE (XEXP (cond, 0)) == REG)
4275 rtx from = XEXP (cond, 0);
4276 enum rtx_code false_code = reverse_condition (true_code);
4277 rtx true_val = XEXP (cond, 1);
4278 rtx false_val = true_val;
4281 /* If FALSE_CODE is EQ, swap the codes and arms. */
4283 if (false_code == EQ)
4285 swapped = 1, true_code = EQ, false_code = NE;
4286 temp = true, true = false, false = temp;
4289 /* If we are comparing against zero and the expression being tested has
4290 only a single bit that might be nonzero, that is its value when it is
4291 not equal to zero. Similarly if it is known to be -1 or 0. */
4293 if (true_code == EQ && true_val == const0_rtx
4294 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4295 false_code = EQ, false_val = GEN_INT (nzb);
4296 else if (true_code == EQ && true_val == const0_rtx
4297 && (num_sign_bit_copies (from, GET_MODE (from))
4298 == GET_MODE_BITSIZE (GET_MODE (from))))
4299 false_code = EQ, false_val = constm1_rtx;
4301 /* Now simplify an arm if we know the value of the register in the
4302 branch and it is used in the arm. Be careful due to the potential
4303 of locally-shared RTL. */
4305 if (reg_mentioned_p (from, true))
4306 true = subst (known_cond (copy_rtx (true), true_code, from, true_val),
4307 pc_rtx, pc_rtx, 0, 0);
4308 if (reg_mentioned_p (from, false))
4309 false = subst (known_cond (copy_rtx (false), false_code,
4311 pc_rtx, pc_rtx, 0, 0);
4313 SUBST (XEXP (x, 1), swapped ? false : true);
4314 SUBST (XEXP (x, 2), swapped ? true : false);
4316 true = XEXP (x, 1), false = XEXP (x, 2), true_code = GET_CODE (cond);
4319 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4320 reversed, do so to avoid needing two sets of patterns for
4321 subtract-and-branch insns. Similarly if we have a constant in the true
4322 arm, the false arm is the same as the first operand of the comparison, or
4323 the false arm is more complicated than the true arm. */
4325 if (comparison_p && reversible_comparison_p (cond)
4327 || (CONSTANT_P (true)
4328 && GET_CODE (false) != CONST_INT && false != pc_rtx)
4329 || true == const0_rtx
4330 || (GET_RTX_CLASS (GET_CODE (true)) == 'o'
4331 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4332 || (GET_CODE (true) == SUBREG
4333 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true))) == 'o'
4334 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4335 || reg_mentioned_p (true, false)
4336 || rtx_equal_p (false, XEXP (cond, 0))))
4338 true_code = reverse_condition (true_code);
4340 gen_binary (true_code, GET_MODE (cond), XEXP (cond, 0),
4343 SUBST (XEXP (x, 1), false);
4344 SUBST (XEXP (x, 2), true);
4346 temp = true, true = false, false = temp, cond = XEXP (x, 0);
4348 /* It is possible that the conditional has been simplified out. */
4349 true_code = GET_CODE (cond);
4350 comparison_p = GET_RTX_CLASS (true_code) == '<';
4353 /* If the two arms are identical, we don't need the comparison. */
4355 if (rtx_equal_p (true, false) && ! side_effects_p (cond))
4358 /* Convert a == b ? b : a to "a". */
4359 if (true_code == EQ && ! side_effects_p (cond)
4360 && rtx_equal_p (XEXP (cond, 0), false)
4361 && rtx_equal_p (XEXP (cond, 1), true))
4363 else if (true_code == NE && ! side_effects_p (cond)
4364 && rtx_equal_p (XEXP (cond, 0), true)
4365 && rtx_equal_p (XEXP (cond, 1), false))
4368 /* Look for cases where we have (abs x) or (neg (abs X)). */
4370 if (GET_MODE_CLASS (mode) == MODE_INT
4371 && GET_CODE (false) == NEG
4372 && rtx_equal_p (true, XEXP (false, 0))
4374 && rtx_equal_p (true, XEXP (cond, 0))
4375 && ! side_effects_p (true))
4380 return gen_unary (ABS, mode, mode, true);
4383 return gen_unary (NEG, mode, mode, gen_unary (ABS, mode, mode, true));
4388 /* Look for MIN or MAX. */
4390 if ((! FLOAT_MODE_P (mode) || flag_fast_math)
4392 && rtx_equal_p (XEXP (cond, 0), true)
4393 && rtx_equal_p (XEXP (cond, 1), false)
4394 && ! side_effects_p (cond))
4399 return gen_binary (SMAX, mode, true, false);
4402 return gen_binary (SMIN, mode, true, false);
4405 return gen_binary (UMAX, mode, true, false);
4408 return gen_binary (UMIN, mode, true, false);
4413 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4414 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4415 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4416 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4417 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4418 neither 1 or -1, but it isn't worth checking for. */
4420 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4421 && comparison_p && mode != VOIDmode && ! side_effects_p (x))
4423 rtx t = make_compound_operation (true, SET);
4424 rtx f = make_compound_operation (false, SET);
4425 rtx cond_op0 = XEXP (cond, 0);
4426 rtx cond_op1 = XEXP (cond, 1);
4427 enum rtx_code op, extend_op = NIL;
4428 enum machine_mode m = mode;
4431 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4432 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4433 || GET_CODE (t) == ASHIFT
4434 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4435 && rtx_equal_p (XEXP (t, 0), f))
4436 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4438 /* If an identity-zero op is commutative, check whether there
4439 would be a match if we swapped the operands. */
4440 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4441 || GET_CODE (t) == XOR)
4442 && rtx_equal_p (XEXP (t, 1), f))
4443 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4444 else if (GET_CODE (t) == SIGN_EXTEND
4445 && (GET_CODE (XEXP (t, 0)) == PLUS
4446 || GET_CODE (XEXP (t, 0)) == MINUS
4447 || GET_CODE (XEXP (t, 0)) == IOR
4448 || GET_CODE (XEXP (t, 0)) == XOR
4449 || GET_CODE (XEXP (t, 0)) == ASHIFT
4450 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4451 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4452 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4453 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4454 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4455 && (num_sign_bit_copies (f, GET_MODE (f))
4456 > (GET_MODE_BITSIZE (mode)
4457 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4459 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4460 extend_op = SIGN_EXTEND;
4461 m = GET_MODE (XEXP (t, 0));
4463 else if (GET_CODE (t) == SIGN_EXTEND
4464 && (GET_CODE (XEXP (t, 0)) == PLUS
4465 || GET_CODE (XEXP (t, 0)) == IOR
4466 || GET_CODE (XEXP (t, 0)) == XOR)
4467 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4468 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4469 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4470 && (num_sign_bit_copies (f, GET_MODE (f))
4471 > (GET_MODE_BITSIZE (mode)
4472 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4474 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4475 extend_op = SIGN_EXTEND;
4476 m = GET_MODE (XEXP (t, 0));
4478 else if (GET_CODE (t) == ZERO_EXTEND
4479 && (GET_CODE (XEXP (t, 0)) == PLUS
4480 || GET_CODE (XEXP (t, 0)) == MINUS
4481 || GET_CODE (XEXP (t, 0)) == IOR
4482 || GET_CODE (XEXP (t, 0)) == XOR
4483 || GET_CODE (XEXP (t, 0)) == ASHIFT
4484 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4485 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4486 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4487 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4488 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4489 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4490 && ((nonzero_bits (f, GET_MODE (f))
4491 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
4494 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4495 extend_op = ZERO_EXTEND;
4496 m = GET_MODE (XEXP (t, 0));
4498 else if (GET_CODE (t) == ZERO_EXTEND
4499 && (GET_CODE (XEXP (t, 0)) == PLUS
4500 || GET_CODE (XEXP (t, 0)) == IOR
4501 || GET_CODE (XEXP (t, 0)) == XOR)
4502 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4503 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4504 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4505 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4506 && ((nonzero_bits (f, GET_MODE (f))
4507 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
4510 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4511 extend_op = ZERO_EXTEND;
4512 m = GET_MODE (XEXP (t, 0));
4517 temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
4518 pc_rtx, pc_rtx, 0, 0);
4519 temp = gen_binary (MULT, m, temp,
4520 gen_binary (MULT, m, c1, const_true_rtx));
4521 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
4522 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
4524 if (extend_op != NIL)
4525 temp = gen_unary (extend_op, mode, m, temp);
4531 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4532 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4533 negation of a single bit, we can convert this operation to a shift. We
4534 can actually do this more generally, but it doesn't seem worth it. */
4536 if (true_code == NE && XEXP (cond, 1) == const0_rtx
4537 && false == const0_rtx && GET_CODE (true) == CONST_INT
4538 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
4539 && (i = exact_log2 (INTVAL (true))) >= 0)
4540 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
4541 == GET_MODE_BITSIZE (mode))
4542 && (i = exact_log2 (- INTVAL (true))) >= 0)))
4544 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4545 gen_lowpart_for_combine (mode, XEXP (cond, 0)), i);
4550 /* Simplify X, a SET expression. Return the new expression. */
4556 rtx src = SET_SRC (x);
4557 rtx dest = SET_DEST (x);
4558 enum machine_mode mode
4559 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
4563 /* (set (pc) (return)) gets written as (return). */
4564 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
4567 /* Now that we know for sure which bits of SRC we are using, see if we can
4568 simplify the expression for the object knowing that we only need the
4571 if (GET_MODE_CLASS (mode) == MODE_INT)
4572 src = force_to_mode (src, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
4574 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4575 the comparison result and try to simplify it unless we already have used
4576 undobuf.other_insn. */
4577 if ((GET_CODE (src) == COMPARE
4582 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
4583 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
4584 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
4585 && rtx_equal_p (XEXP (*cc_use, 0), dest))
4587 enum rtx_code old_code = GET_CODE (*cc_use);
4588 enum rtx_code new_code;
4590 int other_changed = 0;
4591 enum machine_mode compare_mode = GET_MODE (dest);
4593 if (GET_CODE (src) == COMPARE)
4594 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
4596 op0 = src, op1 = const0_rtx;
4598 /* Simplify our comparison, if possible. */
4599 new_code = simplify_comparison (old_code, &op0, &op1);
4601 #ifdef EXTRA_CC_MODES
4602 /* If this machine has CC modes other than CCmode, check to see if we
4603 need to use a different CC mode here. */
4604 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
4605 #endif /* EXTRA_CC_MODES */
4607 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
4608 /* If the mode changed, we have to change SET_DEST, the mode in the
4609 compare, and the mode in the place SET_DEST is used. If SET_DEST is
4610 a hard register, just build new versions with the proper mode. If it
4611 is a pseudo, we lose unless it is only time we set the pseudo, in
4612 which case we can safely change its mode. */
4613 if (compare_mode != GET_MODE (dest))
4615 int regno = REGNO (dest);
4616 rtx new_dest = gen_rtx_REG (compare_mode, regno);
4618 if (regno < FIRST_PSEUDO_REGISTER
4619 || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
4621 if (regno >= FIRST_PSEUDO_REGISTER)
4622 SUBST (regno_reg_rtx[regno], new_dest);
4624 SUBST (SET_DEST (x), new_dest);
4625 SUBST (XEXP (*cc_use, 0), new_dest);
4633 /* If the code changed, we have to build a new comparison in
4634 undobuf.other_insn. */
4635 if (new_code != old_code)
4637 unsigned HOST_WIDE_INT mask;
4639 SUBST (*cc_use, gen_rtx_combine (new_code, GET_MODE (*cc_use),
4642 /* If the only change we made was to change an EQ into an NE or
4643 vice versa, OP0 has only one bit that might be nonzero, and OP1
4644 is zero, check if changing the user of the condition code will
4645 produce a valid insn. If it won't, we can keep the original code
4646 in that insn by surrounding our operation with an XOR. */
4648 if (((old_code == NE && new_code == EQ)
4649 || (old_code == EQ && new_code == NE))
4650 && ! other_changed && op1 == const0_rtx
4651 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
4652 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
4654 rtx pat = PATTERN (other_insn), note = 0;
4657 if ((recog_for_combine (&pat, other_insn, ¬e, &scratches) < 0
4658 && ! check_asm_operands (pat)))
4660 PUT_CODE (*cc_use, old_code);
4663 op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
4671 undobuf.other_insn = other_insn;
4674 /* If we are now comparing against zero, change our source if
4675 needed. If we do not use cc0, we always have a COMPARE. */
4676 if (op1 == const0_rtx && dest == cc0_rtx)
4678 SUBST (SET_SRC (x), op0);
4684 /* Otherwise, if we didn't previously have a COMPARE in the
4685 correct mode, we need one. */
4686 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
4689 gen_rtx_combine (COMPARE, compare_mode, op0, op1));
4694 /* Otherwise, update the COMPARE if needed. */
4695 SUBST (XEXP (src, 0), op0);
4696 SUBST (XEXP (src, 1), op1);
4701 /* Get SET_SRC in a form where we have placed back any
4702 compound expressions. Then do the checks below. */
4703 src = make_compound_operation (src, SET);
4704 SUBST (SET_SRC (x), src);
4707 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
4708 and X being a REG or (subreg (reg)), we may be able to convert this to
4709 (set (subreg:m2 x) (op)).
4711 We can always do this if M1 is narrower than M2 because that means that
4712 we only care about the low bits of the result.
4714 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
4715 perform a narrower operation than requested since the high-order bits will
4716 be undefined. On machine where it is defined, this transformation is safe
4717 as long as M1 and M2 have the same number of words. */
4719 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
4720 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o'
4721 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
4723 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
4724 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
4725 #ifndef WORD_REGISTER_OPERATIONS
4726 && (GET_MODE_SIZE (GET_MODE (src))
4727 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
4729 #ifdef CLASS_CANNOT_CHANGE_SIZE
4730 && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER
4731 && (TEST_HARD_REG_BIT
4732 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE],
4734 && (GET_MODE_SIZE (GET_MODE (src))
4735 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))))
4737 && (GET_CODE (dest) == REG
4738 || (GET_CODE (dest) == SUBREG
4739 && GET_CODE (SUBREG_REG (dest)) == REG)))
4741 SUBST (SET_DEST (x),
4742 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)),
4744 SUBST (SET_SRC (x), SUBREG_REG (src));
4746 src = SET_SRC (x), dest = SET_DEST (x);
4749 #ifdef LOAD_EXTEND_OP
4750 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
4751 would require a paradoxical subreg. Replace the subreg with a
4752 zero_extend to avoid the reload that would otherwise be required. */
4754 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
4755 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
4756 && SUBREG_WORD (src) == 0
4757 && (GET_MODE_SIZE (GET_MODE (src))
4758 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
4759 && GET_CODE (SUBREG_REG (src)) == MEM)
4762 gen_rtx_combine (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
4763 GET_MODE (src), XEXP (src, 0)));
4769 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
4770 are comparing an item known to be 0 or -1 against 0, use a logical
4771 operation instead. Check for one of the arms being an IOR of the other
4772 arm with some value. We compute three terms to be IOR'ed together. In
4773 practice, at most two will be nonzero. Then we do the IOR's. */
4775 if (GET_CODE (dest) != PC
4776 && GET_CODE (src) == IF_THEN_ELSE
4777 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
4778 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
4779 && XEXP (XEXP (src, 0), 1) == const0_rtx
4780 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
4781 #ifdef HAVE_conditional_move
4782 && ! can_conditionally_move_p (GET_MODE (src))
4784 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
4785 GET_MODE (XEXP (XEXP (src, 0), 0)))
4786 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
4787 && ! side_effects_p (src))
4789 rtx true = (GET_CODE (XEXP (src, 0)) == NE
4790 ? XEXP (src, 1) : XEXP (src, 2));
4791 rtx false = (GET_CODE (XEXP (src, 0)) == NE
4792 ? XEXP (src, 2) : XEXP (src, 1));
4793 rtx term1 = const0_rtx, term2, term3;
4795 if (GET_CODE (true) == IOR && rtx_equal_p (XEXP (true, 0), false))
4796 term1 = false, true = XEXP (true, 1), false = const0_rtx;
4797 else if (GET_CODE (true) == IOR
4798 && rtx_equal_p (XEXP (true, 1), false))
4799 term1 = false, true = XEXP (true, 0), false = const0_rtx;
4800 else if (GET_CODE (false) == IOR
4801 && rtx_equal_p (XEXP (false, 0), true))
4802 term1 = true, false = XEXP (false, 1), true = const0_rtx;
4803 else if (GET_CODE (false) == IOR
4804 && rtx_equal_p (XEXP (false, 1), true))
4805 term1 = true, false = XEXP (false, 0), true = const0_rtx;
4807 term2 = gen_binary (AND, GET_MODE (src), XEXP (XEXP (src, 0), 0), true);
4808 term3 = gen_binary (AND, GET_MODE (src),
4809 gen_unary (NOT, GET_MODE (src), GET_MODE (src),
4810 XEXP (XEXP (src, 0), 0)),
4814 gen_binary (IOR, GET_MODE (src),
4815 gen_binary (IOR, GET_MODE (src), term1, term2),
4821 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
4822 whole thing fail. */
4823 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
4825 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
4828 /* Convert this into a field assignment operation, if possible. */
4829 return make_field_assignment (x);
4832 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
4833 result. LAST is nonzero if this is the last retry. */
4836 simplify_logical (x, last)
4840 enum machine_mode mode = GET_MODE (x);
4841 rtx op0 = XEXP (x, 0);
4842 rtx op1 = XEXP (x, 1);
4844 switch (GET_CODE (x))
4847 /* Convert (A ^ B) & A to A & (~ B) since the latter is often a single
4848 insn (and may simplify more). */
4849 if (GET_CODE (op0) == XOR
4850 && rtx_equal_p (XEXP (op0, 0), op1)
4851 && ! side_effects_p (op1))
4852 x = gen_binary (AND, mode,
4853 gen_unary (NOT, mode, mode, XEXP (op0, 1)), op1);
4855 if (GET_CODE (op0) == XOR
4856 && rtx_equal_p (XEXP (op0, 1), op1)
4857 && ! side_effects_p (op1))
4858 x = gen_binary (AND, mode,
4859 gen_unary (NOT, mode, mode, XEXP (op0, 0)), op1);
4861 /* Similarly for (~ (A ^ B)) & A. */
4862 if (GET_CODE (op0) == NOT
4863 && GET_CODE (XEXP (op0, 0)) == XOR
4864 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
4865 && ! side_effects_p (op1))
4866 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
4868 if (GET_CODE (op0) == NOT
4869 && GET_CODE (XEXP (op0, 0)) == XOR
4870 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
4871 && ! side_effects_p (op1))
4872 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
4874 if (GET_CODE (op1) == CONST_INT)
4876 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
4878 /* If we have (ior (and (X C1) C2)) and the next restart would be
4879 the last, simplify this by making C1 as small as possible
4882 && GET_CODE (x) == IOR && GET_CODE (op0) == AND
4883 && GET_CODE (XEXP (op0, 1)) == CONST_INT
4884 && GET_CODE (op1) == CONST_INT)
4885 return gen_binary (IOR, mode,
4886 gen_binary (AND, mode, XEXP (op0, 0),
4887 GEN_INT (INTVAL (XEXP (op0, 1))
4888 & ~ INTVAL (op1))), op1);
4890 if (GET_CODE (x) != AND)
4893 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
4894 || GET_RTX_CLASS (GET_CODE (x)) == '2')
4895 op0 = XEXP (x, 0), op1 = XEXP (x, 1);
4898 /* Convert (A | B) & A to A. */
4899 if (GET_CODE (op0) == IOR
4900 && (rtx_equal_p (XEXP (op0, 0), op1)
4901 || rtx_equal_p (XEXP (op0, 1), op1))
4902 && ! side_effects_p (XEXP (op0, 0))
4903 && ! side_effects_p (XEXP (op0, 1)))
4906 /* In the following group of tests (and those in case IOR below),
4907 we start with some combination of logical operations and apply
4908 the distributive law followed by the inverse distributive law.
4909 Most of the time, this results in no change. However, if some of
4910 the operands are the same or inverses of each other, simplifications
4913 For example, (and (ior A B) (not B)) can occur as the result of
4914 expanding a bit field assignment. When we apply the distributive
4915 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
4916 which then simplifies to (and (A (not B))).
4918 If we have (and (ior A B) C), apply the distributive law and then
4919 the inverse distributive law to see if things simplify. */
4921 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
4923 x = apply_distributive_law
4924 (gen_binary (GET_CODE (op0), mode,
4925 gen_binary (AND, mode, XEXP (op0, 0), op1),
4926 gen_binary (AND, mode, XEXP (op0, 1), op1)));
4927 if (GET_CODE (x) != AND)
4931 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
4932 return apply_distributive_law
4933 (gen_binary (GET_CODE (op1), mode,
4934 gen_binary (AND, mode, XEXP (op1, 0), op0),
4935 gen_binary (AND, mode, XEXP (op1, 1), op0)));
4937 /* Similarly, taking advantage of the fact that
4938 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
4940 if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
4941 return apply_distributive_law
4942 (gen_binary (XOR, mode,
4943 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
4944 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 1))));
4946 else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
4947 return apply_distributive_law
4948 (gen_binary (XOR, mode,
4949 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
4950 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 1))));
4954 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
4955 if (GET_CODE (op1) == CONST_INT
4956 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4957 && (nonzero_bits (op0, mode) & ~ INTVAL (op1)) == 0)
4960 /* Convert (A & B) | A to A. */
4961 if (GET_CODE (op0) == AND
4962 && (rtx_equal_p (XEXP (op0, 0), op1)
4963 || rtx_equal_p (XEXP (op0, 1), op1))
4964 && ! side_effects_p (XEXP (op0, 0))
4965 && ! side_effects_p (XEXP (op0, 1)))
4968 /* If we have (ior (and A B) C), apply the distributive law and then
4969 the inverse distributive law to see if things simplify. */
4971 if (GET_CODE (op0) == AND)
4973 x = apply_distributive_law
4974 (gen_binary (AND, mode,
4975 gen_binary (IOR, mode, XEXP (op0, 0), op1),
4976 gen_binary (IOR, mode, XEXP (op0, 1), op1)));
4978 if (GET_CODE (x) != IOR)
4982 if (GET_CODE (op1) == AND)
4984 x = apply_distributive_law
4985 (gen_binary (AND, mode,
4986 gen_binary (IOR, mode, XEXP (op1, 0), op0),
4987 gen_binary (IOR, mode, XEXP (op1, 1), op0)));
4989 if (GET_CODE (x) != IOR)
4993 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
4994 mode size to (rotate A CX). */
4996 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
4997 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
4998 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
4999 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5000 && GET_CODE (XEXP (op1, 1)) == CONST_INT
5001 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
5002 == GET_MODE_BITSIZE (mode)))
5003 return gen_rtx_ROTATE (mode, XEXP (op0, 0),
5004 (GET_CODE (op0) == ASHIFT
5005 ? XEXP (op0, 1) : XEXP (op1, 1)));
5007 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5008 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5009 does not affect any of the bits in OP1, it can really be done
5010 as a PLUS and we can associate. We do this by seeing if OP1
5011 can be safely shifted left C bits. */
5012 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
5013 && GET_CODE (XEXP (op0, 0)) == PLUS
5014 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
5015 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5016 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
5018 int count = INTVAL (XEXP (op0, 1));
5019 HOST_WIDE_INT mask = INTVAL (op1) << count;
5021 if (mask >> count == INTVAL (op1)
5022 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
5024 SUBST (XEXP (XEXP (op0, 0), 1),
5025 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
5032 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5033 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5036 int num_negated = 0;
5038 if (GET_CODE (op0) == NOT)
5039 num_negated++, op0 = XEXP (op0, 0);
5040 if (GET_CODE (op1) == NOT)
5041 num_negated++, op1 = XEXP (op1, 0);
5043 if (num_negated == 2)
5045 SUBST (XEXP (x, 0), op0);
5046 SUBST (XEXP (x, 1), op1);
5048 else if (num_negated == 1)
5049 return gen_unary (NOT, mode, mode, gen_binary (XOR, mode, op0, op1));
5052 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5053 correspond to a machine insn or result in further simplifications
5054 if B is a constant. */
5056 if (GET_CODE (op0) == AND
5057 && rtx_equal_p (XEXP (op0, 1), op1)
5058 && ! side_effects_p (op1))
5059 return gen_binary (AND, mode,
5060 gen_unary (NOT, mode, mode, XEXP (op0, 0)),
5063 else if (GET_CODE (op0) == AND
5064 && rtx_equal_p (XEXP (op0, 0), op1)
5065 && ! side_effects_p (op1))
5066 return gen_binary (AND, mode,
5067 gen_unary (NOT, mode, mode, XEXP (op0, 1)),
5070 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5071 comparison if STORE_FLAG_VALUE is 1. */
5072 if (STORE_FLAG_VALUE == 1
5073 && op1 == const1_rtx
5074 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5075 && reversible_comparison_p (op0))
5076 return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
5077 mode, XEXP (op0, 0), XEXP (op0, 1));
5079 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5080 is (lt foo (const_int 0)), so we can perform the above
5081 simplification if STORE_FLAG_VALUE is 1. */
5083 if (STORE_FLAG_VALUE == 1
5084 && op1 == const1_rtx
5085 && GET_CODE (op0) == LSHIFTRT
5086 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5087 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
5088 return gen_rtx_combine (GE, mode, XEXP (op0, 0), const0_rtx);
5090 /* (xor (comparison foo bar) (const_int sign-bit))
5091 when STORE_FLAG_VALUE is the sign bit. */
5092 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5093 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5094 == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5095 && op1 == const_true_rtx
5096 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5097 && reversible_comparison_p (op0))
5098 return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
5099 mode, XEXP (op0, 0), XEXP (op0, 1));
5109 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5110 operations" because they can be replaced with two more basic operations.
5111 ZERO_EXTEND is also considered "compound" because it can be replaced with
5112 an AND operation, which is simpler, though only one operation.
5114 The function expand_compound_operation is called with an rtx expression
5115 and will convert it to the appropriate shifts and AND operations,
5116 simplifying at each stage.
5118 The function make_compound_operation is called to convert an expression
5119 consisting of shifts and ANDs into the equivalent compound expression.
5120 It is the inverse of this function, loosely speaking. */
5123 expand_compound_operation (x)
5131 switch (GET_CODE (x))
5136 /* We can't necessarily use a const_int for a multiword mode;
5137 it depends on implicitly extending the value.
5138 Since we don't know the right way to extend it,
5139 we can't tell whether the implicit way is right.
5141 Even for a mode that is no wider than a const_int,
5142 we can't win, because we need to sign extend one of its bits through
5143 the rest of it, and we don't know which bit. */
5144 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5147 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5148 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5149 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5150 reloaded. If not for that, MEM's would very rarely be safe.
5152 Reject MODEs bigger than a word, because we might not be able
5153 to reference a two-register group starting with an arbitrary register
5154 (and currently gen_lowpart might crash for a SUBREG). */
5156 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5159 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5160 /* If the inner object has VOIDmode (the only way this can happen
5161 is if it is a ASM_OPERANDS), we can't do anything since we don't
5162 know how much masking to do. */
5171 /* If the operand is a CLOBBER, just return it. */
5172 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5175 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5176 || GET_CODE (XEXP (x, 2)) != CONST_INT
5177 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5180 len = INTVAL (XEXP (x, 1));
5181 pos = INTVAL (XEXP (x, 2));
5183 /* If this goes outside the object being extracted, replace the object
5184 with a (use (mem ...)) construct that only combine understands
5185 and is used only for this purpose. */
5186 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5187 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
5189 if (BITS_BIG_ENDIAN)
5190 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5198 /* We can optimize some special cases of ZERO_EXTEND. */
5199 if (GET_CODE (x) == ZERO_EXTEND)
5201 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5202 know that the last value didn't have any inappropriate bits
5204 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5205 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5206 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5207 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5208 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5209 return XEXP (XEXP (x, 0), 0);
5211 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5212 if (GET_CODE (XEXP (x, 0)) == SUBREG
5213 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5214 && subreg_lowpart_p (XEXP (x, 0))
5215 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5216 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5217 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5218 return SUBREG_REG (XEXP (x, 0));
5220 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5221 is a comparison and STORE_FLAG_VALUE permits. This is like
5222 the first case, but it works even when GET_MODE (x) is larger
5223 than HOST_WIDE_INT. */
5224 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5225 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5226 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<'
5227 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5228 <= HOST_BITS_PER_WIDE_INT)
5229 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5230 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5231 return XEXP (XEXP (x, 0), 0);
5233 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5234 if (GET_CODE (XEXP (x, 0)) == SUBREG
5235 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5236 && subreg_lowpart_p (XEXP (x, 0))
5237 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<'
5238 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5239 <= HOST_BITS_PER_WIDE_INT)
5240 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5241 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5242 return SUBREG_REG (XEXP (x, 0));
5244 /* If sign extension is cheaper than zero extension, then use it
5245 if we know that no extraneous bits are set, and that the high
5247 if (flag_expensive_optimizations
5248 && ((GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5249 && ((nonzero_bits (XEXP (x, 0), GET_MODE (x))
5250 & ~ (((unsigned HOST_WIDE_INT)
5251 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5254 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
5255 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5256 <= HOST_BITS_PER_WIDE_INT)
5257 && (((HOST_WIDE_INT) STORE_FLAG_VALUE
5258 & ~ (((unsigned HOST_WIDE_INT)
5259 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5263 rtx temp = gen_rtx_SIGN_EXTEND (GET_MODE (x), XEXP (x, 0));
5265 if (rtx_cost (temp, SET) < rtx_cost (x, SET))
5266 return expand_compound_operation (temp);
5270 /* If we reach here, we want to return a pair of shifts. The inner
5271 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5272 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5273 logical depending on the value of UNSIGNEDP.
5275 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5276 converted into an AND of a shift.
5278 We must check for the case where the left shift would have a negative
5279 count. This can happen in a case like (x >> 31) & 255 on machines
5280 that can't shift by a constant. On those machines, we would first
5281 combine the shift with the AND to produce a variable-position
5282 extraction. Then the constant of 31 would be substituted in to produce
5283 a such a position. */
5285 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5286 if (modewidth >= pos - len)
5287 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5289 simplify_shift_const (NULL_RTX, ASHIFT,
5292 modewidth - pos - len),
5295 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5296 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5297 simplify_shift_const (NULL_RTX, LSHIFTRT,
5300 ((HOST_WIDE_INT) 1 << len) - 1);
5302 /* Any other cases we can't handle. */
5306 /* If we couldn't do this for some reason, return the original
5308 if (GET_CODE (tem) == CLOBBER)
5314 /* X is a SET which contains an assignment of one object into
5315 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5316 or certain SUBREGS). If possible, convert it into a series of
5319 We half-heartedly support variable positions, but do not at all
5320 support variable lengths. */
5323 expand_field_assignment (x)
5327 rtx pos; /* Always counts from low bit. */
5330 enum machine_mode compute_mode;
5332 /* Loop until we find something we can't simplify. */
5335 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5336 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5338 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5339 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5340 pos = GEN_INT (BITS_PER_WORD * SUBREG_WORD (XEXP (SET_DEST (x), 0)));
5342 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5343 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5345 inner = XEXP (SET_DEST (x), 0);
5346 len = INTVAL (XEXP (SET_DEST (x), 1));
5347 pos = XEXP (SET_DEST (x), 2);
5349 /* If the position is constant and spans the width of INNER,
5350 surround INNER with a USE to indicate this. */
5351 if (GET_CODE (pos) == CONST_INT
5352 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5353 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
5355 if (BITS_BIG_ENDIAN)
5357 if (GET_CODE (pos) == CONST_INT)
5358 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5360 else if (GET_CODE (pos) == MINUS
5361 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5362 && (INTVAL (XEXP (pos, 1))
5363 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5364 /* If position is ADJUST - X, new position is X. */
5365 pos = XEXP (pos, 0);
5367 pos = gen_binary (MINUS, GET_MODE (pos),
5368 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
5374 /* A SUBREG between two modes that occupy the same numbers of words
5375 can be done by moving the SUBREG to the source. */
5376 else if (GET_CODE (SET_DEST (x)) == SUBREG
5377 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5378 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5379 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5380 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5382 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5383 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (SET_DEST (x))),
5390 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5391 inner = SUBREG_REG (inner);
5393 compute_mode = GET_MODE (inner);
5395 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5396 if (len < HOST_BITS_PER_WIDE_INT)
5397 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5401 /* Now compute the equivalent expression. Make a copy of INNER
5402 for the SET_DEST in case it is a MEM into which we will substitute;
5403 we don't want shared RTL in that case. */
5404 x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
5405 gen_binary (IOR, compute_mode,
5406 gen_binary (AND, compute_mode,
5407 gen_unary (NOT, compute_mode,
5413 gen_binary (ASHIFT, compute_mode,
5414 gen_binary (AND, compute_mode,
5415 gen_lowpart_for_combine
5425 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5426 it is an RTX that represents a variable starting position; otherwise,
5427 POS is the (constant) starting bit position (counted from the LSB).
5429 INNER may be a USE. This will occur when we started with a bitfield
5430 that went outside the boundary of the object in memory, which is
5431 allowed on most machines. To isolate this case, we produce a USE
5432 whose mode is wide enough and surround the MEM with it. The only
5433 code that understands the USE is this routine. If it is not removed,
5434 it will cause the resulting insn not to match.
5436 UNSIGNEDP is non-zero for an unsigned reference and zero for a
5439 IN_DEST is non-zero if this is a reference in the destination of a
5440 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
5441 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5444 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
5445 ZERO_EXTRACT should be built even for bits starting at bit 0.
5447 MODE is the desired mode of the result (if IN_DEST == 0).
5449 The result is an RTX for the extraction or NULL_RTX if the target
5453 make_extraction (mode, inner, pos, pos_rtx, len,
5454 unsignedp, in_dest, in_compare)
5455 enum machine_mode mode;
5461 int in_dest, in_compare;
5463 /* This mode describes the size of the storage area
5464 to fetch the overall value from. Within that, we
5465 ignore the POS lowest bits, etc. */
5466 enum machine_mode is_mode = GET_MODE (inner);
5467 enum machine_mode inner_mode;
5468 enum machine_mode wanted_inner_mode = byte_mode;
5469 enum machine_mode wanted_inner_reg_mode = word_mode;
5470 enum machine_mode pos_mode = word_mode;
5471 enum machine_mode extraction_mode = word_mode;
5472 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5475 rtx orig_pos_rtx = pos_rtx;
5478 /* Get some information about INNER and get the innermost object. */
5479 if (GET_CODE (inner) == USE)
5480 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5481 /* We don't need to adjust the position because we set up the USE
5482 to pretend that it was a full-word object. */
5483 spans_byte = 1, inner = XEXP (inner, 0);
5484 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5486 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5487 consider just the QI as the memory to extract from.
5488 The subreg adds or removes high bits; its mode is
5489 irrelevant to the meaning of this extraction,
5490 since POS and LEN count from the lsb. */
5491 if (GET_CODE (SUBREG_REG (inner)) == MEM)
5492 is_mode = GET_MODE (SUBREG_REG (inner));
5493 inner = SUBREG_REG (inner);
5496 inner_mode = GET_MODE (inner);
5498 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
5499 pos = INTVAL (pos_rtx), pos_rtx = 0;
5501 /* See if this can be done without an extraction. We never can if the
5502 width of the field is not the same as that of some integer mode. For
5503 registers, we can only avoid the extraction if the position is at the
5504 low-order bit and this is either not in the destination or we have the
5505 appropriate STRICT_LOW_PART operation available.
5507 For MEM, we can avoid an extract if the field starts on an appropriate
5508 boundary and we can change the mode of the memory reference. However,
5509 we cannot directly access the MEM if we have a USE and the underlying
5510 MEM is not TMODE. This combination means that MEM was being used in a
5511 context where bits outside its mode were being referenced; that is only
5512 valid in bit-field insns. */
5514 if (tmode != BLKmode
5515 && ! (spans_byte && inner_mode != tmode)
5516 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
5517 && GET_CODE (inner) != MEM
5519 || (GET_CODE (inner) == REG
5520 && (movstrict_optab->handlers[(int) tmode].insn_code
5521 != CODE_FOR_nothing))))
5522 || (GET_CODE (inner) == MEM && pos_rtx == 0
5524 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
5525 : BITS_PER_UNIT)) == 0
5526 /* We can't do this if we are widening INNER_MODE (it
5527 may not be aligned, for one thing). */
5528 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
5529 && (inner_mode == tmode
5530 || (! mode_dependent_address_p (XEXP (inner, 0))
5531 && ! MEM_VOLATILE_P (inner))))))
5533 /* If INNER is a MEM, make a new MEM that encompasses just the desired
5534 field. If the original and current mode are the same, we need not
5535 adjust the offset. Otherwise, we do if bytes big endian.
5537 If INNER is not a MEM, get a piece consisting of just the field
5538 of interest (in this case POS % BITS_PER_WORD must be 0). */
5540 if (GET_CODE (inner) == MEM)
5543 /* POS counts from lsb, but make OFFSET count in memory order. */
5544 if (BYTES_BIG_ENDIAN)
5545 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
5547 offset = pos / BITS_PER_UNIT;
5549 new = gen_rtx_MEM (tmode, plus_constant (XEXP (inner, 0), offset));
5550 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (inner);
5551 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (inner);
5552 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (inner);
5554 else if (GET_CODE (inner) == REG)
5556 /* We can't call gen_lowpart_for_combine here since we always want
5557 a SUBREG and it would sometimes return a new hard register. */
5558 if (tmode != inner_mode)
5559 new = gen_rtx_SUBREG (tmode, inner,
5561 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD
5562 ? (((GET_MODE_SIZE (inner_mode)
5563 - GET_MODE_SIZE (tmode))
5565 - pos / BITS_PER_WORD)
5566 : pos / BITS_PER_WORD));
5571 new = force_to_mode (inner, tmode,
5572 len >= HOST_BITS_PER_WIDE_INT
5573 ? GET_MODE_MASK (tmode)
5574 : ((HOST_WIDE_INT) 1 << len) - 1,
5577 /* If this extraction is going into the destination of a SET,
5578 make a STRICT_LOW_PART unless we made a MEM. */
5581 return (GET_CODE (new) == MEM ? new
5582 : (GET_CODE (new) != SUBREG
5583 ? gen_rtx_CLOBBER (tmode, const0_rtx)
5584 : gen_rtx_combine (STRICT_LOW_PART, VOIDmode, new)));
5586 /* Otherwise, sign- or zero-extend unless we already are in the
5589 return (mode == tmode ? new
5590 : gen_rtx_combine (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
5594 /* Unless this is a COMPARE or we have a funny memory reference,
5595 don't do anything with zero-extending field extracts starting at
5596 the low-order bit since they are simple AND operations. */
5597 if (pos_rtx == 0 && pos == 0 && ! in_dest
5598 && ! in_compare && ! spans_byte && unsignedp)
5601 /* Unless we are allowed to span bytes, reject this if we would be
5602 spanning bytes or if the position is not a constant and the length
5603 is not 1. In all other cases, we would only be going outside
5604 out object in cases when an original shift would have been
5607 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
5608 || (pos_rtx != 0 && len != 1)))
5611 /* Get the mode to use should INNER not be a MEM, the mode for the position,
5612 and the mode for the result. */
5616 wanted_inner_reg_mode = insn_operand_mode[(int) CODE_FOR_insv][0];
5617 pos_mode = insn_operand_mode[(int) CODE_FOR_insv][2];
5618 extraction_mode = insn_operand_mode[(int) CODE_FOR_insv][3];
5623 if (! in_dest && unsignedp)
5625 wanted_inner_reg_mode = insn_operand_mode[(int) CODE_FOR_extzv][1];
5626 pos_mode = insn_operand_mode[(int) CODE_FOR_extzv][3];
5627 extraction_mode = insn_operand_mode[(int) CODE_FOR_extzv][0];
5632 if (! in_dest && ! unsignedp)
5634 wanted_inner_reg_mode = insn_operand_mode[(int) CODE_FOR_extv][1];
5635 pos_mode = insn_operand_mode[(int) CODE_FOR_extv][3];
5636 extraction_mode = insn_operand_mode[(int) CODE_FOR_extv][0];
5640 /* Never narrow an object, since that might not be safe. */
5642 if (mode != VOIDmode
5643 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
5644 extraction_mode = mode;
5646 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
5647 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
5648 pos_mode = GET_MODE (pos_rtx);
5650 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
5651 if we have to change the mode of memory and cannot, the desired mode is
5653 if (GET_CODE (inner) != MEM)
5654 wanted_inner_mode = wanted_inner_reg_mode;
5655 else if (inner_mode != wanted_inner_mode
5656 && (mode_dependent_address_p (XEXP (inner, 0))
5657 || MEM_VOLATILE_P (inner)))
5658 wanted_inner_mode = extraction_mode;
5662 if (BITS_BIG_ENDIAN)
5664 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
5665 BITS_BIG_ENDIAN style. If position is constant, compute new
5666 position. Otherwise, build subtraction.
5667 Note that POS is relative to the mode of the original argument.
5668 If it's a MEM we need to recompute POS relative to that.
5669 However, if we're extracting from (or inserting into) a register,
5670 we want to recompute POS relative to wanted_inner_mode. */
5671 int width = (GET_CODE (inner) == MEM
5672 ? GET_MODE_BITSIZE (is_mode)
5673 : GET_MODE_BITSIZE (wanted_inner_mode));
5676 pos = width - len - pos;
5679 = gen_rtx_combine (MINUS, GET_MODE (pos_rtx),
5680 GEN_INT (width - len), pos_rtx);
5681 /* POS may be less than 0 now, but we check for that below.
5682 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
5685 /* If INNER has a wider mode, make it smaller. If this is a constant
5686 extract, try to adjust the byte to point to the byte containing
5688 if (wanted_inner_mode != VOIDmode
5689 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
5690 && ((GET_CODE (inner) == MEM
5691 && (inner_mode == wanted_inner_mode
5692 || (! mode_dependent_address_p (XEXP (inner, 0))
5693 && ! MEM_VOLATILE_P (inner))))))
5697 /* The computations below will be correct if the machine is big
5698 endian in both bits and bytes or little endian in bits and bytes.
5699 If it is mixed, we must adjust. */
5701 /* If bytes are big endian and we had a paradoxical SUBREG, we must
5702 adjust OFFSET to compensate. */
5703 if (BYTES_BIG_ENDIAN
5705 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
5706 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
5708 /* If this is a constant position, we can move to the desired byte. */
5711 offset += pos / BITS_PER_UNIT;
5712 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
5715 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
5717 && is_mode != wanted_inner_mode)
5718 offset = (GET_MODE_SIZE (is_mode)
5719 - GET_MODE_SIZE (wanted_inner_mode) - offset);
5721 if (offset != 0 || inner_mode != wanted_inner_mode)
5723 rtx newmem = gen_rtx_MEM (wanted_inner_mode,
5724 plus_constant (XEXP (inner, 0), offset));
5725 RTX_UNCHANGING_P (newmem) = RTX_UNCHANGING_P (inner);
5726 MEM_VOLATILE_P (newmem) = MEM_VOLATILE_P (inner);
5727 MEM_IN_STRUCT_P (newmem) = MEM_IN_STRUCT_P (inner);
5732 /* If INNER is not memory, we can always get it into the proper mode. If we
5733 are changing its mode, POS must be a constant and smaller than the size
5735 else if (GET_CODE (inner) != MEM)
5737 if (GET_MODE (inner) != wanted_inner_mode
5739 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
5742 inner = force_to_mode (inner, wanted_inner_mode,
5744 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
5745 ? GET_MODE_MASK (wanted_inner_mode)
5746 : (((HOST_WIDE_INT) 1 << len) - 1) << orig_pos,
5750 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
5751 have to zero extend. Otherwise, we can just use a SUBREG. */
5753 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
5754 pos_rtx = gen_rtx_combine (ZERO_EXTEND, pos_mode, pos_rtx);
5755 else if (pos_rtx != 0
5756 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
5757 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
5759 /* Make POS_RTX unless we already have it and it is correct. If we don't
5760 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
5762 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
5763 pos_rtx = orig_pos_rtx;
5765 else if (pos_rtx == 0)
5766 pos_rtx = GEN_INT (pos);
5768 /* Make the required operation. See if we can use existing rtx. */
5769 new = gen_rtx_combine (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
5770 extraction_mode, inner, GEN_INT (len), pos_rtx);
5772 new = gen_lowpart_for_combine (mode, new);
5777 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
5778 with any other operations in X. Return X without that shift if so. */
5781 extract_left_shift (x, count)
5785 enum rtx_code code = GET_CODE (x);
5786 enum machine_mode mode = GET_MODE (x);
5792 /* This is the shift itself. If it is wide enough, we will return
5793 either the value being shifted if the shift count is equal to
5794 COUNT or a shift for the difference. */
5795 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5796 && INTVAL (XEXP (x, 1)) >= count)
5797 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
5798 INTVAL (XEXP (x, 1)) - count);
5802 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
5803 return gen_unary (code, mode, mode, tem);
5807 case PLUS: case IOR: case XOR: case AND:
5808 /* If we can safely shift this constant and we find the inner shift,
5809 make a new operation. */
5810 if (GET_CODE (XEXP (x,1)) == CONST_INT
5811 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
5812 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
5813 return gen_binary (code, mode, tem,
5814 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
5825 /* Look at the expression rooted at X. Look for expressions
5826 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
5827 Form these expressions.
5829 Return the new rtx, usually just X.
5831 Also, for machines like the Vax that don't have logical shift insns,
5832 try to convert logical to arithmetic shift operations in cases where
5833 they are equivalent. This undoes the canonicalizations to logical
5834 shifts done elsewhere.
5836 We try, as much as possible, to re-use rtl expressions to save memory.
5838 IN_CODE says what kind of expression we are processing. Normally, it is
5839 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
5840 being kludges), it is MEM. When processing the arguments of a comparison
5841 or a COMPARE against zero, it is COMPARE. */
5844 make_compound_operation (x, in_code)
5846 enum rtx_code in_code;
5848 enum rtx_code code = GET_CODE (x);
5849 enum machine_mode mode = GET_MODE (x);
5850 int mode_width = GET_MODE_BITSIZE (mode);
5852 enum rtx_code next_code;
5858 /* Select the code to be used in recursive calls. Once we are inside an
5859 address, we stay there. If we have a comparison, set to COMPARE,
5860 but once inside, go back to our default of SET. */
5862 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
5863 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
5864 && XEXP (x, 1) == const0_rtx) ? COMPARE
5865 : in_code == COMPARE ? SET : in_code);
5867 /* Process depending on the code of this operation. If NEW is set
5868 non-zero, it will be returned. */
5873 /* Convert shifts by constants into multiplications if inside
5875 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
5876 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
5877 && INTVAL (XEXP (x, 1)) >= 0)
5879 new = make_compound_operation (XEXP (x, 0), next_code);
5880 new = gen_rtx_combine (MULT, mode, new,
5881 GEN_INT ((HOST_WIDE_INT) 1
5882 << INTVAL (XEXP (x, 1))));
5887 /* If the second operand is not a constant, we can't do anything
5889 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
5892 /* If the constant is a power of two minus one and the first operand
5893 is a logical right shift, make an extraction. */
5894 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
5895 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5897 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
5898 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
5899 0, in_code == COMPARE);
5902 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
5903 else if (GET_CODE (XEXP (x, 0)) == SUBREG
5904 && subreg_lowpart_p (XEXP (x, 0))
5905 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
5906 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5908 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
5910 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
5911 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
5912 0, in_code == COMPARE);
5914 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
5915 else if ((GET_CODE (XEXP (x, 0)) == XOR
5916 || GET_CODE (XEXP (x, 0)) == IOR)
5917 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
5918 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
5919 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5921 /* Apply the distributive law, and then try to make extractions. */
5922 new = gen_rtx_combine (GET_CODE (XEXP (x, 0)), mode,
5923 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
5925 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
5927 new = make_compound_operation (new, in_code);
5930 /* If we are have (and (rotate X C) M) and C is larger than the number
5931 of bits in M, this is an extraction. */
5933 else if (GET_CODE (XEXP (x, 0)) == ROTATE
5934 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5935 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
5936 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
5938 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
5939 new = make_extraction (mode, new,
5940 (GET_MODE_BITSIZE (mode)
5941 - INTVAL (XEXP (XEXP (x, 0), 1))),
5942 NULL_RTX, i, 1, 0, in_code == COMPARE);
5945 /* On machines without logical shifts, if the operand of the AND is
5946 a logical shift and our mask turns off all the propagated sign
5947 bits, we can replace the logical shift with an arithmetic shift. */
5948 else if (ashr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
5949 && (lshr_optab->handlers[(int) mode].insn_code
5950 == CODE_FOR_nothing)
5951 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
5952 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5953 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
5954 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
5955 && mode_width <= HOST_BITS_PER_WIDE_INT)
5957 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
5959 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
5960 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
5962 gen_rtx_combine (ASHIFTRT, mode,
5963 make_compound_operation (XEXP (XEXP (x, 0), 0),
5965 XEXP (XEXP (x, 0), 1)));
5968 /* If the constant is one less than a power of two, this might be
5969 representable by an extraction even if no shift is present.
5970 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
5971 we are in a COMPARE. */
5972 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5973 new = make_extraction (mode,
5974 make_compound_operation (XEXP (x, 0),
5976 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
5978 /* If we are in a comparison and this is an AND with a power of two,
5979 convert this into the appropriate bit extract. */
5980 else if (in_code == COMPARE
5981 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
5982 new = make_extraction (mode,
5983 make_compound_operation (XEXP (x, 0),
5985 i, NULL_RTX, 1, 1, 0, 1);
5990 /* If the sign bit is known to be zero, replace this with an
5991 arithmetic shift. */
5992 if (ashr_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing
5993 && lshr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
5994 && mode_width <= HOST_BITS_PER_WIDE_INT
5995 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
5997 new = gen_rtx_combine (ASHIFTRT, mode,
5998 make_compound_operation (XEXP (x, 0),
6004 /* ... fall through ... */
6010 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6011 this is a SIGN_EXTRACT. */
6012 if (GET_CODE (rhs) == CONST_INT
6013 && GET_CODE (lhs) == ASHIFT
6014 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6015 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6017 new = make_compound_operation (XEXP (lhs, 0), next_code);
6018 new = make_extraction (mode, new,
6019 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6020 NULL_RTX, mode_width - INTVAL (rhs),
6021 code == LSHIFTRT, 0, in_code == COMPARE);
6024 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6025 If so, try to merge the shifts into a SIGN_EXTEND. We could
6026 also do this for some cases of SIGN_EXTRACT, but it doesn't
6027 seem worth the effort; the case checked for occurs on Alpha. */
6029 if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o'
6030 && ! (GET_CODE (lhs) == SUBREG
6031 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o'))
6032 && GET_CODE (rhs) == CONST_INT
6033 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6034 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6035 new = make_extraction (mode, make_compound_operation (new, next_code),
6036 0, NULL_RTX, mode_width - INTVAL (rhs),
6037 code == LSHIFTRT, 0, in_code == COMPARE);
6042 /* Call ourselves recursively on the inner expression. If we are
6043 narrowing the object and it has a different RTL code from
6044 what it originally did, do this SUBREG as a force_to_mode. */
6046 tem = make_compound_operation (SUBREG_REG (x), in_code);
6047 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6048 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6049 && subreg_lowpart_p (x))
6051 rtx newer = force_to_mode (tem, mode,
6052 GET_MODE_MASK (mode), NULL_RTX, 0);
6054 /* If we have something other than a SUBREG, we might have
6055 done an expansion, so rerun outselves. */
6056 if (GET_CODE (newer) != SUBREG)
6057 newer = make_compound_operation (newer, in_code);
6062 /* If this is a paradoxical subreg, and the new code is a sign or
6063 zero extension, omit the subreg and widen the extension. If it
6064 is a regular subreg, we can still get rid of the subreg by not
6065 widening so much, or in fact removing the extension entirely. */
6066 if ((GET_CODE (tem) == SIGN_EXTEND
6067 || GET_CODE (tem) == ZERO_EXTEND)
6068 && subreg_lowpart_p (x))
6070 if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (tem))
6071 || (GET_MODE_SIZE (mode) >
6072 GET_MODE_SIZE (GET_MODE (XEXP (tem, 0)))))
6073 tem = gen_rtx_combine (GET_CODE (tem), mode, XEXP (tem, 0));
6075 tem = gen_lowpart_for_combine (mode, XEXP (tem, 0));
6086 x = gen_lowpart_for_combine (mode, new);
6087 code = GET_CODE (x);
6090 /* Now recursively process each operand of this operation. */
6091 fmt = GET_RTX_FORMAT (code);
6092 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6095 new = make_compound_operation (XEXP (x, i), next_code);
6096 SUBST (XEXP (x, i), new);
6102 /* Given M see if it is a value that would select a field of bits
6103 within an item, but not the entire word. Return -1 if not.
6104 Otherwise, return the starting position of the field, where 0 is the
6107 *PLEN is set to the length of the field. */
6110 get_pos_from_mask (m, plen)
6111 unsigned HOST_WIDE_INT m;
6114 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6115 int pos = exact_log2 (m & - m);
6120 /* Now shift off the low-order zero bits and see if we have a power of
6122 *plen = exact_log2 ((m >> pos) + 1);
6130 /* See if X can be simplified knowing that we will only refer to it in
6131 MODE and will only refer to those bits that are nonzero in MASK.
6132 If other bits are being computed or if masking operations are done
6133 that select a superset of the bits in MASK, they can sometimes be
6136 Return a possibly simplified expression, but always convert X to
6137 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6139 Also, if REG is non-zero and X is a register equal in value to REG,
6142 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6143 are all off in X. This is used when X will be complemented, by either
6144 NOT, NEG, or XOR. */
6147 force_to_mode (x, mode, mask, reg, just_select)
6149 enum machine_mode mode;
6150 unsigned HOST_WIDE_INT mask;
6154 enum rtx_code code = GET_CODE (x);
6155 int next_select = just_select || code == XOR || code == NOT || code == NEG;
6156 enum machine_mode op_mode;
6157 unsigned HOST_WIDE_INT fuller_mask, nonzero;
6160 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6161 code below will do the wrong thing since the mode of such an
6162 expression is VOIDmode.
6164 Also do nothing if X is a CLOBBER; this can happen if X was
6165 the return value from a call to gen_lowpart_for_combine. */
6166 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6169 /* We want to perform the operation is its present mode unless we know
6170 that the operation is valid in MODE, in which case we do the operation
6172 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6173 && code_to_optab[(int) code] != 0
6174 && (code_to_optab[(int) code]->handlers[(int) mode].insn_code
6175 != CODE_FOR_nothing))
6176 ? mode : GET_MODE (x));
6178 /* It is not valid to do a right-shift in a narrower mode
6179 than the one it came in with. */
6180 if ((code == LSHIFTRT || code == ASHIFTRT)
6181 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6182 op_mode = GET_MODE (x);
6184 /* Truncate MASK to fit OP_MODE. */
6186 mask &= GET_MODE_MASK (op_mode);
6188 /* When we have an arithmetic operation, or a shift whose count we
6189 do not know, we need to assume that all bit the up to the highest-order
6190 bit in MASK will be needed. This is how we form such a mask. */
6192 fuller_mask = (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT
6193 ? GET_MODE_MASK (op_mode)
6194 : ((HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1)) - 1);
6196 fuller_mask = ~ (HOST_WIDE_INT) 0;
6198 /* Determine what bits of X are guaranteed to be (non)zero. */
6199 nonzero = nonzero_bits (x, mode);
6201 /* If none of the bits in X are needed, return a zero. */
6202 if (! just_select && (nonzero & mask) == 0)
6205 /* If X is a CONST_INT, return a new one. Do this here since the
6206 test below will fail. */
6207 if (GET_CODE (x) == CONST_INT)
6209 HOST_WIDE_INT cval = INTVAL (x) & mask;
6210 int width = GET_MODE_BITSIZE (mode);
6212 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6213 number, sign extend it. */
6214 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6215 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6216 cval |= (HOST_WIDE_INT) -1 << width;
6218 return GEN_INT (cval);
6221 /* If X is narrower than MODE and we want all the bits in X's mode, just
6222 get X in the proper mode. */
6223 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6224 && (GET_MODE_MASK (GET_MODE (x)) & ~ mask) == 0)
6225 return gen_lowpart_for_combine (mode, x);
6227 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6228 MASK are already known to be zero in X, we need not do anything. */
6229 if (GET_MODE (x) == mode && code != SUBREG && (~ mask & nonzero) == 0)
6235 /* If X is a (clobber (const_int)), return it since we know we are
6236 generating something that won't match. */
6240 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6241 spanned the boundary of the MEM. If we are now masking so it is
6242 within that boundary, we don't need the USE any more. */
6243 if (! BITS_BIG_ENDIAN
6244 && (mask & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6245 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6252 x = expand_compound_operation (x);
6253 if (GET_CODE (x) != code)
6254 return force_to_mode (x, mode, mask, reg, next_select);
6258 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6259 || rtx_equal_p (reg, get_last_value (x))))
6264 if (subreg_lowpart_p (x)
6265 /* We can ignore the effect of this SUBREG if it narrows the mode or
6266 if the constant masks to zero all the bits the mode doesn't
6268 && ((GET_MODE_SIZE (GET_MODE (x))
6269 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6271 & GET_MODE_MASK (GET_MODE (x))
6272 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6273 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
6277 /* If this is an AND with a constant, convert it into an AND
6278 whose constant is the AND of that constant with MASK. If it
6279 remains an AND of MASK, delete it since it is redundant. */
6281 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6283 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6284 mask & INTVAL (XEXP (x, 1)));
6286 /* If X is still an AND, see if it is an AND with a mask that
6287 is just some low-order bits. If so, and it is MASK, we don't
6290 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6291 && INTVAL (XEXP (x, 1)) == mask)
6294 /* If it remains an AND, try making another AND with the bits
6295 in the mode mask that aren't in MASK turned on. If the
6296 constant in the AND is wide enough, this might make a
6297 cheaper constant. */
6299 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6300 && GET_MODE_MASK (GET_MODE (x)) != mask
6301 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6303 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6304 | (GET_MODE_MASK (GET_MODE (x)) & ~ mask));
6305 int width = GET_MODE_BITSIZE (GET_MODE (x));
6308 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6309 number, sign extend it. */
6310 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6311 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6312 cval |= (HOST_WIDE_INT) -1 << width;
6314 y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
6315 if (rtx_cost (y, SET) < rtx_cost (x, SET))
6325 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6326 low-order bits (as in an alignment operation) and FOO is already
6327 aligned to that boundary, mask C1 to that boundary as well.
6328 This may eliminate that PLUS and, later, the AND. */
6331 int width = GET_MODE_BITSIZE (mode);
6332 unsigned HOST_WIDE_INT smask = mask;
6334 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6335 number, sign extend it. */
6337 if (width < HOST_BITS_PER_WIDE_INT
6338 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6339 smask |= (HOST_WIDE_INT) -1 << width;
6341 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6342 && exact_log2 (- smask) >= 0)
6346 && (XEXP (x, 0) == stack_pointer_rtx
6347 || XEXP (x, 0) == frame_pointer_rtx))
6349 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
6350 unsigned HOST_WIDE_INT sp_mask = GET_MODE_MASK (mode);
6352 sp_mask &= ~ (sp_alignment - 1);
6353 if ((sp_mask & ~ mask) == 0
6354 && ((INTVAL (XEXP (x, 1)) - STACK_BIAS) & ~ mask) != 0)
6355 return force_to_mode (plus_constant (XEXP (x, 0),
6356 ((INTVAL (XEXP (x, 1)) -
6359 mode, mask, reg, next_select);
6362 if ((nonzero_bits (XEXP (x, 0), mode) & ~ mask) == 0
6363 && (INTVAL (XEXP (x, 1)) & ~ mask) != 0)
6364 return force_to_mode (plus_constant (XEXP (x, 0),
6365 INTVAL (XEXP (x, 1)) & mask),
6366 mode, mask, reg, next_select);
6370 /* ... fall through ... */
6374 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6375 most significant bit in MASK since carries from those bits will
6376 affect the bits we are interested in. */
6382 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6383 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6384 operation which may be a bitfield extraction. Ensure that the
6385 constant we form is not wider than the mode of X. */
6387 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6388 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6389 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6390 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6391 && GET_CODE (XEXP (x, 1)) == CONST_INT
6392 && ((INTVAL (XEXP (XEXP (x, 0), 1))
6393 + floor_log2 (INTVAL (XEXP (x, 1))))
6394 < GET_MODE_BITSIZE (GET_MODE (x)))
6395 && (INTVAL (XEXP (x, 1))
6396 & ~ nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
6398 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
6399 << INTVAL (XEXP (XEXP (x, 0), 1)));
6400 temp = gen_binary (GET_CODE (x), GET_MODE (x),
6401 XEXP (XEXP (x, 0), 0), temp);
6402 x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
6403 XEXP (XEXP (x, 0), 1));
6404 return force_to_mode (x, mode, mask, reg, next_select);
6408 /* For most binary operations, just propagate into the operation and
6409 change the mode if we have an operation of that mode. */
6411 op0 = gen_lowpart_for_combine (op_mode,
6412 force_to_mode (XEXP (x, 0), mode, mask,
6414 op1 = gen_lowpart_for_combine (op_mode,
6415 force_to_mode (XEXP (x, 1), mode, mask,
6418 /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside
6419 MASK since OP1 might have been sign-extended but we never want
6420 to turn on extra bits, since combine might have previously relied
6421 on them being off. */
6422 if (GET_CODE (op1) == CONST_INT && (code == IOR || code == XOR)
6423 && (INTVAL (op1) & mask) != 0)
6424 op1 = GEN_INT (INTVAL (op1) & mask);
6426 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6427 x = gen_binary (code, op_mode, op0, op1);
6431 /* For left shifts, do the same, but just for the first operand.
6432 However, we cannot do anything with shifts where we cannot
6433 guarantee that the counts are smaller than the size of the mode
6434 because such a count will have a different meaning in a
6437 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
6438 && INTVAL (XEXP (x, 1)) >= 0
6439 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
6440 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
6441 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
6442 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
6445 /* If the shift count is a constant and we can do arithmetic in
6446 the mode of the shift, refine which bits we need. Otherwise, use the
6447 conservative form of the mask. */
6448 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6449 && INTVAL (XEXP (x, 1)) >= 0
6450 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
6451 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6452 mask >>= INTVAL (XEXP (x, 1));
6456 op0 = gen_lowpart_for_combine (op_mode,
6457 force_to_mode (XEXP (x, 0), op_mode,
6458 mask, reg, next_select));
6460 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6461 x = gen_binary (code, op_mode, op0, XEXP (x, 1));
6465 /* Here we can only do something if the shift count is a constant,
6466 this shift constant is valid for the host, and we can do arithmetic
6469 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6470 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6471 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6473 rtx inner = XEXP (x, 0);
6475 /* Select the mask of the bits we need for the shift operand. */
6476 mask <<= INTVAL (XEXP (x, 1));
6478 /* We can only change the mode of the shift if we can do arithmetic
6479 in the mode of the shift and MASK is no wider than the width of
6481 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT
6482 || (mask & ~ GET_MODE_MASK (op_mode)) != 0)
6483 op_mode = GET_MODE (x);
6485 inner = force_to_mode (inner, op_mode, mask, reg, next_select);
6487 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
6488 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
6491 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
6492 shift and AND produces only copies of the sign bit (C2 is one less
6493 than a power of two), we can do this with just a shift. */
6495 if (GET_CODE (x) == LSHIFTRT
6496 && GET_CODE (XEXP (x, 1)) == CONST_INT
6497 && ((INTVAL (XEXP (x, 1))
6498 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
6499 >= GET_MODE_BITSIZE (GET_MODE (x)))
6500 && exact_log2 (mask + 1) >= 0
6501 && (num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6502 >= exact_log2 (mask + 1)))
6503 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
6504 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
6505 - exact_log2 (mask + 1)));
6509 /* If we are just looking for the sign bit, we don't need this shift at
6510 all, even if it has a variable count. */
6511 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6512 && (mask == ((HOST_WIDE_INT) 1
6513 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
6514 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6516 /* If this is a shift by a constant, get a mask that contains those bits
6517 that are not copies of the sign bit. We then have two cases: If
6518 MASK only includes those bits, this can be a logical shift, which may
6519 allow simplifications. If MASK is a single-bit field not within
6520 those bits, we are requesting a copy of the sign bit and hence can
6521 shift the sign bit to the appropriate location. */
6523 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
6524 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
6528 /* If the considered data is wider then HOST_WIDE_INT, we can't
6529 represent a mask for all its bits in a single scalar.
6530 But we only care about the lower bits, so calculate these. */
6532 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
6534 nonzero = ~ (HOST_WIDE_INT) 0;
6536 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6537 is the number of bits a full-width mask would have set.
6538 We need only shift if these are fewer than nonzero can
6539 hold. If not, we must keep all bits set in nonzero. */
6541 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6542 < HOST_BITS_PER_WIDE_INT)
6543 nonzero >>= INTVAL (XEXP (x, 1))
6544 + HOST_BITS_PER_WIDE_INT
6545 - GET_MODE_BITSIZE (GET_MODE (x)) ;
6549 nonzero = GET_MODE_MASK (GET_MODE (x));
6550 nonzero >>= INTVAL (XEXP (x, 1));
6553 if ((mask & ~ nonzero) == 0
6554 || (i = exact_log2 (mask)) >= 0)
6556 x = simplify_shift_const
6557 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
6558 i < 0 ? INTVAL (XEXP (x, 1))
6559 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
6561 if (GET_CODE (x) != ASHIFTRT)
6562 return force_to_mode (x, mode, mask, reg, next_select);
6566 /* If MASK is 1, convert this to a LSHIFTRT. This can be done
6567 even if the shift count isn't a constant. */
6569 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
6571 /* If this is a sign-extension operation that just affects bits
6572 we don't care about, remove it. Be sure the call above returned
6573 something that is still a shift. */
6575 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
6576 && GET_CODE (XEXP (x, 1)) == CONST_INT
6577 && INTVAL (XEXP (x, 1)) >= 0
6578 && (INTVAL (XEXP (x, 1))
6579 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
6580 && GET_CODE (XEXP (x, 0)) == ASHIFT
6581 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6582 && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1)))
6583 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
6590 /* If the shift count is constant and we can do computations
6591 in the mode of X, compute where the bits we care about are.
6592 Otherwise, we can't do anything. Don't change the mode of
6593 the shift or propagate MODE into the shift, though. */
6594 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6595 && INTVAL (XEXP (x, 1)) >= 0)
6597 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
6598 GET_MODE (x), GEN_INT (mask),
6600 if (temp && GET_CODE(temp) == CONST_INT)
6602 force_to_mode (XEXP (x, 0), GET_MODE (x),
6603 INTVAL (temp), reg, next_select));
6608 /* If we just want the low-order bit, the NEG isn't needed since it
6609 won't change the low-order bit. */
6611 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
6613 /* We need any bits less significant than the most significant bit in
6614 MASK since carries from those bits will affect the bits we are
6620 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
6621 same as the XOR case above. Ensure that the constant we form is not
6622 wider than the mode of X. */
6624 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6625 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6626 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6627 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
6628 < GET_MODE_BITSIZE (GET_MODE (x)))
6629 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
6631 temp = GEN_INT (mask << INTVAL (XEXP (XEXP (x, 0), 1)));
6632 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
6633 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
6635 return force_to_mode (x, mode, mask, reg, next_select);
6638 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
6639 use the full mask inside the NOT. */
6643 op0 = gen_lowpart_for_combine (op_mode,
6644 force_to_mode (XEXP (x, 0), mode, mask,
6646 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6647 x = gen_unary (code, op_mode, op_mode, op0);
6651 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
6652 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
6653 which is equal to STORE_FLAG_VALUE. */
6654 if ((mask & ~ STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
6655 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
6656 && nonzero_bits (XEXP (x, 0), mode) == STORE_FLAG_VALUE)
6657 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6662 /* We have no way of knowing if the IF_THEN_ELSE can itself be
6663 written in a narrower mode. We play it safe and do not do so. */
6666 gen_lowpart_for_combine (GET_MODE (x),
6667 force_to_mode (XEXP (x, 1), mode,
6668 mask, reg, next_select)));
6670 gen_lowpart_for_combine (GET_MODE (x),
6671 force_to_mode (XEXP (x, 2), mode,
6672 mask, reg,next_select)));
6679 /* Ensure we return a value of the proper mode. */
6680 return gen_lowpart_for_combine (mode, x);
6683 /* Return nonzero if X is an expression that has one of two values depending on
6684 whether some other value is zero or nonzero. In that case, we return the
6685 value that is being tested, *PTRUE is set to the value if the rtx being
6686 returned has a nonzero value, and *PFALSE is set to the other alternative.
6688 If we return zero, we set *PTRUE and *PFALSE to X. */
6691 if_then_else_cond (x, ptrue, pfalse)
6693 rtx *ptrue, *pfalse;
6695 enum machine_mode mode = GET_MODE (x);
6696 enum rtx_code code = GET_CODE (x);
6697 int size = GET_MODE_BITSIZE (mode);
6698 rtx cond0, cond1, true0, true1, false0, false1;
6699 unsigned HOST_WIDE_INT nz;
6701 /* If this is a unary operation whose operand has one of two values, apply
6702 our opcode to compute those values. */
6703 if (GET_RTX_CLASS (code) == '1'
6704 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
6706 *ptrue = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), true0);
6707 *pfalse = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), false0);
6711 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
6712 make can't possibly match and would suppress other optimizations. */
6713 else if (code == COMPARE)
6716 /* If this is a binary operation, see if either side has only one of two
6717 values. If either one does or if both do and they are conditional on
6718 the same value, compute the new true and false values. */
6719 else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2'
6720 || GET_RTX_CLASS (code) == '<')
6722 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
6723 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
6725 if ((cond0 != 0 || cond1 != 0)
6726 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
6728 /* If if_then_else_cond returned zero, then true/false are the
6729 same rtl. We must copy one of them to prevent invalid rtl
6732 true0 = copy_rtx (true0);
6733 else if (cond1 == 0)
6734 true1 = copy_rtx (true1);
6736 *ptrue = gen_binary (code, mode, true0, true1);
6737 *pfalse = gen_binary (code, mode, false0, false1);
6738 return cond0 ? cond0 : cond1;
6741 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
6742 operands is zero when the other is non-zero, and vice-versa,
6743 and STORE_FLAG_VALUE is 1 or -1. */
6745 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6746 && (code == PLUS || code == IOR || code == XOR || code == MINUS
6748 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
6750 rtx op0 = XEXP (XEXP (x, 0), 1);
6751 rtx op1 = XEXP (XEXP (x, 1), 1);
6753 cond0 = XEXP (XEXP (x, 0), 0);
6754 cond1 = XEXP (XEXP (x, 1), 0);
6756 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
6757 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
6758 && reversible_comparison_p (cond1)
6759 && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
6760 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
6761 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
6762 || ((swap_condition (GET_CODE (cond0))
6763 == reverse_condition (GET_CODE (cond1)))
6764 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
6765 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
6766 && ! side_effects_p (x))
6768 *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
6769 *pfalse = gen_binary (MULT, mode,
6771 ? gen_unary (NEG, mode, mode, op1) : op1),
6777 /* Similarly for MULT, AND and UMIN, execpt that for these the result
6779 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6780 && (code == MULT || code == AND || code == UMIN)
6781 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
6783 cond0 = XEXP (XEXP (x, 0), 0);
6784 cond1 = XEXP (XEXP (x, 1), 0);
6786 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
6787 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
6788 && reversible_comparison_p (cond1)
6789 && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
6790 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
6791 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
6792 || ((swap_condition (GET_CODE (cond0))
6793 == reverse_condition (GET_CODE (cond1)))
6794 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
6795 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
6796 && ! side_effects_p (x))
6798 *ptrue = *pfalse = const0_rtx;
6804 else if (code == IF_THEN_ELSE)
6806 /* If we have IF_THEN_ELSE already, extract the condition and
6807 canonicalize it if it is NE or EQ. */
6808 cond0 = XEXP (x, 0);
6809 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
6810 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
6811 return XEXP (cond0, 0);
6812 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
6814 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
6815 return XEXP (cond0, 0);
6821 /* If X is a normal SUBREG with both inner and outer modes integral,
6822 we can narrow both the true and false values of the inner expression,
6823 if there is a condition. */
6824 else if (code == SUBREG && GET_MODE_CLASS (mode) == MODE_INT
6825 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_INT
6826 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))
6827 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
6830 *ptrue = force_to_mode (true0, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
6832 = force_to_mode (false0, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
6837 /* If X is a constant, this isn't special and will cause confusions
6838 if we treat it as such. Likewise if it is equivalent to a constant. */
6839 else if (CONSTANT_P (x)
6840 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
6843 /* If X is known to be either 0 or -1, those are the true and
6844 false values when testing X. */
6845 else if (num_sign_bit_copies (x, mode) == size)
6847 *ptrue = constm1_rtx, *pfalse = const0_rtx;
6851 /* Likewise for 0 or a single bit. */
6852 else if (exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
6854 *ptrue = GEN_INT (nz), *pfalse = const0_rtx;
6858 /* Otherwise fail; show no condition with true and false values the same. */
6859 *ptrue = *pfalse = x;
6863 /* Return the value of expression X given the fact that condition COND
6864 is known to be true when applied to REG as its first operand and VAL
6865 as its second. X is known to not be shared and so can be modified in
6868 We only handle the simplest cases, and specifically those cases that
6869 arise with IF_THEN_ELSE expressions. */
6872 known_cond (x, cond, reg, val)
6877 enum rtx_code code = GET_CODE (x);
6882 if (side_effects_p (x))
6885 if (cond == EQ && rtx_equal_p (x, reg))
6888 /* If X is (abs REG) and we know something about REG's relationship
6889 with zero, we may be able to simplify this. */
6891 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
6894 case GE: case GT: case EQ:
6897 return gen_unary (NEG, GET_MODE (XEXP (x, 0)), GET_MODE (XEXP (x, 0)),
6903 /* The only other cases we handle are MIN, MAX, and comparisons if the
6904 operands are the same as REG and VAL. */
6906 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
6908 if (rtx_equal_p (XEXP (x, 0), val))
6909 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
6911 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
6913 if (GET_RTX_CLASS (code) == '<')
6914 return (comparison_dominates_p (cond, code) ? const_true_rtx
6915 : (comparison_dominates_p (cond,
6916 reverse_condition (code))
6919 else if (code == SMAX || code == SMIN
6920 || code == UMIN || code == UMAX)
6922 int unsignedp = (code == UMIN || code == UMAX);
6924 if (code == SMAX || code == UMAX)
6925 cond = reverse_condition (cond);
6930 return unsignedp ? x : XEXP (x, 1);
6932 return unsignedp ? x : XEXP (x, 0);
6934 return unsignedp ? XEXP (x, 1) : x;
6936 return unsignedp ? XEXP (x, 0) : x;
6944 fmt = GET_RTX_FORMAT (code);
6945 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6948 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
6949 else if (fmt[i] == 'E')
6950 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
6951 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
6958 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
6959 assignment as a field assignment. */
6962 rtx_equal_for_field_assignment_p (x, y)
6966 if (x == y || rtx_equal_p (x, y))
6969 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
6972 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
6973 Note that all SUBREGs of MEM are paradoxical; otherwise they
6974 would have been rewritten. */
6975 if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG
6976 && GET_CODE (SUBREG_REG (y)) == MEM
6977 && rtx_equal_p (SUBREG_REG (y),
6978 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x)))
6981 if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG
6982 && GET_CODE (SUBREG_REG (x)) == MEM
6983 && rtx_equal_p (SUBREG_REG (x),
6984 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y)))
6987 /* We used to see if get_last_value of X and Y were the same but that's
6988 not correct. In one direction, we'll cause the assignment to have
6989 the wrong destination and in the case, we'll import a register into this
6990 insn that might have already have been dead. So fail if none of the
6991 above cases are true. */
6995 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
6996 Return that assignment if so.
6998 We only handle the most common cases. */
7001 make_field_assignment (x)
7004 rtx dest = SET_DEST (x);
7005 rtx src = SET_SRC (x);
7011 enum machine_mode mode;
7013 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7014 a clear of a one-bit field. We will have changed it to
7015 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7018 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7019 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7020 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7021 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7023 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7026 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7030 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7031 && subreg_lowpart_p (XEXP (src, 0))
7032 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7033 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7034 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7035 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7036 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7038 assign = make_extraction (VOIDmode, dest, 0,
7039 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7042 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7046 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7048 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7049 && XEXP (XEXP (src, 0), 0) == const1_rtx
7050 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7052 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7055 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7059 /* The other case we handle is assignments into a constant-position
7060 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7061 a mask that has all one bits except for a group of zero bits and
7062 OTHER is known to have zeros where C1 has ones, this is such an
7063 assignment. Compute the position and length from C1. Shift OTHER
7064 to the appropriate position, force it to the required mode, and
7065 make the extraction. Check for the AND in both operands. */
7067 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7070 rhs = expand_compound_operation (XEXP (src, 0));
7071 lhs = expand_compound_operation (XEXP (src, 1));
7073 if (GET_CODE (rhs) == AND
7074 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7075 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7076 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7077 else if (GET_CODE (lhs) == AND
7078 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7079 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7080 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7084 pos = get_pos_from_mask ((~ c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7085 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7086 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7087 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7090 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7094 /* The mode to use for the source is the mode of the assignment, or of
7095 what is inside a possible STRICT_LOW_PART. */
7096 mode = (GET_CODE (assign) == STRICT_LOW_PART
7097 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7099 /* Shift OTHER right POS places and make it the source, restricting it
7100 to the proper length and mode. */
7102 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
7103 GET_MODE (src), other, pos),
7105 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7106 ? GET_MODE_MASK (mode)
7107 : ((HOST_WIDE_INT) 1 << len) - 1,
7110 return gen_rtx_combine (SET, VOIDmode, assign, src);
7113 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7117 apply_distributive_law (x)
7120 enum rtx_code code = GET_CODE (x);
7121 rtx lhs, rhs, other;
7123 enum rtx_code inner_code;
7125 /* Distributivity is not true for floating point.
7126 It can change the value. So don't do it.
7127 -- rms and moshier@world.std.com. */
7128 if (FLOAT_MODE_P (GET_MODE (x)))
7131 /* The outer operation can only be one of the following: */
7132 if (code != IOR && code != AND && code != XOR
7133 && code != PLUS && code != MINUS)
7136 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
7138 /* If either operand is a primitive we can't do anything, so get out
7140 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
7141 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
7144 lhs = expand_compound_operation (lhs);
7145 rhs = expand_compound_operation (rhs);
7146 inner_code = GET_CODE (lhs);
7147 if (inner_code != GET_CODE (rhs))
7150 /* See if the inner and outer operations distribute. */
7157 /* These all distribute except over PLUS. */
7158 if (code == PLUS || code == MINUS)
7163 if (code != PLUS && code != MINUS)
7168 /* This is also a multiply, so it distributes over everything. */
7172 /* Non-paradoxical SUBREGs distributes over all operations, provided
7173 the inner modes and word numbers are the same, this is an extraction
7174 of a low-order part, we don't convert an fp operation to int or
7175 vice versa, and we would not be converting a single-word
7176 operation into a multi-word operation. The latter test is not
7177 required, but it prevents generating unneeded multi-word operations.
7178 Some of the previous tests are redundant given the latter test, but
7179 are retained because they are required for correctness.
7181 We produce the result slightly differently in this case. */
7183 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7184 || SUBREG_WORD (lhs) != SUBREG_WORD (rhs)
7185 || ! subreg_lowpart_p (lhs)
7186 || (GET_MODE_CLASS (GET_MODE (lhs))
7187 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7188 || (GET_MODE_SIZE (GET_MODE (lhs))
7189 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7190 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
7193 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7194 SUBREG_REG (lhs), SUBREG_REG (rhs));
7195 return gen_lowpart_for_combine (GET_MODE (x), tem);
7201 /* Set LHS and RHS to the inner operands (A and B in the example
7202 above) and set OTHER to the common operand (C in the example).
7203 These is only one way to do this unless the inner operation is
7205 if (GET_RTX_CLASS (inner_code) == 'c'
7206 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
7207 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
7208 else if (GET_RTX_CLASS (inner_code) == 'c'
7209 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7210 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7211 else if (GET_RTX_CLASS (inner_code) == 'c'
7212 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
7213 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
7214 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
7215 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
7219 /* Form the new inner operation, seeing if it simplifies first. */
7220 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
7222 /* There is one exception to the general way of distributing:
7223 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
7224 if (code == XOR && inner_code == IOR)
7227 other = gen_unary (NOT, GET_MODE (x), GET_MODE (x), other);
7230 /* We may be able to continuing distributing the result, so call
7231 ourselves recursively on the inner operation before forming the
7232 outer operation, which we return. */
7233 return gen_binary (inner_code, GET_MODE (x),
7234 apply_distributive_law (tem), other);
7237 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7240 Return an equivalent form, if different from X. Otherwise, return X. If
7241 X is zero, we are to always construct the equivalent form. */
7244 simplify_and_const_int (x, mode, varop, constop)
7246 enum machine_mode mode;
7248 unsigned HOST_WIDE_INT constop;
7250 unsigned HOST_WIDE_INT nonzero;
7251 int width = GET_MODE_BITSIZE (mode);
7254 /* Simplify VAROP knowing that we will be only looking at some of the
7256 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
7258 /* If VAROP is a CLOBBER, we will fail so return it; if it is a
7259 CONST_INT, we are done. */
7260 if (GET_CODE (varop) == CLOBBER || GET_CODE (varop) == CONST_INT)
7263 /* See what bits may be nonzero in VAROP. Unlike the general case of
7264 a call to nonzero_bits, here we don't care about bits outside
7267 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
7269 /* If this would be an entire word for the target, but is not for
7270 the host, then sign-extend on the host so that the number will look
7271 the same way on the host that it would on the target.
7273 For example, when building a 64 bit alpha hosted 32 bit sparc
7274 targeted compiler, then we want the 32 bit unsigned value -1 to be
7275 represented as a 64 bit value -1, and not as 0x00000000ffffffff.
7276 The later confuses the sparc backend. */
7278 if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT && BITS_PER_WORD == width
7279 && (nonzero & ((HOST_WIDE_INT) 1 << (width - 1))))
7280 nonzero |= ((HOST_WIDE_INT) (-1) << width);
7282 /* Turn off all bits in the constant that are known to already be zero.
7283 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7284 which is tested below. */
7288 /* If we don't have any bits left, return zero. */
7292 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7293 a power of two, we can replace this with a ASHIFT. */
7294 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
7295 && (i = exact_log2 (constop)) >= 0)
7296 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
7298 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7299 or XOR, then try to apply the distributive law. This may eliminate
7300 operations if either branch can be simplified because of the AND.
7301 It may also make some cases more complex, but those cases probably
7302 won't match a pattern either with or without this. */
7304 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
7306 gen_lowpart_for_combine
7308 apply_distributive_law
7309 (gen_binary (GET_CODE (varop), GET_MODE (varop),
7310 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7311 XEXP (varop, 0), constop),
7312 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7313 XEXP (varop, 1), constop))));
7315 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7316 if we already had one (just check for the simplest cases). */
7317 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
7318 && GET_MODE (XEXP (x, 0)) == mode
7319 && SUBREG_REG (XEXP (x, 0)) == varop)
7320 varop = XEXP (x, 0);
7322 varop = gen_lowpart_for_combine (mode, varop);
7324 /* If we can't make the SUBREG, try to return what we were given. */
7325 if (GET_CODE (varop) == CLOBBER)
7326 return x ? x : varop;
7328 /* If we are only masking insignificant bits, return VAROP. */
7329 if (constop == nonzero)
7332 /* Otherwise, return an AND. See how much, if any, of X we can use. */
7333 else if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
7334 x = gen_binary (AND, mode, varop, GEN_INT (constop));
7338 if (GET_CODE (XEXP (x, 1)) != CONST_INT
7339 || INTVAL (XEXP (x, 1)) != constop)
7340 SUBST (XEXP (x, 1), GEN_INT (constop));
7342 SUBST (XEXP (x, 0), varop);
7348 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
7349 We don't let nonzero_bits recur into num_sign_bit_copies, because that
7350 is less useful. We can't allow both, because that results in exponential
7351 run time recursion. There is a nullstone testcase that triggered
7352 this. This macro avoids accidental uses of num_sign_bit_copies. */
7353 #define num_sign_bit_copies()
7355 /* Given an expression, X, compute which bits in X can be non-zero.
7356 We don't care about bits outside of those defined in MODE.
7358 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
7359 a shift, AND, or zero_extract, we can do better. */
7361 static unsigned HOST_WIDE_INT
7362 nonzero_bits (x, mode)
7364 enum machine_mode mode;
7366 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
7367 unsigned HOST_WIDE_INT inner_nz;
7369 int mode_width = GET_MODE_BITSIZE (mode);
7372 /* For floating-point values, assume all bits are needed. */
7373 if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode))
7376 /* If X is wider than MODE, use its mode instead. */
7377 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
7379 mode = GET_MODE (x);
7380 nonzero = GET_MODE_MASK (mode);
7381 mode_width = GET_MODE_BITSIZE (mode);
7384 if (mode_width > HOST_BITS_PER_WIDE_INT)
7385 /* Our only callers in this case look for single bit values. So
7386 just return the mode mask. Those tests will then be false. */
7389 #ifndef WORD_REGISTER_OPERATIONS
7390 /* If MODE is wider than X, but both are a single word for both the host
7391 and target machines, we can compute this from which bits of the
7392 object might be nonzero in its own mode, taking into account the fact
7393 that on many CISC machines, accessing an object in a wider mode
7394 causes the high-order bits to become undefined. So they are
7395 not known to be zero. */
7397 if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
7398 && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD
7399 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7400 && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x)))
7402 nonzero &= nonzero_bits (x, GET_MODE (x));
7403 nonzero |= GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x));
7408 code = GET_CODE (x);
7412 #ifdef POINTERS_EXTEND_UNSIGNED
7413 /* If pointers extend unsigned and this is a pointer in Pmode, say that
7414 all the bits above ptr_mode are known to be zero. */
7415 if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
7416 && REGNO_POINTER_FLAG (REGNO (x)))
7417 nonzero &= GET_MODE_MASK (ptr_mode);
7420 #ifdef STACK_BOUNDARY
7421 /* If this is the stack pointer, we may know something about its
7422 alignment. If PUSH_ROUNDING is defined, it is possible for the
7423 stack to be momentarily aligned only to that amount, so we pick
7424 the least alignment. */
7426 /* We can't check for arg_pointer_rtx here, because it is not
7427 guaranteed to have as much alignment as the stack pointer.
7428 In particular, in the Irix6 n64 ABI, the stack has 128 bit
7429 alignment but the argument pointer has only 64 bit alignment. */
7431 if ((x == frame_pointer_rtx
7432 || x == stack_pointer_rtx
7433 || x == hard_frame_pointer_rtx
7434 || (REGNO (x) >= FIRST_VIRTUAL_REGISTER
7435 && REGNO (x) <= LAST_VIRTUAL_REGISTER))
7441 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
7443 #ifdef PUSH_ROUNDING
7444 if (REGNO (x) == STACK_POINTER_REGNUM)
7445 sp_alignment = MIN (PUSH_ROUNDING (1), sp_alignment);
7448 /* We must return here, otherwise we may get a worse result from
7449 one of the choices below. There is nothing useful below as
7450 far as the stack pointer is concerned. */
7451 return nonzero &= ~ (sp_alignment - 1);
7455 /* If X is a register whose nonzero bits value is current, use it.
7456 Otherwise, if X is a register whose value we can find, use that
7457 value. Otherwise, use the previously-computed global nonzero bits
7458 for this register. */
7460 if (reg_last_set_value[REGNO (x)] != 0
7461 && reg_last_set_mode[REGNO (x)] == mode
7462 && (REG_N_SETS (REGNO (x)) == 1
7463 || reg_last_set_label[REGNO (x)] == label_tick)
7464 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
7465 return reg_last_set_nonzero_bits[REGNO (x)];
7467 tem = get_last_value (x);
7471 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7472 /* If X is narrower than MODE and TEM is a non-negative
7473 constant that would appear negative in the mode of X,
7474 sign-extend it for use in reg_nonzero_bits because some
7475 machines (maybe most) will actually do the sign-extension
7476 and this is the conservative approach.
7478 ??? For 2.5, try to tighten up the MD files in this regard
7479 instead of this kludge. */
7481 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width
7482 && GET_CODE (tem) == CONST_INT
7484 && 0 != (INTVAL (tem)
7485 & ((HOST_WIDE_INT) 1
7486 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7487 tem = GEN_INT (INTVAL (tem)
7488 | ((HOST_WIDE_INT) (-1)
7489 << GET_MODE_BITSIZE (GET_MODE (x))));
7491 return nonzero_bits (tem, mode);
7493 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
7494 return reg_nonzero_bits[REGNO (x)] & nonzero;
7499 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7500 /* If X is negative in MODE, sign-extend the value. */
7501 if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD
7502 && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1))))
7503 return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width));
7509 #ifdef LOAD_EXTEND_OP
7510 /* In many, if not most, RISC machines, reading a byte from memory
7511 zeros the rest of the register. Noticing that fact saves a lot
7512 of extra zero-extends. */
7513 if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND)
7514 nonzero &= GET_MODE_MASK (GET_MODE (x));
7524 /* If this produces an integer result, we know which bits are set.
7525 Code here used to clear bits outside the mode of X, but that is
7528 if (GET_MODE_CLASS (mode) == MODE_INT
7529 && mode_width <= HOST_BITS_PER_WIDE_INT)
7530 nonzero = STORE_FLAG_VALUE;
7535 /* Disabled to avoid exponential mutual recursion between nonzero_bits
7536 and num_sign_bit_copies. */
7537 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
7538 == GET_MODE_BITSIZE (GET_MODE (x)))
7542 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
7543 nonzero |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x)));
7548 /* Disabled to avoid exponential mutual recursion between nonzero_bits
7549 and num_sign_bit_copies. */
7550 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
7551 == GET_MODE_BITSIZE (GET_MODE (x)))
7557 nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode));
7561 nonzero &= nonzero_bits (XEXP (x, 0), mode);
7562 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
7563 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
7567 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
7568 Otherwise, show all the bits in the outer mode but not the inner
7570 inner_nz = nonzero_bits (XEXP (x, 0), mode);
7571 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
7573 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
7575 & (((HOST_WIDE_INT) 1
7576 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
7577 inner_nz |= (GET_MODE_MASK (mode)
7578 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
7581 nonzero &= inner_nz;
7585 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
7586 & nonzero_bits (XEXP (x, 1), mode));
7590 case UMIN: case UMAX: case SMIN: case SMAX:
7591 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
7592 | nonzero_bits (XEXP (x, 1), mode));
7595 case PLUS: case MINUS:
7597 case DIV: case UDIV:
7598 case MOD: case UMOD:
7599 /* We can apply the rules of arithmetic to compute the number of
7600 high- and low-order zero bits of these operations. We start by
7601 computing the width (position of the highest-order non-zero bit)
7602 and the number of low-order zero bits for each value. */
7604 unsigned HOST_WIDE_INT nz0 = nonzero_bits (XEXP (x, 0), mode);
7605 unsigned HOST_WIDE_INT nz1 = nonzero_bits (XEXP (x, 1), mode);
7606 int width0 = floor_log2 (nz0) + 1;
7607 int width1 = floor_log2 (nz1) + 1;
7608 int low0 = floor_log2 (nz0 & -nz0);
7609 int low1 = floor_log2 (nz1 & -nz1);
7610 HOST_WIDE_INT op0_maybe_minusp
7611 = (nz0 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
7612 HOST_WIDE_INT op1_maybe_minusp
7613 = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
7614 int result_width = mode_width;
7622 && (XEXP (x, 0) == stack_pointer_rtx
7623 || XEXP (x, 0) == frame_pointer_rtx)
7624 && GET_CODE (XEXP (x, 1)) == CONST_INT)
7626 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
7628 nz0 = (GET_MODE_MASK (mode) & ~ (sp_alignment - 1));
7629 nz1 = INTVAL (XEXP (x, 1)) - STACK_BIAS;
7630 width0 = floor_log2 (nz0) + 1;
7631 width1 = floor_log2 (nz1) + 1;
7632 low0 = floor_log2 (nz0 & -nz0);
7633 low1 = floor_log2 (nz1 & -nz1);
7636 result_width = MAX (width0, width1) + 1;
7637 result_low = MIN (low0, low1);
7640 result_low = MIN (low0, low1);
7643 result_width = width0 + width1;
7644 result_low = low0 + low1;
7647 if (! op0_maybe_minusp && ! op1_maybe_minusp)
7648 result_width = width0;
7651 result_width = width0;
7654 if (! op0_maybe_minusp && ! op1_maybe_minusp)
7655 result_width = MIN (width0, width1);
7656 result_low = MIN (low0, low1);
7659 result_width = MIN (width0, width1);
7660 result_low = MIN (low0, low1);
7666 if (result_width < mode_width)
7667 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
7670 nonzero &= ~ (((HOST_WIDE_INT) 1 << result_low) - 1);
7675 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7676 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7677 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
7681 /* If this is a SUBREG formed for a promoted variable that has
7682 been zero-extended, we know that at least the high-order bits
7683 are zero, though others might be too. */
7685 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x))
7686 nonzero = (GET_MODE_MASK (GET_MODE (x))
7687 & nonzero_bits (SUBREG_REG (x), GET_MODE (x)));
7689 /* If the inner mode is a single word for both the host and target
7690 machines, we can compute this from which bits of the inner
7691 object might be nonzero. */
7692 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
7693 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
7694 <= HOST_BITS_PER_WIDE_INT))
7696 nonzero &= nonzero_bits (SUBREG_REG (x), mode);
7698 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
7699 /* If this is a typical RISC machine, we only have to worry
7700 about the way loads are extended. */
7701 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
7703 & (1L << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) - 1)))
7704 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) != ZERO_EXTEND)
7707 /* On many CISC machines, accessing an object in a wider mode
7708 causes the high-order bits to become undefined. So they are
7709 not known to be zero. */
7710 if (GET_MODE_SIZE (GET_MODE (x))
7711 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7712 nonzero |= (GET_MODE_MASK (GET_MODE (x))
7713 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
7722 /* The nonzero bits are in two classes: any bits within MODE
7723 that aren't in GET_MODE (x) are always significant. The rest of the
7724 nonzero bits are those that are significant in the operand of
7725 the shift when shifted the appropriate number of bits. This
7726 shows that high-order bits are cleared by the right shift and
7727 low-order bits by left shifts. */
7728 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7729 && INTVAL (XEXP (x, 1)) >= 0
7730 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7732 enum machine_mode inner_mode = GET_MODE (x);
7733 int width = GET_MODE_BITSIZE (inner_mode);
7734 int count = INTVAL (XEXP (x, 1));
7735 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
7736 unsigned HOST_WIDE_INT op_nonzero = nonzero_bits (XEXP (x, 0), mode);
7737 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
7738 unsigned HOST_WIDE_INT outer = 0;
7740 if (mode_width > width)
7741 outer = (op_nonzero & nonzero & ~ mode_mask);
7743 if (code == LSHIFTRT)
7745 else if (code == ASHIFTRT)
7749 /* If the sign bit may have been nonzero before the shift, we
7750 need to mark all the places it could have been copied to
7751 by the shift as possibly nonzero. */
7752 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
7753 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
7755 else if (code == ASHIFT)
7758 inner = ((inner << (count % width)
7759 | (inner >> (width - (count % width)))) & mode_mask);
7761 nonzero &= (outer | inner);
7766 /* This is at most the number of bits in the mode. */
7767 nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1;
7771 nonzero &= (nonzero_bits (XEXP (x, 1), mode)
7772 | nonzero_bits (XEXP (x, 2), mode));
7782 /* See the macro definition above. */
7783 #undef num_sign_bit_copies
7785 /* Return the number of bits at the high-order end of X that are known to
7786 be equal to the sign bit. X will be used in mode MODE; if MODE is
7787 VOIDmode, X will be used in its own mode. The returned value will always
7788 be between 1 and the number of bits in MODE. */
7791 num_sign_bit_copies (x, mode)
7793 enum machine_mode mode;
7795 enum rtx_code code = GET_CODE (x);
7797 int num0, num1, result;
7798 unsigned HOST_WIDE_INT nonzero;
7801 /* If we weren't given a mode, use the mode of X. If the mode is still
7802 VOIDmode, we don't know anything. Likewise if one of the modes is
7805 if (mode == VOIDmode)
7806 mode = GET_MODE (x);
7808 if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)))
7811 bitwidth = GET_MODE_BITSIZE (mode);
7813 /* For a smaller object, just ignore the high bits. */
7814 if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
7815 return MAX (1, (num_sign_bit_copies (x, GET_MODE (x))
7816 - (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth)));
7818 if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x)))
7820 #ifndef WORD_REGISTER_OPERATIONS
7821 /* If this machine does not do all register operations on the entire
7822 register and MODE is wider than the mode of X, we can say nothing
7823 at all about the high-order bits. */
7826 /* Likewise on machines that do, if the mode of the object is smaller
7827 than a word and loads of that size don't sign extend, we can say
7828 nothing about the high order bits. */
7829 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
7830 #ifdef LOAD_EXTEND_OP
7831 && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND
7842 #ifdef POINTERS_EXTEND_UNSIGNED
7843 /* If pointers extend signed and this is a pointer in Pmode, say that
7844 all the bits above ptr_mode are known to be sign bit copies. */
7845 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
7846 && REGNO_POINTER_FLAG (REGNO (x)))
7847 return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1;
7850 if (reg_last_set_value[REGNO (x)] != 0
7851 && reg_last_set_mode[REGNO (x)] == mode
7852 && (REG_N_SETS (REGNO (x)) == 1
7853 || reg_last_set_label[REGNO (x)] == label_tick)
7854 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
7855 return reg_last_set_sign_bit_copies[REGNO (x)];
7857 tem = get_last_value (x);
7859 return num_sign_bit_copies (tem, mode);
7861 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0)
7862 return reg_sign_bit_copies[REGNO (x)];
7866 #ifdef LOAD_EXTEND_OP
7867 /* Some RISC machines sign-extend all loads of smaller than a word. */
7868 if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
7869 return MAX (1, bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1);
7874 /* If the constant is negative, take its 1's complement and remask.
7875 Then see how many zero bits we have. */
7876 nonzero = INTVAL (x) & GET_MODE_MASK (mode);
7877 if (bitwidth <= HOST_BITS_PER_WIDE_INT
7878 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7879 nonzero = (~ nonzero) & GET_MODE_MASK (mode);
7881 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
7884 /* If this is a SUBREG for a promoted object that is sign-extended
7885 and we are looking at it in a wider mode, we know that at least the
7886 high-order bits are known to be sign bit copies. */
7888 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
7889 return MAX (bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1,
7890 num_sign_bit_copies (SUBREG_REG (x), mode));
7892 /* For a smaller object, just ignore the high bits. */
7893 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
7895 num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode);
7896 return MAX (1, (num0
7897 - (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
7901 #ifdef WORD_REGISTER_OPERATIONS
7902 #ifdef LOAD_EXTEND_OP
7903 /* For paradoxical SUBREGs on machines where all register operations
7904 affect the entire register, just look inside. Note that we are
7905 passing MODE to the recursive call, so the number of sign bit copies
7906 will remain relative to that mode, not the inner mode. */
7908 /* This works only if loads sign extend. Otherwise, if we get a
7909 reload for the inner part, it may be loaded from the stack, and
7910 then we lose all sign bit copies that existed before the store
7913 if ((GET_MODE_SIZE (GET_MODE (x))
7914 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7915 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND)
7916 return num_sign_bit_copies (SUBREG_REG (x), mode);
7922 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
7923 return MAX (1, bitwidth - INTVAL (XEXP (x, 1)));
7927 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
7928 + num_sign_bit_copies (XEXP (x, 0), VOIDmode));
7931 /* For a smaller object, just ignore the high bits. */
7932 num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode);
7933 return MAX (1, (num0 - (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
7937 return num_sign_bit_copies (XEXP (x, 0), mode);
7939 case ROTATE: case ROTATERT:
7940 /* If we are rotating left by a number of bits less than the number
7941 of sign bit copies, we can just subtract that amount from the
7943 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7944 && INTVAL (XEXP (x, 1)) >= 0 && INTVAL (XEXP (x, 1)) < bitwidth)
7946 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7947 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
7948 : bitwidth - INTVAL (XEXP (x, 1))));
7953 /* In general, this subtracts one sign bit copy. But if the value
7954 is known to be positive, the number of sign bit copies is the
7955 same as that of the input. Finally, if the input has just one bit
7956 that might be nonzero, all the bits are copies of the sign bit. */
7957 nonzero = nonzero_bits (XEXP (x, 0), mode);
7961 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7963 && bitwidth <= HOST_BITS_PER_WIDE_INT
7964 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
7969 case IOR: case AND: case XOR:
7970 case SMIN: case SMAX: case UMIN: case UMAX:
7971 /* Logical operations will preserve the number of sign-bit copies.
7972 MIN and MAX operations always return one of the operands. */
7973 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7974 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
7975 return MIN (num0, num1);
7977 case PLUS: case MINUS:
7978 /* For addition and subtraction, we can have a 1-bit carry. However,
7979 if we are subtracting 1 from a positive number, there will not
7980 be such a carry. Furthermore, if the positive number is known to
7981 be 0 or 1, we know the result is either -1 or 0. */
7983 if (code == PLUS && XEXP (x, 1) == constm1_rtx
7984 && bitwidth <= HOST_BITS_PER_WIDE_INT)
7986 nonzero = nonzero_bits (XEXP (x, 0), mode);
7987 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
7988 return (nonzero == 1 || nonzero == 0 ? bitwidth
7989 : bitwidth - floor_log2 (nonzero) - 1);
7992 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7993 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
7994 return MAX (1, MIN (num0, num1) - 1);
7997 /* The number of bits of the product is the sum of the number of
7998 bits of both terms. However, unless one of the terms if known
7999 to be positive, we must allow for an additional bit since negating
8000 a negative number can remove one sign bit copy. */
8002 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8003 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8005 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
8007 && bitwidth <= HOST_BITS_PER_WIDE_INT
8008 && ((nonzero_bits (XEXP (x, 0), mode)
8009 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8010 && ((nonzero_bits (XEXP (x, 1), mode)
8011 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8014 return MAX (1, result);
8017 /* The result must be <= the first operand. */
8018 return num_sign_bit_copies (XEXP (x, 0), mode);
8021 /* The result must be <= the scond operand. */
8022 return num_sign_bit_copies (XEXP (x, 1), mode);
8025 /* Similar to unsigned division, except that we have to worry about
8026 the case where the divisor is negative, in which case we have
8028 result = num_sign_bit_copies (XEXP (x, 0), mode);
8030 && bitwidth <= HOST_BITS_PER_WIDE_INT
8031 && (nonzero_bits (XEXP (x, 1), mode)
8032 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8038 result = num_sign_bit_copies (XEXP (x, 1), mode);
8040 && bitwidth <= HOST_BITS_PER_WIDE_INT
8041 && (nonzero_bits (XEXP (x, 1), mode)
8042 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8048 /* Shifts by a constant add to the number of bits equal to the
8050 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8051 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8052 && INTVAL (XEXP (x, 1)) > 0)
8053 num0 = MIN (bitwidth, num0 + INTVAL (XEXP (x, 1)));
8058 /* Left shifts destroy copies. */
8059 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8060 || INTVAL (XEXP (x, 1)) < 0
8061 || INTVAL (XEXP (x, 1)) >= bitwidth)
8064 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8065 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
8068 num0 = num_sign_bit_copies (XEXP (x, 1), mode);
8069 num1 = num_sign_bit_copies (XEXP (x, 2), mode);
8070 return MIN (num0, num1);
8072 case EQ: case NE: case GE: case GT: case LE: case LT:
8073 case GEU: case GTU: case LEU: case LTU:
8074 if (STORE_FLAG_VALUE == -1)
8082 /* If we haven't been able to figure it out by one of the above rules,
8083 see if some of the high-order bits are known to be zero. If so,
8084 count those bits and return one less than that amount. If we can't
8085 safely compute the mask for this mode, always return BITWIDTH. */
8087 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8090 nonzero = nonzero_bits (x, mode);
8091 return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
8092 ? 1 : bitwidth - floor_log2 (nonzero) - 1);
8095 /* Return the number of "extended" bits there are in X, when interpreted
8096 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8097 unsigned quantities, this is the number of high-order zero bits.
8098 For signed quantities, this is the number of copies of the sign bit
8099 minus 1. In both case, this function returns the number of "spare"
8100 bits. For example, if two quantities for which this function returns
8101 at least 1 are added, the addition is known not to overflow.
8103 This function will always return 0 unless called during combine, which
8104 implies that it must be called from a define_split. */
8107 extended_count (x, mode, unsignedp)
8109 enum machine_mode mode;
8112 if (nonzero_sign_valid == 0)
8116 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8117 && (GET_MODE_BITSIZE (mode) - 1
8118 - floor_log2 (nonzero_bits (x, mode))))
8119 : num_sign_bit_copies (x, mode) - 1);
8122 /* This function is called from `simplify_shift_const' to merge two
8123 outer operations. Specifically, we have already found that we need
8124 to perform operation *POP0 with constant *PCONST0 at the outermost
8125 position. We would now like to also perform OP1 with constant CONST1
8126 (with *POP0 being done last).
8128 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8129 the resulting operation. *PCOMP_P is set to 1 if we would need to
8130 complement the innermost operand, otherwise it is unchanged.
8132 MODE is the mode in which the operation will be done. No bits outside
8133 the width of this mode matter. It is assumed that the width of this mode
8134 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8136 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8137 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8138 result is simply *PCONST0.
8140 If the resulting operation cannot be expressed as one operation, we
8141 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8144 merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
8145 enum rtx_code *pop0;
8146 HOST_WIDE_INT *pconst0;
8148 HOST_WIDE_INT const1;
8149 enum machine_mode mode;
8152 enum rtx_code op0 = *pop0;
8153 HOST_WIDE_INT const0 = *pconst0;
8154 int width = GET_MODE_BITSIZE (mode);
8156 const0 &= GET_MODE_MASK (mode);
8157 const1 &= GET_MODE_MASK (mode);
8159 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8163 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
8166 if (op1 == NIL || op0 == SET)
8169 else if (op0 == NIL)
8170 op0 = op1, const0 = const1;
8172 else if (op0 == op1)
8196 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8197 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8200 /* If the two constants aren't the same, we can't do anything. The
8201 remaining six cases can all be done. */
8202 else if (const0 != const1)
8210 /* (a & b) | b == b */
8212 else /* op1 == XOR */
8213 /* (a ^ b) | b == a | b */
8219 /* (a & b) ^ b == (~a) & b */
8220 op0 = AND, *pcomp_p = 1;
8221 else /* op1 == IOR */
8222 /* (a | b) ^ b == a & ~b */
8223 op0 = AND, *pconst0 = ~ const0;
8228 /* (a | b) & b == b */
8230 else /* op1 == XOR */
8231 /* (a ^ b) & b) == (~a) & b */
8238 /* Check for NO-OP cases. */
8239 const0 &= GET_MODE_MASK (mode);
8241 && (op0 == IOR || op0 == XOR || op0 == PLUS))
8243 else if (const0 == 0 && op0 == AND)
8245 else if (const0 == GET_MODE_MASK (mode) && op0 == AND)
8248 /* If this would be an entire word for the target, but is not for
8249 the host, then sign-extend on the host so that the number will look
8250 the same way on the host that it would on the target.
8252 For example, when building a 64 bit alpha hosted 32 bit sparc
8253 targeted compiler, then we want the 32 bit unsigned value -1 to be
8254 represented as a 64 bit value -1, and not as 0x00000000ffffffff.
8255 The later confuses the sparc backend. */
8257 if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT && BITS_PER_WORD == width
8258 && (const0 & ((HOST_WIDE_INT) 1 << (width - 1))))
8259 const0 |= ((HOST_WIDE_INT) (-1) << width);
8267 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8268 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
8269 that we started with.
8271 The shift is normally computed in the widest mode we find in VAROP, as
8272 long as it isn't a different number of words than RESULT_MODE. Exceptions
8273 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8276 simplify_shift_const (x, code, result_mode, varop, count)
8279 enum machine_mode result_mode;
8283 enum rtx_code orig_code = code;
8284 int orig_count = count;
8285 enum machine_mode mode = result_mode;
8286 enum machine_mode shift_mode, tmode;
8288 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8289 /* We form (outer_op (code varop count) (outer_const)). */
8290 enum rtx_code outer_op = NIL;
8291 HOST_WIDE_INT outer_const = 0;
8293 int complement_p = 0;
8296 /* If we were given an invalid count, don't do anything except exactly
8297 what was requested. */
8299 if (count < 0 || count > GET_MODE_BITSIZE (mode))
8304 return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (count));
8307 /* Unless one of the branches of the `if' in this loop does a `continue',
8308 we will `break' the loop after the `if'. */
8312 /* If we have an operand of (clobber (const_int 0)), just return that
8314 if (GET_CODE (varop) == CLOBBER)
8317 /* If we discovered we had to complement VAROP, leave. Making a NOT
8318 here would cause an infinite loop. */
8322 /* Convert ROTATERT to ROTATE. */
8323 if (code == ROTATERT)
8324 code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count;
8326 /* We need to determine what mode we will do the shift in. If the
8327 shift is a right shift or a ROTATE, we must always do it in the mode
8328 it was originally done in. Otherwise, we can do it in MODE, the
8329 widest mode encountered. */
8331 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8332 ? result_mode : mode);
8334 /* Handle cases where the count is greater than the size of the mode
8335 minus 1. For ASHIFT, use the size minus one as the count (this can
8336 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8337 take the count modulo the size. For other shifts, the result is
8340 Since these shifts are being produced by the compiler by combining
8341 multiple operations, each of which are defined, we know what the
8342 result is supposed to be. */
8344 if (count > GET_MODE_BITSIZE (shift_mode) - 1)
8346 if (code == ASHIFTRT)
8347 count = GET_MODE_BITSIZE (shift_mode) - 1;
8348 else if (code == ROTATE || code == ROTATERT)
8349 count %= GET_MODE_BITSIZE (shift_mode);
8352 /* We can't simply return zero because there may be an
8360 /* Negative counts are invalid and should not have been made (a
8361 programmer-specified negative count should have been handled
8366 /* An arithmetic right shift of a quantity known to be -1 or 0
8368 if (code == ASHIFTRT
8369 && (num_sign_bit_copies (varop, shift_mode)
8370 == GET_MODE_BITSIZE (shift_mode)))
8376 /* If we are doing an arithmetic right shift and discarding all but
8377 the sign bit copies, this is equivalent to doing a shift by the
8378 bitsize minus one. Convert it into that shift because it will often
8379 allow other simplifications. */
8381 if (code == ASHIFTRT
8382 && (count + num_sign_bit_copies (varop, shift_mode)
8383 >= GET_MODE_BITSIZE (shift_mode)))
8384 count = GET_MODE_BITSIZE (shift_mode) - 1;
8386 /* We simplify the tests below and elsewhere by converting
8387 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8388 `make_compound_operation' will convert it to a ASHIFTRT for
8389 those machines (such as Vax) that don't have a LSHIFTRT. */
8390 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8392 && ((nonzero_bits (varop, shift_mode)
8393 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
8397 switch (GET_CODE (varop))
8403 new = expand_compound_operation (varop);
8412 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8413 minus the width of a smaller mode, we can do this with a
8414 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
8415 if ((code == ASHIFTRT || code == LSHIFTRT)
8416 && ! mode_dependent_address_p (XEXP (varop, 0))
8417 && ! MEM_VOLATILE_P (varop)
8418 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8419 MODE_INT, 1)) != BLKmode)
8421 if (BYTES_BIG_ENDIAN)
8422 new = gen_rtx_MEM (tmode, XEXP (varop, 0));
8424 new = gen_rtx_MEM (tmode,
8425 plus_constant (XEXP (varop, 0),
8426 count / BITS_PER_UNIT));
8427 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (varop);
8428 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (varop);
8429 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (varop);
8430 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
8431 : ZERO_EXTEND, mode, new);
8438 /* Similar to the case above, except that we can only do this if
8439 the resulting mode is the same as that of the underlying
8440 MEM and adjust the address depending on the *bits* endianness
8441 because of the way that bit-field extract insns are defined. */
8442 if ((code == ASHIFTRT || code == LSHIFTRT)
8443 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8444 MODE_INT, 1)) != BLKmode
8445 && tmode == GET_MODE (XEXP (varop, 0)))
8447 if (BITS_BIG_ENDIAN)
8448 new = XEXP (varop, 0);
8451 new = copy_rtx (XEXP (varop, 0));
8452 SUBST (XEXP (new, 0),
8453 plus_constant (XEXP (new, 0),
8454 count / BITS_PER_UNIT));
8457 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
8458 : ZERO_EXTEND, mode, new);
8465 /* If VAROP is a SUBREG, strip it as long as the inner operand has
8466 the same number of words as what we've seen so far. Then store
8467 the widest mode in MODE. */
8468 if (subreg_lowpart_p (varop)
8469 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8470 > GET_MODE_SIZE (GET_MODE (varop)))
8471 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8472 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
8475 varop = SUBREG_REG (varop);
8476 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
8477 mode = GET_MODE (varop);
8483 /* Some machines use MULT instead of ASHIFT because MULT
8484 is cheaper. But it is still better on those machines to
8485 merge two shifts into one. */
8486 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8487 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8489 varop = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
8490 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));;
8496 /* Similar, for when divides are cheaper. */
8497 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8498 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8500 varop = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
8501 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
8507 /* If we are extracting just the sign bit of an arithmetic right
8508 shift, that shift is not needed. */
8509 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1)
8511 varop = XEXP (varop, 0);
8515 /* ... fall through ... */
8520 /* Here we have two nested shifts. The result is usually the
8521 AND of a new shift with a mask. We compute the result below. */
8522 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8523 && INTVAL (XEXP (varop, 1)) >= 0
8524 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
8525 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8526 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
8528 enum rtx_code first_code = GET_CODE (varop);
8529 int first_count = INTVAL (XEXP (varop, 1));
8530 unsigned HOST_WIDE_INT mask;
8533 /* We have one common special case. We can't do any merging if
8534 the inner code is an ASHIFTRT of a smaller mode. However, if
8535 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8536 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8537 we can convert it to
8538 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8539 This simplifies certain SIGN_EXTEND operations. */
8540 if (code == ASHIFT && first_code == ASHIFTRT
8541 && (GET_MODE_BITSIZE (result_mode)
8542 - GET_MODE_BITSIZE (GET_MODE (varop))) == count)
8544 /* C3 has the low-order C1 bits zero. */
8546 mask = (GET_MODE_MASK (mode)
8547 & ~ (((HOST_WIDE_INT) 1 << first_count) - 1));
8549 varop = simplify_and_const_int (NULL_RTX, result_mode,
8550 XEXP (varop, 0), mask);
8551 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
8553 count = first_count;
8558 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8559 than C1 high-order bits equal to the sign bit, we can convert
8560 this to either an ASHIFT or a ASHIFTRT depending on the
8563 We cannot do this if VAROP's mode is not SHIFT_MODE. */
8565 if (code == ASHIFTRT && first_code == ASHIFT
8566 && GET_MODE (varop) == shift_mode
8567 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
8570 count -= first_count;
8572 count = - count, code = ASHIFT;
8573 varop = XEXP (varop, 0);
8577 /* There are some cases we can't do. If CODE is ASHIFTRT,
8578 we can only do this if FIRST_CODE is also ASHIFTRT.
8580 We can't do the case when CODE is ROTATE and FIRST_CODE is
8583 If the mode of this shift is not the mode of the outer shift,
8584 we can't do this if either shift is a right shift or ROTATE.
8586 Finally, we can't do any of these if the mode is too wide
8587 unless the codes are the same.
8589 Handle the case where the shift codes are the same
8592 if (code == first_code)
8594 if (GET_MODE (varop) != result_mode
8595 && (code == ASHIFTRT || code == LSHIFTRT
8599 count += first_count;
8600 varop = XEXP (varop, 0);
8604 if (code == ASHIFTRT
8605 || (code == ROTATE && first_code == ASHIFTRT)
8606 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
8607 || (GET_MODE (varop) != result_mode
8608 && (first_code == ASHIFTRT || first_code == LSHIFTRT
8609 || first_code == ROTATE
8610 || code == ROTATE)))
8613 /* To compute the mask to apply after the shift, shift the
8614 nonzero bits of the inner shift the same way the
8615 outer shift will. */
8617 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
8620 = simplify_binary_operation (code, result_mode, mask_rtx,
8623 /* Give up if we can't compute an outer operation to use. */
8625 || GET_CODE (mask_rtx) != CONST_INT
8626 || ! merge_outer_ops (&outer_op, &outer_const, AND,
8628 result_mode, &complement_p))
8631 /* If the shifts are in the same direction, we add the
8632 counts. Otherwise, we subtract them. */
8633 if ((code == ASHIFTRT || code == LSHIFTRT)
8634 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
8635 count += first_count;
8637 count -= first_count;
8639 /* If COUNT is positive, the new shift is usually CODE,
8640 except for the two exceptions below, in which case it is
8641 FIRST_CODE. If the count is negative, FIRST_CODE should
8644 && ((first_code == ROTATE && code == ASHIFT)
8645 || (first_code == ASHIFTRT && code == LSHIFTRT)))
8648 code = first_code, count = - count;
8650 varop = XEXP (varop, 0);
8654 /* If we have (A << B << C) for any shift, we can convert this to
8655 (A << C << B). This wins if A is a constant. Only try this if
8656 B is not a constant. */
8658 else if (GET_CODE (varop) == code
8659 && GET_CODE (XEXP (varop, 1)) != CONST_INT
8661 = simplify_binary_operation (code, mode,
8665 varop = gen_rtx_combine (code, mode, new, XEXP (varop, 1));
8672 /* Make this fit the case below. */
8673 varop = gen_rtx_combine (XOR, mode, XEXP (varop, 0),
8674 GEN_INT (GET_MODE_MASK (mode)));
8680 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
8681 with C the size of VAROP - 1 and the shift is logical if
8682 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8683 we have an (le X 0) operation. If we have an arithmetic shift
8684 and STORE_FLAG_VALUE is 1 or we have a logical shift with
8685 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
8687 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
8688 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
8689 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8690 && (code == LSHIFTRT || code == ASHIFTRT)
8691 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
8692 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8695 varop = gen_rtx_combine (LE, GET_MODE (varop), XEXP (varop, 1),
8698 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8699 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
8704 /* If we have (shift (logical)), move the logical to the outside
8705 to allow it to possibly combine with another logical and the
8706 shift to combine with another shift. This also canonicalizes to
8707 what a ZERO_EXTRACT looks like. Also, some machines have
8708 (and (shift)) insns. */
8710 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8711 && (new = simplify_binary_operation (code, result_mode,
8713 GEN_INT (count))) != 0
8714 && GET_CODE(new) == CONST_INT
8715 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
8716 INTVAL (new), result_mode, &complement_p))
8718 varop = XEXP (varop, 0);
8722 /* If we can't do that, try to simplify the shift in each arm of the
8723 logical expression, make a new logical expression, and apply
8724 the inverse distributive law. */
8726 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8727 XEXP (varop, 0), count);
8728 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8729 XEXP (varop, 1), count);
8731 varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
8732 varop = apply_distributive_law (varop);
8739 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
8740 says that the sign bit can be tested, FOO has mode MODE, C is
8741 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
8742 that may be nonzero. */
8743 if (code == LSHIFTRT
8744 && XEXP (varop, 1) == const0_rtx
8745 && GET_MODE (XEXP (varop, 0)) == result_mode
8746 && count == GET_MODE_BITSIZE (result_mode) - 1
8747 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8748 && ((STORE_FLAG_VALUE
8749 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (result_mode) - 1))))
8750 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
8751 && merge_outer_ops (&outer_op, &outer_const, XOR,
8752 (HOST_WIDE_INT) 1, result_mode,
8755 varop = XEXP (varop, 0);
8762 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
8763 than the number of bits in the mode is equivalent to A. */
8764 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
8765 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
8767 varop = XEXP (varop, 0);
8772 /* NEG commutes with ASHIFT since it is multiplication. Move the
8773 NEG outside to allow shifts to combine. */
8775 && merge_outer_ops (&outer_op, &outer_const, NEG,
8776 (HOST_WIDE_INT) 0, result_mode,
8779 varop = XEXP (varop, 0);
8785 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
8786 is one less than the number of bits in the mode is
8787 equivalent to (xor A 1). */
8788 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
8789 && XEXP (varop, 1) == constm1_rtx
8790 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
8791 && merge_outer_ops (&outer_op, &outer_const, XOR,
8792 (HOST_WIDE_INT) 1, result_mode,
8796 varop = XEXP (varop, 0);
8800 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
8801 that might be nonzero in BAR are those being shifted out and those
8802 bits are known zero in FOO, we can replace the PLUS with FOO.
8803 Similarly in the other operand order. This code occurs when
8804 we are computing the size of a variable-size array. */
8806 if ((code == ASHIFTRT || code == LSHIFTRT)
8807 && count < HOST_BITS_PER_WIDE_INT
8808 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
8809 && (nonzero_bits (XEXP (varop, 1), result_mode)
8810 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
8812 varop = XEXP (varop, 0);
8815 else if ((code == ASHIFTRT || code == LSHIFTRT)
8816 && count < HOST_BITS_PER_WIDE_INT
8817 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8818 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
8820 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
8821 & nonzero_bits (XEXP (varop, 1),
8824 varop = XEXP (varop, 1);
8828 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
8830 && GET_CODE (XEXP (varop, 1)) == CONST_INT
8831 && (new = simplify_binary_operation (ASHIFT, result_mode,
8833 GEN_INT (count))) != 0
8834 && GET_CODE(new) == CONST_INT
8835 && merge_outer_ops (&outer_op, &outer_const, PLUS,
8836 INTVAL (new), result_mode, &complement_p))
8838 varop = XEXP (varop, 0);
8844 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
8845 with C the size of VAROP - 1 and the shift is logical if
8846 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8847 we have a (gt X 0) operation. If the shift is arithmetic with
8848 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
8849 we have a (neg (gt X 0)) operation. */
8851 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8852 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
8853 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
8854 && (code == LSHIFTRT || code == ASHIFTRT)
8855 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
8856 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
8857 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8860 varop = gen_rtx_combine (GT, GET_MODE (varop), XEXP (varop, 1),
8863 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8864 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
8871 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
8872 if the truncate does not affect the value. */
8873 if (code == LSHIFTRT
8874 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
8875 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
8876 && (INTVAL (XEXP (XEXP (varop, 0), 1))
8877 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
8878 - GET_MODE_BITSIZE (GET_MODE (varop)))))
8880 rtx varop_inner = XEXP (varop, 0);
8882 varop_inner = gen_rtx_combine (LSHIFTRT,
8883 GET_MODE (varop_inner),
8884 XEXP (varop_inner, 0),
8885 GEN_INT (count + INTVAL (XEXP (varop_inner, 1))));
8886 varop = gen_rtx_combine (TRUNCATE, GET_MODE (varop),
8900 /* We need to determine what mode to do the shift in. If the shift is
8901 a right shift or ROTATE, we must always do it in the mode it was
8902 originally done in. Otherwise, we can do it in MODE, the widest mode
8903 encountered. The code we care about is that of the shift that will
8904 actually be done, not the shift that was originally requested. */
8906 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8907 ? result_mode : mode);
8909 /* We have now finished analyzing the shift. The result should be
8910 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
8911 OUTER_OP is non-NIL, it is an operation that needs to be applied
8912 to the result of the shift. OUTER_CONST is the relevant constant,
8913 but we must turn off all bits turned off in the shift.
8915 If we were passed a value for X, see if we can use any pieces of
8916 it. If not, make new rtx. */
8918 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
8919 && GET_CODE (XEXP (x, 1)) == CONST_INT
8920 && INTVAL (XEXP (x, 1)) == count)
8921 const_rtx = XEXP (x, 1);
8923 const_rtx = GEN_INT (count);
8925 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
8926 && GET_MODE (XEXP (x, 0)) == shift_mode
8927 && SUBREG_REG (XEXP (x, 0)) == varop)
8928 varop = XEXP (x, 0);
8929 else if (GET_MODE (varop) != shift_mode)
8930 varop = gen_lowpart_for_combine (shift_mode, varop);
8932 /* If we can't make the SUBREG, try to return what we were given. */
8933 if (GET_CODE (varop) == CLOBBER)
8934 return x ? x : varop;
8936 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
8941 if (x == 0 || GET_CODE (x) != code || GET_MODE (x) != shift_mode)
8942 x = gen_rtx_combine (code, shift_mode, varop, const_rtx);
8944 SUBST (XEXP (x, 0), varop);
8945 SUBST (XEXP (x, 1), const_rtx);
8948 /* If we have an outer operation and we just made a shift, it is
8949 possible that we could have simplified the shift were it not
8950 for the outer operation. So try to do the simplification
8953 if (outer_op != NIL && GET_CODE (x) == code
8954 && GET_CODE (XEXP (x, 1)) == CONST_INT)
8955 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
8956 INTVAL (XEXP (x, 1)));
8958 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
8959 turn off all the bits that the shift would have turned off. */
8960 if (orig_code == LSHIFTRT && result_mode != shift_mode)
8961 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
8962 GET_MODE_MASK (result_mode) >> orig_count);
8964 /* Do the remainder of the processing in RESULT_MODE. */
8965 x = gen_lowpart_for_combine (result_mode, x);
8967 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
8970 x = gen_unary (NOT, result_mode, result_mode, x);
8972 if (outer_op != NIL)
8974 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
8976 int width = GET_MODE_BITSIZE (result_mode);
8978 outer_const &= GET_MODE_MASK (result_mode);
8980 /* If this would be an entire word for the target, but is not for
8981 the host, then sign-extend on the host so that the number will
8982 look the same way on the host that it would on the target.
8984 For example, when building a 64 bit alpha hosted 32 bit sparc
8985 targeted compiler, then we want the 32 bit unsigned value -1 to be
8986 represented as a 64 bit value -1, and not as 0x00000000ffffffff.
8987 The later confuses the sparc backend. */
8989 if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT && BITS_PER_WORD == width
8990 && (outer_const & ((HOST_WIDE_INT) 1 << (width - 1))))
8991 outer_const |= ((HOST_WIDE_INT) (-1) << width);
8994 if (outer_op == AND)
8995 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
8996 else if (outer_op == SET)
8997 /* This means that we have determined that the result is
8998 equivalent to a constant. This should be rare. */
8999 x = GEN_INT (outer_const);
9000 else if (GET_RTX_CLASS (outer_op) == '1')
9001 x = gen_unary (outer_op, result_mode, result_mode, x);
9003 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
9009 /* Like recog, but we receive the address of a pointer to a new pattern.
9010 We try to match the rtx that the pointer points to.
9011 If that fails, we may try to modify or replace the pattern,
9012 storing the replacement into the same pointer object.
9014 Modifications include deletion or addition of CLOBBERs.
9016 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9017 the CLOBBERs are placed.
9019 PADDED_SCRATCHES is set to the number of (clobber (scratch)) patterns
9022 The value is the final insn code from the pattern ultimately matched,
9026 recog_for_combine (pnewpat, insn, pnotes, padded_scratches)
9030 int *padded_scratches;
9032 register rtx pat = *pnewpat;
9033 int insn_code_number;
9034 int num_clobbers_to_add = 0;
9038 *padded_scratches = 0;
9040 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9041 we use to indicate that something didn't match. If we find such a
9042 thing, force rejection. */
9043 if (GET_CODE (pat) == PARALLEL)
9044 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9045 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9046 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9049 /* Is the result of combination a valid instruction? */
9050 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9052 /* If it isn't, there is the possibility that we previously had an insn
9053 that clobbered some register as a side effect, but the combined
9054 insn doesn't need to do that. So try once more without the clobbers
9055 unless this represents an ASM insn. */
9057 if (insn_code_number < 0 && ! check_asm_operands (pat)
9058 && GET_CODE (pat) == PARALLEL)
9062 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9063 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9066 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9070 SUBST_INT (XVECLEN (pat, 0), pos);
9073 pat = XVECEXP (pat, 0, 0);
9075 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9078 /* If we had any clobbers to add, make a new pattern than contains
9079 them. Then check to make sure that all of them are dead. */
9080 if (num_clobbers_to_add)
9082 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9083 gen_rtvec (GET_CODE (pat) == PARALLEL
9084 ? XVECLEN (pat, 0) + num_clobbers_to_add
9085 : num_clobbers_to_add + 1));
9087 if (GET_CODE (pat) == PARALLEL)
9088 for (i = 0; i < XVECLEN (pat, 0); i++)
9089 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9091 XVECEXP (newpat, 0, 0) = pat;
9093 add_clobbers (newpat, insn_code_number);
9095 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9096 i < XVECLEN (newpat, 0); i++)
9098 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
9099 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9101 else if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == SCRATCH)
9102 (*padded_scratches)++;
9103 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9104 XEXP (XVECEXP (newpat, 0, i), 0), notes);
9112 return insn_code_number;
9115 /* Like gen_lowpart but for use by combine. In combine it is not possible
9116 to create any new pseudoregs. However, it is safe to create
9117 invalid memory addresses, because combine will try to recognize
9118 them and all they will do is make the combine attempt fail.
9120 If for some reason this cannot do its job, an rtx
9121 (clobber (const_int 0)) is returned.
9122 An insn containing that will not be recognized. */
9127 gen_lowpart_for_combine (mode, x)
9128 enum machine_mode mode;
9133 if (GET_MODE (x) == mode)
9136 /* We can only support MODE being wider than a word if X is a
9137 constant integer or has a mode the same size. */
9139 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
9140 && ! ((GET_MODE (x) == VOIDmode
9141 && (GET_CODE (x) == CONST_INT
9142 || GET_CODE (x) == CONST_DOUBLE))
9143 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
9144 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9146 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9147 won't know what to do. So we will strip off the SUBREG here and
9148 process normally. */
9149 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
9152 if (GET_MODE (x) == mode)
9156 result = gen_lowpart_common (mode, x);
9158 && GET_CODE (result) == SUBREG
9159 && GET_CODE (SUBREG_REG (result)) == REG
9160 && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER
9161 && (GET_MODE_SIZE (GET_MODE (result))
9162 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (result)))))
9163 REG_CHANGES_SIZE (REGNO (SUBREG_REG (result))) = 1;
9168 if (GET_CODE (x) == MEM)
9170 register int offset = 0;
9173 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9175 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9176 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9178 /* If we want to refer to something bigger than the original memref,
9179 generate a perverse subreg instead. That will force a reload
9180 of the original memref X. */
9181 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
9182 return gen_rtx_SUBREG (mode, x, 0);
9184 if (WORDS_BIG_ENDIAN)
9185 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
9186 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
9187 if (BYTES_BIG_ENDIAN)
9189 /* Adjust the address so that the address-after-the-data is
9191 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
9192 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
9194 new = gen_rtx_MEM (mode, plus_constant (XEXP (x, 0), offset));
9195 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (x);
9196 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (x);
9197 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (x);
9201 /* If X is a comparison operator, rewrite it in a new mode. This
9202 probably won't match, but may allow further simplifications. */
9203 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
9204 return gen_rtx_combine (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
9206 /* If we couldn't simplify X any other way, just enclose it in a
9207 SUBREG. Normally, this SUBREG won't match, but some patterns may
9208 include an explicit SUBREG or we may simplify it further in combine. */
9213 if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
9214 word = ((GET_MODE_SIZE (GET_MODE (x))
9215 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
9217 return gen_rtx_SUBREG (mode, x, word);
9221 /* Make an rtx expression. This is a subset of gen_rtx and only supports
9222 expressions of 1, 2, or 3 operands, each of which are rtx expressions.
9224 If the identical expression was previously in the insn (in the undobuf),
9225 it will be returned. Only if it is not found will a new expression
9230 gen_rtx_combine VPROTO((enum rtx_code code, enum machine_mode mode, ...))
9234 enum machine_mode mode;
9247 code = va_arg (p, enum rtx_code);
9248 mode = va_arg (p, enum machine_mode);
9251 n_args = GET_RTX_LENGTH (code);
9252 fmt = GET_RTX_FORMAT (code);
9254 if (n_args == 0 || n_args > 3)
9257 /* Get each arg and verify that it is supposed to be an expression. */
9258 for (j = 0; j < n_args; j++)
9263 args[j] = va_arg (p, rtx);
9266 /* See if this is in undobuf. Be sure we don't use objects that came
9267 from another insn; this could produce circular rtl structures. */
9269 for (undo = undobuf.undos; undo != undobuf.previous_undos; undo = undo->next)
9271 && GET_CODE (undo->old_contents.r) == code
9272 && GET_MODE (undo->old_contents.r) == mode)
9274 for (j = 0; j < n_args; j++)
9275 if (XEXP (undo->old_contents.r, j) != args[j])
9279 return undo->old_contents.r;
9282 /* Otherwise make a new rtx. We know we have 1, 2, or 3 args.
9283 Use rtx_alloc instead of gen_rtx because it's faster on RISC. */
9284 rt = rtx_alloc (code);
9285 PUT_MODE (rt, mode);
9286 XEXP (rt, 0) = args[0];
9289 XEXP (rt, 1) = args[1];
9291 XEXP (rt, 2) = args[2];
9296 /* These routines make binary and unary operations by first seeing if they
9297 fold; if not, a new expression is allocated. */
9300 gen_binary (code, mode, op0, op1)
9302 enum machine_mode mode;
9308 if (GET_RTX_CLASS (code) == 'c'
9309 && (GET_CODE (op0) == CONST_INT
9310 || (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)))
9311 tem = op0, op0 = op1, op1 = tem;
9313 if (GET_RTX_CLASS (code) == '<')
9315 enum machine_mode op_mode = GET_MODE (op0);
9317 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
9318 just (REL_OP X Y). */
9319 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
9321 op1 = XEXP (op0, 1);
9322 op0 = XEXP (op0, 0);
9323 op_mode = GET_MODE (op0);
9326 if (op_mode == VOIDmode)
9327 op_mode = GET_MODE (op1);
9328 result = simplify_relational_operation (code, op_mode, op0, op1);
9331 result = simplify_binary_operation (code, mode, op0, op1);
9336 /* Put complex operands first and constants second. */
9337 if (GET_RTX_CLASS (code) == 'c'
9338 && ((CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
9339 || (GET_RTX_CLASS (GET_CODE (op0)) == 'o'
9340 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')
9341 || (GET_CODE (op0) == SUBREG
9342 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0))) == 'o'
9343 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')))
9344 return gen_rtx_combine (code, mode, op1, op0);
9346 /* If we are turning off bits already known off in OP0, we need not do
9348 else if (code == AND && GET_CODE (op1) == CONST_INT
9349 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9350 && (nonzero_bits (op0, mode) & ~ INTVAL (op1)) == 0)
9353 return gen_rtx_combine (code, mode, op0, op1);
9357 gen_unary (code, mode, op0_mode, op0)
9359 enum machine_mode mode, op0_mode;
9362 rtx result = simplify_unary_operation (code, mode, op0, op0_mode);
9367 return gen_rtx_combine (code, mode, op0);
9370 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9371 comparison code that will be tested.
9373 The result is a possibly different comparison code to use. *POP0 and
9374 *POP1 may be updated.
9376 It is possible that we might detect that a comparison is either always
9377 true or always false. However, we do not perform general constant
9378 folding in combine, so this knowledge isn't useful. Such tautologies
9379 should have been detected earlier. Hence we ignore all such cases. */
9381 static enum rtx_code
9382 simplify_comparison (code, pop0, pop1)
9391 enum machine_mode mode, tmode;
9393 /* Try a few ways of applying the same transformation to both operands. */
9396 #ifndef WORD_REGISTER_OPERATIONS
9397 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9398 so check specially. */
9399 if (code != GTU && code != GEU && code != LTU && code != LEU
9400 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9401 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9402 && GET_CODE (XEXP (op1, 0)) == ASHIFT
9403 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9404 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9405 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9406 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9407 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9408 && GET_CODE (XEXP (op1, 1)) == CONST_INT
9409 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9410 && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT
9411 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (op1, 1))
9412 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op0, 0), 1))
9413 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op1, 0), 1))
9414 && (INTVAL (XEXP (op0, 1))
9415 == (GET_MODE_BITSIZE (GET_MODE (op0))
9417 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9419 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9420 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9424 /* If both operands are the same constant shift, see if we can ignore the
9425 shift. We can if the shift is a rotate or if the bits shifted out of
9426 this shift are known to be zero for both inputs and if the type of
9427 comparison is compatible with the shift. */
9428 if (GET_CODE (op0) == GET_CODE (op1)
9429 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9430 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
9431 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
9432 && (code != GT && code != LT && code != GE && code != LE))
9433 || (GET_CODE (op0) == ASHIFTRT
9434 && (code != GTU && code != LTU
9435 && code != GEU && code != GEU)))
9436 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9437 && INTVAL (XEXP (op0, 1)) >= 0
9438 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9439 && XEXP (op0, 1) == XEXP (op1, 1))
9441 enum machine_mode mode = GET_MODE (op0);
9442 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9443 int shift_count = INTVAL (XEXP (op0, 1));
9445 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
9446 mask &= (mask >> shift_count) << shift_count;
9447 else if (GET_CODE (op0) == ASHIFT)
9448 mask = (mask & (mask << shift_count)) >> shift_count;
9450 if ((nonzero_bits (XEXP (op0, 0), mode) & ~ mask) == 0
9451 && (nonzero_bits (XEXP (op1, 0), mode) & ~ mask) == 0)
9452 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
9457 /* If both operands are AND's of a paradoxical SUBREG by constant, the
9458 SUBREGs are of the same mode, and, in both cases, the AND would
9459 be redundant if the comparison was done in the narrower mode,
9460 do the comparison in the narrower mode (e.g., we are AND'ing with 1
9461 and the operand's possibly nonzero bits are 0xffffff01; in that case
9462 if we only care about QImode, we don't need the AND). This case
9463 occurs if the output mode of an scc insn is not SImode and
9464 STORE_FLAG_VALUE == 1 (e.g., the 386).
9466 Similarly, check for a case where the AND's are ZERO_EXTEND
9467 operations from some narrower mode even though a SUBREG is not
9470 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
9471 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9472 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
9474 rtx inner_op0 = XEXP (op0, 0);
9475 rtx inner_op1 = XEXP (op1, 0);
9476 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
9477 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
9480 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
9481 && (GET_MODE_SIZE (GET_MODE (inner_op0))
9482 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
9483 && (GET_MODE (SUBREG_REG (inner_op0))
9484 == GET_MODE (SUBREG_REG (inner_op1)))
9485 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
9486 <= HOST_BITS_PER_WIDE_INT)
9487 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
9488 GET_MODE (SUBREG_REG (inner_op0)))))
9489 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
9490 GET_MODE (SUBREG_REG (inner_op1))))))
9492 op0 = SUBREG_REG (inner_op0);
9493 op1 = SUBREG_REG (inner_op1);
9495 /* The resulting comparison is always unsigned since we masked
9496 off the original sign bit. */
9497 code = unsigned_condition (code);
9503 for (tmode = GET_CLASS_NARROWEST_MODE
9504 (GET_MODE_CLASS (GET_MODE (op0)));
9505 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
9506 if (c0 == GET_MODE_MASK (tmode))
9508 op0 = gen_lowpart_for_combine (tmode, inner_op0);
9509 op1 = gen_lowpart_for_combine (tmode, inner_op1);
9510 code = unsigned_condition (code);
9519 /* If both operands are NOT, we can strip off the outer operation
9520 and adjust the comparison code for swapped operands; similarly for
9521 NEG, except that this must be an equality comparison. */
9522 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
9523 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
9524 && (code == EQ || code == NE)))
9525 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
9531 /* If the first operand is a constant, swap the operands and adjust the
9532 comparison code appropriately, but don't do this if the second operand
9533 is already a constant integer. */
9534 if (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
9536 tem = op0, op0 = op1, op1 = tem;
9537 code = swap_condition (code);
9540 /* We now enter a loop during which we will try to simplify the comparison.
9541 For the most part, we only are concerned with comparisons with zero,
9542 but some things may really be comparisons with zero but not start
9543 out looking that way. */
9545 while (GET_CODE (op1) == CONST_INT)
9547 enum machine_mode mode = GET_MODE (op0);
9548 int mode_width = GET_MODE_BITSIZE (mode);
9549 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9550 int equality_comparison_p;
9551 int sign_bit_comparison_p;
9552 int unsigned_comparison_p;
9553 HOST_WIDE_INT const_op;
9555 /* We only want to handle integral modes. This catches VOIDmode,
9556 CCmode, and the floating-point modes. An exception is that we
9557 can handle VOIDmode if OP0 is a COMPARE or a comparison
9560 if (GET_MODE_CLASS (mode) != MODE_INT
9561 && ! (mode == VOIDmode
9562 && (GET_CODE (op0) == COMPARE
9563 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
9566 /* Get the constant we are comparing against and turn off all bits
9567 not on in our mode. */
9568 const_op = INTVAL (op1);
9569 if (mode_width <= HOST_BITS_PER_WIDE_INT)
9572 /* If we are comparing against a constant power of two and the value
9573 being compared can only have that single bit nonzero (e.g., it was
9574 `and'ed with that bit), we can replace this with a comparison
9577 && (code == EQ || code == NE || code == GE || code == GEU
9578 || code == LT || code == LTU)
9579 && mode_width <= HOST_BITS_PER_WIDE_INT
9580 && exact_log2 (const_op) >= 0
9581 && nonzero_bits (op0, mode) == const_op)
9583 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
9584 op1 = const0_rtx, const_op = 0;
9587 /* Similarly, if we are comparing a value known to be either -1 or
9588 0 with -1, change it to the opposite comparison against zero. */
9591 && (code == EQ || code == NE || code == GT || code == LE
9592 || code == GEU || code == LTU)
9593 && num_sign_bit_copies (op0, mode) == mode_width)
9595 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
9596 op1 = const0_rtx, const_op = 0;
9599 /* Do some canonicalizations based on the comparison code. We prefer
9600 comparisons against zero and then prefer equality comparisons.
9601 If we can reduce the size of a constant, we will do that too. */
9606 /* < C is equivalent to <= (C - 1) */
9610 op1 = GEN_INT (const_op);
9612 /* ... fall through to LE case below. */
9618 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
9622 op1 = GEN_INT (const_op);
9626 /* If we are doing a <= 0 comparison on a value known to have
9627 a zero sign bit, we can replace this with == 0. */
9628 else if (const_op == 0
9629 && mode_width <= HOST_BITS_PER_WIDE_INT
9630 && (nonzero_bits (op0, mode)
9631 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9636 /* >= C is equivalent to > (C - 1). */
9640 op1 = GEN_INT (const_op);
9642 /* ... fall through to GT below. */
9648 /* > C is equivalent to >= (C + 1); we do this for C < 0*/
9652 op1 = GEN_INT (const_op);
9656 /* If we are doing a > 0 comparison on a value known to have
9657 a zero sign bit, we can replace this with != 0. */
9658 else if (const_op == 0
9659 && mode_width <= HOST_BITS_PER_WIDE_INT
9660 && (nonzero_bits (op0, mode)
9661 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9666 /* < C is equivalent to <= (C - 1). */
9670 op1 = GEN_INT (const_op);
9672 /* ... fall through ... */
9675 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
9676 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9677 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9679 const_op = 0, op1 = const0_rtx;
9687 /* unsigned <= 0 is equivalent to == 0 */
9691 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
9692 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9693 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9695 const_op = 0, op1 = const0_rtx;
9701 /* >= C is equivalent to < (C - 1). */
9705 op1 = GEN_INT (const_op);
9707 /* ... fall through ... */
9710 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
9711 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9712 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9714 const_op = 0, op1 = const0_rtx;
9722 /* unsigned > 0 is equivalent to != 0 */
9726 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
9727 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9728 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9730 const_op = 0, op1 = const0_rtx;
9739 /* Compute some predicates to simplify code below. */
9741 equality_comparison_p = (code == EQ || code == NE);
9742 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
9743 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
9746 /* If this is a sign bit comparison and we can do arithmetic in
9747 MODE, say that we will only be needing the sign bit of OP0. */
9748 if (sign_bit_comparison_p
9749 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9750 op0 = force_to_mode (op0, mode,
9752 << (GET_MODE_BITSIZE (mode) - 1)),
9755 /* Now try cases based on the opcode of OP0. If none of the cases
9756 does a "continue", we exit this loop immediately after the
9759 switch (GET_CODE (op0))
9762 /* If we are extracting a single bit from a variable position in
9763 a constant that has only a single bit set and are comparing it
9764 with zero, we can convert this into an equality comparison
9765 between the position and the location of the single bit. */
9767 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
9768 && XEXP (op0, 1) == const1_rtx
9769 && equality_comparison_p && const_op == 0
9770 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
9772 if (BITS_BIG_ENDIAN)
9774 i = (GET_MODE_BITSIZE
9775 (insn_operand_mode[(int) CODE_FOR_extzv][1]) - 1 - i);
9777 i = BITS_PER_WORD - 1 - i;
9780 op0 = XEXP (op0, 2);
9784 /* Result is nonzero iff shift count is equal to I. */
9785 code = reverse_condition (code);
9789 /* ... fall through ... */
9792 tem = expand_compound_operation (op0);
9801 /* If testing for equality, we can take the NOT of the constant. */
9802 if (equality_comparison_p
9803 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
9805 op0 = XEXP (op0, 0);
9810 /* If just looking at the sign bit, reverse the sense of the
9812 if (sign_bit_comparison_p)
9814 op0 = XEXP (op0, 0);
9815 code = (code == GE ? LT : GE);
9821 /* If testing for equality, we can take the NEG of the constant. */
9822 if (equality_comparison_p
9823 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
9825 op0 = XEXP (op0, 0);
9830 /* The remaining cases only apply to comparisons with zero. */
9834 /* When X is ABS or is known positive,
9835 (neg X) is < 0 if and only if X != 0. */
9837 if (sign_bit_comparison_p
9838 && (GET_CODE (XEXP (op0, 0)) == ABS
9839 || (mode_width <= HOST_BITS_PER_WIDE_INT
9840 && (nonzero_bits (XEXP (op0, 0), mode)
9841 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
9843 op0 = XEXP (op0, 0);
9844 code = (code == LT ? NE : EQ);
9848 /* If we have NEG of something whose two high-order bits are the
9849 same, we know that "(-a) < 0" is equivalent to "a > 0". */
9850 if (num_sign_bit_copies (op0, mode) >= 2)
9852 op0 = XEXP (op0, 0);
9853 code = swap_condition (code);
9859 /* If we are testing equality and our count is a constant, we
9860 can perform the inverse operation on our RHS. */
9861 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
9862 && (tem = simplify_binary_operation (ROTATERT, mode,
9863 op1, XEXP (op0, 1))) != 0)
9865 op0 = XEXP (op0, 0);
9870 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
9871 a particular bit. Convert it to an AND of a constant of that
9872 bit. This will be converted into a ZERO_EXTRACT. */
9873 if (const_op == 0 && sign_bit_comparison_p
9874 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9875 && mode_width <= HOST_BITS_PER_WIDE_INT)
9877 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
9880 - INTVAL (XEXP (op0, 1)))));
9881 code = (code == LT ? NE : EQ);
9885 /* ... fall through ... */
9888 /* ABS is ignorable inside an equality comparison with zero. */
9889 if (const_op == 0 && equality_comparison_p)
9891 op0 = XEXP (op0, 0);
9898 /* Can simplify (compare (zero/sign_extend FOO) CONST)
9899 to (compare FOO CONST) if CONST fits in FOO's mode and we
9900 are either testing inequality or have an unsigned comparison
9901 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
9902 if (! unsigned_comparison_p
9903 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
9904 <= HOST_BITS_PER_WIDE_INT)
9905 && ((unsigned HOST_WIDE_INT) const_op
9906 < (((HOST_WIDE_INT) 1
9907 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
9909 op0 = XEXP (op0, 0);
9915 /* Check for the case where we are comparing A - C1 with C2,
9916 both constants are smaller than 1/2 the maximum positive
9917 value in MODE, and the comparison is equality or unsigned.
9918 In that case, if A is either zero-extended to MODE or has
9919 sufficient sign bits so that the high-order bit in MODE
9920 is a copy of the sign in the inner mode, we can prove that it is
9921 safe to do the operation in the wider mode. This simplifies
9922 many range checks. */
9924 if (mode_width <= HOST_BITS_PER_WIDE_INT
9925 && subreg_lowpart_p (op0)
9926 && GET_CODE (SUBREG_REG (op0)) == PLUS
9927 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
9928 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
9929 && (- INTVAL (XEXP (SUBREG_REG (op0), 1))
9930 < GET_MODE_MASK (mode) / 2)
9931 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
9932 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
9933 GET_MODE (SUBREG_REG (op0)))
9934 & ~ GET_MODE_MASK (mode))
9935 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
9936 GET_MODE (SUBREG_REG (op0)))
9937 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
9938 - GET_MODE_BITSIZE (mode)))))
9940 op0 = SUBREG_REG (op0);
9944 /* If the inner mode is narrower and we are extracting the low part,
9945 we can treat the SUBREG as if it were a ZERO_EXTEND. */
9946 if (subreg_lowpart_p (op0)
9947 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
9948 /* Fall through */ ;
9952 /* ... fall through ... */
9955 if ((unsigned_comparison_p || equality_comparison_p)
9956 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
9957 <= HOST_BITS_PER_WIDE_INT)
9958 && ((unsigned HOST_WIDE_INT) const_op
9959 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
9961 op0 = XEXP (op0, 0);
9967 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
9968 this for equality comparisons due to pathological cases involving
9970 if (equality_comparison_p
9971 && 0 != (tem = simplify_binary_operation (MINUS, mode,
9972 op1, XEXP (op0, 1))))
9974 op0 = XEXP (op0, 0);
9979 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
9980 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
9981 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
9983 op0 = XEXP (XEXP (op0, 0), 0);
9984 code = (code == LT ? EQ : NE);
9990 /* (eq (minus A B) C) -> (eq A (plus B C)) or
9991 (eq B (minus A C)), whichever simplifies. We can only do
9992 this for equality comparisons due to pathological cases involving
9994 if (equality_comparison_p
9995 && 0 != (tem = simplify_binary_operation (PLUS, mode,
9996 XEXP (op0, 1), op1)))
9998 op0 = XEXP (op0, 0);
10003 if (equality_comparison_p
10004 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10005 XEXP (op0, 0), op1)))
10007 op0 = XEXP (op0, 1);
10012 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10013 of bits in X minus 1, is one iff X > 0. */
10014 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10015 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10016 && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
10017 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10019 op0 = XEXP (op0, 1);
10020 code = (code == GE ? LE : GT);
10026 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10027 if C is zero or B is a constant. */
10028 if (equality_comparison_p
10029 && 0 != (tem = simplify_binary_operation (XOR, mode,
10030 XEXP (op0, 1), op1)))
10032 op0 = XEXP (op0, 0);
10039 case LT: case LTU: case LE: case LEU:
10040 case GT: case GTU: case GE: case GEU:
10041 /* We can't do anything if OP0 is a condition code value, rather
10042 than an actual data value. */
10045 || XEXP (op0, 0) == cc0_rtx
10047 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10050 /* Get the two operands being compared. */
10051 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10052 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10054 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10056 /* Check for the cases where we simply want the result of the
10057 earlier test or the opposite of that result. */
10059 || (code == EQ && reversible_comparison_p (op0))
10060 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10061 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10062 && (STORE_FLAG_VALUE
10063 & (((HOST_WIDE_INT) 1
10064 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10066 || (code == GE && reversible_comparison_p (op0)))))
10068 code = (code == LT || code == NE
10069 ? GET_CODE (op0) : reverse_condition (GET_CODE (op0)));
10070 op0 = tem, op1 = tem1;
10076 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
10078 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10079 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10080 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10082 op0 = XEXP (op0, 1);
10083 code = (code == GE ? GT : LE);
10089 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10090 will be converted to a ZERO_EXTRACT later. */
10091 if (const_op == 0 && equality_comparison_p
10092 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10093 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10095 op0 = simplify_and_const_int
10096 (op0, mode, gen_rtx_combine (LSHIFTRT, mode,
10098 XEXP (XEXP (op0, 0), 1)),
10099 (HOST_WIDE_INT) 1);
10103 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10104 zero and X is a comparison and C1 and C2 describe only bits set
10105 in STORE_FLAG_VALUE, we can compare with X. */
10106 if (const_op == 0 && equality_comparison_p
10107 && mode_width <= HOST_BITS_PER_WIDE_INT
10108 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10109 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10110 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10111 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10112 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10114 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10115 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10116 if ((~ STORE_FLAG_VALUE & mask) == 0
10117 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
10118 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10119 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
10121 op0 = XEXP (XEXP (op0, 0), 0);
10126 /* If we are doing an equality comparison of an AND of a bit equal
10127 to the sign bit, replace this with a LT or GE comparison of
10128 the underlying value. */
10129 if (equality_comparison_p
10131 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10132 && mode_width <= HOST_BITS_PER_WIDE_INT
10133 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10134 == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10136 op0 = XEXP (op0, 0);
10137 code = (code == EQ ? GE : LT);
10141 /* If this AND operation is really a ZERO_EXTEND from a narrower
10142 mode, the constant fits within that mode, and this is either an
10143 equality or unsigned comparison, try to do this comparison in
10144 the narrower mode. */
10145 if ((equality_comparison_p || unsigned_comparison_p)
10146 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10147 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10148 & GET_MODE_MASK (mode))
10150 && const_op >> i == 0
10151 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
10153 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
10157 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 fits
10158 in both M1 and M2 and the SUBREG is either paradoxical or
10159 represents the low part, permute the SUBREG and the AND and
10161 if (GET_CODE (XEXP (op0, 0)) == SUBREG
10163 >= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))
10164 #ifdef WORD_REGISTER_OPERATIONS
10165 || subreg_lowpart_p (XEXP (op0, 0))
10168 #ifndef WORD_REGISTER_OPERATIONS
10169 /* It is unsafe to commute the AND into the SUBREG if the SUBREG
10170 is paradoxical and WORD_REGISTER_OPERATIONS is not defined.
10171 As originally written the upper bits have a defined value
10172 due to the AND operation. However, if we commute the AND
10173 inside the SUBREG then they no longer have defined values
10174 and the meaning of the code has been changed. */
10175 && (GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)))
10176 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))
10178 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10179 && mode_width <= HOST_BITS_PER_WIDE_INT
10180 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10181 <= HOST_BITS_PER_WIDE_INT)
10182 && (INTVAL (XEXP (op0, 1)) & ~ mask) == 0
10183 && 0 == (~ GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10184 & INTVAL (XEXP (op0, 1)))
10185 && INTVAL (XEXP (op0, 1)) != mask
10186 && (INTVAL (XEXP (op0, 1))
10187 != GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10191 = gen_lowpart_for_combine
10193 gen_binary (AND, GET_MODE (SUBREG_REG (XEXP (op0, 0))),
10194 SUBREG_REG (XEXP (op0, 0)), XEXP (op0, 1)));
10201 /* If we have (compare (ashift FOO N) (const_int C)) and
10202 the high order N bits of FOO (N+1 if an inequality comparison)
10203 are known to be zero, we can do this by comparing FOO with C
10204 shifted right N bits so long as the low-order N bits of C are
10206 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10207 && INTVAL (XEXP (op0, 1)) >= 0
10208 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10209 < HOST_BITS_PER_WIDE_INT)
10211 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10212 && mode_width <= HOST_BITS_PER_WIDE_INT
10213 && (nonzero_bits (XEXP (op0, 0), mode)
10214 & ~ (mask >> (INTVAL (XEXP (op0, 1))
10215 + ! equality_comparison_p))) == 0)
10217 const_op >>= INTVAL (XEXP (op0, 1));
10218 op1 = GEN_INT (const_op);
10219 op0 = XEXP (op0, 0);
10223 /* If we are doing a sign bit comparison, it means we are testing
10224 a particular bit. Convert it to the appropriate AND. */
10225 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10226 && mode_width <= HOST_BITS_PER_WIDE_INT)
10228 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10231 - INTVAL (XEXP (op0, 1)))));
10232 code = (code == LT ? NE : EQ);
10236 /* If this an equality comparison with zero and we are shifting
10237 the low bit to the sign bit, we can convert this to an AND of the
10239 if (const_op == 0 && equality_comparison_p
10240 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10241 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10243 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10244 (HOST_WIDE_INT) 1);
10250 /* If this is an equality comparison with zero, we can do this
10251 as a logical shift, which might be much simpler. */
10252 if (equality_comparison_p && const_op == 0
10253 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10255 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10257 INTVAL (XEXP (op0, 1)));
10261 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10262 do the comparison in a narrower mode. */
10263 if (! unsigned_comparison_p
10264 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10265 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10266 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10267 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10268 MODE_INT, 1)) != BLKmode
10269 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
10270 || ((unsigned HOST_WIDE_INT) - const_op
10271 <= GET_MODE_MASK (tmode))))
10273 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
10277 /* ... fall through ... */
10279 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10280 the low order N bits of FOO are known to be zero, we can do this
10281 by comparing FOO with C shifted left N bits so long as no
10282 overflow occurs. */
10283 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10284 && INTVAL (XEXP (op0, 1)) >= 0
10285 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10286 && mode_width <= HOST_BITS_PER_WIDE_INT
10287 && (nonzero_bits (XEXP (op0, 0), mode)
10288 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10290 || (floor_log2 (const_op) + INTVAL (XEXP (op0, 1))
10293 const_op <<= INTVAL (XEXP (op0, 1));
10294 op1 = GEN_INT (const_op);
10295 op0 = XEXP (op0, 0);
10299 /* If we are using this shift to extract just the sign bit, we
10300 can replace this with an LT or GE comparison. */
10302 && (equality_comparison_p || sign_bit_comparison_p)
10303 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10304 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10306 op0 = XEXP (op0, 0);
10307 code = (code == NE || code == GT ? LT : GE);
10319 /* Now make any compound operations involved in this comparison. Then,
10320 check for an outmost SUBREG on OP0 that is not doing anything or is
10321 paradoxical. The latter case can only occur when it is known that the
10322 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
10323 We can never remove a SUBREG for a non-equality comparison because the
10324 sign bit is in a different place in the underlying object. */
10326 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10327 op1 = make_compound_operation (op1, SET);
10329 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10330 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10331 && (code == NE || code == EQ)
10332 && ((GET_MODE_SIZE (GET_MODE (op0))
10333 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))))
10335 op0 = SUBREG_REG (op0);
10336 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
10339 else if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10340 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10341 && (code == NE || code == EQ)
10342 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10343 <= HOST_BITS_PER_WIDE_INT)
10344 && (nonzero_bits (SUBREG_REG (op0), GET_MODE (SUBREG_REG (op0)))
10345 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0
10346 && (tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)),
10348 (nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
10349 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0))
10350 op0 = SUBREG_REG (op0), op1 = tem;
10352 /* We now do the opposite procedure: Some machines don't have compare
10353 insns in all modes. If OP0's mode is an integer mode smaller than a
10354 word and we can't do a compare in that mode, see if there is a larger
10355 mode for which we can do the compare. There are a number of cases in
10356 which we can use the wider mode. */
10358 mode = GET_MODE (op0);
10359 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10360 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
10361 && cmp_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
10362 for (tmode = GET_MODE_WIDER_MODE (mode);
10364 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
10365 tmode = GET_MODE_WIDER_MODE (tmode))
10366 if (cmp_optab->handlers[(int) tmode].insn_code != CODE_FOR_nothing)
10368 /* If the only nonzero bits in OP0 and OP1 are those in the
10369 narrower mode and this is an equality or unsigned comparison,
10370 we can use the wider mode. Similarly for sign-extended
10371 values, in which case it is true for all comparisons. */
10372 if (((code == EQ || code == NE
10373 || code == GEU || code == GTU || code == LEU || code == LTU)
10374 && (nonzero_bits (op0, tmode) & ~ GET_MODE_MASK (mode)) == 0
10375 && (nonzero_bits (op1, tmode) & ~ GET_MODE_MASK (mode)) == 0)
10376 || ((num_sign_bit_copies (op0, tmode)
10377 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))
10378 && (num_sign_bit_copies (op1, tmode)
10379 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))))
10381 op0 = gen_lowpart_for_combine (tmode, op0);
10382 op1 = gen_lowpart_for_combine (tmode, op1);
10386 /* If this is a test for negative, we can make an explicit
10387 test of the sign bit. */
10389 if (op1 == const0_rtx && (code == LT || code == GE)
10390 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10392 op0 = gen_binary (AND, tmode,
10393 gen_lowpart_for_combine (tmode, op0),
10394 GEN_INT ((HOST_WIDE_INT) 1
10395 << (GET_MODE_BITSIZE (mode) - 1)));
10396 code = (code == LT) ? NE : EQ;
10401 #ifdef CANONICALIZE_COMPARISON
10402 /* If this machine only supports a subset of valid comparisons, see if we
10403 can convert an unsupported one into a supported one. */
10404 CANONICALIZE_COMPARISON (code, op0, op1);
10413 /* Return 1 if we know that X, a comparison operation, is not operating
10414 on a floating-point value or is EQ or NE, meaning that we can safely
10418 reversible_comparison_p (x)
10421 if (TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
10423 || GET_CODE (x) == NE || GET_CODE (x) == EQ)
10426 switch (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))))
10429 case MODE_PARTIAL_INT:
10430 case MODE_COMPLEX_INT:
10434 /* If the mode of the condition codes tells us that this is safe,
10435 we need look no further. */
10436 if (REVERSIBLE_CC_MODE (GET_MODE (XEXP (x, 0))))
10439 /* Otherwise try and find where the condition codes were last set and
10441 x = get_last_value (XEXP (x, 0));
10442 return (x && GET_CODE (x) == COMPARE
10443 && ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0))));
10450 /* Utility function for following routine. Called when X is part of a value
10451 being stored into reg_last_set_value. Sets reg_last_set_table_tick
10452 for each register mentioned. Similar to mention_regs in cse.c */
10455 update_table_tick (x)
10458 register enum rtx_code code = GET_CODE (x);
10459 register char *fmt = GET_RTX_FORMAT (code);
10464 int regno = REGNO (x);
10465 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10466 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10468 for (i = regno; i < endregno; i++)
10469 reg_last_set_table_tick[i] = label_tick;
10474 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10475 /* Note that we can't have an "E" in values stored; see
10476 get_last_value_validate. */
10478 update_table_tick (XEXP (x, i));
10481 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
10482 are saying that the register is clobbered and we no longer know its
10483 value. If INSN is zero, don't update reg_last_set; this is only permitted
10484 with VALUE also zero and is used to invalidate the register. */
10487 record_value_for_reg (reg, insn, value)
10492 int regno = REGNO (reg);
10493 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10494 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
10497 /* If VALUE contains REG and we have a previous value for REG, substitute
10498 the previous value. */
10499 if (value && insn && reg_overlap_mentioned_p (reg, value))
10503 /* Set things up so get_last_value is allowed to see anything set up to
10505 subst_low_cuid = INSN_CUID (insn);
10506 tem = get_last_value (reg);
10509 value = replace_rtx (copy_rtx (value), reg, tem);
10512 /* For each register modified, show we don't know its value, that
10513 we don't know about its bitwise content, that its value has been
10514 updated, and that we don't know the location of the death of the
10516 for (i = regno; i < endregno; i ++)
10519 reg_last_set[i] = insn;
10520 reg_last_set_value[i] = 0;
10521 reg_last_set_mode[i] = 0;
10522 reg_last_set_nonzero_bits[i] = 0;
10523 reg_last_set_sign_bit_copies[i] = 0;
10524 reg_last_death[i] = 0;
10527 /* Mark registers that are being referenced in this value. */
10529 update_table_tick (value);
10531 /* Now update the status of each register being set.
10532 If someone is using this register in this block, set this register
10533 to invalid since we will get confused between the two lives in this
10534 basic block. This makes using this register always invalid. In cse, we
10535 scan the table to invalidate all entries using this register, but this
10536 is too much work for us. */
10538 for (i = regno; i < endregno; i++)
10540 reg_last_set_label[i] = label_tick;
10541 if (value && reg_last_set_table_tick[i] == label_tick)
10542 reg_last_set_invalid[i] = 1;
10544 reg_last_set_invalid[i] = 0;
10547 /* The value being assigned might refer to X (like in "x++;"). In that
10548 case, we must replace it with (clobber (const_int 0)) to prevent
10550 if (value && ! get_last_value_validate (&value, insn,
10551 reg_last_set_label[regno], 0))
10553 value = copy_rtx (value);
10554 if (! get_last_value_validate (&value, insn,
10555 reg_last_set_label[regno], 1))
10559 /* For the main register being modified, update the value, the mode, the
10560 nonzero bits, and the number of sign bit copies. */
10562 reg_last_set_value[regno] = value;
10566 subst_low_cuid = INSN_CUID (insn);
10567 reg_last_set_mode[regno] = GET_MODE (reg);
10568 reg_last_set_nonzero_bits[regno] = nonzero_bits (value, GET_MODE (reg));
10569 reg_last_set_sign_bit_copies[regno]
10570 = num_sign_bit_copies (value, GET_MODE (reg));
10574 /* Used for communication between the following two routines. */
10575 static rtx record_dead_insn;
10577 /* Called via note_stores from record_dead_and_set_regs to handle one
10578 SET or CLOBBER in an insn. */
10581 record_dead_and_set_regs_1 (dest, setter)
10584 if (GET_CODE (dest) == SUBREG)
10585 dest = SUBREG_REG (dest);
10587 if (GET_CODE (dest) == REG)
10589 /* If we are setting the whole register, we know its value. Otherwise
10590 show that we don't know the value. We can handle SUBREG in
10592 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
10593 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
10594 else if (GET_CODE (setter) == SET
10595 && GET_CODE (SET_DEST (setter)) == SUBREG
10596 && SUBREG_REG (SET_DEST (setter)) == dest
10597 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
10598 && subreg_lowpart_p (SET_DEST (setter)))
10599 record_value_for_reg (dest, record_dead_insn,
10600 gen_lowpart_for_combine (GET_MODE (dest),
10601 SET_SRC (setter)));
10603 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
10605 else if (GET_CODE (dest) == MEM
10606 /* Ignore pushes, they clobber nothing. */
10607 && ! push_operand (dest, GET_MODE (dest)))
10608 mem_last_set = INSN_CUID (record_dead_insn);
10611 /* Update the records of when each REG was most recently set or killed
10612 for the things done by INSN. This is the last thing done in processing
10613 INSN in the combiner loop.
10615 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
10616 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
10617 and also the similar information mem_last_set (which insn most recently
10618 modified memory) and last_call_cuid (which insn was the most recent
10619 subroutine call). */
10622 record_dead_and_set_regs (insn)
10628 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
10630 if (REG_NOTE_KIND (link) == REG_DEAD
10631 && GET_CODE (XEXP (link, 0)) == REG)
10633 int regno = REGNO (XEXP (link, 0));
10635 = regno + (regno < FIRST_PSEUDO_REGISTER
10636 ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0)))
10639 for (i = regno; i < endregno; i++)
10640 reg_last_death[i] = insn;
10642 else if (REG_NOTE_KIND (link) == REG_INC)
10643 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
10646 if (GET_CODE (insn) == CALL_INSN)
10648 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
10649 if (call_used_regs[i])
10651 reg_last_set_value[i] = 0;
10652 reg_last_set_mode[i] = 0;
10653 reg_last_set_nonzero_bits[i] = 0;
10654 reg_last_set_sign_bit_copies[i] = 0;
10655 reg_last_death[i] = 0;
10658 last_call_cuid = mem_last_set = INSN_CUID (insn);
10661 record_dead_insn = insn;
10662 note_stores (PATTERN (insn), record_dead_and_set_regs_1);
10665 /* Utility routine for the following function. Verify that all the registers
10666 mentioned in *LOC are valid when *LOC was part of a value set when
10667 label_tick == TICK. Return 0 if some are not.
10669 If REPLACE is non-zero, replace the invalid reference with
10670 (clobber (const_int 0)) and return 1. This replacement is useful because
10671 we often can get useful information about the form of a value (e.g., if
10672 it was produced by a shift that always produces -1 or 0) even though
10673 we don't know exactly what registers it was produced from. */
10676 get_last_value_validate (loc, insn, tick, replace)
10683 char *fmt = GET_RTX_FORMAT (GET_CODE (x));
10684 int len = GET_RTX_LENGTH (GET_CODE (x));
10687 if (GET_CODE (x) == REG)
10689 int regno = REGNO (x);
10690 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10691 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10694 for (j = regno; j < endregno; j++)
10695 if (reg_last_set_invalid[j]
10696 /* If this is a pseudo-register that was only set once, it is
10698 || (! (regno >= FIRST_PSEUDO_REGISTER && REG_N_SETS (regno) == 1)
10699 && reg_last_set_label[j] > tick))
10702 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
10708 /* If this is a memory reference, make sure that there were
10709 no stores after it that might have clobbered the value. We don't
10710 have alias info, so we assume any store invalidates it. */
10711 else if (GET_CODE (x) == MEM && ! RTX_UNCHANGING_P (x)
10712 && INSN_CUID (insn) <= mem_last_set)
10715 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
10719 for (i = 0; i < len; i++)
10721 && get_last_value_validate (&XEXP (x, i), insn, tick, replace) == 0)
10722 /* Don't bother with these. They shouldn't occur anyway. */
10726 /* If we haven't found a reason for it to be invalid, it is valid. */
10730 /* Get the last value assigned to X, if known. Some registers
10731 in the value may be replaced with (clobber (const_int 0)) if their value
10732 is known longer known reliably. */
10741 /* If this is a non-paradoxical SUBREG, get the value of its operand and
10742 then convert it to the desired mode. If this is a paradoxical SUBREG,
10743 we cannot predict what values the "extra" bits might have. */
10744 if (GET_CODE (x) == SUBREG
10745 && subreg_lowpart_p (x)
10746 && (GET_MODE_SIZE (GET_MODE (x))
10747 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
10748 && (value = get_last_value (SUBREG_REG (x))) != 0)
10749 return gen_lowpart_for_combine (GET_MODE (x), value);
10751 if (GET_CODE (x) != REG)
10755 value = reg_last_set_value[regno];
10757 /* If we don't have a value or if it isn't for this basic block,
10761 || (REG_N_SETS (regno) != 1
10762 && reg_last_set_label[regno] != label_tick))
10765 /* If the value was set in a later insn than the ones we are processing,
10766 we can't use it even if the register was only set once, but make a quick
10767 check to see if the previous insn set it to something. This is commonly
10768 the case when the same pseudo is used by repeated insns.
10770 This does not work if there exists an instruction which is temporarily
10771 not on the insn chain. */
10773 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
10777 /* We can not do anything useful in this case, because there is
10778 an instruction which is not on the insn chain. */
10779 if (subst_prev_insn)
10782 /* Skip over USE insns. They are not useful here, and they may have
10783 been made by combine, in which case they do not have a INSN_CUID
10784 value. We can't use prev_real_insn, because that would incorrectly
10785 take us backwards across labels. Skip over BARRIERs also, since
10786 they could have been made by combine. If we see one, we must be
10787 optimizing dead code, so it doesn't matter what we do. */
10788 for (insn = prev_nonnote_insn (subst_insn);
10789 insn && ((GET_CODE (insn) == INSN
10790 && GET_CODE (PATTERN (insn)) == USE)
10791 || GET_CODE (insn) == BARRIER
10792 || INSN_CUID (insn) >= subst_low_cuid);
10793 insn = prev_nonnote_insn (insn))
10797 && (set = single_set (insn)) != 0
10798 && rtx_equal_p (SET_DEST (set), x))
10800 value = SET_SRC (set);
10802 /* Make sure that VALUE doesn't reference X. Replace any
10803 explicit references with a CLOBBER. If there are any remaining
10804 references (rare), don't use the value. */
10806 if (reg_mentioned_p (x, value))
10807 value = replace_rtx (copy_rtx (value), x,
10808 gen_rtx_CLOBBER (GET_MODE (x), const0_rtx));
10810 if (reg_overlap_mentioned_p (x, value))
10817 /* If the value has all its registers valid, return it. */
10818 if (get_last_value_validate (&value, reg_last_set[regno],
10819 reg_last_set_label[regno], 0))
10822 /* Otherwise, make a copy and replace any invalid register with
10823 (clobber (const_int 0)). If that fails for some reason, return 0. */
10825 value = copy_rtx (value);
10826 if (get_last_value_validate (&value, reg_last_set[regno],
10827 reg_last_set_label[regno], 1))
10833 /* Return nonzero if expression X refers to a REG or to memory
10834 that is set in an instruction more recent than FROM_CUID. */
10837 use_crosses_set_p (x, from_cuid)
10841 register char *fmt;
10843 register enum rtx_code code = GET_CODE (x);
10847 register int regno = REGNO (x);
10848 int endreg = regno + (regno < FIRST_PSEUDO_REGISTER
10849 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10851 #ifdef PUSH_ROUNDING
10852 /* Don't allow uses of the stack pointer to be moved,
10853 because we don't know whether the move crosses a push insn. */
10854 if (regno == STACK_POINTER_REGNUM)
10857 for (;regno < endreg; regno++)
10858 if (reg_last_set[regno]
10859 && INSN_CUID (reg_last_set[regno]) > from_cuid)
10864 if (code == MEM && mem_last_set > from_cuid)
10867 fmt = GET_RTX_FORMAT (code);
10869 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10874 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
10875 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
10878 else if (fmt[i] == 'e'
10879 && use_crosses_set_p (XEXP (x, i), from_cuid))
10885 /* Define three variables used for communication between the following
10888 static int reg_dead_regno, reg_dead_endregno;
10889 static int reg_dead_flag;
10891 /* Function called via note_stores from reg_dead_at_p.
10893 If DEST is within [reg_dead_regno, reg_dead_endregno), set
10894 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
10897 reg_dead_at_p_1 (dest, x)
10901 int regno, endregno;
10903 if (GET_CODE (dest) != REG)
10906 regno = REGNO (dest);
10907 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10908 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
10910 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
10911 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
10914 /* Return non-zero if REG is known to be dead at INSN.
10916 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
10917 referencing REG, it is dead. If we hit a SET referencing REG, it is
10918 live. Otherwise, see if it is live or dead at the start of the basic
10919 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
10920 must be assumed to be always live. */
10923 reg_dead_at_p (reg, insn)
10929 /* Set variables for reg_dead_at_p_1. */
10930 reg_dead_regno = REGNO (reg);
10931 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
10932 ? HARD_REGNO_NREGS (reg_dead_regno,
10938 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
10939 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
10941 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
10942 if (TEST_HARD_REG_BIT (newpat_used_regs, i))
10946 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
10947 beginning of function. */
10948 for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER;
10949 insn = prev_nonnote_insn (insn))
10951 note_stores (PATTERN (insn), reg_dead_at_p_1);
10953 return reg_dead_flag == 1 ? 1 : 0;
10955 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
10959 /* Get the basic block number that we were in. */
10964 for (block = 0; block < n_basic_blocks; block++)
10965 if (insn == basic_block_head[block])
10968 if (block == n_basic_blocks)
10972 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
10973 if (REGNO_REG_SET_P (basic_block_live_at_start[block], i))
10979 /* Note hard registers in X that are used. This code is similar to
10980 that in flow.c, but much simpler since we don't care about pseudos. */
10983 mark_used_regs_combine (x)
10986 register RTX_CODE code = GET_CODE (x);
10987 register int regno;
10999 case ADDR_DIFF_VEC:
11002 /* CC0 must die in the insn after it is set, so we don't need to take
11003 special note of it here. */
11009 /* If we are clobbering a MEM, mark any hard registers inside the
11010 address as used. */
11011 if (GET_CODE (XEXP (x, 0)) == MEM)
11012 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11017 /* A hard reg in a wide mode may really be multiple registers.
11018 If so, mark all of them just like the first. */
11019 if (regno < FIRST_PSEUDO_REGISTER)
11021 /* None of this applies to the stack, frame or arg pointers */
11022 if (regno == STACK_POINTER_REGNUM
11023 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11024 || regno == HARD_FRAME_POINTER_REGNUM
11026 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11027 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11029 || regno == FRAME_POINTER_REGNUM)
11032 i = HARD_REGNO_NREGS (regno, GET_MODE (x));
11034 SET_HARD_REG_BIT (newpat_used_regs, regno + i);
11040 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11042 register rtx testreg = SET_DEST (x);
11044 while (GET_CODE (testreg) == SUBREG
11045 || GET_CODE (testreg) == ZERO_EXTRACT
11046 || GET_CODE (testreg) == SIGN_EXTRACT
11047 || GET_CODE (testreg) == STRICT_LOW_PART)
11048 testreg = XEXP (testreg, 0);
11050 if (GET_CODE (testreg) == MEM)
11051 mark_used_regs_combine (XEXP (testreg, 0));
11053 mark_used_regs_combine (SET_SRC (x));
11061 /* Recursively scan the operands of this expression. */
11064 register char *fmt = GET_RTX_FORMAT (code);
11066 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11069 mark_used_regs_combine (XEXP (x, i));
11070 else if (fmt[i] == 'E')
11074 for (j = 0; j < XVECLEN (x, i); j++)
11075 mark_used_regs_combine (XVECEXP (x, i, j));
11082 /* Remove register number REGNO from the dead registers list of INSN.
11084 Return the note used to record the death, if there was one. */
11087 remove_death (regno, insn)
11091 register rtx note = find_regno_note (insn, REG_DEAD, regno);
11095 REG_N_DEATHS (regno)--;
11096 remove_note (insn, note);
11102 /* For each register (hardware or pseudo) used within expression X, if its
11103 death is in an instruction with cuid between FROM_CUID (inclusive) and
11104 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11105 list headed by PNOTES.
11107 That said, don't move registers killed by maybe_kill_insn.
11109 This is done when X is being merged by combination into TO_INSN. These
11110 notes will then be distributed as needed. */
11113 move_deaths (x, maybe_kill_insn, from_cuid, to_insn, pnotes)
11115 rtx maybe_kill_insn;
11120 register char *fmt;
11121 register int len, i;
11122 register enum rtx_code code = GET_CODE (x);
11126 register int regno = REGNO (x);
11127 register rtx where_dead = reg_last_death[regno];
11128 register rtx before_dead, after_dead;
11130 /* Don't move the register if it gets killed in between from and to */
11131 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11132 && !reg_referenced_p (x, maybe_kill_insn))
11135 /* WHERE_DEAD could be a USE insn made by combine, so first we
11136 make sure that we have insns with valid INSN_CUID values. */
11137 before_dead = where_dead;
11138 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11139 before_dead = PREV_INSN (before_dead);
11140 after_dead = where_dead;
11141 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11142 after_dead = NEXT_INSN (after_dead);
11144 if (before_dead && after_dead
11145 && INSN_CUID (before_dead) >= from_cuid
11146 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
11147 || (where_dead != after_dead
11148 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
11150 rtx note = remove_death (regno, where_dead);
11152 /* It is possible for the call above to return 0. This can occur
11153 when reg_last_death points to I2 or I1 that we combined with.
11154 In that case make a new note.
11156 We must also check for the case where X is a hard register
11157 and NOTE is a death note for a range of hard registers
11158 including X. In that case, we must put REG_DEAD notes for
11159 the remaining registers in place of NOTE. */
11161 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11162 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11163 > GET_MODE_SIZE (GET_MODE (x))))
11165 int deadregno = REGNO (XEXP (note, 0));
11167 = (deadregno + HARD_REGNO_NREGS (deadregno,
11168 GET_MODE (XEXP (note, 0))));
11169 int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11172 for (i = deadregno; i < deadend; i++)
11173 if (i < regno || i >= ourend)
11174 REG_NOTES (where_dead)
11175 = gen_rtx_EXPR_LIST (REG_DEAD,
11176 gen_rtx_REG (reg_raw_mode[i], i),
11177 REG_NOTES (where_dead));
11179 /* If we didn't find any note, or if we found a REG_DEAD note that
11180 covers only part of the given reg, and we have a multi-reg hard
11181 register, then to be safe we must check for REG_DEAD notes
11182 for each register other than the first. They could have
11183 their own REG_DEAD notes lying around. */
11184 else if ((note == 0
11186 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11187 < GET_MODE_SIZE (GET_MODE (x)))))
11188 && regno < FIRST_PSEUDO_REGISTER
11189 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
11191 int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11196 offset = HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0)));
11200 for (i = regno + offset; i < ourend; i++)
11201 move_deaths (gen_rtx_REG (reg_raw_mode[i], i),
11202 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
11205 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
11207 XEXP (note, 1) = *pnotes;
11211 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
11213 REG_N_DEATHS (regno)++;
11219 else if (GET_CODE (x) == SET)
11221 rtx dest = SET_DEST (x);
11223 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
11225 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11226 that accesses one word of a multi-word item, some
11227 piece of everything register in the expression is used by
11228 this insn, so remove any old death. */
11230 if (GET_CODE (dest) == ZERO_EXTRACT
11231 || GET_CODE (dest) == STRICT_LOW_PART
11232 || (GET_CODE (dest) == SUBREG
11233 && (((GET_MODE_SIZE (GET_MODE (dest))
11234 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
11235 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
11236 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
11238 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
11242 /* If this is some other SUBREG, we know it replaces the entire
11243 value, so use that as the destination. */
11244 if (GET_CODE (dest) == SUBREG)
11245 dest = SUBREG_REG (dest);
11247 /* If this is a MEM, adjust deaths of anything used in the address.
11248 For a REG (the only other possibility), the entire value is
11249 being replaced so the old value is not used in this insn. */
11251 if (GET_CODE (dest) == MEM)
11252 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
11257 else if (GET_CODE (x) == CLOBBER)
11260 len = GET_RTX_LENGTH (code);
11261 fmt = GET_RTX_FORMAT (code);
11263 for (i = 0; i < len; i++)
11268 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11269 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
11272 else if (fmt[i] == 'e')
11273 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
11277 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11278 pattern of an insn. X must be a REG. */
11281 reg_bitfield_target_p (x, body)
11287 if (GET_CODE (body) == SET)
11289 rtx dest = SET_DEST (body);
11291 int regno, tregno, endregno, endtregno;
11293 if (GET_CODE (dest) == ZERO_EXTRACT)
11294 target = XEXP (dest, 0);
11295 else if (GET_CODE (dest) == STRICT_LOW_PART)
11296 target = SUBREG_REG (XEXP (dest, 0));
11300 if (GET_CODE (target) == SUBREG)
11301 target = SUBREG_REG (target);
11303 if (GET_CODE (target) != REG)
11306 tregno = REGNO (target), regno = REGNO (x);
11307 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
11308 return target == x;
11310 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
11311 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11313 return endregno > tregno && regno < endtregno;
11316 else if (GET_CODE (body) == PARALLEL)
11317 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
11318 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
11324 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11325 as appropriate. I3 and I2 are the insns resulting from the combination
11326 insns including FROM (I2 may be zero).
11328 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
11329 not need REG_DEAD notes because they are being substituted for. This
11330 saves searching in the most common cases.
11332 Each note in the list is either ignored or placed on some insns, depending
11333 on the type of note. */
11336 distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
11340 rtx elim_i2, elim_i1;
11342 rtx note, next_note;
11345 for (note = notes; note; note = next_note)
11347 rtx place = 0, place2 = 0;
11349 /* If this NOTE references a pseudo register, ensure it references
11350 the latest copy of that register. */
11351 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
11352 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
11353 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
11355 next_note = XEXP (note, 1);
11356 switch (REG_NOTE_KIND (note))
11359 case REG_EXEC_COUNT:
11360 /* Doesn't matter much where we put this, as long as it's somewhere.
11361 It is preferable to keep these notes on branches, which is most
11362 likely to be i3. */
11367 /* Any clobbers for i3 may still exist, and so we must process
11368 REG_UNUSED notes from that insn.
11370 Any clobbers from i2 or i1 can only exist if they were added by
11371 recog_for_combine. In that case, recog_for_combine created the
11372 necessary REG_UNUSED notes. Trying to keep any original
11373 REG_UNUSED notes from these insns can cause incorrect output
11374 if it is for the same register as the original i3 dest.
11375 In that case, we will notice that the register is set in i3,
11376 and then add a REG_UNUSED note for the destination of i3, which
11377 is wrong. However, it is possible to have REG_UNUSED notes from
11378 i2 or i1 for register which were both used and clobbered, so
11379 we keep notes from i2 or i1 if they will turn into REG_DEAD
11382 /* If this register is set or clobbered in I3, put the note there
11383 unless there is one already. */
11384 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
11386 if (from_insn != i3)
11389 if (! (GET_CODE (XEXP (note, 0)) == REG
11390 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
11391 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
11394 /* Otherwise, if this register is used by I3, then this register
11395 now dies here, so we must put a REG_DEAD note here unless there
11397 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
11398 && ! (GET_CODE (XEXP (note, 0)) == REG
11399 ? find_regno_note (i3, REG_DEAD, REGNO (XEXP (note, 0)))
11400 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
11402 PUT_REG_NOTE_KIND (note, REG_DEAD);
11411 /* These notes say something about results of an insn. We can
11412 only support them if they used to be on I3 in which case they
11413 remain on I3. Otherwise they are ignored.
11415 If the note refers to an expression that is not a constant, we
11416 must also ignore the note since we cannot tell whether the
11417 equivalence is still true. It might be possible to do
11418 slightly better than this (we only have a problem if I2DEST
11419 or I1DEST is present in the expression), but it doesn't
11420 seem worth the trouble. */
11422 if (from_insn == i3
11423 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
11428 case REG_NO_CONFLICT:
11430 /* These notes say something about how a register is used. They must
11431 be present on any use of the register in I2 or I3. */
11432 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
11435 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
11445 /* It is too much trouble to try to see if this note is still
11446 correct in all situations. It is better to simply delete it. */
11450 /* If the insn previously containing this note still exists,
11451 put it back where it was. Otherwise move it to the previous
11452 insn. Adjust the corresponding REG_LIBCALL note. */
11453 if (GET_CODE (from_insn) != NOTE)
11457 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
11458 place = prev_real_insn (from_insn);
11460 XEXP (tem, 0) = place;
11465 /* This is handled similarly to REG_RETVAL. */
11466 if (GET_CODE (from_insn) != NOTE)
11470 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
11471 place = next_real_insn (from_insn);
11473 XEXP (tem, 0) = place;
11478 /* If the register is used as an input in I3, it dies there.
11479 Similarly for I2, if it is non-zero and adjacent to I3.
11481 If the register is not used as an input in either I3 or I2
11482 and it is not one of the registers we were supposed to eliminate,
11483 there are two possibilities. We might have a non-adjacent I2
11484 or we might have somehow eliminated an additional register
11485 from a computation. For example, we might have had A & B where
11486 we discover that B will always be zero. In this case we will
11487 eliminate the reference to A.
11489 In both cases, we must search to see if we can find a previous
11490 use of A and put the death note there. */
11493 && GET_CODE (from_insn) == CALL_INSN
11494 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
11496 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
11498 else if (i2 != 0 && next_nonnote_insn (i2) == i3
11499 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11502 if (XEXP (note, 0) == elim_i2 || XEXP (note, 0) == elim_i1)
11505 /* If the register is used in both I2 and I3 and it dies in I3,
11506 we might have added another reference to it. If reg_n_refs
11507 was 2, bump it to 3. This has to be correct since the
11508 register must have been set somewhere. The reason this is
11509 done is because local-alloc.c treats 2 references as a
11512 if (place == i3 && i2 != 0 && GET_CODE (XEXP (note, 0)) == REG
11513 && REG_N_REFS (REGNO (XEXP (note, 0)))== 2
11514 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11515 REG_N_REFS (REGNO (XEXP (note, 0))) = 3;
11519 for (tem = prev_nonnote_insn (i3);
11521 && (GET_CODE (tem) == INSN || GET_CODE (tem) == CALL_INSN);
11522 tem = prev_nonnote_insn (tem))
11524 /* If the register is being set at TEM, see if that is all
11525 TEM is doing. If so, delete TEM. Otherwise, make this
11526 into a REG_UNUSED note instead. */
11527 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
11529 rtx set = single_set (tem);
11530 rtx inner_dest = 0;
11533 for (inner_dest = SET_DEST (set);
11534 GET_CODE (inner_dest) == STRICT_LOW_PART
11535 || GET_CODE (inner_dest) == SUBREG
11536 || GET_CODE (inner_dest) == ZERO_EXTRACT;
11537 inner_dest = XEXP (inner_dest, 0))
11540 /* Verify that it was the set, and not a clobber that
11541 modified the register. */
11543 if (set != 0 && ! side_effects_p (SET_SRC (set))
11544 && rtx_equal_p (XEXP (note, 0), inner_dest))
11546 /* Move the notes and links of TEM elsewhere.
11547 This might delete other dead insns recursively.
11548 First set the pattern to something that won't use
11551 PATTERN (tem) = pc_rtx;
11553 distribute_notes (REG_NOTES (tem), tem, tem,
11554 NULL_RTX, NULL_RTX, NULL_RTX);
11555 distribute_links (LOG_LINKS (tem));
11557 PUT_CODE (tem, NOTE);
11558 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
11559 NOTE_SOURCE_FILE (tem) = 0;
11561 /* If the register is both set and used here, put the
11562 REG_DEAD note here, but place a REG_UNUSED note
11563 here too unless there already is one. */
11564 else if (reg_referenced_p (XEXP (note, 0),
11569 if (! find_regno_note (tem, REG_UNUSED,
11570 REGNO (XEXP (note, 0))))
11572 = gen_rtx_EXPR_LIST (REG_UNUSED,
11578 PUT_REG_NOTE_KIND (note, REG_UNUSED);
11580 /* If there isn't already a REG_UNUSED note, put one
11582 if (! find_regno_note (tem, REG_UNUSED,
11583 REGNO (XEXP (note, 0))))
11588 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
11589 || (GET_CODE (tem) == CALL_INSN
11590 && find_reg_fusage (tem, USE, XEXP (note, 0))))
11594 /* If we are doing a 3->2 combination, and we have a
11595 register which formerly died in i3 and was not used
11596 by i2, which now no longer dies in i3 and is used in
11597 i2 but does not die in i2, and place is between i2
11598 and i3, then we may need to move a link from place to
11600 if (i2 && INSN_UID (place) <= max_uid_cuid
11601 && INSN_CUID (place) > INSN_CUID (i2)
11602 && from_insn && INSN_CUID (from_insn) > INSN_CUID (i2)
11603 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11605 rtx links = LOG_LINKS (place);
11606 LOG_LINKS (place) = 0;
11607 distribute_links (links);
11613 /* If we haven't found an insn for the death note and it
11614 is still a REG_DEAD note, but we have hit a CODE_LABEL,
11615 insert a USE insn for the register at that label and
11616 put the death node there. This prevents problems with
11617 call-state tracking in caller-save.c. */
11618 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0 && tem != 0)
11621 = emit_insn_after (gen_rtx_USE (VOIDmode, XEXP (note, 0)),
11624 /* If this insn was emitted between blocks, then update
11625 basic_block_head of the current block to include it. */
11626 if (basic_block_end[this_basic_block - 1] == tem)
11627 basic_block_head[this_basic_block] = place;
11631 /* If the register is set or already dead at PLACE, we needn't do
11632 anything with this note if it is still a REG_DEAD note.
11633 We can here if it is set at all, not if is it totally replace,
11634 which is what `dead_or_set_p' checks, so also check for it being
11638 if (place && REG_NOTE_KIND (note) == REG_DEAD)
11640 int regno = REGNO (XEXP (note, 0));
11642 if (dead_or_set_p (place, XEXP (note, 0))
11643 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
11645 /* Unless the register previously died in PLACE, clear
11646 reg_last_death. [I no longer understand why this is
11648 if (reg_last_death[regno] != place)
11649 reg_last_death[regno] = 0;
11653 reg_last_death[regno] = place;
11655 /* If this is a death note for a hard reg that is occupying
11656 multiple registers, ensure that we are still using all
11657 parts of the object. If we find a piece of the object
11658 that is unused, we must add a USE for that piece before
11659 PLACE and put the appropriate REG_DEAD note on it.
11661 An alternative would be to put a REG_UNUSED for the pieces
11662 on the insn that set the register, but that can't be done if
11663 it is not in the same block. It is simpler, though less
11664 efficient, to add the USE insns. */
11666 if (place && regno < FIRST_PSEUDO_REGISTER
11667 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
11670 = regno + HARD_REGNO_NREGS (regno,
11671 GET_MODE (XEXP (note, 0)));
11675 for (i = regno; i < endregno; i++)
11676 if (! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
11677 && ! find_regno_fusage (place, USE, i))
11679 rtx piece = gen_rtx_REG (reg_raw_mode[i], i);
11682 /* See if we already placed a USE note for this
11683 register in front of PLACE. */
11685 GET_CODE (PREV_INSN (p)) == INSN
11686 && GET_CODE (PATTERN (PREV_INSN (p))) == USE;
11688 if (rtx_equal_p (piece,
11689 XEXP (PATTERN (PREV_INSN (p)), 0)))
11698 = emit_insn_before (gen_rtx_USE (VOIDmode,
11701 REG_NOTES (use_insn)
11702 = gen_rtx_EXPR_LIST (REG_DEAD, piece,
11703 REG_NOTES (use_insn));
11709 /* Check for the case where the register dying partially
11710 overlaps the register set by this insn. */
11712 for (i = regno; i < endregno; i++)
11713 if (dead_or_set_regno_p (place, i))
11721 /* Put only REG_DEAD notes for pieces that are
11722 still used and that are not already dead or set. */
11724 for (i = regno; i < endregno; i++)
11726 rtx piece = gen_rtx_REG (reg_raw_mode[i], i);
11728 if ((reg_referenced_p (piece, PATTERN (place))
11729 || (GET_CODE (place) == CALL_INSN
11730 && find_reg_fusage (place, USE, piece)))
11731 && ! dead_or_set_p (place, piece)
11732 && ! reg_bitfield_target_p (piece,
11735 = gen_rtx_EXPR_LIST (REG_DEAD,
11736 piece, REG_NOTES (place));
11746 /* Any other notes should not be present at this point in the
11753 XEXP (note, 1) = REG_NOTES (place);
11754 REG_NOTES (place) = note;
11756 else if ((REG_NOTE_KIND (note) == REG_DEAD
11757 || REG_NOTE_KIND (note) == REG_UNUSED)
11758 && GET_CODE (XEXP (note, 0)) == REG)
11759 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
11763 if ((REG_NOTE_KIND (note) == REG_DEAD
11764 || REG_NOTE_KIND (note) == REG_UNUSED)
11765 && GET_CODE (XEXP (note, 0)) == REG)
11766 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
11768 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
11769 REG_NOTE_KIND (note),
11771 REG_NOTES (place2));
11776 /* Similarly to above, distribute the LOG_LINKS that used to be present on
11777 I3, I2, and I1 to new locations. This is also called in one case to
11778 add a link pointing at I3 when I3's destination is changed. */
11781 distribute_links (links)
11784 rtx link, next_link;
11786 for (link = links; link; link = next_link)
11792 next_link = XEXP (link, 1);
11794 /* If the insn that this link points to is a NOTE or isn't a single
11795 set, ignore it. In the latter case, it isn't clear what we
11796 can do other than ignore the link, since we can't tell which
11797 register it was for. Such links wouldn't be used by combine
11800 It is not possible for the destination of the target of the link to
11801 have been changed by combine. The only potential of this is if we
11802 replace I3, I2, and I1 by I3 and I2. But in that case the
11803 destination of I2 also remains unchanged. */
11805 if (GET_CODE (XEXP (link, 0)) == NOTE
11806 || (set = single_set (XEXP (link, 0))) == 0)
11809 reg = SET_DEST (set);
11810 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
11811 || GET_CODE (reg) == SIGN_EXTRACT
11812 || GET_CODE (reg) == STRICT_LOW_PART)
11813 reg = XEXP (reg, 0);
11815 /* A LOG_LINK is defined as being placed on the first insn that uses
11816 a register and points to the insn that sets the register. Start
11817 searching at the next insn after the target of the link and stop
11818 when we reach a set of the register or the end of the basic block.
11820 Note that this correctly handles the link that used to point from
11821 I3 to I2. Also note that not much searching is typically done here
11822 since most links don't point very far away. */
11824 for (insn = NEXT_INSN (XEXP (link, 0));
11825 (insn && (this_basic_block == n_basic_blocks - 1
11826 || basic_block_head[this_basic_block + 1] != insn));
11827 insn = NEXT_INSN (insn))
11828 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
11829 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
11831 if (reg_referenced_p (reg, PATTERN (insn)))
11835 else if (GET_CODE (insn) == CALL_INSN
11836 && find_reg_fusage (insn, USE, reg))
11842 /* If we found a place to put the link, place it there unless there
11843 is already a link to the same insn as LINK at that point. */
11849 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
11850 if (XEXP (link2, 0) == XEXP (link, 0))
11855 XEXP (link, 1) = LOG_LINKS (place);
11856 LOG_LINKS (place) = link;
11858 /* Set added_links_insn to the earliest insn we added a
11860 if (added_links_insn == 0
11861 || INSN_CUID (added_links_insn) > INSN_CUID (place))
11862 added_links_insn = place;
11868 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
11874 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
11875 && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE)
11876 insn = NEXT_INSN (insn);
11878 if (INSN_UID (insn) > max_uid_cuid)
11881 return INSN_CUID (insn);
11885 dump_combine_stats (file)
11890 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
11891 combine_attempts, combine_merges, combine_extras, combine_successes);
11895 dump_combine_total_stats (file)
11900 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
11901 total_attempts, total_merges, total_extras, total_successes);