1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
21 /* This module is essentially the "combiner" phase of the U. of Arizona
22 Portable Optimizer, but redone to work on our list-structured
23 representation for RTL instead of their string representation.
25 The LOG_LINKS of each insn identify the most recent assignment
26 to each REG used in the insn. It is a list of previous insns,
27 each of which contains a SET for a REG that is used in this insn
28 and not used or set in between. LOG_LINKs never cross basic blocks.
29 They were set up by the preceding pass (lifetime analysis).
31 We try to combine each pair of insns joined by a logical link.
32 We also try to combine triples of insns A, B and C when
33 C has a link back to B and B has a link back to A.
35 LOG_LINKS does not have links for use of the CC0. They don't
36 need to, because the insn that sets the CC0 is always immediately
37 before the insn that tests it. So we always regard a branch
38 insn as having a logical link to the preceding insn. The same is true
39 for an insn explicitly using CC0.
41 We check (with use_crosses_set_p) to avoid combining in such a way
42 as to move a computation to a place where its value would be different.
44 Combination is done by mathematically substituting the previous
45 insn(s) values for the regs they set into the expressions in
46 the later insns that refer to these regs. If the result is a valid insn
47 for our target machine, according to the machine description,
48 we install it, delete the earlier insns, and update the data flow
49 information (LOG_LINKS and REG_NOTES) for what we did.
51 There are a few exceptions where the dataflow information created by
52 flow.c aren't completely updated:
54 - reg_live_length is not updated
55 - reg_n_refs is not adjusted in the rare case when a register is
56 no longer required in a computation
57 - there are extremely rare cases (see distribute_regnotes) when a
59 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
60 removed because there is no way to know which register it was
63 To simplify substitution, we combine only when the earlier insn(s)
64 consist of only a single assignment. To simplify updating afterward,
65 we never combine when a subroutine call appears in the middle.
67 Since we do not represent assignments to CC0 explicitly except when that
68 is all an insn does, there is no LOG_LINKS entry in an insn that uses
69 the condition code for the insn that set the condition code.
70 Fortunately, these two insns must be consecutive.
71 Therefore, every JUMP_INSN is taken to have an implicit logical link
72 to the preceding insn. This is not quite right, since non-jumps can
73 also use the condition code; but in practice such insns would not
82 #include "basic-block.h"
83 #include "insn-config.h"
84 #include "insn-flags.h"
85 #include "insn-codes.h"
86 #include "insn-attr.h"
91 /* It is not safe to use ordinary gen_lowpart in combine.
92 Use gen_lowpart_for_combine instead. See comments there. */
93 #define gen_lowpart dont_use_gen_lowpart_you_dummy
95 /* Number of attempts to combine instructions in this function. */
97 static int combine_attempts;
99 /* Number of attempts that got as far as substitution in this function. */
101 static int combine_merges;
103 /* Number of instructions combined with added SETs in this function. */
105 static int combine_extras;
107 /* Number of instructions combined in this function. */
109 static int combine_successes;
111 /* Totals over entire compilation. */
113 static int total_attempts, total_merges, total_extras, total_successes;
115 /* Vector mapping INSN_UIDs to cuids.
116 The cuids are like uids but increase monotonically always.
117 Combine always uses cuids so that it can compare them.
118 But actually renumbering the uids, which we used to do,
119 proves to be a bad idea because it makes it hard to compare
120 the dumps produced by earlier passes with those from later passes. */
122 static int *uid_cuid;
124 /* Get the cuid of an insn. */
126 #define INSN_CUID(INSN) (uid_cuid[INSN_UID (INSN)])
128 /* Maximum register number, which is the size of the tables below. */
130 static int combine_max_regno;
132 /* Record last point of death of (hard or pseudo) register n. */
134 static rtx *reg_last_death;
136 /* Record last point of modification of (hard or pseudo) register n. */
138 static rtx *reg_last_set;
140 /* Record the cuid of the last insn that invalidated memory
141 (anything that writes memory, and subroutine calls, but not pushes). */
143 static int mem_last_set;
145 /* Record the cuid of the last CALL_INSN
146 so we can tell whether a potential combination crosses any calls. */
148 static int last_call_cuid;
150 /* When `subst' is called, this is the insn that is being modified
151 (by combining in a previous insn). The PATTERN of this insn
152 is still the old pattern partially modified and it should not be
153 looked at, but this may be used to examine the successors of the insn
154 to judge whether a simplification is valid. */
156 static rtx subst_insn;
158 /* This is the lowest CUID that `subst' is currently dealing with.
159 get_last_value will not return a value if the register was set at or
160 after this CUID. If not for this mechanism, we could get confused if
161 I2 or I1 in try_combine were an insn that used the old value of a register
162 to obtain a new value. In that case, we might erroneously get the
163 new value of the register when we wanted the old one. */
165 static int subst_low_cuid;
167 /* This is the value of undobuf.num_undo when we started processing this
168 substitution. This will prevent gen_rtx_combine from re-used a piece
169 from the previous expression. Doing so can produce circular rtl
172 static int previous_num_undos;
174 /* The next group of arrays allows the recording of the last value assigned
175 to (hard or pseudo) register n. We use this information to see if a
176 operation being processed is redundant given a prior operation performed
177 on the register. For example, an `and' with a constant is redundant if
178 all the zero bits are already known to be turned off.
180 We use an approach similar to that used by cse, but change it in the
183 (1) We do not want to reinitialize at each label.
184 (2) It is useful, but not critical, to know the actual value assigned
185 to a register. Often just its form is helpful.
187 Therefore, we maintain the following arrays:
189 reg_last_set_value the last value assigned
190 reg_last_set_label records the value of label_tick when the
191 register was assigned
192 reg_last_set_table_tick records the value of label_tick when a
193 value using the register is assigned
194 reg_last_set_invalid set to non-zero when it is not valid
195 to use the value of this register in some
198 To understand the usage of these tables, it is important to understand
199 the distinction between the value in reg_last_set_value being valid
200 and the register being validly contained in some other expression in the
203 Entry I in reg_last_set_value is valid if it is non-zero, and either
204 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
206 Register I may validly appear in any expression returned for the value
207 of another register if reg_n_sets[i] is 1. It may also appear in the
208 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
209 reg_last_set_invalid[j] is zero.
211 If an expression is found in the table containing a register which may
212 not validly appear in an expression, the register is replaced by
213 something that won't match, (clobber (const_int 0)).
215 reg_last_set_invalid[i] is set non-zero when register I is being assigned
216 to and reg_last_set_table_tick[i] == label_tick. */
218 /* Record last value assigned to (hard or pseudo) register n. */
220 static rtx *reg_last_set_value;
222 /* Record the value of label_tick when the value for register n is placed in
223 reg_last_set_value[n]. */
225 static short *reg_last_set_label;
227 /* Record the value of label_tick when an expression involving register n
228 is placed in reg_last_set_value. */
230 static short *reg_last_set_table_tick;
232 /* Set non-zero if references to register n in expressions should not be
235 static char *reg_last_set_invalid;
237 /* Incremented for each label. */
239 static short label_tick;
241 /* Some registers that are set more than once and used in more than one
242 basic block are nevertheless always set in similar ways. For example,
243 a QImode register may be loaded from memory in two places on a machine
244 where byte loads zero extend.
246 We record in the following array what we know about the significant
247 bits of a register, specifically which bits are known to be zero.
249 If an entry is zero, it means that we don't know anything special. */
251 static HOST_WIDE_INT *reg_significant;
253 /* Mode used to compute significance in reg_significant. It is the largest
254 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
256 static enum machine_mode significant_mode;
258 /* Nonzero if we know that a register has some leading bits that are always
259 equal to the sign bit. */
261 static char *reg_sign_bit_copies;
263 /* Nonzero when reg_significant and reg_sign_bit_copies can be safely used.
264 It is zero while computing them and after combine has completed. This
265 former test prevents propagating values based on previously set values,
266 which can be incorrect if a variable is modified in a loop. */
268 static int significant_valid;
270 /* Record one modification to rtl structure
271 to be undone by storing old_contents into *where.
272 is_int is 1 if the contents are an int. */
277 union {rtx rtx; int i;} old_contents;
278 union {rtx *rtx; int *i;} where;
281 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
282 num_undo says how many are currently recorded.
284 storage is nonzero if we must undo the allocation of new storage.
285 The value of storage is what to pass to obfree.
287 other_insn is nonzero if we have modified some other insn in the process
288 of working on subst_insn. It must be verified too. */
296 struct undo undo[MAX_UNDO];
300 static struct undobuf undobuf;
302 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
303 insn. The substitution can be undone by undo_all. If INTO is already
304 set to NEWVAL, do not record this change. Because computing NEWVAL might
305 also call SUBST, we have to compute it before we put anything into
308 #define SUBST(INTO, NEWVAL) \
309 do { rtx _new = (NEWVAL); \
310 if (undobuf.num_undo < MAX_UNDO) \
312 undobuf.undo[undobuf.num_undo].is_int = 0; \
313 undobuf.undo[undobuf.num_undo].where.rtx = &INTO; \
314 undobuf.undo[undobuf.num_undo].old_contents.rtx = INTO; \
316 if (undobuf.undo[undobuf.num_undo].old_contents.rtx != INTO) \
317 undobuf.num_undo++; \
321 /* Similar to SUBST, but NEWVAL is an int. INTO will normally be an XINT
323 Note that substitution for the value of a CONST_INT is not safe. */
325 #define SUBST_INT(INTO, NEWVAL) \
326 do { if (undobuf.num_undo < MAX_UNDO) \
328 undobuf.undo[undobuf.num_undo].is_int = 1; \
329 undobuf.undo[undobuf.num_undo].where.i = (int *) &INTO; \
330 undobuf.undo[undobuf.num_undo].old_contents.i = INTO; \
332 if (undobuf.undo[undobuf.num_undo].old_contents.i != INTO) \
333 undobuf.num_undo++; \
337 /* Number of times the pseudo being substituted for
338 was found and replaced. */
340 static int n_occurrences;
342 static void set_significant ();
343 static void move_deaths ();
345 static void record_value_for_reg ();
346 static void record_dead_and_set_regs ();
347 static int use_crosses_set_p ();
348 static rtx try_combine ();
349 static rtx *find_split_point ();
351 static void undo_all ();
352 static int reg_dead_at_p ();
353 static rtx expand_compound_operation ();
354 static rtx expand_field_assignment ();
355 static rtx make_extraction ();
356 static int get_pos_from_mask ();
357 static rtx force_to_mode ();
358 static rtx known_cond ();
359 static rtx make_field_assignment ();
360 static rtx make_compound_operation ();
361 static rtx apply_distributive_law ();
362 static rtx simplify_and_const_int ();
363 static unsigned HOST_WIDE_INT significant_bits ();
364 static int num_sign_bit_copies ();
365 static int merge_outer_ops ();
366 static rtx simplify_shift_const ();
367 static int recog_for_combine ();
368 static rtx gen_lowpart_for_combine ();
369 static rtx gen_rtx_combine ();
370 static rtx gen_binary ();
371 static rtx gen_unary ();
372 static enum rtx_code simplify_comparison ();
373 static int reversible_comparison_p ();
374 static int get_last_value_validate ();
375 static rtx get_last_value ();
376 static void distribute_notes ();
377 static void distribute_links ();
379 /* Main entry point for combiner. F is the first insn of the function.
380 NREGS is the first unused pseudo-reg number. */
383 combine_instructions (f, nregs)
387 register rtx insn, next, prev;
389 register rtx links, nextlinks;
391 combine_attempts = 0;
394 combine_successes = 0;
396 combine_max_regno = nregs;
398 reg_last_death = (rtx *) alloca (nregs * sizeof (rtx));
399 reg_last_set = (rtx *) alloca (nregs * sizeof (rtx));
400 reg_last_set_value = (rtx *) alloca (nregs * sizeof (rtx));
401 reg_last_set_table_tick = (short *) alloca (nregs * sizeof (short));
402 reg_last_set_label = (short *) alloca (nregs * sizeof (short));
403 reg_last_set_invalid = (char *) alloca (nregs * sizeof (char));
404 reg_significant = (HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT));
405 reg_sign_bit_copies = (char *) alloca (nregs * sizeof (char));
407 bzero (reg_last_death, nregs * sizeof (rtx));
408 bzero (reg_last_set, nregs * sizeof (rtx));
409 bzero (reg_last_set_value, nregs * sizeof (rtx));
410 bzero (reg_last_set_table_tick, nregs * sizeof (short));
411 bzero (reg_last_set_invalid, nregs * sizeof (char));
412 bzero (reg_significant, nregs * sizeof (HOST_WIDE_INT));
413 bzero (reg_sign_bit_copies, nregs * sizeof (char));
415 init_recog_no_volatile ();
417 /* Compute maximum uid value so uid_cuid can be allocated. */
419 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
420 if (INSN_UID (insn) > i)
423 uid_cuid = (int *) alloca ((i + 1) * sizeof (int));
425 significant_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
427 /* Don't use reg_significant when computing it. This can cause problems
428 when, for example, we have j <<= 1 in a loop. */
430 significant_valid = 0;
432 /* Compute the mapping from uids to cuids.
433 Cuids are numbers assigned to insns, like uids,
434 except that cuids increase monotonically through the code.
436 Scan all SETs and see if we can deduce anything about what
437 bits are significant for some registers. */
439 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
441 INSN_CUID (insn) = ++i;
442 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
443 note_stores (PATTERN (insn), set_significant);
446 significant_valid = 1;
448 /* Now scan all the insns in forward order. */
454 for (insn = f; insn; insn = next ? next : NEXT_INSN (insn))
458 if (GET_CODE (insn) == CODE_LABEL)
461 else if (GET_CODE (insn) == INSN
462 || GET_CODE (insn) == CALL_INSN
463 || GET_CODE (insn) == JUMP_INSN)
465 /* Try this insn with each insn it links back to. */
467 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
468 if ((next = try_combine (insn, XEXP (links, 0), NULL_RTX)) != 0)
471 /* Try each sequence of three linked insns ending with this one. */
473 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
474 for (nextlinks = LOG_LINKS (XEXP (links, 0)); nextlinks;
475 nextlinks = XEXP (nextlinks, 1))
476 if ((next = try_combine (insn, XEXP (links, 0),
477 XEXP (nextlinks, 0))) != 0)
481 /* Try to combine a jump insn that uses CC0
482 with a preceding insn that sets CC0, and maybe with its
483 logical predecessor as well.
484 This is how we make decrement-and-branch insns.
485 We need this special code because data flow connections
486 via CC0 do not get entered in LOG_LINKS. */
488 if (GET_CODE (insn) == JUMP_INSN
489 && (prev = prev_nonnote_insn (insn)) != 0
490 && GET_CODE (prev) == INSN
491 && sets_cc0_p (PATTERN (prev)))
493 if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
496 for (nextlinks = LOG_LINKS (prev); nextlinks;
497 nextlinks = XEXP (nextlinks, 1))
498 if ((next = try_combine (insn, prev,
499 XEXP (nextlinks, 0))) != 0)
503 /* Do the same for an insn that explicitly references CC0. */
504 if (GET_CODE (insn) == INSN
505 && (prev = prev_nonnote_insn (insn)) != 0
506 && GET_CODE (prev) == INSN
507 && sets_cc0_p (PATTERN (prev))
508 && GET_CODE (PATTERN (insn)) == SET
509 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
511 if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
514 for (nextlinks = LOG_LINKS (prev); nextlinks;
515 nextlinks = XEXP (nextlinks, 1))
516 if ((next = try_combine (insn, prev,
517 XEXP (nextlinks, 0))) != 0)
521 /* Finally, see if any of the insns that this insn links to
522 explicitly references CC0. If so, try this insn, that insn,
523 and its predecessor if it sets CC0. */
524 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
525 if (GET_CODE (XEXP (links, 0)) == INSN
526 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
527 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
528 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
529 && GET_CODE (prev) == INSN
530 && sets_cc0_p (PATTERN (prev))
531 && (next = try_combine (insn, XEXP (links, 0), prev)) != 0)
535 /* Try combining an insn with two different insns whose results it
537 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
538 for (nextlinks = XEXP (links, 1); nextlinks;
539 nextlinks = XEXP (nextlinks, 1))
540 if ((next = try_combine (insn, XEXP (links, 0),
541 XEXP (nextlinks, 0))) != 0)
544 if (GET_CODE (insn) != NOTE)
545 record_dead_and_set_regs (insn);
552 total_attempts += combine_attempts;
553 total_merges += combine_merges;
554 total_extras += combine_extras;
555 total_successes += combine_successes;
557 significant_valid = 0;
560 /* Called via note_stores. If X is a pseudo that is used in more than
561 one basic block, is narrower that HOST_BITS_PER_WIDE_INT, and is being
562 set, record what bits are significant. If we are clobbering X,
563 ignore this "set" because the clobbered value won't be used.
565 If we are setting only a portion of X and we can't figure out what
566 portion, assume all bits will be used since we don't know what will
569 Similarly, set how many bits of X are known to be copies of the sign bit
570 at all locations in the function. This is the smallest number implied
574 set_significant (x, set)
580 if (GET_CODE (x) == REG
581 && REGNO (x) >= FIRST_PSEUDO_REGISTER
582 && reg_n_sets[REGNO (x)] > 1
583 && reg_basic_block[REGNO (x)] < 0
584 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
586 if (GET_CODE (set) == CLOBBER)
589 /* If this is a complex assignment, see if we can convert it into a
590 simple assignment. */
591 set = expand_field_assignment (set);
592 if (SET_DEST (set) == x)
594 reg_significant[REGNO (x)]
595 |= significant_bits (SET_SRC (set), significant_mode);
596 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
597 if (reg_sign_bit_copies[REGNO (x)] == 0
598 || reg_sign_bit_copies[REGNO (x)] > num)
599 reg_sign_bit_copies[REGNO (x)] = num;
603 reg_significant[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
604 reg_sign_bit_copies[REGNO (x)] = 0;
609 /* See if INSN can be combined into I3. PRED and SUCC are optionally
610 insns that were previously combined into I3 or that will be combined
611 into the merger of INSN and I3.
613 Return 0 if the combination is not allowed for any reason.
615 If the combination is allowed, *PDEST will be set to the single
616 destination of INSN and *PSRC to the single source, and this function
620 can_combine_p (insn, i3, pred, succ, pdest, psrc)
627 rtx set = 0, src, dest;
629 int all_adjacent = (succ ? (next_active_insn (insn) == succ
630 && next_active_insn (succ) == i3)
631 : next_active_insn (insn) == i3);
633 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
634 or a PARALLEL consisting of such a SET and CLOBBERs.
636 If INSN has CLOBBER parallel parts, ignore them for our processing.
637 By definition, these happen during the execution of the insn. When it
638 is merged with another insn, all bets are off. If they are, in fact,
639 needed and aren't also supplied in I3, they may be added by
640 recog_for_combine. Otherwise, it won't match.
642 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
645 Get the source and destination of INSN. If more than one, can't
648 if (GET_CODE (PATTERN (insn)) == SET)
649 set = PATTERN (insn);
650 else if (GET_CODE (PATTERN (insn)) == PARALLEL
651 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
653 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
655 rtx elt = XVECEXP (PATTERN (insn), 0, i);
657 switch (GET_CODE (elt))
659 /* We can ignore CLOBBERs. */
664 /* Ignore SETs whose result isn't used but not those that
665 have side-effects. */
666 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
667 && ! side_effects_p (elt))
670 /* If we have already found a SET, this is a second one and
671 so we cannot combine with this insn. */
679 /* Anything else means we can't combine. */
685 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
686 so don't do anything with it. */
687 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
696 set = expand_field_assignment (set);
697 src = SET_SRC (set), dest = SET_DEST (set);
699 /* Don't eliminate a store in the stack pointer. */
700 if (dest == stack_pointer_rtx
701 /* Don't install a subreg involving two modes not tieable.
702 It can worsen register allocation, and can even make invalid reload
703 insns, since the reg inside may need to be copied from in the
704 outside mode, and that may be invalid if it is an fp reg copied in
705 integer mode. As a special exception, we can allow this if
706 I3 is simply copying DEST, a REG, to CC0. */
707 || (GET_CODE (src) == SUBREG
708 && ! MODES_TIEABLE_P (GET_MODE (src), GET_MODE (SUBREG_REG (src)))
710 && ! (GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
711 && SET_DEST (PATTERN (i3)) == cc0_rtx
712 && GET_CODE (dest) == REG && dest == SET_SRC (PATTERN (i3)))
715 /* If we couldn't eliminate a field assignment, we can't combine. */
716 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
717 /* Don't combine with an insn that sets a register to itself if it has
718 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
719 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
720 /* Can't merge a function call. */
721 || GET_CODE (src) == CALL
722 /* Don't substitute into an incremented register. */
723 || FIND_REG_INC_NOTE (i3, dest)
724 || (succ && FIND_REG_INC_NOTE (succ, dest))
725 /* Don't combine the end of a libcall into anything. */
726 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
727 /* Make sure that DEST is not used after SUCC but before I3. */
728 || (succ && ! all_adjacent
729 && reg_used_between_p (dest, succ, i3))
730 /* Make sure that the value that is to be substituted for the register
731 does not use any registers whose values alter in between. However,
732 If the insns are adjacent, a use can't cross a set even though we
733 think it might (this can happen for a sequence of insns each setting
734 the same destination; reg_last_set of that register might point to
735 a NOTE). Also, don't move a volatile asm across any other insns. */
737 && (use_crosses_set_p (src, INSN_CUID (insn))
738 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))))
739 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
740 better register allocation by not doing the combine. */
741 || find_reg_note (i3, REG_NO_CONFLICT, dest)
742 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
743 /* Don't combine across a CALL_INSN, because that would possibly
744 change whether the life span of some REGs crosses calls or not,
745 and it is a pain to update that information.
746 Exception: if source is a constant, moving it later can't hurt.
747 Accept that special case, because it helps -fforce-addr a lot. */
748 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
751 /* DEST must either be a REG or CC0. */
752 if (GET_CODE (dest) == REG)
754 /* If register alignment is being enforced for multi-word items in all
755 cases except for parameters, it is possible to have a register copy
756 insn referencing a hard register that is not allowed to contain the
757 mode being copied and which would not be valid as an operand of most
758 insns. Eliminate this problem by not combining with such an insn.
760 Also, on some machines we don't want to extend the life of a hard
763 if (GET_CODE (src) == REG
764 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
765 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
766 #ifdef SMALL_REGISTER_CLASSES
767 /* Don't extend the life of a hard register. */
768 || REGNO (src) < FIRST_PSEUDO_REGISTER
770 || (REGNO (src) < FIRST_PSEUDO_REGISTER
771 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))
776 else if (GET_CODE (dest) != CC0)
779 /* Don't substitute for a register intended as a clobberable operand. */
780 if (GET_CODE (PATTERN (i3)) == PARALLEL)
781 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
782 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
783 && rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest))
786 /* If INSN contains anything volatile, or is an `asm' (whether volatile
787 or not), reject, unless nothing volatile comes between it and I3,
788 with the exception of SUCC. */
790 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
791 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
792 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
793 && p != succ && volatile_refs_p (PATTERN (p)))
796 /* If INSN or I2 contains an autoincrement or autodecrement,
797 make sure that register is not used between there and I3,
798 and not already used in I3 either.
799 Also insist that I3 not be a jump; if it were one
800 and the incremented register were spilled, we would lose. */
803 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
804 if (REG_NOTE_KIND (link) == REG_INC
805 && (GET_CODE (i3) == JUMP_INSN
806 || reg_used_between_p (XEXP (link, 0), insn, i3)
807 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
812 /* Don't combine an insn that follows a CC0-setting insn.
813 An insn that uses CC0 must not be separated from the one that sets it.
814 We do, however, allow I2 to follow a CC0-setting insn if that insn
815 is passed as I1; in that case it will be deleted also.
816 We also allow combining in this case if all the insns are adjacent
817 because that would leave the two CC0 insns adjacent as well.
818 It would be more logical to test whether CC0 occurs inside I1 or I2,
819 but that would be much slower, and this ought to be equivalent. */
821 p = prev_nonnote_insn (insn);
822 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
827 /* If we get here, we have passed all the tests and the combination is
836 /* LOC is the location within I3 that contains its pattern or the component
837 of a PARALLEL of the pattern. We validate that it is valid for combining.
839 One problem is if I3 modifies its output, as opposed to replacing it
840 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
841 so would produce an insn that is not equivalent to the original insns.
845 (set (reg:DI 101) (reg:DI 100))
846 (set (subreg:SI (reg:DI 101) 0) <foo>)
848 This is NOT equivalent to:
850 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
851 (set (reg:DI 101) (reg:DI 100))])
853 Not only does this modify 100 (in which case it might still be valid
854 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
856 We can also run into a problem if I2 sets a register that I1
857 uses and I1 gets directly substituted into I3 (not via I2). In that
858 case, we would be getting the wrong value of I2DEST into I3, so we
859 must reject the combination. This case occurs when I2 and I1 both
860 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
861 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
862 of a SET must prevent combination from occurring.
864 On machines where SMALL_REGISTER_CLASSES is defined, we don't combine
865 if the destination of a SET is a hard register.
867 Before doing the above check, we first try to expand a field assignment
868 into a set of logical operations.
870 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
871 we place a register that is both set and used within I3. If more than one
872 such register is detected, we fail.
874 Return 1 if the combination is valid, zero otherwise. */
877 combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
887 if (GET_CODE (x) == SET)
889 rtx set = expand_field_assignment (x);
890 rtx dest = SET_DEST (set);
891 rtx src = SET_SRC (set);
892 rtx inner_dest = dest, inner_src = src;
896 while (GET_CODE (inner_dest) == STRICT_LOW_PART
897 || GET_CODE (inner_dest) == SUBREG
898 || GET_CODE (inner_dest) == ZERO_EXTRACT)
899 inner_dest = XEXP (inner_dest, 0);
901 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
904 while (GET_CODE (inner_src) == STRICT_LOW_PART
905 || GET_CODE (inner_src) == SUBREG
906 || GET_CODE (inner_src) == ZERO_EXTRACT)
907 inner_src = XEXP (inner_src, 0);
909 /* If it is better that two different modes keep two different pseudos,
910 avoid combining them. This avoids producing the following pattern
912 (set (subreg:SI (reg/v:QI 21) 0)
913 (lshiftrt:SI (reg/v:SI 20)
915 If that were made, reload could not handle the pair of
916 reg 20/21, since it would try to get any GENERAL_REGS
917 but some of them don't handle QImode. */
919 if (rtx_equal_p (inner_src, i2dest)
920 && GET_CODE (inner_dest) == REG
921 && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
925 /* Check for the case where I3 modifies its output, as
927 if ((inner_dest != dest
928 && (reg_overlap_mentioned_p (i2dest, inner_dest)
929 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
930 /* This is the same test done in can_combine_p except that we
931 allow a hard register with SMALL_REGISTER_CLASSES if SRC is a
933 || (GET_CODE (inner_dest) == REG
934 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
935 #ifdef SMALL_REGISTER_CLASSES
936 && GET_CODE (src) != CALL
938 && ! HARD_REGNO_MODE_OK (REGNO (inner_dest),
939 GET_MODE (inner_dest))
943 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
946 /* If DEST is used in I3, it is being killed in this insn,
947 so record that for later. */
948 if (pi3dest_killed && GET_CODE (dest) == REG
949 && reg_referenced_p (dest, PATTERN (i3)))
954 *pi3dest_killed = dest;
958 else if (GET_CODE (x) == PARALLEL)
962 for (i = 0; i < XVECLEN (x, 0); i++)
963 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
964 i1_not_in_src, pi3dest_killed))
971 /* Try to combine the insns I1 and I2 into I3.
972 Here I1 and I2 appear earlier than I3.
973 I1 can be zero; then we combine just I2 into I3.
975 It we are combining three insns and the resulting insn is not recognized,
976 try splitting it into two insns. If that happens, I2 and I3 are retained
977 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
980 If we created two insns, return I2; otherwise return I3.
981 Return 0 if the combination does not work. Then nothing is changed. */
984 try_combine (i3, i2, i1)
985 register rtx i3, i2, i1;
987 /* New patterns for I3 and I3, respectively. */
988 rtx newpat, newi2pat = 0;
989 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
990 int added_sets_1, added_sets_2;
991 /* Total number of SETs to put into I3. */
993 /* Nonzero is I2's body now appears in I3. */
995 /* INSN_CODEs for new I3, new I2, and user of condition code. */
996 int insn_code_number, i2_code_number, other_code_number;
997 /* Contains I3 if the destination of I3 is used in its source, which means
998 that the old life of I3 is being killed. If that usage is placed into
999 I2 and not in I3, a REG_DEAD note must be made. */
1000 rtx i3dest_killed = 0;
1001 /* SET_DEST and SET_SRC of I2 and I1. */
1002 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1003 /* PATTERN (I2), or a copy of it in certain cases. */
1005 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1006 int i2dest_in_i2src, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1007 int i1_feeds_i3 = 0;
1008 /* Notes that must be added to REG_NOTES in I3 and I2. */
1009 rtx new_i3_notes, new_i2_notes;
1016 /* If any of I1, I2, and I3 isn't really an insn, we can't do anything.
1017 This can occur when flow deletes an insn that it has merged into an
1018 auto-increment address. We also can't do anything if I3 has a
1019 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1022 if (GET_RTX_CLASS (GET_CODE (i3)) != 'i'
1023 || GET_RTX_CLASS (GET_CODE (i2)) != 'i'
1024 || (i1 && GET_RTX_CLASS (GET_CODE (i1)) != 'i')
1025 || find_reg_note (i3, REG_LIBCALL, NULL_RTX))
1030 undobuf.num_undo = previous_num_undos = 0;
1031 undobuf.other_insn = 0;
1033 /* Save the current high-water-mark so we can free storage if we didn't
1034 accept this combination. */
1035 undobuf.storage = (char *) oballoc (0);
1037 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1038 code below, set I1 to be the earlier of the two insns. */
1039 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1040 temp = i1, i1 = i2, i2 = temp;
1042 /* First check for one important special-case that the code below will
1043 not handle. Namely, the case where I1 is zero, I2 has multiple sets,
1044 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1045 we may be able to replace that destination with the destination of I3.
1046 This occurs in the common code where we compute both a quotient and
1047 remainder into a structure, in which case we want to do the computation
1048 directly into the structure to avoid register-register copies.
1050 We make very conservative checks below and only try to handle the
1051 most common cases of this. For example, we only handle the case
1052 where I2 and I3 are adjacent to avoid making difficult register
1055 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1056 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1057 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1058 #ifdef SMALL_REGISTER_CLASSES
1059 && (GET_CODE (SET_DEST (PATTERN (i3))) != REG
1060 || REGNO (SET_DEST (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER)
1062 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1063 && GET_CODE (PATTERN (i2)) == PARALLEL
1064 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1065 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1066 below would need to check what is inside (and reg_overlap_mentioned_p
1067 doesn't support those codes anyway). Don't allow those destinations;
1068 the resulting insn isn't likely to be recognized anyway. */
1069 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1070 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1071 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1072 SET_DEST (PATTERN (i3)))
1073 && next_real_insn (i2) == i3)
1075 rtx p2 = PATTERN (i2);
1077 /* Make sure that the destination of I3,
1078 which we are going to substitute into one output of I2,
1079 is not used within another output of I2. We must avoid making this:
1080 (parallel [(set (mem (reg 69)) ...)
1081 (set (reg 69) ...)])
1082 which is not well-defined as to order of actions.
1083 (Besides, reload can't handle output reloads for this.)
1085 The problem can also happen if the dest of I3 is a memory ref,
1086 if another dest in I2 is an indirect memory ref. */
1087 for (i = 0; i < XVECLEN (p2, 0); i++)
1088 if (GET_CODE (XVECEXP (p2, 0, i)) == SET
1089 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1090 SET_DEST (XVECEXP (p2, 0, i))))
1093 if (i == XVECLEN (p2, 0))
1094 for (i = 0; i < XVECLEN (p2, 0); i++)
1095 if (SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1100 subst_low_cuid = INSN_CUID (i2);
1103 i2dest = SET_SRC (PATTERN (i3));
1105 /* Replace the dest in I2 with our dest and make the resulting
1106 insn the new pattern for I3. Then skip to where we
1107 validate the pattern. Everything was set up above. */
1108 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1109 SET_DEST (PATTERN (i3)));
1112 goto validate_replacement;
1117 /* If we have no I1 and I2 looks like:
1118 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1120 make up a dummy I1 that is
1123 (set (reg:CC X) (compare:CC Y (const_int 0)))
1125 (We can ignore any trailing CLOBBERs.)
1127 This undoes a previous combination and allows us to match a branch-and-
1130 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1131 && XVECLEN (PATTERN (i2), 0) >= 2
1132 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1133 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1135 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1136 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1137 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1138 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1139 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1140 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1142 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1143 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1148 /* We make I1 with the same INSN_UID as I2. This gives it
1149 the same INSN_CUID for value tracking. Our fake I1 will
1150 never appear in the insn stream so giving it the same INSN_UID
1151 as I2 will not cause a problem. */
1153 i1 = gen_rtx (INSN, VOIDmode, INSN_UID (i2), 0, i2,
1154 XVECEXP (PATTERN (i2), 0, 1), -1, 0, 0);
1156 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1157 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1158 SET_DEST (PATTERN (i1)));
1163 /* Verify that I2 and I1 are valid for combining. */
1164 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1165 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1171 /* Record whether I2DEST is used in I2SRC and similarly for the other
1172 cases. Knowing this will help in register status updating below. */
1173 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1174 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1175 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1177 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1179 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1181 /* Ensure that I3's pattern can be the destination of combines. */
1182 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1183 i1 && i2dest_in_i1src && i1_feeds_i3,
1190 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1191 We used to do this EXCEPT in one case: I3 has a post-inc in an
1192 output operand. However, that exception can give rise to insns like
1194 which is a famous insn on the PDP-11 where the value of r3 used as the
1195 source was model-dependent. Avoid this sort of thing. */
1198 if (!(GET_CODE (PATTERN (i3)) == SET
1199 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1200 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1201 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1202 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1203 /* It's not the exception. */
1206 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1207 if (REG_NOTE_KIND (link) == REG_INC
1208 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1210 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1217 /* See if the SETs in I1 or I2 need to be kept around in the merged
1218 instruction: whenever the value set there is still needed past I3.
1219 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1221 For the SET in I1, we have two cases: If I1 and I2 independently
1222 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1223 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1224 in I1 needs to be kept around unless I1DEST dies or is set in either
1225 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1226 I1DEST. If so, we know I1 feeds into I2. */
1228 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1231 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1232 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1234 /* If the set in I2 needs to be kept around, we must make a copy of
1235 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1236 PATTERN (I2), we are only substituting for the original I1DEST, not into
1237 an already-substituted copy. This also prevents making self-referential
1238 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1241 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1242 ? gen_rtx (SET, VOIDmode, i2dest, i2src)
1246 i2pat = copy_rtx (i2pat);
1250 /* Substitute in the latest insn for the regs set by the earlier ones. */
1252 maxreg = max_reg_num ();
1256 /* It is possible that the source of I2 or I1 may be performing an
1257 unneeded operation, such as a ZERO_EXTEND of something that is known
1258 to have the high part zero. Handle that case by letting subst look at
1259 the innermost one of them.
1261 Another way to do this would be to have a function that tries to
1262 simplify a single insn instead of merging two or more insns. We don't
1263 do this because of the potential of infinite loops and because
1264 of the potential extra memory required. However, doing it the way
1265 we are is a bit of a kludge and doesn't catch all cases.
1267 But only do this if -fexpensive-optimizations since it slows things down
1268 and doesn't usually win. */
1270 if (flag_expensive_optimizations)
1272 /* Pass pc_rtx so no substitutions are done, just simplifications.
1273 The cases that we are interested in here do not involve the few
1274 cases were is_replaced is checked. */
1277 subst_low_cuid = INSN_CUID (i1);
1278 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1282 subst_low_cuid = INSN_CUID (i2);
1283 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1286 previous_num_undos = undobuf.num_undo;
1290 /* Many machines that don't use CC0 have insns that can both perform an
1291 arithmetic operation and set the condition code. These operations will
1292 be represented as a PARALLEL with the first element of the vector
1293 being a COMPARE of an arithmetic operation with the constant zero.
1294 The second element of the vector will set some pseudo to the result
1295 of the same arithmetic operation. If we simplify the COMPARE, we won't
1296 match such a pattern and so will generate an extra insn. Here we test
1297 for this case, where both the comparison and the operation result are
1298 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1299 I2SRC. Later we will make the PARALLEL that contains I2. */
1301 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1302 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1303 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1304 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1307 enum machine_mode compare_mode;
1309 newpat = PATTERN (i3);
1310 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1314 #ifdef EXTRA_CC_MODES
1315 /* See if a COMPARE with the operand we substituted in should be done
1316 with the mode that is currently being used. If not, do the same
1317 processing we do in `subst' for a SET; namely, if the destination
1318 is used only once, try to replace it with a register of the proper
1319 mode and also replace the COMPARE. */
1320 if (undobuf.other_insn == 0
1321 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1322 &undobuf.other_insn))
1323 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1325 != GET_MODE (SET_DEST (newpat))))
1327 int regno = REGNO (SET_DEST (newpat));
1328 rtx new_dest = gen_rtx (REG, compare_mode, regno);
1330 if (regno < FIRST_PSEUDO_REGISTER
1331 || (reg_n_sets[regno] == 1 && ! added_sets_2
1332 && ! REG_USERVAR_P (SET_DEST (newpat))))
1334 if (regno >= FIRST_PSEUDO_REGISTER)
1335 SUBST (regno_reg_rtx[regno], new_dest);
1337 SUBST (SET_DEST (newpat), new_dest);
1338 SUBST (XEXP (*cc_use, 0), new_dest);
1339 SUBST (SET_SRC (newpat),
1340 gen_rtx_combine (COMPARE, compare_mode,
1341 i2src, const0_rtx));
1344 undobuf.other_insn = 0;
1351 n_occurrences = 0; /* `subst' counts here */
1353 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1354 need to make a unique copy of I2SRC each time we substitute it
1355 to avoid self-referential rtl. */
1357 subst_low_cuid = INSN_CUID (i2);
1358 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1359 ! i1_feeds_i3 && i1dest_in_i1src);
1360 previous_num_undos = undobuf.num_undo;
1362 /* Record whether i2's body now appears within i3's body. */
1363 i2_is_used = n_occurrences;
1366 /* If we already got a failure, don't try to do more. Otherwise,
1367 try to substitute in I1 if we have it. */
1369 if (i1 && GET_CODE (newpat) != CLOBBER)
1371 /* Before we can do this substitution, we must redo the test done
1372 above (see detailed comments there) that ensures that I1DEST
1373 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1375 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1383 subst_low_cuid = INSN_CUID (i1);
1384 newpat = subst (newpat, i1dest, i1src, 0, 0);
1385 previous_num_undos = undobuf.num_undo;
1388 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1389 to count all the ways that I2SRC and I1SRC can be used. */
1390 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
1391 && i2_is_used + added_sets_2 > 1)
1392 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
1393 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
1395 /* Fail if we tried to make a new register (we used to abort, but there's
1396 really no reason to). */
1397 || max_reg_num () != maxreg
1398 /* Fail if we couldn't do something and have a CLOBBER. */
1399 || GET_CODE (newpat) == CLOBBER)
1405 /* If the actions of the earlier insns must be kept
1406 in addition to substituting them into the latest one,
1407 we must make a new PARALLEL for the latest insn
1408 to hold additional the SETs. */
1410 if (added_sets_1 || added_sets_2)
1414 if (GET_CODE (newpat) == PARALLEL)
1416 rtvec old = XVEC (newpat, 0);
1417 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
1418 newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets));
1419 bcopy (&old->elem[0], &XVECEXP (newpat, 0, 0),
1420 sizeof (old->elem[0]) * old->num_elem);
1425 total_sets = 1 + added_sets_1 + added_sets_2;
1426 newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets));
1427 XVECEXP (newpat, 0, 0) = old;
1431 XVECEXP (newpat, 0, --total_sets)
1432 = (GET_CODE (PATTERN (i1)) == PARALLEL
1433 ? gen_rtx (SET, VOIDmode, i1dest, i1src) : PATTERN (i1));
1437 /* If there is no I1, use I2's body as is. We used to also not do
1438 the subst call below if I2 was substituted into I3,
1439 but that could lose a simplification. */
1441 XVECEXP (newpat, 0, --total_sets) = i2pat;
1443 /* See comment where i2pat is assigned. */
1444 XVECEXP (newpat, 0, --total_sets)
1445 = subst (i2pat, i1dest, i1src, 0, 0);
1449 /* We come here when we are replacing a destination in I2 with the
1450 destination of I3. */
1451 validate_replacement:
1453 /* Is the result of combination a valid instruction? */
1454 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1456 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
1457 the second SET's destination is a register that is unused. In that case,
1458 we just need the first SET. This can occur when simplifying a divmod
1459 insn. We *must* test for this case here because the code below that
1460 splits two independent SETs doesn't handle this case correctly when it
1461 updates the register status. Also check the case where the first
1462 SET's destination is unused. That would not cause incorrect code, but
1463 does cause an unneeded insn to remain. */
1465 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1466 && XVECLEN (newpat, 0) == 2
1467 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1468 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1469 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
1470 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
1471 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
1472 && asm_noperands (newpat) < 0)
1474 newpat = XVECEXP (newpat, 0, 0);
1475 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1478 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1479 && XVECLEN (newpat, 0) == 2
1480 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1481 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1482 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
1483 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
1484 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
1485 && asm_noperands (newpat) < 0)
1487 newpat = XVECEXP (newpat, 0, 1);
1488 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1491 /* See if this is an XOR. If so, perhaps the problem is that the
1492 constant is out of range. Replace it with a complemented XOR with
1493 a complemented constant; it might be in range. */
1495 else if (insn_code_number < 0 && GET_CODE (newpat) == SET
1496 && GET_CODE (SET_SRC (newpat)) == XOR
1497 && GET_CODE (XEXP (SET_SRC (newpat), 1)) == CONST_INT
1498 && ((temp = simplify_unary_operation (NOT,
1499 GET_MODE (SET_SRC (newpat)),
1500 XEXP (SET_SRC (newpat), 1),
1501 GET_MODE (SET_SRC (newpat))))
1504 enum machine_mode i_mode = GET_MODE (SET_SRC (newpat));
1506 = gen_rtx_combine (SET, VOIDmode, SET_DEST (newpat),
1507 gen_unary (NOT, i_mode,
1508 gen_binary (XOR, i_mode,
1509 XEXP (SET_SRC (newpat), 0),
1512 insn_code_number = recog_for_combine (&pat, i3, &new_i3_notes);
1513 if (insn_code_number >= 0)
1517 /* If we were combining three insns and the result is a simple SET
1518 with no ASM_OPERANDS that wasn't recognized, try to split it into two
1519 insns. There are two ways to do this. It can be split using a
1520 machine-specific method (like when you have an addition of a large
1521 constant) or by combine in the function find_split_point. */
1523 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
1524 && asm_noperands (newpat) < 0)
1526 rtx m_split, *split;
1527 rtx ni2dest = i2dest;
1529 /* See if the MD file can split NEWPAT. If it can't, see if letting it
1530 use I2DEST as a scratch register will help. In the latter case,
1531 convert I2DEST to the mode of the source of NEWPAT if we can. */
1533 m_split = split_insns (newpat, i3);
1536 /* If I2DEST is a hard register or the only use of a pseudo,
1537 we can change its mode. */
1538 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
1539 && GET_MODE (SET_DEST (newpat)) != VOIDmode
1540 && GET_CODE (i2dest) == REG
1541 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
1542 || (reg_n_sets[REGNO (i2dest)] == 1 && ! added_sets_2
1543 && ! REG_USERVAR_P (i2dest))))
1544 ni2dest = gen_rtx (REG, GET_MODE (SET_DEST (newpat)),
1547 m_split = split_insns (gen_rtx (PARALLEL, VOIDmode,
1548 gen_rtvec (2, newpat,
1555 if (m_split && GET_CODE (m_split) == SEQUENCE
1556 && XVECLEN (m_split, 0) == 2
1557 && (next_real_insn (i2) == i3
1558 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)),
1562 rtx newi3pat = PATTERN (XVECEXP (m_split, 0, 1));
1563 newi2pat = PATTERN (XVECEXP (m_split, 0, 0));
1565 i3set = single_set (XVECEXP (m_split, 0, 1));
1566 i2set = single_set (XVECEXP (m_split, 0, 0));
1568 /* In case we changed the mode of I2DEST, replace it in the
1569 pseudo-register table here. We can't do it above in case this
1570 code doesn't get executed and we do a split the other way. */
1572 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
1573 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
1575 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1577 /* If I2 or I3 has multiple SETs, we won't know how to track
1578 register status, so don't use these insns. */
1580 if (i2_code_number >= 0 && i2set && i3set)
1581 insn_code_number = recog_for_combine (&newi3pat, i3,
1584 if (insn_code_number >= 0)
1587 /* It is possible that both insns now set the destination of I3.
1588 If so, we must show an extra use of it. */
1590 if (insn_code_number >= 0 && GET_CODE (SET_DEST (i3set)) == REG
1591 && GET_CODE (SET_DEST (i2set)) == REG
1592 && REGNO (SET_DEST (i3set)) == REGNO (SET_DEST (i2set)))
1593 reg_n_sets[REGNO (SET_DEST (i2set))]++;
1596 /* If we can split it and use I2DEST, go ahead and see if that
1597 helps things be recognized. Verify that none of the registers
1598 are set between I2 and I3. */
1599 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
1601 && GET_CODE (i2dest) == REG
1603 /* We need I2DEST in the proper mode. If it is a hard register
1604 or the only use of a pseudo, we can change its mode. */
1605 && (GET_MODE (*split) == GET_MODE (i2dest)
1606 || GET_MODE (*split) == VOIDmode
1607 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
1608 || (reg_n_sets[REGNO (i2dest)] == 1 && ! added_sets_2
1609 && ! REG_USERVAR_P (i2dest)))
1610 && (next_real_insn (i2) == i3
1611 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
1612 /* We can't overwrite I2DEST if its value is still used by
1614 && ! reg_referenced_p (i2dest, newpat))
1616 rtx newdest = i2dest;
1618 /* Get NEWDEST as a register in the proper mode. We have already
1619 validated that we can do this. */
1620 if (GET_MODE (i2dest) != GET_MODE (*split)
1621 && GET_MODE (*split) != VOIDmode)
1623 newdest = gen_rtx (REG, GET_MODE (*split), REGNO (i2dest));
1625 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
1626 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
1629 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
1630 an ASHIFT. This can occur if it was inside a PLUS and hence
1631 appeared to be a memory address. This is a kludge. */
1632 if (GET_CODE (*split) == MULT
1633 && GET_CODE (XEXP (*split, 1)) == CONST_INT
1634 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
1635 SUBST (*split, gen_rtx_combine (ASHIFT, GET_MODE (*split),
1636 XEXP (*split, 0), GEN_INT (i)));
1638 #ifdef INSN_SCHEDULING
1639 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
1640 be written as a ZERO_EXTEND. */
1641 if (GET_CODE (*split) == SUBREG
1642 && GET_CODE (SUBREG_REG (*split)) == MEM)
1643 SUBST (*split, gen_rtx_combine (ZERO_EXTEND, GET_MODE (*split),
1647 newi2pat = gen_rtx_combine (SET, VOIDmode, newdest, *split);
1648 SUBST (*split, newdest);
1649 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1650 if (i2_code_number >= 0)
1651 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1655 /* Check for a case where we loaded from memory in a narrow mode and
1656 then sign extended it, but we need both registers. In that case,
1657 we have a PARALLEL with both loads from the same memory location.
1658 We can split this into a load from memory followed by a register-register
1659 copy. This saves at least one insn, more if register allocation can
1660 eliminate the copy. */
1662 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
1663 && GET_CODE (newpat) == PARALLEL
1664 && XVECLEN (newpat, 0) == 2
1665 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1666 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
1667 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1668 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1669 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
1670 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1672 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
1673 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
1674 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
1675 SET_SRC (XVECEXP (newpat, 0, 1)))
1676 && ! find_reg_note (i3, REG_UNUSED,
1677 SET_DEST (XVECEXP (newpat, 0, 0))))
1681 newi2pat = XVECEXP (newpat, 0, 0);
1682 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
1683 newpat = XVECEXP (newpat, 0, 1);
1684 SUBST (SET_SRC (newpat),
1685 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
1686 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1687 if (i2_code_number >= 0)
1688 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1690 if (insn_code_number >= 0)
1695 /* If we will be able to accept this, we have made a change to the
1696 destination of I3. This can invalidate a LOG_LINKS pointing
1697 to I3. No other part of combine.c makes such a transformation.
1699 The new I3 will have a destination that was previously the
1700 destination of I1 or I2 and which was used in i2 or I3. Call
1701 distribute_links to make a LOG_LINK from the next use of
1702 that destination. */
1704 PATTERN (i3) = newpat;
1705 distribute_links (gen_rtx (INSN_LIST, VOIDmode, i3, NULL_RTX));
1707 /* I3 now uses what used to be its destination and which is
1708 now I2's destination. That means we need a LOG_LINK from
1709 I3 to I2. But we used to have one, so we still will.
1711 However, some later insn might be using I2's dest and have
1712 a LOG_LINK pointing at I3. We must remove this link.
1713 The simplest way to remove the link is to point it at I1,
1714 which we know will be a NOTE. */
1716 for (insn = NEXT_INSN (i3);
1717 insn && GET_CODE (insn) != CODE_LABEL
1718 && GET_CODE (PREV_INSN (insn)) != JUMP_INSN;
1719 insn = NEXT_INSN (insn))
1721 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
1722 && reg_referenced_p (ni2dest, PATTERN (insn)))
1724 for (link = LOG_LINKS (insn); link;
1725 link = XEXP (link, 1))
1726 if (XEXP (link, 0) == i3)
1727 XEXP (link, 0) = i1;
1735 /* Similarly, check for a case where we have a PARALLEL of two independent
1736 SETs but we started with three insns. In this case, we can do the sets
1737 as two separate insns. This case occurs when some SET allows two
1738 other insns to combine, but the destination of that SET is still live. */
1740 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
1741 && GET_CODE (newpat) == PARALLEL
1742 && XVECLEN (newpat, 0) == 2
1743 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1744 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
1745 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
1746 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1747 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
1748 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
1749 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1751 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
1752 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
1753 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
1754 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
1755 XVECEXP (newpat, 0, 0))
1756 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
1757 XVECEXP (newpat, 0, 1)))
1759 newi2pat = XVECEXP (newpat, 0, 1);
1760 newpat = XVECEXP (newpat, 0, 0);
1762 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1763 if (i2_code_number >= 0)
1764 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1767 /* If it still isn't recognized, fail and change things back the way they
1769 if ((insn_code_number < 0
1770 /* Is the result a reasonable ASM_OPERANDS? */
1771 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
1777 /* If we had to change another insn, make sure it is valid also. */
1778 if (undobuf.other_insn)
1780 rtx other_notes = REG_NOTES (undobuf.other_insn);
1781 rtx other_pat = PATTERN (undobuf.other_insn);
1782 rtx new_other_notes;
1785 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
1788 if (other_code_number < 0 && ! check_asm_operands (other_pat))
1794 PATTERN (undobuf.other_insn) = other_pat;
1796 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
1797 are still valid. Then add any non-duplicate notes added by
1798 recog_for_combine. */
1799 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
1801 next = XEXP (note, 1);
1803 if (REG_NOTE_KIND (note) == REG_UNUSED
1804 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
1806 if (GET_CODE (XEXP (note, 0)) == REG)
1807 reg_n_deaths[REGNO (XEXP (note, 0))]--;
1809 remove_note (undobuf.other_insn, note);
1813 for (note = new_other_notes; note; note = XEXP (note, 1))
1814 if (GET_CODE (XEXP (note, 0)) == REG)
1815 reg_n_deaths[REGNO (XEXP (note, 0))]++;
1817 distribute_notes (new_other_notes, undobuf.other_insn,
1818 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
1821 /* We now know that we can do this combination. Merge the insns and
1822 update the status of registers and LOG_LINKS. */
1825 rtx i3notes, i2notes, i1notes = 0;
1826 rtx i3links, i2links, i1links = 0;
1828 int all_adjacent = (next_real_insn (i2) == i3
1829 && (i1 == 0 || next_real_insn (i1) == i2));
1831 /* Compute which registers we expect to eliminate. */
1832 rtx elim_i2 = (newi2pat || i2dest_in_i2src || i2dest_in_i1src
1834 rtx elim_i1 = i1 == 0 || i1dest_in_i1src ? 0 : i1dest;
1836 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
1838 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
1839 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
1841 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
1843 /* Ensure that we do not have something that should not be shared but
1844 occurs multiple times in the new insns. Check this by first
1845 resetting all the `used' flags and then copying anything is shared. */
1847 reset_used_flags (i3notes);
1848 reset_used_flags (i2notes);
1849 reset_used_flags (i1notes);
1850 reset_used_flags (newpat);
1851 reset_used_flags (newi2pat);
1852 if (undobuf.other_insn)
1853 reset_used_flags (PATTERN (undobuf.other_insn));
1855 i3notes = copy_rtx_if_shared (i3notes);
1856 i2notes = copy_rtx_if_shared (i2notes);
1857 i1notes = copy_rtx_if_shared (i1notes);
1858 newpat = copy_rtx_if_shared (newpat);
1859 newi2pat = copy_rtx_if_shared (newi2pat);
1860 if (undobuf.other_insn)
1861 reset_used_flags (PATTERN (undobuf.other_insn));
1863 INSN_CODE (i3) = insn_code_number;
1864 PATTERN (i3) = newpat;
1865 if (undobuf.other_insn)
1866 INSN_CODE (undobuf.other_insn) = other_code_number;
1868 /* We had one special case above where I2 had more than one set and
1869 we replaced a destination of one of those sets with the destination
1870 of I3. In that case, we have to update LOG_LINKS of insns later
1871 in this basic block. Note that this (expensive) case is rare. */
1873 if (GET_CODE (PATTERN (i2)) == PARALLEL)
1874 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
1875 if (GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
1876 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
1877 && ! find_reg_note (i2, REG_UNUSED,
1878 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
1882 for (insn = NEXT_INSN (i2); insn; insn = NEXT_INSN (insn))
1884 if (insn != i3 && GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1885 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
1886 if (XEXP (link, 0) == i2)
1887 XEXP (link, 0) = i3;
1889 if (GET_CODE (insn) == CODE_LABEL
1890 || GET_CODE (insn) == JUMP_INSN)
1902 INSN_CODE (i2) = i2_code_number;
1903 PATTERN (i2) = newi2pat;
1907 PUT_CODE (i2, NOTE);
1908 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
1909 NOTE_SOURCE_FILE (i2) = 0;
1916 PUT_CODE (i1, NOTE);
1917 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
1918 NOTE_SOURCE_FILE (i1) = 0;
1921 /* Get death notes for everything that is now used in either I3 or
1922 I2 and used to die in a previous insn. */
1924 move_deaths (newpat, i1 ? INSN_CUID (i1) : INSN_CUID (i2), i3, &midnotes);
1926 move_deaths (newi2pat, INSN_CUID (i1), i2, &midnotes);
1928 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
1930 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
1933 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
1936 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
1939 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
1942 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
1943 know these are REG_UNUSED and want them to go to the desired insn,
1944 so we always pass it as i3. We have not counted the notes in
1945 reg_n_deaths yet, so we need to do so now. */
1947 if (newi2pat && new_i2_notes)
1949 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
1950 if (GET_CODE (XEXP (temp, 0)) == REG)
1951 reg_n_deaths[REGNO (XEXP (temp, 0))]++;
1953 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
1958 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
1959 if (GET_CODE (XEXP (temp, 0)) == REG)
1960 reg_n_deaths[REGNO (XEXP (temp, 0))]++;
1962 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
1965 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
1966 put a REG_DEAD note for it somewhere. Similarly for I2 and I1.
1967 Show an additional death due to the REG_DEAD note we make here. If
1968 we discard it in distribute_notes, we will decrement it again. */
1972 if (GET_CODE (i3dest_killed) == REG)
1973 reg_n_deaths[REGNO (i3dest_killed)]++;
1975 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i3dest_killed,
1977 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
1978 NULL_RTX, NULL_RTX);
1981 /* For I2 and I1, we have to be careful. If NEWI2PAT exists and sets
1982 I2DEST or I1DEST, the death must be somewhere before I2, not I3. If
1983 we passed I3 in that case, it might delete I2. */
1985 if (i2dest_in_i2src)
1987 if (GET_CODE (i2dest) == REG)
1988 reg_n_deaths[REGNO (i2dest)]++;
1990 if (newi2pat && reg_set_p (i2dest, newi2pat))
1991 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i2dest, NULL_RTX),
1992 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
1994 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i2dest, NULL_RTX),
1995 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
1996 NULL_RTX, NULL_RTX);
1999 if (i1dest_in_i1src)
2001 if (GET_CODE (i1dest) == REG)
2002 reg_n_deaths[REGNO (i1dest)]++;
2004 if (newi2pat && reg_set_p (i1dest, newi2pat))
2005 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i1dest, NULL_RTX),
2006 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2008 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i1dest, NULL_RTX),
2009 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2010 NULL_RTX, NULL_RTX);
2013 distribute_links (i3links);
2014 distribute_links (i2links);
2015 distribute_links (i1links);
2017 if (GET_CODE (i2dest) == REG)
2020 rtx i2_insn = 0, i2_val = 0, set;
2022 /* The insn that used to set this register doesn't exist, and
2023 this life of the register may not exist either. See if one of
2024 I3's links points to an insn that sets I2DEST. If it does,
2025 that is now the last known value for I2DEST. If we don't update
2026 this and I2 set the register to a value that depended on its old
2027 contents, we will get confused. If this insn is used, thing
2028 will be set correctly in combine_instructions. */
2030 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2031 if ((set = single_set (XEXP (link, 0))) != 0
2032 && rtx_equal_p (i2dest, SET_DEST (set)))
2033 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2035 record_value_for_reg (i2dest, i2_insn, i2_val);
2037 /* If the reg formerly set in I2 died only once and that was in I3,
2038 zero its use count so it won't make `reload' do any work. */
2039 if (! added_sets_2 && newi2pat == 0)
2041 regno = REGNO (i2dest);
2042 reg_n_sets[regno]--;
2043 if (reg_n_sets[regno] == 0
2044 && ! (basic_block_live_at_start[0][regno / REGSET_ELT_BITS]
2045 & ((REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS))))
2046 reg_n_refs[regno] = 0;
2050 if (i1 && GET_CODE (i1dest) == REG)
2053 rtx i1_insn = 0, i1_val = 0, set;
2055 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2056 if ((set = single_set (XEXP (link, 0))) != 0
2057 && rtx_equal_p (i1dest, SET_DEST (set)))
2058 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2060 record_value_for_reg (i1dest, i1_insn, i1_val);
2062 regno = REGNO (i1dest);
2065 reg_n_sets[regno]--;
2066 if (reg_n_sets[regno] == 0
2067 && ! (basic_block_live_at_start[0][regno / REGSET_ELT_BITS]
2068 & ((REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS))))
2069 reg_n_refs[regno] = 0;
2073 /* Update reg_significant et al for any changes that may have been made
2076 note_stores (newpat, set_significant);
2078 note_stores (newi2pat, set_significant);
2080 /* If I3 is now an unconditional jump, ensure that it has a
2081 BARRIER following it since it may have initially been a
2082 conditional jump. */
2084 if ((GET_CODE (newpat) == RETURN || simplejump_p (i3))
2085 && GET_CODE (next_nonnote_insn (i3)) != BARRIER)
2086 emit_barrier_after (i3);
2089 combine_successes++;
2091 return newi2pat ? i2 : i3;
2094 /* Undo all the modifications recorded in undobuf. */
2100 if (undobuf.num_undo > MAX_UNDO)
2101 undobuf.num_undo = MAX_UNDO;
2102 for (i = undobuf.num_undo - 1; i >= 0; i--)
2104 if (undobuf.undo[i].is_int)
2105 *undobuf.undo[i].where.i = undobuf.undo[i].old_contents.i;
2107 *undobuf.undo[i].where.rtx = undobuf.undo[i].old_contents.rtx;
2111 obfree (undobuf.storage);
2112 undobuf.num_undo = 0;
2115 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2116 where we have an arithmetic expression and return that point. LOC will
2119 try_combine will call this function to see if an insn can be split into
2123 find_split_point (loc, insn)
2128 enum rtx_code code = GET_CODE (x);
2130 int len = 0, pos, unsignedp;
2133 /* First special-case some codes. */
2137 #ifdef INSN_SCHEDULING
2138 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2140 if (GET_CODE (SUBREG_REG (x)) == MEM)
2143 return find_split_point (&SUBREG_REG (x), insn);
2147 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2148 using LO_SUM and HIGH. */
2149 if (GET_CODE (XEXP (x, 0)) == CONST
2150 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2153 gen_rtx_combine (LO_SUM, Pmode,
2154 gen_rtx_combine (HIGH, Pmode, XEXP (x, 0)),
2156 return &XEXP (XEXP (x, 0), 0);
2160 /* If we have a PLUS whose second operand is a constant and the
2161 address is not valid, perhaps will can split it up using
2162 the machine-specific way to split large constants. We use
2163 the first psuedo-reg (one of the virtual regs) as a placeholder;
2164 it will not remain in the result. */
2165 if (GET_CODE (XEXP (x, 0)) == PLUS
2166 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2167 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2169 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2170 rtx seq = split_insns (gen_rtx (SET, VOIDmode, reg, XEXP (x, 0)),
2173 /* This should have produced two insns, each of which sets our
2174 placeholder. If the source of the second is a valid address,
2175 we can make put both sources together and make a split point
2178 if (seq && XVECLEN (seq, 0) == 2
2179 && GET_CODE (XVECEXP (seq, 0, 0)) == INSN
2180 && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET
2181 && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg
2182 && ! reg_mentioned_p (reg,
2183 SET_SRC (PATTERN (XVECEXP (seq, 0, 0))))
2184 && GET_CODE (XVECEXP (seq, 0, 1)) == INSN
2185 && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET
2186 && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg
2187 && memory_address_p (GET_MODE (x),
2188 SET_SRC (PATTERN (XVECEXP (seq, 0, 1)))))
2190 rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0)));
2191 rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1)));
2193 /* Replace the placeholder in SRC2 with SRC1. If we can
2194 find where in SRC2 it was placed, that can become our
2195 split point and we can replace this address with SRC2.
2196 Just try two obvious places. */
2198 src2 = replace_rtx (src2, reg, src1);
2200 if (XEXP (src2, 0) == src1)
2201 split = &XEXP (src2, 0);
2202 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2203 && XEXP (XEXP (src2, 0), 0) == src1)
2204 split = &XEXP (XEXP (src2, 0), 0);
2208 SUBST (XEXP (x, 0), src2);
2213 /* If that didn't work, perhaps the first operand is complex and
2214 needs to be computed separately, so make a split point there.
2215 This will occur on machines that just support REG + CONST
2216 and have a constant moved through some previous computation. */
2218 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
2219 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
2220 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
2222 return &XEXP (XEXP (x, 0), 0);
2228 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2229 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2230 we need to put the operand into a register. So split at that
2233 if (SET_DEST (x) == cc0_rtx
2234 && GET_CODE (SET_SRC (x)) != COMPARE
2235 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
2236 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
2237 && ! (GET_CODE (SET_SRC (x)) == SUBREG
2238 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
2239 return &SET_SRC (x);
2242 /* See if we can split SET_SRC as it stands. */
2243 split = find_split_point (&SET_SRC (x), insn);
2244 if (split && split != &SET_SRC (x))
2247 /* See if this is a bitfield assignment with everything constant. If
2248 so, this is an IOR of an AND, so split it into that. */
2249 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
2250 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
2251 <= HOST_BITS_PER_WIDE_INT)
2252 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
2253 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
2254 && GET_CODE (SET_SRC (x)) == CONST_INT
2255 && ((INTVAL (XEXP (SET_DEST (x), 1))
2256 + INTVAL (XEXP (SET_DEST (x), 2)))
2257 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
2258 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
2260 int pos = INTVAL (XEXP (SET_DEST (x), 2));
2261 int len = INTVAL (XEXP (SET_DEST (x), 1));
2262 int src = INTVAL (SET_SRC (x));
2263 rtx dest = XEXP (SET_DEST (x), 0);
2264 enum machine_mode mode = GET_MODE (dest);
2265 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
2268 pos = GET_MODE_BITSIZE (mode) - len - pos;
2273 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
2276 gen_binary (IOR, mode,
2277 gen_binary (AND, mode, dest,
2278 GEN_INT (~ (mask << pos)
2279 & GET_MODE_MASK (mode))),
2280 GEN_INT (src << pos)));
2282 SUBST (SET_DEST (x), dest);
2284 split = find_split_point (&SET_SRC (x), insn);
2285 if (split && split != &SET_SRC (x))
2289 /* Otherwise, see if this is an operation that we can split into two.
2290 If so, try to split that. */
2291 code = GET_CODE (SET_SRC (x));
2296 /* If we are AND'ing with a large constant that is only a single
2297 bit and the result is only being used in a context where we
2298 need to know if it is zero or non-zero, replace it with a bit
2299 extraction. This will avoid the large constant, which might
2300 have taken more than one insn to make. If the constant were
2301 not a valid argument to the AND but took only one insn to make,
2302 this is no worse, but if it took more than one insn, it will
2305 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2306 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
2307 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
2308 && GET_CODE (SET_DEST (x)) == REG
2309 && (split = find_single_use (SET_DEST (x), insn, NULL_PTR)) != 0
2310 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
2311 && XEXP (*split, 0) == SET_DEST (x)
2312 && XEXP (*split, 1) == const0_rtx)
2315 make_extraction (GET_MODE (SET_DEST (x)),
2316 XEXP (SET_SRC (x), 0),
2317 pos, NULL_RTX, 1, 1, 0, 0));
2318 return find_split_point (loc, insn);
2323 inner = XEXP (SET_SRC (x), 0);
2325 len = GET_MODE_BITSIZE (GET_MODE (inner));
2331 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2332 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
2334 inner = XEXP (SET_SRC (x), 0);
2335 len = INTVAL (XEXP (SET_SRC (x), 1));
2336 pos = INTVAL (XEXP (SET_SRC (x), 2));
2339 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
2341 unsignedp = (code == ZERO_EXTRACT);
2346 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
2348 enum machine_mode mode = GET_MODE (SET_SRC (x));
2350 /* For unsigned, we have a choice of a shift followed by an
2351 AND or two shifts. Use two shifts for field sizes where the
2352 constant might be too large. We assume here that we can
2353 always at least get 8-bit constants in an AND insn, which is
2354 true for every current RISC. */
2356 if (unsignedp && len <= 8)
2361 gen_rtx_combine (LSHIFTRT, mode,
2362 gen_lowpart_for_combine (mode, inner),
2364 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
2366 split = find_split_point (&SET_SRC (x), insn);
2367 if (split && split != &SET_SRC (x))
2374 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
2375 gen_rtx_combine (ASHIFT, mode,
2376 gen_lowpart_for_combine (mode, inner),
2377 GEN_INT (GET_MODE_BITSIZE (mode)
2379 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
2381 split = find_split_point (&SET_SRC (x), insn);
2382 if (split && split != &SET_SRC (x))
2387 /* See if this is a simple operation with a constant as the second
2388 operand. It might be that this constant is out of range and hence
2389 could be used as a split point. */
2390 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2391 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2392 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
2393 && CONSTANT_P (XEXP (SET_SRC (x), 1))
2394 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
2395 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
2396 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
2398 return &XEXP (SET_SRC (x), 1);
2400 /* Finally, see if this is a simple operation with its first operand
2401 not in a register. The operation might require this operand in a
2402 register, so return it as a split point. We can always do this
2403 because if the first operand were another operation, we would have
2404 already found it as a split point. */
2405 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2406 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2407 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
2408 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
2409 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
2410 return &XEXP (SET_SRC (x), 0);
2416 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
2417 it is better to write this as (not (ior A B)) so we can split it.
2418 Similarly for IOR. */
2419 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
2422 gen_rtx_combine (NOT, GET_MODE (x),
2423 gen_rtx_combine (code == IOR ? AND : IOR,
2425 XEXP (XEXP (x, 0), 0),
2426 XEXP (XEXP (x, 1), 0))));
2427 return find_split_point (loc, insn);
2430 /* Many RISC machines have a large set of logical insns. If the
2431 second operand is a NOT, put it first so we will try to split the
2432 other operand first. */
2433 if (GET_CODE (XEXP (x, 1)) == NOT)
2435 rtx tem = XEXP (x, 0);
2436 SUBST (XEXP (x, 0), XEXP (x, 1));
2437 SUBST (XEXP (x, 1), tem);
2442 /* Otherwise, select our actions depending on our rtx class. */
2443 switch (GET_RTX_CLASS (code))
2445 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
2447 split = find_split_point (&XEXP (x, 2), insn);
2450 /* ... fall through ... */
2454 split = find_split_point (&XEXP (x, 1), insn);
2457 /* ... fall through ... */
2459 /* Some machines have (and (shift ...) ...) insns. If X is not
2460 an AND, but XEXP (X, 0) is, use it as our split point. */
2461 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
2462 return &XEXP (x, 0);
2464 split = find_split_point (&XEXP (x, 0), insn);
2470 /* Otherwise, we don't have a split point. */
2474 /* Throughout X, replace FROM with TO, and return the result.
2475 The result is TO if X is FROM;
2476 otherwise the result is X, but its contents may have been modified.
2477 If they were modified, a record was made in undobuf so that
2478 undo_all will (among other things) return X to its original state.
2480 If the number of changes necessary is too much to record to undo,
2481 the excess changes are not made, so the result is invalid.
2482 The changes already made can still be undone.
2483 undobuf.num_undo is incremented for such changes, so by testing that
2484 the caller can tell whether the result is valid.
2486 `n_occurrences' is incremented each time FROM is replaced.
2488 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
2490 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
2491 by copying if `n_occurrences' is non-zero. */
2494 subst (x, from, to, in_dest, unique_copy)
2495 register rtx x, from, to;
2500 register int len, i;
2501 register enum rtx_code code = GET_CODE (x), orig_code = code;
2503 enum machine_mode mode = GET_MODE (x);
2504 enum machine_mode op0_mode = VOIDmode;
2509 /* FAKE_EXTEND_SAFE_P (MODE, FROM) is 1 if (subreg:MODE FROM 0) is a safe
2510 replacement for (zero_extend:MODE FROM) or (sign_extend:MODE FROM).
2511 If it is 0, that cannot be done. We can now do this for any MEM
2512 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be reloaded.
2513 If not for that, MEM's would very rarely be safe. */
2515 /* Reject MODEs bigger than a word, because we might not be able
2516 to reference a two-register group starting with an arbitrary register
2517 (and currently gen_lowpart might crash for a SUBREG). */
2519 #define FAKE_EXTEND_SAFE_P(MODE, FROM) \
2520 (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD)
2522 /* Two expressions are equal if they are identical copies of a shared
2523 RTX or if they are both registers with the same register number
2526 #define COMBINE_RTX_EQUAL_P(X,Y) \
2528 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
2529 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
2531 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
2534 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
2537 /* If X and FROM are the same register but different modes, they will
2538 not have been seen as equal above. However, flow.c will make a
2539 LOG_LINKS entry for that case. If we do nothing, we will try to
2540 rerecognize our original insn and, when it succeeds, we will
2541 delete the feeding insn, which is incorrect.
2543 So force this insn not to match in this (rare) case. */
2544 if (! in_dest && code == REG && GET_CODE (from) == REG
2545 && REGNO (x) == REGNO (from))
2546 return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
2548 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
2549 of which may contain things that can be combined. */
2550 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
2553 /* It is possible to have a subexpression appear twice in the insn.
2554 Suppose that FROM is a register that appears within TO.
2555 Then, after that subexpression has been scanned once by `subst',
2556 the second time it is scanned, TO may be found. If we were
2557 to scan TO here, we would find FROM within it and create a
2558 self-referent rtl structure which is completely wrong. */
2559 if (COMBINE_RTX_EQUAL_P (x, to))
2562 len = GET_RTX_LENGTH (code);
2563 fmt = GET_RTX_FORMAT (code);
2565 /* We don't need to process a SET_DEST that is a register, CC0, or PC, so
2566 set up to skip this common case. All other cases where we want to
2567 suppress replacing something inside a SET_SRC are handled via the
2570 && (GET_CODE (SET_DEST (x)) == REG
2571 || GET_CODE (SET_DEST (x)) == CC0
2572 || GET_CODE (SET_DEST (x)) == PC))
2575 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a constant. */
2577 op0_mode = GET_MODE (XEXP (x, 0));
2579 for (i = 0; i < len; i++)
2584 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2587 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
2589 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
2594 new = subst (XVECEXP (x, i, j), from, to, 0, unique_copy);
2596 /* If this substitution failed, this whole thing fails. */
2597 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
2601 SUBST (XVECEXP (x, i, j), new);
2604 else if (fmt[i] == 'e')
2608 if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
2610 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
2614 /* If we are in a SET_DEST, suppress most cases unless we
2615 have gone inside a MEM, in which case we want to
2616 simplify the address. We assume here that things that
2617 are actually part of the destination have their inner
2618 parts in the first expression. This is true for SUBREG,
2619 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
2620 things aside from REG and MEM that should appear in a
2622 new = subst (XEXP (x, i), from, to,
2624 && (code == SUBREG || code == STRICT_LOW_PART
2625 || code == ZERO_EXTRACT))
2627 && i == 0), unique_copy);
2629 /* If we found that we will have to reject this combination,
2630 indicate that by returning the CLOBBER ourselves, rather than
2631 an expression containing it. This will speed things up as
2632 well as prevent accidents where two CLOBBERs are considered
2633 to be equal, thus producing an incorrect simplification. */
2635 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
2638 SUBST (XEXP (x, i), new);
2642 /* We come back to here if we have replaced the expression with one of
2643 a different code and it is likely that further simplification will be
2648 /* If we have restarted more than 4 times, we are probably looping, so
2650 if (++n_restarts > 4)
2653 /* If we are restarting at all, it means that we no longer know the
2654 original mode of operand 0 (since we have probably changed the
2658 op0_mode = VOIDmode;
2660 code = GET_CODE (x);
2662 /* If this is a commutative operation, put a constant last and a complex
2663 expression first. We don't need to do this for comparisons here. */
2664 if (GET_RTX_CLASS (code) == 'c'
2665 && ((CONSTANT_P (XEXP (x, 0)) && GET_CODE (XEXP (x, 1)) != CONST_INT)
2666 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == 'o'
2667 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')
2668 || (GET_CODE (XEXP (x, 0)) == SUBREG
2669 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o'
2670 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')))
2673 SUBST (XEXP (x, 0), XEXP (x, 1));
2674 SUBST (XEXP (x, 1), temp);
2677 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
2678 sign extension of a PLUS with a constant, reverse the order of the sign
2679 extension and the addition. Note that this not the same as the original
2680 code, but overflow is undefined for signed values. Also note that the
2681 PLUS will have been partially moved "inside" the sign-extension, so that
2682 the first operand of X will really look like:
2683 (ashiftrt (plus (ashift A C4) C5) C4).
2685 (plus (ashiftrt (ashift A C4) C2) C4)
2686 and replace the first operand of X with that expression. Later parts
2687 of this function may simplify the expression further.
2689 For example, if we start with (mult (sign_extend (plus A C1)) C2),
2690 we swap the SIGN_EXTEND and PLUS. Later code will apply the
2691 distributive law to produce (plus (mult (sign_extend X) C1) C3).
2693 We do this to simplify address expressions. */
2695 if ((code == PLUS || code == MINUS || code == MULT)
2696 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
2697 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
2698 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
2699 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
2700 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2701 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
2702 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
2703 && (temp = simplify_binary_operation (ASHIFTRT, mode,
2704 XEXP (XEXP (XEXP (x, 0), 0), 1),
2705 XEXP (XEXP (x, 0), 1))) != 0)
2708 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
2709 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
2710 INTVAL (XEXP (XEXP (x, 0), 1)));
2712 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
2713 INTVAL (XEXP (XEXP (x, 0), 1)));
2715 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
2718 /* If this is a simple operation applied to an IF_THEN_ELSE, try
2719 applying it to the arms of the IF_THEN_ELSE. This often simplifies
2720 things. Don't deal with operations that change modes here. */
2722 if ((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c')
2723 && GET_CODE (XEXP (x, 0)) == IF_THEN_ELSE)
2725 /* Don't do this by using SUBST inside X since we might be messing
2726 up a shared expression. */
2727 rtx cond = XEXP (XEXP (x, 0), 0);
2728 rtx t_arm = subst (gen_binary (code, mode, XEXP (XEXP (x, 0), 1),
2730 pc_rtx, pc_rtx, 0, 0);
2731 rtx f_arm = subst (gen_binary (code, mode, XEXP (XEXP (x, 0), 2),
2733 pc_rtx, pc_rtx, 0, 0);
2736 x = gen_rtx (IF_THEN_ELSE, mode, cond, t_arm, f_arm);
2740 else if (GET_RTX_CLASS (code) == '1'
2741 && GET_CODE (XEXP (x, 0)) == IF_THEN_ELSE
2742 && GET_MODE (XEXP (x, 0)) == mode)
2744 rtx cond = XEXP (XEXP (x, 0), 0);
2745 rtx t_arm = subst (gen_unary (code, mode, XEXP (XEXP (x, 0), 1)),
2746 pc_rtx, pc_rtx, 0, 0);
2747 rtx f_arm = subst (gen_unary (code, mode, XEXP (XEXP (x, 0), 2)),
2748 pc_rtx, pc_rtx, 0, 0);
2750 x = gen_rtx_combine (IF_THEN_ELSE, mode, cond, t_arm, f_arm);
2754 /* Try to fold this expression in case we have constants that weren't
2757 switch (GET_RTX_CLASS (code))
2760 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
2763 temp = simplify_relational_operation (code, op0_mode,
2764 XEXP (x, 0), XEXP (x, 1));
2765 #ifdef FLOAT_STORE_FLAG_VALUE
2766 if (temp != 0 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2767 temp = ((temp == const0_rtx) ? CONST0_RTX (GET_MODE (x))
2768 : immed_real_const_1 (FLOAT_STORE_FLAG_VALUE, GET_MODE (x)));
2773 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
2777 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
2778 XEXP (x, 1), XEXP (x, 2));
2783 x = temp, code = GET_CODE (temp);
2785 /* First see if we can apply the inverse distributive law. */
2786 if (code == PLUS || code == MINUS || code == IOR || code == XOR)
2788 x = apply_distributive_law (x);
2789 code = GET_CODE (x);
2792 /* If CODE is an associative operation not otherwise handled, see if we
2793 can associate some operands. This can win if they are constants or
2794 if they are logically related (i.e. (a & b) & a. */
2795 if ((code == PLUS || code == MINUS
2796 || code == MULT || code == AND || code == IOR || code == XOR
2797 || code == DIV || code == UDIV
2798 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
2799 && GET_MODE_CLASS (mode) == MODE_INT)
2801 if (GET_CODE (XEXP (x, 0)) == code)
2803 rtx other = XEXP (XEXP (x, 0), 0);
2804 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
2805 rtx inner_op1 = XEXP (x, 1);
2808 /* Make sure we pass the constant operand if any as the second
2809 one if this is a commutative operation. */
2810 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
2812 rtx tem = inner_op0;
2813 inner_op0 = inner_op1;
2816 inner = simplify_binary_operation (code == MINUS ? PLUS
2817 : code == DIV ? MULT
2818 : code == UDIV ? MULT
2820 mode, inner_op0, inner_op1);
2822 /* For commutative operations, try the other pair if that one
2824 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
2826 other = XEXP (XEXP (x, 0), 1);
2827 inner = simplify_binary_operation (code, mode,
2828 XEXP (XEXP (x, 0), 0),
2834 x = gen_binary (code, mode, other, inner);
2841 /* A little bit of algebraic simplification here. */
2845 /* Ensure that our address has any ASHIFTs converted to MULT in case
2846 address-recognizing predicates are called later. */
2847 temp = make_compound_operation (XEXP (x, 0), MEM);
2848 SUBST (XEXP (x, 0), temp);
2852 /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG
2853 is paradoxical. If we can't do that safely, then it becomes
2854 something nonsensical so that this combination won't take place. */
2856 if (GET_CODE (SUBREG_REG (x)) == MEM
2857 && (GET_MODE_SIZE (mode)
2858 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
2860 rtx inner = SUBREG_REG (x);
2861 int endian_offset = 0;
2862 /* Don't change the mode of the MEM
2863 if that would change the meaning of the address. */
2864 if (MEM_VOLATILE_P (SUBREG_REG (x))
2865 || mode_dependent_address_p (XEXP (inner, 0)))
2866 return gen_rtx (CLOBBER, mode, const0_rtx);
2868 #if BYTES_BIG_ENDIAN
2869 if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
2870 endian_offset += UNITS_PER_WORD - GET_MODE_SIZE (mode);
2871 if (GET_MODE_SIZE (GET_MODE (inner)) < UNITS_PER_WORD)
2872 endian_offset -= UNITS_PER_WORD - GET_MODE_SIZE (GET_MODE (inner));
2874 /* Note if the plus_constant doesn't make a valid address
2875 then this combination won't be accepted. */
2876 x = gen_rtx (MEM, mode,
2877 plus_constant (XEXP (inner, 0),
2878 (SUBREG_WORD (x) * UNITS_PER_WORD
2880 MEM_VOLATILE_P (x) = MEM_VOLATILE_P (inner);
2881 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (inner);
2882 MEM_IN_STRUCT_P (x) = MEM_IN_STRUCT_P (inner);
2886 /* If we are in a SET_DEST, these other cases can't apply. */
2890 /* Changing mode twice with SUBREG => just change it once,
2891 or not at all if changing back to starting mode. */
2892 if (GET_CODE (SUBREG_REG (x)) == SUBREG)
2894 if (mode == GET_MODE (SUBREG_REG (SUBREG_REG (x)))
2895 && SUBREG_WORD (x) == 0 && SUBREG_WORD (SUBREG_REG (x)) == 0)
2896 return SUBREG_REG (SUBREG_REG (x));
2898 SUBST_INT (SUBREG_WORD (x),
2899 SUBREG_WORD (x) + SUBREG_WORD (SUBREG_REG (x)));
2900 SUBST (SUBREG_REG (x), SUBREG_REG (SUBREG_REG (x)));
2903 /* SUBREG of a hard register => just change the register number
2904 and/or mode. If the hard register is not valid in that mode,
2905 suppress this combination. If the hard register is the stack,
2906 frame, or argument pointer, leave this as a SUBREG. */
2908 if (GET_CODE (SUBREG_REG (x)) == REG
2909 && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER
2910 && REGNO (SUBREG_REG (x)) != FRAME_POINTER_REGNUM
2911 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
2912 && REGNO (SUBREG_REG (x)) != ARG_POINTER_REGNUM
2914 && REGNO (SUBREG_REG (x)) != STACK_POINTER_REGNUM)
2916 if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x)) + SUBREG_WORD (x),
2918 return gen_rtx (REG, mode,
2919 REGNO (SUBREG_REG (x)) + SUBREG_WORD (x));
2921 return gen_rtx (CLOBBER, mode, const0_rtx);
2924 /* For a constant, try to pick up the part we want. Handle a full
2925 word and low-order part. Only do this if we are narrowing
2926 the constant; if it is being widened, we have no idea what
2927 the extra bits will have been set to. */
2929 if (CONSTANT_P (SUBREG_REG (x)) && op0_mode != VOIDmode
2930 && GET_MODE_SIZE (mode) == UNITS_PER_WORD
2931 && GET_MODE_SIZE (op0_mode) < UNITS_PER_WORD
2932 && GET_MODE_CLASS (mode) == MODE_INT)
2934 temp = operand_subword (SUBREG_REG (x), SUBREG_WORD (x),
2940 if (CONSTANT_P (SUBREG_REG (x)) && subreg_lowpart_p (x)
2941 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (op0_mode))
2942 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
2944 /* If we are narrowing the object, we need to see if we can simplify
2945 the expression for the object knowing that we only need the
2948 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))
2949 && subreg_lowpart_p (x))
2950 return force_to_mode (SUBREG_REG (x), mode, GET_MODE_BITSIZE (mode),
2955 /* (not (plus X -1)) can become (neg X). */
2956 if (GET_CODE (XEXP (x, 0)) == PLUS
2957 && XEXP (XEXP (x, 0), 1) == constm1_rtx)
2959 x = gen_rtx_combine (NEG, mode, XEXP (XEXP (x, 0), 0));
2963 /* Similarly, (not (neg X)) is (plus X -1). */
2964 if (GET_CODE (XEXP (x, 0)) == NEG)
2966 x = gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
2970 /* (not (xor X C)) for C constant is (xor X D) with D = ~ C. */
2971 if (GET_CODE (XEXP (x, 0)) == XOR
2972 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2973 && (temp = simplify_unary_operation (NOT, mode,
2974 XEXP (XEXP (x, 0), 1),
2977 SUBST (XEXP (XEXP (x, 0), 1), temp);
2981 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
2982 other than 1, but that is not valid. We could do a similar
2983 simplification for (not (lshiftrt C X)) where C is just the sign bit,
2984 but this doesn't seem common enough to bother with. */
2985 if (GET_CODE (XEXP (x, 0)) == ASHIFT
2986 && XEXP (XEXP (x, 0), 0) == const1_rtx)
2988 x = gen_rtx (ROTATE, mode, gen_unary (NOT, mode, const1_rtx),
2989 XEXP (XEXP (x, 0), 1));
2993 if (GET_CODE (XEXP (x, 0)) == SUBREG
2994 && subreg_lowpart_p (XEXP (x, 0))
2995 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
2996 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
2997 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
2998 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3000 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3002 x = gen_rtx (ROTATE, inner_mode,
3003 gen_unary (NOT, inner_mode, const1_rtx),
3004 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3005 x = gen_lowpart_for_combine (mode, x);
3009 #if STORE_FLAG_VALUE == -1
3010 /* (not (comparison foo bar)) can be done by reversing the comparison
3012 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3013 && reversible_comparison_p (XEXP (x, 0)))
3014 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
3015 mode, XEXP (XEXP (x, 0), 0),
3016 XEXP (XEXP (x, 0), 1));
3019 /* Apply De Morgan's laws to reduce number of patterns for machines
3020 with negating logical insns (and-not, nand, etc.). If result has
3021 only one NOT, put it first, since that is how the patterns are
3024 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3026 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3028 if (GET_CODE (in1) == NOT)
3029 in1 = XEXP (in1, 0);
3031 in1 = gen_rtx_combine (NOT, GET_MODE (in1), in1);
3033 if (GET_CODE (in2) == NOT)
3034 in2 = XEXP (in2, 0);
3035 else if (GET_CODE (in2) == CONST_INT
3036 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3037 in2 = GEN_INT (GET_MODE_MASK (mode) & ~ INTVAL (in2));
3039 in2 = gen_rtx_combine (NOT, GET_MODE (in2), in2);
3041 if (GET_CODE (in2) == NOT)
3044 in2 = in1; in1 = tem;
3047 x = gen_rtx_combine (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3054 /* (neg (plus X 1)) can become (not X). */
3055 if (GET_CODE (XEXP (x, 0)) == PLUS
3056 && XEXP (XEXP (x, 0), 1) == const1_rtx)
3058 x = gen_rtx_combine (NOT, mode, XEXP (XEXP (x, 0), 0));
3062 /* Similarly, (neg (not X)) is (plus X 1). */
3063 if (GET_CODE (XEXP (x, 0)) == NOT)
3065 x = gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0), const1_rtx);
3069 /* (neg (minus X Y)) can become (minus Y X). */
3070 if (GET_CODE (XEXP (x, 0)) == MINUS
3071 && (GET_MODE_CLASS (mode) != MODE_FLOAT
3072 /* x-y != -(y-x) with IEEE floating point. */
3073 || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT))
3075 x = gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
3076 XEXP (XEXP (x, 0), 0));
3080 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3081 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
3082 && significant_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
3084 x = gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3088 /* NEG commutes with ASHIFT since it is multiplication. Only do this
3089 if we can then eliminate the NEG (e.g.,
3090 if the operand is a constant). */
3092 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
3094 temp = simplify_unary_operation (NEG, mode,
3095 XEXP (XEXP (x, 0), 0), mode);
3098 SUBST (XEXP (XEXP (x, 0), 0), temp);
3103 temp = expand_compound_operation (XEXP (x, 0));
3105 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3106 replaced by (lshiftrt X C). This will convert
3107 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3109 if (GET_CODE (temp) == ASHIFTRT
3110 && GET_CODE (XEXP (temp, 1)) == CONST_INT
3111 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
3113 x = simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
3114 INTVAL (XEXP (temp, 1)));
3118 /* If X has only a single bit significant, say, bit I, convert
3119 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3120 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
3121 (sign_extract X 1 Y). But only do this if TEMP isn't a register
3122 or a SUBREG of one since we'd be making the expression more
3123 complex if it was just a register. */
3125 if (GET_CODE (temp) != REG
3126 && ! (GET_CODE (temp) == SUBREG
3127 && GET_CODE (SUBREG_REG (temp)) == REG)
3128 && (i = exact_log2 (significant_bits (temp, mode))) >= 0)
3130 rtx temp1 = simplify_shift_const
3131 (NULL_RTX, ASHIFTRT, mode,
3132 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
3133 GET_MODE_BITSIZE (mode) - 1 - i),
3134 GET_MODE_BITSIZE (mode) - 1 - i);
3136 /* If all we did was surround TEMP with the two shifts, we
3137 haven't improved anything, so don't use it. Otherwise,
3138 we are better off with TEMP1. */
3139 if (GET_CODE (temp1) != ASHIFTRT
3140 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
3141 || XEXP (XEXP (temp1, 0), 0) != temp)
3149 case FLOAT_TRUNCATE:
3150 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
3151 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
3152 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
3153 return XEXP (XEXP (x, 0), 0);
3158 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
3159 using cc0, in which case we want to leave it as a COMPARE
3160 so we can distinguish it from a register-register-copy. */
3161 if (XEXP (x, 1) == const0_rtx)
3164 /* In IEEE floating point, x-0 is not the same as x. */
3165 if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3166 || GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) == MODE_INT)
3167 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
3173 /* (const (const X)) can become (const X). Do it this way rather than
3174 returning the inner CONST since CONST can be shared with a
3176 if (GET_CODE (XEXP (x, 0)) == CONST)
3177 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
3182 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
3183 can add in an offset. find_split_point will split this address up
3184 again if it doesn't match. */
3185 if (GET_CODE (XEXP (x, 0)) == HIGH
3186 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
3192 /* If we have (plus (plus (A const) B)), associate it so that CONST is
3193 outermost. That's because that's the way indexed addresses are
3194 supposed to appear. This code used to check many more cases, but
3195 they are now checked elsewhere. */
3196 if (GET_CODE (XEXP (x, 0)) == PLUS
3197 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
3198 return gen_binary (PLUS, mode,
3199 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
3201 XEXP (XEXP (x, 0), 1));
3203 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
3204 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
3205 bit-field and can be replaced by either a sign_extend or a
3206 sign_extract. The `and' may be a zero_extend. */
3207 if (GET_CODE (XEXP (x, 0)) == XOR
3208 && GET_CODE (XEXP (x, 1)) == CONST_INT
3209 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3210 && INTVAL (XEXP (x, 1)) == - INTVAL (XEXP (XEXP (x, 0), 1))
3211 && (i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
3212 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3213 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
3214 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3215 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
3216 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
3217 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
3218 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
3221 x = simplify_shift_const
3222 (NULL_RTX, ASHIFTRT, mode,
3223 simplify_shift_const (NULL_RTX, ASHIFT, mode,
3224 XEXP (XEXP (XEXP (x, 0), 0), 0),
3225 GET_MODE_BITSIZE (mode) - (i + 1)),
3226 GET_MODE_BITSIZE (mode) - (i + 1));
3230 /* If only the low-order bit of X is significant, (plus x -1)
3231 can become (ashiftrt (ashift (xor x 1) C) C) where C is
3232 the bitsize of the mode - 1. This allows simplification of
3233 "a = (b & 8) == 0;" */
3234 if (XEXP (x, 1) == constm1_rtx
3235 && GET_CODE (XEXP (x, 0)) != REG
3236 && ! (GET_CODE (XEXP (x,0)) == SUBREG
3237 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
3238 && significant_bits (XEXP (x, 0), mode) == 1)
3240 x = simplify_shift_const
3241 (NULL_RTX, ASHIFTRT, mode,
3242 simplify_shift_const (NULL_RTX, ASHIFT, mode,
3243 gen_rtx_combine (XOR, mode,
3244 XEXP (x, 0), const1_rtx),
3245 GET_MODE_BITSIZE (mode) - 1),
3246 GET_MODE_BITSIZE (mode) - 1);
3250 /* If we are adding two things that have no bits in common, convert
3251 the addition into an IOR. This will often be further simplified,
3252 for example in cases like ((a & 1) + (a & 2)), which can
3255 if ((significant_bits (XEXP (x, 0), mode)
3256 & significant_bits (XEXP (x, 1), mode)) == 0)
3258 x = gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
3264 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
3265 (and <foo> (const_int pow2-1)) */
3266 if (GET_CODE (XEXP (x, 1)) == AND
3267 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
3268 && exact_log2 (- INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
3269 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
3271 x = simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
3272 - INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
3278 /* If we have (mult (plus A B) C), apply the distributive law and then
3279 the inverse distributive law to see if things simplify. This
3280 occurs mostly in addresses, often when unrolling loops. */
3282 if (GET_CODE (XEXP (x, 0)) == PLUS)
3284 x = apply_distributive_law
3285 (gen_binary (PLUS, mode,
3286 gen_binary (MULT, mode,
3287 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
3288 gen_binary (MULT, mode,
3289 XEXP (XEXP (x, 0), 1), XEXP (x, 1))));
3291 if (GET_CODE (x) != MULT)
3295 /* If this is multiplication by a power of two and its first operand is
3296 a shift, treat the multiply as a shift to allow the shifts to
3297 possibly combine. */
3298 if (GET_CODE (XEXP (x, 1)) == CONST_INT
3299 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
3300 && (GET_CODE (XEXP (x, 0)) == ASHIFT
3301 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
3302 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
3303 || GET_CODE (XEXP (x, 0)) == ROTATE
3304 || GET_CODE (XEXP (x, 0)) == ROTATERT))
3306 x = simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0), i);
3310 /* Convert (mult (ashift (const_int 1) A) B) to (ashift B A). */
3311 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3312 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3313 return gen_rtx_combine (ASHIFT, mode, XEXP (x, 1),
3314 XEXP (XEXP (x, 0), 1));
3318 /* If this is a divide by a power of two, treat it as a shift if
3319 its first operand is a shift. */
3320 if (GET_CODE (XEXP (x, 1)) == CONST_INT
3321 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
3322 && (GET_CODE (XEXP (x, 0)) == ASHIFT
3323 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
3324 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
3325 || GET_CODE (XEXP (x, 0)) == ROTATE
3326 || GET_CODE (XEXP (x, 0)) == ROTATERT))
3328 x = simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
3334 case GT: case GTU: case GE: case GEU:
3335 case LT: case LTU: case LE: case LEU:
3336 /* If the first operand is a condition code, we can't do anything
3338 if (GET_CODE (XEXP (x, 0)) == COMPARE
3339 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
3341 && XEXP (x, 0) != cc0_rtx
3345 rtx op0 = XEXP (x, 0);
3346 rtx op1 = XEXP (x, 1);
3347 enum rtx_code new_code;
3349 if (GET_CODE (op0) == COMPARE)
3350 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
3352 /* Simplify our comparison, if possible. */
3353 new_code = simplify_comparison (code, &op0, &op1);
3355 #if STORE_FLAG_VALUE == 1
3356 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
3357 if only the low-order bit is significant in X (such as when
3358 X is a ZERO_EXTRACT of one bit. Similarly, we can convert
3360 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3361 && op1 == const0_rtx
3362 && significant_bits (op0, GET_MODE (op0)) == 1)
3363 return gen_lowpart_for_combine (mode, op0);
3364 else if (new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3365 && op1 == const0_rtx
3366 && significant_bits (op0, GET_MODE (op0)) == 1)
3367 return gen_rtx_combine (XOR, mode,
3368 gen_lowpart_for_combine (mode, op0),
3372 #if STORE_FLAG_VALUE == -1
3373 /* If STORE_FLAG_VALUE is -1, we can convert (ne x 0)
3374 to (neg x) if only the low-order bit of X is significant.
3375 This converts (ne (zero_extract X 1 Y) 0) to
3376 (sign_extract X 1 Y). */
3377 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3378 && op1 == const0_rtx
3379 && significant_bits (op0, GET_MODE (op0)) == 1)
3381 x = gen_rtx_combine (NEG, mode,
3382 gen_lowpart_for_combine (mode, op0));
3387 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
3388 one significant bit, we can convert (ne x 0) to (ashift x c)
3389 where C puts the bit in the sign bit. Remove any AND with
3390 STORE_FLAG_VALUE when we are done, since we are only going to
3391 test the sign bit. */
3392 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3393 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3394 && (STORE_FLAG_VALUE
3395 == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
3396 && op1 == const0_rtx
3397 && mode == GET_MODE (op0)
3398 && (i = exact_log2 (significant_bits (op0, GET_MODE (op0)))) >= 0)
3400 x = simplify_shift_const (NULL_RTX, ASHIFT, mode, op0,
3401 GET_MODE_BITSIZE (mode) - 1 - i);
3402 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
3408 /* If the code changed, return a whole new comparison. */
3409 if (new_code != code)
3410 return gen_rtx_combine (new_code, mode, op0, op1);
3412 /* Otherwise, keep this operation, but maybe change its operands.
3413 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
3414 SUBST (XEXP (x, 0), op0);
3415 SUBST (XEXP (x, 1), op1);
3420 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register
3421 used in it is being compared against certain values. Get the
3422 true and false comparisons and see if that says anything about the
3423 value of each arm. */
3425 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3426 && reversible_comparison_p (XEXP (x, 0))
3427 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG)
3430 rtx from = XEXP (XEXP (x, 0), 0);
3431 enum rtx_code true_code = GET_CODE (XEXP (x, 0));
3432 enum rtx_code false_code = reverse_condition (true_code);
3433 rtx true_val = XEXP (XEXP (x, 0), 1);
3434 rtx false_val = true_val;
3435 rtx true_arm = XEXP (x, 1);
3436 rtx false_arm = XEXP (x, 2);
3439 /* If FALSE_CODE is EQ, swap the codes and arms. */
3441 if (false_code == EQ)
3443 swapped = 1, true_code = EQ, false_code = NE;
3444 true_arm = XEXP (x, 2), false_arm = XEXP (x, 1);
3447 /* If we are comparing against zero and the expression being tested
3448 has only a single significant bit, that is its value when it is
3449 not equal to zero. Similarly if it is known to be -1 or 0. */
3451 if (true_code == EQ && true_val == const0_rtx
3452 && exact_log2 (sig = significant_bits (from,
3453 GET_MODE (from))) >= 0)
3454 false_code = EQ, false_val = GEN_INT (sig);
3455 else if (true_code == EQ && true_val == const0_rtx
3456 && (num_sign_bit_copies (from, GET_MODE (from))
3457 == GET_MODE_BITSIZE (GET_MODE (from))))
3458 false_code = EQ, false_val = constm1_rtx;
3460 /* Now simplify an arm if we know the value of the register
3461 in the branch and it is used in the arm. Be carefull due to
3462 the potential of locally-shared RTL. */
3464 if (reg_mentioned_p (from, true_arm))
3465 true_arm = subst (known_cond (copy_rtx (true_arm), true_code,
3467 pc_rtx, pc_rtx, 0, 0);
3468 if (reg_mentioned_p (from, false_arm))
3469 false_arm = subst (known_cond (copy_rtx (false_arm), false_code,
3471 pc_rtx, pc_rtx, 0, 0);
3473 SUBST (XEXP (x, 1), swapped ? false_arm : true_arm);
3474 SUBST (XEXP (x, 2), swapped ? true_arm : false_arm);
3477 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
3478 reversed, do so to avoid needing two sets of patterns for
3479 subtract-and-branch insns. Similarly if we have a constant in that
3480 position or if the third operand is the same as the first operand
3481 of the comparison. */
3483 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3484 && reversible_comparison_p (XEXP (x, 0))
3485 && (XEXP (x, 1) == pc_rtx || GET_CODE (XEXP (x, 1)) == CONST_INT
3486 || rtx_equal_p (XEXP (x, 2), XEXP (XEXP (x, 0), 0))))
3489 gen_binary (reverse_condition (GET_CODE (XEXP (x, 0))),
3490 GET_MODE (XEXP (x, 0)),
3491 XEXP (XEXP (x, 0), 0), XEXP (XEXP (x, 0), 1)));
3494 SUBST (XEXP (x, 1), XEXP (x, 2));
3495 SUBST (XEXP (x, 2), temp);
3498 /* If the two arms are identical, we don't need the comparison. */
3500 if (rtx_equal_p (XEXP (x, 1), XEXP (x, 2))
3501 && ! side_effects_p (XEXP (x, 0)))
3504 /* Look for cases where we have (abs x) or (neg (abs X)). */
3506 if (GET_MODE_CLASS (mode) == MODE_INT
3507 && GET_CODE (XEXP (x, 2)) == NEG
3508 && rtx_equal_p (XEXP (x, 1), XEXP (XEXP (x, 2), 0))
3509 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3510 && rtx_equal_p (XEXP (x, 1), XEXP (XEXP (x, 0), 0))
3511 && ! side_effects_p (XEXP (x, 1)))
3512 switch (GET_CODE (XEXP (x, 0)))
3516 x = gen_unary (ABS, mode, XEXP (x, 1));
3520 x = gen_unary (NEG, mode, gen_unary (ABS, mode, XEXP (x, 1)));
3524 /* Look for MIN or MAX. */
3526 if (GET_MODE_CLASS (mode) == MODE_INT
3527 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3528 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))
3529 && rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 2))
3530 && ! side_effects_p (XEXP (x, 0)))
3531 switch (GET_CODE (XEXP (x, 0)))
3535 x = gen_binary (SMAX, mode, XEXP (x, 1), XEXP (x, 2));
3539 x = gen_binary (SMIN, mode, XEXP (x, 1), XEXP (x, 2));
3543 x = gen_binary (UMAX, mode, XEXP (x, 1), XEXP (x, 2));
3547 x = gen_binary (UMIN, mode, XEXP (x, 1), XEXP (x, 2));
3551 /* If we have something like (if_then_else (ne A 0) (OP X C) X),
3552 A is known to be either 0 or 1, and OP is an identity when its
3553 second operand is zero, this can be done as (OP X (mult A C)).
3554 Similarly if A is known to be 0 or -1 and also similarly if we have
3555 a ZERO_EXTEND or SIGN_EXTEND as long as X is already extended (so
3556 we don't destroy it). */
3558 if (mode != VOIDmode
3559 && (GET_CODE (XEXP (x, 0)) == EQ || GET_CODE (XEXP (x, 0)) == NE)
3560 && XEXP (XEXP (x, 0), 1) == const0_rtx
3561 && (significant_bits (XEXP (XEXP (x, 0), 0), mode) == 1
3562 || (num_sign_bit_copies (XEXP (XEXP (x, 0), 0), mode)
3563 == GET_MODE_BITSIZE (mode))))
3565 rtx nz = make_compound_operation (GET_CODE (XEXP (x, 0)) == NE
3566 ? XEXP (x, 1) : XEXP (x, 2));
3567 rtx z = GET_CODE (XEXP (x, 0)) == NE ? XEXP (x, 2) : XEXP (x, 1);
3568 rtx dir = (significant_bits (XEXP (XEXP (x, 0), 0), mode) == 1
3569 ? const1_rtx : constm1_rtx);
3571 enum machine_mode m = mode;
3572 enum rtx_code op, extend_op = 0;
3574 if ((GET_CODE (nz) == PLUS || GET_CODE (nz) == MINUS
3575 || GET_CODE (nz) == IOR || GET_CODE (nz) == XOR
3576 || GET_CODE (nz) == ASHIFT
3577 || GET_CODE (nz) == LSHIFTRT || GET_CODE (nz) == ASHIFTRT)
3578 && rtx_equal_p (XEXP (nz, 0), z))
3579 c = XEXP (nz, 1), op = GET_CODE (nz);
3580 else if (GET_CODE (nz) == SIGN_EXTEND
3581 && (GET_CODE (XEXP (nz, 0)) == PLUS
3582 || GET_CODE (XEXP (nz, 0)) == MINUS
3583 || GET_CODE (XEXP (nz, 0)) == IOR
3584 || GET_CODE (XEXP (nz, 0)) == XOR
3585 || GET_CODE (XEXP (nz, 0)) == ASHIFT
3586 || GET_CODE (XEXP (nz, 0)) == LSHIFTRT
3587 || GET_CODE (XEXP (nz, 0)) == ASHIFTRT)
3588 && GET_CODE (XEXP (XEXP (nz, 0), 0)) == SUBREG
3589 && subreg_lowpart_p (XEXP (XEXP (nz, 0), 0))
3590 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (nz, 0), 0)), z)
3591 && (num_sign_bit_copies (z, GET_MODE (z))
3592 >= (GET_MODE_BITSIZE (mode)
3593 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (nz, 0), 0))))))
3595 c = XEXP (XEXP (nz, 0), 1);
3596 op = GET_CODE (XEXP (nz, 0));
3597 extend_op = SIGN_EXTEND;
3598 m = GET_MODE (XEXP (nz, 0));
3600 else if (GET_CODE (nz) == ZERO_EXTEND
3601 && (GET_CODE (XEXP (nz, 0)) == PLUS
3602 || GET_CODE (XEXP (nz, 0)) == MINUS
3603 || GET_CODE (XEXP (nz, 0)) == IOR
3604 || GET_CODE (XEXP (nz, 0)) == XOR
3605 || GET_CODE (XEXP (nz, 0)) == ASHIFT
3606 || GET_CODE (XEXP (nz, 0)) == LSHIFTRT
3607 || GET_CODE (XEXP (nz, 0)) == ASHIFTRT)
3608 && GET_CODE (XEXP (XEXP (nz, 0), 0)) == SUBREG
3609 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3610 && subreg_lowpart_p (XEXP (XEXP (nz, 0), 0))
3611 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (nz, 0), 0)), z)
3612 && ((significant_bits (z, GET_MODE (z))
3613 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (nz, 0), 0))))
3616 c = XEXP (XEXP (nz, 0), 1);
3617 op = GET_CODE (XEXP (nz, 0));
3618 extend_op = ZERO_EXTEND;
3619 m = GET_MODE (XEXP (nz, 0));
3622 if (c && ! side_effects_p (c) && ! side_effects_p (z))
3625 = gen_binary (MULT, m,
3626 gen_lowpart_for_combine (m,
3627 XEXP (XEXP (x, 0), 0)),
3628 gen_binary (MULT, m, c, dir));
3630 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
3633 temp = gen_unary (extend_op, mode, temp);
3644 /* If we are processing SET_DEST, we are done. */
3648 x = expand_compound_operation (x);
3649 if (GET_CODE (x) != code)
3654 /* (set (pc) (return)) gets written as (return). */
3655 if (GET_CODE (SET_DEST (x)) == PC && GET_CODE (SET_SRC (x)) == RETURN)
3658 /* Convert this into a field assignment operation, if possible. */
3659 x = make_field_assignment (x);
3661 /* If we are setting CC0 or if the source is a COMPARE, look for the
3662 use of the comparison result and try to simplify it unless we already
3663 have used undobuf.other_insn. */
3664 if ((GET_CODE (SET_SRC (x)) == COMPARE
3666 || SET_DEST (x) == cc0_rtx
3669 && (cc_use = find_single_use (SET_DEST (x), subst_insn,
3671 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
3672 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
3673 && XEXP (*cc_use, 0) == SET_DEST (x))
3675 enum rtx_code old_code = GET_CODE (*cc_use);
3676 enum rtx_code new_code;
3678 int other_changed = 0;
3679 enum machine_mode compare_mode = GET_MODE (SET_DEST (x));
3681 if (GET_CODE (SET_SRC (x)) == COMPARE)
3682 op0 = XEXP (SET_SRC (x), 0), op1 = XEXP (SET_SRC (x), 1);
3684 op0 = SET_SRC (x), op1 = const0_rtx;
3686 /* Simplify our comparison, if possible. */
3687 new_code = simplify_comparison (old_code, &op0, &op1);
3689 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
3690 /* If this machine has CC modes other than CCmode, check to see
3691 if we need to use a different CC mode here. */
3692 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
3694 /* If the mode changed, we have to change SET_DEST, the mode
3695 in the compare, and the mode in the place SET_DEST is used.
3696 If SET_DEST is a hard register, just build new versions with
3697 the proper mode. If it is a pseudo, we lose unless it is only
3698 time we set the pseudo, in which case we can safely change
3700 if (compare_mode != GET_MODE (SET_DEST (x)))
3702 int regno = REGNO (SET_DEST (x));
3703 rtx new_dest = gen_rtx (REG, compare_mode, regno);
3705 if (regno < FIRST_PSEUDO_REGISTER
3706 || (reg_n_sets[regno] == 1
3707 && ! REG_USERVAR_P (SET_DEST (x))))
3709 if (regno >= FIRST_PSEUDO_REGISTER)
3710 SUBST (regno_reg_rtx[regno], new_dest);
3712 SUBST (SET_DEST (x), new_dest);
3713 SUBST (XEXP (*cc_use, 0), new_dest);
3719 /* If the code changed, we have to build a new comparison
3720 in undobuf.other_insn. */
3721 if (new_code != old_code)
3725 SUBST (*cc_use, gen_rtx_combine (new_code, GET_MODE (*cc_use),
3726 SET_DEST (x), const0_rtx));
3728 /* If the only change we made was to change an EQ into an
3729 NE or vice versa, OP0 has only one significant bit,
3730 and OP1 is zero, check if changing the user of the condition
3731 code will produce a valid insn. If it won't, we can keep
3732 the original code in that insn by surrounding our operation
3735 if (((old_code == NE && new_code == EQ)
3736 || (old_code == EQ && new_code == NE))
3737 && ! other_changed && op1 == const0_rtx
3738 && (GET_MODE_BITSIZE (GET_MODE (op0))
3739 <= HOST_BITS_PER_WIDE_INT)
3740 && (exact_log2 (mask = significant_bits (op0,
3744 rtx pat = PATTERN (other_insn), note = 0;
3746 if ((recog_for_combine (&pat, undobuf.other_insn, ¬e) < 0
3747 && ! check_asm_operands (pat)))
3749 PUT_CODE (*cc_use, old_code);
3752 op0 = gen_binary (XOR, GET_MODE (op0), op0,
3761 undobuf.other_insn = other_insn;
3764 /* If we are now comparing against zero, change our source if
3765 needed. If we do not use cc0, we always have a COMPARE. */
3766 if (op1 == const0_rtx && SET_DEST (x) == cc0_rtx)
3767 SUBST (SET_SRC (x), op0);
3771 /* Otherwise, if we didn't previously have a COMPARE in the
3772 correct mode, we need one. */
3773 if (GET_CODE (SET_SRC (x)) != COMPARE
3774 || GET_MODE (SET_SRC (x)) != compare_mode)
3775 SUBST (SET_SRC (x), gen_rtx_combine (COMPARE, compare_mode,
3779 /* Otherwise, update the COMPARE if needed. */
3780 SUBST (XEXP (SET_SRC (x), 0), op0);
3781 SUBST (XEXP (SET_SRC (x), 1), op1);
3786 /* Get SET_SRC in a form where we have placed back any
3787 compound expressions. Then do the checks below. */
3788 temp = make_compound_operation (SET_SRC (x), SET);
3789 SUBST (SET_SRC (x), temp);
3792 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some
3793 operation, and X being a REG or (subreg (reg)), we may be able to
3794 convert this to (set (subreg:m2 x) (op)).
3796 We can always do this if M1 is narrower than M2 because that
3797 means that we only care about the low bits of the result.
3799 However, on most machines (those with BYTE_LOADS_ZERO_EXTEND
3800 and BYTES_LOADS_SIGN_EXTEND not defined), we cannot perform a
3801 narrower operation that requested since the high-order bits will
3802 be undefined. On machine where BYTE_LOADS_*_EXTEND is defined,
3803 however, this transformation is safe as long as M1 and M2 have
3804 the same number of words. */
3806 if (GET_CODE (SET_SRC (x)) == SUBREG
3807 && subreg_lowpart_p (SET_SRC (x))
3808 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) != 'o'
3809 && (((GET_MODE_SIZE (GET_MODE (SET_SRC (x))) + (UNITS_PER_WORD - 1))
3811 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_SRC (x))))
3812 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
3813 #if ! defined(BYTE_LOADS_ZERO_EXTEND) && ! defined (BYTE_LOADS_SIGN_EXTEND)
3814 && (GET_MODE_SIZE (GET_MODE (SET_SRC (x)))
3815 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_SRC (x)))))
3817 && (GET_CODE (SET_DEST (x)) == REG
3818 || (GET_CODE (SET_DEST (x)) == SUBREG
3819 && GET_CODE (SUBREG_REG (SET_DEST (x))) == REG)))
3821 SUBST (SET_DEST (x),
3822 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (SET_SRC (x))),
3824 SUBST (SET_SRC (x), SUBREG_REG (SET_SRC (x)));
3827 #ifdef BYTE_LOADS_ZERO_EXTEND
3828 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with
3829 M wider than N, this would require a paradoxical subreg.
3830 Replace the subreg with a zero_extend to avoid the reload that
3831 would otherwise be required. */
3832 if (GET_CODE (SET_SRC (x)) == SUBREG
3833 && subreg_lowpart_p (SET_SRC (x))
3834 && SUBREG_WORD (SET_SRC (x)) == 0
3835 && (GET_MODE_SIZE (GET_MODE (SET_SRC (x)))
3836 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_SRC (x)))))
3837 && GET_CODE (SUBREG_REG (SET_SRC (x))) == MEM)
3838 SUBST (SET_SRC (x), gen_rtx_combine (ZERO_EXTEND,
3839 GET_MODE (SET_SRC (x)),
3840 XEXP (SET_SRC (x), 0)));
3843 #ifndef HAVE_conditional_move
3845 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE,
3846 and we are comparing an item known to be 0 or -1 against 0, use a
3847 logical operation instead. Check for one of the arms being an IOR
3848 of the other arm with some value. We compute three terms to be
3849 IOR'ed together. In practice, at most two will be nonzero. Then
3852 if (GET_CODE (SET_SRC (x)) == IF_THEN_ELSE
3853 && (GET_CODE (XEXP (SET_SRC (x), 0)) == EQ
3854 || GET_CODE (XEXP (SET_SRC (x), 0)) == NE)
3855 && XEXP (XEXP (SET_SRC (x), 0), 1) == const0_rtx
3856 && (num_sign_bit_copies (XEXP (XEXP (SET_SRC (x), 0), 0),
3857 GET_MODE (XEXP (XEXP (SET_SRC (x), 0), 0)))
3858 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (SET_SRC (x), 0), 0))))
3859 && ! side_effects_p (SET_SRC (x)))
3861 rtx true = (GET_CODE (XEXP (SET_SRC (x), 0)) == NE
3862 ? XEXP (SET_SRC (x), 1) : XEXP (SET_SRC (x), 2));
3863 rtx false = (GET_CODE (XEXP (SET_SRC (x), 0)) == NE
3864 ? XEXP (SET_SRC (x), 2) : XEXP (SET_SRC (x), 1));
3865 rtx term1 = const0_rtx, term2, term3;
3867 if (GET_CODE (true) == IOR && rtx_equal_p (XEXP (true, 0), false))
3868 term1 = false, true = XEXP (true, 1), false = const0_rtx;
3869 else if (GET_CODE (true) == IOR
3870 && rtx_equal_p (XEXP (true, 1), false))
3871 term1 = false, true = XEXP (true, 0), false = const0_rtx;
3872 else if (GET_CODE (false) == IOR
3873 && rtx_equal_p (XEXP (false, 0), true))
3874 term1 = true, false = XEXP (false, 1), true = const0_rtx;
3875 else if (GET_CODE (false) == IOR
3876 && rtx_equal_p (XEXP (false, 1), true))
3877 term1 = true, false = XEXP (false, 0), true = const0_rtx;
3879 term2 = gen_binary (AND, GET_MODE (SET_SRC (x)),
3880 XEXP (XEXP (SET_SRC (x), 0), 0), true);
3881 term3 = gen_binary (AND, GET_MODE (SET_SRC (x)),
3882 gen_unary (NOT, GET_MODE (SET_SRC (x)),
3883 XEXP (XEXP (SET_SRC (x), 0), 0)),
3887 gen_binary (IOR, GET_MODE (SET_SRC (x)),
3888 gen_binary (IOR, GET_MODE (SET_SRC (x)),
3896 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3898 x = simplify_and_const_int (x, mode, XEXP (x, 0),
3899 INTVAL (XEXP (x, 1)));
3901 /* If we have (ior (and (X C1) C2)) and the next restart would be
3902 the last, simplify this by making C1 as small as possible
3904 if (n_restarts >= 3 && GET_CODE (x) == IOR
3905 && GET_CODE (XEXP (x, 0)) == AND
3906 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3907 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3909 temp = gen_binary (AND, mode, XEXP (XEXP (x, 0), 0),
3910 GEN_INT (INTVAL (XEXP (XEXP (x, 0), 1))
3911 & ~ INTVAL (XEXP (x, 1))));
3912 return gen_binary (IOR, mode, temp, XEXP (x, 1));
3915 if (GET_CODE (x) != AND)
3919 /* Convert (A | B) & A to A. */
3920 if (GET_CODE (XEXP (x, 0)) == IOR
3921 && (rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))
3922 || rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 1)))
3923 && ! side_effects_p (XEXP (XEXP (x, 0), 0))
3924 && ! side_effects_p (XEXP (XEXP (x, 0), 1)))
3927 /* Convert (A ^ B) & A to A & (~ B) since the latter is often a single
3928 insn (and may simplify more). */
3929 else if (GET_CODE (XEXP (x, 0)) == XOR
3930 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))
3931 && ! side_effects_p (XEXP (x, 1)))
3933 x = gen_binary (AND, mode,
3934 gen_unary (NOT, mode, XEXP (XEXP (x, 0), 1)),
3938 else if (GET_CODE (XEXP (x, 0)) == XOR
3939 && rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 1))
3940 && ! side_effects_p (XEXP (x, 1)))
3942 x = gen_binary (AND, mode,
3943 gen_unary (NOT, mode, XEXP (XEXP (x, 0), 0)),
3948 /* Similarly for (~ (A ^ B)) & A. */
3949 else if (GET_CODE (XEXP (x, 0)) == NOT
3950 && GET_CODE (XEXP (XEXP (x, 0), 0)) == XOR
3951 && rtx_equal_p (XEXP (XEXP (XEXP (x, 0), 0), 0), XEXP (x, 1))
3952 && ! side_effects_p (XEXP (x, 1)))
3954 x = gen_binary (AND, mode, XEXP (XEXP (XEXP (x, 0), 0), 1),
3958 else if (GET_CODE (XEXP (x, 0)) == NOT
3959 && GET_CODE (XEXP (XEXP (x, 0), 0)) == XOR
3960 && rtx_equal_p (XEXP (XEXP (XEXP (x, 0), 0), 1), XEXP (x, 1))
3961 && ! side_effects_p (XEXP (x, 1)))
3963 x = gen_binary (AND, mode, XEXP (XEXP (XEXP (x, 0), 0), 0),
3968 /* If we have (and A B) with A not an object but that is known to
3969 be -1 or 0, this is equivalent to the expression
3970 (if_then_else (ne A (const_int 0)) B (const_int 0))
3971 We make this conversion because it may allow further
3972 simplifications and then allow use of conditional move insns.
3973 If the machine doesn't have condition moves, code in case SET
3974 will convert the IF_THEN_ELSE back to the logical operation.
3975 We build the IF_THEN_ELSE here in case further simplification
3976 is possible (e.g., we can convert it to ABS). */
3978 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3979 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3980 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o')
3981 && (num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
3982 == GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
3984 rtx op0 = XEXP (x, 0);
3985 rtx op1 = const0_rtx;
3986 enum rtx_code comp_code
3987 = simplify_comparison (NE, &op0, &op1);
3989 x = gen_rtx_combine (IF_THEN_ELSE, mode,
3990 gen_binary (comp_code, VOIDmode, op0, op1),
3991 XEXP (x, 1), const0_rtx);
3995 /* In the following group of tests (and those in case IOR below),
3996 we start with some combination of logical operations and apply
3997 the distributive law followed by the inverse distributive law.
3998 Most of the time, this results in no change. However, if some of
3999 the operands are the same or inverses of each other, simplifications
4002 For example, (and (ior A B) (not B)) can occur as the result of
4003 expanding a bit field assignment. When we apply the distributive
4004 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
4005 which then simplifies to (and (A (not B))). */
4007 /* If we have (and (ior A B) C), apply the distributive law and then
4008 the inverse distributive law to see if things simplify. */
4010 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == XOR)
4012 x = apply_distributive_law
4013 (gen_binary (GET_CODE (XEXP (x, 0)), mode,
4014 gen_binary (AND, mode,
4015 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4016 gen_binary (AND, mode,
4017 XEXP (XEXP (x, 0), 1), XEXP (x, 1))));
4018 if (GET_CODE (x) != AND)
4022 if (GET_CODE (XEXP (x, 1)) == IOR || GET_CODE (XEXP (x, 1)) == XOR)
4024 x = apply_distributive_law
4025 (gen_binary (GET_CODE (XEXP (x, 1)), mode,
4026 gen_binary (AND, mode,
4027 XEXP (XEXP (x, 1), 0), XEXP (x, 0)),
4028 gen_binary (AND, mode,
4029 XEXP (XEXP (x, 1), 1), XEXP (x, 0))));
4030 if (GET_CODE (x) != AND)
4034 /* Similarly, taking advantage of the fact that
4035 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
4037 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == XOR)
4039 x = apply_distributive_law
4040 (gen_binary (XOR, mode,
4041 gen_binary (IOR, mode, XEXP (XEXP (x, 0), 0),
4042 XEXP (XEXP (x, 1), 0)),
4043 gen_binary (IOR, mode, XEXP (XEXP (x, 0), 0),
4044 XEXP (XEXP (x, 1), 1))));
4045 if (GET_CODE (x) != AND)
4049 else if (GET_CODE (XEXP (x, 1)) == NOT && GET_CODE (XEXP (x, 0)) == XOR)
4051 x = apply_distributive_law
4052 (gen_binary (XOR, mode,
4053 gen_binary (IOR, mode, XEXP (XEXP (x, 1), 0),
4054 XEXP (XEXP (x, 0), 0)),
4055 gen_binary (IOR, mode, XEXP (XEXP (x, 1), 0),
4056 XEXP (XEXP (x, 0), 1))));
4057 if (GET_CODE (x) != AND)
4063 /* (ior A C) is C if all significant bits of A are on in C. */
4064 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4065 && (significant_bits (XEXP (x, 0), mode)
4066 & ~ INTVAL (XEXP (x, 1))) == 0)
4069 /* Convert (A & B) | A to A. */
4070 if (GET_CODE (XEXP (x, 0)) == AND
4071 && (rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))
4072 || rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 1)))
4073 && ! side_effects_p (XEXP (XEXP (x, 0), 0))
4074 && ! side_effects_p (XEXP (XEXP (x, 0), 1)))
4077 /* If we have (ior (and A B) C), apply the distributive law and then
4078 the inverse distributive law to see if things simplify. */
4080 if (GET_CODE (XEXP (x, 0)) == AND)
4082 x = apply_distributive_law
4083 (gen_binary (AND, mode,
4084 gen_binary (IOR, mode,
4085 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4086 gen_binary (IOR, mode,
4087 XEXP (XEXP (x, 0), 1), XEXP (x, 1))));
4089 if (GET_CODE (x) != IOR)
4093 if (GET_CODE (XEXP (x, 1)) == AND)
4095 x = apply_distributive_law
4096 (gen_binary (AND, mode,
4097 gen_binary (IOR, mode,
4098 XEXP (XEXP (x, 1), 0), XEXP (x, 0)),
4099 gen_binary (IOR, mode,
4100 XEXP (XEXP (x, 1), 1), XEXP (x, 0))));
4102 if (GET_CODE (x) != IOR)
4106 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
4107 mode size to (rotate A CX). */
4109 if (((GET_CODE (XEXP (x, 0)) == ASHIFT
4110 && GET_CODE (XEXP (x, 1)) == LSHIFTRT)
4111 || (GET_CODE (XEXP (x, 1)) == ASHIFT
4112 && GET_CODE (XEXP (x, 0)) == LSHIFTRT))
4113 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (XEXP (x, 1), 0))
4114 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4115 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4116 && (INTVAL (XEXP (XEXP (x, 0), 1)) + INTVAL (XEXP (XEXP (x, 1), 1))
4117 == GET_MODE_BITSIZE (mode)))
4121 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
4122 shift_count = XEXP (XEXP (x, 0), 1);
4124 shift_count = XEXP (XEXP (x, 1), 1);
4125 x = gen_rtx (ROTATE, mode, XEXP (XEXP (x, 0), 0), shift_count);
4131 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
4132 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
4135 int num_negated = 0;
4136 rtx in1 = XEXP (x, 0), in2 = XEXP (x, 1);
4138 if (GET_CODE (in1) == NOT)
4139 num_negated++, in1 = XEXP (in1, 0);
4140 if (GET_CODE (in2) == NOT)
4141 num_negated++, in2 = XEXP (in2, 0);
4143 if (num_negated == 2)
4145 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4146 SUBST (XEXP (x, 1), XEXP (XEXP (x, 1), 0));
4148 else if (num_negated == 1)
4150 x = gen_unary (NOT, mode,
4151 gen_binary (XOR, mode, in1, in2));
4156 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
4157 correspond to a machine insn or result in further simplifications
4158 if B is a constant. */
4160 if (GET_CODE (XEXP (x, 0)) == AND
4161 && rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 1))
4162 && ! side_effects_p (XEXP (x, 1)))
4164 x = gen_binary (AND, mode,
4165 gen_unary (NOT, mode, XEXP (XEXP (x, 0), 0)),
4169 else if (GET_CODE (XEXP (x, 0)) == AND
4170 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))
4171 && ! side_effects_p (XEXP (x, 1)))
4173 x = gen_binary (AND, mode,
4174 gen_unary (NOT, mode, XEXP (XEXP (x, 0), 1)),
4180 #if STORE_FLAG_VALUE == 1
4181 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
4183 if (XEXP (x, 1) == const1_rtx
4184 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4185 && reversible_comparison_p (XEXP (x, 0)))
4186 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
4187 mode, XEXP (XEXP (x, 0), 0),
4188 XEXP (XEXP (x, 0), 1));
4191 /* (xor (comparison foo bar) (const_int sign-bit))
4192 when STORE_FLAG_VALUE is the sign bit. */
4193 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4194 && (STORE_FLAG_VALUE
4195 == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4196 && XEXP (x, 1) == const_true_rtx
4197 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4198 && reversible_comparison_p (XEXP (x, 0)))
4199 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
4200 mode, XEXP (XEXP (x, 0), 0),
4201 XEXP (XEXP (x, 0), 1));
4205 /* (abs (neg <foo>)) -> (abs <foo>) */
4206 if (GET_CODE (XEXP (x, 0)) == NEG)
4207 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4209 /* If operand is something known to be positive, ignore the ABS. */
4210 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4211 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4212 <= HOST_BITS_PER_WIDE_INT)
4213 && ((significant_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4214 & ((HOST_WIDE_INT) 1
4215 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4220 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4221 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4223 x = gen_rtx_combine (NEG, mode, XEXP (x, 0));
4229 /* (ffs (*_extend <X>)) = (ffs <X>) */
4230 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4231 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4232 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4236 /* (float (sign_extend <X>)) = (float <X>). */
4237 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4238 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4247 /* If this is a shift by a constant amount, simplify it. */
4248 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4250 x = simplify_shift_const (x, code, mode, XEXP (x, 0),
4251 INTVAL (XEXP (x, 1)));
4252 if (GET_CODE (x) != code)
4256 #ifdef SHIFT_COUNT_TRUNCATED
4257 else if (GET_CODE (XEXP (x, 1)) != REG)
4259 force_to_mode (XEXP (x, 1), GET_MODE (x),
4260 exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))),
4270 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
4271 operations" because they can be replaced with two more basic operations.
4272 ZERO_EXTEND is also considered "compound" because it can be replaced with
4273 an AND operation, which is simpler, though only one operation.
4275 The function expand_compound_operation is called with an rtx expression
4276 and will convert it to the appropriate shifts and AND operations,
4277 simplifying at each stage.
4279 The function make_compound_operation is called to convert an expression
4280 consisting of shifts and ANDs into the equivalent compound expression.
4281 It is the inverse of this function, loosely speaking. */
4284 expand_compound_operation (x)
4292 switch (GET_CODE (x))
4297 /* We can't necessarily use a const_int for a multiword mode;
4298 it depends on implicitly extending the value.
4299 Since we don't know the right way to extend it,
4300 we can't tell whether the implicit way is right.
4302 Even for a mode that is no wider than a const_int,
4303 we can't win, because we need to sign extend one of its bits through
4304 the rest of it, and we don't know which bit. */
4305 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
4308 if (! FAKE_EXTEND_SAFE_P (GET_MODE (XEXP (x, 0)), XEXP (x, 0)))
4311 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
4312 /* If the inner object has VOIDmode (the only way this can happen
4313 is if it is a ASM_OPERANDS), we can't do anything since we don't
4314 know how much masking to do. */
4323 /* If the operand is a CLOBBER, just return it. */
4324 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
4327 if (GET_CODE (XEXP (x, 1)) != CONST_INT
4328 || GET_CODE (XEXP (x, 2)) != CONST_INT
4329 || GET_MODE (XEXP (x, 0)) == VOIDmode)
4332 len = INTVAL (XEXP (x, 1));
4333 pos = INTVAL (XEXP (x, 2));
4335 /* If this goes outside the object being extracted, replace the object
4336 with a (use (mem ...)) construct that only combine understands
4337 and is used only for this purpose. */
4338 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
4339 SUBST (XEXP (x, 0), gen_rtx (USE, GET_MODE (x), XEXP (x, 0)));
4342 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
4350 /* If we reach here, we want to return a pair of shifts. The inner
4351 shift is a left shift of BITSIZE - POS - LEN bits. The outer
4352 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
4353 logical depending on the value of UNSIGNEDP.
4355 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
4356 converted into an AND of a shift.
4358 We must check for the case where the left shift would have a negative
4359 count. This can happen in a case like (x >> 31) & 255 on machines
4360 that can't shift by a constant. On those machines, we would first
4361 combine the shift with the AND to produce a variable-position
4362 extraction. Then the constant of 31 would be substituted in to produce
4363 a such a position. */
4365 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
4366 if (modewidth >= pos - len)
4367 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
4369 simplify_shift_const (NULL_RTX, ASHIFT,
4372 modewidth - pos - len),
4375 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
4376 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
4377 simplify_shift_const (NULL_RTX, LSHIFTRT,
4380 ((HOST_WIDE_INT) 1 << len) - 1);
4382 /* Any other cases we can't handle. */
4386 /* If we couldn't do this for some reason, return the original
4388 if (GET_CODE (tem) == CLOBBER)
4394 /* X is a SET which contains an assignment of one object into
4395 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
4396 or certain SUBREGS). If possible, convert it into a series of
4399 We half-heartedly support variable positions, but do not at all
4400 support variable lengths. */
4403 expand_field_assignment (x)
4407 rtx pos; /* Always counts from low bit. */
4410 enum machine_mode compute_mode;
4412 /* Loop until we find something we can't simplify. */
4415 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
4416 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
4418 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
4419 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
4422 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
4423 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
4425 inner = XEXP (SET_DEST (x), 0);
4426 len = INTVAL (XEXP (SET_DEST (x), 1));
4427 pos = XEXP (SET_DEST (x), 2);
4429 /* If the position is constant and spans the width of INNER,
4430 surround INNER with a USE to indicate this. */
4431 if (GET_CODE (pos) == CONST_INT
4432 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
4433 inner = gen_rtx (USE, GET_MODE (SET_DEST (x)), inner);
4436 if (GET_CODE (pos) == CONST_INT)
4437 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
4439 else if (GET_CODE (pos) == MINUS
4440 && GET_CODE (XEXP (pos, 1)) == CONST_INT
4441 && (INTVAL (XEXP (pos, 1))
4442 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
4443 /* If position is ADJUST - X, new position is X. */
4444 pos = XEXP (pos, 0);
4446 pos = gen_binary (MINUS, GET_MODE (pos),
4447 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
4453 /* A SUBREG between two modes that occupy the same numbers of words
4454 can be done by moving the SUBREG to the source. */
4455 else if (GET_CODE (SET_DEST (x)) == SUBREG
4456 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
4457 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
4458 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
4459 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
4461 x = gen_rtx (SET, VOIDmode, SUBREG_REG (SET_DEST (x)),
4462 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (SET_DEST (x))),
4469 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
4470 inner = SUBREG_REG (inner);
4472 compute_mode = GET_MODE (inner);
4474 /* Compute a mask of LEN bits, if we can do this on the host machine. */
4475 if (len < HOST_BITS_PER_WIDE_INT)
4476 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
4480 /* Now compute the equivalent expression. Make a copy of INNER
4481 for the SET_DEST in case it is a MEM into which we will substitute;
4482 we don't want shared RTL in that case. */
4483 x = gen_rtx (SET, VOIDmode, copy_rtx (inner),
4484 gen_binary (IOR, compute_mode,
4485 gen_binary (AND, compute_mode,
4486 gen_unary (NOT, compute_mode,
4491 gen_binary (ASHIFT, compute_mode,
4492 gen_binary (AND, compute_mode,
4493 gen_lowpart_for_combine
4503 /* Return an RTX for a reference to LEN bits of INNER. POS is the starting
4504 bit position (counted from the LSB) if >= 0; otherwise POS_RTX represents
4505 the starting bit position.
4507 INNER may be a USE. This will occur when we started with a bitfield
4508 that went outside the boundary of the object in memory, which is
4509 allowed on most machines. To isolate this case, we produce a USE
4510 whose mode is wide enough and surround the MEM with it. The only
4511 code that understands the USE is this routine. If it is not removed,
4512 it will cause the resulting insn not to match.
4514 UNSIGNEDP is non-zero for an unsigned reference and zero for a
4517 IN_DEST is non-zero if this is a reference in the destination of a
4518 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
4519 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
4522 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
4523 ZERO_EXTRACT should be built even for bits starting at bit 0.
4525 MODE is the desired mode of the result (if IN_DEST == 0). */
4528 make_extraction (mode, inner, pos, pos_rtx, len,
4529 unsignedp, in_dest, in_compare)
4530 enum machine_mode mode;
4536 int in_dest, in_compare;
4538 enum machine_mode is_mode = GET_MODE (inner);
4539 enum machine_mode inner_mode;
4540 enum machine_mode wanted_mem_mode = byte_mode;
4541 enum machine_mode pos_mode = word_mode;
4542 enum machine_mode extraction_mode = word_mode;
4543 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
4547 /* Get some information about INNER and get the innermost object. */
4548 if (GET_CODE (inner) == USE)
4549 /* We don't need to adjust the position because we set up the USE
4550 to pretend that it was a full-word object. */
4551 spans_byte = 1, inner = XEXP (inner, 0);
4552 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
4553 inner = SUBREG_REG (inner);
4555 inner_mode = GET_MODE (inner);
4557 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
4558 pos = INTVAL (pos_rtx);
4560 /* See if this can be done without an extraction. We never can if the
4561 width of the field is not the same as that of some integer mode. For
4562 registers, we can only avoid the extraction if the position is at the
4563 low-order bit and this is either not in the destination or we have the
4564 appropriate STRICT_LOW_PART operation available.
4566 For MEM, we can avoid an extract if the field starts on an appropriate
4567 boundary and we can change the mode of the memory reference. However,
4568 we cannot directly access the MEM if we have a USE and the underlying
4569 MEM is not TMODE. This combination means that MEM was being used in a
4570 context where bits outside its mode were being referenced; that is only
4571 valid in bit-field insns. */
4573 if (tmode != BLKmode
4574 && ! (spans_byte && inner_mode != tmode)
4575 && ((pos == 0 && GET_CODE (inner) != MEM
4577 || (GET_CODE (inner) == REG
4578 && (movstrict_optab->handlers[(int) tmode].insn_code
4579 != CODE_FOR_nothing))))
4580 || (GET_CODE (inner) == MEM && pos >= 0
4582 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
4583 : BITS_PER_UNIT)) == 0
4584 /* We can't do this if we are widening INNER_MODE (it
4585 may not be aligned, for one thing). */
4586 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
4587 && (inner_mode == tmode
4588 || (! mode_dependent_address_p (XEXP (inner, 0))
4589 && ! MEM_VOLATILE_P (inner))))))
4591 int offset = pos / BITS_PER_UNIT;
4593 /* If INNER is a MEM, make a new MEM that encompasses just the desired
4594 field. If the original and current mode are the same, we need not
4595 adjust the offset. Otherwise, we do if bytes big endian.
4597 If INNER is not a MEM, get a piece consisting of the just the field
4598 of interest (in this case POS must be 0). */
4600 if (GET_CODE (inner) == MEM)
4602 #if BYTES_BIG_ENDIAN
4603 if (inner_mode != tmode)
4604 offset = (GET_MODE_SIZE (inner_mode)
4605 - GET_MODE_SIZE (tmode) - offset);
4608 new = gen_rtx (MEM, tmode, plus_constant (XEXP (inner, 0), offset));
4609 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (inner);
4610 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (inner);
4611 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (inner);
4613 else if (GET_CODE (inner) == REG)
4614 /* We can't call gen_lowpart_for_combine here since we always want
4615 a SUBREG and it would sometimes return a new hard register. */
4616 new = gen_rtx (SUBREG, tmode, inner,
4618 && GET_MODE_SIZE (is_mode) > UNITS_PER_WORD)
4619 ? ((GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (tmode)
4623 new = force_to_mode (inner, tmode, len, NULL_RTX);
4625 /* If this extraction is going into the destination of a SET,
4626 make a STRICT_LOW_PART unless we made a MEM. */
4629 return (GET_CODE (new) == MEM ? new
4630 : (GET_CODE (new) != SUBREG
4631 ? gen_rtx (CLOBBER, tmode, const0_rtx)
4632 : gen_rtx_combine (STRICT_LOW_PART, VOIDmode, new)));
4634 /* Otherwise, sign- or zero-extend unless we already are in the
4637 return (mode == tmode ? new
4638 : gen_rtx_combine (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
4642 /* Unless this is a COMPARE or we have a funny memory reference,
4643 don't do anything with zero-extending field extracts starting at
4644 the low-order bit since they are simple AND operations. */
4645 if (pos == 0 && ! in_dest && ! in_compare && ! spans_byte && unsignedp)
4648 /* Get the mode to use should INNER be a MEM, the mode for the position,
4649 and the mode for the result. */
4653 wanted_mem_mode = insn_operand_mode[(int) CODE_FOR_insv][0];
4654 pos_mode = insn_operand_mode[(int) CODE_FOR_insv][2];
4655 extraction_mode = insn_operand_mode[(int) CODE_FOR_insv][3];
4660 if (! in_dest && unsignedp)
4662 wanted_mem_mode = insn_operand_mode[(int) CODE_FOR_extzv][1];
4663 pos_mode = insn_operand_mode[(int) CODE_FOR_extzv][3];
4664 extraction_mode = insn_operand_mode[(int) CODE_FOR_extzv][0];
4669 if (! in_dest && ! unsignedp)
4671 wanted_mem_mode = insn_operand_mode[(int) CODE_FOR_extv][1];
4672 pos_mode = insn_operand_mode[(int) CODE_FOR_extv][3];
4673 extraction_mode = insn_operand_mode[(int) CODE_FOR_extv][0];
4677 /* Never narrow an object, since that might not be safe. */
4679 if (mode != VOIDmode
4680 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
4681 extraction_mode = mode;
4683 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
4684 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
4685 pos_mode = GET_MODE (pos_rtx);
4687 /* If this is not from memory or we have to change the mode of memory and
4688 cannot, the desired mode is EXTRACTION_MODE. */
4689 if (GET_CODE (inner) != MEM
4690 || (inner_mode != wanted_mem_mode
4691 && (mode_dependent_address_p (XEXP (inner, 0))
4692 || MEM_VOLATILE_P (inner))))
4693 wanted_mem_mode = extraction_mode;
4696 /* If position is constant, compute new position. Otherwise, build
4699 pos = (MAX (GET_MODE_BITSIZE (is_mode), GET_MODE_BITSIZE (wanted_mem_mode))
4703 = gen_rtx_combine (MINUS, GET_MODE (pos_rtx),
4704 GEN_INT (MAX (GET_MODE_BITSIZE (is_mode),
4705 GET_MODE_BITSIZE (wanted_mem_mode))
4710 /* If INNER has a wider mode, make it smaller. If this is a constant
4711 extract, try to adjust the byte to point to the byte containing
4713 if (wanted_mem_mode != VOIDmode
4714 && GET_MODE_SIZE (wanted_mem_mode) < GET_MODE_SIZE (is_mode)
4715 && ((GET_CODE (inner) == MEM
4716 && (inner_mode == wanted_mem_mode
4717 || (! mode_dependent_address_p (XEXP (inner, 0))
4718 && ! MEM_VOLATILE_P (inner))))))
4722 /* The computations below will be correct if the machine is big
4723 endian in both bits and bytes or little endian in bits and bytes.
4724 If it is mixed, we must adjust. */
4726 #if BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
4727 if (! spans_byte && is_mode != wanted_mem_mode)
4728 offset = (GET_MODE_SIZE (is_mode)
4729 - GET_MODE_SIZE (wanted_mem_mode) - offset);
4732 /* If bytes are big endian and we had a paradoxical SUBREG, we must
4733 adjust OFFSET to compensate. */
4734 #if BYTES_BIG_ENDIAN
4736 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
4737 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
4740 /* If this is a constant position, we can move to the desired byte. */
4743 offset += pos / BITS_PER_UNIT;
4744 pos %= GET_MODE_BITSIZE (wanted_mem_mode);
4747 if (offset != 0 || inner_mode != wanted_mem_mode)
4749 rtx newmem = gen_rtx (MEM, wanted_mem_mode,
4750 plus_constant (XEXP (inner, 0), offset));
4751 RTX_UNCHANGING_P (newmem) = RTX_UNCHANGING_P (inner);
4752 MEM_VOLATILE_P (newmem) = MEM_VOLATILE_P (inner);
4753 MEM_IN_STRUCT_P (newmem) = MEM_IN_STRUCT_P (inner);
4758 /* If INNER is not memory, we can always get it into the proper mode. */
4759 else if (GET_CODE (inner) != MEM)
4760 inner = force_to_mode (inner, extraction_mode,
4761 (pos < 0 ? GET_MODE_BITSIZE (extraction_mode)
4765 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
4766 have to zero extend. Otherwise, we can just use a SUBREG. */
4768 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
4769 pos_rtx = gen_rtx_combine (ZERO_EXTEND, pos_mode, pos_rtx);
4771 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
4772 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
4774 /* Make POS_RTX unless we already have it and it is correct. */
4775 if (pos_rtx == 0 || (pos >= 0 && INTVAL (pos_rtx) != pos))
4776 pos_rtx = GEN_INT (pos);
4778 /* Make the required operation. See if we can use existing rtx. */
4779 new = gen_rtx_combine (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
4780 extraction_mode, inner, GEN_INT (len), pos_rtx);
4782 new = gen_lowpart_for_combine (mode, new);
4787 /* Look at the expression rooted at X. Look for expressions
4788 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
4789 Form these expressions.
4791 Return the new rtx, usually just X.
4793 Also, for machines like the Vax that don't have logical shift insns,
4794 try to convert logical to arithmetic shift operations in cases where
4795 they are equivalent. This undoes the canonicalizations to logical
4796 shifts done elsewhere.
4798 We try, as much as possible, to re-use rtl expressions to save memory.
4800 IN_CODE says what kind of expression we are processing. Normally, it is
4801 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
4802 being kludges), it is MEM. When processing the arguments of a comparison
4803 or a COMPARE against zero, it is COMPARE. */
4806 make_compound_operation (x, in_code)
4808 enum rtx_code in_code;
4810 enum rtx_code code = GET_CODE (x);
4811 enum machine_mode mode = GET_MODE (x);
4812 int mode_width = GET_MODE_BITSIZE (mode);
4813 enum rtx_code next_code;
4818 /* Select the code to be used in recursive calls. Once we are inside an
4819 address, we stay there. If we have a comparison, set to COMPARE,
4820 but once inside, go back to our default of SET. */
4822 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
4823 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
4824 && XEXP (x, 1) == const0_rtx) ? COMPARE
4825 : in_code == COMPARE ? SET : in_code);
4827 /* Process depending on the code of this operation. If NEW is set
4828 non-zero, it will be returned. */
4834 /* Convert shifts by constants into multiplications if inside
4836 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
4837 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
4838 && INTVAL (XEXP (x, 1)) >= 0)
4839 new = gen_rtx_combine (MULT, mode, XEXP (x, 0),
4840 GEN_INT ((HOST_WIDE_INT) 1
4841 << INTVAL (XEXP (x, 1))));
4845 /* If the second operand is not a constant, we can't do anything
4847 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
4850 /* If the constant is a power of two minus one and the first operand
4851 is a logical right shift, make an extraction. */
4852 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
4853 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
4854 new = make_extraction (mode, XEXP (XEXP (x, 0), 0), -1,
4855 XEXP (XEXP (x, 0), 1), i, 1,
4856 0, in_code == COMPARE);
4858 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
4859 else if (GET_CODE (XEXP (x, 0)) == SUBREG
4860 && subreg_lowpart_p (XEXP (x, 0))
4861 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
4862 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
4863 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))),
4864 XEXP (SUBREG_REG (XEXP (x, 0)), 0), -1,
4865 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
4866 0, in_code == COMPARE);
4869 /* If we are have (and (rotate X C) M) and C is larger than the number
4870 of bits in M, this is an extraction. */
4872 else if (GET_CODE (XEXP (x, 0)) == ROTATE
4873 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4874 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
4875 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
4876 new = make_extraction (mode, XEXP (XEXP (x, 0), 0),
4877 (GET_MODE_BITSIZE (mode)
4878 - INTVAL (XEXP (XEXP (x, 0), 1))),
4879 NULL_RTX, i, 1, 0, in_code == COMPARE);
4881 /* On machines without logical shifts, if the operand of the AND is
4882 a logical shift and our mask turns off all the propagated sign
4883 bits, we can replace the logical shift with an arithmetic shift. */
4884 else if (ashr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
4885 && (lshr_optab->handlers[(int) mode].insn_code
4886 == CODE_FOR_nothing)
4887 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
4888 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4889 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
4890 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
4891 && mode_width <= HOST_BITS_PER_WIDE_INT)
4893 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
4895 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
4896 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
4898 gen_rtx_combine (ASHIFTRT, mode, XEXP (XEXP (x, 0), 0),
4899 XEXP (XEXP (x, 0), 1)));
4902 /* If the constant is one less than a power of two, this might be
4903 representable by an extraction even if no shift is present.
4904 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
4905 we are in a COMPARE. */
4906 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
4907 new = make_extraction (mode, XEXP (x, 0), 0, NULL_RTX, i, 1,
4908 0, in_code == COMPARE);
4910 /* If we are in a comparison and this is an AND with a power of two,
4911 convert this into the appropriate bit extract. */
4912 else if (in_code == COMPARE
4913 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4914 new = make_extraction (mode, XEXP (x, 0), i, NULL_RTX, 1, 1, 0, 1);
4919 /* If the sign bit is known to be zero, replace this with an
4920 arithmetic shift. */
4921 if (ashr_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing
4922 && lshr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
4923 && mode_width <= HOST_BITS_PER_WIDE_INT
4924 && (significant_bits (XEXP (x, 0), mode)
4925 & (1 << (mode_width - 1))) == 0)
4927 new = gen_rtx_combine (ASHIFTRT, mode, XEXP (x, 0), XEXP (x, 1));
4931 /* ... fall through ... */
4934 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
4935 this is a SIGN_EXTRACT. */
4936 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4937 && GET_CODE (XEXP (x, 0)) == ASHIFT
4938 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4939 && INTVAL (XEXP (x, 1)) >= INTVAL (XEXP (XEXP (x, 0), 1)))
4940 new = make_extraction (mode, XEXP (XEXP (x, 0), 0),
4941 (INTVAL (XEXP (x, 1))
4942 - INTVAL (XEXP (XEXP (x, 0), 1))),
4943 NULL_RTX, mode_width - INTVAL (XEXP (x, 1)),
4944 code == LSHIFTRT, 0, in_code == COMPARE);
4946 /* Similarly if we have (ashifrt (OP (ashift foo C1) C3) C2). In these
4947 cases, we are better off returning a SIGN_EXTEND of the operation. */
4949 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4950 && (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND
4951 || GET_CODE (XEXP (x, 0)) == XOR
4952 || GET_CODE (XEXP (x, 0)) == PLUS)
4953 && GET_CODE (XEXP (XEXP (x, 0), 0)) == ASHIFT
4954 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4955 && INTVAL (XEXP (x, 1)) >= INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4956 && INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)) < HOST_BITS_PER_WIDE_INT
4957 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4958 && (INTVAL (XEXP (XEXP (x, 0), 1))
4959 & (((HOST_WIDE_INT) 1
4960 << INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))) - 1)) == 0)
4962 HOST_WIDE_INT newop1
4963 = (INTVAL (XEXP (XEXP (x, 0), 1))
4964 >> INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)));
4966 new = make_extraction (mode,
4967 gen_binary (GET_CODE (XEXP (x, 0)), mode,
4968 XEXP (XEXP (XEXP (x, 0), 0), 0),
4970 (INTVAL (XEXP (x, 1))
4971 - INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))),
4972 NULL_RTX, mode_width - INTVAL (XEXP (x, 1)),
4973 code == LSHIFTRT, 0, in_code == COMPARE);
4976 /* Similarly for (ashiftrt (neg (ashift FOO C1)) C2). */
4977 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4978 && GET_CODE (XEXP (x, 0)) == NEG
4979 && GET_CODE (XEXP (XEXP (x, 0), 0)) == ASHIFT
4980 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4981 && INTVAL (XEXP (x, 1)) >= INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)))
4982 new = make_extraction (mode,
4983 gen_unary (GET_CODE (XEXP (x, 0)), mode,
4984 XEXP (XEXP (XEXP (x, 0), 0), 0)),
4985 (INTVAL (XEXP (x, 1))
4986 - INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))),
4987 NULL_RTX, mode_width - INTVAL (XEXP (x, 1)),
4988 code == LSHIFTRT, 0, in_code == COMPARE);
4994 x = gen_lowpart_for_combine (mode, new);
4995 code = GET_CODE (x);
4998 /* Now recursively process each operand of this operation. */
4999 fmt = GET_RTX_FORMAT (code);
5000 for (i = 0; i < GET_RTX_LENGTH (code); i++)
5003 new = make_compound_operation (XEXP (x, i), next_code);
5004 SUBST (XEXP (x, i), new);
5010 /* Given M see if it is a value that would select a field of bits
5011 within an item, but not the entire word. Return -1 if not.
5012 Otherwise, return the starting position of the field, where 0 is the
5015 *PLEN is set to the length of the field. */
5018 get_pos_from_mask (m, plen)
5019 unsigned HOST_WIDE_INT m;
5022 /* Get the bit number of the first 1 bit from the right, -1 if none. */
5023 int pos = exact_log2 (m & - m);
5028 /* Now shift off the low-order zero bits and see if we have a power of
5030 *plen = exact_log2 ((m >> pos) + 1);
5038 /* Rewrite X so that it is an expression in MODE. We only care about the
5039 low-order BITS bits so we can ignore AND operations that just clear
5042 Also, if REG is non-zero and X is a register equal in value to REG,
5043 replace X with REG. */
5046 force_to_mode (x, mode, bits, reg)
5048 enum machine_mode mode;
5052 enum rtx_code code = GET_CODE (x);
5053 enum machine_mode op_mode = mode;
5055 /* If X is narrower than MODE or if BITS is larger than the size of MODE,
5056 just get X in the proper mode. */
5058 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
5059 || bits > GET_MODE_BITSIZE (mode))
5060 return gen_lowpart_for_combine (mode, x);
5068 x = expand_compound_operation (x);
5069 if (GET_CODE (x) != code)
5070 return force_to_mode (x, mode, bits, reg);
5074 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
5075 || rtx_equal_p (reg, get_last_value (x))))
5080 if (bits < HOST_BITS_PER_WIDE_INT)
5081 x = GEN_INT (INTVAL (x) & (((HOST_WIDE_INT) 1 << bits) - 1));
5085 /* Ignore low-order SUBREGs. */
5086 if (subreg_lowpart_p (x))
5087 return force_to_mode (SUBREG_REG (x), mode, bits, reg);
5091 /* If this is an AND with a constant. Otherwise, we fall through to
5092 do the general binary case. */
5094 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
5096 HOST_WIDE_INT mask = INTVAL (XEXP (x, 1));
5097 int len = exact_log2 (mask + 1);
5098 rtx op = XEXP (x, 0);
5100 /* If this is masking some low-order bits, we may be able to
5101 impose a stricter constraint on what bits of the operand are
5104 op = force_to_mode (op, mode, len > 0 ? MIN (len, bits) : bits,
5107 if (bits < HOST_BITS_PER_WIDE_INT)
5108 mask &= ((HOST_WIDE_INT) 1 << bits) - 1;
5110 /* If we have no AND in MODE, use the original mode for the
5113 if (and_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
5114 op_mode = GET_MODE (x);
5116 x = simplify_and_const_int (x, op_mode, op, mask);
5118 /* If X is still an AND, see if it is an AND with a mask that
5119 is just some low-order bits. If so, and it is BITS wide (it
5120 can't be wider), we don't need it. */
5122 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
5123 && bits < HOST_BITS_PER_WIDE_INT
5124 && INTVAL (XEXP (x, 1)) == ((HOST_WIDE_INT) 1 << bits) - 1)
5130 /* ... fall through ... */
5137 /* For most binary operations, just propagate into the operation and
5138 change the mode if we have an operation of that mode. */
5141 && add_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
5143 && sub_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
5144 || (code == MULT && (smul_optab->handlers[(int) mode].insn_code
5145 == CODE_FOR_nothing))
5147 && and_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
5149 && ior_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
5150 || (code == XOR && (xor_optab->handlers[(int) mode].insn_code
5151 == CODE_FOR_nothing)))
5152 op_mode = GET_MODE (x);
5154 x = gen_binary (code, op_mode,
5155 gen_lowpart_for_combine (op_mode,
5156 force_to_mode (XEXP (x, 0),
5159 gen_lowpart_for_combine (op_mode,
5160 force_to_mode (XEXP (x, 1),
5167 /* For left shifts, do the same, but just for the first operand.
5168 If the shift count is a constant, we need even fewer bits of the
5171 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) < bits)
5172 bits -= INTVAL (XEXP (x, 1));
5175 && ashl_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
5176 || (code == LSHIFT && (lshl_optab->handlers[(int) mode].insn_code
5177 == CODE_FOR_nothing)))
5178 op_mode = GET_MODE (x);
5180 x = gen_binary (code, op_mode,
5181 gen_lowpart_for_combine (op_mode,
5182 force_to_mode (XEXP (x, 0),
5189 /* Here we can only do something if the shift count is a constant and
5190 the count plus BITS is no larger than the width of MODE, we can do
5191 the shift in MODE. */
5193 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5194 && INTVAL (XEXP (x, 1)) + bits <= GET_MODE_BITSIZE (mode))
5196 rtx inner = force_to_mode (XEXP (x, 0), mode,
5197 bits + INTVAL (XEXP (x, 1)), reg);
5199 if (lshr_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
5200 op_mode = GET_MODE (x);
5202 x = gen_binary (LSHIFTRT, op_mode,
5203 gen_lowpart_for_combine (op_mode, inner),
5209 /* If this is a sign-extension operation that just affects bits
5210 we don't care about, remove it. */
5212 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5213 && INTVAL (XEXP (x, 1)) >= 0
5214 && INTVAL (XEXP (x, 1)) <= GET_MODE_BITSIZE (GET_MODE (x)) - bits
5215 && GET_CODE (XEXP (x, 0)) == ASHIFT
5216 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5217 && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1)))
5218 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, bits, reg);
5224 && neg_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
5225 || (code == NOT && (one_cmpl_optab->handlers[(int) mode].insn_code
5226 == CODE_FOR_nothing)))
5227 op_mode = GET_MODE (x);
5229 /* Handle these similarly to the way we handle most binary operations. */
5230 x = gen_unary (code, op_mode,
5231 gen_lowpart_for_combine (op_mode,
5232 force_to_mode (XEXP (x, 0), mode,
5237 /* We have no way of knowing if the IF_THEN_ELSE can itself be
5238 written in a narrower mode. We play it safe and do not do so. */
5241 gen_lowpart_for_combine (GET_MODE (x),
5242 force_to_mode (XEXP (x, 1), mode,
5245 gen_lowpart_for_combine (GET_MODE (x),
5246 force_to_mode (XEXP (x, 2), mode,
5251 /* Ensure we return a value of the proper mode. */
5252 return gen_lowpart_for_combine (mode, x);
5255 /* Return the value of expression X given the fact that condition COND
5256 is known to be true when applied to REG as its first operand and VAL
5257 as its second. X is known to not be shared and so can be modified in
5260 We only handle the simplest cases, and specifically those cases that
5261 arise with IF_THEN_ELSE expressions. */
5264 known_cond (x, cond, reg, val)
5269 enum rtx_code code = GET_CODE (x);
5274 if (side_effects_p (x))
5277 if (cond == EQ && rtx_equal_p (x, reg))
5280 /* If X is (abs REG) and we know something about REG's relationship
5281 with zero, we may be able to simplify this. */
5283 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
5286 case GE: case GT: case EQ:
5289 return gen_unary (NEG, GET_MODE (XEXP (x, 0)), XEXP (x, 0));
5292 /* The only other cases we handle are MIN, MAX, and comparisons if the
5293 operands are the same as REG and VAL. */
5295 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
5297 if (rtx_equal_p (XEXP (x, 0), val))
5298 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
5300 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
5302 if (GET_RTX_CLASS (code) == '<')
5303 return (comparison_dominates_p (cond, code) ? const_true_rtx
5304 : (comparison_dominates_p (cond,
5305 reverse_condition (code))
5308 else if (code == SMAX || code == SMIN
5309 || code == UMIN || code == UMAX)
5311 int unsignedp = (code == UMIN || code == UMAX);
5313 if (code == SMAX || code == UMAX)
5314 cond = reverse_condition (cond);
5319 return unsignedp ? x : XEXP (x, 1);
5321 return unsignedp ? x : XEXP (x, 0);
5323 return unsignedp ? XEXP (x, 1) : x;
5325 return unsignedp ? XEXP (x, 0) : x;
5331 fmt = GET_RTX_FORMAT (code);
5332 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5335 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
5336 else if (fmt[i] == 'E')
5337 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5338 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
5345 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
5346 Return that assignment if so.
5348 We only handle the most common cases. */
5351 make_field_assignment (x)
5354 rtx dest = SET_DEST (x);
5355 rtx src = SET_SRC (x);
5361 enum machine_mode mode;
5363 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
5364 a clear of a one-bit field. We will have changed it to
5365 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
5368 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
5369 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
5370 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
5371 && (rtx_equal_p (dest, XEXP (src, 1))
5372 || rtx_equal_p (dest, get_last_value (XEXP (src, 1)))
5373 || rtx_equal_p (get_last_value (dest), XEXP (src, 1))))
5375 assign = make_extraction (VOIDmode, dest, -1, XEXP (XEXP (src, 0), 1),
5377 return gen_rtx (SET, VOIDmode, assign, const0_rtx);
5380 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
5381 && subreg_lowpart_p (XEXP (src, 0))
5382 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
5383 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
5384 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
5385 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
5386 && (rtx_equal_p (dest, XEXP (src, 1))
5387 || rtx_equal_p (dest, get_last_value (XEXP (src, 1)))
5388 || rtx_equal_p (get_last_value (dest), XEXP (src, 1))))
5390 assign = make_extraction (VOIDmode, dest, -1,
5391 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
5393 return gen_rtx (SET, VOIDmode, assign, const0_rtx);
5396 /* If SRC is (ior (ashift (const_int 1) POS DEST)), this is a set of a
5398 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
5399 && XEXP (XEXP (src, 0), 0) == const1_rtx
5400 && (rtx_equal_p (dest, XEXP (src, 1))
5401 || rtx_equal_p (dest, get_last_value (XEXP (src, 1)))
5402 || rtx_equal_p (get_last_value (dest), XEXP (src, 1))))
5404 assign = make_extraction (VOIDmode, dest, -1, XEXP (XEXP (src, 0), 1),
5406 return gen_rtx (SET, VOIDmode, assign, const1_rtx);
5409 /* The other case we handle is assignments into a constant-position
5410 field. They look like (ior (and DEST C1) OTHER). If C1 represents
5411 a mask that has all one bits except for a group of zero bits and
5412 OTHER is known to have zeros where C1 has ones, this is such an
5413 assignment. Compute the position and length from C1. Shift OTHER
5414 to the appropriate position, force it to the required mode, and
5415 make the extraction. Check for the AND in both operands. */
5417 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == AND
5418 && GET_CODE (XEXP (XEXP (src, 0), 1)) == CONST_INT
5419 && (rtx_equal_p (XEXP (XEXP (src, 0), 0), dest)
5420 || rtx_equal_p (XEXP (XEXP (src, 0), 0), get_last_value (dest))
5421 || rtx_equal_p (get_last_value (XEXP (XEXP (src, 0), 1)), dest)))
5422 c1 = INTVAL (XEXP (XEXP (src, 0), 1)), other = XEXP (src, 1);
5423 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 1)) == AND
5424 && GET_CODE (XEXP (XEXP (src, 1), 1)) == CONST_INT
5425 && (rtx_equal_p (XEXP (XEXP (src, 1), 0), dest)
5426 || rtx_equal_p (XEXP (XEXP (src, 1), 0), get_last_value (dest))
5427 || rtx_equal_p (get_last_value (XEXP (XEXP (src, 1), 0)),
5429 c1 = INTVAL (XEXP (XEXP (src, 1), 1)), other = XEXP (src, 0);
5433 pos = get_pos_from_mask (~c1, &len);
5434 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
5435 || (c1 & significant_bits (other, GET_MODE (other))) != 0)
5438 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
5440 /* The mode to use for the source is the mode of the assignment, or of
5441 what is inside a possible STRICT_LOW_PART. */
5442 mode = (GET_CODE (assign) == STRICT_LOW_PART
5443 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
5445 /* Shift OTHER right POS places and make it the source, restricting it
5446 to the proper length and mode. */
5448 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
5449 GET_MODE (src), other, pos),
5452 return gen_rtx_combine (SET, VOIDmode, assign, src);
5455 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
5459 apply_distributive_law (x)
5462 enum rtx_code code = GET_CODE (x);
5463 rtx lhs, rhs, other;
5465 enum rtx_code inner_code;
5467 /* The outer operation can only be one of the following: */
5468 if (code != IOR && code != AND && code != XOR
5469 && code != PLUS && code != MINUS)
5472 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
5474 /* If either operand is a primitive we can't do anything, so get out fast. */
5475 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
5476 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
5479 lhs = expand_compound_operation (lhs);
5480 rhs = expand_compound_operation (rhs);
5481 inner_code = GET_CODE (lhs);
5482 if (inner_code != GET_CODE (rhs))
5485 /* See if the inner and outer operations distribute. */
5492 /* These all distribute except over PLUS. */
5493 if (code == PLUS || code == MINUS)
5498 if (code != PLUS && code != MINUS)
5504 /* These are also multiplies, so they distribute over everything. */
5508 /* Non-paradoxical SUBREGs distributes over all operations, provided
5509 the inner modes and word numbers are the same, this is an extraction
5510 of a low-order part, we don't convert an fp operation to int or
5511 vice versa, and we would not be converting a single-word
5512 operation into a multi-word operation. The latter test is not
5513 required, but it prevents generating unneeded multi-word operations.
5514 Some of the previous tests are redundant given the latter test, but
5515 are retained because they are required for correctness.
5517 We produce the result slightly differently in this case. */
5519 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
5520 || SUBREG_WORD (lhs) != SUBREG_WORD (rhs)
5521 || ! subreg_lowpart_p (lhs)
5522 || (GET_MODE_CLASS (GET_MODE (lhs))
5523 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
5524 || (GET_MODE_SIZE (GET_MODE (lhs))
5525 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
5526 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
5529 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
5530 SUBREG_REG (lhs), SUBREG_REG (rhs));
5531 return gen_lowpart_for_combine (GET_MODE (x), tem);
5537 /* Set LHS and RHS to the inner operands (A and B in the example
5538 above) and set OTHER to the common operand (C in the example).
5539 These is only one way to do this unless the inner operation is
5541 if (GET_RTX_CLASS (inner_code) == 'c'
5542 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
5543 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
5544 else if (GET_RTX_CLASS (inner_code) == 'c'
5545 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
5546 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
5547 else if (GET_RTX_CLASS (inner_code) == 'c'
5548 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
5549 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
5550 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
5551 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
5555 /* Form the new inner operation, seeing if it simplifies first. */
5556 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
5558 /* There is one exception to the general way of distributing:
5559 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
5560 if (code == XOR && inner_code == IOR)
5563 other = gen_unary (NOT, GET_MODE (x), other);
5566 /* We may be able to continuing distributing the result, so call
5567 ourselves recursively on the inner operation before forming the
5568 outer operation, which we return. */
5569 return gen_binary (inner_code, GET_MODE (x),
5570 apply_distributive_law (tem), other);
5573 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
5576 Return an equivalent form, if different from X. Otherwise, return X. If
5577 X is zero, we are to always construct the equivalent form. */
5580 simplify_and_const_int (x, mode, varop, constop)
5582 enum machine_mode mode;
5584 unsigned HOST_WIDE_INT constop;
5586 register enum machine_mode tmode;
5588 unsigned HOST_WIDE_INT significant;
5590 /* There is a large class of optimizations based on the principle that
5591 some operations produce results where certain bits are known to be zero,
5592 and hence are not significant to the AND. For example, if we have just
5593 done a left shift of one bit, the low-order bit is known to be zero and
5594 hence an AND with a mask of ~1 would not do anything.
5596 At the end of the following loop, we set:
5598 VAROP to be the item to be AND'ed with;
5599 CONSTOP to the constant value to AND it with. */
5603 /* If we ever encounter a mode wider than the host machine's widest
5604 integer size, we can't compute the masks accurately, so give up. */
5605 if (GET_MODE_BITSIZE (GET_MODE (varop)) > HOST_BITS_PER_WIDE_INT)
5608 /* Unless one of the cases below does a `continue',
5609 a `break' will be executed to exit the loop. */
5611 switch (GET_CODE (varop))
5614 /* If VAROP is a (clobber (const_int)), return it since we know
5615 we are generating something that won't match. */
5618 #if ! BITS_BIG_ENDIAN
5620 /* VAROP is a (use (mem ..)) that was made from a bit-field
5621 extraction that spanned the boundary of the MEM. If we are
5622 now masking so it is within that boundary, we don't need the
5624 if ((constop & ~ GET_MODE_MASK (GET_MODE (XEXP (varop, 0)))) == 0)
5626 varop = XEXP (varop, 0);
5633 if (subreg_lowpart_p (varop)
5634 /* We can ignore the effect this SUBREG if it narrows the mode
5635 or, on machines where byte operations extend, if the
5636 constant masks to zero all the bits the mode doesn't have. */
5637 && ((GET_MODE_SIZE (GET_MODE (varop))
5638 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop))))
5639 #if defined(BYTE_LOADS_ZERO_EXTEND) || defined(BYTE_LOADS_SIGN_EXTEND)
5641 & GET_MODE_MASK (GET_MODE (varop))
5642 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (varop)))))
5646 varop = SUBREG_REG (varop);
5655 /* Try to expand these into a series of shifts and then work
5656 with that result. If we can't, for example, if the extract
5657 isn't at a fixed position, give up. */
5658 temp = expand_compound_operation (varop);
5667 if (GET_CODE (XEXP (varop, 1)) == CONST_INT)
5669 constop &= INTVAL (XEXP (varop, 1));
5670 varop = XEXP (varop, 0);
5677 /* If VAROP is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
5678 LSHIFT so we end up with an (and (lshiftrt (ior ...) ...) ...)
5679 operation which may be a bitfield extraction. */
5681 if (GET_CODE (XEXP (varop, 0)) == LSHIFTRT
5682 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
5683 && INTVAL (XEXP (XEXP (varop, 0), 1)) >= 0
5684 && INTVAL (XEXP (XEXP (varop, 0), 1)) < HOST_BITS_PER_WIDE_INT
5685 && GET_CODE (XEXP (varop, 1)) == CONST_INT
5686 && (INTVAL (XEXP (varop, 1))
5687 & ~ significant_bits (XEXP (varop, 0),
5688 GET_MODE (varop)) == 0))
5690 temp = GEN_INT ((INTVAL (XEXP (varop, 1)) & constop)
5691 << INTVAL (XEXP (XEXP (varop, 0), 1)));
5692 temp = gen_binary (GET_CODE (varop), GET_MODE (varop),
5693 XEXP (XEXP (varop, 0), 0), temp);
5694 varop = gen_rtx_combine (LSHIFTRT, GET_MODE (varop),
5695 temp, XEXP (varop, 1));
5699 /* Apply the AND to both branches of the IOR or XOR, then try to
5700 apply the distributive law. This may eliminate operations
5701 if either branch can be simplified because of the AND.
5702 It may also make some cases more complex, but those cases
5703 probably won't match a pattern either with or without this. */
5705 gen_lowpart_for_combine
5706 (mode, apply_distributive_law
5708 (GET_CODE (varop), GET_MODE (varop),
5709 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
5710 XEXP (varop, 0), constop),
5711 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
5712 XEXP (varop, 1), constop))));
5715 /* (and (not FOO)) is (and (xor FOO CONST_OP)) so if FOO is an
5716 LSHIFTRT we can do the same as above. */
5718 if (GET_CODE (XEXP (varop, 0)) == LSHIFTRT
5719 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
5720 && INTVAL (XEXP (XEXP (varop, 0), 1)) >= 0
5721 && INTVAL (XEXP (XEXP (varop, 0), 1)) < HOST_BITS_PER_WIDE_INT)
5723 temp = GEN_INT (constop << INTVAL (XEXP (XEXP (varop, 0), 1)));
5724 temp = gen_binary (XOR, GET_MODE (varop),
5725 XEXP (XEXP (varop, 0), 0), temp);
5726 varop = gen_rtx_combine (LSHIFTRT, GET_MODE (varop),
5727 temp, XEXP (XEXP (varop, 0), 1));
5733 /* If we are just looking for the sign bit, we don't need this
5734 shift at all, even if it has a variable count. */
5735 if (constop == ((HOST_WIDE_INT) 1
5736 << (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)))
5738 varop = XEXP (varop, 0);
5742 /* If this is a shift by a constant, get a mask that contains
5743 those bits that are not copies of the sign bit. We then have
5744 two cases: If CONSTOP only includes those bits, this can be
5745 a logical shift, which may allow simplifications. If CONSTOP
5746 is a single-bit field not within those bits, we are requesting
5747 a copy of the sign bit and hence can shift the sign bit to
5748 the appropriate location. */
5749 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
5750 && INTVAL (XEXP (varop, 1)) >= 0
5751 && INTVAL (XEXP (varop, 1)) < HOST_BITS_PER_WIDE_INT)
5755 significant = GET_MODE_MASK (GET_MODE (varop));
5756 significant >>= INTVAL (XEXP (varop, 1));
5758 if ((constop & ~significant) == 0
5759 || (i = exact_log2 (constop)) >= 0)
5761 varop = simplify_shift_const
5762 (varop, LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
5763 i < 0 ? INTVAL (XEXP (varop, 1))
5764 : GET_MODE_BITSIZE (GET_MODE (varop)) - 1 - i);
5765 if (GET_CODE (varop) != ASHIFTRT)
5770 /* If our mask is 1, convert this to a LSHIFTRT. This can be done
5771 even if the shift count isn't a constant. */
5773 varop = gen_rtx_combine (LSHIFTRT, GET_MODE (varop),
5774 XEXP (varop, 0), XEXP (varop, 1));
5778 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is
5779 included in STORE_FLAG_VALUE and FOO has no significant bits
5781 if ((constop & ~ STORE_FLAG_VALUE) == 0
5782 && XEXP (varop, 0) == const0_rtx
5783 && (significant_bits (XEXP (varop, 0), mode) & ~ constop) == 0)
5785 varop = XEXP (varop, 0);
5791 /* In (and (plus FOO C1) M), if M is a mask that just turns off
5792 low-order bits (as in an alignment operation) and FOO is already
5793 aligned to that boundary, we can convert remove this AND
5794 and possibly the PLUS if it is now adding zero. */
5795 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
5796 && exact_log2 (-constop) >= 0
5797 && (significant_bits (XEXP (varop, 0), mode) & ~ constop) == 0)
5799 varop = plus_constant (XEXP (varop, 0),
5800 INTVAL (XEXP (varop, 1)) & constop);
5805 /* ... fall through ... */
5808 /* In (and (plus (and FOO M1) BAR) M2), if M1 and M2 are one
5809 less than powers of two and M2 is narrower than M1, we can
5810 eliminate the inner AND. This occurs when incrementing
5813 if (GET_CODE (XEXP (varop, 0)) == ZERO_EXTRACT
5814 || GET_CODE (XEXP (varop, 0)) == ZERO_EXTEND)
5815 SUBST (XEXP (varop, 0),
5816 expand_compound_operation (XEXP (varop, 0)));
5818 if (GET_CODE (XEXP (varop, 0)) == AND
5819 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
5820 && exact_log2 (constop + 1) >= 0
5821 && exact_log2 (INTVAL (XEXP (XEXP (varop, 0), 1)) + 1) >= 0
5822 && (~ INTVAL (XEXP (XEXP (varop, 0), 1)) & constop) == 0)
5823 SUBST (XEXP (varop, 0), XEXP (XEXP (varop, 0), 0));
5830 /* If we have reached a constant, this whole thing is constant. */
5831 if (GET_CODE (varop) == CONST_INT)
5832 return GEN_INT (constop & INTVAL (varop));
5834 /* See what bits are significant in VAROP. */
5835 significant = significant_bits (varop, mode);
5837 /* Turn off all bits in the constant that are known to already be zero.
5838 Thus, if the AND isn't needed at all, we will have CONSTOP == SIGNIFICANT
5839 which is tested below. */
5841 constop &= significant;
5843 /* If we don't have any bits left, return zero. */
5847 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
5848 if we already had one (just check for the simplest cases). */
5849 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
5850 && GET_MODE (XEXP (x, 0)) == mode
5851 && SUBREG_REG (XEXP (x, 0)) == varop)
5852 varop = XEXP (x, 0);
5854 varop = gen_lowpart_for_combine (mode, varop);
5856 /* If we can't make the SUBREG, try to return what we were given. */
5857 if (GET_CODE (varop) == CLOBBER)
5858 return x ? x : varop;
5860 /* If we are only masking insignificant bits, return VAROP. */
5861 if (constop == significant)
5864 /* Otherwise, return an AND. See how much, if any, of X we can use. */
5865 else if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
5866 x = gen_rtx_combine (AND, mode, varop, GEN_INT (constop));
5870 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5871 || INTVAL (XEXP (x, 1)) != constop)
5872 SUBST (XEXP (x, 1), GEN_INT (constop));
5874 SUBST (XEXP (x, 0), varop);
5880 /* Given an expression, X, compute which bits in X can be non-zero.
5881 We don't care about bits outside of those defined in MODE.
5883 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
5884 a shift, AND, or zero_extract, we can do better. */
5886 static unsigned HOST_WIDE_INT
5887 significant_bits (x, mode)
5889 enum machine_mode mode;
5891 unsigned HOST_WIDE_INT significant = GET_MODE_MASK (mode);
5892 unsigned HOST_WIDE_INT inner_sig;
5894 int mode_width = GET_MODE_BITSIZE (mode);
5897 /* If X is wider than MODE, use its mode instead. */
5898 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
5900 mode = GET_MODE (x);
5901 significant = GET_MODE_MASK (mode);
5902 mode_width = GET_MODE_BITSIZE (mode);
5905 if (mode_width > HOST_BITS_PER_WIDE_INT)
5906 /* Our only callers in this case look for single bit values. So
5907 just return the mode mask. Those tests will then be false. */
5910 code = GET_CODE (x);
5914 #ifdef STACK_BOUNDARY
5915 /* If this is the stack pointer, we may know something about its
5916 alignment. If PUSH_ROUNDING is defined, it is possible for the
5917 stack to be momentarily aligned only to that amount, so we pick
5918 the least alignment. */
5920 if (x == stack_pointer_rtx)
5922 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
5924 #ifdef PUSH_ROUNDING
5925 sp_alignment = MIN (PUSH_ROUNDING (1), sp_alignment);
5928 return significant & ~ (sp_alignment - 1);
5932 /* If X is a register whose value we can find, use that value.
5933 Otherwise, use the previously-computed significant bits for this
5936 tem = get_last_value (x);
5938 return significant_bits (tem, mode);
5939 else if (significant_valid && reg_significant[REGNO (x)])
5940 return reg_significant[REGNO (x)] & significant;
5947 #ifdef BYTE_LOADS_ZERO_EXTEND
5949 /* In many, if not most, RISC machines, reading a byte from memory
5950 zeros the rest of the register. Noticing that fact saves a lot
5951 of extra zero-extends. */
5952 significant &= GET_MODE_MASK (GET_MODE (x));
5956 #if STORE_FLAG_VALUE == 1
5963 if (GET_MODE_CLASS (mode) == MODE_INT)
5966 /* A comparison operation only sets the bits given by its mode. The
5967 rest are set undefined. */
5968 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
5969 significant |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x)));
5974 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
5975 == GET_MODE_BITSIZE (GET_MODE (x)))
5978 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
5979 significant |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x)));
5983 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
5984 == GET_MODE_BITSIZE (GET_MODE (x)))
5989 significant &= (significant_bits (XEXP (x, 0), mode)
5990 & GET_MODE_MASK (mode));
5994 significant &= significant_bits (XEXP (x, 0), mode);
5995 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
5996 significant &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
6000 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
6001 Otherwise, show all the bits in the outer mode but not the inner
6003 inner_sig = significant_bits (XEXP (x, 0), mode);
6004 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
6006 inner_sig &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
6009 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
6010 inner_sig |= (GET_MODE_MASK (mode)
6011 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
6014 significant &= inner_sig;
6018 significant &= (significant_bits (XEXP (x, 0), mode)
6019 & significant_bits (XEXP (x, 1), mode));
6023 case UMIN: case UMAX: case SMIN: case SMAX:
6024 significant &= (significant_bits (XEXP (x, 0), mode)
6025 | significant_bits (XEXP (x, 1), mode));
6028 case PLUS: case MINUS:
6030 case DIV: case UDIV:
6031 case MOD: case UMOD:
6032 /* We can apply the rules of arithmetic to compute the number of
6033 high- and low-order zero bits of these operations. We start by
6034 computing the width (position of the highest-order non-zero bit)
6035 and the number of low-order zero bits for each value. */
6037 unsigned HOST_WIDE_INT sig0 = significant_bits (XEXP (x, 0), mode);
6038 unsigned HOST_WIDE_INT sig1 = significant_bits (XEXP (x, 1), mode);
6039 int width0 = floor_log2 (sig0) + 1;
6040 int width1 = floor_log2 (sig1) + 1;
6041 int low0 = floor_log2 (sig0 & -sig0);
6042 int low1 = floor_log2 (sig1 & -sig1);
6043 int op0_maybe_minusp = (sig0 & (1 << (mode_width - 1)));
6044 int op1_maybe_minusp = (sig1 & (1 << (mode_width - 1)));
6045 int result_width = mode_width;
6051 result_width = MAX (width0, width1) + 1;
6052 result_low = MIN (low0, low1);
6055 result_low = MIN (low0, low1);
6058 result_width = width0 + width1;
6059 result_low = low0 + low1;
6062 if (! op0_maybe_minusp && ! op1_maybe_minusp)
6063 result_width = width0;
6066 result_width = width0;
6069 if (! op0_maybe_minusp && ! op1_maybe_minusp)
6070 result_width = MIN (width0, width1);
6071 result_low = MIN (low0, low1);
6074 result_width = MIN (width0, width1);
6075 result_low = MIN (low0, low1);
6079 if (result_width < mode_width)
6080 significant &= ((HOST_WIDE_INT) 1 << result_width) - 1;
6083 significant &= ~ (((HOST_WIDE_INT) 1 << result_low) - 1);
6088 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6089 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
6090 significant &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
6094 /* If this is a SUBREG formed for a promoted variable that has
6095 been zero-extended, we know that at least the high-order bits
6096 are zero, though others might be too. */
6098 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x))
6099 significant = (GET_MODE_MASK (GET_MODE (x))
6100 & significant_bits (SUBREG_REG (x), GET_MODE (x)));
6102 /* If the inner mode is a single word for both the host and target
6103 machines, we can compute this from which bits of the inner
6104 object are known significant. */
6105 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
6106 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
6107 <= HOST_BITS_PER_WIDE_INT))
6109 significant &= significant_bits (SUBREG_REG (x), mode);
6110 #if ! defined(BYTE_LOADS_ZERO_EXTEND) && ! defined(BYTE_LOADS_SIGN_EXTEND)
6111 /* On many CISC machines, accessing an object in a wider mode
6112 causes the high-order bits to become undefined. So they are
6113 not known to be zero. */
6114 if (GET_MODE_SIZE (GET_MODE (x))
6115 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6116 significant |= (GET_MODE_MASK (GET_MODE (x))
6117 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
6127 /* The significant bits are in two classes: any bits within MODE
6128 that aren't in GET_MODE (x) are always significant. The rest of the
6129 significant bits are those that are significant in the operand of
6130 the shift when shifted the appropriate number of bits. This
6131 shows that high-order bits are cleared by the right shift and
6132 low-order bits by left shifts. */
6133 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6134 && INTVAL (XEXP (x, 1)) >= 0
6135 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
6137 enum machine_mode inner_mode = GET_MODE (x);
6138 int width = GET_MODE_BITSIZE (inner_mode);
6139 int count = INTVAL (XEXP (x, 1));
6140 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
6141 unsigned HOST_WIDE_INT op_significant
6142 = significant_bits (XEXP (x, 0), mode);
6143 unsigned HOST_WIDE_INT inner = op_significant & mode_mask;
6144 unsigned HOST_WIDE_INT outer = 0;
6146 if (mode_width > width)
6147 outer = (op_significant & significant & ~ mode_mask);
6149 if (code == LSHIFTRT)
6151 else if (code == ASHIFTRT)
6155 /* If the sign bit was significant at before the shift, we
6156 need to mark all the places it could have been copied to
6157 by the shift significant. */
6158 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
6159 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
6161 else if (code == LSHIFT || code == ASHIFT)
6164 inner = ((inner << (count % width)
6165 | (inner >> (width - (count % width)))) & mode_mask);
6167 significant &= (outer | inner);
6172 /* This is at most the number of bits in the mode. */
6173 significant = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1;
6177 significant &= (significant_bits (XEXP (x, 1), mode)
6178 | significant_bits (XEXP (x, 2), mode));
6185 /* Return the number of bits at the high-order end of X that are known to
6186 be equal to the sign bit. This number will always be between 1 and
6187 the number of bits in the mode of X. MODE is the mode to be used
6188 if X is VOIDmode. */
6191 num_sign_bit_copies (x, mode)
6193 enum machine_mode mode;
6195 enum rtx_code code = GET_CODE (x);
6197 int num0, num1, result;
6198 unsigned HOST_WIDE_INT sig;
6201 /* If we weren't given a mode, use the mode of X. If the mode is still
6202 VOIDmode, we don't know anything. */
6204 if (mode == VOIDmode)
6205 mode = GET_MODE (x);
6207 if (mode == VOIDmode)
6210 bitwidth = GET_MODE_BITSIZE (mode);
6215 if (significant_valid && reg_sign_bit_copies[REGNO (x)] != 0)
6216 return reg_sign_bit_copies[REGNO (x)];
6218 tem = get_last_value (x);
6220 return num_sign_bit_copies (tem, mode);
6223 #ifdef BYTE_LOADS_SIGN_EXTEND
6225 /* Some RISC machines sign-extend all loads of smaller than a word. */
6226 return MAX (1, bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1);
6230 /* If the constant is negative, take its 1's complement and remask.
6231 Then see how many zero bits we have. */
6232 sig = INTVAL (x) & GET_MODE_MASK (mode);
6233 if (sig & ((HOST_WIDE_INT) 1 << (bitwidth - 1)))
6234 sig = (~ sig) & GET_MODE_MASK (mode);
6236 return (sig == 0 ? bitwidth : bitwidth - floor_log2 (sig) - 1);
6239 /* If this is a SUBREG for a promoted object that is sign-extended
6240 and we are looking at it in a wider mode, we know that at least the
6241 high-order bits are known to be sign bit copies. */
6243 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
6244 return (GET_MODE_BITSIZE (mode) - GET_MODE_BITSIZE (GET_MODE (x))
6245 + num_sign_bit_copies (SUBREG_REG (x), GET_MODE (x)));
6247 /* For a smaller object, just ignore the high bits. */
6248 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
6250 num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode);
6251 return MAX (1, (num0
6252 - (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
6256 #if defined(BYTE_LOADS_ZERO_EXTEND) || defined(BYTE_LOADS_SIGN_EXTEND)
6257 /* For paradoxical SUBREGs, just look inside since, on machines with
6258 one of these defined, we assume that operations are actually
6259 performed on the full register. Note that we are passing MODE
6260 to the recursive call, so the number of sign bit copies will
6261 remain relative to that mode, not the inner mode. */
6263 if (GET_MODE_SIZE (GET_MODE (x))
6264 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6265 return num_sign_bit_copies (SUBREG_REG (x), mode);
6271 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6272 return MAX (1, bitwidth - INTVAL (XEXP (x, 1)));
6276 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6277 + num_sign_bit_copies (XEXP (x, 0), VOIDmode));
6280 /* For a smaller object, just ignore the high bits. */
6281 num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode);
6282 return MAX (1, (num0 - (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6286 return num_sign_bit_copies (XEXP (x, 0), mode);
6288 case ROTATE: case ROTATERT:
6289 /* If we are rotating left by a number of bits less than the number
6290 of sign bit copies, we can just subtract that amount from the
6292 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6293 && INTVAL (XEXP (x, 1)) >= 0 && INTVAL (XEXP (x, 1)) < bitwidth)
6295 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
6296 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
6297 : bitwidth - INTVAL (XEXP (x, 1))));
6302 /* In general, this subtracts one sign bit copy. But if the value
6303 is known to be positive, the number of sign bit copies is the
6304 same as that of the input. Finally, if the input has just one
6305 significant bit, all the bits are copies of the sign bit. */
6306 sig = significant_bits (XEXP (x, 0), mode);
6310 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
6312 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & sig))
6317 case IOR: case AND: case XOR:
6318 case SMIN: case SMAX: case UMIN: case UMAX:
6319 /* Logical operations will preserve the number of sign-bit copies.
6320 MIN and MAX operations always return one of the operands. */
6321 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
6322 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
6323 return MIN (num0, num1);
6325 case PLUS: case MINUS:
6326 /* For addition and subtraction, we can have a 1-bit carry. However,
6327 if we are subtracting 1 from a positive number, there will not
6328 be such a carry. Furthermore, if the positive number is known to
6329 be 0 or 1, we know the result is either -1 or 0. */
6331 if (code == PLUS && XEXP (x, 1) == constm1_rtx)
6333 sig = significant_bits (XEXP (x, 0), mode);
6334 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & sig) == 0)
6335 return (sig == 1 || sig == 0 ? bitwidth
6336 : bitwidth - floor_log2 (sig));
6339 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
6340 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
6341 return MAX (1, MIN (num0, num1) - 1);
6344 /* The number of bits of the product is the sum of the number of
6345 bits of both terms. However, unless one of the terms if known
6346 to be positive, we must allow for an additional bit since negating
6347 a negative number can remove one sign bit copy. */
6349 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
6350 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
6352 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
6354 && ((significant_bits (XEXP (x, 0), mode)
6355 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
6356 && (significant_bits (XEXP (x, 1), mode)
6357 & ((HOST_WIDE_INT) 1 << (bitwidth - 1)) != 0))
6360 return MAX (1, result);
6363 /* The result must be <= the first operand. */
6364 return num_sign_bit_copies (XEXP (x, 0), mode);
6367 /* The result must be <= the scond operand. */
6368 return num_sign_bit_copies (XEXP (x, 1), mode);
6371 /* Similar to unsigned division, except that we have to worry about
6372 the case where the divisor is negative, in which case we have
6374 result = num_sign_bit_copies (XEXP (x, 0), mode);
6376 && (significant_bits (XEXP (x, 1), mode)
6377 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
6383 result = num_sign_bit_copies (XEXP (x, 1), mode);
6385 && (significant_bits (XEXP (x, 1), mode)
6386 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
6392 /* Shifts by a constant add to the number of bits equal to the
6394 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
6395 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6396 && INTVAL (XEXP (x, 1)) > 0)
6397 num0 = MIN (bitwidth, num0 + INTVAL (XEXP (x, 1)));
6403 /* Left shifts destroy copies. */
6404 if (GET_CODE (XEXP (x, 1)) != CONST_INT
6405 || INTVAL (XEXP (x, 1)) < 0
6406 || INTVAL (XEXP (x, 1)) >= bitwidth)
6409 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
6410 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
6413 num0 = num_sign_bit_copies (XEXP (x, 1), mode);
6414 num1 = num_sign_bit_copies (XEXP (x, 2), mode);
6415 return MIN (num0, num1);
6417 #if STORE_FLAG_VALUE == -1
6418 case EQ: case NE: case GE: case GT: case LE: case LT:
6419 case GEU: case GTU: case LEU: case LTU:
6424 /* If we haven't been able to figure it out by one of the above rules,
6425 see if some of the high-order bits are known to be zero. If so,
6426 count those bits and return one less than that amount. */
6428 sig = significant_bits (x, mode);
6429 return sig == GET_MODE_MASK (mode) ? 1 : bitwidth - floor_log2 (sig) - 1;
6432 /* Return the number of "extended" bits there are in X, when interpreted
6433 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
6434 unsigned quantities, this is the number of high-order zero bits.
6435 For signed quantities, this is the number of copies of the sign bit
6436 minus 1. In both case, this function returns the number of "spare"
6437 bits. For example, if two quantities for which this function returns
6438 at least 1 are added, the addition is known not to overflow.
6440 This function will always return 0 unless called during combine, which
6441 implies that it must be called from a define_split. */
6444 extended_count (x, mode, unsignedp)
6446 enum machine_mode mode;
6449 if (significant_valid == 0)
6453 ? (GET_MODE_BITSIZE (mode) - 1
6454 - floor_log2 (significant_bits (x, mode)))
6455 : num_sign_bit_copies (x, mode) - 1);
6458 /* This function is called from `simplify_shift_const' to merge two
6459 outer operations. Specifically, we have already found that we need
6460 to perform operation *POP0 with constant *PCONST0 at the outermost
6461 position. We would now like to also perform OP1 with constant CONST1
6462 (with *POP0 being done last).
6464 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
6465 the resulting operation. *PCOMP_P is set to 1 if we would need to
6466 complement the innermost operand, otherwise it is unchanged.
6468 MODE is the mode in which the operation will be done. No bits outside
6469 the width of this mode matter. It is assumed that the width of this mode
6470 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
6472 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
6473 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
6474 result is simply *PCONST0.
6476 If the resulting operation cannot be expressed as one operation, we
6477 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
6480 merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
6481 enum rtx_code *pop0;
6482 HOST_WIDE_INT *pconst0;
6484 HOST_WIDE_INT const1;
6485 enum machine_mode mode;
6488 enum rtx_code op0 = *pop0;
6489 HOST_WIDE_INT const0 = *pconst0;
6491 const0 &= GET_MODE_MASK (mode);
6492 const1 &= GET_MODE_MASK (mode);
6494 /* If OP0 is an AND, clear unimportant bits in CONST1. */
6498 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
6501 if (op1 == NIL || op0 == SET)
6504 else if (op0 == NIL)
6505 op0 = op1, const0 = const1;
6507 else if (op0 == op1)
6529 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
6530 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
6533 /* If the two constants aren't the same, we can't do anything. The
6534 remaining six cases can all be done. */
6535 else if (const0 != const1)
6543 /* (a & b) | b == b */
6545 else /* op1 == XOR */
6546 /* (a ^ b) | b == a | b */
6552 /* (a & b) ^ b == (~a) & b */
6553 op0 = AND, *pcomp_p = 1;
6554 else /* op1 == IOR */
6555 /* (a | b) ^ b == a & ~b */
6556 op0 = AND, *pconst0 = ~ const0;
6561 /* (a | b) & b == b */
6563 else /* op1 == XOR */
6564 /* (a ^ b) & b) == (~a) & b */
6569 /* Check for NO-OP cases. */
6570 const0 &= GET_MODE_MASK (mode);
6572 && (op0 == IOR || op0 == XOR || op0 == PLUS))
6574 else if (const0 == 0 && op0 == AND)
6576 else if (const0 == GET_MODE_MASK (mode) && op0 == AND)
6585 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
6586 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
6587 that we started with.
6589 The shift is normally computed in the widest mode we find in VAROP, as
6590 long as it isn't a different number of words than RESULT_MODE. Exceptions
6591 are ASHIFTRT and ROTATE, which are always done in their original mode, */
6594 simplify_shift_const (x, code, result_mode, varop, count)
6597 enum machine_mode result_mode;
6601 enum rtx_code orig_code = code;
6602 int orig_count = count;
6603 enum machine_mode mode = result_mode;
6604 enum machine_mode shift_mode, tmode;
6606 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
6607 /* We form (outer_op (code varop count) (outer_const)). */
6608 enum rtx_code outer_op = NIL;
6609 HOST_WIDE_INT outer_const;
6611 int complement_p = 0;
6614 /* If we were given an invalid count, don't do anything except exactly
6615 what was requested. */
6617 if (count < 0 || count > GET_MODE_BITSIZE (mode))
6622 return gen_rtx (code, mode, varop, GEN_INT (count));
6625 /* Unless one of the branches of the `if' in this loop does a `continue',
6626 we will `break' the loop after the `if'. */
6630 /* If we have an operand of (clobber (const_int 0)), just return that
6632 if (GET_CODE (varop) == CLOBBER)
6635 /* If we discovered we had to complement VAROP, leave. Making a NOT
6636 here would cause an infinite loop. */
6640 /* Convert ROTATETRT to ROTATE. */
6641 if (code == ROTATERT)
6642 code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count;
6644 /* Canonicalize LSHIFT to ASHIFT. */
6648 /* We need to determine what mode we will do the shift in. If the
6649 shift is a ASHIFTRT or ROTATE, we must always do it in the mode it
6650 was originally done in. Otherwise, we can do it in MODE, the widest
6651 mode encountered. */
6652 shift_mode = (code == ASHIFTRT || code == ROTATE ? result_mode : mode);
6654 /* Handle cases where the count is greater than the size of the mode
6655 minus 1. For ASHIFT, use the size minus one as the count (this can
6656 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
6657 take the count modulo the size. For other shifts, the result is
6660 Since these shifts are being produced by the compiler by combining
6661 multiple operations, each of which are defined, we know what the
6662 result is supposed to be. */
6664 if (count > GET_MODE_BITSIZE (shift_mode) - 1)
6666 if (code == ASHIFTRT)
6667 count = GET_MODE_BITSIZE (shift_mode) - 1;
6668 else if (code == ROTATE || code == ROTATERT)
6669 count %= GET_MODE_BITSIZE (shift_mode);
6672 /* We can't simply return zero because there may be an
6680 /* Negative counts are invalid and should not have been made (a
6681 programmer-specified negative count should have been handled
6686 /* An arithmetic right shift of a quantity known to be -1 or 0
6688 if (code == ASHIFTRT
6689 && (num_sign_bit_copies (varop, shift_mode)
6690 == GET_MODE_BITSIZE (shift_mode)))
6696 /* We simplify the tests below and elsewhere by converting
6697 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
6698 `make_compound_operation' will convert it to a ASHIFTRT for
6699 those machines (such as Vax) that don't have a LSHIFTRT. */
6700 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
6702 && ((significant_bits (varop, shift_mode)
6703 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
6707 switch (GET_CODE (varop))
6713 new = expand_compound_operation (varop);
6722 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
6723 minus the width of a smaller mode, we can do this with a
6724 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
6725 if ((code == ASHIFTRT || code == LSHIFTRT)
6726 && ! mode_dependent_address_p (XEXP (varop, 0))
6727 && ! MEM_VOLATILE_P (varop)
6728 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
6729 MODE_INT, 1)) != BLKmode)
6731 #if BYTES_BIG_ENDIAN
6732 new = gen_rtx (MEM, tmode, XEXP (varop, 0));
6734 new = gen_rtx (MEM, tmode,
6735 plus_constant (XEXP (varop, 0),
6736 count / BITS_PER_UNIT));
6737 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (varop);
6738 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (varop);
6739 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (varop);
6741 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
6742 : ZERO_EXTEND, mode, new);
6749 /* Similar to the case above, except that we can only do this if
6750 the resulting mode is the same as that of the underlying
6751 MEM and adjust the address depending on the *bits* endianness
6752 because of the way that bit-field extract insns are defined. */
6753 if ((code == ASHIFTRT || code == LSHIFTRT)
6754 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
6755 MODE_INT, 1)) != BLKmode
6756 && tmode == GET_MODE (XEXP (varop, 0)))
6759 new = XEXP (varop, 0);
6761 new = copy_rtx (XEXP (varop, 0));
6762 SUBST (XEXP (new, 0),
6763 plus_constant (XEXP (new, 0),
6764 count / BITS_PER_UNIT));
6767 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
6768 : ZERO_EXTEND, mode, new);
6775 /* If VAROP is a SUBREG, strip it as long as the inner operand has
6776 the same number of words as what we've seen so far. Then store
6777 the widest mode in MODE. */
6778 if (SUBREG_WORD (varop) == 0
6779 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
6780 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
6783 varop = SUBREG_REG (varop);
6784 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
6785 mode = GET_MODE (varop);
6791 /* Some machines use MULT instead of ASHIFT because MULT
6792 is cheaper. But it is still better on those machines to
6793 merge two shifts into one. */
6794 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
6795 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
6797 varop = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
6798 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));;
6804 /* Similar, for when divides are cheaper. */
6805 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
6806 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
6808 varop = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
6809 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
6815 /* If we are extracting just the sign bit of an arithmetic right
6816 shift, that shift is not needed. */
6817 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1)
6819 varop = XEXP (varop, 0);
6823 /* ... fall through ... */
6829 /* Here we have two nested shifts. The result is usually the
6830 AND of a new shift with a mask. We compute the result below. */
6831 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
6832 && INTVAL (XEXP (varop, 1)) >= 0
6833 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
6834 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
6835 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
6837 enum rtx_code first_code = GET_CODE (varop);
6838 int first_count = INTVAL (XEXP (varop, 1));
6839 unsigned HOST_WIDE_INT mask;
6843 if (first_code == LSHIFT)
6844 first_code = ASHIFT;
6846 /* We have one common special case. We can't do any merging if
6847 the inner code is an ASHIFTRT of a smaller mode. However, if
6848 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
6849 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
6850 we can convert it to
6851 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
6852 This simplifies certain SIGN_EXTEND operations. */
6853 if (code == ASHIFT && first_code == ASHIFTRT
6854 && (GET_MODE_BITSIZE (result_mode)
6855 - GET_MODE_BITSIZE (GET_MODE (varop))) == count)
6857 /* C3 has the low-order C1 bits zero. */
6859 mask = (GET_MODE_MASK (mode)
6860 & ~ (((HOST_WIDE_INT) 1 << first_count) - 1));
6862 varop = simplify_and_const_int (NULL_RTX, result_mode,
6863 XEXP (varop, 0), mask);
6864 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
6866 count = first_count;
6871 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
6872 than C1 high-order bits equal to the sign bit, we can convert
6873 this to either an ASHIFT or a ASHIFTRT depending on the
6876 We cannot do this if VAROP's mode is not SHIFT_MODE. */
6878 if (code == ASHIFTRT && first_code == ASHIFT
6879 && GET_MODE (varop) == shift_mode
6880 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
6883 count -= first_count;
6885 count = - count, code = ASHIFT;
6886 varop = XEXP (varop, 0);
6890 /* There are some cases we can't do. If CODE is ASHIFTRT,
6891 we can only do this if FIRST_CODE is also ASHIFTRT.
6893 We can't do the case when CODE is ROTATE and FIRST_CODE is
6896 If the mode of this shift is not the mode of the outer shift,
6897 we can't do this if either shift is ASHIFTRT or ROTATE.
6899 Finally, we can't do any of these if the mode is too wide
6900 unless the codes are the same.
6902 Handle the case where the shift codes are the same
6905 if (code == first_code)
6907 if (GET_MODE (varop) != result_mode
6908 && (code == ASHIFTRT || code == ROTATE))
6911 count += first_count;
6912 varop = XEXP (varop, 0);
6916 if (code == ASHIFTRT
6917 || (code == ROTATE && first_code == ASHIFTRT)
6918 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
6919 || (GET_MODE (varop) != result_mode
6920 && (first_code == ASHIFTRT || first_code == ROTATE
6921 || code == ROTATE)))
6924 /* To compute the mask to apply after the shift, shift the
6925 significant bits of the inner shift the same way the
6926 outer shift will. */
6928 mask_rtx = GEN_INT (significant_bits (varop, GET_MODE (varop)));
6931 = simplify_binary_operation (code, result_mode, mask_rtx,
6934 /* Give up if we can't compute an outer operation to use. */
6936 || GET_CODE (mask_rtx) != CONST_INT
6937 || ! merge_outer_ops (&outer_op, &outer_const, AND,
6939 result_mode, &complement_p))
6942 /* If the shifts are in the same direction, we add the
6943 counts. Otherwise, we subtract them. */
6944 if ((code == ASHIFTRT || code == LSHIFTRT)
6945 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
6946 count += first_count;
6948 count -= first_count;
6950 /* If COUNT is positive, the new shift is usually CODE,
6951 except for the two exceptions below, in which case it is
6952 FIRST_CODE. If the count is negative, FIRST_CODE should
6955 && ((first_code == ROTATE && code == ASHIFT)
6956 || (first_code == ASHIFTRT && code == LSHIFTRT)))
6959 code = first_code, count = - count;
6961 varop = XEXP (varop, 0);
6965 /* If we have (A << B << C) for any shift, we can convert this to
6966 (A << C << B). This wins if A is a constant. Only try this if
6967 B is not a constant. */
6969 else if (GET_CODE (varop) == code
6970 && GET_CODE (XEXP (varop, 1)) != CONST_INT
6972 = simplify_binary_operation (code, mode,
6976 varop = gen_rtx_combine (code, mode, new, XEXP (varop, 1));
6983 /* Make this fit the case below. */
6984 varop = gen_rtx_combine (XOR, mode, XEXP (varop, 0),
6985 GEN_INT (GET_MODE_MASK (mode)));
6991 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
6992 with C the size of VAROP - 1 and the shift is logical if
6993 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
6994 we have an (le X 0) operation. If we have an arithmetic shift
6995 and STORE_FLAG_VALUE is 1 or we have a logical shift with
6996 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
6998 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
6999 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
7000 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7001 && (code == LSHIFTRT || code == ASHIFTRT)
7002 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
7003 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
7006 varop = gen_rtx_combine (LE, GET_MODE (varop), XEXP (varop, 1),
7009 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
7010 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
7015 /* If we have (shift (logical)), move the logical to the outside
7016 to allow it to possibly combine with another logical and the
7017 shift to combine with another shift. This also canonicalizes to
7018 what a ZERO_EXTRACT looks like. Also, some machines have
7019 (and (shift)) insns. */
7021 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
7022 && (new = simplify_binary_operation (code, result_mode,
7024 GEN_INT (count))) != 0
7025 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
7026 INTVAL (new), result_mode, &complement_p))
7028 varop = XEXP (varop, 0);
7032 /* If we can't do that, try to simplify the shift in each arm of the
7033 logical expression, make a new logical expression, and apply
7034 the inverse distributive law. */
7036 rtx lhs = simplify_shift_const (NULL_RTX, code, result_mode,
7037 XEXP (varop, 0), count);
7038 rtx rhs = simplify_shift_const (NULL_RTX, code, result_mode,
7039 XEXP (varop, 1), count);
7041 varop = gen_binary (GET_CODE (varop), result_mode, lhs, rhs);
7042 varop = apply_distributive_law (varop);
7049 /* convert (lshift (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
7050 says that the sign bit can be tested, FOO has mode MODE, C is
7051 GET_MODE_BITSIZE (MODE) - 1, and FOO has only the low-order bit
7054 && XEXP (varop, 1) == const0_rtx
7055 && GET_MODE (XEXP (varop, 0)) == result_mode
7056 && count == GET_MODE_BITSIZE (result_mode) - 1
7057 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
7058 && ((STORE_FLAG_VALUE
7059 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (result_mode) - 1))))
7060 && significant_bits (XEXP (varop, 0), result_mode) == 1
7061 && merge_outer_ops (&outer_op, &outer_const, XOR,
7062 (HOST_WIDE_INT) 1, result_mode,
7065 varop = XEXP (varop, 0);
7072 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
7073 than the number of bits in the mode is equivalent to A. */
7074 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
7075 && significant_bits (XEXP (varop, 0), result_mode) == 1)
7077 varop = XEXP (varop, 0);
7082 /* NEG commutes with ASHIFT since it is multiplication. Move the
7083 NEG outside to allow shifts to combine. */
7085 && merge_outer_ops (&outer_op, &outer_const, NEG,
7086 (HOST_WIDE_INT) 0, result_mode,
7089 varop = XEXP (varop, 0);
7095 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
7096 is one less than the number of bits in the mode is
7097 equivalent to (xor A 1). */
7098 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
7099 && XEXP (varop, 1) == constm1_rtx
7100 && significant_bits (XEXP (varop, 0), result_mode) == 1
7101 && merge_outer_ops (&outer_op, &outer_const, XOR,
7102 (HOST_WIDE_INT) 1, result_mode,
7106 varop = XEXP (varop, 0);
7110 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
7111 significant in BAR are those being shifted out and those
7112 bits are known zero in FOO, we can replace the PLUS with FOO.
7113 Similarly in the other operand order. This code occurs when
7114 we are computing the size of a variable-size array. */
7116 if ((code == ASHIFTRT || code == LSHIFTRT)
7117 && count < HOST_BITS_PER_WIDE_INT
7118 && significant_bits (XEXP (varop, 1), result_mode) >> count == 0
7119 && (significant_bits (XEXP (varop, 1), result_mode)
7120 & significant_bits (XEXP (varop, 0), result_mode)) == 0)
7122 varop = XEXP (varop, 0);
7125 else if ((code == ASHIFTRT || code == LSHIFTRT)
7126 && count < HOST_BITS_PER_WIDE_INT
7127 && 0 == (significant_bits (XEXP (varop, 0), result_mode)
7129 && 0 == (significant_bits (XEXP (varop, 0), result_mode)
7130 & significant_bits (XEXP (varop, 1),
7133 varop = XEXP (varop, 1);
7137 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
7139 && GET_CODE (XEXP (varop, 1)) == CONST_INT
7140 && (new = simplify_binary_operation (ASHIFT, result_mode,
7142 GEN_INT (count))) != 0
7143 && merge_outer_ops (&outer_op, &outer_const, PLUS,
7144 INTVAL (new), result_mode, &complement_p))
7146 varop = XEXP (varop, 0);
7152 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
7153 with C the size of VAROP - 1 and the shift is logical if
7154 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
7155 we have a (gt X 0) operation. If the shift is arithmetic with
7156 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
7157 we have a (neg (gt X 0)) operation. */
7159 if (GET_CODE (XEXP (varop, 0)) == ASHIFTRT
7160 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
7161 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7162 && (code == LSHIFTRT || code == ASHIFTRT)
7163 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
7164 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
7165 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
7168 varop = gen_rtx_combine (GT, GET_MODE (varop), XEXP (varop, 1),
7171 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
7172 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
7182 /* We need to determine what mode to do the shift in. If the shift is
7183 a ASHIFTRT or ROTATE, we must always do it in the mode it was originally
7184 done in. Otherwise, we can do it in MODE, the widest mode encountered.
7185 The code we care about is that of the shift that will actually be done,
7186 not the shift that was originally requested. */
7187 shift_mode = (code == ASHIFTRT || code == ROTATE ? result_mode : mode);
7189 /* We have now finished analyzing the shift. The result should be
7190 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
7191 OUTER_OP is non-NIL, it is an operation that needs to be applied
7192 to the result of the shift. OUTER_CONST is the relevant constant,
7193 but we must turn off all bits turned off in the shift.
7195 If we were passed a value for X, see if we can use any pieces of
7196 it. If not, make new rtx. */
7198 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
7199 && GET_CODE (XEXP (x, 1)) == CONST_INT
7200 && INTVAL (XEXP (x, 1)) == count)
7201 const_rtx = XEXP (x, 1);
7203 const_rtx = GEN_INT (count);
7205 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
7206 && GET_MODE (XEXP (x, 0)) == shift_mode
7207 && SUBREG_REG (XEXP (x, 0)) == varop)
7208 varop = XEXP (x, 0);
7209 else if (GET_MODE (varop) != shift_mode)
7210 varop = gen_lowpart_for_combine (shift_mode, varop);
7212 /* If we can't make the SUBREG, try to return what we were given. */
7213 if (GET_CODE (varop) == CLOBBER)
7214 return x ? x : varop;
7216 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
7221 if (x == 0 || GET_CODE (x) != code || GET_MODE (x) != shift_mode)
7222 x = gen_rtx_combine (code, shift_mode, varop, const_rtx);
7224 SUBST (XEXP (x, 0), varop);
7225 SUBST (XEXP (x, 1), const_rtx);
7228 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
7229 turn off all the bits that the shift would have turned off. */
7230 if (orig_code == LSHIFTRT && result_mode != shift_mode)
7231 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
7232 GET_MODE_MASK (result_mode) >> orig_count);
7234 /* Do the remainder of the processing in RESULT_MODE. */
7235 x = gen_lowpart_for_combine (result_mode, x);
7237 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
7240 x = gen_unary (NOT, result_mode, x);
7242 if (outer_op != NIL)
7244 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
7245 outer_const &= GET_MODE_MASK (result_mode);
7247 if (outer_op == AND)
7248 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
7249 else if (outer_op == SET)
7250 /* This means that we have determined that the result is
7251 equivalent to a constant. This should be rare. */
7252 x = GEN_INT (outer_const);
7253 else if (GET_RTX_CLASS (outer_op) == '1')
7254 x = gen_unary (outer_op, result_mode, x);
7256 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
7262 /* Like recog, but we receive the address of a pointer to a new pattern.
7263 We try to match the rtx that the pointer points to.
7264 If that fails, we may try to modify or replace the pattern,
7265 storing the replacement into the same pointer object.
7267 Modifications include deletion or addition of CLOBBERs.
7269 PNOTES is a pointer to a location where any REG_UNUSED notes added for
7270 the CLOBBERs are placed.
7272 The value is the final insn code from the pattern ultimately matched,
7276 recog_for_combine (pnewpat, insn, pnotes)
7281 register rtx pat = *pnewpat;
7282 int insn_code_number;
7283 int num_clobbers_to_add = 0;
7287 /* Is the result of combination a valid instruction? */
7288 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
7290 /* If it isn't, there is the possibility that we previously had an insn
7291 that clobbered some register as a side effect, but the combined
7292 insn doesn't need to do that. So try once more without the clobbers
7293 unless this represents an ASM insn. */
7295 if (insn_code_number < 0 && ! check_asm_operands (pat)
7296 && GET_CODE (pat) == PARALLEL)
7300 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
7301 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
7304 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
7308 SUBST_INT (XVECLEN (pat, 0), pos);
7311 pat = XVECEXP (pat, 0, 0);
7313 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
7316 /* If we had any clobbers to add, make a new pattern than contains
7317 them. Then check to make sure that all of them are dead. */
7318 if (num_clobbers_to_add)
7320 rtx newpat = gen_rtx (PARALLEL, VOIDmode,
7321 gen_rtvec (GET_CODE (pat) == PARALLEL
7322 ? XVECLEN (pat, 0) + num_clobbers_to_add
7323 : num_clobbers_to_add + 1));
7325 if (GET_CODE (pat) == PARALLEL)
7326 for (i = 0; i < XVECLEN (pat, 0); i++)
7327 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
7329 XVECEXP (newpat, 0, 0) = pat;
7331 add_clobbers (newpat, insn_code_number);
7333 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
7334 i < XVECLEN (newpat, 0); i++)
7336 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
7337 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
7339 notes = gen_rtx (EXPR_LIST, REG_UNUSED,
7340 XEXP (XVECEXP (newpat, 0, i), 0), notes);
7348 return insn_code_number;
7351 /* Like gen_lowpart but for use by combine. In combine it is not possible
7352 to create any new pseudoregs. However, it is safe to create
7353 invalid memory addresses, because combine will try to recognize
7354 them and all they will do is make the combine attempt fail.
7356 If for some reason this cannot do its job, an rtx
7357 (clobber (const_int 0)) is returned.
7358 An insn containing that will not be recognized. */
7363 gen_lowpart_for_combine (mode, x)
7364 enum machine_mode mode;
7369 if (GET_MODE (x) == mode)
7372 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
7373 return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
7375 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
7376 won't know what to do. So we will strip off the SUBREG here and
7377 process normally. */
7378 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
7381 if (GET_MODE (x) == mode)
7385 result = gen_lowpart_common (mode, x);
7389 if (GET_CODE (x) == MEM)
7391 register int offset = 0;
7394 /* Refuse to work on a volatile memory ref or one with a mode-dependent
7396 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
7397 return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
7399 /* If we want to refer to something bigger than the original memref,
7400 generate a perverse subreg instead. That will force a reload
7401 of the original memref X. */
7402 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
7403 return gen_rtx (SUBREG, mode, x, 0);
7405 #if WORDS_BIG_ENDIAN
7406 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
7407 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
7409 #if BYTES_BIG_ENDIAN
7410 /* Adjust the address so that the address-after-the-data
7412 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
7413 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
7415 new = gen_rtx (MEM, mode, plus_constant (XEXP (x, 0), offset));
7416 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (x);
7417 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (x);
7418 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (x);
7422 /* If X is a comparison operator, rewrite it in a new mode. This
7423 probably won't match, but may allow further simplifications. */
7424 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
7425 return gen_rtx_combine (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
7427 /* If we couldn't simplify X any other way, just enclose it in a
7428 SUBREG. Normally, this SUBREG won't match, but some patterns may
7429 include an explicit SUBREG or we may simplify it further in combine. */
7434 if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
7435 word = ((GET_MODE_SIZE (GET_MODE (x))
7436 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
7438 return gen_rtx (SUBREG, mode, x, word);
7442 /* Make an rtx expression. This is a subset of gen_rtx and only supports
7443 expressions of 1, 2, or 3 operands, each of which are rtx expressions.
7445 If the identical expression was previously in the insn (in the undobuf),
7446 it will be returned. Only if it is not found will a new expression
7451 gen_rtx_combine (va_alist)
7456 enum machine_mode mode;
7464 code = va_arg (p, enum rtx_code);
7465 mode = va_arg (p, enum machine_mode);
7466 n_args = GET_RTX_LENGTH (code);
7467 fmt = GET_RTX_FORMAT (code);
7469 if (n_args == 0 || n_args > 3)
7472 /* Get each arg and verify that it is supposed to be an expression. */
7473 for (j = 0; j < n_args; j++)
7478 args[j] = va_arg (p, rtx);
7481 /* See if this is in undobuf. Be sure we don't use objects that came
7482 from another insn; this could produce circular rtl structures. */
7484 for (i = previous_num_undos; i < undobuf.num_undo; i++)
7485 if (!undobuf.undo[i].is_int
7486 && GET_CODE (undobuf.undo[i].old_contents.rtx) == code
7487 && GET_MODE (undobuf.undo[i].old_contents.rtx) == mode)
7489 for (j = 0; j < n_args; j++)
7490 if (XEXP (undobuf.undo[i].old_contents.rtx, j) != args[j])
7494 return undobuf.undo[i].old_contents.rtx;
7497 /* Otherwise make a new rtx. We know we have 1, 2, or 3 args.
7498 Use rtx_alloc instead of gen_rtx because it's faster on RISC. */
7499 rt = rtx_alloc (code);
7500 PUT_MODE (rt, mode);
7501 XEXP (rt, 0) = args[0];
7504 XEXP (rt, 1) = args[1];
7506 XEXP (rt, 2) = args[2];
7511 /* These routines make binary and unary operations by first seeing if they
7512 fold; if not, a new expression is allocated. */
7515 gen_binary (code, mode, op0, op1)
7517 enum machine_mode mode;
7523 if (GET_RTX_CLASS (code) == 'c'
7524 && (GET_CODE (op0) == CONST_INT
7525 || (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)))
7526 tem = op0, op0 = op1, op1 = tem;
7528 if (GET_RTX_CLASS (code) == '<')
7530 enum machine_mode op_mode = GET_MODE (op0);
7531 if (op_mode == VOIDmode)
7532 op_mode = GET_MODE (op1);
7533 result = simplify_relational_operation (code, op_mode, op0, op1);
7536 result = simplify_binary_operation (code, mode, op0, op1);
7541 /* Put complex operands first and constants second. */
7542 if (GET_RTX_CLASS (code) == 'c'
7543 && ((CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
7544 || (GET_RTX_CLASS (GET_CODE (op0)) == 'o'
7545 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')
7546 || (GET_CODE (op0) == SUBREG
7547 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0))) == 'o'
7548 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')))
7549 return gen_rtx_combine (code, mode, op1, op0);
7551 return gen_rtx_combine (code, mode, op0, op1);
7555 gen_unary (code, mode, op0)
7557 enum machine_mode mode;
7560 rtx result = simplify_unary_operation (code, mode, op0, mode);
7565 return gen_rtx_combine (code, mode, op0);
7568 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
7569 comparison code that will be tested.
7571 The result is a possibly different comparison code to use. *POP0 and
7572 *POP1 may be updated.
7574 It is possible that we might detect that a comparison is either always
7575 true or always false. However, we do not perform general constant
7576 folding in combine, so this knowledge isn't useful. Such tautologies
7577 should have been detected earlier. Hence we ignore all such cases. */
7579 static enum rtx_code
7580 simplify_comparison (code, pop0, pop1)
7589 enum machine_mode mode, tmode;
7591 /* Try a few ways of applying the same transformation to both operands. */
7594 /* If both operands are the same constant shift, see if we can ignore the
7595 shift. We can if the shift is a rotate or if the bits shifted out of
7596 this shift are not significant for either input and if the type of
7597 comparison is compatible with the shift. */
7598 if (GET_CODE (op0) == GET_CODE (op1)
7599 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
7600 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
7601 || ((GET_CODE (op0) == LSHIFTRT
7602 || GET_CODE (op0) == ASHIFT || GET_CODE (op0) == LSHIFT)
7603 && (code != GT && code != LT && code != GE && code != LE))
7604 || (GET_CODE (op0) == ASHIFTRT
7605 && (code != GTU && code != LTU
7606 && code != GEU && code != GEU)))
7607 && GET_CODE (XEXP (op0, 1)) == CONST_INT
7608 && INTVAL (XEXP (op0, 1)) >= 0
7609 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
7610 && XEXP (op0, 1) == XEXP (op1, 1))
7612 enum machine_mode mode = GET_MODE (op0);
7613 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
7614 int shift_count = INTVAL (XEXP (op0, 1));
7616 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
7617 mask &= (mask >> shift_count) << shift_count;
7618 else if (GET_CODE (op0) == ASHIFT || GET_CODE (op0) == LSHIFT)
7619 mask = (mask & (mask << shift_count)) >> shift_count;
7621 if ((significant_bits (XEXP (op0, 0), mode) & ~ mask) == 0
7622 && (significant_bits (XEXP (op1, 0), mode) & ~ mask) == 0)
7623 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
7628 /* If both operands are AND's of a paradoxical SUBREG by constant, the
7629 SUBREGs are of the same mode, and, in both cases, the AND would
7630 be redundant if the comparison was done in the narrower mode,
7631 do the comparison in the narrower mode (e.g., we are AND'ing with 1
7632 and the operand's significant bits are 0xffffff01; in that case if
7633 we only care about QImode, we don't need the AND). This case occurs
7634 if the output mode of an scc insn is not SImode and
7635 STORE_FLAG_VALUE == 1 (e.g., the 386). */
7637 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
7638 && GET_CODE (XEXP (op0, 1)) == CONST_INT
7639 && GET_CODE (XEXP (op1, 1)) == CONST_INT
7640 && GET_CODE (XEXP (op0, 0)) == SUBREG
7641 && GET_CODE (XEXP (op1, 0)) == SUBREG
7642 && (GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)))
7643 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))
7644 && (GET_MODE (SUBREG_REG (XEXP (op0, 0)))
7645 == GET_MODE (SUBREG_REG (XEXP (op1, 0))))
7646 && (significant_bits (SUBREG_REG (XEXP (op0, 0)),
7647 GET_MODE (SUBREG_REG (XEXP (op0, 0))))
7648 & ~ INTVAL (XEXP (op0, 1))) == 0
7649 && (significant_bits (SUBREG_REG (XEXP (op1, 0)),
7650 GET_MODE (SUBREG_REG (XEXP (op1, 0))))
7651 & ~ INTVAL (XEXP (op1, 1))) == 0)
7653 op0 = SUBREG_REG (XEXP (op0, 0));
7654 op1 = SUBREG_REG (XEXP (op1, 0));
7656 /* the resulting comparison is always unsigned since we masked off
7657 the original sign bit. */
7658 code = unsigned_condition (code);
7664 /* If the first operand is a constant, swap the operands and adjust the
7665 comparison code appropriately. */
7666 if (CONSTANT_P (op0))
7668 tem = op0, op0 = op1, op1 = tem;
7669 code = swap_condition (code);
7672 /* We now enter a loop during which we will try to simplify the comparison.
7673 For the most part, we only are concerned with comparisons with zero,
7674 but some things may really be comparisons with zero but not start
7675 out looking that way. */
7677 while (GET_CODE (op1) == CONST_INT)
7679 enum machine_mode mode = GET_MODE (op0);
7680 int mode_width = GET_MODE_BITSIZE (mode);
7681 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
7682 int equality_comparison_p;
7683 int sign_bit_comparison_p;
7684 int unsigned_comparison_p;
7685 HOST_WIDE_INT const_op;
7687 /* We only want to handle integral modes. This catches VOIDmode,
7688 CCmode, and the floating-point modes. An exception is that we
7689 can handle VOIDmode if OP0 is a COMPARE or a comparison
7692 if (GET_MODE_CLASS (mode) != MODE_INT
7693 && ! (mode == VOIDmode
7694 && (GET_CODE (op0) == COMPARE
7695 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
7698 /* Get the constant we are comparing against and turn off all bits
7699 not on in our mode. */
7700 const_op = INTVAL (op1);
7701 if (mode_width <= HOST_BITS_PER_WIDE_INT)
7704 /* If we are comparing against a constant power of two and the value
7705 being compared has only that single significant bit (e.g., it was
7706 `and'ed with that bit), we can replace this with a comparison
7709 && (code == EQ || code == NE || code == GE || code == GEU
7710 || code == LT || code == LTU)
7711 && mode_width <= HOST_BITS_PER_WIDE_INT
7712 && exact_log2 (const_op) >= 0
7713 && significant_bits (op0, mode) == const_op)
7715 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
7716 op1 = const0_rtx, const_op = 0;
7719 /* Similarly, if we are comparing a value known to be either -1 or
7720 0 with -1, change it to the opposite comparison against zero. */
7723 && (code == EQ || code == NE || code == GT || code == LE
7724 || code == GEU || code == LTU)
7725 && num_sign_bit_copies (op0, mode) == mode_width)
7727 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
7728 op1 = const0_rtx, const_op = 0;
7731 /* Do some canonicalizations based on the comparison code. We prefer
7732 comparisons against zero and then prefer equality comparisons.
7733 If we can reduce the size of a constant, we will do that too. */
7738 /* < C is equivalent to <= (C - 1) */
7742 op1 = GEN_INT (const_op);
7744 /* ... fall through to LE case below. */
7750 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
7754 op1 = GEN_INT (const_op);
7758 /* If we are doing a <= 0 comparison on a value known to have
7759 a zero sign bit, we can replace this with == 0. */
7760 else if (const_op == 0
7761 && mode_width <= HOST_BITS_PER_WIDE_INT
7762 && (significant_bits (op0, mode)
7763 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
7768 /* >= C is equivalent to > (C - 1). */
7772 op1 = GEN_INT (const_op);
7774 /* ... fall through to GT below. */
7780 /* > C is equivalent to >= (C + 1); we do this for C < 0*/
7784 op1 = GEN_INT (const_op);
7788 /* If we are doing a > 0 comparison on a value known to have
7789 a zero sign bit, we can replace this with != 0. */
7790 else if (const_op == 0
7791 && mode_width <= HOST_BITS_PER_WIDE_INT
7792 && (significant_bits (op0, mode)
7793 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
7798 /* < C is equivalent to <= (C - 1). */
7802 op1 = GEN_INT (const_op);
7804 /* ... fall through ... */
7807 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
7808 else if (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1))
7810 const_op = 0, op1 = const0_rtx;
7818 /* unsigned <= 0 is equivalent to == 0 */
7822 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
7823 else if (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
7825 const_op = 0, op1 = const0_rtx;
7831 /* >= C is equivalent to < (C - 1). */
7835 op1 = GEN_INT (const_op);
7837 /* ... fall through ... */
7840 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
7841 else if (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1))
7843 const_op = 0, op1 = const0_rtx;
7850 /* unsigned > 0 is equivalent to != 0 */
7854 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
7855 else if (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
7857 const_op = 0, op1 = const0_rtx;
7863 /* Compute some predicates to simplify code below. */
7865 equality_comparison_p = (code == EQ || code == NE);
7866 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
7867 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
7870 /* Now try cases based on the opcode of OP0. If none of the cases
7871 does a "continue", we exit this loop immediately after the
7874 switch (GET_CODE (op0))
7877 /* If we are extracting a single bit from a variable position in
7878 a constant that has only a single bit set and are comparing it
7879 with zero, we can convert this into an equality comparison
7880 between the position and the location of the single bit. We can't
7881 do this if bit endian and we don't have an extzv since we then
7882 can't know what mode to use for the endianness adjustment. */
7884 #if ! BITS_BIG_ENDIAN || defined (HAVE_extzv)
7885 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
7886 && XEXP (op0, 1) == const1_rtx
7887 && equality_comparison_p && const_op == 0
7888 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
7891 i = (GET_MODE_BITSIZE
7892 (insn_operand_mode[(int) CODE_FOR_extzv][1]) - 1 - i);
7895 op0 = XEXP (op0, 2);
7899 /* Result is nonzero iff shift count is equal to I. */
7900 code = reverse_condition (code);
7905 /* ... fall through ... */
7908 tem = expand_compound_operation (op0);
7917 /* If testing for equality, we can take the NOT of the constant. */
7918 if (equality_comparison_p
7919 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
7921 op0 = XEXP (op0, 0);
7926 /* If just looking at the sign bit, reverse the sense of the
7928 if (sign_bit_comparison_p)
7930 op0 = XEXP (op0, 0);
7931 code = (code == GE ? LT : GE);
7937 /* If testing for equality, we can take the NEG of the constant. */
7938 if (equality_comparison_p
7939 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
7941 op0 = XEXP (op0, 0);
7946 /* The remaining cases only apply to comparisons with zero. */
7950 /* When X is ABS or is known positive,
7951 (neg X) is < 0 if and only if X != 0. */
7953 if (sign_bit_comparison_p
7954 && (GET_CODE (XEXP (op0, 0)) == ABS
7955 || (mode_width <= HOST_BITS_PER_WIDE_INT
7956 && (significant_bits (XEXP (op0, 0), mode)
7957 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
7959 op0 = XEXP (op0, 0);
7960 code = (code == LT ? NE : EQ);
7964 /* If we have NEG of something that is the result of a
7965 SIGN_EXTEND, SIGN_EXTRACT, or ASHIFTRT, we know that the
7966 two high-order bits must be the same and hence that
7967 "(-a) < 0" is equivalent to "a > 0". Otherwise, we can't
7969 if (GET_CODE (XEXP (op0, 0)) == SIGN_EXTEND
7970 || (GET_CODE (XEXP (op0, 0)) == SIGN_EXTRACT
7971 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
7972 && (INTVAL (XEXP (XEXP (op0, 0), 1))
7973 < GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (op0, 0), 0)))))
7974 || (GET_CODE (XEXP (op0, 0)) == ASHIFTRT
7975 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
7976 && XEXP (XEXP (op0, 0), 1) != const0_rtx)
7977 || ((tem = get_last_value (XEXP (op0, 0))) != 0
7978 && (GET_CODE (tem) == SIGN_EXTEND
7979 || (GET_CODE (tem) == SIGN_EXTRACT
7980 && GET_CODE (XEXP (tem, 1)) == CONST_INT
7981 && (INTVAL (XEXP (tem, 1))
7982 < GET_MODE_BITSIZE (GET_MODE (XEXP (tem, 0)))))
7983 || (GET_CODE (tem) == ASHIFTRT
7984 && GET_CODE (XEXP (tem, 1)) == CONST_INT
7985 && XEXP (tem, 1) != const0_rtx))))
7987 op0 = XEXP (op0, 0);
7988 code = swap_condition (code);
7994 /* If we are testing equality and our count is a constant, we
7995 can perform the inverse operation on our RHS. */
7996 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
7997 && (tem = simplify_binary_operation (ROTATERT, mode,
7998 op1, XEXP (op0, 1))) != 0)
8000 op0 = XEXP (op0, 0);
8005 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
8006 a particular bit. Convert it to an AND of a constant of that
8007 bit. This will be converted into a ZERO_EXTRACT. */
8008 if (const_op == 0 && sign_bit_comparison_p
8009 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8010 && mode_width <= HOST_BITS_PER_WIDE_INT)
8012 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
8015 - INTVAL (XEXP (op0, 1)))));
8016 code = (code == LT ? NE : EQ);
8020 /* ... fall through ... */
8023 /* ABS is ignorable inside an equality comparison with zero. */
8024 if (const_op == 0 && equality_comparison_p)
8026 op0 = XEXP (op0, 0);
8033 /* Can simplify (compare (zero/sign_extend FOO) CONST)
8034 to (compare FOO CONST) if CONST fits in FOO's mode and we
8035 are either testing inequality or have an unsigned comparison
8036 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
8037 if (! unsigned_comparison_p
8038 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
8039 <= HOST_BITS_PER_WIDE_INT)
8040 && ((unsigned HOST_WIDE_INT) const_op
8041 < (((HOST_WIDE_INT) 1
8042 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
8044 op0 = XEXP (op0, 0);
8050 /* Check for the case where we are comparing A - C1 with C2,
8051 both constants are smaller than 1/2 the maxium positive
8052 value in MODE, and the comparison is equality or unsigned.
8053 In that case, if A is either zero-extended to MODE or has
8054 sufficient sign bits so that the high-order bit in MODE
8055 is a copy of the sign in the inner mode, we can prove that it is
8056 safe to do the operation in the wider mode. This simplifies
8057 many range checks. */
8059 if (mode_width <= HOST_BITS_PER_WIDE_INT
8060 && subreg_lowpart_p (op0)
8061 && GET_CODE (SUBREG_REG (op0)) == PLUS
8062 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
8063 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
8064 && (- INTVAL (XEXP (SUBREG_REG (op0), 1))
8065 < GET_MODE_MASK (mode) / 2)
8066 && (unsigned) const_op < GET_MODE_MASK (mode) / 2
8067 && (0 == (significant_bits (XEXP (SUBREG_REG (op0), 0),
8068 GET_MODE (SUBREG_REG (op0)))
8069 & ~ GET_MODE_MASK (mode))
8070 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
8071 GET_MODE (SUBREG_REG (op0)))
8072 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
8073 - GET_MODE_BITSIZE (mode)))))
8075 op0 = SUBREG_REG (op0);
8079 /* If the inner mode is narrower and we are extracting the low part,
8080 we can treat the SUBREG as if it were a ZERO_EXTEND. */
8081 if (subreg_lowpart_p (op0)
8082 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
8083 /* Fall through */ ;
8087 /* ... fall through ... */
8090 if ((unsigned_comparison_p || equality_comparison_p)
8091 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
8092 <= HOST_BITS_PER_WIDE_INT)
8093 && ((unsigned HOST_WIDE_INT) const_op
8094 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
8096 op0 = XEXP (op0, 0);
8102 /* (eq (plus X C1) C2) -> (eq X (minus C2 C1)). We can only do
8103 this for equality comparisons due to pathological cases involving
8105 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
8106 && (tem = simplify_binary_operation (MINUS, mode, op1,
8107 XEXP (op0, 1))) != 0)
8109 op0 = XEXP (op0, 0);
8114 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
8115 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
8116 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
8118 op0 = XEXP (XEXP (op0, 0), 0);
8119 code = (code == LT ? EQ : NE);
8125 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
8126 of bits in X minus 1, is one iff X > 0. */
8127 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
8128 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
8129 && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
8130 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
8132 op0 = XEXP (op0, 1);
8133 code = (code == GE ? LE : GT);
8139 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
8140 if C is zero or B is a constant. */
8141 if (equality_comparison_p
8142 && 0 != (tem = simplify_binary_operation (XOR, mode,
8143 XEXP (op0, 1), op1)))
8145 op0 = XEXP (op0, 0);
8152 case LT: case LTU: case LE: case LEU:
8153 case GT: case GTU: case GE: case GEU:
8154 /* We can't do anything if OP0 is a condition code value, rather
8155 than an actual data value. */
8158 || XEXP (op0, 0) == cc0_rtx
8160 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
8163 /* Get the two operands being compared. */
8164 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
8165 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
8167 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
8169 /* Check for the cases where we simply want the result of the
8170 earlier test or the opposite of that result. */
8172 || (code == EQ && reversible_comparison_p (op0))
8173 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
8174 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
8175 && (STORE_FLAG_VALUE
8176 & (((HOST_WIDE_INT) 1
8177 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
8179 || (code == GE && reversible_comparison_p (op0)))))
8181 code = (code == LT || code == NE
8182 ? GET_CODE (op0) : reverse_condition (GET_CODE (op0)));
8183 op0 = tem, op1 = tem1;
8189 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
8191 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
8192 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
8193 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
8195 op0 = XEXP (op0, 1);
8196 code = (code == GE ? GT : LE);
8202 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
8203 will be converted to a ZERO_EXTRACT later. */
8204 if (const_op == 0 && equality_comparison_p
8205 && (GET_CODE (XEXP (op0, 0)) == ASHIFT
8206 || GET_CODE (XEXP (op0, 0)) == LSHIFT)
8207 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
8209 op0 = simplify_and_const_int
8210 (op0, mode, gen_rtx_combine (LSHIFTRT, mode,
8212 XEXP (XEXP (op0, 0), 1)),
8217 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
8218 zero and X is a comparison and C1 and C2 describe only bits set
8219 in STORE_FLAG_VALUE, we can compare with X. */
8220 if (const_op == 0 && equality_comparison_p
8221 && mode_width <= HOST_BITS_PER_WIDE_INT
8222 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8223 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
8224 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
8225 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
8226 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
8228 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
8229 << INTVAL (XEXP (XEXP (op0, 0), 1)));
8230 if ((~ STORE_FLAG_VALUE & mask) == 0
8231 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
8232 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
8233 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
8235 op0 = XEXP (XEXP (op0, 0), 0);
8240 /* If we are doing an equality comparison of an AND of a bit equal
8241 to the sign bit, replace this with a LT or GE comparison of
8242 the underlying value. */
8243 if (equality_comparison_p
8245 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8246 && mode_width <= HOST_BITS_PER_WIDE_INT
8247 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
8248 == (HOST_WIDE_INT) 1 << (mode_width - 1)))
8250 op0 = XEXP (op0, 0);
8251 code = (code == EQ ? GE : LT);
8255 /* If this AND operation is really a ZERO_EXTEND from a narrower
8256 mode, the constant fits within that mode, and this is either an
8257 equality or unsigned comparison, try to do this comparison in
8258 the narrower mode. */
8259 if ((equality_comparison_p || unsigned_comparison_p)
8260 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8261 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
8262 & GET_MODE_MASK (mode))
8264 && const_op >> i == 0
8265 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
8267 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
8274 /* If we have (compare (xshift FOO N) (const_int C)) and
8275 the high order N bits of FOO (N+1 if an inequality comparison)
8276 are not significant, we can do this by comparing FOO with C
8277 shifted right N bits so long as the low-order N bits of C are
8279 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
8280 && INTVAL (XEXP (op0, 1)) >= 0
8281 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
8282 < HOST_BITS_PER_WIDE_INT)
8284 & ((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1) == 0)
8285 && mode_width <= HOST_BITS_PER_WIDE_INT
8286 && (significant_bits (XEXP (op0, 0), mode)
8287 & ~ (mask >> (INTVAL (XEXP (op0, 1))
8288 + ! equality_comparison_p))) == 0)
8290 const_op >>= INTVAL (XEXP (op0, 1));
8291 op1 = GEN_INT (const_op);
8292 op0 = XEXP (op0, 0);
8296 /* If we are doing a sign bit comparison, it means we are testing
8297 a particular bit. Convert it to the appropriate AND. */
8298 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
8299 && mode_width <= HOST_BITS_PER_WIDE_INT)
8301 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
8304 - INTVAL (XEXP (op0, 1)))));
8305 code = (code == LT ? NE : EQ);
8309 /* If this an equality comparison with zero and we are shifting
8310 the low bit to the sign bit, we can convert this to an AND of the
8312 if (const_op == 0 && equality_comparison_p
8313 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8314 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
8316 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
8323 /* If this is an equality comparison with zero, we can do this
8324 as a logical shift, which might be much simpler. */
8325 if (equality_comparison_p && const_op == 0
8326 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
8328 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
8330 INTVAL (XEXP (op0, 1)));
8334 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
8335 do the comparison in a narrower mode. */
8336 if (! unsigned_comparison_p
8337 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8338 && GET_CODE (XEXP (op0, 0)) == ASHIFT
8339 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
8340 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
8341 MODE_INT, 1)) != VOIDmode
8342 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
8343 || ((unsigned HOST_WIDE_INT) - const_op
8344 <= GET_MODE_MASK (tmode))))
8346 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
8350 /* ... fall through ... */
8352 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
8353 the low order N bits of FOO are not significant, we can do this
8354 by comparing FOO with C shifted left N bits so long as no
8356 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
8357 && INTVAL (XEXP (op0, 1)) >= 0
8358 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
8359 && mode_width <= HOST_BITS_PER_WIDE_INT
8360 && (significant_bits (XEXP (op0, 0), mode)
8361 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
8363 || (floor_log2 (const_op) + INTVAL (XEXP (op0, 1))
8366 const_op <<= INTVAL (XEXP (op0, 1));
8367 op1 = GEN_INT (const_op);
8368 op0 = XEXP (op0, 0);
8372 /* If we are using this shift to extract just the sign bit, we
8373 can replace this with an LT or GE comparison. */
8375 && (equality_comparison_p || sign_bit_comparison_p)
8376 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8377 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
8379 op0 = XEXP (op0, 0);
8380 code = (code == NE || code == GT ? LT : GE);
8389 /* Now make any compound operations involved in this comparison. Then,
8390 check for an outmost SUBREG on OP0 that isn't doing anything or is
8391 paradoxical. The latter case can only occur when it is known that the
8392 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
8393 We can never remove a SUBREG for a non-equality comparison because the
8394 sign bit is in a different place in the underlying object. */
8396 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
8397 op1 = make_compound_operation (op1, SET);
8399 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
8400 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
8401 && (code == NE || code == EQ)
8402 && ((GET_MODE_SIZE (GET_MODE (op0))
8403 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))))
8405 op0 = SUBREG_REG (op0);
8406 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
8409 else if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
8410 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
8411 && (code == NE || code == EQ)
8412 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
8413 && (significant_bits (SUBREG_REG (op0), GET_MODE (SUBREG_REG (op0)))
8414 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0
8415 && (tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)),
8417 (significant_bits (tem, GET_MODE (SUBREG_REG (op0)))
8418 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0))
8419 op0 = SUBREG_REG (op0), op1 = tem;
8421 /* We now do the opposite procedure: Some machines don't have compare
8422 insns in all modes. If OP0's mode is an integer mode smaller than a
8423 word and we can't do a compare in that mode, see if there is a larger
8424 mode for which we can do the compare. There are a number of cases in
8425 which we can use the wider mode. */
8427 mode = GET_MODE (op0);
8428 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
8429 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
8430 && cmp_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
8431 for (tmode = GET_MODE_WIDER_MODE (mode);
8433 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
8434 tmode = GET_MODE_WIDER_MODE (tmode))
8435 if (cmp_optab->handlers[(int) tmode].insn_code != CODE_FOR_nothing)
8437 /* If the only significant bits in OP0 and OP1 are those in the
8438 narrower mode and this is an equality or unsigned comparison,
8439 we can use the wider mode. Similarly for sign-extended
8440 values and equality or signed comparisons. */
8441 if (((code == EQ || code == NE
8442 || code == GEU || code == GTU || code == LEU || code == LTU)
8443 && ((significant_bits (op0, tmode) & ~ GET_MODE_MASK (mode))
8445 && ((significant_bits (op1, tmode) & ~ GET_MODE_MASK (mode))
8447 || ((code == EQ || code == NE
8448 || code == GE || code == GT || code == LE || code == LT)
8449 && (num_sign_bit_copies (op0, tmode)
8450 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))
8451 && (num_sign_bit_copies (op1, tmode)
8452 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))))
8454 op0 = gen_lowpart_for_combine (tmode, op0);
8455 op1 = gen_lowpart_for_combine (tmode, op1);
8459 /* If this is a test for negative, we can make an explicit
8460 test of the sign bit. */
8462 if (op1 == const0_rtx && (code == LT || code == GE)
8463 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
8465 op0 = gen_binary (AND, tmode,
8466 gen_lowpart_for_combine (tmode, op0),
8467 GEN_INT ((HOST_WIDE_INT) 1
8468 << (GET_MODE_BITSIZE (mode) - 1)));
8469 code = (code == LT) ? NE : EQ;
8480 /* Return 1 if we know that X, a comparison operation, is not operating
8481 on a floating-point value or is EQ or NE, meaning that we can safely
8485 reversible_comparison_p (x)
8488 if (TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
8489 || GET_CODE (x) == NE || GET_CODE (x) == EQ)
8492 switch (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))))
8498 x = get_last_value (XEXP (x, 0));
8499 return (x && GET_CODE (x) == COMPARE
8500 && GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) == MODE_INT);
8506 /* Utility function for following routine. Called when X is part of a value
8507 being stored into reg_last_set_value. Sets reg_last_set_table_tick
8508 for each register mentioned. Similar to mention_regs in cse.c */
8511 update_table_tick (x)
8514 register enum rtx_code code = GET_CODE (x);
8515 register char *fmt = GET_RTX_FORMAT (code);
8520 int regno = REGNO (x);
8521 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
8522 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
8524 for (i = regno; i < endregno; i++)
8525 reg_last_set_table_tick[i] = label_tick;
8530 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8531 /* Note that we can't have an "E" in values stored; see
8532 get_last_value_validate. */
8534 update_table_tick (XEXP (x, i));
8537 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
8538 are saying that the register is clobbered and we no longer know its
8539 value. If INSN is zero, don't update reg_last_set; this call is normally
8540 done with VALUE also zero to invalidate the register. */
8543 record_value_for_reg (reg, insn, value)
8548 int regno = REGNO (reg);
8549 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
8550 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
8553 /* If VALUE contains REG and we have a previous value for REG, substitute
8554 the previous value. */
8555 if (value && insn && reg_overlap_mentioned_p (reg, value))
8559 /* Set things up so get_last_value is allowed to see anything set up to
8561 subst_low_cuid = INSN_CUID (insn);
8562 tem = get_last_value (reg);
8565 value = replace_rtx (copy_rtx (value), reg, tem);
8568 /* For each register modified, show we don't know its value, that
8569 its value has been updated, and that we don't know the location of
8570 the death of the register. */
8571 for (i = regno; i < endregno; i ++)
8574 reg_last_set[i] = insn;
8575 reg_last_set_value[i] = 0;
8576 reg_last_death[i] = 0;
8579 /* Mark registers that are being referenced in this value. */
8581 update_table_tick (value);
8583 /* Now update the status of each register being set.
8584 If someone is using this register in this block, set this register
8585 to invalid since we will get confused between the two lives in this
8586 basic block. This makes using this register always invalid. In cse, we
8587 scan the table to invalidate all entries using this register, but this
8588 is too much work for us. */
8590 for (i = regno; i < endregno; i++)
8592 reg_last_set_label[i] = label_tick;
8593 if (value && reg_last_set_table_tick[i] == label_tick)
8594 reg_last_set_invalid[i] = 1;
8596 reg_last_set_invalid[i] = 0;
8599 /* The value being assigned might refer to X (like in "x++;"). In that
8600 case, we must replace it with (clobber (const_int 0)) to prevent
8602 if (value && ! get_last_value_validate (&value,
8603 reg_last_set_label[regno], 0))
8605 value = copy_rtx (value);
8606 if (! get_last_value_validate (&value, reg_last_set_label[regno], 1))
8610 /* For the main register being modified, update the value. */
8611 reg_last_set_value[regno] = value;
8615 /* Used for communication between the following two routines. */
8616 static rtx record_dead_insn;
8618 /* Called via note_stores from record_dead_and_set_regs to handle one
8619 SET or CLOBBER in an insn. */
8622 record_dead_and_set_regs_1 (dest, setter)
8625 if (GET_CODE (dest) == REG)
8627 /* If we are setting the whole register, we know its value. Otherwise
8628 show that we don't know the value. We can handle SUBREG in
8630 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
8631 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
8632 else if (GET_CODE (setter) == SET
8633 && GET_CODE (SET_DEST (setter)) == SUBREG
8634 && SUBREG_REG (SET_DEST (setter)) == dest
8635 && subreg_lowpart_p (SET_DEST (setter)))
8636 record_value_for_reg (dest, record_dead_insn,
8637 gen_lowpart_for_combine (GET_MODE (dest),
8640 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
8642 else if (GET_CODE (dest) == MEM
8643 /* Ignore pushes, they clobber nothing. */
8644 && ! push_operand (dest, GET_MODE (dest)))
8645 mem_last_set = INSN_CUID (record_dead_insn);
8648 /* Update the records of when each REG was most recently set or killed
8649 for the things done by INSN. This is the last thing done in processing
8650 INSN in the combiner loop.
8652 We update reg_last_set, reg_last_set_value, reg_last_death, and also the
8653 similar information mem_last_set (which insn most recently modified memory)
8654 and last_call_cuid (which insn was the most recent subroutine call). */
8657 record_dead_and_set_regs (insn)
8661 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
8663 if (REG_NOTE_KIND (link) == REG_DEAD)
8664 reg_last_death[REGNO (XEXP (link, 0))] = insn;
8665 else if (REG_NOTE_KIND (link) == REG_INC)
8666 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
8669 if (GET_CODE (insn) == CALL_INSN)
8670 last_call_cuid = mem_last_set = INSN_CUID (insn);
8672 record_dead_insn = insn;
8673 note_stores (PATTERN (insn), record_dead_and_set_regs_1);
8676 /* Utility routine for the following function. Verify that all the registers
8677 mentioned in *LOC are valid when *LOC was part of a value set when
8678 label_tick == TICK. Return 0 if some are not.
8680 If REPLACE is non-zero, replace the invalid reference with
8681 (clobber (const_int 0)) and return 1. This replacement is useful because
8682 we often can get useful information about the form of a value (e.g., if
8683 it was produced by a shift that always produces -1 or 0) even though
8684 we don't know exactly what registers it was produced from. */
8687 get_last_value_validate (loc, tick, replace)
8693 char *fmt = GET_RTX_FORMAT (GET_CODE (x));
8694 int len = GET_RTX_LENGTH (GET_CODE (x));
8697 if (GET_CODE (x) == REG)
8699 int regno = REGNO (x);
8700 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
8701 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
8704 for (j = regno; j < endregno; j++)
8705 if (reg_last_set_invalid[j]
8706 /* If this is a pseudo-register that was only set once, it is
8708 || (! (regno >= FIRST_PSEUDO_REGISTER && reg_n_sets[regno] == 1)
8709 && reg_last_set_label[j] > tick))
8712 *loc = gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
8719 for (i = 0; i < len; i++)
8721 && get_last_value_validate (&XEXP (x, i), tick, replace) == 0)
8722 /* Don't bother with these. They shouldn't occur anyway. */
8726 /* If we haven't found a reason for it to be invalid, it is valid. */
8730 /* Get the last value assigned to X, if known. Some registers
8731 in the value may be replaced with (clobber (const_int 0)) if their value
8732 is known longer known reliably. */
8741 /* If this is a non-paradoxical SUBREG, get the value of its operand and
8742 then convert it to the desired mode. If this is a paradoxical SUBREG,
8743 we cannot predict what values the "extra" bits might have. */
8744 if (GET_CODE (x) == SUBREG
8745 && subreg_lowpart_p (x)
8746 && (GET_MODE_SIZE (GET_MODE (x))
8747 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8748 && (value = get_last_value (SUBREG_REG (x))) != 0)
8749 return gen_lowpart_for_combine (GET_MODE (x), value);
8751 if (GET_CODE (x) != REG)
8755 value = reg_last_set_value[regno];
8757 /* If we don't have a value or if it isn't for this basic block, return 0. */
8760 || (reg_n_sets[regno] != 1
8761 && (reg_last_set_label[regno] != label_tick)))
8764 /* If the value was set in a later insn that the ones we are processing,
8765 we can't use it, but make a quick check to see if the previous insn
8766 set it to something. This is commonly the case when the same pseudo
8767 is used by repeated insns. */
8769 if (reg_n_sets[regno] != 1
8770 && INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
8774 for (insn = prev_nonnote_insn (subst_insn);
8775 insn && INSN_CUID (insn) >= subst_low_cuid;
8776 insn = prev_nonnote_insn (insn))
8780 && (set = single_set (insn)) != 0
8781 && rtx_equal_p (SET_DEST (set), x))
8783 value = SET_SRC (set);
8785 /* Make sure that VALUE doesn't reference X. Replace any
8786 expliit references with a CLOBBER. If there are any remaining
8787 references (rare), don't use the value. */
8789 if (reg_mentioned_p (x, value))
8790 value = replace_rtx (copy_rtx (value), x,
8791 gen_rtx (CLOBBER, GET_MODE (x), const0_rtx));
8793 if (reg_overlap_mentioned_p (x, value))
8800 /* If the value has all its registers valid, return it. */
8801 if (get_last_value_validate (&value, reg_last_set_label[regno], 0))
8804 /* Otherwise, make a copy and replace any invalid register with
8805 (clobber (const_int 0)). If that fails for some reason, return 0. */
8807 value = copy_rtx (value);
8808 if (get_last_value_validate (&value, reg_last_set_label[regno], 1))
8814 /* Return nonzero if expression X refers to a REG or to memory
8815 that is set in an instruction more recent than FROM_CUID. */
8818 use_crosses_set_p (x, from_cuid)
8824 register enum rtx_code code = GET_CODE (x);
8828 register int regno = REGNO (x);
8829 #ifdef PUSH_ROUNDING
8830 /* Don't allow uses of the stack pointer to be moved,
8831 because we don't know whether the move crosses a push insn. */
8832 if (regno == STACK_POINTER_REGNUM)
8835 return (reg_last_set[regno]
8836 && INSN_CUID (reg_last_set[regno]) > from_cuid);
8839 if (code == MEM && mem_last_set > from_cuid)
8842 fmt = GET_RTX_FORMAT (code);
8844 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8849 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8850 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
8853 else if (fmt[i] == 'e'
8854 && use_crosses_set_p (XEXP (x, i), from_cuid))
8860 /* Define three variables used for communication between the following
8863 static int reg_dead_regno, reg_dead_endregno;
8864 static int reg_dead_flag;
8866 /* Function called via note_stores from reg_dead_at_p.
8868 If DEST is within [reg_dead_rengno, reg_dead_endregno), set
8869 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
8872 reg_dead_at_p_1 (dest, x)
8876 int regno, endregno;
8878 if (GET_CODE (dest) != REG)
8881 regno = REGNO (dest);
8882 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
8883 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
8885 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
8886 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
8889 /* Return non-zero if REG is known to be dead at INSN.
8891 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
8892 referencing REG, it is dead. If we hit a SET referencing REG, it is
8893 live. Otherwise, see if it is live or dead at the start of the basic
8897 reg_dead_at_p (reg, insn)
8903 /* Set variables for reg_dead_at_p_1. */
8904 reg_dead_regno = REGNO (reg);
8905 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
8906 ? HARD_REGNO_NREGS (reg_dead_regno,
8912 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
8913 beginning of function. */
8914 for (; insn && GET_CODE (insn) != CODE_LABEL;
8915 insn = prev_nonnote_insn (insn))
8917 note_stores (PATTERN (insn), reg_dead_at_p_1);
8919 return reg_dead_flag == 1 ? 1 : 0;
8921 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
8925 /* Get the basic block number that we were in. */
8930 for (block = 0; block < n_basic_blocks; block++)
8931 if (insn == basic_block_head[block])
8934 if (block == n_basic_blocks)
8938 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
8939 if (basic_block_live_at_start[block][i / REGSET_ELT_BITS]
8940 & ((REGSET_ELT_TYPE) 1 << (i % REGSET_ELT_BITS)))
8946 /* Remove register number REGNO from the dead registers list of INSN.
8948 Return the note used to record the death, if there was one. */
8951 remove_death (regno, insn)
8955 register rtx note = find_regno_note (insn, REG_DEAD, regno);
8959 reg_n_deaths[regno]--;
8960 remove_note (insn, note);
8966 /* For each register (hardware or pseudo) used within expression X, if its
8967 death is in an instruction with cuid between FROM_CUID (inclusive) and
8968 TO_INSN (exclusive), put a REG_DEAD note for that register in the
8969 list headed by PNOTES.
8971 This is done when X is being merged by combination into TO_INSN. These
8972 notes will then be distributed as needed. */
8975 move_deaths (x, from_cuid, to_insn, pnotes)
8982 register int len, i;
8983 register enum rtx_code code = GET_CODE (x);
8987 register int regno = REGNO (x);
8988 register rtx where_dead = reg_last_death[regno];
8990 if (where_dead && INSN_CUID (where_dead) >= from_cuid
8991 && INSN_CUID (where_dead) < INSN_CUID (to_insn))
8993 rtx note = remove_death (regno, reg_last_death[regno]);
8995 /* It is possible for the call above to return 0. This can occur
8996 when reg_last_death points to I2 or I1 that we combined with.
8997 In that case make a new note. */
9001 XEXP (note, 1) = *pnotes;
9005 *pnotes = gen_rtx (EXPR_LIST, REG_DEAD, x, *pnotes);
9007 reg_n_deaths[regno]++;
9013 else if (GET_CODE (x) == SET)
9015 rtx dest = SET_DEST (x);
9017 move_deaths (SET_SRC (x), from_cuid, to_insn, pnotes);
9019 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
9020 that accesses one word of a multi-word item, some
9021 piece of everything register in the expression is used by
9022 this insn, so remove any old death. */
9024 if (GET_CODE (dest) == ZERO_EXTRACT
9025 || GET_CODE (dest) == STRICT_LOW_PART
9026 || (GET_CODE (dest) == SUBREG
9027 && (((GET_MODE_SIZE (GET_MODE (dest))
9028 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
9029 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
9030 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
9032 move_deaths (dest, from_cuid, to_insn, pnotes);
9036 /* If this is some other SUBREG, we know it replaces the entire
9037 value, so use that as the destination. */
9038 if (GET_CODE (dest) == SUBREG)
9039 dest = SUBREG_REG (dest);
9041 /* If this is a MEM, adjust deaths of anything used in the address.
9042 For a REG (the only other possibility), the entire value is
9043 being replaced so the old value is not used in this insn. */
9045 if (GET_CODE (dest) == MEM)
9046 move_deaths (XEXP (dest, 0), from_cuid, to_insn, pnotes);
9050 else if (GET_CODE (x) == CLOBBER)
9053 len = GET_RTX_LENGTH (code);
9054 fmt = GET_RTX_FORMAT (code);
9056 for (i = 0; i < len; i++)
9061 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9062 move_deaths (XVECEXP (x, i, j), from_cuid, to_insn, pnotes);
9064 else if (fmt[i] == 'e')
9065 move_deaths (XEXP (x, i), from_cuid, to_insn, pnotes);
9069 /* Return 1 if X is the target of a bit-field assignment in BODY, the
9070 pattern of an insn. X must be a REG. */
9073 reg_bitfield_target_p (x, body)
9079 if (GET_CODE (body) == SET)
9081 rtx dest = SET_DEST (body);
9083 int regno, tregno, endregno, endtregno;
9085 if (GET_CODE (dest) == ZERO_EXTRACT)
9086 target = XEXP (dest, 0);
9087 else if (GET_CODE (dest) == STRICT_LOW_PART)
9088 target = SUBREG_REG (XEXP (dest, 0));
9092 if (GET_CODE (target) == SUBREG)
9093 target = SUBREG_REG (target);
9095 if (GET_CODE (target) != REG)
9098 tregno = REGNO (target), regno = REGNO (x);
9099 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
9102 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
9103 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
9105 return endregno > tregno && regno < endtregno;
9108 else if (GET_CODE (body) == PARALLEL)
9109 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
9110 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
9116 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
9117 as appropriate. I3 and I2 are the insns resulting from the combination
9118 insns including FROM (I2 may be zero).
9120 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
9121 not need REG_DEAD notes because they are being substituted for. This
9122 saves searching in the most common cases.
9124 Each note in the list is either ignored or placed on some insns, depending
9125 on the type of note. */
9128 distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
9132 rtx elim_i2, elim_i1;
9134 rtx note, next_note;
9137 for (note = notes; note; note = next_note)
9139 rtx place = 0, place2 = 0;
9141 /* If this NOTE references a pseudo register, ensure it references
9142 the latest copy of that register. */
9143 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
9144 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
9145 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
9147 next_note = XEXP (note, 1);
9148 switch (REG_NOTE_KIND (note))
9151 /* If this register is set or clobbered in I3, put the note there
9152 unless there is one already. */
9153 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
9155 if (! (GET_CODE (XEXP (note, 0)) == REG
9156 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
9157 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
9160 /* Otherwise, if this register is used by I3, then this register
9161 now dies here, so we must put a REG_DEAD note here unless there
9163 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
9164 && ! (GET_CODE (XEXP (note, 0)) == REG
9165 ? find_regno_note (i3, REG_DEAD, REGNO (XEXP (note, 0)))
9166 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
9168 PUT_REG_NOTE_KIND (note, REG_DEAD);
9176 /* These notes say something about results of an insn. We can
9177 only support them if they used to be on I3 in which case they
9178 remain on I3. Otherwise they are ignored.
9180 If the note refers to an expression that is not a constant, we
9181 must also ignore the note since we cannot tell whether the
9182 equivalence is still true. It might be possible to do
9183 slightly better than this (we only have a problem if I2DEST
9184 or I1DEST is present in the expression), but it doesn't
9185 seem worth the trouble. */
9188 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
9193 case REG_NO_CONFLICT:
9195 /* These notes say something about how a register is used. They must
9196 be present on any use of the register in I2 or I3. */
9197 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
9200 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
9210 /* It is too much trouble to try to see if this note is still
9211 correct in all situations. It is better to simply delete it. */
9215 /* If the insn previously containing this note still exists,
9216 put it back where it was. Otherwise move it to the previous
9217 insn. Adjust the corresponding REG_LIBCALL note. */
9218 if (GET_CODE (from_insn) != NOTE)
9222 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
9223 place = prev_real_insn (from_insn);
9225 XEXP (tem, 0) = place;
9230 /* This is handled similarly to REG_RETVAL. */
9231 if (GET_CODE (from_insn) != NOTE)
9235 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
9236 place = next_real_insn (from_insn);
9238 XEXP (tem, 0) = place;
9243 /* If the register is used as an input in I3, it dies there.
9244 Similarly for I2, if it is non-zero and adjacent to I3.
9246 If the register is not used as an input in either I3 or I2
9247 and it is not one of the registers we were supposed to eliminate,
9248 there are two possibilities. We might have a non-adjacent I2
9249 or we might have somehow eliminated an additional register
9250 from a computation. For example, we might have had A & B where
9251 we discover that B will always be zero. In this case we will
9252 eliminate the reference to A.
9254 In both cases, we must search to see if we can find a previous
9255 use of A and put the death note there. */
9257 if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
9259 else if (i2 != 0 && next_nonnote_insn (i2) == i3
9260 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
9263 if (XEXP (note, 0) == elim_i2 || XEXP (note, 0) == elim_i1)
9266 /* If the register is used in both I2 and I3 and it dies in I3,
9267 we might have added another reference to it. If reg_n_refs
9268 was 2, bump it to 3. This has to be correct since the
9269 register must have been set somewhere. The reason this is
9270 done is because local-alloc.c treats 2 references as a
9273 if (place == i3 && i2 != 0 && GET_CODE (XEXP (note, 0)) == REG
9274 && reg_n_refs[REGNO (XEXP (note, 0))]== 2
9275 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
9276 reg_n_refs[REGNO (XEXP (note, 0))] = 3;
9279 for (tem = prev_nonnote_insn (i3);
9280 tem && (GET_CODE (tem) == INSN
9281 || GET_CODE (tem) == CALL_INSN);
9282 tem = prev_nonnote_insn (tem))
9284 /* If the register is being set at TEM, see if that is all
9285 TEM is doing. If so, delete TEM. Otherwise, make this
9286 into a REG_UNUSED note instead. */
9287 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
9289 rtx set = single_set (tem);
9291 /* Verify that it was the set, and not a clobber that
9292 modified the register. */
9294 if (set != 0 && ! side_effects_p (SET_SRC (set))
9295 && rtx_equal_p (XEXP (note, 0), SET_DEST (set)))
9297 /* Move the notes and links of TEM elsewhere.
9298 This might delete other dead insns recursively.
9299 First set the pattern to something that won't use
9302 PATTERN (tem) = pc_rtx;
9304 distribute_notes (REG_NOTES (tem), tem, tem,
9305 NULL_RTX, NULL_RTX, NULL_RTX);
9306 distribute_links (LOG_LINKS (tem));
9308 PUT_CODE (tem, NOTE);
9309 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
9310 NOTE_SOURCE_FILE (tem) = 0;
9314 PUT_REG_NOTE_KIND (note, REG_UNUSED);
9316 /* If there isn't already a REG_UNUSED note, put one
9318 if (! find_regno_note (tem, REG_UNUSED,
9319 REGNO (XEXP (note, 0))))
9324 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem)))
9331 /* If the register is set or already dead at PLACE, we needn't do
9332 anything with this note if it is still a REG_DEAD note.
9334 Note that we cannot use just `dead_or_set_p' here since we can
9335 convert an assignment to a register into a bit-field assignment.
9336 Therefore, we must also omit the note if the register is the
9337 target of a bitfield assignment. */
9339 if (place && REG_NOTE_KIND (note) == REG_DEAD)
9341 int regno = REGNO (XEXP (note, 0));
9343 if (dead_or_set_p (place, XEXP (note, 0))
9344 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
9346 /* Unless the register previously died in PLACE, clear
9347 reg_last_death. [I no longer understand why this is
9349 if (reg_last_death[regno] != place)
9350 reg_last_death[regno] = 0;
9354 reg_last_death[regno] = place;
9356 /* If this is a death note for a hard reg that is occupying
9357 multiple registers, ensure that we are still using all
9358 parts of the object. If we find a piece of the object
9359 that is unused, we must add a USE for that piece before
9360 PLACE and put the appropriate REG_DEAD note on it.
9362 An alternative would be to put a REG_UNUSED for the pieces
9363 on the insn that set the register, but that can't be done if
9364 it is not in the same block. It is simpler, though less
9365 efficient, to add the USE insns. */
9367 if (place && regno < FIRST_PSEUDO_REGISTER
9368 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
9371 = regno + HARD_REGNO_NREGS (regno,
9372 GET_MODE (XEXP (note, 0)));
9376 for (i = regno; i < endregno; i++)
9377 if (! refers_to_regno_p (i, i + 1, PATTERN (place), 0))
9379 rtx piece = gen_rtx (REG, word_mode, i);
9382 /* See if we already placed a USE note for this
9383 register in front of PLACE. */
9385 GET_CODE (PREV_INSN (p)) == INSN
9386 && GET_CODE (PATTERN (PREV_INSN (p))) == USE;
9388 if (rtx_equal_p (piece,
9389 XEXP (PATTERN (PREV_INSN (p)), 0)))
9398 = emit_insn_before (gen_rtx (USE, VOIDmode,
9401 REG_NOTES (use_insn)
9402 = gen_rtx (EXPR_LIST, REG_DEAD, piece,
9403 REG_NOTES (use_insn));
9411 /* Put only REG_DEAD notes for pieces that are
9412 still used and that are not already dead or set. */
9414 for (i = regno; i < endregno; i++)
9416 rtx piece = gen_rtx (REG, word_mode, i);
9418 if (reg_referenced_p (piece, PATTERN (place))
9419 && ! dead_or_set_p (place, piece)
9420 && ! reg_bitfield_target_p (piece,
9422 REG_NOTES (place) = gen_rtx (EXPR_LIST, REG_DEAD,
9434 /* Any other notes should not be present at this point in the
9441 XEXP (note, 1) = REG_NOTES (place);
9442 REG_NOTES (place) = note;
9444 else if ((REG_NOTE_KIND (note) == REG_DEAD
9445 || REG_NOTE_KIND (note) == REG_UNUSED)
9446 && GET_CODE (XEXP (note, 0)) == REG)
9447 reg_n_deaths[REGNO (XEXP (note, 0))]--;
9451 if ((REG_NOTE_KIND (note) == REG_DEAD
9452 || REG_NOTE_KIND (note) == REG_UNUSED)
9453 && GET_CODE (XEXP (note, 0)) == REG)
9454 reg_n_deaths[REGNO (XEXP (note, 0))]++;
9456 REG_NOTES (place2) = gen_rtx (GET_CODE (note), REG_NOTE_KIND (note),
9457 XEXP (note, 0), REG_NOTES (place2));
9462 /* Similarly to above, distribute the LOG_LINKS that used to be present on
9463 I3, I2, and I1 to new locations. This is also called in one case to
9464 add a link pointing at I3 when I3's destination is changed. */
9467 distribute_links (links)
9470 rtx link, next_link;
9472 for (link = links; link; link = next_link)
9478 next_link = XEXP (link, 1);
9480 /* If the insn that this link points to is a NOTE or isn't a single
9481 set, ignore it. In the latter case, it isn't clear what we
9482 can do other than ignore the link, since we can't tell which
9483 register it was for. Such links wouldn't be used by combine
9486 It is not possible for the destination of the target of the link to
9487 have been changed by combine. The only potential of this is if we
9488 replace I3, I2, and I1 by I3 and I2. But in that case the
9489 destination of I2 also remains unchanged. */
9491 if (GET_CODE (XEXP (link, 0)) == NOTE
9492 || (set = single_set (XEXP (link, 0))) == 0)
9495 reg = SET_DEST (set);
9496 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
9497 || GET_CODE (reg) == SIGN_EXTRACT
9498 || GET_CODE (reg) == STRICT_LOW_PART)
9499 reg = XEXP (reg, 0);
9501 /* A LOG_LINK is defined as being placed on the first insn that uses
9502 a register and points to the insn that sets the register. Start
9503 searching at the next insn after the target of the link and stop
9504 when we reach a set of the register or the end of the basic block.
9506 Note that this correctly handles the link that used to point from
9507 I3 to I2. Also note that not much searching is typically done here
9508 since most links don't point very far away. */
9510 for (insn = NEXT_INSN (XEXP (link, 0));
9511 (insn && GET_CODE (insn) != CODE_LABEL
9512 && GET_CODE (PREV_INSN (insn)) != JUMP_INSN);
9513 insn = NEXT_INSN (insn))
9514 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
9515 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
9517 if (reg_referenced_p (reg, PATTERN (insn)))
9522 /* If we found a place to put the link, place it there unless there
9523 is already a link to the same insn as LINK at that point. */
9529 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
9530 if (XEXP (link2, 0) == XEXP (link, 0))
9535 XEXP (link, 1) = LOG_LINKS (place);
9536 LOG_LINKS (place) = link;
9543 dump_combine_stats (file)
9548 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
9549 combine_attempts, combine_merges, combine_extras, combine_successes);
9553 dump_combine_total_stats (file)
9558 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
9559 total_attempts, total_merges, total_extras, total_successes);