1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
57 removed because there is no way to know which register it was
60 To simplify substitution, we combine only when the earlier insn(s)
61 consist of only a single assignment. To simplify updating afterward,
62 we never combine when a subroutine call appears in the middle.
64 Since we do not represent assignments to CC0 explicitly except when that
65 is all an insn does, there is no LOG_LINKS entry in an insn that uses
66 the condition code for the insn that set the condition code.
67 Fortunately, these two insns must be consecutive.
68 Therefore, every JUMP_INSN is taken to have an implicit logical link
69 to the preceding insn. This is not quite right, since non-jumps can
70 also use the condition code; but in practice such insns would not
75 #include "coretypes.h"
82 #include "hard-reg-set.h"
83 #include "basic-block.h"
84 #include "insn-config.h"
86 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
88 #include "insn-attr.h"
93 #include "rtlhooks-def.h"
94 /* Include output.h for dump_file. */
97 /* Number of attempts to combine instructions in this function. */
99 static int combine_attempts;
101 /* Number of attempts that got as far as substitution in this function. */
103 static int combine_merges;
105 /* Number of instructions combined with added SETs in this function. */
107 static int combine_extras;
109 /* Number of instructions combined in this function. */
111 static int combine_successes;
113 /* Totals over entire compilation. */
115 static int total_attempts, total_merges, total_extras, total_successes;
118 /* Vector mapping INSN_UIDs to cuids.
119 The cuids are like uids but increase monotonically always.
120 Combine always uses cuids so that it can compare them.
121 But actually renumbering the uids, which we used to do,
122 proves to be a bad idea because it makes it hard to compare
123 the dumps produced by earlier passes with those from later passes. */
125 static int *uid_cuid;
126 static int max_uid_cuid;
128 /* Get the cuid of an insn. */
130 #define INSN_CUID(INSN) \
131 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
133 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
134 BITS_PER_WORD would invoke undefined behavior. Work around it. */
136 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
137 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
139 /* Maximum register number, which is the size of the tables below. */
141 static unsigned int combine_max_regno;
144 /* Record last point of death of (hard or pseudo) register n. */
147 /* Record last point of modification of (hard or pseudo) register n. */
150 /* The next group of fields allows the recording of the last value assigned
151 to (hard or pseudo) register n. We use this information to see if an
152 operation being processed is redundant given a prior operation performed
153 on the register. For example, an `and' with a constant is redundant if
154 all the zero bits are already known to be turned off.
156 We use an approach similar to that used by cse, but change it in the
159 (1) We do not want to reinitialize at each label.
160 (2) It is useful, but not critical, to know the actual value assigned
161 to a register. Often just its form is helpful.
163 Therefore, we maintain the following fields:
165 last_set_value the last value assigned
166 last_set_label records the value of label_tick when the
167 register was assigned
168 last_set_table_tick records the value of label_tick when a
169 value using the register is assigned
170 last_set_invalid set to nonzero when it is not valid
171 to use the value of this register in some
174 To understand the usage of these tables, it is important to understand
175 the distinction between the value in last_set_value being valid and
176 the register being validly contained in some other expression in the
179 (The next two parameters are out of date).
181 reg_stat[i].last_set_value is valid if it is nonzero, and either
182 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
184 Register I may validly appear in any expression returned for the value
185 of another register if reg_n_sets[i] is 1. It may also appear in the
186 value for register J if reg_stat[j].last_set_invalid is zero, or
187 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
189 If an expression is found in the table containing a register which may
190 not validly appear in an expression, the register is replaced by
191 something that won't match, (clobber (const_int 0)). */
193 /* Record last value assigned to (hard or pseudo) register n. */
197 /* Record the value of label_tick when an expression involving register n
198 is placed in last_set_value. */
200 int last_set_table_tick;
202 /* Record the value of label_tick when the value for register n is placed in
207 /* These fields are maintained in parallel with last_set_value and are
208 used to store the mode in which the register was last set, te bits
209 that were known to be zero when it was last set, and the number of
210 sign bits copies it was known to have when it was last set. */
212 unsigned HOST_WIDE_INT last_set_nonzero_bits;
213 char last_set_sign_bit_copies;
214 ENUM_BITFIELD(machine_mode) last_set_mode : 8;
216 /* Set nonzero if references to register n in expressions should not be
217 used. last_set_invalid is set nonzero when this register is being
218 assigned to and last_set_table_tick == label_tick. */
220 char last_set_invalid;
222 /* Some registers that are set more than once and used in more than one
223 basic block are nevertheless always set in similar ways. For example,
224 a QImode register may be loaded from memory in two places on a machine
225 where byte loads zero extend.
227 We record in the following fields if a register has some leading bits
228 that are always equal to the sign bit, and what we know about the
229 nonzero bits of a register, specifically which bits are known to be
232 If an entry is zero, it means that we don't know anything special. */
234 unsigned char sign_bit_copies;
236 unsigned HOST_WIDE_INT nonzero_bits;
239 static struct reg_stat *reg_stat;
241 /* Record the cuid of the last insn that invalidated memory
242 (anything that writes memory, and subroutine calls, but not pushes). */
244 static int mem_last_set;
246 /* Record the cuid of the last CALL_INSN
247 so we can tell whether a potential combination crosses any calls. */
249 static int last_call_cuid;
251 /* When `subst' is called, this is the insn that is being modified
252 (by combining in a previous insn). The PATTERN of this insn
253 is still the old pattern partially modified and it should not be
254 looked at, but this may be used to examine the successors of the insn
255 to judge whether a simplification is valid. */
257 static rtx subst_insn;
259 /* This is the lowest CUID that `subst' is currently dealing with.
260 get_last_value will not return a value if the register was set at or
261 after this CUID. If not for this mechanism, we could get confused if
262 I2 or I1 in try_combine were an insn that used the old value of a register
263 to obtain a new value. In that case, we might erroneously get the
264 new value of the register when we wanted the old one. */
266 static int subst_low_cuid;
268 /* This contains any hard registers that are used in newpat; reg_dead_at_p
269 must consider all these registers to be always live. */
271 static HARD_REG_SET newpat_used_regs;
273 /* This is an insn to which a LOG_LINKS entry has been added. If this
274 insn is the earlier than I2 or I3, combine should rescan starting at
277 static rtx added_links_insn;
279 /* Basic block in which we are performing combines. */
280 static basic_block this_basic_block;
282 /* A bitmap indicating which blocks had registers go dead at entry.
283 After combine, we'll need to re-do global life analysis with
284 those blocks as starting points. */
285 static sbitmap refresh_blocks;
287 /* The following array records the combine_insn_cost for every insn
288 in the instruction stream. */
290 static int *uid_insn_cost;
292 /* Length of the currently allocated uid_insn_cost array. */
294 static int last_insn_cost;
296 /* Incremented for each label. */
298 static int label_tick;
300 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
301 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
303 static enum machine_mode nonzero_bits_mode;
305 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
306 be safely used. It is zero while computing them and after combine has
307 completed. This former test prevents propagating values based on
308 previously set values, which can be incorrect if a variable is modified
311 static int nonzero_sign_valid;
314 /* Record one modification to rtl structure
315 to be undone by storing old_contents into *where.
316 is_int is 1 if the contents are an int. */
322 union {rtx r; int i;} old_contents;
323 union {rtx *r; int *i;} where;
326 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
327 num_undo says how many are currently recorded.
329 other_insn is nonzero if we have modified some other insn in the process
330 of working on subst_insn. It must be verified too. */
339 static struct undobuf undobuf;
341 /* Number of times the pseudo being substituted for
342 was found and replaced. */
344 static int n_occurrences;
346 static rtx reg_nonzero_bits_for_combine (rtx, enum machine_mode, rtx,
348 unsigned HOST_WIDE_INT,
349 unsigned HOST_WIDE_INT *);
350 static rtx reg_num_sign_bit_copies_for_combine (rtx, enum machine_mode, rtx,
352 unsigned int, unsigned int *);
353 static void do_SUBST (rtx *, rtx);
354 static void do_SUBST_INT (int *, int);
355 static void init_reg_last (void);
356 static void setup_incoming_promotions (void);
357 static void set_nonzero_bits_and_sign_copies (rtx, rtx, void *);
358 static int cant_combine_insn_p (rtx);
359 static int can_combine_p (rtx, rtx, rtx, rtx, rtx *, rtx *);
360 static int combinable_i3pat (rtx, rtx *, rtx, rtx, int, rtx *);
361 static int contains_muldiv (rtx);
362 static rtx try_combine (rtx, rtx, rtx, int *);
363 static void undo_all (void);
364 static void undo_commit (void);
365 static rtx *find_split_point (rtx *, rtx);
366 static rtx subst (rtx, rtx, rtx, int, int);
367 static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
368 static rtx simplify_if_then_else (rtx);
369 static rtx simplify_set (rtx);
370 static rtx simplify_logical (rtx);
371 static rtx expand_compound_operation (rtx);
372 static rtx expand_field_assignment (rtx);
373 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
374 rtx, unsigned HOST_WIDE_INT, int, int, int);
375 static rtx extract_left_shift (rtx, int);
376 static rtx make_compound_operation (rtx, enum rtx_code);
377 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
378 unsigned HOST_WIDE_INT *);
379 static rtx force_to_mode (rtx, enum machine_mode,
380 unsigned HOST_WIDE_INT, rtx, int);
381 static rtx if_then_else_cond (rtx, rtx *, rtx *);
382 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
383 static int rtx_equal_for_field_assignment_p (rtx, rtx);
384 static rtx make_field_assignment (rtx);
385 static rtx apply_distributive_law (rtx);
386 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
387 unsigned HOST_WIDE_INT);
388 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
389 HOST_WIDE_INT, enum machine_mode, int *);
390 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
392 static int recog_for_combine (rtx *, rtx, rtx *);
393 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
394 static rtx gen_binary (enum rtx_code, enum machine_mode, rtx, rtx);
395 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
396 static void update_table_tick (rtx);
397 static void record_value_for_reg (rtx, rtx, rtx);
398 static void check_promoted_subreg (rtx, rtx);
399 static void record_dead_and_set_regs_1 (rtx, rtx, void *);
400 static void record_dead_and_set_regs (rtx);
401 static int get_last_value_validate (rtx *, rtx, int, int);
402 static rtx get_last_value (rtx);
403 static int use_crosses_set_p (rtx, int);
404 static void reg_dead_at_p_1 (rtx, rtx, void *);
405 static int reg_dead_at_p (rtx, rtx);
406 static void move_deaths (rtx, rtx, int, rtx, rtx *);
407 static int reg_bitfield_target_p (rtx, rtx);
408 static void distribute_notes (rtx, rtx, rtx, rtx);
409 static void distribute_links (rtx);
410 static void mark_used_regs_combine (rtx);
411 static int insn_cuid (rtx);
412 static void record_promoted_value (rtx, rtx);
413 static rtx reversed_comparison (rtx, enum machine_mode, rtx, rtx);
414 static enum rtx_code combine_reversed_comparison_code (rtx);
415 static int unmentioned_reg_p_1 (rtx *, void *);
416 static bool unmentioned_reg_p (rtx, rtx);
419 /* It is not safe to use ordinary gen_lowpart in combine.
420 See comments in gen_lowpart_for_combine. */
421 #undef RTL_HOOKS_GEN_LOWPART
422 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
424 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
425 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
427 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
428 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
430 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
433 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
434 insn. The substitution can be undone by undo_all. If INTO is already
435 set to NEWVAL, do not record this change. Because computing NEWVAL might
436 also call SUBST, we have to compute it before we put anything into
440 do_SUBST (rtx *into, rtx newval)
445 if (oldval == newval)
448 /* We'd like to catch as many invalid transformations here as
449 possible. Unfortunately, there are way too many mode changes
450 that are perfectly valid, so we'd waste too much effort for
451 little gain doing the checks here. Focus on catching invalid
452 transformations involving integer constants. */
453 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
454 && GET_CODE (newval) == CONST_INT)
456 /* Sanity check that we're replacing oldval with a CONST_INT
457 that is a valid sign-extension for the original mode. */
458 if (INTVAL (newval) != trunc_int_for_mode (INTVAL (newval),
462 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
463 CONST_INT is not valid, because after the replacement, the
464 original mode would be gone. Unfortunately, we can't tell
465 when do_SUBST is called to replace the operand thereof, so we
466 perform this test on oldval instead, checking whether an
467 invalid replacement took place before we got here. */
468 if ((GET_CODE (oldval) == SUBREG
469 && GET_CODE (SUBREG_REG (oldval)) == CONST_INT)
470 || (GET_CODE (oldval) == ZERO_EXTEND
471 && GET_CODE (XEXP (oldval, 0)) == CONST_INT))
476 buf = undobuf.frees, undobuf.frees = buf->next;
478 buf = xmalloc (sizeof (struct undo));
482 buf->old_contents.r = oldval;
485 buf->next = undobuf.undos, undobuf.undos = buf;
488 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
490 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
491 for the value of a HOST_WIDE_INT value (including CONST_INT) is
495 do_SUBST_INT (int *into, int newval)
500 if (oldval == newval)
504 buf = undobuf.frees, undobuf.frees = buf->next;
506 buf = xmalloc (sizeof (struct undo));
510 buf->old_contents.i = oldval;
513 buf->next = undobuf.undos, undobuf.undos = buf;
516 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
518 /* Calculate the rtx_cost of a single instruction. A return value of zero
519 indicates an instruction without a known cost. */
522 combine_insn_cost (rtx pat)
527 /* Extract the single set rtx from the instruction pattern.
528 We can't use single_set since we only have the pattern. */
529 if (GET_CODE (pat) == SET)
531 else if (GET_CODE (pat) == PARALLEL)
534 for (i = 0; i < XVECLEN (pat, 0); i++)
536 rtx x = XVECEXP (pat, 0, i);
537 if (GET_CODE (x) == SET)
550 cost = rtx_cost (SET_SRC (set), SET);
551 return cost > 0 ? cost : COSTS_N_INSNS (1);
554 /* Subroutine of try_combine. Determine whether the combine replacement
555 patterns NEWPAT and NEWI2PAT are cheaper according to combine_insn_cost
556 that the original instruction sequence I1, I2 and I3. Note that I1
557 and/or NEWI2PAT may be NULL_RTX. This function returns false, if the
558 costs of all instructions can be estimated, and the replacements are
559 more expensive than the original sequence. */
562 combine_validate_cost (rtx i1, rtx i2, rtx i3, rtx newpat, rtx newi2pat)
564 int i1_cost, i2_cost, i3_cost;
565 int new_i2_cost, new_i3_cost;
566 int old_cost, new_cost;
568 /* Lookup the original combine_insn_costs. */
569 i2_cost = INSN_UID (i2) <= last_insn_cost
570 ? uid_insn_cost[INSN_UID (i2)] : 0;
571 i3_cost = INSN_UID (i3) <= last_insn_cost
572 ? uid_insn_cost[INSN_UID (i3)] : 0;
576 i1_cost = INSN_UID (i1) <= last_insn_cost
577 ? uid_insn_cost[INSN_UID (i1)] : 0;
578 old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0)
579 ? i1_cost + i2_cost + i3_cost : 0;
583 old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
587 /* Calculate the replacement combine_insn_costs. */
588 new_i3_cost = combine_insn_cost (newpat);
591 new_i2_cost = combine_insn_cost (newi2pat);
592 new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
593 ? new_i2_cost + new_i3_cost : 0;
597 new_cost = new_i3_cost;
601 /* Disallow this recombination if both new_cost and old_cost are
602 greater than zero, and new_cost is greater than old cost. */
603 if (!undobuf.other_insn
605 && new_cost > old_cost)
612 "rejecting combination of insns %d, %d and %d\n",
613 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
614 fprintf (dump_file, "original costs %d + %d + %d = %d\n",
615 i1_cost, i2_cost, i3_cost, old_cost);
620 "rejecting combination of insns %d and %d\n",
621 INSN_UID (i2), INSN_UID (i3));
622 fprintf (dump_file, "original costs %d + %d = %d\n",
623 i2_cost, i3_cost, old_cost);
628 fprintf (dump_file, "replacement costs %d + %d = %d\n",
629 new_i2_cost, new_i3_cost, new_cost);
632 fprintf (dump_file, "replacement cost %d\n", new_cost);
638 /* Update the uid_insn_cost array with the replacement costs. */
639 uid_insn_cost[INSN_UID (i2)] = new_i2_cost;
640 uid_insn_cost[INSN_UID (i3)] = new_i3_cost;
642 uid_insn_cost[INSN_UID (i1)] = 0;
647 /* Main entry point for combiner. F is the first insn of the function.
648 NREGS is the first unused pseudo-reg number.
650 Return nonzero if the combiner has turned an indirect jump
651 instruction into a direct jump. */
653 combine_instructions (rtx f, unsigned int nregs)
660 rtx links, nextlinks;
662 int new_direct_jump_p = 0;
664 combine_attempts = 0;
667 combine_successes = 0;
669 combine_max_regno = nregs;
671 rtl_hooks = combine_rtl_hooks;
673 reg_stat = xcalloc (nregs, sizeof (struct reg_stat));
675 init_recog_no_volatile ();
677 /* Compute maximum uid value so uid_cuid can be allocated. */
679 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
680 if (INSN_UID (insn) > i)
683 uid_cuid = xmalloc ((i + 1) * sizeof (int));
686 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
688 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
689 problems when, for example, we have j <<= 1 in a loop. */
691 nonzero_sign_valid = 0;
693 /* Compute the mapping from uids to cuids.
694 Cuids are numbers assigned to insns, like uids,
695 except that cuids increase monotonically through the code.
697 Scan all SETs and see if we can deduce anything about what
698 bits are known to be zero for some registers and how many copies
699 of the sign bit are known to exist for those registers.
701 Also set any known values so that we can use it while searching
702 for what bits are known to be set. */
706 setup_incoming_promotions ();
708 refresh_blocks = sbitmap_alloc (last_basic_block);
709 sbitmap_zero (refresh_blocks);
711 /* Allocate array of current combine_insn_costs. */
712 uid_insn_cost = xcalloc (max_uid_cuid + 1, sizeof (int));
713 last_insn_cost = max_uid_cuid;
715 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
717 uid_cuid[INSN_UID (insn)] = ++i;
723 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
725 record_dead_and_set_regs (insn);
728 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
729 if (REG_NOTE_KIND (links) == REG_INC)
730 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
734 /* Record the current combine_insn_cost of this instruction. */
735 uid_insn_cost[INSN_UID (insn)] = combine_insn_cost (PATTERN (insn));
737 fprintf(dump_file, "insn_cost %d: %d\n",
738 INSN_UID (insn), uid_insn_cost[INSN_UID (insn)]);
741 if (GET_CODE (insn) == CODE_LABEL)
745 nonzero_sign_valid = 1;
747 /* Now scan all the insns in forward order. */
753 setup_incoming_promotions ();
755 FOR_EACH_BB (this_basic_block)
757 for (insn = BB_HEAD (this_basic_block);
758 insn != NEXT_INSN (BB_END (this_basic_block));
759 insn = next ? next : NEXT_INSN (insn))
763 if (GET_CODE (insn) == CODE_LABEL)
766 else if (INSN_P (insn))
768 /* See if we know about function return values before this
769 insn based upon SUBREG flags. */
770 check_promoted_subreg (insn, PATTERN (insn));
772 /* Try this insn with each insn it links back to. */
774 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
775 if ((next = try_combine (insn, XEXP (links, 0),
776 NULL_RTX, &new_direct_jump_p)) != 0)
779 /* Try each sequence of three linked insns ending with this one. */
781 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
783 rtx link = XEXP (links, 0);
785 /* If the linked insn has been replaced by a note, then there
786 is no point in pursuing this chain any further. */
787 if (GET_CODE (link) == NOTE)
790 for (nextlinks = LOG_LINKS (link);
792 nextlinks = XEXP (nextlinks, 1))
793 if ((next = try_combine (insn, link,
795 &new_direct_jump_p)) != 0)
800 /* Try to combine a jump insn that uses CC0
801 with a preceding insn that sets CC0, and maybe with its
802 logical predecessor as well.
803 This is how we make decrement-and-branch insns.
804 We need this special code because data flow connections
805 via CC0 do not get entered in LOG_LINKS. */
807 if (GET_CODE (insn) == JUMP_INSN
808 && (prev = prev_nonnote_insn (insn)) != 0
809 && GET_CODE (prev) == INSN
810 && sets_cc0_p (PATTERN (prev)))
812 if ((next = try_combine (insn, prev,
813 NULL_RTX, &new_direct_jump_p)) != 0)
816 for (nextlinks = LOG_LINKS (prev); nextlinks;
817 nextlinks = XEXP (nextlinks, 1))
818 if ((next = try_combine (insn, prev,
820 &new_direct_jump_p)) != 0)
824 /* Do the same for an insn that explicitly references CC0. */
825 if (GET_CODE (insn) == INSN
826 && (prev = prev_nonnote_insn (insn)) != 0
827 && GET_CODE (prev) == INSN
828 && sets_cc0_p (PATTERN (prev))
829 && GET_CODE (PATTERN (insn)) == SET
830 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
832 if ((next = try_combine (insn, prev,
833 NULL_RTX, &new_direct_jump_p)) != 0)
836 for (nextlinks = LOG_LINKS (prev); nextlinks;
837 nextlinks = XEXP (nextlinks, 1))
838 if ((next = try_combine (insn, prev,
840 &new_direct_jump_p)) != 0)
844 /* Finally, see if any of the insns that this insn links to
845 explicitly references CC0. If so, try this insn, that insn,
846 and its predecessor if it sets CC0. */
847 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
848 if (GET_CODE (XEXP (links, 0)) == INSN
849 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
850 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
851 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
852 && GET_CODE (prev) == INSN
853 && sets_cc0_p (PATTERN (prev))
854 && (next = try_combine (insn, XEXP (links, 0),
855 prev, &new_direct_jump_p)) != 0)
859 /* Try combining an insn with two different insns whose results it
861 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
862 for (nextlinks = XEXP (links, 1); nextlinks;
863 nextlinks = XEXP (nextlinks, 1))
864 if ((next = try_combine (insn, XEXP (links, 0),
866 &new_direct_jump_p)) != 0)
869 /* Try this insn with each REG_EQUAL note it links back to. */
870 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
873 rtx temp = XEXP (links, 0);
874 if ((set = single_set (temp)) != 0
875 && (note = find_reg_equal_equiv_note (temp)) != 0
876 && GET_CODE (XEXP (note, 0)) != EXPR_LIST
877 /* Avoid using a register that may already been marked
878 dead by an earlier instruction. */
879 && ! unmentioned_reg_p (XEXP (note, 0), SET_SRC (set)))
881 /* Temporarily replace the set's source with the
882 contents of the REG_EQUAL note. The insn will
883 be deleted or recognized by try_combine. */
884 rtx orig = SET_SRC (set);
885 SET_SRC (set) = XEXP (note, 0);
886 next = try_combine (insn, temp, NULL_RTX,
890 SET_SRC (set) = orig;
894 if (GET_CODE (insn) != NOTE)
895 record_dead_and_set_regs (insn);
904 EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks, 0, i,
905 BASIC_BLOCK (i)->flags |= BB_DIRTY);
906 new_direct_jump_p |= purge_all_dead_edges (0);
907 delete_noop_moves ();
909 update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES,
910 PROP_DEATH_NOTES | PROP_SCAN_DEAD_CODE
911 | PROP_KILL_DEAD_CODE);
914 sbitmap_free (refresh_blocks);
915 free (uid_insn_cost);
920 struct undo *undo, *next;
921 for (undo = undobuf.frees; undo; undo = next)
929 total_attempts += combine_attempts;
930 total_merges += combine_merges;
931 total_extras += combine_extras;
932 total_successes += combine_successes;
934 nonzero_sign_valid = 0;
935 rtl_hooks = general_rtl_hooks;
937 /* Make recognizer allow volatile MEMs again. */
940 return new_direct_jump_p;
943 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
949 for (i = 0; i < combine_max_regno; i++)
950 memset (reg_stat + i, 0, offsetof (struct reg_stat, sign_bit_copies));
953 /* Set up any promoted values for incoming argument registers. */
956 setup_incoming_promotions (void)
960 enum machine_mode mode;
962 rtx first = get_insns ();
964 if (targetm.calls.promote_function_args (TREE_TYPE (cfun->decl)))
966 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
967 /* Check whether this register can hold an incoming pointer
968 argument. FUNCTION_ARG_REGNO_P tests outgoing register
969 numbers, so translate if necessary due to register windows. */
970 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
971 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
974 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
977 gen_rtx_CLOBBER (mode, const0_rtx)));
982 /* Called via note_stores. If X is a pseudo that is narrower than
983 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
985 If we are setting only a portion of X and we can't figure out what
986 portion, assume all bits will be used since we don't know what will
989 Similarly, set how many bits of X are known to be copies of the sign bit
990 at all locations in the function. This is the smallest number implied
994 set_nonzero_bits_and_sign_copies (rtx x, rtx set,
995 void *data ATTRIBUTE_UNUSED)
1000 && REGNO (x) >= FIRST_PSEUDO_REGISTER
1001 /* If this register is undefined at the start of the file, we can't
1002 say what its contents were. */
1003 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, REGNO (x))
1004 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
1006 if (set == 0 || GET_CODE (set) == CLOBBER)
1008 reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1009 reg_stat[REGNO (x)].sign_bit_copies = 1;
1013 /* If this is a complex assignment, see if we can convert it into a
1014 simple assignment. */
1015 set = expand_field_assignment (set);
1017 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1018 set what we know about X. */
1020 if (SET_DEST (set) == x
1021 || (GET_CODE (SET_DEST (set)) == SUBREG
1022 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
1023 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
1024 && SUBREG_REG (SET_DEST (set)) == x))
1026 rtx src = SET_SRC (set);
1028 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1029 /* If X is narrower than a word and SRC is a non-negative
1030 constant that would appear negative in the mode of X,
1031 sign-extend it for use in reg_stat[].nonzero_bits because some
1032 machines (maybe most) will actually do the sign-extension
1033 and this is the conservative approach.
1035 ??? For 2.5, try to tighten up the MD files in this regard
1036 instead of this kludge. */
1038 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
1039 && GET_CODE (src) == CONST_INT
1041 && 0 != (INTVAL (src)
1042 & ((HOST_WIDE_INT) 1
1043 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
1044 src = GEN_INT (INTVAL (src)
1045 | ((HOST_WIDE_INT) (-1)
1046 << GET_MODE_BITSIZE (GET_MODE (x))));
1049 /* Don't call nonzero_bits if it cannot change anything. */
1050 if (reg_stat[REGNO (x)].nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1051 reg_stat[REGNO (x)].nonzero_bits
1052 |= nonzero_bits (src, nonzero_bits_mode);
1053 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1054 if (reg_stat[REGNO (x)].sign_bit_copies == 0
1055 || reg_stat[REGNO (x)].sign_bit_copies > num)
1056 reg_stat[REGNO (x)].sign_bit_copies = num;
1060 reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1061 reg_stat[REGNO (x)].sign_bit_copies = 1;
1066 /* See if INSN can be combined into I3. PRED and SUCC are optionally
1067 insns that were previously combined into I3 or that will be combined
1068 into the merger of INSN and I3.
1070 Return 0 if the combination is not allowed for any reason.
1072 If the combination is allowed, *PDEST will be set to the single
1073 destination of INSN and *PSRC to the single source, and this function
1077 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ,
1078 rtx *pdest, rtx *psrc)
1081 rtx set = 0, src, dest;
1086 int all_adjacent = (succ ? (next_active_insn (insn) == succ
1087 && next_active_insn (succ) == i3)
1088 : next_active_insn (insn) == i3);
1090 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1091 or a PARALLEL consisting of such a SET and CLOBBERs.
1093 If INSN has CLOBBER parallel parts, ignore them for our processing.
1094 By definition, these happen during the execution of the insn. When it
1095 is merged with another insn, all bets are off. If they are, in fact,
1096 needed and aren't also supplied in I3, they may be added by
1097 recog_for_combine. Otherwise, it won't match.
1099 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1102 Get the source and destination of INSN. If more than one, can't
1105 if (GET_CODE (PATTERN (insn)) == SET)
1106 set = PATTERN (insn);
1107 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1108 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1110 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1112 rtx elt = XVECEXP (PATTERN (insn), 0, i);
1115 switch (GET_CODE (elt))
1117 /* This is important to combine floating point insns
1118 for the SH4 port. */
1120 /* Combining an isolated USE doesn't make sense.
1121 We depend here on combinable_i3pat to reject them. */
1122 /* The code below this loop only verifies that the inputs of
1123 the SET in INSN do not change. We call reg_set_between_p
1124 to verify that the REG in the USE does not change between
1126 If the USE in INSN was for a pseudo register, the matching
1127 insn pattern will likely match any register; combining this
1128 with any other USE would only be safe if we knew that the
1129 used registers have identical values, or if there was
1130 something to tell them apart, e.g. different modes. For
1131 now, we forgo such complicated tests and simply disallow
1132 combining of USES of pseudo registers with any other USE. */
1133 if (REG_P (XEXP (elt, 0))
1134 && GET_CODE (PATTERN (i3)) == PARALLEL)
1136 rtx i3pat = PATTERN (i3);
1137 int i = XVECLEN (i3pat, 0) - 1;
1138 unsigned int regno = REGNO (XEXP (elt, 0));
1142 rtx i3elt = XVECEXP (i3pat, 0, i);
1144 if (GET_CODE (i3elt) == USE
1145 && REG_P (XEXP (i3elt, 0))
1146 && (REGNO (XEXP (i3elt, 0)) == regno
1147 ? reg_set_between_p (XEXP (elt, 0),
1148 PREV_INSN (insn), i3)
1149 : regno >= FIRST_PSEUDO_REGISTER))
1156 /* We can ignore CLOBBERs. */
1161 /* Ignore SETs whose result isn't used but not those that
1162 have side-effects. */
1163 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1164 && (!(note = find_reg_note (insn, REG_EH_REGION, NULL_RTX))
1165 || INTVAL (XEXP (note, 0)) <= 0)
1166 && ! side_effects_p (elt))
1169 /* If we have already found a SET, this is a second one and
1170 so we cannot combine with this insn. */
1178 /* Anything else means we can't combine. */
1184 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1185 so don't do anything with it. */
1186 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1195 set = expand_field_assignment (set);
1196 src = SET_SRC (set), dest = SET_DEST (set);
1198 /* Don't eliminate a store in the stack pointer. */
1199 if (dest == stack_pointer_rtx
1200 /* Don't combine with an insn that sets a register to itself if it has
1201 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1202 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1203 /* Can't merge an ASM_OPERANDS. */
1204 || GET_CODE (src) == ASM_OPERANDS
1205 /* Can't merge a function call. */
1206 || GET_CODE (src) == CALL
1207 /* Don't eliminate a function call argument. */
1208 || (GET_CODE (i3) == CALL_INSN
1209 && (find_reg_fusage (i3, USE, dest)
1211 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1212 && global_regs[REGNO (dest)])))
1213 /* Don't substitute into an incremented register. */
1214 || FIND_REG_INC_NOTE (i3, dest)
1215 || (succ && FIND_REG_INC_NOTE (succ, dest))
1217 /* Don't combine the end of a libcall into anything. */
1218 /* ??? This gives worse code, and appears to be unnecessary, since no
1219 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1220 use REG_RETVAL notes for noconflict blocks, but other code here
1221 makes sure that those insns don't disappear. */
1222 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1224 /* Make sure that DEST is not used after SUCC but before I3. */
1225 || (succ && ! all_adjacent
1226 && reg_used_between_p (dest, succ, i3))
1227 /* Make sure that the value that is to be substituted for the register
1228 does not use any registers whose values alter in between. However,
1229 If the insns are adjacent, a use can't cross a set even though we
1230 think it might (this can happen for a sequence of insns each setting
1231 the same destination; last_set of that register might point to
1232 a NOTE). If INSN has a REG_EQUIV note, the register is always
1233 equivalent to the memory so the substitution is valid even if there
1234 are intervening stores. Also, don't move a volatile asm or
1235 UNSPEC_VOLATILE across any other insns. */
1237 && (((GET_CODE (src) != MEM
1238 || ! find_reg_note (insn, REG_EQUIV, src))
1239 && use_crosses_set_p (src, INSN_CUID (insn)))
1240 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1241 || GET_CODE (src) == UNSPEC_VOLATILE))
1242 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1243 better register allocation by not doing the combine. */
1244 || find_reg_note (i3, REG_NO_CONFLICT, dest)
1245 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1246 /* Don't combine across a CALL_INSN, because that would possibly
1247 change whether the life span of some REGs crosses calls or not,
1248 and it is a pain to update that information.
1249 Exception: if source is a constant, moving it later can't hurt.
1250 Accept that special case, because it helps -fforce-addr a lot. */
1251 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1254 /* DEST must either be a REG or CC0. */
1257 /* If register alignment is being enforced for multi-word items in all
1258 cases except for parameters, it is possible to have a register copy
1259 insn referencing a hard register that is not allowed to contain the
1260 mode being copied and which would not be valid as an operand of most
1261 insns. Eliminate this problem by not combining with such an insn.
1263 Also, on some machines we don't want to extend the life of a hard
1267 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1268 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1269 /* Don't extend the life of a hard register unless it is
1270 user variable (if we have few registers) or it can't
1271 fit into the desired register (meaning something special
1273 Also avoid substituting a return register into I3, because
1274 reload can't handle a conflict with constraints of other
1276 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1277 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1280 else if (GET_CODE (dest) != CC0)
1284 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1285 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1286 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1288 /* Don't substitute for a register intended as a clobberable
1290 rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1291 if (rtx_equal_p (reg, dest))
1294 /* If the clobber represents an earlyclobber operand, we must not
1295 substitute an expression containing the clobbered register.
1296 As we do not analyse the constraint strings here, we have to
1297 make the conservative assumption. However, if the register is
1298 a fixed hard reg, the clobber cannot represent any operand;
1299 we leave it up to the machine description to either accept or
1300 reject use-and-clobber patterns. */
1302 || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1303 || !fixed_regs[REGNO (reg)])
1304 if (reg_overlap_mentioned_p (reg, src))
1308 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1309 or not), reject, unless nothing volatile comes between it and I3 */
1311 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1313 /* Make sure succ doesn't contain a volatile reference. */
1314 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1317 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1318 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1322 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1323 to be an explicit register variable, and was chosen for a reason. */
1325 if (GET_CODE (src) == ASM_OPERANDS
1326 && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1329 /* If there are any volatile insns between INSN and I3, reject, because
1330 they might affect machine state. */
1332 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1333 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1336 /* If INSN or I2 contains an autoincrement or autodecrement,
1337 make sure that register is not used between there and I3,
1338 and not already used in I3 either.
1339 Also insist that I3 not be a jump; if it were one
1340 and the incremented register were spilled, we would lose. */
1343 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1344 if (REG_NOTE_KIND (link) == REG_INC
1345 && (GET_CODE (i3) == JUMP_INSN
1346 || reg_used_between_p (XEXP (link, 0), insn, i3)
1347 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1352 /* Don't combine an insn that follows a CC0-setting insn.
1353 An insn that uses CC0 must not be separated from the one that sets it.
1354 We do, however, allow I2 to follow a CC0-setting insn if that insn
1355 is passed as I1; in that case it will be deleted also.
1356 We also allow combining in this case if all the insns are adjacent
1357 because that would leave the two CC0 insns adjacent as well.
1358 It would be more logical to test whether CC0 occurs inside I1 or I2,
1359 but that would be much slower, and this ought to be equivalent. */
1361 p = prev_nonnote_insn (insn);
1362 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
1367 /* If we get here, we have passed all the tests and the combination is
1376 /* LOC is the location within I3 that contains its pattern or the component
1377 of a PARALLEL of the pattern. We validate that it is valid for combining.
1379 One problem is if I3 modifies its output, as opposed to replacing it
1380 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1381 so would produce an insn that is not equivalent to the original insns.
1385 (set (reg:DI 101) (reg:DI 100))
1386 (set (subreg:SI (reg:DI 101) 0) <foo>)
1388 This is NOT equivalent to:
1390 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1391 (set (reg:DI 101) (reg:DI 100))])
1393 Not only does this modify 100 (in which case it might still be valid
1394 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1396 We can also run into a problem if I2 sets a register that I1
1397 uses and I1 gets directly substituted into I3 (not via I2). In that
1398 case, we would be getting the wrong value of I2DEST into I3, so we
1399 must reject the combination. This case occurs when I2 and I1 both
1400 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1401 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1402 of a SET must prevent combination from occurring.
1404 Before doing the above check, we first try to expand a field assignment
1405 into a set of logical operations.
1407 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1408 we place a register that is both set and used within I3. If more than one
1409 such register is detected, we fail.
1411 Return 1 if the combination is valid, zero otherwise. */
1414 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest,
1415 int i1_not_in_src, rtx *pi3dest_killed)
1419 if (GET_CODE (x) == SET)
1422 rtx dest = SET_DEST (set);
1423 rtx src = SET_SRC (set);
1424 rtx inner_dest = dest;
1426 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1427 || GET_CODE (inner_dest) == SUBREG
1428 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1429 inner_dest = XEXP (inner_dest, 0);
1431 /* Check for the case where I3 modifies its output, as discussed
1432 above. We don't want to prevent pseudos from being combined
1433 into the address of a MEM, so only prevent the combination if
1434 i1 or i2 set the same MEM. */
1435 if ((inner_dest != dest &&
1436 (GET_CODE (inner_dest) != MEM
1437 || rtx_equal_p (i2dest, inner_dest)
1438 || (i1dest && rtx_equal_p (i1dest, inner_dest)))
1439 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1440 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1442 /* This is the same test done in can_combine_p except we can't test
1443 all_adjacent; we don't have to, since this instruction will stay
1444 in place, thus we are not considering increasing the lifetime of
1447 Also, if this insn sets a function argument, combining it with
1448 something that might need a spill could clobber a previous
1449 function argument; the all_adjacent test in can_combine_p also
1450 checks this; here, we do a more specific test for this case. */
1452 || (REG_P (inner_dest)
1453 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1454 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1455 GET_MODE (inner_dest))))
1456 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1459 /* If DEST is used in I3, it is being killed in this insn,
1460 so record that for later.
1461 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1462 STACK_POINTER_REGNUM, since these are always considered to be
1463 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1464 if (pi3dest_killed && REG_P (dest)
1465 && reg_referenced_p (dest, PATTERN (i3))
1466 && REGNO (dest) != FRAME_POINTER_REGNUM
1467 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1468 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1470 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1471 && (REGNO (dest) != ARG_POINTER_REGNUM
1472 || ! fixed_regs [REGNO (dest)])
1474 && REGNO (dest) != STACK_POINTER_REGNUM)
1476 if (*pi3dest_killed)
1479 *pi3dest_killed = dest;
1483 else if (GET_CODE (x) == PARALLEL)
1487 for (i = 0; i < XVECLEN (x, 0); i++)
1488 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1489 i1_not_in_src, pi3dest_killed))
1496 /* Return 1 if X is an arithmetic expression that contains a multiplication
1497 and division. We don't count multiplications by powers of two here. */
1500 contains_muldiv (rtx x)
1502 switch (GET_CODE (x))
1504 case MOD: case DIV: case UMOD: case UDIV:
1508 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1509 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1512 return contains_muldiv (XEXP (x, 0))
1513 || contains_muldiv (XEXP (x, 1));
1516 return contains_muldiv (XEXP (x, 0));
1522 /* Determine whether INSN can be used in a combination. Return nonzero if
1523 not. This is used in try_combine to detect early some cases where we
1524 can't perform combinations. */
1527 cant_combine_insn_p (rtx insn)
1532 /* If this isn't really an insn, we can't do anything.
1533 This can occur when flow deletes an insn that it has merged into an
1534 auto-increment address. */
1535 if (! INSN_P (insn))
1538 /* Never combine loads and stores involving hard regs that are likely
1539 to be spilled. The register allocator can usually handle such
1540 reg-reg moves by tying. If we allow the combiner to make
1541 substitutions of likely-spilled regs, we may abort in reload.
1542 As an exception, we allow combinations involving fixed regs; these are
1543 not available to the register allocator so there's no risk involved. */
1545 set = single_set (insn);
1548 src = SET_SRC (set);
1549 dest = SET_DEST (set);
1550 if (GET_CODE (src) == SUBREG)
1551 src = SUBREG_REG (src);
1552 if (GET_CODE (dest) == SUBREG)
1553 dest = SUBREG_REG (dest);
1554 if (REG_P (src) && REG_P (dest)
1555 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
1556 && ! fixed_regs[REGNO (src)]
1557 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src))))
1558 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
1559 && ! fixed_regs[REGNO (dest)]
1560 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest))))))
1566 /* Adjust INSN after we made a change to its destination.
1568 Changing the destination can invalidate notes that say something about
1569 the results of the insn and a LOG_LINK pointing to the insn. */
1572 adjust_for_new_dest (rtx insn)
1576 /* For notes, be conservative and simply remove them. */
1577 loc = ®_NOTES (insn);
1580 enum reg_note kind = REG_NOTE_KIND (*loc);
1581 if (kind == REG_EQUAL || kind == REG_EQUIV)
1582 *loc = XEXP (*loc, 1);
1584 loc = &XEXP (*loc, 1);
1587 /* The new insn will have a destination that was previously the destination
1588 of an insn just above it. Call distribute_links to make a LOG_LINK from
1589 the next use of that destination. */
1590 distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX));
1593 /* Try to combine the insns I1 and I2 into I3.
1594 Here I1 and I2 appear earlier than I3.
1595 I1 can be zero; then we combine just I2 into I3.
1597 If we are combining three insns and the resulting insn is not recognized,
1598 try splitting it into two insns. If that happens, I2 and I3 are retained
1599 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1602 Return 0 if the combination does not work. Then nothing is changed.
1603 If we did the combination, return the insn at which combine should
1606 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1607 new direct jump instruction. */
1610 try_combine (rtx i3, rtx i2, rtx i1, int *new_direct_jump_p)
1612 /* New patterns for I3 and I2, respectively. */
1613 rtx newpat, newi2pat = 0;
1614 int substed_i2 = 0, substed_i1 = 0;
1615 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1616 int added_sets_1, added_sets_2;
1617 /* Total number of SETs to put into I3. */
1619 /* Nonzero if I2's body now appears in I3. */
1621 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1622 int insn_code_number, i2_code_number = 0, other_code_number = 0;
1623 /* Contains I3 if the destination of I3 is used in its source, which means
1624 that the old life of I3 is being killed. If that usage is placed into
1625 I2 and not in I3, a REG_DEAD note must be made. */
1626 rtx i3dest_killed = 0;
1627 /* SET_DEST and SET_SRC of I2 and I1. */
1628 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1629 /* PATTERN (I2), or a copy of it in certain cases. */
1631 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1632 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1633 int i1_feeds_i3 = 0;
1634 /* Notes that must be added to REG_NOTES in I3 and I2. */
1635 rtx new_i3_notes, new_i2_notes;
1636 /* Notes that we substituted I3 into I2 instead of the normal case. */
1637 int i3_subst_into_i2 = 0;
1638 /* Notes that I1, I2 or I3 is a MULT operation. */
1646 /* Exit early if one of the insns involved can't be used for
1648 if (cant_combine_insn_p (i3)
1649 || cant_combine_insn_p (i2)
1650 || (i1 && cant_combine_insn_p (i1))
1651 /* We also can't do anything if I3 has a
1652 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1655 /* ??? This gives worse code, and appears to be unnecessary, since no
1656 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1657 || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1663 undobuf.other_insn = 0;
1665 /* Reset the hard register usage information. */
1666 CLEAR_HARD_REG_SET (newpat_used_regs);
1668 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1669 code below, set I1 to be the earlier of the two insns. */
1670 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1671 temp = i1, i1 = i2, i2 = temp;
1673 added_links_insn = 0;
1675 /* First check for one important special-case that the code below will
1676 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1677 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1678 we may be able to replace that destination with the destination of I3.
1679 This occurs in the common code where we compute both a quotient and
1680 remainder into a structure, in which case we want to do the computation
1681 directly into the structure to avoid register-register copies.
1683 Note that this case handles both multiple sets in I2 and also
1684 cases where I2 has a number of CLOBBER or PARALLELs.
1686 We make very conservative checks below and only try to handle the
1687 most common cases of this. For example, we only handle the case
1688 where I2 and I3 are adjacent to avoid making difficult register
1691 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1692 && REG_P (SET_SRC (PATTERN (i3)))
1693 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1694 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1695 && GET_CODE (PATTERN (i2)) == PARALLEL
1696 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1697 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1698 below would need to check what is inside (and reg_overlap_mentioned_p
1699 doesn't support those codes anyway). Don't allow those destinations;
1700 the resulting insn isn't likely to be recognized anyway. */
1701 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1702 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1703 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1704 SET_DEST (PATTERN (i3)))
1705 && next_real_insn (i2) == i3)
1707 rtx p2 = PATTERN (i2);
1709 /* Make sure that the destination of I3,
1710 which we are going to substitute into one output of I2,
1711 is not used within another output of I2. We must avoid making this:
1712 (parallel [(set (mem (reg 69)) ...)
1713 (set (reg 69) ...)])
1714 which is not well-defined as to order of actions.
1715 (Besides, reload can't handle output reloads for this.)
1717 The problem can also happen if the dest of I3 is a memory ref,
1718 if another dest in I2 is an indirect memory ref. */
1719 for (i = 0; i < XVECLEN (p2, 0); i++)
1720 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1721 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1722 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1723 SET_DEST (XVECEXP (p2, 0, i))))
1726 if (i == XVECLEN (p2, 0))
1727 for (i = 0; i < XVECLEN (p2, 0); i++)
1728 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1729 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1730 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1735 subst_low_cuid = INSN_CUID (i2);
1737 added_sets_2 = added_sets_1 = 0;
1738 i2dest = SET_SRC (PATTERN (i3));
1740 /* Replace the dest in I2 with our dest and make the resulting
1741 insn the new pattern for I3. Then skip to where we
1742 validate the pattern. Everything was set up above. */
1743 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1744 SET_DEST (PATTERN (i3)));
1747 i3_subst_into_i2 = 1;
1748 goto validate_replacement;
1752 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1753 one of those words to another constant, merge them by making a new
1756 && (temp = single_set (i2)) != 0
1757 && (GET_CODE (SET_SRC (temp)) == CONST_INT
1758 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1759 && REG_P (SET_DEST (temp))
1760 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp))) == MODE_INT
1761 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp))) == 2 * UNITS_PER_WORD
1762 && GET_CODE (PATTERN (i3)) == SET
1763 && GET_CODE (SET_DEST (PATTERN (i3))) == SUBREG
1764 && SUBREG_REG (SET_DEST (PATTERN (i3))) == SET_DEST (temp)
1765 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3)))) == MODE_INT
1766 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3)))) == UNITS_PER_WORD
1767 && GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT)
1769 HOST_WIDE_INT lo, hi;
1771 if (GET_CODE (SET_SRC (temp)) == CONST_INT)
1772 lo = INTVAL (SET_SRC (temp)), hi = lo < 0 ? -1 : 0;
1775 lo = CONST_DOUBLE_LOW (SET_SRC (temp));
1776 hi = CONST_DOUBLE_HIGH (SET_SRC (temp));
1779 if (subreg_lowpart_p (SET_DEST (PATTERN (i3))))
1781 /* We don't handle the case of the target word being wider
1782 than a host wide int. */
1783 if (HOST_BITS_PER_WIDE_INT < BITS_PER_WORD)
1786 lo &= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1787 lo |= (INTVAL (SET_SRC (PATTERN (i3)))
1788 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1790 else if (HOST_BITS_PER_WIDE_INT == BITS_PER_WORD)
1791 hi = INTVAL (SET_SRC (PATTERN (i3)));
1792 else if (HOST_BITS_PER_WIDE_INT >= 2 * BITS_PER_WORD)
1794 int sign = -(int) ((unsigned HOST_WIDE_INT) lo
1795 >> (HOST_BITS_PER_WIDE_INT - 1));
1797 lo &= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1798 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1799 lo |= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1800 (INTVAL (SET_SRC (PATTERN (i3)))));
1802 hi = lo < 0 ? -1 : 0;
1805 /* We don't handle the case of the higher word not fitting
1806 entirely in either hi or lo. */
1811 subst_low_cuid = INSN_CUID (i2);
1812 added_sets_2 = added_sets_1 = 0;
1813 i2dest = SET_DEST (temp);
1815 SUBST (SET_SRC (temp),
1816 immed_double_const (lo, hi, GET_MODE (SET_DEST (temp))));
1818 newpat = PATTERN (i2);
1819 goto validate_replacement;
1823 /* If we have no I1 and I2 looks like:
1824 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1826 make up a dummy I1 that is
1829 (set (reg:CC X) (compare:CC Y (const_int 0)))
1831 (We can ignore any trailing CLOBBERs.)
1833 This undoes a previous combination and allows us to match a branch-and-
1836 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1837 && XVECLEN (PATTERN (i2), 0) >= 2
1838 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1839 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1841 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1842 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1843 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1844 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
1845 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1846 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1848 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1849 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1854 /* We make I1 with the same INSN_UID as I2. This gives it
1855 the same INSN_CUID for value tracking. Our fake I1 will
1856 never appear in the insn stream so giving it the same INSN_UID
1857 as I2 will not cause a problem. */
1859 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1860 BLOCK_FOR_INSN (i2), INSN_LOCATOR (i2),
1861 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
1864 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1865 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1866 SET_DEST (PATTERN (i1)));
1871 /* Verify that I2 and I1 are valid for combining. */
1872 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1873 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1879 /* Record whether I2DEST is used in I2SRC and similarly for the other
1880 cases. Knowing this will help in register status updating below. */
1881 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1882 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1883 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1885 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1887 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1889 /* Ensure that I3's pattern can be the destination of combines. */
1890 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1891 i1 && i2dest_in_i1src && i1_feeds_i3,
1898 /* See if any of the insns is a MULT operation. Unless one is, we will
1899 reject a combination that is, since it must be slower. Be conservative
1901 if (GET_CODE (i2src) == MULT
1902 || (i1 != 0 && GET_CODE (i1src) == MULT)
1903 || (GET_CODE (PATTERN (i3)) == SET
1904 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1907 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1908 We used to do this EXCEPT in one case: I3 has a post-inc in an
1909 output operand. However, that exception can give rise to insns like
1911 which is a famous insn on the PDP-11 where the value of r3 used as the
1912 source was model-dependent. Avoid this sort of thing. */
1915 if (!(GET_CODE (PATTERN (i3)) == SET
1916 && REG_P (SET_SRC (PATTERN (i3)))
1917 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1918 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1919 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1920 /* It's not the exception. */
1923 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1924 if (REG_NOTE_KIND (link) == REG_INC
1925 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1927 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1934 /* See if the SETs in I1 or I2 need to be kept around in the merged
1935 instruction: whenever the value set there is still needed past I3.
1936 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1938 For the SET in I1, we have two cases: If I1 and I2 independently
1939 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1940 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1941 in I1 needs to be kept around unless I1DEST dies or is set in either
1942 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1943 I1DEST. If so, we know I1 feeds into I2. */
1945 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1948 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1949 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1951 /* If the set in I2 needs to be kept around, we must make a copy of
1952 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1953 PATTERN (I2), we are only substituting for the original I1DEST, not into
1954 an already-substituted copy. This also prevents making self-referential
1955 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1958 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1959 ? gen_rtx_SET (VOIDmode, i2dest, i2src)
1963 i2pat = copy_rtx (i2pat);
1967 /* Substitute in the latest insn for the regs set by the earlier ones. */
1969 maxreg = max_reg_num ();
1973 /* It is possible that the source of I2 or I1 may be performing an
1974 unneeded operation, such as a ZERO_EXTEND of something that is known
1975 to have the high part zero. Handle that case by letting subst look at
1976 the innermost one of them.
1978 Another way to do this would be to have a function that tries to
1979 simplify a single insn instead of merging two or more insns. We don't
1980 do this because of the potential of infinite loops and because
1981 of the potential extra memory required. However, doing it the way
1982 we are is a bit of a kludge and doesn't catch all cases.
1984 But only do this if -fexpensive-optimizations since it slows things down
1985 and doesn't usually win. */
1987 if (flag_expensive_optimizations)
1989 /* Pass pc_rtx so no substitutions are done, just simplifications. */
1992 subst_low_cuid = INSN_CUID (i1);
1993 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1997 subst_low_cuid = INSN_CUID (i2);
1998 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
2003 /* Many machines that don't use CC0 have insns that can both perform an
2004 arithmetic operation and set the condition code. These operations will
2005 be represented as a PARALLEL with the first element of the vector
2006 being a COMPARE of an arithmetic operation with the constant zero.
2007 The second element of the vector will set some pseudo to the result
2008 of the same arithmetic operation. If we simplify the COMPARE, we won't
2009 match such a pattern and so will generate an extra insn. Here we test
2010 for this case, where both the comparison and the operation result are
2011 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2012 I2SRC. Later we will make the PARALLEL that contains I2. */
2014 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
2015 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
2016 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
2017 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2019 #ifdef SELECT_CC_MODE
2021 enum machine_mode compare_mode;
2024 newpat = PATTERN (i3);
2025 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
2029 #ifdef SELECT_CC_MODE
2030 /* See if a COMPARE with the operand we substituted in should be done
2031 with the mode that is currently being used. If not, do the same
2032 processing we do in `subst' for a SET; namely, if the destination
2033 is used only once, try to replace it with a register of the proper
2034 mode and also replace the COMPARE. */
2035 if (undobuf.other_insn == 0
2036 && (cc_use = find_single_use (SET_DEST (newpat), i3,
2037 &undobuf.other_insn))
2038 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
2040 != GET_MODE (SET_DEST (newpat))))
2042 unsigned int regno = REGNO (SET_DEST (newpat));
2043 rtx new_dest = gen_rtx_REG (compare_mode, regno);
2045 if (regno < FIRST_PSEUDO_REGISTER
2046 || (REG_N_SETS (regno) == 1 && ! added_sets_2
2047 && ! REG_USERVAR_P (SET_DEST (newpat))))
2049 if (regno >= FIRST_PSEUDO_REGISTER)
2050 SUBST (regno_reg_rtx[regno], new_dest);
2052 SUBST (SET_DEST (newpat), new_dest);
2053 SUBST (XEXP (*cc_use, 0), new_dest);
2054 SUBST (SET_SRC (newpat),
2055 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
2058 undobuf.other_insn = 0;
2065 n_occurrences = 0; /* `subst' counts here */
2067 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2068 need to make a unique copy of I2SRC each time we substitute it
2069 to avoid self-referential rtl. */
2071 subst_low_cuid = INSN_CUID (i2);
2072 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
2073 ! i1_feeds_i3 && i1dest_in_i1src);
2076 /* Record whether i2's body now appears within i3's body. */
2077 i2_is_used = n_occurrences;
2080 /* If we already got a failure, don't try to do more. Otherwise,
2081 try to substitute in I1 if we have it. */
2083 if (i1 && GET_CODE (newpat) != CLOBBER)
2085 /* Before we can do this substitution, we must redo the test done
2086 above (see detailed comments there) that ensures that I1DEST
2087 isn't mentioned in any SETs in NEWPAT that are field assignments. */
2089 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
2097 subst_low_cuid = INSN_CUID (i1);
2098 newpat = subst (newpat, i1dest, i1src, 0, 0);
2102 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2103 to count all the ways that I2SRC and I1SRC can be used. */
2104 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
2105 && i2_is_used + added_sets_2 > 1)
2106 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2107 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
2109 /* Fail if we tried to make a new register (we used to abort, but there's
2110 really no reason to). */
2111 || max_reg_num () != maxreg
2112 /* Fail if we couldn't do something and have a CLOBBER. */
2113 || GET_CODE (newpat) == CLOBBER
2114 /* Fail if this new pattern is a MULT and we didn't have one before
2115 at the outer level. */
2116 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
2123 /* If the actions of the earlier insns must be kept
2124 in addition to substituting them into the latest one,
2125 we must make a new PARALLEL for the latest insn
2126 to hold additional the SETs. */
2128 if (added_sets_1 || added_sets_2)
2132 if (GET_CODE (newpat) == PARALLEL)
2134 rtvec old = XVEC (newpat, 0);
2135 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2136 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2137 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
2138 sizeof (old->elem[0]) * old->num_elem);
2143 total_sets = 1 + added_sets_1 + added_sets_2;
2144 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2145 XVECEXP (newpat, 0, 0) = old;
2149 XVECEXP (newpat, 0, --total_sets)
2150 = (GET_CODE (PATTERN (i1)) == PARALLEL
2151 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
2155 /* If there is no I1, use I2's body as is. We used to also not do
2156 the subst call below if I2 was substituted into I3,
2157 but that could lose a simplification. */
2159 XVECEXP (newpat, 0, --total_sets) = i2pat;
2161 /* See comment where i2pat is assigned. */
2162 XVECEXP (newpat, 0, --total_sets)
2163 = subst (i2pat, i1dest, i1src, 0, 0);
2167 /* We come here when we are replacing a destination in I2 with the
2168 destination of I3. */
2169 validate_replacement:
2171 /* Note which hard regs this insn has as inputs. */
2172 mark_used_regs_combine (newpat);
2174 /* Is the result of combination a valid instruction? */
2175 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2177 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2178 the second SET's destination is a register that is unused and isn't
2179 marked as an instruction that might trap in an EH region. In that case,
2180 we just need the first SET. This can occur when simplifying a divmod
2181 insn. We *must* test for this case here because the code below that
2182 splits two independent SETs doesn't handle this case correctly when it
2183 updates the register status.
2185 It's pointless doing this if we originally had two sets, one from
2186 i3, and one from i2. Combining then splitting the parallel results
2187 in the original i2 again plus an invalid insn (which we delete).
2188 The net effect is only to move instructions around, which makes
2189 debug info less accurate.
2191 Also check the case where the first SET's destination is unused.
2192 That would not cause incorrect code, but does cause an unneeded
2195 if (insn_code_number < 0
2196 && !(added_sets_2 && i1 == 0)
2197 && GET_CODE (newpat) == PARALLEL
2198 && XVECLEN (newpat, 0) == 2
2199 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2200 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2201 && asm_noperands (newpat) < 0)
2203 rtx set0 = XVECEXP (newpat, 0, 0);
2204 rtx set1 = XVECEXP (newpat, 0, 1);
2207 if (((REG_P (SET_DEST (set1))
2208 && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
2209 || (GET_CODE (SET_DEST (set1)) == SUBREG
2210 && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
2211 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2212 || INTVAL (XEXP (note, 0)) <= 0)
2213 && ! side_effects_p (SET_SRC (set1)))
2216 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2219 else if (((REG_P (SET_DEST (set0))
2220 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
2221 || (GET_CODE (SET_DEST (set0)) == SUBREG
2222 && find_reg_note (i3, REG_UNUSED,
2223 SUBREG_REG (SET_DEST (set0)))))
2224 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2225 || INTVAL (XEXP (note, 0)) <= 0)
2226 && ! side_effects_p (SET_SRC (set0)))
2229 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2231 if (insn_code_number >= 0)
2233 /* If we will be able to accept this, we have made a
2234 change to the destination of I3. This requires us to
2235 do a few adjustments. */
2237 PATTERN (i3) = newpat;
2238 adjust_for_new_dest (i3);
2243 /* If we were combining three insns and the result is a simple SET
2244 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2245 insns. There are two ways to do this. It can be split using a
2246 machine-specific method (like when you have an addition of a large
2247 constant) or by combine in the function find_split_point. */
2249 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2250 && asm_noperands (newpat) < 0)
2252 rtx m_split, *split;
2253 rtx ni2dest = i2dest;
2255 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2256 use I2DEST as a scratch register will help. In the latter case,
2257 convert I2DEST to the mode of the source of NEWPAT if we can. */
2259 m_split = split_insns (newpat, i3);
2261 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2262 inputs of NEWPAT. */
2264 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2265 possible to try that as a scratch reg. This would require adding
2266 more code to make it work though. */
2268 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
2270 /* If I2DEST is a hard register or the only use of a pseudo,
2271 we can change its mode. */
2272 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
2273 && GET_MODE (SET_DEST (newpat)) != VOIDmode
2275 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2276 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2277 && ! REG_USERVAR_P (i2dest))))
2278 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
2281 m_split = split_insns (gen_rtx_PARALLEL
2283 gen_rtvec (2, newpat,
2284 gen_rtx_CLOBBER (VOIDmode,
2287 /* If the split with the mode-changed register didn't work, try
2288 the original register. */
2289 if (! m_split && ni2dest != i2dest)
2292 m_split = split_insns (gen_rtx_PARALLEL
2294 gen_rtvec (2, newpat,
2295 gen_rtx_CLOBBER (VOIDmode,
2301 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
2303 m_split = PATTERN (m_split);
2304 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
2305 if (insn_code_number >= 0)
2308 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
2309 && (next_real_insn (i2) == i3
2310 || ! use_crosses_set_p (PATTERN (m_split), INSN_CUID (i2))))
2313 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
2314 newi2pat = PATTERN (m_split);
2316 i3set = single_set (NEXT_INSN (m_split));
2317 i2set = single_set (m_split);
2319 /* In case we changed the mode of I2DEST, replace it in the
2320 pseudo-register table here. We can't do it above in case this
2321 code doesn't get executed and we do a split the other way. */
2323 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2324 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
2326 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2328 /* If I2 or I3 has multiple SETs, we won't know how to track
2329 register status, so don't use these insns. If I2's destination
2330 is used between I2 and I3, we also can't use these insns. */
2332 if (i2_code_number >= 0 && i2set && i3set
2333 && (next_real_insn (i2) == i3
2334 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2335 insn_code_number = recog_for_combine (&newi3pat, i3,
2337 if (insn_code_number >= 0)
2340 /* It is possible that both insns now set the destination of I3.
2341 If so, we must show an extra use of it. */
2343 if (insn_code_number >= 0)
2345 rtx new_i3_dest = SET_DEST (i3set);
2346 rtx new_i2_dest = SET_DEST (i2set);
2348 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2349 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2350 || GET_CODE (new_i3_dest) == SUBREG)
2351 new_i3_dest = XEXP (new_i3_dest, 0);
2353 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2354 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2355 || GET_CODE (new_i2_dest) == SUBREG)
2356 new_i2_dest = XEXP (new_i2_dest, 0);
2358 if (REG_P (new_i3_dest)
2359 && REG_P (new_i2_dest)
2360 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2361 REG_N_SETS (REGNO (new_i2_dest))++;
2365 /* If we can split it and use I2DEST, go ahead and see if that
2366 helps things be recognized. Verify that none of the registers
2367 are set between I2 and I3. */
2368 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2372 /* We need I2DEST in the proper mode. If it is a hard register
2373 or the only use of a pseudo, we can change its mode. */
2374 && (GET_MODE (*split) == GET_MODE (i2dest)
2375 || GET_MODE (*split) == VOIDmode
2376 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2377 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2378 && ! REG_USERVAR_P (i2dest)))
2379 && (next_real_insn (i2) == i3
2380 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2381 /* We can't overwrite I2DEST if its value is still used by
2383 && ! reg_referenced_p (i2dest, newpat))
2385 rtx newdest = i2dest;
2386 enum rtx_code split_code = GET_CODE (*split);
2387 enum machine_mode split_mode = GET_MODE (*split);
2389 /* Get NEWDEST as a register in the proper mode. We have already
2390 validated that we can do this. */
2391 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2393 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2395 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2396 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
2399 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2400 an ASHIFT. This can occur if it was inside a PLUS and hence
2401 appeared to be a memory address. This is a kludge. */
2402 if (split_code == MULT
2403 && GET_CODE (XEXP (*split, 1)) == CONST_INT
2404 && INTVAL (XEXP (*split, 1)) > 0
2405 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2407 SUBST (*split, gen_rtx_ASHIFT (split_mode,
2408 XEXP (*split, 0), GEN_INT (i)));
2409 /* Update split_code because we may not have a multiply
2411 split_code = GET_CODE (*split);
2414 #ifdef INSN_SCHEDULING
2415 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2416 be written as a ZERO_EXTEND. */
2417 if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM)
2419 #ifdef LOAD_EXTEND_OP
2420 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2421 what it really is. */
2422 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
2424 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
2425 SUBREG_REG (*split)));
2428 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
2429 SUBREG_REG (*split)));
2433 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
2434 SUBST (*split, newdest);
2435 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2437 /* If the split point was a MULT and we didn't have one before,
2438 don't use one now. */
2439 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2440 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2444 /* Check for a case where we loaded from memory in a narrow mode and
2445 then sign extended it, but we need both registers. In that case,
2446 we have a PARALLEL with both loads from the same memory location.
2447 We can split this into a load from memory followed by a register-register
2448 copy. This saves at least one insn, more if register allocation can
2451 We cannot do this if the destination of the first assignment is a
2452 condition code register or cc0. We eliminate this case by making sure
2453 the SET_DEST and SET_SRC have the same mode.
2455 We cannot do this if the destination of the second assignment is
2456 a register that we have already assumed is zero-extended. Similarly
2457 for a SUBREG of such a register. */
2459 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2460 && GET_CODE (newpat) == PARALLEL
2461 && XVECLEN (newpat, 0) == 2
2462 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2463 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2464 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
2465 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
2466 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2467 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2468 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2469 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2471 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2472 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2473 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2475 && reg_stat[REGNO (temp)].nonzero_bits != 0
2476 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2477 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2478 && (reg_stat[REGNO (temp)].nonzero_bits
2479 != GET_MODE_MASK (word_mode))))
2480 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2481 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2483 && reg_stat[REGNO (temp)].nonzero_bits != 0
2484 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2485 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2486 && (reg_stat[REGNO (temp)].nonzero_bits
2487 != GET_MODE_MASK (word_mode)))))
2488 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2489 SET_SRC (XVECEXP (newpat, 0, 1)))
2490 && ! find_reg_note (i3, REG_UNUSED,
2491 SET_DEST (XVECEXP (newpat, 0, 0))))
2495 newi2pat = XVECEXP (newpat, 0, 0);
2496 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2497 newpat = XVECEXP (newpat, 0, 1);
2498 SUBST (SET_SRC (newpat),
2499 gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
2500 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2502 if (i2_code_number >= 0)
2503 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2505 if (insn_code_number >= 0)
2510 /* If we will be able to accept this, we have made a change to the
2511 destination of I3. This requires us to do a few adjustments. */
2512 PATTERN (i3) = newpat;
2513 adjust_for_new_dest (i3);
2515 /* I3 now uses what used to be its destination and which is
2516 now I2's destination. That means we need a LOG_LINK from
2517 I3 to I2. But we used to have one, so we still will.
2519 However, some later insn might be using I2's dest and have
2520 a LOG_LINK pointing at I3. We must remove this link.
2521 The simplest way to remove the link is to point it at I1,
2522 which we know will be a NOTE. */
2524 for (insn = NEXT_INSN (i3);
2525 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
2526 || insn != BB_HEAD (this_basic_block->next_bb));
2527 insn = NEXT_INSN (insn))
2529 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
2531 for (link = LOG_LINKS (insn); link;
2532 link = XEXP (link, 1))
2533 if (XEXP (link, 0) == i3)
2534 XEXP (link, 0) = i1;
2542 /* Similarly, check for a case where we have a PARALLEL of two independent
2543 SETs but we started with three insns. In this case, we can do the sets
2544 as two separate insns. This case occurs when some SET allows two
2545 other insns to combine, but the destination of that SET is still live. */
2547 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2548 && GET_CODE (newpat) == PARALLEL
2549 && XVECLEN (newpat, 0) == 2
2550 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2551 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2552 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2553 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2554 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2555 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2556 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2558 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2559 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2560 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2561 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2562 XVECEXP (newpat, 0, 0))
2563 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2564 XVECEXP (newpat, 0, 1))
2565 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2566 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
2568 /* Normally, it doesn't matter which of the two is done first,
2569 but it does if one references cc0. In that case, it has to
2572 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2574 newi2pat = XVECEXP (newpat, 0, 0);
2575 newpat = XVECEXP (newpat, 0, 1);
2580 newi2pat = XVECEXP (newpat, 0, 1);
2581 newpat = XVECEXP (newpat, 0, 0);
2584 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2586 if (i2_code_number >= 0)
2587 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2590 /* If it still isn't recognized, fail and change things back the way they
2592 if ((insn_code_number < 0
2593 /* Is the result a reasonable ASM_OPERANDS? */
2594 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2600 /* If we had to change another insn, make sure it is valid also. */
2601 if (undobuf.other_insn)
2603 rtx other_pat = PATTERN (undobuf.other_insn);
2604 rtx new_other_notes;
2607 CLEAR_HARD_REG_SET (newpat_used_regs);
2609 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2612 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2618 PATTERN (undobuf.other_insn) = other_pat;
2620 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2621 are still valid. Then add any non-duplicate notes added by
2622 recog_for_combine. */
2623 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2625 next = XEXP (note, 1);
2627 if (REG_NOTE_KIND (note) == REG_UNUSED
2628 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2630 if (REG_P (XEXP (note, 0)))
2631 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2633 remove_note (undobuf.other_insn, note);
2637 for (note = new_other_notes; note; note = XEXP (note, 1))
2638 if (REG_P (XEXP (note, 0)))
2639 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2641 distribute_notes (new_other_notes, undobuf.other_insn,
2642 undobuf.other_insn, NULL_RTX);
2645 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
2646 they are adjacent to each other or not. */
2648 rtx p = prev_nonnote_insn (i3);
2649 if (p && p != i2 && GET_CODE (p) == INSN && newi2pat
2650 && sets_cc0_p (newi2pat))
2658 /* Only allow this combination if combine_insn_costs reports that the
2659 replacement instructions are cheaper than the originals. */
2660 if (!combine_validate_cost (i1, i2, i3, newpat, newi2pat))
2666 /* We now know that we can do this combination. Merge the insns and
2667 update the status of registers and LOG_LINKS. */
2670 rtx i3notes, i2notes, i1notes = 0;
2671 rtx i3links, i2links, i1links = 0;
2675 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2677 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2678 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2680 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2682 /* Ensure that we do not have something that should not be shared but
2683 occurs multiple times in the new insns. Check this by first
2684 resetting all the `used' flags and then copying anything is shared. */
2686 reset_used_flags (i3notes);
2687 reset_used_flags (i2notes);
2688 reset_used_flags (i1notes);
2689 reset_used_flags (newpat);
2690 reset_used_flags (newi2pat);
2691 if (undobuf.other_insn)
2692 reset_used_flags (PATTERN (undobuf.other_insn));
2694 i3notes = copy_rtx_if_shared (i3notes);
2695 i2notes = copy_rtx_if_shared (i2notes);
2696 i1notes = copy_rtx_if_shared (i1notes);
2697 newpat = copy_rtx_if_shared (newpat);
2698 newi2pat = copy_rtx_if_shared (newi2pat);
2699 if (undobuf.other_insn)
2700 reset_used_flags (PATTERN (undobuf.other_insn));
2702 INSN_CODE (i3) = insn_code_number;
2703 PATTERN (i3) = newpat;
2705 if (GET_CODE (i3) == CALL_INSN && CALL_INSN_FUNCTION_USAGE (i3))
2707 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
2709 reset_used_flags (call_usage);
2710 call_usage = copy_rtx (call_usage);
2713 replace_rtx (call_usage, i2dest, i2src);
2716 replace_rtx (call_usage, i1dest, i1src);
2718 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
2721 if (undobuf.other_insn)
2722 INSN_CODE (undobuf.other_insn) = other_code_number;
2724 /* We had one special case above where I2 had more than one set and
2725 we replaced a destination of one of those sets with the destination
2726 of I3. In that case, we have to update LOG_LINKS of insns later
2727 in this basic block. Note that this (expensive) case is rare.
2729 Also, in this case, we must pretend that all REG_NOTEs for I2
2730 actually came from I3, so that REG_UNUSED notes from I2 will be
2731 properly handled. */
2733 if (i3_subst_into_i2)
2735 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2736 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != USE
2737 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
2738 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2739 && ! find_reg_note (i2, REG_UNUSED,
2740 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2741 for (temp = NEXT_INSN (i2);
2742 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
2743 || BB_HEAD (this_basic_block) != temp);
2744 temp = NEXT_INSN (temp))
2745 if (temp != i3 && INSN_P (temp))
2746 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2747 if (XEXP (link, 0) == i2)
2748 XEXP (link, 0) = i3;
2753 while (XEXP (link, 1))
2754 link = XEXP (link, 1);
2755 XEXP (link, 1) = i2notes;
2769 INSN_CODE (i2) = i2_code_number;
2770 PATTERN (i2) = newi2pat;
2774 PUT_CODE (i2, NOTE);
2775 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2776 NOTE_SOURCE_FILE (i2) = 0;
2783 PUT_CODE (i1, NOTE);
2784 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2785 NOTE_SOURCE_FILE (i1) = 0;
2788 /* Get death notes for everything that is now used in either I3 or
2789 I2 and used to die in a previous insn. If we built two new
2790 patterns, move from I1 to I2 then I2 to I3 so that we get the
2791 proper movement on registers that I2 modifies. */
2795 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2796 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2799 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2802 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2804 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX);
2806 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX);
2808 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX);
2810 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2812 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2813 know these are REG_UNUSED and want them to go to the desired insn,
2814 so we always pass it as i3. We have not counted the notes in
2815 reg_n_deaths yet, so we need to do so now. */
2817 if (newi2pat && new_i2_notes)
2819 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2820 if (REG_P (XEXP (temp, 0)))
2821 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2823 distribute_notes (new_i2_notes, i2, i2, NULL_RTX);
2828 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2829 if (REG_P (XEXP (temp, 0)))
2830 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2832 distribute_notes (new_i3_notes, i3, i3, NULL_RTX);
2835 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2836 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2837 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2838 in that case, it might delete I2. Similarly for I2 and I1.
2839 Show an additional death due to the REG_DEAD note we make here. If
2840 we discard it in distribute_notes, we will decrement it again. */
2844 if (REG_P (i3dest_killed))
2845 REG_N_DEATHS (REGNO (i3dest_killed))++;
2847 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
2848 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2850 NULL_RTX, i2, NULL_RTX);
2852 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2854 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2857 if (i2dest_in_i2src)
2860 REG_N_DEATHS (REGNO (i2dest))++;
2862 if (newi2pat && reg_set_p (i2dest, newi2pat))
2863 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2864 NULL_RTX, i2, NULL_RTX);
2866 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2867 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2870 if (i1dest_in_i1src)
2873 REG_N_DEATHS (REGNO (i1dest))++;
2875 if (newi2pat && reg_set_p (i1dest, newi2pat))
2876 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2877 NULL_RTX, i2, NULL_RTX);
2879 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2880 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2883 distribute_links (i3links);
2884 distribute_links (i2links);
2885 distribute_links (i1links);
2890 rtx i2_insn = 0, i2_val = 0, set;
2892 /* The insn that used to set this register doesn't exist, and
2893 this life of the register may not exist either. See if one of
2894 I3's links points to an insn that sets I2DEST. If it does,
2895 that is now the last known value for I2DEST. If we don't update
2896 this and I2 set the register to a value that depended on its old
2897 contents, we will get confused. If this insn is used, thing
2898 will be set correctly in combine_instructions. */
2900 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2901 if ((set = single_set (XEXP (link, 0))) != 0
2902 && rtx_equal_p (i2dest, SET_DEST (set)))
2903 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2905 record_value_for_reg (i2dest, i2_insn, i2_val);
2907 /* If the reg formerly set in I2 died only once and that was in I3,
2908 zero its use count so it won't make `reload' do any work. */
2910 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2911 && ! i2dest_in_i2src)
2913 regno = REGNO (i2dest);
2914 REG_N_SETS (regno)--;
2918 if (i1 && REG_P (i1dest))
2921 rtx i1_insn = 0, i1_val = 0, set;
2923 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2924 if ((set = single_set (XEXP (link, 0))) != 0
2925 && rtx_equal_p (i1dest, SET_DEST (set)))
2926 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2928 record_value_for_reg (i1dest, i1_insn, i1_val);
2930 regno = REGNO (i1dest);
2931 if (! added_sets_1 && ! i1dest_in_i1src)
2932 REG_N_SETS (regno)--;
2935 /* Update reg_stat[].nonzero_bits et al for any changes that may have
2936 been made to this insn. The order of
2937 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
2938 can affect nonzero_bits of newpat */
2940 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
2941 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
2943 /* Set new_direct_jump_p if a new return or simple jump instruction
2946 If I3 is now an unconditional jump, ensure that it has a
2947 BARRIER following it since it may have initially been a
2948 conditional jump. It may also be the last nonnote insn. */
2950 if (returnjump_p (i3) || any_uncondjump_p (i3))
2952 *new_direct_jump_p = 1;
2953 mark_jump_label (PATTERN (i3), i3, 0);
2955 if ((temp = next_nonnote_insn (i3)) == NULL_RTX
2956 || GET_CODE (temp) != BARRIER)
2957 emit_barrier_after (i3);
2960 if (undobuf.other_insn != NULL_RTX
2961 && (returnjump_p (undobuf.other_insn)
2962 || any_uncondjump_p (undobuf.other_insn)))
2964 *new_direct_jump_p = 1;
2966 if ((temp = next_nonnote_insn (undobuf.other_insn)) == NULL_RTX
2967 || GET_CODE (temp) != BARRIER)
2968 emit_barrier_after (undobuf.other_insn);
2971 /* An NOOP jump does not need barrier, but it does need cleaning up
2973 if (GET_CODE (newpat) == SET
2974 && SET_SRC (newpat) == pc_rtx
2975 && SET_DEST (newpat) == pc_rtx)
2976 *new_direct_jump_p = 1;
2979 combine_successes++;
2982 if (added_links_insn
2983 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2984 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2985 return added_links_insn;
2987 return newi2pat ? i2 : i3;
2990 /* Undo all the modifications recorded in undobuf. */
2995 struct undo *undo, *next;
2997 for (undo = undobuf.undos; undo; undo = next)
3001 *undo->where.i = undo->old_contents.i;
3003 *undo->where.r = undo->old_contents.r;
3005 undo->next = undobuf.frees;
3006 undobuf.frees = undo;
3012 /* We've committed to accepting the changes we made. Move all
3013 of the undos to the free list. */
3018 struct undo *undo, *next;
3020 for (undo = undobuf.undos; undo; undo = next)
3023 undo->next = undobuf.frees;
3024 undobuf.frees = undo;
3030 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
3031 where we have an arithmetic expression and return that point. LOC will
3034 try_combine will call this function to see if an insn can be split into
3038 find_split_point (rtx *loc, rtx insn)
3041 enum rtx_code code = GET_CODE (x);
3043 unsigned HOST_WIDE_INT len = 0;
3044 HOST_WIDE_INT pos = 0;
3046 rtx inner = NULL_RTX;
3048 /* First special-case some codes. */
3052 #ifdef INSN_SCHEDULING
3053 /* If we are making a paradoxical SUBREG invalid, it becomes a split
3055 if (GET_CODE (SUBREG_REG (x)) == MEM)
3058 return find_split_point (&SUBREG_REG (x), insn);
3062 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
3063 using LO_SUM and HIGH. */
3064 if (GET_CODE (XEXP (x, 0)) == CONST
3065 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
3068 gen_rtx_LO_SUM (Pmode,
3069 gen_rtx_HIGH (Pmode, XEXP (x, 0)),
3071 return &XEXP (XEXP (x, 0), 0);
3075 /* If we have a PLUS whose second operand is a constant and the
3076 address is not valid, perhaps will can split it up using
3077 the machine-specific way to split large constants. We use
3078 the first pseudo-reg (one of the virtual regs) as a placeholder;
3079 it will not remain in the result. */
3080 if (GET_CODE (XEXP (x, 0)) == PLUS
3081 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3082 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
3084 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
3085 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
3088 /* This should have produced two insns, each of which sets our
3089 placeholder. If the source of the second is a valid address,
3090 we can make put both sources together and make a split point
3094 && NEXT_INSN (seq) != NULL_RTX
3095 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
3096 && GET_CODE (seq) == INSN
3097 && GET_CODE (PATTERN (seq)) == SET
3098 && SET_DEST (PATTERN (seq)) == reg
3099 && ! reg_mentioned_p (reg,
3100 SET_SRC (PATTERN (seq)))
3101 && GET_CODE (NEXT_INSN (seq)) == INSN
3102 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
3103 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
3104 && memory_address_p (GET_MODE (x),
3105 SET_SRC (PATTERN (NEXT_INSN (seq)))))
3107 rtx src1 = SET_SRC (PATTERN (seq));
3108 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
3110 /* Replace the placeholder in SRC2 with SRC1. If we can
3111 find where in SRC2 it was placed, that can become our
3112 split point and we can replace this address with SRC2.
3113 Just try two obvious places. */
3115 src2 = replace_rtx (src2, reg, src1);
3117 if (XEXP (src2, 0) == src1)
3118 split = &XEXP (src2, 0);
3119 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
3120 && XEXP (XEXP (src2, 0), 0) == src1)
3121 split = &XEXP (XEXP (src2, 0), 0);
3125 SUBST (XEXP (x, 0), src2);
3130 /* If that didn't work, perhaps the first operand is complex and
3131 needs to be computed separately, so make a split point there.
3132 This will occur on machines that just support REG + CONST
3133 and have a constant moved through some previous computation. */
3135 else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
3136 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
3137 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
3138 return &XEXP (XEXP (x, 0), 0);
3144 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3145 ZERO_EXTRACT, the most likely reason why this doesn't match is that
3146 we need to put the operand into a register. So split at that
3149 if (SET_DEST (x) == cc0_rtx
3150 && GET_CODE (SET_SRC (x)) != COMPARE
3151 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
3152 && !OBJECT_P (SET_SRC (x))
3153 && ! (GET_CODE (SET_SRC (x)) == SUBREG
3154 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
3155 return &SET_SRC (x);
3158 /* See if we can split SET_SRC as it stands. */
3159 split = find_split_point (&SET_SRC (x), insn);
3160 if (split && split != &SET_SRC (x))
3163 /* See if we can split SET_DEST as it stands. */
3164 split = find_split_point (&SET_DEST (x), insn);
3165 if (split && split != &SET_DEST (x))
3168 /* See if this is a bitfield assignment with everything constant. If
3169 so, this is an IOR of an AND, so split it into that. */
3170 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
3171 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
3172 <= HOST_BITS_PER_WIDE_INT)
3173 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
3174 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
3175 && GET_CODE (SET_SRC (x)) == CONST_INT
3176 && ((INTVAL (XEXP (SET_DEST (x), 1))
3177 + INTVAL (XEXP (SET_DEST (x), 2)))
3178 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
3179 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
3181 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
3182 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
3183 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
3184 rtx dest = XEXP (SET_DEST (x), 0);
3185 enum machine_mode mode = GET_MODE (dest);
3186 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
3188 if (BITS_BIG_ENDIAN)
3189 pos = GET_MODE_BITSIZE (mode) - len - pos;
3193 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
3196 gen_binary (IOR, mode,
3197 gen_binary (AND, mode, dest,
3198 gen_int_mode (~(mask << pos),
3200 GEN_INT (src << pos)));
3202 SUBST (SET_DEST (x), dest);
3204 split = find_split_point (&SET_SRC (x), insn);
3205 if (split && split != &SET_SRC (x))
3209 /* Otherwise, see if this is an operation that we can split into two.
3210 If so, try to split that. */
3211 code = GET_CODE (SET_SRC (x));
3216 /* If we are AND'ing with a large constant that is only a single
3217 bit and the result is only being used in a context where we
3218 need to know if it is zero or nonzero, replace it with a bit
3219 extraction. This will avoid the large constant, which might
3220 have taken more than one insn to make. If the constant were
3221 not a valid argument to the AND but took only one insn to make,
3222 this is no worse, but if it took more than one insn, it will
3225 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3226 && REG_P (XEXP (SET_SRC (x), 0))
3227 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
3228 && REG_P (SET_DEST (x))
3229 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
3230 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
3231 && XEXP (*split, 0) == SET_DEST (x)
3232 && XEXP (*split, 1) == const0_rtx)
3234 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
3235 XEXP (SET_SRC (x), 0),
3236 pos, NULL_RTX, 1, 1, 0, 0);
3237 if (extraction != 0)
3239 SUBST (SET_SRC (x), extraction);
3240 return find_split_point (loc, insn);
3246 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3247 is known to be on, this can be converted into a NEG of a shift. */
3248 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
3249 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
3250 && 1 <= (pos = exact_log2
3251 (nonzero_bits (XEXP (SET_SRC (x), 0),
3252 GET_MODE (XEXP (SET_SRC (x), 0))))))
3254 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
3258 gen_rtx_LSHIFTRT (mode,
3259 XEXP (SET_SRC (x), 0),
3262 split = find_split_point (&SET_SRC (x), insn);
3263 if (split && split != &SET_SRC (x))
3269 inner = XEXP (SET_SRC (x), 0);
3271 /* We can't optimize if either mode is a partial integer
3272 mode as we don't know how many bits are significant
3274 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3275 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3279 len = GET_MODE_BITSIZE (GET_MODE (inner));
3285 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3286 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3288 inner = XEXP (SET_SRC (x), 0);
3289 len = INTVAL (XEXP (SET_SRC (x), 1));
3290 pos = INTVAL (XEXP (SET_SRC (x), 2));
3292 if (BITS_BIG_ENDIAN)
3293 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3294 unsignedp = (code == ZERO_EXTRACT);
3302 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3304 enum machine_mode mode = GET_MODE (SET_SRC (x));
3306 /* For unsigned, we have a choice of a shift followed by an
3307 AND or two shifts. Use two shifts for field sizes where the
3308 constant might be too large. We assume here that we can
3309 always at least get 8-bit constants in an AND insn, which is
3310 true for every current RISC. */
3312 if (unsignedp && len <= 8)
3317 (mode, gen_lowpart (mode, inner),
3319 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3321 split = find_split_point (&SET_SRC (x), insn);
3322 if (split && split != &SET_SRC (x))
3329 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3330 gen_rtx_ASHIFT (mode,
3331 gen_lowpart (mode, inner),
3332 GEN_INT (GET_MODE_BITSIZE (mode)
3334 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3336 split = find_split_point (&SET_SRC (x), insn);
3337 if (split && split != &SET_SRC (x))
3342 /* See if this is a simple operation with a constant as the second
3343 operand. It might be that this constant is out of range and hence
3344 could be used as a split point. */
3345 if (BINARY_P (SET_SRC (x))
3346 && CONSTANT_P (XEXP (SET_SRC (x), 1))
3347 && (OBJECT_P (XEXP (SET_SRC (x), 0))
3348 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3349 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
3350 return &XEXP (SET_SRC (x), 1);
3352 /* Finally, see if this is a simple operation with its first operand
3353 not in a register. The operation might require this operand in a
3354 register, so return it as a split point. We can always do this
3355 because if the first operand were another operation, we would have
3356 already found it as a split point. */
3357 if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
3358 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3359 return &XEXP (SET_SRC (x), 0);
3365 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3366 it is better to write this as (not (ior A B)) so we can split it.
3367 Similarly for IOR. */
3368 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3371 gen_rtx_NOT (GET_MODE (x),
3372 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
3374 XEXP (XEXP (x, 0), 0),
3375 XEXP (XEXP (x, 1), 0))));
3376 return find_split_point (loc, insn);
3379 /* Many RISC machines have a large set of logical insns. If the
3380 second operand is a NOT, put it first so we will try to split the
3381 other operand first. */
3382 if (GET_CODE (XEXP (x, 1)) == NOT)
3384 rtx tem = XEXP (x, 0);
3385 SUBST (XEXP (x, 0), XEXP (x, 1));
3386 SUBST (XEXP (x, 1), tem);
3394 /* Otherwise, select our actions depending on our rtx class. */
3395 switch (GET_RTX_CLASS (code))
3397 case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3399 split = find_split_point (&XEXP (x, 2), insn);
3402 /* ... fall through ... */
3404 case RTX_COMM_ARITH:
3406 case RTX_COMM_COMPARE:
3407 split = find_split_point (&XEXP (x, 1), insn);
3410 /* ... fall through ... */
3412 /* Some machines have (and (shift ...) ...) insns. If X is not
3413 an AND, but XEXP (X, 0) is, use it as our split point. */
3414 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3415 return &XEXP (x, 0);
3417 split = find_split_point (&XEXP (x, 0), insn);
3423 /* Otherwise, we don't have a split point. */
3428 /* Throughout X, replace FROM with TO, and return the result.
3429 The result is TO if X is FROM;
3430 otherwise the result is X, but its contents may have been modified.
3431 If they were modified, a record was made in undobuf so that
3432 undo_all will (among other things) return X to its original state.
3434 If the number of changes necessary is too much to record to undo,
3435 the excess changes are not made, so the result is invalid.
3436 The changes already made can still be undone.
3437 undobuf.num_undo is incremented for such changes, so by testing that
3438 the caller can tell whether the result is valid.
3440 `n_occurrences' is incremented each time FROM is replaced.
3442 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3444 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
3445 by copying if `n_occurrences' is nonzero. */
3448 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
3450 enum rtx_code code = GET_CODE (x);
3451 enum machine_mode op0_mode = VOIDmode;
3456 /* Two expressions are equal if they are identical copies of a shared
3457 RTX or if they are both registers with the same register number
3460 #define COMBINE_RTX_EQUAL_P(X,Y) \
3462 || (REG_P (X) && REG_P (Y) \
3463 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3465 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3468 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3471 /* If X and FROM are the same register but different modes, they will
3472 not have been seen as equal above. However, flow.c will make a
3473 LOG_LINKS entry for that case. If we do nothing, we will try to
3474 rerecognize our original insn and, when it succeeds, we will
3475 delete the feeding insn, which is incorrect.
3477 So force this insn not to match in this (rare) case. */
3478 if (! in_dest && code == REG && REG_P (from)
3479 && REGNO (x) == REGNO (from))
3480 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3482 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3483 of which may contain things that can be combined. */
3484 if (code != MEM && code != LO_SUM && OBJECT_P (x))
3487 /* It is possible to have a subexpression appear twice in the insn.
3488 Suppose that FROM is a register that appears within TO.
3489 Then, after that subexpression has been scanned once by `subst',
3490 the second time it is scanned, TO may be found. If we were
3491 to scan TO here, we would find FROM within it and create a
3492 self-referent rtl structure which is completely wrong. */
3493 if (COMBINE_RTX_EQUAL_P (x, to))
3496 /* Parallel asm_operands need special attention because all of the
3497 inputs are shared across the arms. Furthermore, unsharing the
3498 rtl results in recognition failures. Failure to handle this case
3499 specially can result in circular rtl.
3501 Solve this by doing a normal pass across the first entry of the
3502 parallel, and only processing the SET_DESTs of the subsequent
3505 if (code == PARALLEL
3506 && GET_CODE (XVECEXP (x, 0, 0)) == SET
3507 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3509 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3511 /* If this substitution failed, this whole thing fails. */
3512 if (GET_CODE (new) == CLOBBER
3513 && XEXP (new, 0) == const0_rtx)
3516 SUBST (XVECEXP (x, 0, 0), new);
3518 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3520 rtx dest = SET_DEST (XVECEXP (x, 0, i));
3523 && GET_CODE (dest) != CC0
3524 && GET_CODE (dest) != PC)
3526 new = subst (dest, from, to, 0, unique_copy);
3528 /* If this substitution failed, this whole thing fails. */
3529 if (GET_CODE (new) == CLOBBER
3530 && XEXP (new, 0) == const0_rtx)
3533 SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3539 len = GET_RTX_LENGTH (code);
3540 fmt = GET_RTX_FORMAT (code);
3542 /* We don't need to process a SET_DEST that is a register, CC0,
3543 or PC, so set up to skip this common case. All other cases
3544 where we want to suppress replacing something inside a
3545 SET_SRC are handled via the IN_DEST operand. */
3547 && (REG_P (SET_DEST (x))
3548 || GET_CODE (SET_DEST (x)) == CC0
3549 || GET_CODE (SET_DEST (x)) == PC))
3552 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3555 op0_mode = GET_MODE (XEXP (x, 0));
3557 for (i = 0; i < len; i++)
3562 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3564 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3566 new = (unique_copy && n_occurrences
3567 ? copy_rtx (to) : to);
3572 new = subst (XVECEXP (x, i, j), from, to, 0,
3575 /* If this substitution failed, this whole thing
3577 if (GET_CODE (new) == CLOBBER
3578 && XEXP (new, 0) == const0_rtx)
3582 SUBST (XVECEXP (x, i, j), new);
3585 else if (fmt[i] == 'e')
3587 /* If this is a register being set, ignore it. */
3590 && (code == SUBREG || code == STRICT_LOW_PART
3591 || code == ZERO_EXTRACT)
3596 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3598 /* In general, don't install a subreg involving two
3599 modes not tieable. It can worsen register
3600 allocation, and can even make invalid reload
3601 insns, since the reg inside may need to be copied
3602 from in the outside mode, and that may be invalid
3603 if it is an fp reg copied in integer mode.
3605 We allow two exceptions to this: It is valid if
3606 it is inside another SUBREG and the mode of that
3607 SUBREG and the mode of the inside of TO is
3608 tieable and it is valid if X is a SET that copies
3611 if (GET_CODE (to) == SUBREG
3612 && ! MODES_TIEABLE_P (GET_MODE (to),
3613 GET_MODE (SUBREG_REG (to)))
3614 && ! (code == SUBREG
3615 && MODES_TIEABLE_P (GET_MODE (x),
3616 GET_MODE (SUBREG_REG (to))))
3618 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3621 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3623 #ifdef CANNOT_CHANGE_MODE_CLASS
3626 && REGNO (to) < FIRST_PSEUDO_REGISTER
3627 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
3630 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3633 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3637 /* If we are in a SET_DEST, suppress most cases unless we
3638 have gone inside a MEM, in which case we want to
3639 simplify the address. We assume here that things that
3640 are actually part of the destination have their inner
3641 parts in the first expression. This is true for SUBREG,
3642 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3643 things aside from REG and MEM that should appear in a
3645 new = subst (XEXP (x, i), from, to,
3647 && (code == SUBREG || code == STRICT_LOW_PART
3648 || code == ZERO_EXTRACT))
3650 && i == 0), unique_copy);
3652 /* If we found that we will have to reject this combination,
3653 indicate that by returning the CLOBBER ourselves, rather than
3654 an expression containing it. This will speed things up as
3655 well as prevent accidents where two CLOBBERs are considered
3656 to be equal, thus producing an incorrect simplification. */
3658 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3661 if (GET_CODE (x) == SUBREG
3662 && (GET_CODE (new) == CONST_INT
3663 || GET_CODE (new) == CONST_DOUBLE))
3665 enum machine_mode mode = GET_MODE (x);
3667 x = simplify_subreg (GET_MODE (x), new,
3668 GET_MODE (SUBREG_REG (x)),
3671 x = gen_rtx_CLOBBER (mode, const0_rtx);
3673 else if (GET_CODE (new) == CONST_INT
3674 && GET_CODE (x) == ZERO_EXTEND)
3676 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
3677 new, GET_MODE (XEXP (x, 0)));
3682 SUBST (XEXP (x, i), new);
3687 /* Try to simplify X. If the simplification changed the code, it is likely
3688 that further simplification will help, so loop, but limit the number
3689 of repetitions that will be performed. */
3691 for (i = 0; i < 4; i++)
3693 /* If X is sufficiently simple, don't bother trying to do anything
3695 if (code != CONST_INT && code != REG && code != CLOBBER)
3696 x = combine_simplify_rtx (x, op0_mode, in_dest);
3698 if (GET_CODE (x) == code)
3701 code = GET_CODE (x);
3703 /* We no longer know the original mode of operand 0 since we
3704 have changed the form of X) */
3705 op0_mode = VOIDmode;
3711 /* Simplify X, a piece of RTL. We just operate on the expression at the
3712 outer level; call `subst' to simplify recursively. Return the new
3715 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
3716 if we are inside a SET_DEST. */
3719 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
3721 enum rtx_code code = GET_CODE (x);
3722 enum machine_mode mode = GET_MODE (x);
3727 /* If this is a commutative operation, put a constant last and a complex
3728 expression first. We don't need to do this for comparisons here. */
3729 if (COMMUTATIVE_ARITH_P (x)
3730 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
3733 SUBST (XEXP (x, 0), XEXP (x, 1));
3734 SUBST (XEXP (x, 1), temp);
3737 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3738 sign extension of a PLUS with a constant, reverse the order of the sign
3739 extension and the addition. Note that this not the same as the original
3740 code, but overflow is undefined for signed values. Also note that the
3741 PLUS will have been partially moved "inside" the sign-extension, so that
3742 the first operand of X will really look like:
3743 (ashiftrt (plus (ashift A C4) C5) C4).
3745 (plus (ashiftrt (ashift A C4) C2) C4)
3746 and replace the first operand of X with that expression. Later parts
3747 of this function may simplify the expression further.
3749 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3750 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3751 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3753 We do this to simplify address expressions. */
3755 if ((code == PLUS || code == MINUS || code == MULT)
3756 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3757 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3758 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3759 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3760 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3761 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3762 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3763 && (temp = simplify_binary_operation (ASHIFTRT, mode,
3764 XEXP (XEXP (XEXP (x, 0), 0), 1),
3765 XEXP (XEXP (x, 0), 1))) != 0)
3768 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3769 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3770 INTVAL (XEXP (XEXP (x, 0), 1)));
3772 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3773 INTVAL (XEXP (XEXP (x, 0), 1)));
3775 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3778 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3779 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3780 things. Check for cases where both arms are testing the same
3783 Don't do anything if all operands are very simple. */
3786 && ((!OBJECT_P (XEXP (x, 0))
3787 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3788 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
3789 || (!OBJECT_P (XEXP (x, 1))
3790 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3791 && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
3793 && (!OBJECT_P (XEXP (x, 0))
3794 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3795 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
3797 rtx cond, true_rtx, false_rtx;
3799 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
3801 /* If everything is a comparison, what we have is highly unlikely
3802 to be simpler, so don't use it. */
3803 && ! (COMPARISON_P (x)
3804 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
3806 rtx cop1 = const0_rtx;
3807 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3809 if (cond_code == NE && COMPARISON_P (cond))
3812 /* Simplify the alternative arms; this may collapse the true and
3813 false arms to store-flag values. Be careful to use copy_rtx
3814 here since true_rtx or false_rtx might share RTL with x as a
3815 result of the if_then_else_cond call above. */
3816 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
3817 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
3819 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3820 is unlikely to be simpler. */
3821 if (general_operand (true_rtx, VOIDmode)
3822 && general_operand (false_rtx, VOIDmode))
3824 enum rtx_code reversed;
3826 /* Restarting if we generate a store-flag expression will cause
3827 us to loop. Just drop through in this case. */
3829 /* If the result values are STORE_FLAG_VALUE and zero, we can
3830 just make the comparison operation. */
3831 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
3832 x = gen_binary (cond_code, mode, cond, cop1);
3833 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
3834 && ((reversed = reversed_comparison_code_parts
3835 (cond_code, cond, cop1, NULL))
3837 x = gen_binary (reversed, mode, cond, cop1);
3839 /* Likewise, we can make the negate of a comparison operation
3840 if the result values are - STORE_FLAG_VALUE and zero. */
3841 else if (GET_CODE (true_rtx) == CONST_INT
3842 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
3843 && false_rtx == const0_rtx)
3844 x = simplify_gen_unary (NEG, mode,
3845 gen_binary (cond_code, mode, cond,
3848 else if (GET_CODE (false_rtx) == CONST_INT
3849 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
3850 && true_rtx == const0_rtx
3851 && ((reversed = reversed_comparison_code_parts
3852 (cond_code, cond, cop1, NULL))
3854 x = simplify_gen_unary (NEG, mode,
3855 gen_binary (reversed, mode,
3859 return gen_rtx_IF_THEN_ELSE (mode,
3860 gen_binary (cond_code, VOIDmode,
3862 true_rtx, false_rtx);
3864 code = GET_CODE (x);
3865 op0_mode = VOIDmode;
3870 /* Try to fold this expression in case we have constants that weren't
3873 switch (GET_RTX_CLASS (code))
3876 if (op0_mode == VOIDmode)
3877 op0_mode = GET_MODE (XEXP (x, 0));
3878 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3881 case RTX_COMM_COMPARE:
3883 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
3884 if (cmp_mode == VOIDmode)
3886 cmp_mode = GET_MODE (XEXP (x, 1));
3887 if (cmp_mode == VOIDmode)
3888 cmp_mode = op0_mode;
3890 temp = simplify_relational_operation (code, mode, cmp_mode,
3891 XEXP (x, 0), XEXP (x, 1));
3894 case RTX_COMM_ARITH:
3896 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3898 case RTX_BITFIELD_OPS:
3900 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3901 XEXP (x, 1), XEXP (x, 2));
3910 code = GET_CODE (temp);
3911 op0_mode = VOIDmode;
3912 mode = GET_MODE (temp);
3915 /* First see if we can apply the inverse distributive law. */
3916 if (code == PLUS || code == MINUS
3917 || code == AND || code == IOR || code == XOR)
3919 x = apply_distributive_law (x);
3920 code = GET_CODE (x);
3921 op0_mode = VOIDmode;
3924 /* If CODE is an associative operation not otherwise handled, see if we
3925 can associate some operands. This can win if they are constants or
3926 if they are logically related (i.e. (a & b) & a). */
3927 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
3928 || code == AND || code == IOR || code == XOR
3929 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3930 && ((INTEGRAL_MODE_P (mode) && code != DIV)
3931 || (flag_unsafe_math_optimizations && FLOAT_MODE_P (mode))))
3933 if (GET_CODE (XEXP (x, 0)) == code)
3935 rtx other = XEXP (XEXP (x, 0), 0);
3936 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3937 rtx inner_op1 = XEXP (x, 1);
3940 /* Make sure we pass the constant operand if any as the second
3941 one if this is a commutative operation. */
3942 if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
3944 rtx tem = inner_op0;
3945 inner_op0 = inner_op1;
3948 inner = simplify_binary_operation (code == MINUS ? PLUS
3949 : code == DIV ? MULT
3951 mode, inner_op0, inner_op1);
3953 /* For commutative operations, try the other pair if that one
3955 if (inner == 0 && COMMUTATIVE_ARITH_P (x))
3957 other = XEXP (XEXP (x, 0), 1);
3958 inner = simplify_binary_operation (code, mode,
3959 XEXP (XEXP (x, 0), 0),
3964 return gen_binary (code, mode, other, inner);
3968 /* A little bit of algebraic simplification here. */
3972 /* Ensure that our address has any ASHIFTs converted to MULT in case
3973 address-recognizing predicates are called later. */
3974 temp = make_compound_operation (XEXP (x, 0), MEM);
3975 SUBST (XEXP (x, 0), temp);
3979 if (op0_mode == VOIDmode)
3980 op0_mode = GET_MODE (SUBREG_REG (x));
3982 /* See if this can be moved to simplify_subreg. */
3983 if (CONSTANT_P (SUBREG_REG (x))
3984 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
3985 /* Don't call gen_lowpart if the inner mode
3986 is VOIDmode and we cannot simplify it, as SUBREG without
3987 inner mode is invalid. */
3988 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
3989 || gen_lowpart_common (mode, SUBREG_REG (x))))
3990 return gen_lowpart (mode, SUBREG_REG (x));
3992 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
3996 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
4002 /* Don't change the mode of the MEM if that would change the meaning
4004 if (GET_CODE (SUBREG_REG (x)) == MEM
4005 && (MEM_VOLATILE_P (SUBREG_REG (x))
4006 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
4007 return gen_rtx_CLOBBER (mode, const0_rtx);
4009 /* Note that we cannot do any narrowing for non-constants since
4010 we might have been counting on using the fact that some bits were
4011 zero. We now do this in the SET. */
4016 if (GET_CODE (XEXP (x, 0)) == SUBREG
4017 && subreg_lowpart_p (XEXP (x, 0))
4018 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
4019 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
4020 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
4021 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
4023 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
4025 x = gen_rtx_ROTATE (inner_mode,
4026 simplify_gen_unary (NOT, inner_mode, const1_rtx,
4028 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
4029 return gen_lowpart (mode, x);
4032 /* Apply De Morgan's laws to reduce number of patterns for machines
4033 with negating logical insns (and-not, nand, etc.). If result has
4034 only one NOT, put it first, since that is how the patterns are
4037 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
4039 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
4040 enum machine_mode op_mode;
4042 op_mode = GET_MODE (in1);
4043 in1 = simplify_gen_unary (NOT, op_mode, in1, op_mode);
4045 op_mode = GET_MODE (in2);
4046 if (op_mode == VOIDmode)
4048 in2 = simplify_gen_unary (NOT, op_mode, in2, op_mode);
4050 if (GET_CODE (in2) == NOT && GET_CODE (in1) != NOT)
4053 in2 = in1; in1 = tem;
4056 return gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
4062 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
4063 if (GET_CODE (XEXP (x, 0)) == XOR
4064 && XEXP (XEXP (x, 0), 1) == const1_rtx
4065 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
4066 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
4068 temp = expand_compound_operation (XEXP (x, 0));
4070 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4071 replaced by (lshiftrt X C). This will convert
4072 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4074 if (GET_CODE (temp) == ASHIFTRT
4075 && GET_CODE (XEXP (temp, 1)) == CONST_INT
4076 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4077 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
4078 INTVAL (XEXP (temp, 1)));
4080 /* If X has only a single bit that might be nonzero, say, bit I, convert
4081 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4082 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4083 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4084 or a SUBREG of one since we'd be making the expression more
4085 complex if it was just a register. */
4088 && ! (GET_CODE (temp) == SUBREG
4089 && REG_P (SUBREG_REG (temp)))
4090 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4092 rtx temp1 = simplify_shift_const
4093 (NULL_RTX, ASHIFTRT, mode,
4094 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4095 GET_MODE_BITSIZE (mode) - 1 - i),
4096 GET_MODE_BITSIZE (mode) - 1 - i);
4098 /* If all we did was surround TEMP with the two shifts, we
4099 haven't improved anything, so don't use it. Otherwise,
4100 we are better off with TEMP1. */
4101 if (GET_CODE (temp1) != ASHIFTRT
4102 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4103 || XEXP (XEXP (temp1, 0), 0) != temp)
4109 /* We can't handle truncation to a partial integer mode here
4110 because we don't know the real bitsize of the partial
4112 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4115 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4116 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4117 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4119 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4120 GET_MODE_MASK (mode), NULL_RTX, 0));
4122 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
4123 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4124 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4125 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4126 return XEXP (XEXP (x, 0), 0);
4128 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
4129 (OP:SI foo:SI) if OP is NEG or ABS. */
4130 if ((GET_CODE (XEXP (x, 0)) == ABS
4131 || GET_CODE (XEXP (x, 0)) == NEG)
4132 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
4133 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
4134 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4135 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4136 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4138 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4140 if (GET_CODE (XEXP (x, 0)) == SUBREG
4141 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
4142 && subreg_lowpart_p (XEXP (x, 0)))
4143 return SUBREG_REG (XEXP (x, 0));
4145 /* If we know that the value is already truncated, we can
4146 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4147 is nonzero for the corresponding modes. But don't do this
4148 for an (LSHIFTRT (MULT ...)) since this will cause problems
4149 with the umulXi3_highpart patterns. */
4150 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4151 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
4152 && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4153 >= (unsigned int) (GET_MODE_BITSIZE (mode) + 1)
4154 && ! (GET_CODE (XEXP (x, 0)) == LSHIFTRT
4155 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT))
4156 return gen_lowpart (mode, XEXP (x, 0));
4158 /* A truncate of a comparison can be replaced with a subreg if
4159 STORE_FLAG_VALUE permits. This is like the previous test,
4160 but it works even if the comparison is done in a mode larger
4161 than HOST_BITS_PER_WIDE_INT. */
4162 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4163 && COMPARISON_P (XEXP (x, 0))
4164 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0)
4165 return gen_lowpart (mode, XEXP (x, 0));
4167 /* Similarly, a truncate of a register whose value is a
4168 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4170 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4171 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4172 && (temp = get_last_value (XEXP (x, 0)))
4173 && COMPARISON_P (temp))
4174 return gen_lowpart (mode, XEXP (x, 0));
4178 case FLOAT_TRUNCATE:
4179 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4180 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4181 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4182 return XEXP (XEXP (x, 0), 0);
4184 /* (float_truncate:SF (float_truncate:DF foo:XF))
4185 = (float_truncate:SF foo:XF).
4186 This may eliminate double rounding, so it is unsafe.
4188 (float_truncate:SF (float_extend:XF foo:DF))
4189 = (float_truncate:SF foo:DF).
4191 (float_truncate:DF (float_extend:XF foo:SF))
4192 = (float_extend:SF foo:DF). */
4193 if ((GET_CODE (XEXP (x, 0)) == FLOAT_TRUNCATE
4194 && flag_unsafe_math_optimizations)
4195 || GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND)
4196 return simplify_gen_unary (GET_MODE_SIZE (GET_MODE (XEXP (XEXP (x, 0),
4198 > GET_MODE_SIZE (mode)
4199 ? FLOAT_TRUNCATE : FLOAT_EXTEND,
4201 XEXP (XEXP (x, 0), 0), mode);
4203 /* (float_truncate (float x)) is (float x) */
4204 if (GET_CODE (XEXP (x, 0)) == FLOAT
4205 && (flag_unsafe_math_optimizations
4206 || ((unsigned)significand_size (GET_MODE (XEXP (x, 0)))
4207 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x, 0), 0)))
4208 - num_sign_bit_copies (XEXP (XEXP (x, 0), 0),
4209 GET_MODE (XEXP (XEXP (x, 0), 0)))))))
4210 return simplify_gen_unary (FLOAT, mode,
4211 XEXP (XEXP (x, 0), 0),
4212 GET_MODE (XEXP (XEXP (x, 0), 0)));
4214 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4215 (OP:SF foo:SF) if OP is NEG or ABS. */
4216 if ((GET_CODE (XEXP (x, 0)) == ABS
4217 || GET_CODE (XEXP (x, 0)) == NEG)
4218 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
4219 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4220 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4221 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4223 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4224 is (float_truncate:SF x). */
4225 if (GET_CODE (XEXP (x, 0)) == SUBREG
4226 && subreg_lowpart_p (XEXP (x, 0))
4227 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
4228 return SUBREG_REG (XEXP (x, 0));
4231 /* (float_extend (float_extend x)) is (float_extend x)
4233 (float_extend (float x)) is (float x) assuming that double
4234 rounding can't happen.
4236 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4237 || (GET_CODE (XEXP (x, 0)) == FLOAT
4238 && ((unsigned)significand_size (GET_MODE (XEXP (x, 0)))
4239 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x, 0), 0)))
4240 - num_sign_bit_copies (XEXP (XEXP (x, 0), 0),
4241 GET_MODE (XEXP (XEXP (x, 0), 0)))))))
4242 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4243 XEXP (XEXP (x, 0), 0),
4244 GET_MODE (XEXP (XEXP (x, 0), 0)));
4249 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4250 using cc0, in which case we want to leave it as a COMPARE
4251 so we can distinguish it from a register-register-copy. */
4252 if (XEXP (x, 1) == const0_rtx)
4255 /* x - 0 is the same as x unless x's mode has signed zeros and
4256 allows rounding towards -infinity. Under those conditions,
4258 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0)))
4259 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0))))
4260 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4266 /* (const (const X)) can become (const X). Do it this way rather than
4267 returning the inner CONST since CONST can be shared with a
4269 if (GET_CODE (XEXP (x, 0)) == CONST)
4270 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4275 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4276 can add in an offset. find_split_point will split this address up
4277 again if it doesn't match. */
4278 if (GET_CODE (XEXP (x, 0)) == HIGH
4279 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4285 /* Canonicalize (plus (mult (neg B) C) A) to (minus A (mult B C)).
4287 if (GET_CODE (XEXP (x, 0)) == MULT
4288 && GET_CODE (XEXP (XEXP (x, 0), 0)) == NEG)
4292 in1 = XEXP (XEXP (XEXP (x, 0), 0), 0);
4293 in2 = XEXP (XEXP (x, 0), 1);
4294 return gen_binary (MINUS, mode, XEXP (x, 1),
4295 gen_binary (MULT, mode, in1, in2));
4298 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4299 outermost. That's because that's the way indexed addresses are
4300 supposed to appear. This code used to check many more cases, but
4301 they are now checked elsewhere. */
4302 if (GET_CODE (XEXP (x, 0)) == PLUS
4303 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
4304 return gen_binary (PLUS, mode,
4305 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
4307 XEXP (XEXP (x, 0), 1));
4309 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4310 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4311 bit-field and can be replaced by either a sign_extend or a
4312 sign_extract. The `and' may be a zero_extend and the two
4313 <c>, -<c> constants may be reversed. */
4314 if (GET_CODE (XEXP (x, 0)) == XOR
4315 && GET_CODE (XEXP (x, 1)) == CONST_INT
4316 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4317 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4318 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4319 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4320 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4321 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4322 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4323 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4324 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4325 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4326 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4327 == (unsigned int) i + 1))))
4328 return simplify_shift_const
4329 (NULL_RTX, ASHIFTRT, mode,
4330 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4331 XEXP (XEXP (XEXP (x, 0), 0), 0),
4332 GET_MODE_BITSIZE (mode) - (i + 1)),
4333 GET_MODE_BITSIZE (mode) - (i + 1));
4335 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4336 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4337 is 1. This produces better code than the alternative immediately
4339 if (COMPARISON_P (XEXP (x, 0))
4340 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
4341 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx))
4342 && (reversed = reversed_comparison (XEXP (x, 0), mode,
4343 XEXP (XEXP (x, 0), 0),
4344 XEXP (XEXP (x, 0), 1))))
4346 simplify_gen_unary (NEG, mode, reversed, mode);
4348 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4349 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4350 the bitsize of the mode - 1. This allows simplification of
4351 "a = (b & 8) == 0;" */
4352 if (XEXP (x, 1) == constm1_rtx
4353 && !REG_P (XEXP (x, 0))
4354 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4355 && REG_P (SUBREG_REG (XEXP (x, 0))))
4356 && nonzero_bits (XEXP (x, 0), mode) == 1)
4357 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4358 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4359 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4360 GET_MODE_BITSIZE (mode) - 1),
4361 GET_MODE_BITSIZE (mode) - 1);
4363 /* If we are adding two things that have no bits in common, convert
4364 the addition into an IOR. This will often be further simplified,
4365 for example in cases like ((a & 1) + (a & 2)), which can
4368 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4369 && (nonzero_bits (XEXP (x, 0), mode)
4370 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4372 /* Try to simplify the expression further. */
4373 rtx tor = gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4374 temp = combine_simplify_rtx (tor, mode, in_dest);
4376 /* If we could, great. If not, do not go ahead with the IOR
4377 replacement, since PLUS appears in many special purpose
4378 address arithmetic instructions. */
4379 if (GET_CODE (temp) != CLOBBER && temp != tor)
4385 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4386 by reversing the comparison code if valid. */
4387 if (STORE_FLAG_VALUE == 1
4388 && XEXP (x, 0) == const1_rtx
4389 && COMPARISON_P (XEXP (x, 1))
4390 && (reversed = reversed_comparison (XEXP (x, 1), mode,
4391 XEXP (XEXP (x, 1), 0),
4392 XEXP (XEXP (x, 1), 1))))
4395 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4396 (and <foo> (const_int pow2-1)) */
4397 if (GET_CODE (XEXP (x, 1)) == AND
4398 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4399 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4400 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4401 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4402 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4404 /* Canonicalize (minus A (mult (neg B) C)) to (plus (mult B C) A).
4406 if (GET_CODE (XEXP (x, 1)) == MULT
4407 && GET_CODE (XEXP (XEXP (x, 1), 0)) == NEG)
4411 in1 = XEXP (XEXP (XEXP (x, 1), 0), 0);
4412 in2 = XEXP (XEXP (x, 1), 1);
4413 return gen_binary (PLUS, mode, gen_binary (MULT, mode, in1, in2),
4417 /* Canonicalize (minus (neg A) (mult B C)) to
4418 (minus (mult (neg B) C) A). */
4419 if (GET_CODE (XEXP (x, 1)) == MULT
4420 && GET_CODE (XEXP (x, 0)) == NEG)
4424 in1 = simplify_gen_unary (NEG, mode, XEXP (XEXP (x, 1), 0), mode);
4425 in2 = XEXP (XEXP (x, 1), 1);
4426 return gen_binary (MINUS, mode, gen_binary (MULT, mode, in1, in2),
4427 XEXP (XEXP (x, 0), 0));
4430 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4432 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
4433 return gen_binary (MINUS, mode,
4434 gen_binary (MINUS, mode, XEXP (x, 0),
4435 XEXP (XEXP (x, 1), 0)),
4436 XEXP (XEXP (x, 1), 1));
4440 /* If we have (mult (plus A B) C), apply the distributive law and then
4441 the inverse distributive law to see if things simplify. This
4442 occurs mostly in addresses, often when unrolling loops. */
4444 if (GET_CODE (XEXP (x, 0)) == PLUS)
4446 x = apply_distributive_law
4447 (gen_binary (PLUS, mode,
4448 gen_binary (MULT, mode,
4449 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4450 gen_binary (MULT, mode,
4451 XEXP (XEXP (x, 0), 1),
4452 copy_rtx (XEXP (x, 1)))));
4454 if (GET_CODE (x) != MULT)
4457 /* Try simplify a*(b/c) as (a*b)/c. */
4458 if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations
4459 && GET_CODE (XEXP (x, 0)) == DIV)
4461 rtx tem = simplify_binary_operation (MULT, mode,
4462 XEXP (XEXP (x, 0), 0),
4465 return gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
4470 /* If this is a divide by a power of two, treat it as a shift if
4471 its first operand is a shift. */
4472 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4473 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4474 && (GET_CODE (XEXP (x, 0)) == ASHIFT
4475 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4476 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4477 || GET_CODE (XEXP (x, 0)) == ROTATE
4478 || GET_CODE (XEXP (x, 0)) == ROTATERT))
4479 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4483 case GT: case GTU: case GE: case GEU:
4484 case LT: case LTU: case LE: case LEU:
4485 case UNEQ: case LTGT:
4486 case UNGT: case UNGE:
4487 case UNLT: case UNLE:
4488 case UNORDERED: case ORDERED:
4489 /* If the first operand is a condition code, we can't do anything
4491 if (GET_CODE (XEXP (x, 0)) == COMPARE
4492 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4493 && ! CC0_P (XEXP (x, 0))))
4495 rtx op0 = XEXP (x, 0);
4496 rtx op1 = XEXP (x, 1);
4497 enum rtx_code new_code;
4499 if (GET_CODE (op0) == COMPARE)
4500 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4502 /* Simplify our comparison, if possible. */
4503 new_code = simplify_comparison (code, &op0, &op1);
4505 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4506 if only the low-order bit is possibly nonzero in X (such as when
4507 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4508 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4509 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4512 Remove any ZERO_EXTRACT we made when thinking this was a
4513 comparison. It may now be simpler to use, e.g., an AND. If a
4514 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4515 the call to make_compound_operation in the SET case. */
4517 if (STORE_FLAG_VALUE == 1
4518 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4519 && op1 == const0_rtx
4520 && mode == GET_MODE (op0)
4521 && nonzero_bits (op0, mode) == 1)
4522 return gen_lowpart (mode,
4523 expand_compound_operation (op0));
4525 else if (STORE_FLAG_VALUE == 1
4526 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4527 && op1 == const0_rtx
4528 && mode == GET_MODE (op0)
4529 && (num_sign_bit_copies (op0, mode)
4530 == GET_MODE_BITSIZE (mode)))
4532 op0 = expand_compound_operation (op0);
4533 return simplify_gen_unary (NEG, mode,
4534 gen_lowpart (mode, op0),
4538 else if (STORE_FLAG_VALUE == 1
4539 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4540 && op1 == const0_rtx
4541 && mode == GET_MODE (op0)
4542 && nonzero_bits (op0, mode) == 1)
4544 op0 = expand_compound_operation (op0);
4545 return gen_binary (XOR, mode,
4546 gen_lowpart (mode, op0),
4550 else if (STORE_FLAG_VALUE == 1
4551 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4552 && op1 == const0_rtx
4553 && mode == GET_MODE (op0)
4554 && (num_sign_bit_copies (op0, mode)
4555 == GET_MODE_BITSIZE (mode)))
4557 op0 = expand_compound_operation (op0);
4558 return plus_constant (gen_lowpart (mode, op0), 1);
4561 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4563 if (STORE_FLAG_VALUE == -1
4564 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4565 && op1 == const0_rtx
4566 && (num_sign_bit_copies (op0, mode)
4567 == GET_MODE_BITSIZE (mode)))
4568 return gen_lowpart (mode,
4569 expand_compound_operation (op0));
4571 else if (STORE_FLAG_VALUE == -1
4572 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4573 && op1 == const0_rtx
4574 && mode == GET_MODE (op0)
4575 && nonzero_bits (op0, mode) == 1)
4577 op0 = expand_compound_operation (op0);
4578 return simplify_gen_unary (NEG, mode,
4579 gen_lowpart (mode, op0),
4583 else if (STORE_FLAG_VALUE == -1
4584 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4585 && op1 == const0_rtx
4586 && mode == GET_MODE (op0)
4587 && (num_sign_bit_copies (op0, mode)
4588 == GET_MODE_BITSIZE (mode)))
4590 op0 = expand_compound_operation (op0);
4591 return simplify_gen_unary (NOT, mode,
4592 gen_lowpart (mode, op0),
4596 /* If X is 0/1, (eq X 0) is X-1. */
4597 else if (STORE_FLAG_VALUE == -1
4598 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4599 && op1 == const0_rtx
4600 && mode == GET_MODE (op0)
4601 && nonzero_bits (op0, mode) == 1)
4603 op0 = expand_compound_operation (op0);
4604 return plus_constant (gen_lowpart (mode, op0), -1);
4607 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4608 one bit that might be nonzero, we can convert (ne x 0) to
4609 (ashift x c) where C puts the bit in the sign bit. Remove any
4610 AND with STORE_FLAG_VALUE when we are done, since we are only
4611 going to test the sign bit. */
4612 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4613 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4614 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4615 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4616 && op1 == const0_rtx
4617 && mode == GET_MODE (op0)
4618 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4620 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4621 expand_compound_operation (op0),
4622 GET_MODE_BITSIZE (mode) - 1 - i);
4623 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4629 /* If the code changed, return a whole new comparison. */
4630 if (new_code != code)
4631 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
4633 /* Otherwise, keep this operation, but maybe change its operands.
4634 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4635 SUBST (XEXP (x, 0), op0);
4636 SUBST (XEXP (x, 1), op1);
4641 return simplify_if_then_else (x);
4647 /* If we are processing SET_DEST, we are done. */
4651 return expand_compound_operation (x);
4654 return simplify_set (x);
4659 return simplify_logical (x);
4662 /* (abs (neg <foo>)) -> (abs <foo>) */
4663 if (GET_CODE (XEXP (x, 0)) == NEG)
4664 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4666 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4668 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
4671 /* If operand is something known to be positive, ignore the ABS. */
4672 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4673 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4674 <= HOST_BITS_PER_WIDE_INT)
4675 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4676 & ((HOST_WIDE_INT) 1
4677 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4681 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4682 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4683 return gen_rtx_NEG (mode, XEXP (x, 0));
4688 /* (ffs (*_extend <X>)) = (ffs <X>) */
4689 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4690 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4691 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4696 /* (pop* (zero_extend <X>)) = (pop* <X>) */
4697 if (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4698 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4702 /* (float (sign_extend <X>)) = (float <X>). */
4703 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4704 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4712 /* If this is a shift by a constant amount, simplify it. */
4713 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4714 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4715 INTVAL (XEXP (x, 1)));
4717 else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
4719 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
4721 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4728 rtx op0 = XEXP (x, 0);
4729 rtx op1 = XEXP (x, 1);
4732 if (GET_CODE (op1) != PARALLEL)
4734 len = XVECLEN (op1, 0);
4736 && GET_CODE (XVECEXP (op1, 0, 0)) == CONST_INT
4737 && GET_CODE (op0) == VEC_CONCAT)
4739 int offset = INTVAL (XVECEXP (op1, 0, 0)) * GET_MODE_SIZE (GET_MODE (x));
4741 /* Try to find the element in the VEC_CONCAT. */
4744 if (GET_MODE (op0) == GET_MODE (x))
4746 if (GET_CODE (op0) == VEC_CONCAT)
4748 HOST_WIDE_INT op0_size = GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)));
4749 if (op0_size < offset)
4750 op0 = XEXP (op0, 0);
4754 op0 = XEXP (op0, 1);
4772 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4775 simplify_if_then_else (rtx x)
4777 enum machine_mode mode = GET_MODE (x);
4778 rtx cond = XEXP (x, 0);
4779 rtx true_rtx = XEXP (x, 1);
4780 rtx false_rtx = XEXP (x, 2);
4781 enum rtx_code true_code = GET_CODE (cond);
4782 int comparison_p = COMPARISON_P (cond);
4785 enum rtx_code false_code;
4788 /* Simplify storing of the truth value. */
4789 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
4790 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
4792 /* Also when the truth value has to be reversed. */
4794 && true_rtx == const0_rtx && false_rtx == const_true_rtx
4795 && (reversed = reversed_comparison (cond, mode, XEXP (cond, 0),
4799 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4800 in it is being compared against certain values. Get the true and false
4801 comparisons and see if that says anything about the value of each arm. */
4804 && ((false_code = combine_reversed_comparison_code (cond))
4806 && REG_P (XEXP (cond, 0)))
4809 rtx from = XEXP (cond, 0);
4810 rtx true_val = XEXP (cond, 1);
4811 rtx false_val = true_val;
4814 /* If FALSE_CODE is EQ, swap the codes and arms. */
4816 if (false_code == EQ)
4818 swapped = 1, true_code = EQ, false_code = NE;
4819 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4822 /* If we are comparing against zero and the expression being tested has
4823 only a single bit that might be nonzero, that is its value when it is
4824 not equal to zero. Similarly if it is known to be -1 or 0. */
4826 if (true_code == EQ && true_val == const0_rtx
4827 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4828 false_code = EQ, false_val = GEN_INT (nzb);
4829 else if (true_code == EQ && true_val == const0_rtx
4830 && (num_sign_bit_copies (from, GET_MODE (from))
4831 == GET_MODE_BITSIZE (GET_MODE (from))))
4832 false_code = EQ, false_val = constm1_rtx;
4834 /* Now simplify an arm if we know the value of the register in the
4835 branch and it is used in the arm. Be careful due to the potential
4836 of locally-shared RTL. */
4838 if (reg_mentioned_p (from, true_rtx))
4839 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
4841 pc_rtx, pc_rtx, 0, 0);
4842 if (reg_mentioned_p (from, false_rtx))
4843 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
4845 pc_rtx, pc_rtx, 0, 0);
4847 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
4848 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
4850 true_rtx = XEXP (x, 1);
4851 false_rtx = XEXP (x, 2);
4852 true_code = GET_CODE (cond);
4855 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4856 reversed, do so to avoid needing two sets of patterns for
4857 subtract-and-branch insns. Similarly if we have a constant in the true
4858 arm, the false arm is the same as the first operand of the comparison, or
4859 the false arm is more complicated than the true arm. */
4862 && combine_reversed_comparison_code (cond) != UNKNOWN
4863 && (true_rtx == pc_rtx
4864 || (CONSTANT_P (true_rtx)
4865 && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
4866 || true_rtx == const0_rtx
4867 || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
4868 || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
4869 && !OBJECT_P (false_rtx))
4870 || reg_mentioned_p (true_rtx, false_rtx)
4871 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
4873 true_code = reversed_comparison_code (cond, NULL);
4875 reversed_comparison (cond, GET_MODE (cond), XEXP (cond, 0),
4878 SUBST (XEXP (x, 1), false_rtx);
4879 SUBST (XEXP (x, 2), true_rtx);
4881 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4884 /* It is possible that the conditional has been simplified out. */
4885 true_code = GET_CODE (cond);
4886 comparison_p = COMPARISON_P (cond);
4889 /* If the two arms are identical, we don't need the comparison. */
4891 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
4894 /* Convert a == b ? b : a to "a". */
4895 if (true_code == EQ && ! side_effects_p (cond)
4896 && !HONOR_NANS (mode)
4897 && rtx_equal_p (XEXP (cond, 0), false_rtx)
4898 && rtx_equal_p (XEXP (cond, 1), true_rtx))
4900 else if (true_code == NE && ! side_effects_p (cond)
4901 && !HONOR_NANS (mode)
4902 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4903 && rtx_equal_p (XEXP (cond, 1), false_rtx))
4906 /* Look for cases where we have (abs x) or (neg (abs X)). */
4908 if (GET_MODE_CLASS (mode) == MODE_INT
4909 && GET_CODE (false_rtx) == NEG
4910 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
4912 && rtx_equal_p (true_rtx, XEXP (cond, 0))
4913 && ! side_effects_p (true_rtx))
4918 return simplify_gen_unary (ABS, mode, true_rtx, mode);
4922 simplify_gen_unary (NEG, mode,
4923 simplify_gen_unary (ABS, mode, true_rtx, mode),
4929 /* Look for MIN or MAX. */
4931 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4933 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4934 && rtx_equal_p (XEXP (cond, 1), false_rtx)
4935 && ! side_effects_p (cond))
4940 return gen_binary (SMAX, mode, true_rtx, false_rtx);
4943 return gen_binary (SMIN, mode, true_rtx, false_rtx);
4946 return gen_binary (UMAX, mode, true_rtx, false_rtx);
4949 return gen_binary (UMIN, mode, true_rtx, false_rtx);
4954 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4955 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4956 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4957 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4958 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4959 neither 1 or -1, but it isn't worth checking for. */
4961 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4963 && GET_MODE_CLASS (mode) == MODE_INT
4964 && ! side_effects_p (x))
4966 rtx t = make_compound_operation (true_rtx, SET);
4967 rtx f = make_compound_operation (false_rtx, SET);
4968 rtx cond_op0 = XEXP (cond, 0);
4969 rtx cond_op1 = XEXP (cond, 1);
4970 enum rtx_code op = NIL, extend_op = NIL;
4971 enum machine_mode m = mode;
4972 rtx z = 0, c1 = NULL_RTX;
4974 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4975 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4976 || GET_CODE (t) == ASHIFT
4977 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4978 && rtx_equal_p (XEXP (t, 0), f))
4979 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4981 /* If an identity-zero op is commutative, check whether there
4982 would be a match if we swapped the operands. */
4983 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4984 || GET_CODE (t) == XOR)
4985 && rtx_equal_p (XEXP (t, 1), f))
4986 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4987 else if (GET_CODE (t) == SIGN_EXTEND
4988 && (GET_CODE (XEXP (t, 0)) == PLUS
4989 || GET_CODE (XEXP (t, 0)) == MINUS
4990 || GET_CODE (XEXP (t, 0)) == IOR
4991 || GET_CODE (XEXP (t, 0)) == XOR
4992 || GET_CODE (XEXP (t, 0)) == ASHIFT
4993 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4994 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4995 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4996 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4997 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4998 && (num_sign_bit_copies (f, GET_MODE (f))
5000 (GET_MODE_BITSIZE (mode)
5001 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
5003 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5004 extend_op = SIGN_EXTEND;
5005 m = GET_MODE (XEXP (t, 0));
5007 else if (GET_CODE (t) == SIGN_EXTEND
5008 && (GET_CODE (XEXP (t, 0)) == PLUS
5009 || GET_CODE (XEXP (t, 0)) == IOR
5010 || GET_CODE (XEXP (t, 0)) == XOR)
5011 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5012 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5013 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5014 && (num_sign_bit_copies (f, GET_MODE (f))
5016 (GET_MODE_BITSIZE (mode)
5017 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
5019 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5020 extend_op = SIGN_EXTEND;
5021 m = GET_MODE (XEXP (t, 0));
5023 else if (GET_CODE (t) == ZERO_EXTEND
5024 && (GET_CODE (XEXP (t, 0)) == PLUS
5025 || GET_CODE (XEXP (t, 0)) == MINUS
5026 || GET_CODE (XEXP (t, 0)) == IOR
5027 || GET_CODE (XEXP (t, 0)) == XOR
5028 || GET_CODE (XEXP (t, 0)) == ASHIFT
5029 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5030 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5031 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5032 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5033 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5034 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5035 && ((nonzero_bits (f, GET_MODE (f))
5036 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
5039 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5040 extend_op = ZERO_EXTEND;
5041 m = GET_MODE (XEXP (t, 0));
5043 else if (GET_CODE (t) == ZERO_EXTEND
5044 && (GET_CODE (XEXP (t, 0)) == PLUS
5045 || GET_CODE (XEXP (t, 0)) == IOR
5046 || GET_CODE (XEXP (t, 0)) == XOR)
5047 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5048 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5049 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5050 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5051 && ((nonzero_bits (f, GET_MODE (f))
5052 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
5055 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5056 extend_op = ZERO_EXTEND;
5057 m = GET_MODE (XEXP (t, 0));
5062 temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
5063 pc_rtx, pc_rtx, 0, 0);
5064 temp = gen_binary (MULT, m, temp,
5065 gen_binary (MULT, m, c1, const_true_rtx));
5066 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
5067 temp = gen_binary (op, m, gen_lowpart (m, z), temp);
5069 if (extend_op != NIL)
5070 temp = simplify_gen_unary (extend_op, mode, temp, m);
5076 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5077 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5078 negation of a single bit, we can convert this operation to a shift. We
5079 can actually do this more generally, but it doesn't seem worth it. */
5081 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5082 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5083 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
5084 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
5085 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
5086 == GET_MODE_BITSIZE (mode))
5087 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
5089 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5090 gen_lowpart (mode, XEXP (cond, 0)), i);
5092 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
5093 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5094 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5095 && GET_MODE (XEXP (cond, 0)) == mode
5096 && (INTVAL (true_rtx) & GET_MODE_MASK (mode))
5097 == nonzero_bits (XEXP (cond, 0), mode)
5098 && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
5099 return XEXP (cond, 0);
5104 /* Simplify X, a SET expression. Return the new expression. */
5107 simplify_set (rtx x)
5109 rtx src = SET_SRC (x);
5110 rtx dest = SET_DEST (x);
5111 enum machine_mode mode
5112 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
5116 /* (set (pc) (return)) gets written as (return). */
5117 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
5120 /* Now that we know for sure which bits of SRC we are using, see if we can
5121 simplify the expression for the object knowing that we only need the
5124 if (GET_MODE_CLASS (mode) == MODE_INT
5125 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5127 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, NULL_RTX, 0);
5128 SUBST (SET_SRC (x), src);
5131 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5132 the comparison result and try to simplify it unless we already have used
5133 undobuf.other_insn. */
5134 if ((GET_MODE_CLASS (mode) == MODE_CC
5135 || GET_CODE (src) == COMPARE
5137 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5138 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5139 && COMPARISON_P (*cc_use)
5140 && rtx_equal_p (XEXP (*cc_use, 0), dest))
5142 enum rtx_code old_code = GET_CODE (*cc_use);
5143 enum rtx_code new_code;
5145 int other_changed = 0;
5146 enum machine_mode compare_mode = GET_MODE (dest);
5148 if (GET_CODE (src) == COMPARE)
5149 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5151 op0 = src, op1 = const0_rtx;
5153 tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
5156 new_code = old_code;
5157 else if (!CONSTANT_P (tmp))
5159 new_code = GET_CODE (tmp);
5160 op0 = XEXP (tmp, 0);
5161 op1 = XEXP (tmp, 1);
5165 rtx pat = PATTERN (other_insn);
5166 undobuf.other_insn = other_insn;
5167 SUBST (*cc_use, tmp);
5169 /* Attempt to simplify CC user. */
5170 if (GET_CODE (pat) == SET)
5172 rtx new = simplify_rtx (SET_SRC (pat));
5173 if (new != NULL_RTX)
5174 SUBST (SET_SRC (pat), new);
5177 /* Convert X into a no-op move. */
5178 SUBST (SET_DEST (x), pc_rtx);
5179 SUBST (SET_SRC (x), pc_rtx);
5183 /* Simplify our comparison, if possible. */
5184 new_code = simplify_comparison (new_code, &op0, &op1);
5186 #ifdef SELECT_CC_MODE
5187 /* If this machine has CC modes other than CCmode, check to see if we
5188 need to use a different CC mode here. */
5189 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
5190 compare_mode = GET_MODE (op0);
5192 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5195 /* If the mode changed, we have to change SET_DEST, the mode in the
5196 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5197 a hard register, just build new versions with the proper mode. If it
5198 is a pseudo, we lose unless it is only time we set the pseudo, in
5199 which case we can safely change its mode. */
5200 if (compare_mode != GET_MODE (dest))
5202 unsigned int regno = REGNO (dest);
5203 rtx new_dest = gen_rtx_REG (compare_mode, regno);
5205 if (regno < FIRST_PSEUDO_REGISTER
5206 || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
5208 if (regno >= FIRST_PSEUDO_REGISTER)
5209 SUBST (regno_reg_rtx[regno], new_dest);
5211 SUBST (SET_DEST (x), new_dest);
5212 SUBST (XEXP (*cc_use, 0), new_dest);
5219 #endif /* SELECT_CC_MODE */
5221 /* If the code changed, we have to build a new comparison in
5222 undobuf.other_insn. */
5223 if (new_code != old_code)
5225 int other_changed_previously = other_changed;
5226 unsigned HOST_WIDE_INT mask;
5228 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5232 /* If the only change we made was to change an EQ into an NE or
5233 vice versa, OP0 has only one bit that might be nonzero, and OP1
5234 is zero, check if changing the user of the condition code will
5235 produce a valid insn. If it won't, we can keep the original code
5236 in that insn by surrounding our operation with an XOR. */
5238 if (((old_code == NE && new_code == EQ)
5239 || (old_code == EQ && new_code == NE))
5240 && ! other_changed_previously && op1 == const0_rtx
5241 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5242 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5244 rtx pat = PATTERN (other_insn), note = 0;
5246 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
5247 && ! check_asm_operands (pat)))
5249 PUT_CODE (*cc_use, old_code);
5252 op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
5258 undobuf.other_insn = other_insn;
5261 /* If we are now comparing against zero, change our source if
5262 needed. If we do not use cc0, we always have a COMPARE. */
5263 if (op1 == const0_rtx && dest == cc0_rtx)
5265 SUBST (SET_SRC (x), op0);
5271 /* Otherwise, if we didn't previously have a COMPARE in the
5272 correct mode, we need one. */
5273 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5275 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5280 /* Otherwise, update the COMPARE if needed. */
5281 SUBST (XEXP (src, 0), op0);
5282 SUBST (XEXP (src, 1), op1);
5287 /* Get SET_SRC in a form where we have placed back any
5288 compound expressions. Then do the checks below. */
5289 src = make_compound_operation (src, SET);
5290 SUBST (SET_SRC (x), src);
5293 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5294 and X being a REG or (subreg (reg)), we may be able to convert this to
5295 (set (subreg:m2 x) (op)).
5297 We can always do this if M1 is narrower than M2 because that means that
5298 we only care about the low bits of the result.
5300 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5301 perform a narrower operation than requested since the high-order bits will
5302 be undefined. On machine where it is defined, this transformation is safe
5303 as long as M1 and M2 have the same number of words. */
5305 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5306 && !OBJECT_P (SUBREG_REG (src))
5307 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5309 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5310 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5311 #ifndef WORD_REGISTER_OPERATIONS
5312 && (GET_MODE_SIZE (GET_MODE (src))
5313 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5315 #ifdef CANNOT_CHANGE_MODE_CLASS
5316 && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
5317 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
5318 GET_MODE (SUBREG_REG (src)),
5322 || (GET_CODE (dest) == SUBREG
5323 && REG_P (SUBREG_REG (dest)))))
5325 SUBST (SET_DEST (x),
5326 gen_lowpart (GET_MODE (SUBREG_REG (src)),
5328 SUBST (SET_SRC (x), SUBREG_REG (src));
5330 src = SET_SRC (x), dest = SET_DEST (x);
5334 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5337 && GET_CODE (src) == SUBREG
5338 && subreg_lowpart_p (src)
5339 && (GET_MODE_BITSIZE (GET_MODE (src))
5340 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
5342 rtx inner = SUBREG_REG (src);
5343 enum machine_mode inner_mode = GET_MODE (inner);
5345 /* Here we make sure that we don't have a sign bit on. */
5346 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
5347 && (nonzero_bits (inner, inner_mode)
5348 < ((unsigned HOST_WIDE_INT) 1
5349 << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
5351 SUBST (SET_SRC (x), inner);
5357 #ifdef LOAD_EXTEND_OP
5358 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5359 would require a paradoxical subreg. Replace the subreg with a
5360 zero_extend to avoid the reload that would otherwise be required. */
5362 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5363 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
5364 && SUBREG_BYTE (src) == 0
5365 && (GET_MODE_SIZE (GET_MODE (src))
5366 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5367 && GET_CODE (SUBREG_REG (src)) == MEM)
5370 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5371 GET_MODE (src), SUBREG_REG (src)));
5377 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5378 are comparing an item known to be 0 or -1 against 0, use a logical
5379 operation instead. Check for one of the arms being an IOR of the other
5380 arm with some value. We compute three terms to be IOR'ed together. In
5381 practice, at most two will be nonzero. Then we do the IOR's. */
5383 if (GET_CODE (dest) != PC
5384 && GET_CODE (src) == IF_THEN_ELSE
5385 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5386 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5387 && XEXP (XEXP (src, 0), 1) == const0_rtx
5388 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5389 #ifdef HAVE_conditional_move
5390 && ! can_conditionally_move_p (GET_MODE (src))
5392 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5393 GET_MODE (XEXP (XEXP (src, 0), 0)))
5394 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5395 && ! side_effects_p (src))
5397 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5398 ? XEXP (src, 1) : XEXP (src, 2));
5399 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5400 ? XEXP (src, 2) : XEXP (src, 1));
5401 rtx term1 = const0_rtx, term2, term3;
5403 if (GET_CODE (true_rtx) == IOR
5404 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5405 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
5406 else if (GET_CODE (true_rtx) == IOR
5407 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5408 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
5409 else if (GET_CODE (false_rtx) == IOR
5410 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5411 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
5412 else if (GET_CODE (false_rtx) == IOR
5413 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5414 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
5416 term2 = gen_binary (AND, GET_MODE (src),
5417 XEXP (XEXP (src, 0), 0), true_rtx);
5418 term3 = gen_binary (AND, GET_MODE (src),
5419 simplify_gen_unary (NOT, GET_MODE (src),
5420 XEXP (XEXP (src, 0), 0),
5425 gen_binary (IOR, GET_MODE (src),
5426 gen_binary (IOR, GET_MODE (src), term1, term2),
5432 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5433 whole thing fail. */
5434 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5436 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5439 /* Convert this into a field assignment operation, if possible. */
5440 return make_field_assignment (x);
5443 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5447 simplify_logical (rtx x)
5449 enum machine_mode mode = GET_MODE (x);
5450 rtx op0 = XEXP (x, 0);
5451 rtx op1 = XEXP (x, 1);
5454 switch (GET_CODE (x))
5457 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5458 insn (and may simplify more). */
5459 if (GET_CODE (op0) == XOR
5460 && rtx_equal_p (XEXP (op0, 0), op1)
5461 && ! side_effects_p (op1))
5462 x = gen_binary (AND, mode,
5463 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
5466 if (GET_CODE (op0) == XOR
5467 && rtx_equal_p (XEXP (op0, 1), op1)
5468 && ! side_effects_p (op1))
5469 x = gen_binary (AND, mode,
5470 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
5473 /* Similarly for (~(A ^ B)) & A. */
5474 if (GET_CODE (op0) == NOT
5475 && GET_CODE (XEXP (op0, 0)) == XOR
5476 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
5477 && ! side_effects_p (op1))
5478 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
5480 if (GET_CODE (op0) == NOT
5481 && GET_CODE (XEXP (op0, 0)) == XOR
5482 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
5483 && ! side_effects_p (op1))
5484 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
5486 /* We can call simplify_and_const_int only if we don't lose
5487 any (sign) bits when converting INTVAL (op1) to
5488 "unsigned HOST_WIDE_INT". */
5489 if (GET_CODE (op1) == CONST_INT
5490 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5491 || INTVAL (op1) > 0))
5493 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5495 /* If we have (ior (and (X C1) C2)) and the next restart would be
5496 the last, simplify this by making C1 as small as possible
5497 and then exit. Only do this if C1 actually changes: for now
5498 this only saves memory but, should this transformation be
5499 moved to simplify-rtx.c, we'd risk unbounded recursion there. */
5500 if (GET_CODE (x) == IOR && GET_CODE (op0) == AND
5501 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5502 && GET_CODE (op1) == CONST_INT
5503 && (INTVAL (XEXP (op0, 1)) & INTVAL (op1)) != 0)
5504 return gen_binary (IOR, mode,
5505 gen_binary (AND, mode, XEXP (op0, 0),
5506 GEN_INT (INTVAL (XEXP (op0, 1))
5507 & ~INTVAL (op1))), op1);
5509 if (GET_CODE (x) != AND)
5516 /* Convert (A | B) & A to A. */
5517 if (GET_CODE (op0) == IOR
5518 && (rtx_equal_p (XEXP (op0, 0), op1)
5519 || rtx_equal_p (XEXP (op0, 1), op1))
5520 && ! side_effects_p (XEXP (op0, 0))
5521 && ! side_effects_p (XEXP (op0, 1)))
5524 /* In the following group of tests (and those in case IOR below),
5525 we start with some combination of logical operations and apply
5526 the distributive law followed by the inverse distributive law.
5527 Most of the time, this results in no change. However, if some of
5528 the operands are the same or inverses of each other, simplifications
5531 For example, (and (ior A B) (not B)) can occur as the result of
5532 expanding a bit field assignment. When we apply the distributive
5533 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5534 which then simplifies to (and (A (not B))).
5536 If we have (and (ior A B) C), apply the distributive law and then
5537 the inverse distributive law to see if things simplify. */
5539 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5541 x = apply_distributive_law
5542 (gen_binary (GET_CODE (op0), mode,
5543 gen_binary (AND, mode, XEXP (op0, 0), op1),
5544 gen_binary (AND, mode, XEXP (op0, 1),
5546 if (GET_CODE (x) != AND)
5550 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5551 return apply_distributive_law
5552 (gen_binary (GET_CODE (op1), mode,
5553 gen_binary (AND, mode, XEXP (op1, 0), op0),
5554 gen_binary (AND, mode, XEXP (op1, 1),
5557 /* Similarly, taking advantage of the fact that
5558 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5560 if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
5561 return apply_distributive_law
5562 (gen_binary (XOR, mode,
5563 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
5564 gen_binary (IOR, mode, copy_rtx (XEXP (op0, 0)),
5567 else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
5568 return apply_distributive_law
5569 (gen_binary (XOR, mode,
5570 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
5571 gen_binary (IOR, mode, copy_rtx (XEXP (op1, 0)), XEXP (op0, 1))));
5575 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5576 if (GET_CODE (op1) == CONST_INT
5577 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5578 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
5581 /* Convert (A & B) | A to A. */
5582 if (GET_CODE (op0) == AND
5583 && (rtx_equal_p (XEXP (op0, 0), op1)
5584 || rtx_equal_p (XEXP (op0, 1), op1))
5585 && ! side_effects_p (XEXP (op0, 0))
5586 && ! side_effects_p (XEXP (op0, 1)))
5589 /* If we have (ior (and A B) C), apply the distributive law and then
5590 the inverse distributive law to see if things simplify. */
5592 if (GET_CODE (op0) == AND)
5594 x = apply_distributive_law
5595 (gen_binary (AND, mode,
5596 gen_binary (IOR, mode, XEXP (op0, 0), op1),
5597 gen_binary (IOR, mode, XEXP (op0, 1),
5600 if (GET_CODE (x) != IOR)
5604 if (GET_CODE (op1) == AND)
5606 x = apply_distributive_law
5607 (gen_binary (AND, mode,
5608 gen_binary (IOR, mode, XEXP (op1, 0), op0),
5609 gen_binary (IOR, mode, XEXP (op1, 1),
5612 if (GET_CODE (x) != IOR)
5616 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5617 mode size to (rotate A CX). */
5619 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
5620 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
5621 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
5622 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5623 && GET_CODE (XEXP (op1, 1)) == CONST_INT
5624 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
5625 == GET_MODE_BITSIZE (mode)))
5626 return gen_rtx_ROTATE (mode, XEXP (op0, 0),
5627 (GET_CODE (op0) == ASHIFT
5628 ? XEXP (op0, 1) : XEXP (op1, 1)));
5630 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5631 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5632 does not affect any of the bits in OP1, it can really be done
5633 as a PLUS and we can associate. We do this by seeing if OP1
5634 can be safely shifted left C bits. */
5635 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
5636 && GET_CODE (XEXP (op0, 0)) == PLUS
5637 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
5638 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5639 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
5641 int count = INTVAL (XEXP (op0, 1));
5642 HOST_WIDE_INT mask = INTVAL (op1) << count;
5644 if (mask >> count == INTVAL (op1)
5645 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
5647 SUBST (XEXP (XEXP (op0, 0), 1),
5648 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
5655 /* If we are XORing two things that have no bits in common,
5656 convert them into an IOR. This helps to detect rotation encoded
5657 using those methods and possibly other simplifications. */
5659 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5660 && (nonzero_bits (op0, mode)
5661 & nonzero_bits (op1, mode)) == 0)
5662 return (gen_binary (IOR, mode, op0, op1));
5664 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5665 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5668 int num_negated = 0;
5670 if (GET_CODE (op0) == NOT)
5671 num_negated++, op0 = XEXP (op0, 0);
5672 if (GET_CODE (op1) == NOT)
5673 num_negated++, op1 = XEXP (op1, 0);
5675 if (num_negated == 2)
5677 SUBST (XEXP (x, 0), op0);
5678 SUBST (XEXP (x, 1), op1);
5680 else if (num_negated == 1)
5682 simplify_gen_unary (NOT, mode, gen_binary (XOR, mode, op0, op1),
5686 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5687 correspond to a machine insn or result in further simplifications
5688 if B is a constant. */
5690 if (GET_CODE (op0) == AND
5691 && rtx_equal_p (XEXP (op0, 1), op1)
5692 && ! side_effects_p (op1))
5693 return gen_binary (AND, mode,
5694 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
5697 else if (GET_CODE (op0) == AND
5698 && rtx_equal_p (XEXP (op0, 0), op1)
5699 && ! side_effects_p (op1))
5700 return gen_binary (AND, mode,
5701 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
5704 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5705 comparison if STORE_FLAG_VALUE is 1. */
5706 if (STORE_FLAG_VALUE == 1
5707 && op1 == const1_rtx
5708 && COMPARISON_P (op0)
5709 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5713 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5714 is (lt foo (const_int 0)), so we can perform the above
5715 simplification if STORE_FLAG_VALUE is 1. */
5717 if (STORE_FLAG_VALUE == 1
5718 && op1 == const1_rtx
5719 && GET_CODE (op0) == LSHIFTRT
5720 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5721 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
5722 return gen_rtx_GE (mode, XEXP (op0, 0), const0_rtx);
5724 /* (xor (comparison foo bar) (const_int sign-bit))
5725 when STORE_FLAG_VALUE is the sign bit. */
5726 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5727 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5728 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5729 && op1 == const_true_rtx
5730 && COMPARISON_P (op0)
5731 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5744 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5745 operations" because they can be replaced with two more basic operations.
5746 ZERO_EXTEND is also considered "compound" because it can be replaced with
5747 an AND operation, which is simpler, though only one operation.
5749 The function expand_compound_operation is called with an rtx expression
5750 and will convert it to the appropriate shifts and AND operations,
5751 simplifying at each stage.
5753 The function make_compound_operation is called to convert an expression
5754 consisting of shifts and ANDs into the equivalent compound expression.
5755 It is the inverse of this function, loosely speaking. */
5758 expand_compound_operation (rtx x)
5760 unsigned HOST_WIDE_INT pos = 0, len;
5762 unsigned int modewidth;
5765 switch (GET_CODE (x))
5770 /* We can't necessarily use a const_int for a multiword mode;
5771 it depends on implicitly extending the value.
5772 Since we don't know the right way to extend it,
5773 we can't tell whether the implicit way is right.
5775 Even for a mode that is no wider than a const_int,
5776 we can't win, because we need to sign extend one of its bits through
5777 the rest of it, and we don't know which bit. */
5778 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5781 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5782 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5783 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5784 reloaded. If not for that, MEM's would very rarely be safe.
5786 Reject MODEs bigger than a word, because we might not be able
5787 to reference a two-register group starting with an arbitrary register
5788 (and currently gen_lowpart might crash for a SUBREG). */
5790 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5793 /* Reject MODEs that aren't scalar integers because turning vector
5794 or complex modes into shifts causes problems. */
5796 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5799 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5800 /* If the inner object has VOIDmode (the only way this can happen
5801 is if it is an ASM_OPERANDS), we can't do anything since we don't
5802 know how much masking to do. */
5811 /* If the operand is a CLOBBER, just return it. */
5812 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5815 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5816 || GET_CODE (XEXP (x, 2)) != CONST_INT
5817 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5820 /* Reject MODEs that aren't scalar integers because turning vector
5821 or complex modes into shifts causes problems. */
5823 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5826 len = INTVAL (XEXP (x, 1));
5827 pos = INTVAL (XEXP (x, 2));
5829 /* If this goes outside the object being extracted, replace the object
5830 with a (use (mem ...)) construct that only combine understands
5831 and is used only for this purpose. */
5832 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5833 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
5835 if (BITS_BIG_ENDIAN)
5836 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5843 /* Convert sign extension to zero extension, if we know that the high
5844 bit is not set, as this is easier to optimize. It will be converted
5845 back to cheaper alternative in make_extraction. */
5846 if (GET_CODE (x) == SIGN_EXTEND
5847 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5848 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5849 & ~(((unsigned HOST_WIDE_INT)
5850 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5854 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5855 rtx temp2 = expand_compound_operation (temp);
5857 /* Make sure this is a profitable operation. */
5858 if (rtx_cost (x, SET) > rtx_cost (temp2, SET))
5860 else if (rtx_cost (x, SET) > rtx_cost (temp, SET))
5866 /* We can optimize some special cases of ZERO_EXTEND. */
5867 if (GET_CODE (x) == ZERO_EXTEND)
5869 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5870 know that the last value didn't have any inappropriate bits
5872 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5873 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5874 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5875 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5876 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5877 return XEXP (XEXP (x, 0), 0);
5879 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5880 if (GET_CODE (XEXP (x, 0)) == SUBREG
5881 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5882 && subreg_lowpart_p (XEXP (x, 0))
5883 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5884 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5885 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5886 return SUBREG_REG (XEXP (x, 0));
5888 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5889 is a comparison and STORE_FLAG_VALUE permits. This is like
5890 the first case, but it works even when GET_MODE (x) is larger
5891 than HOST_WIDE_INT. */
5892 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5893 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5894 && COMPARISON_P (XEXP (XEXP (x, 0), 0))
5895 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5896 <= HOST_BITS_PER_WIDE_INT)
5897 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5898 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5899 return XEXP (XEXP (x, 0), 0);
5901 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5902 if (GET_CODE (XEXP (x, 0)) == SUBREG
5903 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5904 && subreg_lowpart_p (XEXP (x, 0))
5905 && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
5906 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5907 <= HOST_BITS_PER_WIDE_INT)
5908 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5909 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5910 return SUBREG_REG (XEXP (x, 0));
5914 /* If we reach here, we want to return a pair of shifts. The inner
5915 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5916 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5917 logical depending on the value of UNSIGNEDP.
5919 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5920 converted into an AND of a shift.
5922 We must check for the case where the left shift would have a negative
5923 count. This can happen in a case like (x >> 31) & 255 on machines
5924 that can't shift by a constant. On those machines, we would first
5925 combine the shift with the AND to produce a variable-position
5926 extraction. Then the constant of 31 would be substituted in to produce
5927 a such a position. */
5929 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5930 if (modewidth + len >= pos)
5931 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5933 simplify_shift_const (NULL_RTX, ASHIFT,
5936 modewidth - pos - len),
5939 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5940 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5941 simplify_shift_const (NULL_RTX, LSHIFTRT,
5944 ((HOST_WIDE_INT) 1 << len) - 1);
5946 /* Any other cases we can't handle. */
5949 /* If we couldn't do this for some reason, return the original
5951 if (GET_CODE (tem) == CLOBBER)
5957 /* X is a SET which contains an assignment of one object into
5958 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5959 or certain SUBREGS). If possible, convert it into a series of
5962 We half-heartedly support variable positions, but do not at all
5963 support variable lengths. */
5966 expand_field_assignment (rtx x)
5969 rtx pos; /* Always counts from low bit. */
5972 enum machine_mode compute_mode;
5974 /* Loop until we find something we can't simplify. */
5977 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5978 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5980 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5981 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5982 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
5984 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5985 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5987 inner = XEXP (SET_DEST (x), 0);
5988 len = INTVAL (XEXP (SET_DEST (x), 1));
5989 pos = XEXP (SET_DEST (x), 2);
5991 /* If the position is constant and spans the width of INNER,
5992 surround INNER with a USE to indicate this. */
5993 if (GET_CODE (pos) == CONST_INT
5994 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5995 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
5997 if (BITS_BIG_ENDIAN)
5999 if (GET_CODE (pos) == CONST_INT)
6000 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
6002 else if (GET_CODE (pos) == MINUS
6003 && GET_CODE (XEXP (pos, 1)) == CONST_INT
6004 && (INTVAL (XEXP (pos, 1))
6005 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
6006 /* If position is ADJUST - X, new position is X. */
6007 pos = XEXP (pos, 0);
6009 pos = gen_binary (MINUS, GET_MODE (pos),
6010 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
6016 /* A SUBREG between two modes that occupy the same numbers of words
6017 can be done by moving the SUBREG to the source. */
6018 else if (GET_CODE (SET_DEST (x)) == SUBREG
6019 /* We need SUBREGs to compute nonzero_bits properly. */
6020 && nonzero_sign_valid
6021 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
6022 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
6023 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
6024 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
6026 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
6028 (GET_MODE (SUBREG_REG (SET_DEST (x))),
6035 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6036 inner = SUBREG_REG (inner);
6038 compute_mode = GET_MODE (inner);
6040 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6041 if (! SCALAR_INT_MODE_P (compute_mode))
6043 enum machine_mode imode;
6045 /* Don't do anything for vector or complex integral types. */
6046 if (! FLOAT_MODE_P (compute_mode))
6049 /* Try to find an integral mode to pun with. */
6050 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
6051 if (imode == BLKmode)
6054 compute_mode = imode;
6055 inner = gen_lowpart (imode, inner);
6058 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6059 if (len < HOST_BITS_PER_WIDE_INT)
6060 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
6064 /* Now compute the equivalent expression. Make a copy of INNER
6065 for the SET_DEST in case it is a MEM into which we will substitute;
6066 we don't want shared RTL in that case. */
6068 (VOIDmode, copy_rtx (inner),
6069 gen_binary (IOR, compute_mode,
6070 gen_binary (AND, compute_mode,
6071 simplify_gen_unary (NOT, compute_mode,
6077 gen_binary (ASHIFT, compute_mode,
6078 gen_binary (AND, compute_mode,
6080 (compute_mode, SET_SRC (x)),
6088 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6089 it is an RTX that represents a variable starting position; otherwise,
6090 POS is the (constant) starting bit position (counted from the LSB).
6092 INNER may be a USE. This will occur when we started with a bitfield
6093 that went outside the boundary of the object in memory, which is
6094 allowed on most machines. To isolate this case, we produce a USE
6095 whose mode is wide enough and surround the MEM with it. The only
6096 code that understands the USE is this routine. If it is not removed,
6097 it will cause the resulting insn not to match.
6099 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6102 IN_DEST is nonzero if this is a reference in the destination of a
6103 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6104 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6107 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6108 ZERO_EXTRACT should be built even for bits starting at bit 0.
6110 MODE is the desired mode of the result (if IN_DEST == 0).
6112 The result is an RTX for the extraction or NULL_RTX if the target
6116 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
6117 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
6118 int in_dest, int in_compare)
6120 /* This mode describes the size of the storage area
6121 to fetch the overall value from. Within that, we
6122 ignore the POS lowest bits, etc. */
6123 enum machine_mode is_mode = GET_MODE (inner);
6124 enum machine_mode inner_mode;
6125 enum machine_mode wanted_inner_mode = byte_mode;
6126 enum machine_mode wanted_inner_reg_mode = word_mode;
6127 enum machine_mode pos_mode = word_mode;
6128 enum machine_mode extraction_mode = word_mode;
6129 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
6132 rtx orig_pos_rtx = pos_rtx;
6133 HOST_WIDE_INT orig_pos;
6135 /* Get some information about INNER and get the innermost object. */
6136 if (GET_CODE (inner) == USE)
6137 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
6138 /* We don't need to adjust the position because we set up the USE
6139 to pretend that it was a full-word object. */
6140 spans_byte = 1, inner = XEXP (inner, 0);
6141 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6143 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6144 consider just the QI as the memory to extract from.
6145 The subreg adds or removes high bits; its mode is
6146 irrelevant to the meaning of this extraction,
6147 since POS and LEN count from the lsb. */
6148 if (GET_CODE (SUBREG_REG (inner)) == MEM)
6149 is_mode = GET_MODE (SUBREG_REG (inner));
6150 inner = SUBREG_REG (inner);
6152 else if (GET_CODE (inner) == ASHIFT
6153 && GET_CODE (XEXP (inner, 1)) == CONST_INT
6154 && pos_rtx == 0 && pos == 0
6155 && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
6157 /* We're extracting the least significant bits of an rtx
6158 (ashift X (const_int C)), where LEN > C. Extract the
6159 least significant (LEN - C) bits of X, giving an rtx
6160 whose mode is MODE, then shift it left C times. */
6161 new = make_extraction (mode, XEXP (inner, 0),
6162 0, 0, len - INTVAL (XEXP (inner, 1)),
6163 unsignedp, in_dest, in_compare);
6165 return gen_rtx_ASHIFT (mode, new, XEXP (inner, 1));
6168 inner_mode = GET_MODE (inner);
6170 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
6171 pos = INTVAL (pos_rtx), pos_rtx = 0;
6173 /* See if this can be done without an extraction. We never can if the
6174 width of the field is not the same as that of some integer mode. For
6175 registers, we can only avoid the extraction if the position is at the
6176 low-order bit and this is either not in the destination or we have the
6177 appropriate STRICT_LOW_PART operation available.
6179 For MEM, we can avoid an extract if the field starts on an appropriate
6180 boundary and we can change the mode of the memory reference. However,
6181 we cannot directly access the MEM if we have a USE and the underlying
6182 MEM is not TMODE. This combination means that MEM was being used in a
6183 context where bits outside its mode were being referenced; that is only
6184 valid in bit-field insns. */
6186 if (tmode != BLKmode
6187 && ! (spans_byte && inner_mode != tmode)
6188 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
6189 && GET_CODE (inner) != MEM
6192 && have_insn_for (STRICT_LOW_PART, tmode))))
6193 || (GET_CODE (inner) == MEM && pos_rtx == 0
6195 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
6196 : BITS_PER_UNIT)) == 0
6197 /* We can't do this if we are widening INNER_MODE (it
6198 may not be aligned, for one thing). */
6199 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
6200 && (inner_mode == tmode
6201 || (! mode_dependent_address_p (XEXP (inner, 0))
6202 && ! MEM_VOLATILE_P (inner))))))
6204 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6205 field. If the original and current mode are the same, we need not
6206 adjust the offset. Otherwise, we do if bytes big endian.
6208 If INNER is not a MEM, get a piece consisting of just the field
6209 of interest (in this case POS % BITS_PER_WORD must be 0). */
6211 if (GET_CODE (inner) == MEM)
6213 HOST_WIDE_INT offset;
6215 /* POS counts from lsb, but make OFFSET count in memory order. */
6216 if (BYTES_BIG_ENDIAN)
6217 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6219 offset = pos / BITS_PER_UNIT;
6221 new = adjust_address_nv (inner, tmode, offset);
6223 else if (REG_P (inner))
6225 if (tmode != inner_mode)
6227 /* We can't call gen_lowpart in a DEST since we
6228 always want a SUBREG (see below) and it would sometimes
6229 return a new hard register. */
6232 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6234 if (WORDS_BIG_ENDIAN
6235 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6236 final_word = ((GET_MODE_SIZE (inner_mode)
6237 - GET_MODE_SIZE (tmode))
6238 / UNITS_PER_WORD) - final_word;
6240 final_word *= UNITS_PER_WORD;
6241 if (BYTES_BIG_ENDIAN &&
6242 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6243 final_word += (GET_MODE_SIZE (inner_mode)
6244 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6246 /* Avoid creating invalid subregs, for example when
6247 simplifying (x>>32)&255. */
6248 if (final_word >= GET_MODE_SIZE (inner_mode))
6251 new = gen_rtx_SUBREG (tmode, inner, final_word);
6254 new = gen_lowpart (tmode, inner);
6260 new = force_to_mode (inner, tmode,
6261 len >= HOST_BITS_PER_WIDE_INT
6262 ? ~(unsigned HOST_WIDE_INT) 0
6263 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6266 /* If this extraction is going into the destination of a SET,
6267 make a STRICT_LOW_PART unless we made a MEM. */
6270 return (GET_CODE (new) == MEM ? new
6271 : (GET_CODE (new) != SUBREG
6272 ? gen_rtx_CLOBBER (tmode, const0_rtx)
6273 : gen_rtx_STRICT_LOW_PART (VOIDmode, new)));
6278 if (GET_CODE (new) == CONST_INT)
6279 return gen_int_mode (INTVAL (new), mode);
6281 /* If we know that no extraneous bits are set, and that the high
6282 bit is not set, convert the extraction to the cheaper of
6283 sign and zero extension, that are equivalent in these cases. */
6284 if (flag_expensive_optimizations
6285 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6286 && ((nonzero_bits (new, tmode)
6287 & ~(((unsigned HOST_WIDE_INT)
6288 GET_MODE_MASK (tmode))
6292 rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
6293 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
6295 /* Prefer ZERO_EXTENSION, since it gives more information to
6297 if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
6302 /* Otherwise, sign- or zero-extend unless we already are in the
6305 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6309 /* Unless this is a COMPARE or we have a funny memory reference,
6310 don't do anything with zero-extending field extracts starting at
6311 the low-order bit since they are simple AND operations. */
6312 if (pos_rtx == 0 && pos == 0 && ! in_dest
6313 && ! in_compare && ! spans_byte && unsignedp)
6316 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6317 we would be spanning bytes or if the position is not a constant and the
6318 length is not 1. In all other cases, we would only be going outside
6319 our object in cases when an original shift would have been
6321 if (! spans_byte && GET_CODE (inner) == MEM
6322 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6323 || (pos_rtx != 0 && len != 1)))
6326 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6327 and the mode for the result. */
6328 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6330 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6331 pos_mode = mode_for_extraction (EP_insv, 2);
6332 extraction_mode = mode_for_extraction (EP_insv, 3);
6335 if (! in_dest && unsignedp
6336 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6338 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6339 pos_mode = mode_for_extraction (EP_extzv, 3);
6340 extraction_mode = mode_for_extraction (EP_extzv, 0);
6343 if (! in_dest && ! unsignedp
6344 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6346 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6347 pos_mode = mode_for_extraction (EP_extv, 3);
6348 extraction_mode = mode_for_extraction (EP_extv, 0);
6351 /* Never narrow an object, since that might not be safe. */
6353 if (mode != VOIDmode
6354 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6355 extraction_mode = mode;
6357 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6358 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6359 pos_mode = GET_MODE (pos_rtx);
6361 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6362 if we have to change the mode of memory and cannot, the desired mode is
6364 if (GET_CODE (inner) != MEM)
6365 wanted_inner_mode = wanted_inner_reg_mode;
6366 else if (inner_mode != wanted_inner_mode
6367 && (mode_dependent_address_p (XEXP (inner, 0))
6368 || MEM_VOLATILE_P (inner)))
6369 wanted_inner_mode = extraction_mode;
6373 if (BITS_BIG_ENDIAN)
6375 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6376 BITS_BIG_ENDIAN style. If position is constant, compute new
6377 position. Otherwise, build subtraction.
6378 Note that POS is relative to the mode of the original argument.
6379 If it's a MEM we need to recompute POS relative to that.
6380 However, if we're extracting from (or inserting into) a register,
6381 we want to recompute POS relative to wanted_inner_mode. */
6382 int width = (GET_CODE (inner) == MEM
6383 ? GET_MODE_BITSIZE (is_mode)
6384 : GET_MODE_BITSIZE (wanted_inner_mode));
6387 pos = width - len - pos;
6390 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6391 /* POS may be less than 0 now, but we check for that below.
6392 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6395 /* If INNER has a wider mode, make it smaller. If this is a constant
6396 extract, try to adjust the byte to point to the byte containing
6398 if (wanted_inner_mode != VOIDmode
6399 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6400 && ((GET_CODE (inner) == MEM
6401 && (inner_mode == wanted_inner_mode
6402 || (! mode_dependent_address_p (XEXP (inner, 0))
6403 && ! MEM_VOLATILE_P (inner))))))
6407 /* The computations below will be correct if the machine is big
6408 endian in both bits and bytes or little endian in bits and bytes.
6409 If it is mixed, we must adjust. */
6411 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6412 adjust OFFSET to compensate. */
6413 if (BYTES_BIG_ENDIAN
6415 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6416 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6418 /* If this is a constant position, we can move to the desired byte. */
6421 offset += pos / BITS_PER_UNIT;
6422 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6425 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6427 && is_mode != wanted_inner_mode)
6428 offset = (GET_MODE_SIZE (is_mode)
6429 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6431 if (offset != 0 || inner_mode != wanted_inner_mode)
6432 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6435 /* If INNER is not memory, we can always get it into the proper mode. If we
6436 are changing its mode, POS must be a constant and smaller than the size
6438 else if (GET_CODE (inner) != MEM)
6440 if (GET_MODE (inner) != wanted_inner_mode
6442 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6445 inner = force_to_mode (inner, wanted_inner_mode,
6447 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6448 ? ~(unsigned HOST_WIDE_INT) 0
6449 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6454 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6455 have to zero extend. Otherwise, we can just use a SUBREG. */
6457 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6459 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6461 /* If we know that no extraneous bits are set, and that the high
6462 bit is not set, convert extraction to cheaper one - either
6463 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6465 if (flag_expensive_optimizations
6466 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6467 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6468 & ~(((unsigned HOST_WIDE_INT)
6469 GET_MODE_MASK (GET_MODE (pos_rtx)))
6473 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6475 /* Prefer ZERO_EXTENSION, since it gives more information to
6477 if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6482 else if (pos_rtx != 0
6483 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6484 pos_rtx = gen_lowpart (pos_mode, pos_rtx);
6486 /* Make POS_RTX unless we already have it and it is correct. If we don't
6487 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6489 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6490 pos_rtx = orig_pos_rtx;
6492 else if (pos_rtx == 0)
6493 pos_rtx = GEN_INT (pos);
6495 /* Make the required operation. See if we can use existing rtx. */
6496 new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6497 extraction_mode, inner, GEN_INT (len), pos_rtx);
6499 new = gen_lowpart (mode, new);
6504 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6505 with any other operations in X. Return X without that shift if so. */
6508 extract_left_shift (rtx x, int count)
6510 enum rtx_code code = GET_CODE (x);
6511 enum machine_mode mode = GET_MODE (x);
6517 /* This is the shift itself. If it is wide enough, we will return
6518 either the value being shifted if the shift count is equal to
6519 COUNT or a shift for the difference. */
6520 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6521 && INTVAL (XEXP (x, 1)) >= count)
6522 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6523 INTVAL (XEXP (x, 1)) - count);
6527 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6528 return simplify_gen_unary (code, mode, tem, mode);
6532 case PLUS: case IOR: case XOR: case AND:
6533 /* If we can safely shift this constant and we find the inner shift,
6534 make a new operation. */
6535 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6536 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6537 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6538 return gen_binary (code, mode, tem,
6539 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6550 /* Look at the expression rooted at X. Look for expressions
6551 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6552 Form these expressions.
6554 Return the new rtx, usually just X.
6556 Also, for machines like the VAX that don't have logical shift insns,
6557 try to convert logical to arithmetic shift operations in cases where
6558 they are equivalent. This undoes the canonicalizations to logical
6559 shifts done elsewhere.
6561 We try, as much as possible, to re-use rtl expressions to save memory.
6563 IN_CODE says what kind of expression we are processing. Normally, it is
6564 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6565 being kludges), it is MEM. When processing the arguments of a comparison
6566 or a COMPARE against zero, it is COMPARE. */
6569 make_compound_operation (rtx x, enum rtx_code in_code)
6571 enum rtx_code code = GET_CODE (x);
6572 enum machine_mode mode = GET_MODE (x);
6573 int mode_width = GET_MODE_BITSIZE (mode);
6575 enum rtx_code next_code;
6581 /* Select the code to be used in recursive calls. Once we are inside an
6582 address, we stay there. If we have a comparison, set to COMPARE,
6583 but once inside, go back to our default of SET. */
6585 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6586 : ((code == COMPARE || COMPARISON_P (x))
6587 && XEXP (x, 1) == const0_rtx) ? COMPARE
6588 : in_code == COMPARE ? SET : in_code);
6590 /* Process depending on the code of this operation. If NEW is set
6591 nonzero, it will be returned. */
6596 /* Convert shifts by constants into multiplications if inside
6598 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6599 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6600 && INTVAL (XEXP (x, 1)) >= 0)
6602 new = make_compound_operation (XEXP (x, 0), next_code);
6603 new = gen_rtx_MULT (mode, new,
6604 GEN_INT ((HOST_WIDE_INT) 1
6605 << INTVAL (XEXP (x, 1))));
6610 /* If the second operand is not a constant, we can't do anything
6612 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6615 /* If the constant is a power of two minus one and the first operand
6616 is a logical right shift, make an extraction. */
6617 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6618 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6620 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6621 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6622 0, in_code == COMPARE);
6625 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6626 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6627 && subreg_lowpart_p (XEXP (x, 0))
6628 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6629 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6631 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6633 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6634 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6635 0, in_code == COMPARE);
6637 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6638 else if ((GET_CODE (XEXP (x, 0)) == XOR
6639 || GET_CODE (XEXP (x, 0)) == IOR)
6640 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6641 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6642 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6644 /* Apply the distributive law, and then try to make extractions. */
6645 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6646 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6648 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6650 new = make_compound_operation (new, in_code);
6653 /* If we are have (and (rotate X C) M) and C is larger than the number
6654 of bits in M, this is an extraction. */
6656 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6657 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6658 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6659 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6661 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6662 new = make_extraction (mode, new,
6663 (GET_MODE_BITSIZE (mode)
6664 - INTVAL (XEXP (XEXP (x, 0), 1))),
6665 NULL_RTX, i, 1, 0, in_code == COMPARE);
6668 /* On machines without logical shifts, if the operand of the AND is
6669 a logical shift and our mask turns off all the propagated sign
6670 bits, we can replace the logical shift with an arithmetic shift. */
6671 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6672 && !have_insn_for (LSHIFTRT, mode)
6673 && have_insn_for (ASHIFTRT, mode)
6674 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6675 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6676 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6677 && mode_width <= HOST_BITS_PER_WIDE_INT)
6679 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6681 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6682 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6684 gen_rtx_ASHIFTRT (mode,
6685 make_compound_operation
6686 (XEXP (XEXP (x, 0), 0), next_code),
6687 XEXP (XEXP (x, 0), 1)));
6690 /* If the constant is one less than a power of two, this might be
6691 representable by an extraction even if no shift is present.
6692 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6693 we are in a COMPARE. */
6694 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6695 new = make_extraction (mode,
6696 make_compound_operation (XEXP (x, 0),
6698 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6700 /* If we are in a comparison and this is an AND with a power of two,
6701 convert this into the appropriate bit extract. */
6702 else if (in_code == COMPARE
6703 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6704 new = make_extraction (mode,
6705 make_compound_operation (XEXP (x, 0),
6707 i, NULL_RTX, 1, 1, 0, 1);
6712 /* If the sign bit is known to be zero, replace this with an
6713 arithmetic shift. */
6714 if (have_insn_for (ASHIFTRT, mode)
6715 && ! have_insn_for (LSHIFTRT, mode)
6716 && mode_width <= HOST_BITS_PER_WIDE_INT
6717 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6719 new = gen_rtx_ASHIFTRT (mode,
6720 make_compound_operation (XEXP (x, 0),
6726 /* ... fall through ... */
6732 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6733 this is a SIGN_EXTRACT. */
6734 if (GET_CODE (rhs) == CONST_INT
6735 && GET_CODE (lhs) == ASHIFT
6736 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6737 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6739 new = make_compound_operation (XEXP (lhs, 0), next_code);
6740 new = make_extraction (mode, new,
6741 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6742 NULL_RTX, mode_width - INTVAL (rhs),
6743 code == LSHIFTRT, 0, in_code == COMPARE);
6747 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6748 If so, try to merge the shifts into a SIGN_EXTEND. We could
6749 also do this for some cases of SIGN_EXTRACT, but it doesn't
6750 seem worth the effort; the case checked for occurs on Alpha. */
6753 && ! (GET_CODE (lhs) == SUBREG
6754 && (OBJECT_P (SUBREG_REG (lhs))))
6755 && GET_CODE (rhs) == CONST_INT
6756 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6757 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6758 new = make_extraction (mode, make_compound_operation (new, next_code),
6759 0, NULL_RTX, mode_width - INTVAL (rhs),
6760 code == LSHIFTRT, 0, in_code == COMPARE);
6765 /* Call ourselves recursively on the inner expression. If we are
6766 narrowing the object and it has a different RTL code from
6767 what it originally did, do this SUBREG as a force_to_mode. */
6769 tem = make_compound_operation (SUBREG_REG (x), in_code);
6770 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6771 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6772 && subreg_lowpart_p (x))
6774 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
6777 /* If we have something other than a SUBREG, we might have
6778 done an expansion, so rerun ourselves. */
6779 if (GET_CODE (newer) != SUBREG)
6780 newer = make_compound_operation (newer, in_code);
6785 /* If this is a paradoxical subreg, and the new code is a sign or
6786 zero extension, omit the subreg and widen the extension. If it
6787 is a regular subreg, we can still get rid of the subreg by not
6788 widening so much, or in fact removing the extension entirely. */
6789 if ((GET_CODE (tem) == SIGN_EXTEND
6790 || GET_CODE (tem) == ZERO_EXTEND)
6791 && subreg_lowpart_p (x))
6793 if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (tem))
6794 || (GET_MODE_SIZE (mode) >
6795 GET_MODE_SIZE (GET_MODE (XEXP (tem, 0)))))
6797 if (! SCALAR_INT_MODE_P (mode))
6799 tem = gen_rtx_fmt_e (GET_CODE (tem), mode, XEXP (tem, 0));
6802 tem = gen_lowpart (mode, XEXP (tem, 0));
6813 x = gen_lowpart (mode, new);
6814 code = GET_CODE (x);
6817 /* Now recursively process each operand of this operation. */
6818 fmt = GET_RTX_FORMAT (code);
6819 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6822 new = make_compound_operation (XEXP (x, i), next_code);
6823 SUBST (XEXP (x, i), new);
6829 /* Given M see if it is a value that would select a field of bits
6830 within an item, but not the entire word. Return -1 if not.
6831 Otherwise, return the starting position of the field, where 0 is the
6834 *PLEN is set to the length of the field. */
6837 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
6839 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6840 int pos = exact_log2 (m & -m);
6844 /* Now shift off the low-order zero bits and see if we have a
6845 power of two minus 1. */
6846 len = exact_log2 ((m >> pos) + 1);
6855 /* See if X can be simplified knowing that we will only refer to it in
6856 MODE and will only refer to those bits that are nonzero in MASK.
6857 If other bits are being computed or if masking operations are done
6858 that select a superset of the bits in MASK, they can sometimes be
6861 Return a possibly simplified expression, but always convert X to
6862 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6864 Also, if REG is nonzero and X is a register equal in value to REG,
6867 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6868 are all off in X. This is used when X will be complemented, by either
6869 NOT, NEG, or XOR. */
6872 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
6873 rtx reg, int just_select)
6875 enum rtx_code code = GET_CODE (x);
6876 int next_select = just_select || code == XOR || code == NOT || code == NEG;
6877 enum machine_mode op_mode;
6878 unsigned HOST_WIDE_INT fuller_mask, nonzero;
6881 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6882 code below will do the wrong thing since the mode of such an
6883 expression is VOIDmode.
6885 Also do nothing if X is a CLOBBER; this can happen if X was
6886 the return value from a call to gen_lowpart. */
6887 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6890 /* We want to perform the operation is its present mode unless we know
6891 that the operation is valid in MODE, in which case we do the operation
6893 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6894 && have_insn_for (code, mode))
6895 ? mode : GET_MODE (x));
6897 /* It is not valid to do a right-shift in a narrower mode
6898 than the one it came in with. */
6899 if ((code == LSHIFTRT || code == ASHIFTRT)
6900 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6901 op_mode = GET_MODE (x);
6903 /* Truncate MASK to fit OP_MODE. */
6905 mask &= GET_MODE_MASK (op_mode);
6907 /* When we have an arithmetic operation, or a shift whose count we
6908 do not know, we need to assume that all bits up to the highest-order
6909 bit in MASK will be needed. This is how we form such a mask. */
6910 if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
6911 fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
6913 fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
6916 /* Determine what bits of X are guaranteed to be (non)zero. */
6917 nonzero = nonzero_bits (x, mode);
6919 /* If none of the bits in X are needed, return a zero. */
6920 if (! just_select && (nonzero & mask) == 0)
6923 /* If X is a CONST_INT, return a new one. Do this here since the
6924 test below will fail. */
6925 if (GET_CODE (x) == CONST_INT)
6927 if (SCALAR_INT_MODE_P (mode))
6928 return gen_int_mode (INTVAL (x) & mask, mode);
6931 x = GEN_INT (INTVAL (x) & mask);
6932 return gen_lowpart_common (mode, x);
6936 /* If X is narrower than MODE and we want all the bits in X's mode, just
6937 get X in the proper mode. */
6938 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6939 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
6940 return gen_lowpart (mode, x);
6942 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6943 MASK are already known to be zero in X, we need not do anything. */
6944 if (GET_MODE (x) == mode && code != SUBREG && (~mask & nonzero) == 0)
6950 /* If X is a (clobber (const_int)), return it since we know we are
6951 generating something that won't match. */
6955 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6956 spanned the boundary of the MEM. If we are now masking so it is
6957 within that boundary, we don't need the USE any more. */
6958 if (! BITS_BIG_ENDIAN
6959 && (mask & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6960 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6967 x = expand_compound_operation (x);
6968 if (GET_CODE (x) != code)
6969 return force_to_mode (x, mode, mask, reg, next_select);
6973 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6974 || rtx_equal_p (reg, get_last_value (x))))
6979 if (subreg_lowpart_p (x)
6980 /* We can ignore the effect of this SUBREG if it narrows the mode or
6981 if the constant masks to zero all the bits the mode doesn't
6983 && ((GET_MODE_SIZE (GET_MODE (x))
6984 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6986 & GET_MODE_MASK (GET_MODE (x))
6987 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6988 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
6992 /* If this is an AND with a constant, convert it into an AND
6993 whose constant is the AND of that constant with MASK. If it
6994 remains an AND of MASK, delete it since it is redundant. */
6996 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6998 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6999 mask & INTVAL (XEXP (x, 1)));
7001 /* If X is still an AND, see if it is an AND with a mask that
7002 is just some low-order bits. If so, and it is MASK, we don't
7005 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
7006 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
7010 /* If it remains an AND, try making another AND with the bits
7011 in the mode mask that aren't in MASK turned on. If the
7012 constant in the AND is wide enough, this might make a
7013 cheaper constant. */
7015 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
7016 && GET_MODE_MASK (GET_MODE (x)) != mask
7017 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
7019 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
7020 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
7021 int width = GET_MODE_BITSIZE (GET_MODE (x));
7024 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
7025 number, sign extend it. */
7026 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
7027 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7028 cval |= (HOST_WIDE_INT) -1 << width;
7030 y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
7031 if (rtx_cost (y, SET) < rtx_cost (x, SET))
7041 /* In (and (plus FOO C1) M), if M is a mask that just turns off
7042 low-order bits (as in an alignment operation) and FOO is already
7043 aligned to that boundary, mask C1 to that boundary as well.
7044 This may eliminate that PLUS and, later, the AND. */
7047 unsigned int width = GET_MODE_BITSIZE (mode);
7048 unsigned HOST_WIDE_INT smask = mask;
7050 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
7051 number, sign extend it. */
7053 if (width < HOST_BITS_PER_WIDE_INT
7054 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7055 smask |= (HOST_WIDE_INT) -1 << width;
7057 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7058 && exact_log2 (- smask) >= 0
7059 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
7060 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
7061 return force_to_mode (plus_constant (XEXP (x, 0),
7062 (INTVAL (XEXP (x, 1)) & smask)),
7063 mode, smask, reg, next_select);
7066 /* ... fall through ... */
7069 /* For PLUS, MINUS and MULT, we need any bits less significant than the
7070 most significant bit in MASK since carries from those bits will
7071 affect the bits we are interested in. */
7076 /* If X is (minus C Y) where C's least set bit is larger than any bit
7077 in the mask, then we may replace with (neg Y). */
7078 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7079 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
7080 & -INTVAL (XEXP (x, 0))))
7083 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
7085 return force_to_mode (x, mode, mask, reg, next_select);
7088 /* Similarly, if C contains every bit in the fuller_mask, then we may
7089 replace with (not Y). */
7090 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7091 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
7092 == INTVAL (XEXP (x, 0))))
7094 x = simplify_gen_unary (NOT, GET_MODE (x),
7095 XEXP (x, 1), GET_MODE (x));
7096 return force_to_mode (x, mode, mask, reg, next_select);
7104 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7105 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7106 operation which may be a bitfield extraction. Ensure that the
7107 constant we form is not wider than the mode of X. */
7109 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7110 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7111 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7112 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7113 && GET_CODE (XEXP (x, 1)) == CONST_INT
7114 && ((INTVAL (XEXP (XEXP (x, 0), 1))
7115 + floor_log2 (INTVAL (XEXP (x, 1))))
7116 < GET_MODE_BITSIZE (GET_MODE (x)))
7117 && (INTVAL (XEXP (x, 1))
7118 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
7120 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
7121 << INTVAL (XEXP (XEXP (x, 0), 1)));
7122 temp = gen_binary (GET_CODE (x), GET_MODE (x),
7123 XEXP (XEXP (x, 0), 0), temp);
7124 x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
7125 XEXP (XEXP (x, 0), 1));
7126 return force_to_mode (x, mode, mask, reg, next_select);
7130 /* For most binary operations, just propagate into the operation and
7131 change the mode if we have an operation of that mode. */
7133 op0 = gen_lowpart (op_mode,
7134 force_to_mode (XEXP (x, 0), mode, mask,
7136 op1 = gen_lowpart (op_mode,
7137 force_to_mode (XEXP (x, 1), mode, mask,
7140 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7141 x = gen_binary (code, op_mode, op0, op1);
7145 /* For left shifts, do the same, but just for the first operand.
7146 However, we cannot do anything with shifts where we cannot
7147 guarantee that the counts are smaller than the size of the mode
7148 because such a count will have a different meaning in a
7151 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
7152 && INTVAL (XEXP (x, 1)) >= 0
7153 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
7154 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
7155 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
7156 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
7159 /* If the shift count is a constant and we can do arithmetic in
7160 the mode of the shift, refine which bits we need. Otherwise, use the
7161 conservative form of the mask. */
7162 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7163 && INTVAL (XEXP (x, 1)) >= 0
7164 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
7165 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7166 mask >>= INTVAL (XEXP (x, 1));
7170 op0 = gen_lowpart (op_mode,
7171 force_to_mode (XEXP (x, 0), op_mode,
7172 mask, reg, next_select));
7174 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7175 x = gen_binary (code, op_mode, op0, XEXP (x, 1));
7179 /* Here we can only do something if the shift count is a constant,
7180 this shift constant is valid for the host, and we can do arithmetic
7183 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7184 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7185 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7187 rtx inner = XEXP (x, 0);
7188 unsigned HOST_WIDE_INT inner_mask;
7190 /* Select the mask of the bits we need for the shift operand. */
7191 inner_mask = mask << INTVAL (XEXP (x, 1));
7193 /* We can only change the mode of the shift if we can do arithmetic
7194 in the mode of the shift and INNER_MASK is no wider than the
7195 width of OP_MODE. */
7196 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT
7197 || (inner_mask & ~GET_MODE_MASK (op_mode)) != 0)
7198 op_mode = GET_MODE (x);
7200 inner = force_to_mode (inner, op_mode, inner_mask, reg, next_select);
7202 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7203 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7206 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7207 shift and AND produces only copies of the sign bit (C2 is one less
7208 than a power of two), we can do this with just a shift. */
7210 if (GET_CODE (x) == LSHIFTRT
7211 && GET_CODE (XEXP (x, 1)) == CONST_INT
7212 /* The shift puts one of the sign bit copies in the least significant
7214 && ((INTVAL (XEXP (x, 1))
7215 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7216 >= GET_MODE_BITSIZE (GET_MODE (x)))
7217 && exact_log2 (mask + 1) >= 0
7218 /* Number of bits left after the shift must be more than the mask
7220 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7221 <= GET_MODE_BITSIZE (GET_MODE (x)))
7222 /* Must be more sign bit copies than the mask needs. */
7223 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7224 >= exact_log2 (mask + 1)))
7225 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7226 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7227 - exact_log2 (mask + 1)));
7232 /* If we are just looking for the sign bit, we don't need this shift at
7233 all, even if it has a variable count. */
7234 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7235 && (mask == ((unsigned HOST_WIDE_INT) 1
7236 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7237 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7239 /* If this is a shift by a constant, get a mask that contains those bits
7240 that are not copies of the sign bit. We then have two cases: If
7241 MASK only includes those bits, this can be a logical shift, which may
7242 allow simplifications. If MASK is a single-bit field not within
7243 those bits, we are requesting a copy of the sign bit and hence can
7244 shift the sign bit to the appropriate location. */
7246 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7247 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7251 /* If the considered data is wider than HOST_WIDE_INT, we can't
7252 represent a mask for all its bits in a single scalar.
7253 But we only care about the lower bits, so calculate these. */
7255 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7257 nonzero = ~(HOST_WIDE_INT) 0;
7259 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7260 is the number of bits a full-width mask would have set.
7261 We need only shift if these are fewer than nonzero can
7262 hold. If not, we must keep all bits set in nonzero. */
7264 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7265 < HOST_BITS_PER_WIDE_INT)
7266 nonzero >>= INTVAL (XEXP (x, 1))
7267 + HOST_BITS_PER_WIDE_INT
7268 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7272 nonzero = GET_MODE_MASK (GET_MODE (x));
7273 nonzero >>= INTVAL (XEXP (x, 1));
7276 if ((mask & ~nonzero) == 0
7277 || (i = exact_log2 (mask)) >= 0)
7279 x = simplify_shift_const
7280 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7281 i < 0 ? INTVAL (XEXP (x, 1))
7282 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7284 if (GET_CODE (x) != ASHIFTRT)
7285 return force_to_mode (x, mode, mask, reg, next_select);
7289 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7290 even if the shift count isn't a constant. */
7292 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
7296 /* If this is a zero- or sign-extension operation that just affects bits
7297 we don't care about, remove it. Be sure the call above returned
7298 something that is still a shift. */
7300 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7301 && GET_CODE (XEXP (x, 1)) == CONST_INT
7302 && INTVAL (XEXP (x, 1)) >= 0
7303 && (INTVAL (XEXP (x, 1))
7304 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7305 && GET_CODE (XEXP (x, 0)) == ASHIFT
7306 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
7307 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7314 /* If the shift count is constant and we can do computations
7315 in the mode of X, compute where the bits we care about are.
7316 Otherwise, we can't do anything. Don't change the mode of
7317 the shift or propagate MODE into the shift, though. */
7318 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7319 && INTVAL (XEXP (x, 1)) >= 0)
7321 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7322 GET_MODE (x), GEN_INT (mask),
7324 if (temp && GET_CODE (temp) == CONST_INT)
7326 force_to_mode (XEXP (x, 0), GET_MODE (x),
7327 INTVAL (temp), reg, next_select));
7332 /* If we just want the low-order bit, the NEG isn't needed since it
7333 won't change the low-order bit. */
7335 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
7337 /* We need any bits less significant than the most significant bit in
7338 MASK since carries from those bits will affect the bits we are
7344 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7345 same as the XOR case above. Ensure that the constant we form is not
7346 wider than the mode of X. */
7348 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7349 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7350 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7351 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7352 < GET_MODE_BITSIZE (GET_MODE (x)))
7353 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7355 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
7357 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
7358 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
7360 return force_to_mode (x, mode, mask, reg, next_select);
7363 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7364 use the full mask inside the NOT. */
7368 op0 = gen_lowpart (op_mode,
7369 force_to_mode (XEXP (x, 0), mode, mask,
7371 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7372 x = simplify_gen_unary (code, op_mode, op0, op_mode);
7376 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7377 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7378 which is equal to STORE_FLAG_VALUE. */
7379 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7380 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7381 && (nonzero_bits (XEXP (x, 0), mode)
7382 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
7383 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7388 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7389 written in a narrower mode. We play it safe and do not do so. */
7392 gen_lowpart (GET_MODE (x),
7393 force_to_mode (XEXP (x, 1), mode,
7394 mask, reg, next_select)));
7396 gen_lowpart (GET_MODE (x),
7397 force_to_mode (XEXP (x, 2), mode,
7398 mask, reg, next_select)));
7405 /* Ensure we return a value of the proper mode. */
7406 return gen_lowpart (mode, x);
7409 /* Return nonzero if X is an expression that has one of two values depending on
7410 whether some other value is zero or nonzero. In that case, we return the
7411 value that is being tested, *PTRUE is set to the value if the rtx being
7412 returned has a nonzero value, and *PFALSE is set to the other alternative.
7414 If we return zero, we set *PTRUE and *PFALSE to X. */
7417 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
7419 enum machine_mode mode = GET_MODE (x);
7420 enum rtx_code code = GET_CODE (x);
7421 rtx cond0, cond1, true0, true1, false0, false1;
7422 unsigned HOST_WIDE_INT nz;
7424 /* If we are comparing a value against zero, we are done. */
7425 if ((code == NE || code == EQ)
7426 && XEXP (x, 1) == const0_rtx)
7428 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7429 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7433 /* If this is a unary operation whose operand has one of two values, apply
7434 our opcode to compute those values. */
7435 else if (UNARY_P (x)
7436 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7438 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7439 *pfalse = simplify_gen_unary (code, mode, false0,
7440 GET_MODE (XEXP (x, 0)));
7444 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7445 make can't possibly match and would suppress other optimizations. */
7446 else if (code == COMPARE)
7449 /* If this is a binary operation, see if either side has only one of two
7450 values. If either one does or if both do and they are conditional on
7451 the same value, compute the new true and false values. */
7452 else if (BINARY_P (x))
7454 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7455 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7457 if ((cond0 != 0 || cond1 != 0)
7458 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7460 /* If if_then_else_cond returned zero, then true/false are the
7461 same rtl. We must copy one of them to prevent invalid rtl
7464 true0 = copy_rtx (true0);
7465 else if (cond1 == 0)
7466 true1 = copy_rtx (true1);
7468 *ptrue = gen_binary (code, mode, true0, true1);
7469 *pfalse = gen_binary (code, mode, false0, false1);
7470 return cond0 ? cond0 : cond1;
7473 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7474 operands is zero when the other is nonzero, and vice-versa,
7475 and STORE_FLAG_VALUE is 1 or -1. */
7477 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7478 && (code == PLUS || code == IOR || code == XOR || code == MINUS
7480 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7482 rtx op0 = XEXP (XEXP (x, 0), 1);
7483 rtx op1 = XEXP (XEXP (x, 1), 1);
7485 cond0 = XEXP (XEXP (x, 0), 0);
7486 cond1 = XEXP (XEXP (x, 1), 0);
7488 if (COMPARISON_P (cond0)
7489 && COMPARISON_P (cond1)
7490 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7491 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7492 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7493 || ((swap_condition (GET_CODE (cond0))
7494 == combine_reversed_comparison_code (cond1))
7495 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7496 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7497 && ! side_effects_p (x))
7499 *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
7500 *pfalse = gen_binary (MULT, mode,
7502 ? simplify_gen_unary (NEG, mode, op1,
7510 /* Similarly for MULT, AND and UMIN, except that for these the result
7512 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7513 && (code == MULT || code == AND || code == UMIN)
7514 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7516 cond0 = XEXP (XEXP (x, 0), 0);
7517 cond1 = XEXP (XEXP (x, 1), 0);
7519 if (COMPARISON_P (cond0)
7520 && COMPARISON_P (cond1)
7521 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7522 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7523 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7524 || ((swap_condition (GET_CODE (cond0))
7525 == combine_reversed_comparison_code (cond1))
7526 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7527 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7528 && ! side_effects_p (x))
7530 *ptrue = *pfalse = const0_rtx;
7536 else if (code == IF_THEN_ELSE)
7538 /* If we have IF_THEN_ELSE already, extract the condition and
7539 canonicalize it if it is NE or EQ. */
7540 cond0 = XEXP (x, 0);
7541 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7542 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7543 return XEXP (cond0, 0);
7544 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7546 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7547 return XEXP (cond0, 0);
7553 /* If X is a SUBREG, we can narrow both the true and false values
7554 if the inner expression, if there is a condition. */
7555 else if (code == SUBREG
7556 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7559 true0 = simplify_gen_subreg (mode, true0,
7560 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7561 false0 = simplify_gen_subreg (mode, false0,
7562 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7563 if (true0 && false0)
7571 /* If X is a constant, this isn't special and will cause confusions
7572 if we treat it as such. Likewise if it is equivalent to a constant. */
7573 else if (CONSTANT_P (x)
7574 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7577 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7578 will be least confusing to the rest of the compiler. */
7579 else if (mode == BImode)
7581 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7585 /* If X is known to be either 0 or -1, those are the true and
7586 false values when testing X. */
7587 else if (x == constm1_rtx || x == const0_rtx
7588 || (mode != VOIDmode
7589 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7591 *ptrue = constm1_rtx, *pfalse = const0_rtx;
7595 /* Likewise for 0 or a single bit. */
7596 else if (SCALAR_INT_MODE_P (mode)
7597 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7598 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7600 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
7604 /* Otherwise fail; show no condition with true and false values the same. */
7605 *ptrue = *pfalse = x;
7609 /* Return the value of expression X given the fact that condition COND
7610 is known to be true when applied to REG as its first operand and VAL
7611 as its second. X is known to not be shared and so can be modified in
7614 We only handle the simplest cases, and specifically those cases that
7615 arise with IF_THEN_ELSE expressions. */
7618 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
7620 enum rtx_code code = GET_CODE (x);
7625 if (side_effects_p (x))
7628 /* If either operand of the condition is a floating point value,
7629 then we have to avoid collapsing an EQ comparison. */
7631 && rtx_equal_p (x, reg)
7632 && ! FLOAT_MODE_P (GET_MODE (x))
7633 && ! FLOAT_MODE_P (GET_MODE (val)))
7636 if (cond == UNEQ && rtx_equal_p (x, reg))
7639 /* If X is (abs REG) and we know something about REG's relationship
7640 with zero, we may be able to simplify this. */
7642 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7645 case GE: case GT: case EQ:
7648 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
7650 GET_MODE (XEXP (x, 0)));
7655 /* The only other cases we handle are MIN, MAX, and comparisons if the
7656 operands are the same as REG and VAL. */
7658 else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
7660 if (rtx_equal_p (XEXP (x, 0), val))
7661 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7663 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7665 if (COMPARISON_P (x))
7667 if (comparison_dominates_p (cond, code))
7668 return const_true_rtx;
7670 code = combine_reversed_comparison_code (x);
7672 && comparison_dominates_p (cond, code))
7677 else if (code == SMAX || code == SMIN
7678 || code == UMIN || code == UMAX)
7680 int unsignedp = (code == UMIN || code == UMAX);
7682 /* Do not reverse the condition when it is NE or EQ.
7683 This is because we cannot conclude anything about
7684 the value of 'SMAX (x, y)' when x is not equal to y,
7685 but we can when x equals y. */
7686 if ((code == SMAX || code == UMAX)
7687 && ! (cond == EQ || cond == NE))
7688 cond = reverse_condition (cond);
7693 return unsignedp ? x : XEXP (x, 1);
7695 return unsignedp ? x : XEXP (x, 0);
7697 return unsignedp ? XEXP (x, 1) : x;
7699 return unsignedp ? XEXP (x, 0) : x;
7706 else if (code == SUBREG)
7708 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
7709 rtx new, r = known_cond (SUBREG_REG (x), cond, reg, val);
7711 if (SUBREG_REG (x) != r)
7713 /* We must simplify subreg here, before we lose track of the
7714 original inner_mode. */
7715 new = simplify_subreg (GET_MODE (x), r,
7716 inner_mode, SUBREG_BYTE (x));
7720 SUBST (SUBREG_REG (x), r);
7725 /* We don't have to handle SIGN_EXTEND here, because even in the
7726 case of replacing something with a modeless CONST_INT, a
7727 CONST_INT is already (supposed to be) a valid sign extension for
7728 its narrower mode, which implies it's already properly
7729 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7730 story is different. */
7731 else if (code == ZERO_EXTEND)
7733 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
7734 rtx new, r = known_cond (XEXP (x, 0), cond, reg, val);
7736 if (XEXP (x, 0) != r)
7738 /* We must simplify the zero_extend here, before we lose
7739 track of the original inner_mode. */
7740 new = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
7745 SUBST (XEXP (x, 0), r);
7751 fmt = GET_RTX_FORMAT (code);
7752 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7755 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7756 else if (fmt[i] == 'E')
7757 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7758 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7765 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7766 assignment as a field assignment. */
7769 rtx_equal_for_field_assignment_p (rtx x, rtx y)
7771 if (x == y || rtx_equal_p (x, y))
7774 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7777 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7778 Note that all SUBREGs of MEM are paradoxical; otherwise they
7779 would have been rewritten. */
7780 if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG
7781 && GET_CODE (SUBREG_REG (y)) == MEM
7782 && rtx_equal_p (SUBREG_REG (y),
7783 gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
7786 if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG
7787 && GET_CODE (SUBREG_REG (x)) == MEM
7788 && rtx_equal_p (SUBREG_REG (x),
7789 gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
7792 /* We used to see if get_last_value of X and Y were the same but that's
7793 not correct. In one direction, we'll cause the assignment to have
7794 the wrong destination and in the case, we'll import a register into this
7795 insn that might have already have been dead. So fail if none of the
7796 above cases are true. */
7800 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7801 Return that assignment if so.
7803 We only handle the most common cases. */
7806 make_field_assignment (rtx x)
7808 rtx dest = SET_DEST (x);
7809 rtx src = SET_SRC (x);
7814 unsigned HOST_WIDE_INT len;
7816 enum machine_mode mode;
7818 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7819 a clear of a one-bit field. We will have changed it to
7820 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7823 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7824 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7825 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7826 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7828 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7831 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7835 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7836 && subreg_lowpart_p (XEXP (src, 0))
7837 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7838 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7839 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7840 && GET_CODE (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == CONST_INT
7841 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7842 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7844 assign = make_extraction (VOIDmode, dest, 0,
7845 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7848 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7852 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7854 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7855 && XEXP (XEXP (src, 0), 0) == const1_rtx
7856 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7858 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7861 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7865 /* The other case we handle is assignments into a constant-position
7866 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7867 a mask that has all one bits except for a group of zero bits and
7868 OTHER is known to have zeros where C1 has ones, this is such an
7869 assignment. Compute the position and length from C1. Shift OTHER
7870 to the appropriate position, force it to the required mode, and
7871 make the extraction. Check for the AND in both operands. */
7873 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7876 rhs = expand_compound_operation (XEXP (src, 0));
7877 lhs = expand_compound_operation (XEXP (src, 1));
7879 if (GET_CODE (rhs) == AND
7880 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7881 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7882 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7883 else if (GET_CODE (lhs) == AND
7884 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7885 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7886 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7890 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7891 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7892 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7893 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7896 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7900 /* The mode to use for the source is the mode of the assignment, or of
7901 what is inside a possible STRICT_LOW_PART. */
7902 mode = (GET_CODE (assign) == STRICT_LOW_PART
7903 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7905 /* Shift OTHER right POS places and make it the source, restricting it
7906 to the proper length and mode. */
7908 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
7909 GET_MODE (src), other, pos),
7911 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7912 ? ~(unsigned HOST_WIDE_INT) 0
7913 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7916 /* If SRC is masked by an AND that does not make a difference in
7917 the value being stored, strip it. */
7918 if (GET_CODE (assign) == ZERO_EXTRACT
7919 && GET_CODE (XEXP (assign, 1)) == CONST_INT
7920 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
7921 && GET_CODE (src) == AND
7922 && GET_CODE (XEXP (src, 1)) == CONST_INT
7923 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
7924 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
7925 src = XEXP (src, 0);
7927 return gen_rtx_SET (VOIDmode, assign, src);
7930 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7934 apply_distributive_law (rtx x)
7936 enum rtx_code code = GET_CODE (x);
7937 enum rtx_code inner_code;
7938 rtx lhs, rhs, other;
7941 /* Distributivity is not true for floating point as it can change the
7942 value. So we don't do it unless -funsafe-math-optimizations. */
7943 if (FLOAT_MODE_P (GET_MODE (x))
7944 && ! flag_unsafe_math_optimizations)
7947 /* The outer operation can only be one of the following: */
7948 if (code != IOR && code != AND && code != XOR
7949 && code != PLUS && code != MINUS)
7955 /* If either operand is a primitive we can't do anything, so get out
7957 if (OBJECT_P (lhs) || OBJECT_P (rhs))
7960 lhs = expand_compound_operation (lhs);
7961 rhs = expand_compound_operation (rhs);
7962 inner_code = GET_CODE (lhs);
7963 if (inner_code != GET_CODE (rhs))
7966 /* See if the inner and outer operations distribute. */
7973 /* These all distribute except over PLUS. */
7974 if (code == PLUS || code == MINUS)
7979 if (code != PLUS && code != MINUS)
7984 /* This is also a multiply, so it distributes over everything. */
7988 /* Non-paradoxical SUBREGs distributes over all operations, provided
7989 the inner modes and byte offsets are the same, this is an extraction
7990 of a low-order part, we don't convert an fp operation to int or
7991 vice versa, and we would not be converting a single-word
7992 operation into a multi-word operation. The latter test is not
7993 required, but it prevents generating unneeded multi-word operations.
7994 Some of the previous tests are redundant given the latter test, but
7995 are retained because they are required for correctness.
7997 We produce the result slightly differently in this case. */
7999 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
8000 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
8001 || ! subreg_lowpart_p (lhs)
8002 || (GET_MODE_CLASS (GET_MODE (lhs))
8003 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
8004 || (GET_MODE_SIZE (GET_MODE (lhs))
8005 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
8006 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
8009 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
8010 SUBREG_REG (lhs), SUBREG_REG (rhs));
8011 return gen_lowpart (GET_MODE (x), tem);
8017 /* Set LHS and RHS to the inner operands (A and B in the example
8018 above) and set OTHER to the common operand (C in the example).
8019 There is only one way to do this unless the inner operation is
8021 if (COMMUTATIVE_ARITH_P (lhs)
8022 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
8023 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
8024 else if (COMMUTATIVE_ARITH_P (lhs)
8025 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
8026 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
8027 else if (COMMUTATIVE_ARITH_P (lhs)
8028 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
8029 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
8030 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
8031 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
8035 /* Form the new inner operation, seeing if it simplifies first. */
8036 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
8038 /* There is one exception to the general way of distributing:
8039 (a | c) ^ (b | c) -> (a ^ b) & ~c */
8040 if (code == XOR && inner_code == IOR)
8043 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
8046 /* We may be able to continuing distributing the result, so call
8047 ourselves recursively on the inner operation before forming the
8048 outer operation, which we return. */
8049 return gen_binary (inner_code, GET_MODE (x),
8050 apply_distributive_law (tem), other);
8053 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8056 Return an equivalent form, if different from X. Otherwise, return X. If
8057 X is zero, we are to always construct the equivalent form. */
8060 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
8061 unsigned HOST_WIDE_INT constop)
8063 unsigned HOST_WIDE_INT nonzero;
8066 /* Simplify VAROP knowing that we will be only looking at some of the
8069 Note by passing in CONSTOP, we guarantee that the bits not set in
8070 CONSTOP are not significant and will never be examined. We must
8071 ensure that is the case by explicitly masking out those bits
8072 before returning. */
8073 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
8075 /* If VAROP is a CLOBBER, we will fail so return it. */
8076 if (GET_CODE (varop) == CLOBBER)
8079 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8080 to VAROP and return the new constant. */
8081 if (GET_CODE (varop) == CONST_INT)
8082 return GEN_INT (trunc_int_for_mode (INTVAL (varop) & constop, mode));
8084 /* See what bits may be nonzero in VAROP. Unlike the general case of
8085 a call to nonzero_bits, here we don't care about bits outside
8088 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
8090 /* Turn off all bits in the constant that are known to already be zero.
8091 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8092 which is tested below. */
8096 /* If we don't have any bits left, return zero. */
8100 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8101 a power of two, we can replace this with an ASHIFT. */
8102 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
8103 && (i = exact_log2 (constop)) >= 0)
8104 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
8106 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8107 or XOR, then try to apply the distributive law. This may eliminate
8108 operations if either branch can be simplified because of the AND.
8109 It may also make some cases more complex, but those cases probably
8110 won't match a pattern either with or without this. */
8112 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
8116 apply_distributive_law
8117 (gen_binary (GET_CODE (varop), GET_MODE (varop),
8118 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
8119 XEXP (varop, 0), constop),
8120 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
8121 XEXP (varop, 1), constop))));
8123 /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
8124 the AND and see if one of the operands simplifies to zero. If so, we
8125 may eliminate it. */
8127 if (GET_CODE (varop) == PLUS
8128 && exact_log2 (constop + 1) >= 0)
8132 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
8133 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
8134 if (o0 == const0_rtx)
8136 if (o1 == const0_rtx)
8140 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
8141 if we already had one (just check for the simplest cases). */
8142 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
8143 && GET_MODE (XEXP (x, 0)) == mode
8144 && SUBREG_REG (XEXP (x, 0)) == varop)
8145 varop = XEXP (x, 0);
8147 varop = gen_lowpart (mode, varop);
8149 /* If we can't make the SUBREG, try to return what we were given. */
8150 if (GET_CODE (varop) == CLOBBER)
8151 return x ? x : varop;
8153 /* If we are only masking insignificant bits, return VAROP. */
8154 if (constop == nonzero)
8158 /* Otherwise, return an AND. */
8159 constop = trunc_int_for_mode (constop, mode);
8160 /* See how much, if any, of X we can use. */
8161 if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
8162 x = gen_binary (AND, mode, varop, GEN_INT (constop));
8166 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8167 || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop)
8168 SUBST (XEXP (x, 1), GEN_INT (constop));
8170 SUBST (XEXP (x, 0), varop);
8177 /* Given a REG, X, compute which bits in X can be nonzero.
8178 We don't care about bits outside of those defined in MODE.
8180 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8181 a shift, AND, or zero_extract, we can do better. */
8184 reg_nonzero_bits_for_combine (rtx x, enum machine_mode mode,
8185 rtx known_x ATTRIBUTE_UNUSED,
8186 enum machine_mode known_mode ATTRIBUTE_UNUSED,
8187 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
8188 unsigned HOST_WIDE_INT *nonzero)
8192 /* If X is a register whose nonzero bits value is current, use it.
8193 Otherwise, if X is a register whose value we can find, use that
8194 value. Otherwise, use the previously-computed global nonzero bits
8195 for this register. */
8197 if (reg_stat[REGNO (x)].last_set_value != 0
8198 && (reg_stat[REGNO (x)].last_set_mode == mode
8199 || (GET_MODE_CLASS (reg_stat[REGNO (x)].last_set_mode) == MODE_INT
8200 && GET_MODE_CLASS (mode) == MODE_INT))
8201 && (reg_stat[REGNO (x)].last_set_label == label_tick
8202 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8203 && REG_N_SETS (REGNO (x)) == 1
8204 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start,
8206 && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid)
8208 *nonzero &= reg_stat[REGNO (x)].last_set_nonzero_bits;
8212 tem = get_last_value (x);
8216 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8217 /* If X is narrower than MODE and TEM is a non-negative
8218 constant that would appear negative in the mode of X,
8219 sign-extend it for use in reg_nonzero_bits because some
8220 machines (maybe most) will actually do the sign-extension
8221 and this is the conservative approach.
8223 ??? For 2.5, try to tighten up the MD files in this regard
8224 instead of this kludge. */
8226 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)
8227 && GET_CODE (tem) == CONST_INT
8229 && 0 != (INTVAL (tem)
8230 & ((HOST_WIDE_INT) 1
8231 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8232 tem = GEN_INT (INTVAL (tem)
8233 | ((HOST_WIDE_INT) (-1)
8234 << GET_MODE_BITSIZE (GET_MODE (x))));
8238 else if (nonzero_sign_valid && reg_stat[REGNO (x)].nonzero_bits)
8240 unsigned HOST_WIDE_INT mask = reg_stat[REGNO (x)].nonzero_bits;
8242 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode))
8243 /* We don't know anything about the upper bits. */
8244 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
8251 /* Return the number of bits at the high-order end of X that are known to
8252 be equal to the sign bit. X will be used in mode MODE; if MODE is
8253 VOIDmode, X will be used in its own mode. The returned value will always
8254 be between 1 and the number of bits in MODE. */
8257 reg_num_sign_bit_copies_for_combine (rtx x, enum machine_mode mode,
8258 rtx known_x ATTRIBUTE_UNUSED,
8259 enum machine_mode known_mode
8261 unsigned int known_ret ATTRIBUTE_UNUSED,
8262 unsigned int *result)
8266 if (reg_stat[REGNO (x)].last_set_value != 0
8267 && reg_stat[REGNO (x)].last_set_mode == mode
8268 && (reg_stat[REGNO (x)].last_set_label == label_tick
8269 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8270 && REG_N_SETS (REGNO (x)) == 1
8271 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start,
8273 && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid)
8275 *result = reg_stat[REGNO (x)].last_set_sign_bit_copies;
8279 tem = get_last_value (x);
8283 if (nonzero_sign_valid && reg_stat[REGNO (x)].sign_bit_copies != 0
8284 && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode))
8285 *result = reg_stat[REGNO (x)].sign_bit_copies;
8290 /* Return the number of "extended" bits there are in X, when interpreted
8291 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8292 unsigned quantities, this is the number of high-order zero bits.
8293 For signed quantities, this is the number of copies of the sign bit
8294 minus 1. In both case, this function returns the number of "spare"
8295 bits. For example, if two quantities for which this function returns
8296 at least 1 are added, the addition is known not to overflow.
8298 This function will always return 0 unless called during combine, which
8299 implies that it must be called from a define_split. */
8302 extended_count (rtx x, enum machine_mode mode, int unsignedp)
8304 if (nonzero_sign_valid == 0)
8308 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8309 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
8310 - floor_log2 (nonzero_bits (x, mode)))
8312 : num_sign_bit_copies (x, mode) - 1);
8315 /* This function is called from `simplify_shift_const' to merge two
8316 outer operations. Specifically, we have already found that we need
8317 to perform operation *POP0 with constant *PCONST0 at the outermost
8318 position. We would now like to also perform OP1 with constant CONST1
8319 (with *POP0 being done last).
8321 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8322 the resulting operation. *PCOMP_P is set to 1 if we would need to
8323 complement the innermost operand, otherwise it is unchanged.
8325 MODE is the mode in which the operation will be done. No bits outside
8326 the width of this mode matter. It is assumed that the width of this mode
8327 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8329 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8330 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8331 result is simply *PCONST0.
8333 If the resulting operation cannot be expressed as one operation, we
8334 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8337 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
8339 enum rtx_code op0 = *pop0;
8340 HOST_WIDE_INT const0 = *pconst0;
8342 const0 &= GET_MODE_MASK (mode);
8343 const1 &= GET_MODE_MASK (mode);
8345 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8349 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
8352 if (op1 == NIL || op0 == SET)
8355 else if (op0 == NIL)
8356 op0 = op1, const0 = const1;
8358 else if (op0 == op1)
8382 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8383 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8386 /* If the two constants aren't the same, we can't do anything. The
8387 remaining six cases can all be done. */
8388 else if (const0 != const1)
8396 /* (a & b) | b == b */
8398 else /* op1 == XOR */
8399 /* (a ^ b) | b == a | b */
8405 /* (a & b) ^ b == (~a) & b */
8406 op0 = AND, *pcomp_p = 1;
8407 else /* op1 == IOR */
8408 /* (a | b) ^ b == a & ~b */
8409 op0 = AND, const0 = ~const0;
8414 /* (a | b) & b == b */
8416 else /* op1 == XOR */
8417 /* (a ^ b) & b) == (~a) & b */
8424 /* Check for NO-OP cases. */
8425 const0 &= GET_MODE_MASK (mode);
8427 && (op0 == IOR || op0 == XOR || op0 == PLUS))
8429 else if (const0 == 0 && op0 == AND)
8431 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8435 /* ??? Slightly redundant with the above mask, but not entirely.
8436 Moving this above means we'd have to sign-extend the mode mask
8437 for the final test. */
8438 const0 = trunc_int_for_mode (const0, mode);
8446 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8447 The result of the shift is RESULT_MODE. X, if nonzero, is an expression
8448 that we started with.
8450 The shift is normally computed in the widest mode we find in VAROP, as
8451 long as it isn't a different number of words than RESULT_MODE. Exceptions
8452 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8455 simplify_shift_const (rtx x, enum rtx_code code,
8456 enum machine_mode result_mode, rtx varop,
8459 enum rtx_code orig_code = code;
8462 enum machine_mode mode = result_mode;
8463 enum machine_mode shift_mode, tmode;
8464 unsigned int mode_words
8465 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8466 /* We form (outer_op (code varop count) (outer_const)). */
8467 enum rtx_code outer_op = NIL;
8468 HOST_WIDE_INT outer_const = 0;
8470 int complement_p = 0;
8473 /* Make sure and truncate the "natural" shift on the way in. We don't
8474 want to do this inside the loop as it makes it more difficult to
8476 if (SHIFT_COUNT_TRUNCATED)
8477 orig_count &= GET_MODE_BITSIZE (mode) - 1;
8479 /* If we were given an invalid count, don't do anything except exactly
8480 what was requested. */
8482 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
8487 return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (orig_count));
8492 /* Unless one of the branches of the `if' in this loop does a `continue',
8493 we will `break' the loop after the `if'. */
8497 /* If we have an operand of (clobber (const_int 0)), just return that
8499 if (GET_CODE (varop) == CLOBBER)
8502 /* If we discovered we had to complement VAROP, leave. Making a NOT
8503 here would cause an infinite loop. */
8507 /* Convert ROTATERT to ROTATE. */
8508 if (code == ROTATERT)
8510 unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
8512 if (VECTOR_MODE_P (result_mode))
8513 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
8515 count = bitsize - count;
8518 /* We need to determine what mode we will do the shift in. If the
8519 shift is a right shift or a ROTATE, we must always do it in the mode
8520 it was originally done in. Otherwise, we can do it in MODE, the
8521 widest mode encountered. */
8523 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8524 ? result_mode : mode);
8526 /* Handle cases where the count is greater than the size of the mode
8527 minus 1. For ASHIFT, use the size minus one as the count (this can
8528 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8529 take the count modulo the size. For other shifts, the result is
8532 Since these shifts are being produced by the compiler by combining
8533 multiple operations, each of which are defined, we know what the
8534 result is supposed to be. */
8536 if (count > (unsigned int) (GET_MODE_BITSIZE (shift_mode) - 1))
8538 if (code == ASHIFTRT)
8539 count = GET_MODE_BITSIZE (shift_mode) - 1;
8540 else if (code == ROTATE || code == ROTATERT)
8541 count %= GET_MODE_BITSIZE (shift_mode);
8544 /* We can't simply return zero because there may be an
8552 /* An arithmetic right shift of a quantity known to be -1 or 0
8554 if (code == ASHIFTRT
8555 && (num_sign_bit_copies (varop, shift_mode)
8556 == GET_MODE_BITSIZE (shift_mode)))
8562 /* If we are doing an arithmetic right shift and discarding all but
8563 the sign bit copies, this is equivalent to doing a shift by the
8564 bitsize minus one. Convert it into that shift because it will often
8565 allow other simplifications. */
8567 if (code == ASHIFTRT
8568 && (count + num_sign_bit_copies (varop, shift_mode)
8569 >= GET_MODE_BITSIZE (shift_mode)))
8570 count = GET_MODE_BITSIZE (shift_mode) - 1;
8572 /* We simplify the tests below and elsewhere by converting
8573 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8574 `make_compound_operation' will convert it to an ASHIFTRT for
8575 those machines (such as VAX) that don't have an LSHIFTRT. */
8576 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8578 && ((nonzero_bits (varop, shift_mode)
8579 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
8583 if (code == LSHIFTRT
8584 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8585 && !(nonzero_bits (varop, shift_mode) >> count))
8588 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8589 && !((nonzero_bits (varop, shift_mode) << count)
8590 & GET_MODE_MASK (shift_mode)))
8593 switch (GET_CODE (varop))
8599 new = expand_compound_operation (varop);
8608 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8609 minus the width of a smaller mode, we can do this with a
8610 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
8611 if ((code == ASHIFTRT || code == LSHIFTRT)
8612 && ! mode_dependent_address_p (XEXP (varop, 0))
8613 && ! MEM_VOLATILE_P (varop)
8614 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8615 MODE_INT, 1)) != BLKmode)
8617 new = adjust_address_nv (varop, tmode,
8618 BYTES_BIG_ENDIAN ? 0
8619 : count / BITS_PER_UNIT);
8621 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
8622 : ZERO_EXTEND, mode, new);
8629 /* Similar to the case above, except that we can only do this if
8630 the resulting mode is the same as that of the underlying
8631 MEM and adjust the address depending on the *bits* endianness
8632 because of the way that bit-field extract insns are defined. */
8633 if ((code == ASHIFTRT || code == LSHIFTRT)
8634 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8635 MODE_INT, 1)) != BLKmode
8636 && tmode == GET_MODE (XEXP (varop, 0)))
8638 if (BITS_BIG_ENDIAN)
8639 new = XEXP (varop, 0);
8642 new = copy_rtx (XEXP (varop, 0));
8643 SUBST (XEXP (new, 0),
8644 plus_constant (XEXP (new, 0),
8645 count / BITS_PER_UNIT));
8648 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
8649 : ZERO_EXTEND, mode, new);
8656 /* If VAROP is a SUBREG, strip it as long as the inner operand has
8657 the same number of words as what we've seen so far. Then store
8658 the widest mode in MODE. */
8659 if (subreg_lowpart_p (varop)
8660 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8661 > GET_MODE_SIZE (GET_MODE (varop)))
8662 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8663 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
8666 varop = SUBREG_REG (varop);
8667 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
8668 mode = GET_MODE (varop);
8674 /* Some machines use MULT instead of ASHIFT because MULT
8675 is cheaper. But it is still better on those machines to
8676 merge two shifts into one. */
8677 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8678 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8681 = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
8682 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
8688 /* Similar, for when divides are cheaper. */
8689 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8690 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8693 = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
8694 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
8700 /* If we are extracting just the sign bit of an arithmetic
8701 right shift, that shift is not needed. However, the sign
8702 bit of a wider mode may be different from what would be
8703 interpreted as the sign bit in a narrower mode, so, if
8704 the result is narrower, don't discard the shift. */
8705 if (code == LSHIFTRT
8706 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
8707 && (GET_MODE_BITSIZE (result_mode)
8708 >= GET_MODE_BITSIZE (GET_MODE (varop))))
8710 varop = XEXP (varop, 0);
8714 /* ... fall through ... */
8719 /* Here we have two nested shifts. The result is usually the
8720 AND of a new shift with a mask. We compute the result below. */
8721 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8722 && INTVAL (XEXP (varop, 1)) >= 0
8723 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
8724 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8725 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
8727 enum rtx_code first_code = GET_CODE (varop);
8728 unsigned int first_count = INTVAL (XEXP (varop, 1));
8729 unsigned HOST_WIDE_INT mask;
8732 /* We have one common special case. We can't do any merging if
8733 the inner code is an ASHIFTRT of a smaller mode. However, if
8734 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8735 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8736 we can convert it to
8737 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8738 This simplifies certain SIGN_EXTEND operations. */
8739 if (code == ASHIFT && first_code == ASHIFTRT
8740 && count == (unsigned int)
8741 (GET_MODE_BITSIZE (result_mode)
8742 - GET_MODE_BITSIZE (GET_MODE (varop))))
8744 /* C3 has the low-order C1 bits zero. */
8746 mask = (GET_MODE_MASK (mode)
8747 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
8749 varop = simplify_and_const_int (NULL_RTX, result_mode,
8750 XEXP (varop, 0), mask);
8751 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
8753 count = first_count;
8758 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8759 than C1 high-order bits equal to the sign bit, we can convert
8760 this to either an ASHIFT or an ASHIFTRT depending on the
8763 We cannot do this if VAROP's mode is not SHIFT_MODE. */
8765 if (code == ASHIFTRT && first_code == ASHIFT
8766 && GET_MODE (varop) == shift_mode
8767 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
8770 varop = XEXP (varop, 0);
8772 signed_count = count - first_count;
8773 if (signed_count < 0)
8774 count = -signed_count, code = ASHIFT;
8776 count = signed_count;
8781 /* There are some cases we can't do. If CODE is ASHIFTRT,
8782 we can only do this if FIRST_CODE is also ASHIFTRT.
8784 We can't do the case when CODE is ROTATE and FIRST_CODE is
8787 If the mode of this shift is not the mode of the outer shift,
8788 we can't do this if either shift is a right shift or ROTATE.
8790 Finally, we can't do any of these if the mode is too wide
8791 unless the codes are the same.
8793 Handle the case where the shift codes are the same
8796 if (code == first_code)
8798 if (GET_MODE (varop) != result_mode
8799 && (code == ASHIFTRT || code == LSHIFTRT
8803 count += first_count;
8804 varop = XEXP (varop, 0);
8808 if (code == ASHIFTRT
8809 || (code == ROTATE && first_code == ASHIFTRT)
8810 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
8811 || (GET_MODE (varop) != result_mode
8812 && (first_code == ASHIFTRT || first_code == LSHIFTRT
8813 || first_code == ROTATE
8814 || code == ROTATE)))
8817 /* To compute the mask to apply after the shift, shift the
8818 nonzero bits of the inner shift the same way the
8819 outer shift will. */
8821 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
8824 = simplify_binary_operation (code, result_mode, mask_rtx,
8827 /* Give up if we can't compute an outer operation to use. */
8829 || GET_CODE (mask_rtx) != CONST_INT
8830 || ! merge_outer_ops (&outer_op, &outer_const, AND,
8832 result_mode, &complement_p))
8835 /* If the shifts are in the same direction, we add the
8836 counts. Otherwise, we subtract them. */
8837 signed_count = count;
8838 if ((code == ASHIFTRT || code == LSHIFTRT)
8839 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
8840 signed_count += first_count;
8842 signed_count -= first_count;
8844 /* If COUNT is positive, the new shift is usually CODE,
8845 except for the two exceptions below, in which case it is
8846 FIRST_CODE. If the count is negative, FIRST_CODE should
8848 if (signed_count > 0
8849 && ((first_code == ROTATE && code == ASHIFT)
8850 || (first_code == ASHIFTRT && code == LSHIFTRT)))
8851 code = first_code, count = signed_count;
8852 else if (signed_count < 0)
8853 code = first_code, count = -signed_count;
8855 count = signed_count;
8857 varop = XEXP (varop, 0);
8861 /* If we have (A << B << C) for any shift, we can convert this to
8862 (A << C << B). This wins if A is a constant. Only try this if
8863 B is not a constant. */
8865 else if (GET_CODE (varop) == code
8866 && GET_CODE (XEXP (varop, 1)) != CONST_INT
8868 = simplify_binary_operation (code, mode,
8872 varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1));
8879 /* Make this fit the case below. */
8880 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
8881 GEN_INT (GET_MODE_MASK (mode)));
8887 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
8888 with C the size of VAROP - 1 and the shift is logical if
8889 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8890 we have an (le X 0) operation. If we have an arithmetic shift
8891 and STORE_FLAG_VALUE is 1 or we have a logical shift with
8892 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
8894 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
8895 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
8896 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8897 && (code == LSHIFTRT || code == ASHIFTRT)
8898 && count == (unsigned int)
8899 (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
8900 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8903 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
8906 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8907 varop = gen_rtx_NEG (GET_MODE (varop), varop);
8912 /* If we have (shift (logical)), move the logical to the outside
8913 to allow it to possibly combine with another logical and the
8914 shift to combine with another shift. This also canonicalizes to
8915 what a ZERO_EXTRACT looks like. Also, some machines have
8916 (and (shift)) insns. */
8918 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8919 /* We can't do this if we have (ashiftrt (xor)) and the
8920 constant has its sign bit set in shift_mode. */
8921 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
8922 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
8924 && (new = simplify_binary_operation (code, result_mode,
8926 GEN_INT (count))) != 0
8927 && GET_CODE (new) == CONST_INT
8928 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
8929 INTVAL (new), result_mode, &complement_p))
8931 varop = XEXP (varop, 0);
8935 /* If we can't do that, try to simplify the shift in each arm of the
8936 logical expression, make a new logical expression, and apply
8937 the inverse distributive law. This also can't be done
8938 for some (ashiftrt (xor)). */
8939 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8940 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
8941 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
8944 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8945 XEXP (varop, 0), count);
8946 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8947 XEXP (varop, 1), count);
8949 varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
8950 varop = apply_distributive_law (varop);
8958 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
8959 says that the sign bit can be tested, FOO has mode MODE, C is
8960 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
8961 that may be nonzero. */
8962 if (code == LSHIFTRT
8963 && XEXP (varop, 1) == const0_rtx
8964 && GET_MODE (XEXP (varop, 0)) == result_mode
8965 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
8966 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8967 && ((STORE_FLAG_VALUE
8968 & ((HOST_WIDE_INT) 1
8969 < (GET_MODE_BITSIZE (result_mode) - 1))))
8970 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
8971 && merge_outer_ops (&outer_op, &outer_const, XOR,
8972 (HOST_WIDE_INT) 1, result_mode,
8975 varop = XEXP (varop, 0);
8982 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
8983 than the number of bits in the mode is equivalent to A. */
8984 if (code == LSHIFTRT
8985 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
8986 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
8988 varop = XEXP (varop, 0);
8993 /* NEG commutes with ASHIFT since it is multiplication. Move the
8994 NEG outside to allow shifts to combine. */
8996 && merge_outer_ops (&outer_op, &outer_const, NEG,
8997 (HOST_WIDE_INT) 0, result_mode,
9000 varop = XEXP (varop, 0);
9006 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9007 is one less than the number of bits in the mode is
9008 equivalent to (xor A 1). */
9009 if (code == LSHIFTRT
9010 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9011 && XEXP (varop, 1) == constm1_rtx
9012 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9013 && merge_outer_ops (&outer_op, &outer_const, XOR,
9014 (HOST_WIDE_INT) 1, result_mode,
9018 varop = XEXP (varop, 0);
9022 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9023 that might be nonzero in BAR are those being shifted out and those
9024 bits are known zero in FOO, we can replace the PLUS with FOO.
9025 Similarly in the other operand order. This code occurs when
9026 we are computing the size of a variable-size array. */
9028 if ((code == ASHIFTRT || code == LSHIFTRT)
9029 && count < HOST_BITS_PER_WIDE_INT
9030 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9031 && (nonzero_bits (XEXP (varop, 1), result_mode)
9032 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9034 varop = XEXP (varop, 0);
9037 else if ((code == ASHIFTRT || code == LSHIFTRT)
9038 && count < HOST_BITS_PER_WIDE_INT
9039 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9040 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9042 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9043 & nonzero_bits (XEXP (varop, 1),
9046 varop = XEXP (varop, 1);
9050 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9052 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9053 && (new = simplify_binary_operation (ASHIFT, result_mode,
9055 GEN_INT (count))) != 0
9056 && GET_CODE (new) == CONST_INT
9057 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9058 INTVAL (new), result_mode, &complement_p))
9060 varop = XEXP (varop, 0);
9066 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9067 with C the size of VAROP - 1 and the shift is logical if
9068 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9069 we have a (gt X 0) operation. If the shift is arithmetic with
9070 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9071 we have a (neg (gt X 0)) operation. */
9073 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9074 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9075 && count == (unsigned int)
9076 (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9077 && (code == LSHIFTRT || code == ASHIFTRT)
9078 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9079 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (varop, 0), 1))
9081 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9084 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9087 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9088 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9095 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9096 if the truncate does not affect the value. */
9097 if (code == LSHIFTRT
9098 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9099 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9100 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9101 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9102 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9104 rtx varop_inner = XEXP (varop, 0);
9107 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9108 XEXP (varop_inner, 0),
9110 (count + INTVAL (XEXP (varop_inner, 1))));
9111 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9124 /* We need to determine what mode to do the shift in. If the shift is
9125 a right shift or ROTATE, we must always do it in the mode it was
9126 originally done in. Otherwise, we can do it in MODE, the widest mode
9127 encountered. The code we care about is that of the shift that will
9128 actually be done, not the shift that was originally requested. */
9130 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9131 ? result_mode : mode);
9133 /* We have now finished analyzing the shift. The result should be
9134 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9135 OUTER_OP is non-NIL, it is an operation that needs to be applied
9136 to the result of the shift. OUTER_CONST is the relevant constant,
9137 but we must turn off all bits turned off in the shift.
9139 If we were passed a value for X, see if we can use any pieces of
9140 it. If not, make new rtx. */
9142 if (x && GET_RTX_CLASS (GET_CODE (x)) == RTX_BIN_ARITH
9143 && GET_CODE (XEXP (x, 1)) == CONST_INT
9144 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) == count)
9145 const_rtx = XEXP (x, 1);
9147 const_rtx = GEN_INT (count);
9149 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
9150 && GET_MODE (XEXP (x, 0)) == shift_mode
9151 && SUBREG_REG (XEXP (x, 0)) == varop)
9152 varop = XEXP (x, 0);
9153 else if (GET_MODE (varop) != shift_mode)
9154 varop = gen_lowpart (shift_mode, varop);
9156 /* If we can't make the SUBREG, try to return what we were given. */
9157 if (GET_CODE (varop) == CLOBBER)
9158 return x ? x : varop;
9160 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
9164 x = gen_rtx_fmt_ee (code, shift_mode, varop, const_rtx);
9166 /* If we have an outer operation and we just made a shift, it is
9167 possible that we could have simplified the shift were it not
9168 for the outer operation. So try to do the simplification
9171 if (outer_op != NIL && GET_CODE (x) == code
9172 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9173 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
9174 INTVAL (XEXP (x, 1)));
9176 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9177 turn off all the bits that the shift would have turned off. */
9178 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9179 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9180 GET_MODE_MASK (result_mode) >> orig_count);
9182 /* Do the remainder of the processing in RESULT_MODE. */
9183 x = gen_lowpart (result_mode, x);
9185 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9188 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
9190 if (outer_op != NIL)
9192 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9193 outer_const = trunc_int_for_mode (outer_const, result_mode);
9195 if (outer_op == AND)
9196 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9197 else if (outer_op == SET)
9198 /* This means that we have determined that the result is
9199 equivalent to a constant. This should be rare. */
9200 x = GEN_INT (outer_const);
9201 else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
9202 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
9204 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
9210 /* Like recog, but we receive the address of a pointer to a new pattern.
9211 We try to match the rtx that the pointer points to.
9212 If that fails, we may try to modify or replace the pattern,
9213 storing the replacement into the same pointer object.
9215 Modifications include deletion or addition of CLOBBERs.
9217 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9218 the CLOBBERs are placed.
9220 The value is the final insn code from the pattern ultimately matched,
9224 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
9227 int insn_code_number;
9228 int num_clobbers_to_add = 0;
9231 rtx old_notes, old_pat;
9233 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9234 we use to indicate that something didn't match. If we find such a
9235 thing, force rejection. */
9236 if (GET_CODE (pat) == PARALLEL)
9237 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9238 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9239 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9242 old_pat = PATTERN (insn);
9243 old_notes = REG_NOTES (insn);
9244 PATTERN (insn) = pat;
9245 REG_NOTES (insn) = 0;
9247 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9249 /* If it isn't, there is the possibility that we previously had an insn
9250 that clobbered some register as a side effect, but the combined
9251 insn doesn't need to do that. So try once more without the clobbers
9252 unless this represents an ASM insn. */
9254 if (insn_code_number < 0 && ! check_asm_operands (pat)
9255 && GET_CODE (pat) == PARALLEL)
9259 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9260 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9263 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9267 SUBST_INT (XVECLEN (pat, 0), pos);
9270 pat = XVECEXP (pat, 0, 0);
9272 PATTERN (insn) = pat;
9273 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9275 PATTERN (insn) = old_pat;
9276 REG_NOTES (insn) = old_notes;
9278 /* Recognize all noop sets, these will be killed by followup pass. */
9279 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
9280 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
9282 /* If we had any clobbers to add, make a new pattern than contains
9283 them. Then check to make sure that all of them are dead. */
9284 if (num_clobbers_to_add)
9286 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9287 rtvec_alloc (GET_CODE (pat) == PARALLEL
9289 + num_clobbers_to_add)
9290 : num_clobbers_to_add + 1));
9292 if (GET_CODE (pat) == PARALLEL)
9293 for (i = 0; i < XVECLEN (pat, 0); i++)
9294 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9296 XVECEXP (newpat, 0, 0) = pat;
9298 add_clobbers (newpat, insn_code_number);
9300 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9301 i < XVECLEN (newpat, 0); i++)
9303 if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
9304 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9306 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9307 XEXP (XVECEXP (newpat, 0, i), 0), notes);
9315 return insn_code_number;
9318 /* Like gen_lowpart_general but for use by combine. In combine it
9319 is not possible to create any new pseudoregs. However, it is
9320 safe to create invalid memory addresses, because combine will
9321 try to recognize them and all they will do is make the combine
9324 If for some reason this cannot do its job, an rtx
9325 (clobber (const_int 0)) is returned.
9326 An insn containing that will not be recognized. */
9329 gen_lowpart_for_combine (enum machine_mode mode, rtx x)
9333 if (GET_MODE (x) == mode)
9336 /* Return identity if this is a CONST or symbolic
9339 && (GET_CODE (x) == CONST
9340 || GET_CODE (x) == SYMBOL_REF
9341 || GET_CODE (x) == LABEL_REF))
9344 /* We can only support MODE being wider than a word if X is a
9345 constant integer or has a mode the same size. */
9347 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
9348 && ! ((GET_MODE (x) == VOIDmode
9349 && (GET_CODE (x) == CONST_INT
9350 || GET_CODE (x) == CONST_DOUBLE))
9351 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
9352 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9354 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9355 won't know what to do. So we will strip off the SUBREG here and
9356 process normally. */
9357 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
9360 if (GET_MODE (x) == mode)
9364 result = gen_lowpart_common (mode, x);
9365 #ifdef CANNOT_CHANGE_MODE_CLASS
9367 && GET_CODE (result) == SUBREG
9368 && REG_P (SUBREG_REG (result))
9369 && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER)
9370 bitmap_set_bit (&subregs_of_mode, REGNO (SUBREG_REG (result))
9372 + GET_MODE (result));
9378 if (GET_CODE (x) == MEM)
9382 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9384 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9385 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9387 /* If we want to refer to something bigger than the original memref,
9388 generate a paradoxical subreg instead. That will force a reload
9389 of the original memref X. */
9390 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
9391 return gen_rtx_SUBREG (mode, x, 0);
9393 if (WORDS_BIG_ENDIAN)
9394 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
9395 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
9397 if (BYTES_BIG_ENDIAN)
9399 /* Adjust the address so that the address-after-the-data is
9401 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
9402 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
9405 return adjust_address_nv (x, mode, offset);
9408 /* If X is a comparison operator, rewrite it in a new mode. This
9409 probably won't match, but may allow further simplifications. */
9410 else if (COMPARISON_P (x))
9411 return gen_rtx_fmt_ee (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
9413 /* If we couldn't simplify X any other way, just enclose it in a
9414 SUBREG. Normally, this SUBREG won't match, but some patterns may
9415 include an explicit SUBREG or we may simplify it further in combine. */
9420 enum machine_mode sub_mode = GET_MODE (x);
9422 offset = subreg_lowpart_offset (mode, sub_mode);
9423 if (sub_mode == VOIDmode)
9425 sub_mode = int_mode_for_mode (mode);
9426 x = gen_lowpart_common (sub_mode, x);
9428 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
9430 res = simplify_gen_subreg (mode, x, sub_mode, offset);
9433 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9437 /* These routines make binary and unary operations by first seeing if they
9438 fold; if not, a new expression is allocated. */
9441 gen_binary (enum rtx_code code, enum machine_mode mode, rtx op0, rtx op1)
9446 if (GET_CODE (op0) == CLOBBER)
9448 else if (GET_CODE (op1) == CLOBBER)
9451 if (GET_RTX_CLASS (code) == RTX_COMM_ARITH
9452 && swap_commutative_operands_p (op0, op1))
9453 tem = op0, op0 = op1, op1 = tem;
9455 if (GET_RTX_CLASS (code) == RTX_COMPARE
9456 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
9458 enum machine_mode op_mode = GET_MODE (op0);
9460 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
9461 just (REL_OP X Y). */
9462 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
9464 op1 = XEXP (op0, 1);
9465 op0 = XEXP (op0, 0);
9466 op_mode = GET_MODE (op0);
9469 if (op_mode == VOIDmode)
9470 op_mode = GET_MODE (op1);
9471 result = simplify_relational_operation (code, mode, op_mode, op0, op1);
9474 result = simplify_binary_operation (code, mode, op0, op1);
9479 /* Put complex operands first and constants second. */
9480 if (GET_RTX_CLASS (code) == RTX_COMM_ARITH
9481 && swap_commutative_operands_p (op0, op1))
9482 return gen_rtx_fmt_ee (code, mode, op1, op0);
9484 /* If we are turning off bits already known off in OP0, we need not do
9486 else if (code == AND && GET_CODE (op1) == CONST_INT
9487 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9488 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
9491 return gen_rtx_fmt_ee (code, mode, op0, op1);
9494 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9495 comparison code that will be tested.
9497 The result is a possibly different comparison code to use. *POP0 and
9498 *POP1 may be updated.
9500 It is possible that we might detect that a comparison is either always
9501 true or always false. However, we do not perform general constant
9502 folding in combine, so this knowledge isn't useful. Such tautologies
9503 should have been detected earlier. Hence we ignore all such cases. */
9505 static enum rtx_code
9506 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
9512 enum machine_mode mode, tmode;
9514 /* Try a few ways of applying the same transformation to both operands. */
9517 #ifndef WORD_REGISTER_OPERATIONS
9518 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9519 so check specially. */
9520 if (code != GTU && code != GEU && code != LTU && code != LEU
9521 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9522 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9523 && GET_CODE (XEXP (op1, 0)) == ASHIFT
9524 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9525 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9526 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9527 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9528 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9529 && XEXP (op0, 1) == XEXP (op1, 1)
9530 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
9531 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
9532 && (INTVAL (XEXP (op0, 1))
9533 == (GET_MODE_BITSIZE (GET_MODE (op0))
9535 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9537 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9538 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9542 /* If both operands are the same constant shift, see if we can ignore the
9543 shift. We can if the shift is a rotate or if the bits shifted out of
9544 this shift are known to be zero for both inputs and if the type of
9545 comparison is compatible with the shift. */
9546 if (GET_CODE (op0) == GET_CODE (op1)
9547 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9548 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
9549 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
9550 && (code != GT && code != LT && code != GE && code != LE))
9551 || (GET_CODE (op0) == ASHIFTRT
9552 && (code != GTU && code != LTU
9553 && code != GEU && code != LEU)))
9554 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9555 && INTVAL (XEXP (op0, 1)) >= 0
9556 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9557 && XEXP (op0, 1) == XEXP (op1, 1))
9559 enum machine_mode mode = GET_MODE (op0);
9560 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9561 int shift_count = INTVAL (XEXP (op0, 1));
9563 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
9564 mask &= (mask >> shift_count) << shift_count;
9565 else if (GET_CODE (op0) == ASHIFT)
9566 mask = (mask & (mask << shift_count)) >> shift_count;
9568 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
9569 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
9570 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
9575 /* If both operands are AND's of a paradoxical SUBREG by constant, the
9576 SUBREGs are of the same mode, and, in both cases, the AND would
9577 be redundant if the comparison was done in the narrower mode,
9578 do the comparison in the narrower mode (e.g., we are AND'ing with 1
9579 and the operand's possibly nonzero bits are 0xffffff01; in that case
9580 if we only care about QImode, we don't need the AND). This case
9581 occurs if the output mode of an scc insn is not SImode and
9582 STORE_FLAG_VALUE == 1 (e.g., the 386).
9584 Similarly, check for a case where the AND's are ZERO_EXTEND
9585 operations from some narrower mode even though a SUBREG is not
9588 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
9589 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9590 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
9592 rtx inner_op0 = XEXP (op0, 0);
9593 rtx inner_op1 = XEXP (op1, 0);
9594 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
9595 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
9598 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
9599 && (GET_MODE_SIZE (GET_MODE (inner_op0))
9600 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
9601 && (GET_MODE (SUBREG_REG (inner_op0))
9602 == GET_MODE (SUBREG_REG (inner_op1)))
9603 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
9604 <= HOST_BITS_PER_WIDE_INT)
9605 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
9606 GET_MODE (SUBREG_REG (inner_op0)))))
9607 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
9608 GET_MODE (SUBREG_REG (inner_op1))))))
9610 op0 = SUBREG_REG (inner_op0);
9611 op1 = SUBREG_REG (inner_op1);
9613 /* The resulting comparison is always unsigned since we masked
9614 off the original sign bit. */
9615 code = unsigned_condition (code);
9621 for (tmode = GET_CLASS_NARROWEST_MODE
9622 (GET_MODE_CLASS (GET_MODE (op0)));
9623 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
9624 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
9626 op0 = gen_lowpart (tmode, inner_op0);
9627 op1 = gen_lowpart (tmode, inner_op1);
9628 code = unsigned_condition (code);
9637 /* If both operands are NOT, we can strip off the outer operation
9638 and adjust the comparison code for swapped operands; similarly for
9639 NEG, except that this must be an equality comparison. */
9640 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
9641 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
9642 && (code == EQ || code == NE)))
9643 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
9649 /* If the first operand is a constant, swap the operands and adjust the
9650 comparison code appropriately, but don't do this if the second operand
9651 is already a constant integer. */
9652 if (swap_commutative_operands_p (op0, op1))
9654 tem = op0, op0 = op1, op1 = tem;
9655 code = swap_condition (code);
9658 /* We now enter a loop during which we will try to simplify the comparison.
9659 For the most part, we only are concerned with comparisons with zero,
9660 but some things may really be comparisons with zero but not start
9661 out looking that way. */
9663 while (GET_CODE (op1) == CONST_INT)
9665 enum machine_mode mode = GET_MODE (op0);
9666 unsigned int mode_width = GET_MODE_BITSIZE (mode);
9667 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9668 int equality_comparison_p;
9669 int sign_bit_comparison_p;
9670 int unsigned_comparison_p;
9671 HOST_WIDE_INT const_op;
9673 /* We only want to handle integral modes. This catches VOIDmode,
9674 CCmode, and the floating-point modes. An exception is that we
9675 can handle VOIDmode if OP0 is a COMPARE or a comparison
9678 if (GET_MODE_CLASS (mode) != MODE_INT
9679 && ! (mode == VOIDmode
9680 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
9683 /* Get the constant we are comparing against and turn off all bits
9684 not on in our mode. */
9685 const_op = INTVAL (op1);
9686 if (mode != VOIDmode)
9687 const_op = trunc_int_for_mode (const_op, mode);
9688 op1 = GEN_INT (const_op);
9690 /* If we are comparing against a constant power of two and the value
9691 being compared can only have that single bit nonzero (e.g., it was
9692 `and'ed with that bit), we can replace this with a comparison
9695 && (code == EQ || code == NE || code == GE || code == GEU
9696 || code == LT || code == LTU)
9697 && mode_width <= HOST_BITS_PER_WIDE_INT
9698 && exact_log2 (const_op) >= 0
9699 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
9701 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
9702 op1 = const0_rtx, const_op = 0;
9705 /* Similarly, if we are comparing a value known to be either -1 or
9706 0 with -1, change it to the opposite comparison against zero. */
9709 && (code == EQ || code == NE || code == GT || code == LE
9710 || code == GEU || code == LTU)
9711 && num_sign_bit_copies (op0, mode) == mode_width)
9713 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
9714 op1 = const0_rtx, const_op = 0;
9717 /* Do some canonicalizations based on the comparison code. We prefer
9718 comparisons against zero and then prefer equality comparisons.
9719 If we can reduce the size of a constant, we will do that too. */
9724 /* < C is equivalent to <= (C - 1) */
9728 op1 = GEN_INT (const_op);
9730 /* ... fall through to LE case below. */
9736 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
9740 op1 = GEN_INT (const_op);
9744 /* If we are doing a <= 0 comparison on a value known to have
9745 a zero sign bit, we can replace this with == 0. */
9746 else if (const_op == 0
9747 && mode_width <= HOST_BITS_PER_WIDE_INT
9748 && (nonzero_bits (op0, mode)
9749 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9754 /* >= C is equivalent to > (C - 1). */
9758 op1 = GEN_INT (const_op);
9760 /* ... fall through to GT below. */
9766 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
9770 op1 = GEN_INT (const_op);
9774 /* If we are doing a > 0 comparison on a value known to have
9775 a zero sign bit, we can replace this with != 0. */
9776 else if (const_op == 0
9777 && mode_width <= HOST_BITS_PER_WIDE_INT
9778 && (nonzero_bits (op0, mode)
9779 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9784 /* < C is equivalent to <= (C - 1). */
9788 op1 = GEN_INT (const_op);
9790 /* ... fall through ... */
9793 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
9794 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9795 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9797 const_op = 0, op1 = const0_rtx;
9805 /* unsigned <= 0 is equivalent to == 0 */
9809 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
9810 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9811 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9813 const_op = 0, op1 = const0_rtx;
9819 /* >= C is equivalent to < (C - 1). */
9823 op1 = GEN_INT (const_op);
9825 /* ... fall through ... */
9828 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
9829 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9830 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9832 const_op = 0, op1 = const0_rtx;
9840 /* unsigned > 0 is equivalent to != 0 */
9844 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
9845 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9846 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9848 const_op = 0, op1 = const0_rtx;
9857 /* Compute some predicates to simplify code below. */
9859 equality_comparison_p = (code == EQ || code == NE);
9860 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
9861 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
9864 /* If this is a sign bit comparison and we can do arithmetic in
9865 MODE, say that we will only be needing the sign bit of OP0. */
9866 if (sign_bit_comparison_p
9867 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9868 op0 = force_to_mode (op0, mode,
9870 << (GET_MODE_BITSIZE (mode) - 1)),
9873 /* Now try cases based on the opcode of OP0. If none of the cases
9874 does a "continue", we exit this loop immediately after the
9877 switch (GET_CODE (op0))
9880 /* If we are extracting a single bit from a variable position in
9881 a constant that has only a single bit set and are comparing it
9882 with zero, we can convert this into an equality comparison
9883 between the position and the location of the single bit. */
9884 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
9885 have already reduced the shift count modulo the word size. */
9886 if (!SHIFT_COUNT_TRUNCATED
9887 && GET_CODE (XEXP (op0, 0)) == CONST_INT
9888 && XEXP (op0, 1) == const1_rtx
9889 && equality_comparison_p && const_op == 0
9890 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
9892 if (BITS_BIG_ENDIAN)
9894 enum machine_mode new_mode
9895 = mode_for_extraction (EP_extzv, 1);
9896 if (new_mode == MAX_MACHINE_MODE)
9897 i = BITS_PER_WORD - 1 - i;
9901 i = (GET_MODE_BITSIZE (mode) - 1 - i);
9905 op0 = XEXP (op0, 2);
9909 /* Result is nonzero iff shift count is equal to I. */
9910 code = reverse_condition (code);
9914 /* ... fall through ... */
9917 tem = expand_compound_operation (op0);
9926 /* If testing for equality, we can take the NOT of the constant. */
9927 if (equality_comparison_p
9928 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
9930 op0 = XEXP (op0, 0);
9935 /* If just looking at the sign bit, reverse the sense of the
9937 if (sign_bit_comparison_p)
9939 op0 = XEXP (op0, 0);
9940 code = (code == GE ? LT : GE);
9946 /* If testing for equality, we can take the NEG of the constant. */
9947 if (equality_comparison_p
9948 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
9950 op0 = XEXP (op0, 0);
9955 /* The remaining cases only apply to comparisons with zero. */
9959 /* When X is ABS or is known positive,
9960 (neg X) is < 0 if and only if X != 0. */
9962 if (sign_bit_comparison_p
9963 && (GET_CODE (XEXP (op0, 0)) == ABS
9964 || (mode_width <= HOST_BITS_PER_WIDE_INT
9965 && (nonzero_bits (XEXP (op0, 0), mode)
9966 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
9968 op0 = XEXP (op0, 0);
9969 code = (code == LT ? NE : EQ);
9973 /* If we have NEG of something whose two high-order bits are the
9974 same, we know that "(-a) < 0" is equivalent to "a > 0". */
9975 if (num_sign_bit_copies (op0, mode) >= 2)
9977 op0 = XEXP (op0, 0);
9978 code = swap_condition (code);
9984 /* If we are testing equality and our count is a constant, we
9985 can perform the inverse operation on our RHS. */
9986 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
9987 && (tem = simplify_binary_operation (ROTATERT, mode,
9988 op1, XEXP (op0, 1))) != 0)
9990 op0 = XEXP (op0, 0);
9995 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
9996 a particular bit. Convert it to an AND of a constant of that
9997 bit. This will be converted into a ZERO_EXTRACT. */
9998 if (const_op == 0 && sign_bit_comparison_p
9999 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10000 && mode_width <= HOST_BITS_PER_WIDE_INT)
10002 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10005 - INTVAL (XEXP (op0, 1)))));
10006 code = (code == LT ? NE : EQ);
10010 /* Fall through. */
10013 /* ABS is ignorable inside an equality comparison with zero. */
10014 if (const_op == 0 && equality_comparison_p)
10016 op0 = XEXP (op0, 0);
10022 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10023 to (compare FOO CONST) if CONST fits in FOO's mode and we
10024 are either testing inequality or have an unsigned comparison
10025 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10026 if (! unsigned_comparison_p
10027 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10028 <= HOST_BITS_PER_WIDE_INT)
10029 && ((unsigned HOST_WIDE_INT) const_op
10030 < (((unsigned HOST_WIDE_INT) 1
10031 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
10033 op0 = XEXP (op0, 0);
10039 /* Check for the case where we are comparing A - C1 with C2,
10040 both constants are smaller than 1/2 the maximum positive
10041 value in MODE, and the comparison is equality or unsigned.
10042 In that case, if A is either zero-extended to MODE or has
10043 sufficient sign bits so that the high-order bit in MODE
10044 is a copy of the sign in the inner mode, we can prove that it is
10045 safe to do the operation in the wider mode. This simplifies
10046 many range checks. */
10048 if (mode_width <= HOST_BITS_PER_WIDE_INT
10049 && subreg_lowpart_p (op0)
10050 && GET_CODE (SUBREG_REG (op0)) == PLUS
10051 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
10052 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
10053 && (-INTVAL (XEXP (SUBREG_REG (op0), 1))
10054 < (HOST_WIDE_INT) (GET_MODE_MASK (mode) / 2))
10055 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
10056 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
10057 GET_MODE (SUBREG_REG (op0)))
10058 & ~GET_MODE_MASK (mode))
10059 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
10060 GET_MODE (SUBREG_REG (op0)))
10062 (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10063 - GET_MODE_BITSIZE (mode)))))
10065 op0 = SUBREG_REG (op0);
10069 /* If the inner mode is narrower and we are extracting the low part,
10070 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10071 if (subreg_lowpart_p (op0)
10072 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10073 /* Fall through */ ;
10077 /* ... fall through ... */
10080 if ((unsigned_comparison_p || equality_comparison_p)
10081 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10082 <= HOST_BITS_PER_WIDE_INT)
10083 && ((unsigned HOST_WIDE_INT) const_op
10084 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
10086 op0 = XEXP (op0, 0);
10092 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10093 this for equality comparisons due to pathological cases involving
10095 if (equality_comparison_p
10096 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10097 op1, XEXP (op0, 1))))
10099 op0 = XEXP (op0, 0);
10104 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10105 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10106 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10108 op0 = XEXP (XEXP (op0, 0), 0);
10109 code = (code == LT ? EQ : NE);
10115 /* We used to optimize signed comparisons against zero, but that
10116 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10117 arrive here as equality comparisons, or (GEU, LTU) are
10118 optimized away. No need to special-case them. */
10120 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10121 (eq B (minus A C)), whichever simplifies. We can only do
10122 this for equality comparisons due to pathological cases involving
10124 if (equality_comparison_p
10125 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10126 XEXP (op0, 1), op1)))
10128 op0 = XEXP (op0, 0);
10133 if (equality_comparison_p
10134 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10135 XEXP (op0, 0), op1)))
10137 op0 = XEXP (op0, 1);
10142 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10143 of bits in X minus 1, is one iff X > 0. */
10144 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10145 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10146 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
10148 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10150 op0 = XEXP (op0, 1);
10151 code = (code == GE ? LE : GT);
10157 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10158 if C is zero or B is a constant. */
10159 if (equality_comparison_p
10160 && 0 != (tem = simplify_binary_operation (XOR, mode,
10161 XEXP (op0, 1), op1)))
10163 op0 = XEXP (op0, 0);
10170 case UNEQ: case LTGT:
10171 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
10172 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
10173 case UNORDERED: case ORDERED:
10174 /* We can't do anything if OP0 is a condition code value, rather
10175 than an actual data value. */
10177 || CC0_P (XEXP (op0, 0))
10178 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10181 /* Get the two operands being compared. */
10182 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10183 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10185 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10187 /* Check for the cases where we simply want the result of the
10188 earlier test or the opposite of that result. */
10189 if (code == NE || code == EQ
10190 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10191 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10192 && (STORE_FLAG_VALUE
10193 & (((HOST_WIDE_INT) 1
10194 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10195 && (code == LT || code == GE)))
10197 enum rtx_code new_code;
10198 if (code == LT || code == NE)
10199 new_code = GET_CODE (op0);
10201 new_code = combine_reversed_comparison_code (op0);
10203 if (new_code != UNKNOWN)
10214 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10216 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10217 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10218 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10220 op0 = XEXP (op0, 1);
10221 code = (code == GE ? GT : LE);
10227 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10228 will be converted to a ZERO_EXTRACT later. */
10229 if (const_op == 0 && equality_comparison_p
10230 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10231 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10233 op0 = simplify_and_const_int
10234 (op0, mode, gen_rtx_LSHIFTRT (mode,
10236 XEXP (XEXP (op0, 0), 1)),
10237 (HOST_WIDE_INT) 1);
10241 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10242 zero and X is a comparison and C1 and C2 describe only bits set
10243 in STORE_FLAG_VALUE, we can compare with X. */
10244 if (const_op == 0 && equality_comparison_p
10245 && mode_width <= HOST_BITS_PER_WIDE_INT
10246 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10247 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10248 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10249 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10250 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10252 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10253 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10254 if ((~STORE_FLAG_VALUE & mask) == 0
10255 && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
10256 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10257 && COMPARISON_P (tem))))
10259 op0 = XEXP (XEXP (op0, 0), 0);
10264 /* If we are doing an equality comparison of an AND of a bit equal
10265 to the sign bit, replace this with a LT or GE comparison of
10266 the underlying value. */
10267 if (equality_comparison_p
10269 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10270 && mode_width <= HOST_BITS_PER_WIDE_INT
10271 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10272 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10274 op0 = XEXP (op0, 0);
10275 code = (code == EQ ? GE : LT);
10279 /* If this AND operation is really a ZERO_EXTEND from a narrower
10280 mode, the constant fits within that mode, and this is either an
10281 equality or unsigned comparison, try to do this comparison in
10282 the narrower mode. */
10283 if ((equality_comparison_p || unsigned_comparison_p)
10284 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10285 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10286 & GET_MODE_MASK (mode))
10288 && const_op >> i == 0
10289 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
10291 op0 = gen_lowpart (tmode, XEXP (op0, 0));
10295 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10296 fits in both M1 and M2 and the SUBREG is either paradoxical
10297 or represents the low part, permute the SUBREG and the AND
10299 if (GET_CODE (XEXP (op0, 0)) == SUBREG)
10301 unsigned HOST_WIDE_INT c1;
10302 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
10303 /* Require an integral mode, to avoid creating something like
10305 if (SCALAR_INT_MODE_P (tmode)
10306 /* It is unsafe to commute the AND into the SUBREG if the
10307 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10308 not defined. As originally written the upper bits
10309 have a defined value due to the AND operation.
10310 However, if we commute the AND inside the SUBREG then
10311 they no longer have defined values and the meaning of
10312 the code has been changed. */
10314 #ifdef WORD_REGISTER_OPERATIONS
10315 || (mode_width > GET_MODE_BITSIZE (tmode)
10316 && mode_width <= BITS_PER_WORD)
10318 || (mode_width <= GET_MODE_BITSIZE (tmode)
10319 && subreg_lowpart_p (XEXP (op0, 0))))
10320 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10321 && mode_width <= HOST_BITS_PER_WIDE_INT
10322 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
10323 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
10324 && (c1 & ~GET_MODE_MASK (tmode)) == 0
10326 && c1 != GET_MODE_MASK (tmode))
10328 op0 = gen_binary (AND, tmode,
10329 SUBREG_REG (XEXP (op0, 0)),
10330 gen_int_mode (c1, tmode));
10331 op0 = gen_lowpart (mode, op0);
10336 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
10337 if (const_op == 0 && equality_comparison_p
10338 && XEXP (op0, 1) == const1_rtx
10339 && GET_CODE (XEXP (op0, 0)) == NOT)
10341 op0 = simplify_and_const_int
10342 (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1);
10343 code = (code == NE ? EQ : NE);
10347 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10348 (eq (and (lshiftrt X) 1) 0).
10349 Also handle the case where (not X) is expressed using xor. */
10350 if (const_op == 0 && equality_comparison_p
10351 && XEXP (op0, 1) == const1_rtx
10352 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
10354 rtx shift_op = XEXP (XEXP (op0, 0), 0);
10355 rtx shift_count = XEXP (XEXP (op0, 0), 1);
10357 if (GET_CODE (shift_op) == NOT
10358 || (GET_CODE (shift_op) == XOR
10359 && GET_CODE (XEXP (shift_op, 1)) == CONST_INT
10360 && GET_CODE (shift_count) == CONST_INT
10361 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
10362 && (INTVAL (XEXP (shift_op, 1))
10363 == (HOST_WIDE_INT) 1 << INTVAL (shift_count))))
10365 op0 = simplify_and_const_int
10367 gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count),
10368 (HOST_WIDE_INT) 1);
10369 code = (code == NE ? EQ : NE);
10376 /* If we have (compare (ashift FOO N) (const_int C)) and
10377 the high order N bits of FOO (N+1 if an inequality comparison)
10378 are known to be zero, we can do this by comparing FOO with C
10379 shifted right N bits so long as the low-order N bits of C are
10381 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10382 && INTVAL (XEXP (op0, 1)) >= 0
10383 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10384 < HOST_BITS_PER_WIDE_INT)
10386 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10387 && mode_width <= HOST_BITS_PER_WIDE_INT
10388 && (nonzero_bits (XEXP (op0, 0), mode)
10389 & ~(mask >> (INTVAL (XEXP (op0, 1))
10390 + ! equality_comparison_p))) == 0)
10392 /* We must perform a logical shift, not an arithmetic one,
10393 as we want the top N bits of C to be zero. */
10394 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10396 temp >>= INTVAL (XEXP (op0, 1));
10397 op1 = gen_int_mode (temp, mode);
10398 op0 = XEXP (op0, 0);
10402 /* If we are doing a sign bit comparison, it means we are testing
10403 a particular bit. Convert it to the appropriate AND. */
10404 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10405 && mode_width <= HOST_BITS_PER_WIDE_INT)
10407 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10410 - INTVAL (XEXP (op0, 1)))));
10411 code = (code == LT ? NE : EQ);
10415 /* If this an equality comparison with zero and we are shifting
10416 the low bit to the sign bit, we can convert this to an AND of the
10418 if (const_op == 0 && equality_comparison_p
10419 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10420 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10423 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10424 (HOST_WIDE_INT) 1);
10430 /* If this is an equality comparison with zero, we can do this
10431 as a logical shift, which might be much simpler. */
10432 if (equality_comparison_p && const_op == 0
10433 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10435 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10437 INTVAL (XEXP (op0, 1)));
10441 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10442 do the comparison in a narrower mode. */
10443 if (! unsigned_comparison_p
10444 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10445 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10446 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10447 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10448 MODE_INT, 1)) != BLKmode
10449 && (((unsigned HOST_WIDE_INT) const_op
10450 + (GET_MODE_MASK (tmode) >> 1) + 1)
10451 <= GET_MODE_MASK (tmode)))
10453 op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
10457 /* Likewise if OP0 is a PLUS of a sign extension with a
10458 constant, which is usually represented with the PLUS
10459 between the shifts. */
10460 if (! unsigned_comparison_p
10461 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10462 && GET_CODE (XEXP (op0, 0)) == PLUS
10463 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10464 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
10465 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
10466 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10467 MODE_INT, 1)) != BLKmode
10468 && (((unsigned HOST_WIDE_INT) const_op
10469 + (GET_MODE_MASK (tmode) >> 1) + 1)
10470 <= GET_MODE_MASK (tmode)))
10472 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
10473 rtx add_const = XEXP (XEXP (op0, 0), 1);
10474 rtx new_const = gen_binary (ASHIFTRT, GET_MODE (op0), add_const,
10477 op0 = gen_binary (PLUS, tmode,
10478 gen_lowpart (tmode, inner),
10483 /* ... fall through ... */
10485 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10486 the low order N bits of FOO are known to be zero, we can do this
10487 by comparing FOO with C shifted left N bits so long as no
10488 overflow occurs. */
10489 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10490 && INTVAL (XEXP (op0, 1)) >= 0
10491 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10492 && mode_width <= HOST_BITS_PER_WIDE_INT
10493 && (nonzero_bits (XEXP (op0, 0), mode)
10494 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10495 && (((unsigned HOST_WIDE_INT) const_op
10496 + (GET_CODE (op0) != LSHIFTRT
10497 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
10500 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
10502 /* If the shift was logical, then we must make the condition
10504 if (GET_CODE (op0) == LSHIFTRT)
10505 code = unsigned_condition (code);
10507 const_op <<= INTVAL (XEXP (op0, 1));
10508 op1 = GEN_INT (const_op);
10509 op0 = XEXP (op0, 0);
10513 /* If we are using this shift to extract just the sign bit, we
10514 can replace this with an LT or GE comparison. */
10516 && (equality_comparison_p || sign_bit_comparison_p)
10517 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10518 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10521 op0 = XEXP (op0, 0);
10522 code = (code == NE || code == GT ? LT : GE);
10534 /* Now make any compound operations involved in this comparison. Then,
10535 check for an outmost SUBREG on OP0 that is not doing anything or is
10536 paradoxical. The latter transformation must only be performed when
10537 it is known that the "extra" bits will be the same in op0 and op1 or
10538 that they don't matter. There are three cases to consider:
10540 1. SUBREG_REG (op0) is a register. In this case the bits are don't
10541 care bits and we can assume they have any convenient value. So
10542 making the transformation is safe.
10544 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
10545 In this case the upper bits of op0 are undefined. We should not make
10546 the simplification in that case as we do not know the contents of
10549 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
10550 NIL. In that case we know those bits are zeros or ones. We must
10551 also be sure that they are the same as the upper bits of op1.
10553 We can never remove a SUBREG for a non-equality comparison because
10554 the sign bit is in a different place in the underlying object. */
10556 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10557 op1 = make_compound_operation (op1, SET);
10559 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10560 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10561 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
10562 && (code == NE || code == EQ))
10564 if (GET_MODE_SIZE (GET_MODE (op0))
10565 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
10567 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
10569 if (REG_P (SUBREG_REG (op0)))
10571 op0 = SUBREG_REG (op0);
10572 op1 = gen_lowpart (GET_MODE (op0), op1);
10575 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10576 <= HOST_BITS_PER_WIDE_INT)
10577 && (nonzero_bits (SUBREG_REG (op0),
10578 GET_MODE (SUBREG_REG (op0)))
10579 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
10581 tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
10583 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
10584 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
10585 op0 = SUBREG_REG (op0), op1 = tem;
10589 /* We now do the opposite procedure: Some machines don't have compare
10590 insns in all modes. If OP0's mode is an integer mode smaller than a
10591 word and we can't do a compare in that mode, see if there is a larger
10592 mode for which we can do the compare. There are a number of cases in
10593 which we can use the wider mode. */
10595 mode = GET_MODE (op0);
10596 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10597 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
10598 && ! have_insn_for (COMPARE, mode))
10599 for (tmode = GET_MODE_WIDER_MODE (mode);
10601 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
10602 tmode = GET_MODE_WIDER_MODE (tmode))
10603 if (have_insn_for (COMPARE, tmode))
10607 /* If the only nonzero bits in OP0 and OP1 are those in the
10608 narrower mode and this is an equality or unsigned comparison,
10609 we can use the wider mode. Similarly for sign-extended
10610 values, in which case it is true for all comparisons. */
10611 zero_extended = ((code == EQ || code == NE
10612 || code == GEU || code == GTU
10613 || code == LEU || code == LTU)
10614 && (nonzero_bits (op0, tmode)
10615 & ~GET_MODE_MASK (mode)) == 0
10616 && ((GET_CODE (op1) == CONST_INT
10617 || (nonzero_bits (op1, tmode)
10618 & ~GET_MODE_MASK (mode)) == 0)));
10621 || ((num_sign_bit_copies (op0, tmode)
10622 > (unsigned int) (GET_MODE_BITSIZE (tmode)
10623 - GET_MODE_BITSIZE (mode)))
10624 && (num_sign_bit_copies (op1, tmode)
10625 > (unsigned int) (GET_MODE_BITSIZE (tmode)
10626 - GET_MODE_BITSIZE (mode)))))
10628 /* If OP0 is an AND and we don't have an AND in MODE either,
10629 make a new AND in the proper mode. */
10630 if (GET_CODE (op0) == AND
10631 && !have_insn_for (AND, mode))
10632 op0 = gen_binary (AND, tmode,
10633 gen_lowpart (tmode,
10635 gen_lowpart (tmode,
10638 op0 = gen_lowpart (tmode, op0);
10639 if (zero_extended && GET_CODE (op1) == CONST_INT)
10640 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
10641 op1 = gen_lowpart (tmode, op1);
10645 /* If this is a test for negative, we can make an explicit
10646 test of the sign bit. */
10648 if (op1 == const0_rtx && (code == LT || code == GE)
10649 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10651 op0 = gen_binary (AND, tmode,
10652 gen_lowpart (tmode, op0),
10653 GEN_INT ((HOST_WIDE_INT) 1
10654 << (GET_MODE_BITSIZE (mode) - 1)));
10655 code = (code == LT) ? NE : EQ;
10660 #ifdef CANONICALIZE_COMPARISON
10661 /* If this machine only supports a subset of valid comparisons, see if we
10662 can convert an unsupported one into a supported one. */
10663 CANONICALIZE_COMPARISON (code, op0, op1);
10672 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
10673 searching backward. */
10674 static enum rtx_code
10675 combine_reversed_comparison_code (rtx exp)
10677 enum rtx_code code1 = reversed_comparison_code (exp, NULL);
10680 if (code1 != UNKNOWN
10681 || GET_MODE_CLASS (GET_MODE (XEXP (exp, 0))) != MODE_CC)
10683 /* Otherwise try and find where the condition codes were last set and
10685 x = get_last_value (XEXP (exp, 0));
10686 if (!x || GET_CODE (x) != COMPARE)
10688 return reversed_comparison_code_parts (GET_CODE (exp),
10689 XEXP (x, 0), XEXP (x, 1), NULL);
10692 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
10693 Return NULL_RTX in case we fail to do the reversal. */
10695 reversed_comparison (rtx exp, enum machine_mode mode, rtx op0, rtx op1)
10697 enum rtx_code reversed_code = combine_reversed_comparison_code (exp);
10698 if (reversed_code == UNKNOWN)
10701 return gen_binary (reversed_code, mode, op0, op1);
10704 /* Utility function for following routine. Called when X is part of a value
10705 being stored into last_set_value. Sets last_set_table_tick
10706 for each register mentioned. Similar to mention_regs in cse.c */
10709 update_table_tick (rtx x)
10711 enum rtx_code code = GET_CODE (x);
10712 const char *fmt = GET_RTX_FORMAT (code);
10717 unsigned int regno = REGNO (x);
10718 unsigned int endregno
10719 = regno + (regno < FIRST_PSEUDO_REGISTER
10720 ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
10723 for (r = regno; r < endregno; r++)
10724 reg_stat[r].last_set_table_tick = label_tick;
10729 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10730 /* Note that we can't have an "E" in values stored; see
10731 get_last_value_validate. */
10734 /* Check for identical subexpressions. If x contains
10735 identical subexpression we only have to traverse one of
10737 if (i == 0 && ARITHMETIC_P (x))
10739 /* Note that at this point x1 has already been
10741 rtx x0 = XEXP (x, 0);
10742 rtx x1 = XEXP (x, 1);
10744 /* If x0 and x1 are identical then there is no need to
10749 /* If x0 is identical to a subexpression of x1 then while
10750 processing x1, x0 has already been processed. Thus we
10751 are done with x. */
10752 if (ARITHMETIC_P (x1)
10753 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
10756 /* If x1 is identical to a subexpression of x0 then we
10757 still have to process the rest of x0. */
10758 if (ARITHMETIC_P (x0)
10759 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
10761 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
10766 update_table_tick (XEXP (x, i));
10770 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
10771 are saying that the register is clobbered and we no longer know its
10772 value. If INSN is zero, don't update reg_stat[].last_set; this is
10773 only permitted with VALUE also zero and is used to invalidate the
10777 record_value_for_reg (rtx reg, rtx insn, rtx value)
10779 unsigned int regno = REGNO (reg);
10780 unsigned int endregno
10781 = regno + (regno < FIRST_PSEUDO_REGISTER
10782 ? hard_regno_nregs[regno][GET_MODE (reg)] : 1);
10785 /* If VALUE contains REG and we have a previous value for REG, substitute
10786 the previous value. */
10787 if (value && insn && reg_overlap_mentioned_p (reg, value))
10791 /* Set things up so get_last_value is allowed to see anything set up to
10793 subst_low_cuid = INSN_CUID (insn);
10794 tem = get_last_value (reg);
10796 /* If TEM is simply a binary operation with two CLOBBERs as operands,
10797 it isn't going to be useful and will take a lot of time to process,
10798 so just use the CLOBBER. */
10802 if (ARITHMETIC_P (tem)
10803 && GET_CODE (XEXP (tem, 0)) == CLOBBER
10804 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
10805 tem = XEXP (tem, 0);
10807 value = replace_rtx (copy_rtx (value), reg, tem);
10811 /* For each register modified, show we don't know its value, that
10812 we don't know about its bitwise content, that its value has been
10813 updated, and that we don't know the location of the death of the
10815 for (i = regno; i < endregno; i++)
10818 reg_stat[i].last_set = insn;
10820 reg_stat[i].last_set_value = 0;
10821 reg_stat[i].last_set_mode = 0;
10822 reg_stat[i].last_set_nonzero_bits = 0;
10823 reg_stat[i].last_set_sign_bit_copies = 0;
10824 reg_stat[i].last_death = 0;
10827 /* Mark registers that are being referenced in this value. */
10829 update_table_tick (value);
10831 /* Now update the status of each register being set.
10832 If someone is using this register in this block, set this register
10833 to invalid since we will get confused between the two lives in this
10834 basic block. This makes using this register always invalid. In cse, we
10835 scan the table to invalidate all entries using this register, but this
10836 is too much work for us. */
10838 for (i = regno; i < endregno; i++)
10840 reg_stat[i].last_set_label = label_tick;
10841 if (value && reg_stat[i].last_set_table_tick == label_tick)
10842 reg_stat[i].last_set_invalid = 1;
10844 reg_stat[i].last_set_invalid = 0;
10847 /* The value being assigned might refer to X (like in "x++;"). In that
10848 case, we must replace it with (clobber (const_int 0)) to prevent
10850 if (value && ! get_last_value_validate (&value, insn,
10851 reg_stat[regno].last_set_label, 0))
10853 value = copy_rtx (value);
10854 if (! get_last_value_validate (&value, insn,
10855 reg_stat[regno].last_set_label, 1))
10859 /* For the main register being modified, update the value, the mode, the
10860 nonzero bits, and the number of sign bit copies. */
10862 reg_stat[regno].last_set_value = value;
10866 enum machine_mode mode = GET_MODE (reg);
10867 subst_low_cuid = INSN_CUID (insn);
10868 reg_stat[regno].last_set_mode = mode;
10869 if (GET_MODE_CLASS (mode) == MODE_INT
10870 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10871 mode = nonzero_bits_mode;
10872 reg_stat[regno].last_set_nonzero_bits = nonzero_bits (value, mode);
10873 reg_stat[regno].last_set_sign_bit_copies
10874 = num_sign_bit_copies (value, GET_MODE (reg));
10878 /* Called via note_stores from record_dead_and_set_regs to handle one
10879 SET or CLOBBER in an insn. DATA is the instruction in which the
10880 set is occurring. */
10883 record_dead_and_set_regs_1 (rtx dest, rtx setter, void *data)
10885 rtx record_dead_insn = (rtx) data;
10887 if (GET_CODE (dest) == SUBREG)
10888 dest = SUBREG_REG (dest);
10892 /* If we are setting the whole register, we know its value. Otherwise
10893 show that we don't know the value. We can handle SUBREG in
10895 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
10896 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
10897 else if (GET_CODE (setter) == SET
10898 && GET_CODE (SET_DEST (setter)) == SUBREG
10899 && SUBREG_REG (SET_DEST (setter)) == dest
10900 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
10901 && subreg_lowpart_p (SET_DEST (setter)))
10902 record_value_for_reg (dest, record_dead_insn,
10903 gen_lowpart (GET_MODE (dest),
10904 SET_SRC (setter)));
10906 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
10908 else if (GET_CODE (dest) == MEM
10909 /* Ignore pushes, they clobber nothing. */
10910 && ! push_operand (dest, GET_MODE (dest)))
10911 mem_last_set = INSN_CUID (record_dead_insn);
10914 /* Update the records of when each REG was most recently set or killed
10915 for the things done by INSN. This is the last thing done in processing
10916 INSN in the combiner loop.
10918 We update reg_stat[], in particular fields last_set, last_set_value,
10919 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
10920 last_death, and also the similar information mem_last_set (which insn
10921 most recently modified memory) and last_call_cuid (which insn was the
10922 most recent subroutine call). */
10925 record_dead_and_set_regs (rtx insn)
10930 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
10932 if (REG_NOTE_KIND (link) == REG_DEAD
10933 && REG_P (XEXP (link, 0)))
10935 unsigned int regno = REGNO (XEXP (link, 0));
10936 unsigned int endregno
10937 = regno + (regno < FIRST_PSEUDO_REGISTER
10938 ? hard_regno_nregs[regno][GET_MODE (XEXP (link, 0))]
10941 for (i = regno; i < endregno; i++)
10942 reg_stat[i].last_death = insn;
10944 else if (REG_NOTE_KIND (link) == REG_INC)
10945 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
10948 if (GET_CODE (insn) == CALL_INSN)
10950 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
10951 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
10953 reg_stat[i].last_set_value = 0;
10954 reg_stat[i].last_set_mode = 0;
10955 reg_stat[i].last_set_nonzero_bits = 0;
10956 reg_stat[i].last_set_sign_bit_copies = 0;
10957 reg_stat[i].last_death = 0;
10960 last_call_cuid = mem_last_set = INSN_CUID (insn);
10962 /* Don't bother recording what this insn does. It might set the
10963 return value register, but we can't combine into a call
10964 pattern anyway, so there's no point trying (and it may cause
10965 a crash, if e.g. we wind up asking for last_set_value of a
10966 SUBREG of the return value register). */
10970 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
10973 /* If a SUBREG has the promoted bit set, it is in fact a property of the
10974 register present in the SUBREG, so for each such SUBREG go back and
10975 adjust nonzero and sign bit information of the registers that are
10976 known to have some zero/sign bits set.
10978 This is needed because when combine blows the SUBREGs away, the
10979 information on zero/sign bits is lost and further combines can be
10980 missed because of that. */
10983 record_promoted_value (rtx insn, rtx subreg)
10986 unsigned int regno = REGNO (SUBREG_REG (subreg));
10987 enum machine_mode mode = GET_MODE (subreg);
10989 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
10992 for (links = LOG_LINKS (insn); links;)
10994 insn = XEXP (links, 0);
10995 set = single_set (insn);
10997 if (! set || !REG_P (SET_DEST (set))
10998 || REGNO (SET_DEST (set)) != regno
10999 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11001 links = XEXP (links, 1);
11005 if (reg_stat[regno].last_set == insn)
11007 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11008 reg_stat[regno].last_set_nonzero_bits &= GET_MODE_MASK (mode);
11011 if (REG_P (SET_SRC (set)))
11013 regno = REGNO (SET_SRC (set));
11014 links = LOG_LINKS (insn);
11021 /* Scan X for promoted SUBREGs. For each one found,
11022 note what it implies to the registers used in it. */
11025 check_promoted_subreg (rtx insn, rtx x)
11027 if (GET_CODE (x) == SUBREG && SUBREG_PROMOTED_VAR_P (x)
11028 && REG_P (SUBREG_REG (x)))
11029 record_promoted_value (insn, x);
11032 const char *format = GET_RTX_FORMAT (GET_CODE (x));
11035 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11039 check_promoted_subreg (insn, XEXP (x, i));
11043 if (XVEC (x, i) != 0)
11044 for (j = 0; j < XVECLEN (x, i); j++)
11045 check_promoted_subreg (insn, XVECEXP (x, i, j));
11051 /* Utility routine for the following function. Verify that all the registers
11052 mentioned in *LOC are valid when *LOC was part of a value set when
11053 label_tick == TICK. Return 0 if some are not.
11055 If REPLACE is nonzero, replace the invalid reference with
11056 (clobber (const_int 0)) and return 1. This replacement is useful because
11057 we often can get useful information about the form of a value (e.g., if
11058 it was produced by a shift that always produces -1 or 0) even though
11059 we don't know exactly what registers it was produced from. */
11062 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
11065 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11066 int len = GET_RTX_LENGTH (GET_CODE (x));
11071 unsigned int regno = REGNO (x);
11072 unsigned int endregno
11073 = regno + (regno < FIRST_PSEUDO_REGISTER
11074 ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
11077 for (j = regno; j < endregno; j++)
11078 if (reg_stat[j].last_set_invalid
11079 /* If this is a pseudo-register that was only set once and not
11080 live at the beginning of the function, it is always valid. */
11081 || (! (regno >= FIRST_PSEUDO_REGISTER
11082 && REG_N_SETS (regno) == 1
11083 && (! REGNO_REG_SET_P
11084 (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, regno)))
11085 && reg_stat[j].last_set_label > tick))
11088 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11094 /* If this is a memory reference, make sure that there were
11095 no stores after it that might have clobbered the value. We don't
11096 have alias info, so we assume any store invalidates it. */
11097 else if (GET_CODE (x) == MEM && ! RTX_UNCHANGING_P (x)
11098 && INSN_CUID (insn) <= mem_last_set)
11101 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11105 for (i = 0; i < len; i++)
11109 /* Check for identical subexpressions. If x contains
11110 identical subexpression we only have to traverse one of
11112 if (i == 1 && ARITHMETIC_P (x))
11114 /* Note that at this point x0 has already been checked
11115 and found valid. */
11116 rtx x0 = XEXP (x, 0);
11117 rtx x1 = XEXP (x, 1);
11119 /* If x0 and x1 are identical then x is also valid. */
11123 /* If x1 is identical to a subexpression of x0 then
11124 while checking x0, x1 has already been checked. Thus
11125 it is valid and so as x. */
11126 if (ARITHMETIC_P (x0)
11127 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11130 /* If x0 is identical to a subexpression of x1 then x is
11131 valid iff the rest of x1 is valid. */
11132 if (ARITHMETIC_P (x1)
11133 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11135 get_last_value_validate (&XEXP (x1,
11136 x0 == XEXP (x1, 0) ? 1 : 0),
11137 insn, tick, replace);
11140 if (get_last_value_validate (&XEXP (x, i), insn, tick,
11144 /* Don't bother with these. They shouldn't occur anyway. */
11145 else if (fmt[i] == 'E')
11149 /* If we haven't found a reason for it to be invalid, it is valid. */
11153 /* Get the last value assigned to X, if known. Some registers
11154 in the value may be replaced with (clobber (const_int 0)) if their value
11155 is known longer known reliably. */
11158 get_last_value (rtx x)
11160 unsigned int regno;
11163 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11164 then convert it to the desired mode. If this is a paradoxical SUBREG,
11165 we cannot predict what values the "extra" bits might have. */
11166 if (GET_CODE (x) == SUBREG
11167 && subreg_lowpart_p (x)
11168 && (GET_MODE_SIZE (GET_MODE (x))
11169 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11170 && (value = get_last_value (SUBREG_REG (x))) != 0)
11171 return gen_lowpart (GET_MODE (x), value);
11177 value = reg_stat[regno].last_set_value;
11179 /* If we don't have a value, or if it isn't for this basic block and
11180 it's either a hard register, set more than once, or it's a live
11181 at the beginning of the function, return 0.
11183 Because if it's not live at the beginning of the function then the reg
11184 is always set before being used (is never used without being set).
11185 And, if it's set only once, and it's always set before use, then all
11186 uses must have the same last value, even if it's not from this basic
11190 || (reg_stat[regno].last_set_label != label_tick
11191 && (regno < FIRST_PSEUDO_REGISTER
11192 || REG_N_SETS (regno) != 1
11193 || (REGNO_REG_SET_P
11194 (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, regno)))))
11197 /* If the value was set in a later insn than the ones we are processing,
11198 we can't use it even if the register was only set once. */
11199 if (INSN_CUID (reg_stat[regno].last_set) >= subst_low_cuid)
11202 /* If the value has all its registers valid, return it. */
11203 if (get_last_value_validate (&value, reg_stat[regno].last_set,
11204 reg_stat[regno].last_set_label, 0))
11207 /* Otherwise, make a copy and replace any invalid register with
11208 (clobber (const_int 0)). If that fails for some reason, return 0. */
11210 value = copy_rtx (value);
11211 if (get_last_value_validate (&value, reg_stat[regno].last_set,
11212 reg_stat[regno].last_set_label, 1))
11218 /* Return nonzero if expression X refers to a REG or to memory
11219 that is set in an instruction more recent than FROM_CUID. */
11222 use_crosses_set_p (rtx x, int from_cuid)
11226 enum rtx_code code = GET_CODE (x);
11230 unsigned int regno = REGNO (x);
11231 unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER
11232 ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
11234 #ifdef PUSH_ROUNDING
11235 /* Don't allow uses of the stack pointer to be moved,
11236 because we don't know whether the move crosses a push insn. */
11237 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11240 for (; regno < endreg; regno++)
11241 if (reg_stat[regno].last_set
11242 && INSN_CUID (reg_stat[regno].last_set) > from_cuid)
11247 if (code == MEM && mem_last_set > from_cuid)
11250 fmt = GET_RTX_FORMAT (code);
11252 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11257 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11258 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11261 else if (fmt[i] == 'e'
11262 && use_crosses_set_p (XEXP (x, i), from_cuid))
11268 /* Define three variables used for communication between the following
11271 static unsigned int reg_dead_regno, reg_dead_endregno;
11272 static int reg_dead_flag;
11274 /* Function called via note_stores from reg_dead_at_p.
11276 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11277 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11280 reg_dead_at_p_1 (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
11282 unsigned int regno, endregno;
11287 regno = REGNO (dest);
11288 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11289 ? hard_regno_nregs[regno][GET_MODE (dest)] : 1);
11291 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11292 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11295 /* Return nonzero if REG is known to be dead at INSN.
11297 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11298 referencing REG, it is dead. If we hit a SET referencing REG, it is
11299 live. Otherwise, see if it is live or dead at the start of the basic
11300 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11301 must be assumed to be always live. */
11304 reg_dead_at_p (rtx reg, rtx insn)
11309 /* Set variables for reg_dead_at_p_1. */
11310 reg_dead_regno = REGNO (reg);
11311 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
11312 ? hard_regno_nregs[reg_dead_regno]
11318 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
11319 we allow the machine description to decide whether use-and-clobber
11320 patterns are OK. */
11321 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11323 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11324 if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
11328 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11329 beginning of function. */
11330 for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER;
11331 insn = prev_nonnote_insn (insn))
11333 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11335 return reg_dead_flag == 1 ? 1 : 0;
11337 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11341 /* Get the basic block that we were in. */
11343 block = ENTRY_BLOCK_PTR->next_bb;
11346 FOR_EACH_BB (block)
11347 if (insn == BB_HEAD (block))
11350 if (block == EXIT_BLOCK_PTR)
11354 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11355 if (REGNO_REG_SET_P (block->global_live_at_start, i))
11361 /* Note hard registers in X that are used. This code is similar to
11362 that in flow.c, but much simpler since we don't care about pseudos. */
11365 mark_used_regs_combine (rtx x)
11367 RTX_CODE code = GET_CODE (x);
11368 unsigned int regno;
11381 case ADDR_DIFF_VEC:
11384 /* CC0 must die in the insn after it is set, so we don't need to take
11385 special note of it here. */
11391 /* If we are clobbering a MEM, mark any hard registers inside the
11392 address as used. */
11393 if (GET_CODE (XEXP (x, 0)) == MEM)
11394 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11399 /* A hard reg in a wide mode may really be multiple registers.
11400 If so, mark all of them just like the first. */
11401 if (regno < FIRST_PSEUDO_REGISTER)
11403 unsigned int endregno, r;
11405 /* None of this applies to the stack, frame or arg pointers. */
11406 if (regno == STACK_POINTER_REGNUM
11407 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11408 || regno == HARD_FRAME_POINTER_REGNUM
11410 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11411 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11413 || regno == FRAME_POINTER_REGNUM)
11416 endregno = regno + hard_regno_nregs[regno][GET_MODE (x)];
11417 for (r = regno; r < endregno; r++)
11418 SET_HARD_REG_BIT (newpat_used_regs, r);
11424 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11426 rtx testreg = SET_DEST (x);
11428 while (GET_CODE (testreg) == SUBREG
11429 || GET_CODE (testreg) == ZERO_EXTRACT
11430 || GET_CODE (testreg) == SIGN_EXTRACT
11431 || GET_CODE (testreg) == STRICT_LOW_PART)
11432 testreg = XEXP (testreg, 0);
11434 if (GET_CODE (testreg) == MEM)
11435 mark_used_regs_combine (XEXP (testreg, 0));
11437 mark_used_regs_combine (SET_SRC (x));
11445 /* Recursively scan the operands of this expression. */
11448 const char *fmt = GET_RTX_FORMAT (code);
11450 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11453 mark_used_regs_combine (XEXP (x, i));
11454 else if (fmt[i] == 'E')
11458 for (j = 0; j < XVECLEN (x, i); j++)
11459 mark_used_regs_combine (XVECEXP (x, i, j));
11465 /* Remove register number REGNO from the dead registers list of INSN.
11467 Return the note used to record the death, if there was one. */
11470 remove_death (unsigned int regno, rtx insn)
11472 rtx note = find_regno_note (insn, REG_DEAD, regno);
11476 REG_N_DEATHS (regno)--;
11477 remove_note (insn, note);
11483 /* For each register (hardware or pseudo) used within expression X, if its
11484 death is in an instruction with cuid between FROM_CUID (inclusive) and
11485 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11486 list headed by PNOTES.
11488 That said, don't move registers killed by maybe_kill_insn.
11490 This is done when X is being merged by combination into TO_INSN. These
11491 notes will then be distributed as needed. */
11494 move_deaths (rtx x, rtx maybe_kill_insn, int from_cuid, rtx to_insn,
11499 enum rtx_code code = GET_CODE (x);
11503 unsigned int regno = REGNO (x);
11504 rtx where_dead = reg_stat[regno].last_death;
11505 rtx before_dead, after_dead;
11507 /* Don't move the register if it gets killed in between from and to. */
11508 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11509 && ! reg_referenced_p (x, maybe_kill_insn))
11512 /* WHERE_DEAD could be a USE insn made by combine, so first we
11513 make sure that we have insns with valid INSN_CUID values. */
11514 before_dead = where_dead;
11515 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11516 before_dead = PREV_INSN (before_dead);
11518 after_dead = where_dead;
11519 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11520 after_dead = NEXT_INSN (after_dead);
11522 if (before_dead && after_dead
11523 && INSN_CUID (before_dead) >= from_cuid
11524 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
11525 || (where_dead != after_dead
11526 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
11528 rtx note = remove_death (regno, where_dead);
11530 /* It is possible for the call above to return 0. This can occur
11531 when last_death points to I2 or I1 that we combined with.
11532 In that case make a new note.
11534 We must also check for the case where X is a hard register
11535 and NOTE is a death note for a range of hard registers
11536 including X. In that case, we must put REG_DEAD notes for
11537 the remaining registers in place of NOTE. */
11539 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11540 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11541 > GET_MODE_SIZE (GET_MODE (x))))
11543 unsigned int deadregno = REGNO (XEXP (note, 0));
11544 unsigned int deadend
11545 = (deadregno + hard_regno_nregs[deadregno]
11546 [GET_MODE (XEXP (note, 0))]);
11547 unsigned int ourend
11548 = regno + hard_regno_nregs[regno][GET_MODE (x)];
11551 for (i = deadregno; i < deadend; i++)
11552 if (i < regno || i >= ourend)
11553 REG_NOTES (where_dead)
11554 = gen_rtx_EXPR_LIST (REG_DEAD,
11556 REG_NOTES (where_dead));
11559 /* If we didn't find any note, or if we found a REG_DEAD note that
11560 covers only part of the given reg, and we have a multi-reg hard
11561 register, then to be safe we must check for REG_DEAD notes
11562 for each register other than the first. They could have
11563 their own REG_DEAD notes lying around. */
11564 else if ((note == 0
11566 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11567 < GET_MODE_SIZE (GET_MODE (x)))))
11568 && regno < FIRST_PSEUDO_REGISTER
11569 && hard_regno_nregs[regno][GET_MODE (x)] > 1)
11571 unsigned int ourend
11572 = regno + hard_regno_nregs[regno][GET_MODE (x)];
11573 unsigned int i, offset;
11577 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
11581 for (i = regno + offset; i < ourend; i++)
11582 move_deaths (regno_reg_rtx[i],
11583 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
11586 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
11588 XEXP (note, 1) = *pnotes;
11592 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
11594 REG_N_DEATHS (regno)++;
11600 else if (GET_CODE (x) == SET)
11602 rtx dest = SET_DEST (x);
11604 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
11606 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11607 that accesses one word of a multi-word item, some
11608 piece of everything register in the expression is used by
11609 this insn, so remove any old death. */
11610 /* ??? So why do we test for equality of the sizes? */
11612 if (GET_CODE (dest) == ZERO_EXTRACT
11613 || GET_CODE (dest) == STRICT_LOW_PART
11614 || (GET_CODE (dest) == SUBREG
11615 && (((GET_MODE_SIZE (GET_MODE (dest))
11616 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
11617 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
11618 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
11620 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
11624 /* If this is some other SUBREG, we know it replaces the entire
11625 value, so use that as the destination. */
11626 if (GET_CODE (dest) == SUBREG)
11627 dest = SUBREG_REG (dest);
11629 /* If this is a MEM, adjust deaths of anything used in the address.
11630 For a REG (the only other possibility), the entire value is
11631 being replaced so the old value is not used in this insn. */
11633 if (GET_CODE (dest) == MEM)
11634 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
11639 else if (GET_CODE (x) == CLOBBER)
11642 len = GET_RTX_LENGTH (code);
11643 fmt = GET_RTX_FORMAT (code);
11645 for (i = 0; i < len; i++)
11650 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11651 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
11654 else if (fmt[i] == 'e')
11655 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
11659 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11660 pattern of an insn. X must be a REG. */
11663 reg_bitfield_target_p (rtx x, rtx body)
11667 if (GET_CODE (body) == SET)
11669 rtx dest = SET_DEST (body);
11671 unsigned int regno, tregno, endregno, endtregno;
11673 if (GET_CODE (dest) == ZERO_EXTRACT)
11674 target = XEXP (dest, 0);
11675 else if (GET_CODE (dest) == STRICT_LOW_PART)
11676 target = SUBREG_REG (XEXP (dest, 0));
11680 if (GET_CODE (target) == SUBREG)
11681 target = SUBREG_REG (target);
11683 if (!REG_P (target))
11686 tregno = REGNO (target), regno = REGNO (x);
11687 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
11688 return target == x;
11690 endtregno = tregno + hard_regno_nregs[tregno][GET_MODE (target)];
11691 endregno = regno + hard_regno_nregs[regno][GET_MODE (x)];
11693 return endregno > tregno && regno < endtregno;
11696 else if (GET_CODE (body) == PARALLEL)
11697 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
11698 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
11704 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11705 as appropriate. I3 and I2 are the insns resulting from the combination
11706 insns including FROM (I2 may be zero).
11708 Each note in the list is either ignored or placed on some insns, depending
11709 on the type of note. */
11712 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2)
11714 rtx note, next_note;
11717 for (note = notes; note; note = next_note)
11719 rtx place = 0, place2 = 0;
11721 /* If this NOTE references a pseudo register, ensure it references
11722 the latest copy of that register. */
11723 if (XEXP (note, 0) && REG_P (XEXP (note, 0))
11724 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
11725 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
11727 next_note = XEXP (note, 1);
11728 switch (REG_NOTE_KIND (note))
11732 /* Doesn't matter much where we put this, as long as it's somewhere.
11733 It is preferable to keep these notes on branches, which is most
11734 likely to be i3. */
11738 case REG_VALUE_PROFILE:
11739 /* Just get rid of this note, as it is unused later anyway. */
11742 case REG_VTABLE_REF:
11743 /* ??? Should remain with *a particular* memory load. Given the
11744 nature of vtable data, the last insn seems relatively safe. */
11748 case REG_NON_LOCAL_GOTO:
11749 if (GET_CODE (i3) == JUMP_INSN)
11751 else if (i2 && GET_CODE (i2) == JUMP_INSN)
11757 case REG_EH_REGION:
11758 /* These notes must remain with the call or trapping instruction. */
11759 if (GET_CODE (i3) == CALL_INSN)
11761 else if (i2 && GET_CODE (i2) == CALL_INSN)
11763 else if (flag_non_call_exceptions)
11765 if (may_trap_p (i3))
11767 else if (i2 && may_trap_p (i2))
11769 /* ??? Otherwise assume we've combined things such that we
11770 can now prove that the instructions can't trap. Drop the
11771 note in this case. */
11777 case REG_ALWAYS_RETURN:
11780 /* These notes must remain with the call. It should not be
11781 possible for both I2 and I3 to be a call. */
11782 if (GET_CODE (i3) == CALL_INSN)
11784 else if (i2 && GET_CODE (i2) == CALL_INSN)
11791 /* Any clobbers for i3 may still exist, and so we must process
11792 REG_UNUSED notes from that insn.
11794 Any clobbers from i2 or i1 can only exist if they were added by
11795 recog_for_combine. In that case, recog_for_combine created the
11796 necessary REG_UNUSED notes. Trying to keep any original
11797 REG_UNUSED notes from these insns can cause incorrect output
11798 if it is for the same register as the original i3 dest.
11799 In that case, we will notice that the register is set in i3,
11800 and then add a REG_UNUSED note for the destination of i3, which
11801 is wrong. However, it is possible to have REG_UNUSED notes from
11802 i2 or i1 for register which were both used and clobbered, so
11803 we keep notes from i2 or i1 if they will turn into REG_DEAD
11806 /* If this register is set or clobbered in I3, put the note there
11807 unless there is one already. */
11808 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
11810 if (from_insn != i3)
11813 if (! (REG_P (XEXP (note, 0))
11814 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
11815 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
11818 /* Otherwise, if this register is used by I3, then this register
11819 now dies here, so we must put a REG_DEAD note here unless there
11821 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
11822 && ! (REG_P (XEXP (note, 0))
11823 ? find_regno_note (i3, REG_DEAD,
11824 REGNO (XEXP (note, 0)))
11825 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
11827 PUT_REG_NOTE_KIND (note, REG_DEAD);
11835 /* These notes say something about results of an insn. We can
11836 only support them if they used to be on I3 in which case they
11837 remain on I3. Otherwise they are ignored.
11839 If the note refers to an expression that is not a constant, we
11840 must also ignore the note since we cannot tell whether the
11841 equivalence is still true. It might be possible to do
11842 slightly better than this (we only have a problem if I2DEST
11843 or I1DEST is present in the expression), but it doesn't
11844 seem worth the trouble. */
11846 if (from_insn == i3
11847 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
11852 case REG_NO_CONFLICT:
11853 /* These notes say something about how a register is used. They must
11854 be present on any use of the register in I2 or I3. */
11855 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
11858 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
11868 /* This can show up in several ways -- either directly in the
11869 pattern, or hidden off in the constant pool with (or without?)
11870 a REG_EQUAL note. */
11871 /* ??? Ignore the without-reg_equal-note problem for now. */
11872 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
11873 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
11874 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
11875 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
11879 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
11880 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
11881 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
11882 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
11890 /* Don't attach REG_LABEL note to a JUMP_INSN which has
11891 JUMP_LABEL already. Instead, decrement LABEL_NUSES. */
11892 if (place && GET_CODE (place) == JUMP_INSN && JUMP_LABEL (place))
11894 if (JUMP_LABEL (place) != XEXP (note, 0))
11896 if (GET_CODE (JUMP_LABEL (place)) == CODE_LABEL)
11897 LABEL_NUSES (JUMP_LABEL (place))--;
11900 if (place2 && GET_CODE (place2) == JUMP_INSN && JUMP_LABEL (place2))
11902 if (JUMP_LABEL (place2) != XEXP (note, 0))
11904 if (GET_CODE (JUMP_LABEL (place2)) == CODE_LABEL)
11905 LABEL_NUSES (JUMP_LABEL (place2))--;
11911 /* This note says something about the value of a register prior
11912 to the execution of an insn. It is too much trouble to see
11913 if the note is still correct in all situations. It is better
11914 to simply delete it. */
11918 /* If the insn previously containing this note still exists,
11919 put it back where it was. Otherwise move it to the previous
11920 insn. Adjust the corresponding REG_LIBCALL note. */
11921 if (GET_CODE (from_insn) != NOTE)
11925 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
11926 place = prev_real_insn (from_insn);
11928 XEXP (tem, 0) = place;
11929 /* If we're deleting the last remaining instruction of a
11930 libcall sequence, don't add the notes. */
11931 else if (XEXP (note, 0) == from_insn)
11933 /* Don't add the dangling REG_RETVAL note. */
11940 /* This is handled similarly to REG_RETVAL. */
11941 if (GET_CODE (from_insn) != NOTE)
11945 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
11946 place = next_real_insn (from_insn);
11948 XEXP (tem, 0) = place;
11949 /* If we're deleting the last remaining instruction of a
11950 libcall sequence, don't add the notes. */
11951 else if (XEXP (note, 0) == from_insn)
11953 /* Don't add the dangling REG_LIBCALL note. */
11960 /* If the register is used as an input in I3, it dies there.
11961 Similarly for I2, if it is nonzero and adjacent to I3.
11963 If the register is not used as an input in either I3 or I2
11964 and it is not one of the registers we were supposed to eliminate,
11965 there are two possibilities. We might have a non-adjacent I2
11966 or we might have somehow eliminated an additional register
11967 from a computation. For example, we might have had A & B where
11968 we discover that B will always be zero. In this case we will
11969 eliminate the reference to A.
11971 In both cases, we must search to see if we can find a previous
11972 use of A and put the death note there. */
11975 && GET_CODE (from_insn) == CALL_INSN
11976 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
11978 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
11980 else if (i2 != 0 && next_nonnote_insn (i2) == i3
11981 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11986 basic_block bb = this_basic_block;
11988 for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem))
11990 if (! INSN_P (tem))
11992 if (tem == BB_HEAD (bb))
11997 /* If the register is being set at TEM, see if that is all
11998 TEM is doing. If so, delete TEM. Otherwise, make this
11999 into a REG_UNUSED note instead. Don't delete sets to
12000 global register vars. */
12001 if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
12002 || !global_regs[REGNO (XEXP (note, 0))])
12003 && reg_set_p (XEXP (note, 0), PATTERN (tem)))
12005 rtx set = single_set (tem);
12006 rtx inner_dest = 0;
12008 rtx cc0_setter = NULL_RTX;
12012 for (inner_dest = SET_DEST (set);
12013 (GET_CODE (inner_dest) == STRICT_LOW_PART
12014 || GET_CODE (inner_dest) == SUBREG
12015 || GET_CODE (inner_dest) == ZERO_EXTRACT);
12016 inner_dest = XEXP (inner_dest, 0))
12019 /* Verify that it was the set, and not a clobber that
12020 modified the register.
12022 CC0 targets must be careful to maintain setter/user
12023 pairs. If we cannot delete the setter due to side
12024 effects, mark the user with an UNUSED note instead
12027 if (set != 0 && ! side_effects_p (SET_SRC (set))
12028 && rtx_equal_p (XEXP (note, 0), inner_dest)
12030 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12031 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12032 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12036 /* Move the notes and links of TEM elsewhere.
12037 This might delete other dead insns recursively.
12038 First set the pattern to something that won't use
12040 rtx old_notes = REG_NOTES (tem);
12042 PATTERN (tem) = pc_rtx;
12043 REG_NOTES (tem) = NULL;
12045 distribute_notes (old_notes, tem, tem, NULL_RTX);
12046 distribute_links (LOG_LINKS (tem));
12048 PUT_CODE (tem, NOTE);
12049 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
12050 NOTE_SOURCE_FILE (tem) = 0;
12053 /* Delete the setter too. */
12056 PATTERN (cc0_setter) = pc_rtx;
12057 old_notes = REG_NOTES (cc0_setter);
12058 REG_NOTES (cc0_setter) = NULL;
12060 distribute_notes (old_notes, cc0_setter,
12061 cc0_setter, NULL_RTX);
12062 distribute_links (LOG_LINKS (cc0_setter));
12064 PUT_CODE (cc0_setter, NOTE);
12065 NOTE_LINE_NUMBER (cc0_setter)
12066 = NOTE_INSN_DELETED;
12067 NOTE_SOURCE_FILE (cc0_setter) = 0;
12073 PUT_REG_NOTE_KIND (note, REG_UNUSED);
12075 /* If there isn't already a REG_UNUSED note, put one
12076 here. Do not place a REG_DEAD note, even if
12077 the register is also used here; that would not
12078 match the algorithm used in lifetime analysis
12079 and can cause the consistency check in the
12080 scheduler to fail. */
12081 if (! find_regno_note (tem, REG_UNUSED,
12082 REGNO (XEXP (note, 0))))
12087 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12088 || (GET_CODE (tem) == CALL_INSN
12089 && find_reg_fusage (tem, USE, XEXP (note, 0))))
12093 /* If we are doing a 3->2 combination, and we have a
12094 register which formerly died in i3 and was not used
12095 by i2, which now no longer dies in i3 and is used in
12096 i2 but does not die in i2, and place is between i2
12097 and i3, then we may need to move a link from place to
12099 if (i2 && INSN_UID (place) <= max_uid_cuid
12100 && INSN_CUID (place) > INSN_CUID (i2)
12102 && INSN_CUID (from_insn) > INSN_CUID (i2)
12103 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12105 rtx links = LOG_LINKS (place);
12106 LOG_LINKS (place) = 0;
12107 distribute_links (links);
12112 if (tem == BB_HEAD (bb))
12116 /* We haven't found an insn for the death note and it
12117 is still a REG_DEAD note, but we have hit the beginning
12118 of the block. If the existing life info says the reg
12119 was dead, there's nothing left to do. Otherwise, we'll
12120 need to do a global life update after combine. */
12121 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
12122 && REGNO_REG_SET_P (bb->global_live_at_start,
12123 REGNO (XEXP (note, 0))))
12124 SET_BIT (refresh_blocks, this_basic_block->index);
12127 /* If the register is set or already dead at PLACE, we needn't do
12128 anything with this note if it is still a REG_DEAD note.
12129 We check here if it is set at all, not if is it totally replaced,
12130 which is what `dead_or_set_p' checks, so also check for it being
12133 if (place && REG_NOTE_KIND (note) == REG_DEAD)
12135 unsigned int regno = REGNO (XEXP (note, 0));
12137 /* Similarly, if the instruction on which we want to place
12138 the note is a noop, we'll need do a global live update
12139 after we remove them in delete_noop_moves. */
12140 if (noop_move_p (place))
12141 SET_BIT (refresh_blocks, this_basic_block->index);
12143 if (dead_or_set_p (place, XEXP (note, 0))
12144 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12146 /* Unless the register previously died in PLACE, clear
12147 last_death. [I no longer understand why this is
12149 if (reg_stat[regno].last_death != place)
12150 reg_stat[regno].last_death = 0;
12154 reg_stat[regno].last_death = place;
12156 /* If this is a death note for a hard reg that is occupying
12157 multiple registers, ensure that we are still using all
12158 parts of the object. If we find a piece of the object
12159 that is unused, we must arrange for an appropriate REG_DEAD
12160 note to be added for it. However, we can't just emit a USE
12161 and tag the note to it, since the register might actually
12162 be dead; so we recourse, and the recursive call then finds
12163 the previous insn that used this register. */
12165 if (place && regno < FIRST_PSEUDO_REGISTER
12166 && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
12168 unsigned int endregno
12169 = regno + hard_regno_nregs[regno]
12170 [GET_MODE (XEXP (note, 0))];
12174 for (i = regno; i < endregno; i++)
12175 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12176 && ! find_regno_fusage (place, USE, i))
12177 || dead_or_set_regno_p (place, i))
12182 /* Put only REG_DEAD notes for pieces that are
12183 not already dead or set. */
12185 for (i = regno; i < endregno;
12186 i += hard_regno_nregs[i][reg_raw_mode[i]])
12188 rtx piece = regno_reg_rtx[i];
12189 basic_block bb = this_basic_block;
12191 if (! dead_or_set_p (place, piece)
12192 && ! reg_bitfield_target_p (piece,
12196 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
12198 distribute_notes (new_note, place, place,
12201 else if (! refers_to_regno_p (i, i + 1,
12202 PATTERN (place), 0)
12203 && ! find_regno_fusage (place, USE, i))
12204 for (tem = PREV_INSN (place); ;
12205 tem = PREV_INSN (tem))
12207 if (! INSN_P (tem))
12209 if (tem == BB_HEAD (bb))
12211 SET_BIT (refresh_blocks,
12212 this_basic_block->index);
12217 if (dead_or_set_p (tem, piece)
12218 || reg_bitfield_target_p (piece,
12222 = gen_rtx_EXPR_LIST (REG_UNUSED, piece,
12237 /* Any other notes should not be present at this point in the
12244 XEXP (note, 1) = REG_NOTES (place);
12245 REG_NOTES (place) = note;
12247 else if ((REG_NOTE_KIND (note) == REG_DEAD
12248 || REG_NOTE_KIND (note) == REG_UNUSED)
12249 && REG_P (XEXP (note, 0)))
12250 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
12254 if ((REG_NOTE_KIND (note) == REG_DEAD
12255 || REG_NOTE_KIND (note) == REG_UNUSED)
12256 && REG_P (XEXP (note, 0)))
12257 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
12259 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
12260 REG_NOTE_KIND (note),
12262 REG_NOTES (place2));
12267 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12268 I3, I2, and I1 to new locations. This is also called to add a link
12269 pointing at I3 when I3's destination is changed. */
12272 distribute_links (rtx links)
12274 rtx link, next_link;
12276 for (link = links; link; link = next_link)
12282 next_link = XEXP (link, 1);
12284 /* If the insn that this link points to is a NOTE or isn't a single
12285 set, ignore it. In the latter case, it isn't clear what we
12286 can do other than ignore the link, since we can't tell which
12287 register it was for. Such links wouldn't be used by combine
12290 It is not possible for the destination of the target of the link to
12291 have been changed by combine. The only potential of this is if we
12292 replace I3, I2, and I1 by I3 and I2. But in that case the
12293 destination of I2 also remains unchanged. */
12295 if (GET_CODE (XEXP (link, 0)) == NOTE
12296 || (set = single_set (XEXP (link, 0))) == 0)
12299 reg = SET_DEST (set);
12300 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12301 || GET_CODE (reg) == SIGN_EXTRACT
12302 || GET_CODE (reg) == STRICT_LOW_PART)
12303 reg = XEXP (reg, 0);
12305 /* A LOG_LINK is defined as being placed on the first insn that uses
12306 a register and points to the insn that sets the register. Start
12307 searching at the next insn after the target of the link and stop
12308 when we reach a set of the register or the end of the basic block.
12310 Note that this correctly handles the link that used to point from
12311 I3 to I2. Also note that not much searching is typically done here
12312 since most links don't point very far away. */
12314 for (insn = NEXT_INSN (XEXP (link, 0));
12315 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
12316 || BB_HEAD (this_basic_block->next_bb) != insn));
12317 insn = NEXT_INSN (insn))
12318 if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12320 if (reg_referenced_p (reg, PATTERN (insn)))
12324 else if (GET_CODE (insn) == CALL_INSN
12325 && find_reg_fusage (insn, USE, reg))
12330 else if (INSN_P (insn) && reg_set_p (reg, insn))
12333 /* If we found a place to put the link, place it there unless there
12334 is already a link to the same insn as LINK at that point. */
12340 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12341 if (XEXP (link2, 0) == XEXP (link, 0))
12346 XEXP (link, 1) = LOG_LINKS (place);
12347 LOG_LINKS (place) = link;
12349 /* Set added_links_insn to the earliest insn we added a
12351 if (added_links_insn == 0
12352 || INSN_CUID (added_links_insn) > INSN_CUID (place))
12353 added_links_insn = place;
12359 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
12360 Check whether the expression pointer to by LOC is a register or
12361 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
12362 Otherwise return zero. */
12365 unmentioned_reg_p_1 (rtx *loc, void *expr)
12370 && (REG_P (x) || GET_CODE (x) == MEM)
12371 && ! reg_mentioned_p (x, (rtx) expr))
12376 /* Check for any register or memory mentioned in EQUIV that is not
12377 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
12378 of EXPR where some registers may have been replaced by constants. */
12381 unmentioned_reg_p (rtx equiv, rtx expr)
12383 return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
12386 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12389 insn_cuid (rtx insn)
12391 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
12392 && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE)
12393 insn = NEXT_INSN (insn);
12395 if (INSN_UID (insn) > max_uid_cuid)
12398 return INSN_CUID (insn);
12402 dump_combine_stats (FILE *file)
12406 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12407 combine_attempts, combine_merges, combine_extras, combine_successes);
12411 dump_combine_total_stats (FILE *file)
12415 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12416 total_attempts, total_merges, total_extras, total_successes);