1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_regnotes) when a
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
83 #include "hard-reg-set.h"
84 #include "basic-block.h"
85 #include "insn-config.h"
87 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
89 #include "insn-attr.h"
94 /* It is not safe to use ordinary gen_lowpart in combine.
95 Use gen_lowpart_for_combine instead. See comments there. */
96 #define gen_lowpart dont_use_gen_lowpart_you_dummy
98 /* Number of attempts to combine instructions in this function. */
100 static int combine_attempts;
102 /* Number of attempts that got as far as substitution in this function. */
104 static int combine_merges;
106 /* Number of instructions combined with added SETs in this function. */
108 static int combine_extras;
110 /* Number of instructions combined in this function. */
112 static int combine_successes;
114 /* Totals over entire compilation. */
116 static int total_attempts, total_merges, total_extras, total_successes;
119 /* Vector mapping INSN_UIDs to cuids.
120 The cuids are like uids but increase monotonically always.
121 Combine always uses cuids so that it can compare them.
122 But actually renumbering the uids, which we used to do,
123 proves to be a bad idea because it makes it hard to compare
124 the dumps produced by earlier passes with those from later passes. */
126 static int *uid_cuid;
127 static int max_uid_cuid;
129 /* Get the cuid of an insn. */
131 #define INSN_CUID(INSN) \
132 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
134 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
135 BITS_PER_WORD would invoke undefined behavior. Work around it. */
137 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
138 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
140 /* Maximum register number, which is the size of the tables below. */
142 static unsigned int combine_max_regno;
144 /* Record last point of death of (hard or pseudo) register n. */
146 static rtx *reg_last_death;
148 /* Record last point of modification of (hard or pseudo) register n. */
150 static rtx *reg_last_set;
152 /* Record the cuid of the last insn that invalidated memory
153 (anything that writes memory, and subroutine calls, but not pushes). */
155 static int mem_last_set;
157 /* Record the cuid of the last CALL_INSN
158 so we can tell whether a potential combination crosses any calls. */
160 static int last_call_cuid;
162 /* When `subst' is called, this is the insn that is being modified
163 (by combining in a previous insn). The PATTERN of this insn
164 is still the old pattern partially modified and it should not be
165 looked at, but this may be used to examine the successors of the insn
166 to judge whether a simplification is valid. */
168 static rtx subst_insn;
170 /* This is an insn that belongs before subst_insn, but is not currently
171 on the insn chain. */
173 static rtx subst_prev_insn;
175 /* This is the lowest CUID that `subst' is currently dealing with.
176 get_last_value will not return a value if the register was set at or
177 after this CUID. If not for this mechanism, we could get confused if
178 I2 or I1 in try_combine were an insn that used the old value of a register
179 to obtain a new value. In that case, we might erroneously get the
180 new value of the register when we wanted the old one. */
182 static int subst_low_cuid;
184 /* This contains any hard registers that are used in newpat; reg_dead_at_p
185 must consider all these registers to be always live. */
187 static HARD_REG_SET newpat_used_regs;
189 /* This is an insn to which a LOG_LINKS entry has been added. If this
190 insn is the earlier than I2 or I3, combine should rescan starting at
193 static rtx added_links_insn;
195 /* Basic block in which we are performing combines. */
196 static basic_block this_basic_block;
198 /* A bitmap indicating which blocks had registers go dead at entry.
199 After combine, we'll need to re-do global life analysis with
200 those blocks as starting points. */
201 static sbitmap refresh_blocks;
202 static int need_refresh;
204 /* The next group of arrays allows the recording of the last value assigned
205 to (hard or pseudo) register n. We use this information to see if a
206 operation being processed is redundant given a prior operation performed
207 on the register. For example, an `and' with a constant is redundant if
208 all the zero bits are already known to be turned off.
210 We use an approach similar to that used by cse, but change it in the
213 (1) We do not want to reinitialize at each label.
214 (2) It is useful, but not critical, to know the actual value assigned
215 to a register. Often just its form is helpful.
217 Therefore, we maintain the following arrays:
219 reg_last_set_value the last value assigned
220 reg_last_set_label records the value of label_tick when the
221 register was assigned
222 reg_last_set_table_tick records the value of label_tick when a
223 value using the register is assigned
224 reg_last_set_invalid set to nonzero when it is not valid
225 to use the value of this register in some
228 To understand the usage of these tables, it is important to understand
229 the distinction between the value in reg_last_set_value being valid
230 and the register being validly contained in some other expression in the
233 Entry I in reg_last_set_value is valid if it is nonzero, and either
234 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
236 Register I may validly appear in any expression returned for the value
237 of another register if reg_n_sets[i] is 1. It may also appear in the
238 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
239 reg_last_set_invalid[j] is zero.
241 If an expression is found in the table containing a register which may
242 not validly appear in an expression, the register is replaced by
243 something that won't match, (clobber (const_int 0)).
245 reg_last_set_invalid[i] is set nonzero when register I is being assigned
246 to and reg_last_set_table_tick[i] == label_tick. */
248 /* Record last value assigned to (hard or pseudo) register n. */
250 static rtx *reg_last_set_value;
252 /* Record the value of label_tick when the value for register n is placed in
253 reg_last_set_value[n]. */
255 static int *reg_last_set_label;
257 /* Record the value of label_tick when an expression involving register n
258 is placed in reg_last_set_value. */
260 static int *reg_last_set_table_tick;
262 /* Set nonzero if references to register n in expressions should not be
265 static char *reg_last_set_invalid;
267 /* Incremented for each label. */
269 static int label_tick;
271 /* Some registers that are set more than once and used in more than one
272 basic block are nevertheless always set in similar ways. For example,
273 a QImode register may be loaded from memory in two places on a machine
274 where byte loads zero extend.
276 We record in the following array what we know about the nonzero
277 bits of a register, specifically which bits are known to be zero.
279 If an entry is zero, it means that we don't know anything special. */
281 static unsigned HOST_WIDE_INT *reg_nonzero_bits;
283 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
284 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
286 static enum machine_mode nonzero_bits_mode;
288 /* Nonzero if we know that a register has some leading bits that are always
289 equal to the sign bit. */
291 static unsigned char *reg_sign_bit_copies;
293 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
294 It is zero while computing them and after combine has completed. This
295 former test prevents propagating values based on previously set values,
296 which can be incorrect if a variable is modified in a loop. */
298 static int nonzero_sign_valid;
300 /* These arrays are maintained in parallel with reg_last_set_value
301 and are used to store the mode in which the register was last set,
302 the bits that were known to be zero when it was last set, and the
303 number of sign bits copies it was known to have when it was last set. */
305 static enum machine_mode *reg_last_set_mode;
306 static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
307 static char *reg_last_set_sign_bit_copies;
309 /* Record one modification to rtl structure
310 to be undone by storing old_contents into *where.
311 is_int is 1 if the contents are an int. */
317 union {rtx r; int i;} old_contents;
318 union {rtx *r; int *i;} where;
321 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
322 num_undo says how many are currently recorded.
324 other_insn is nonzero if we have modified some other insn in the process
325 of working on subst_insn. It must be verified too. */
334 static struct undobuf undobuf;
336 /* Number of times the pseudo being substituted for
337 was found and replaced. */
339 static int n_occurrences;
341 static void do_SUBST PARAMS ((rtx *, rtx));
342 static void do_SUBST_INT PARAMS ((int *, int));
343 static void init_reg_last_arrays PARAMS ((void));
344 static void setup_incoming_promotions PARAMS ((void));
345 static void set_nonzero_bits_and_sign_copies PARAMS ((rtx, rtx, void *));
346 static int cant_combine_insn_p PARAMS ((rtx));
347 static int can_combine_p PARAMS ((rtx, rtx, rtx, rtx, rtx *, rtx *));
348 static int sets_function_arg_p PARAMS ((rtx));
349 static int combinable_i3pat PARAMS ((rtx, rtx *, rtx, rtx, int, rtx *));
350 static int contains_muldiv PARAMS ((rtx));
351 static rtx try_combine PARAMS ((rtx, rtx, rtx, int *));
352 static void undo_all PARAMS ((void));
353 static void undo_commit PARAMS ((void));
354 static rtx *find_split_point PARAMS ((rtx *, rtx));
355 static rtx subst PARAMS ((rtx, rtx, rtx, int, int));
356 static rtx combine_simplify_rtx PARAMS ((rtx, enum machine_mode, int, int));
357 static rtx simplify_if_then_else PARAMS ((rtx));
358 static rtx simplify_set PARAMS ((rtx));
359 static rtx simplify_logical PARAMS ((rtx, int));
360 static rtx expand_compound_operation PARAMS ((rtx));
361 static rtx expand_field_assignment PARAMS ((rtx));
362 static rtx make_extraction PARAMS ((enum machine_mode, rtx, HOST_WIDE_INT,
363 rtx, unsigned HOST_WIDE_INT, int,
365 static rtx extract_left_shift PARAMS ((rtx, int));
366 static rtx make_compound_operation PARAMS ((rtx, enum rtx_code));
367 static int get_pos_from_mask PARAMS ((unsigned HOST_WIDE_INT,
368 unsigned HOST_WIDE_INT *));
369 static rtx force_to_mode PARAMS ((rtx, enum machine_mode,
370 unsigned HOST_WIDE_INT, rtx, int));
371 static rtx if_then_else_cond PARAMS ((rtx, rtx *, rtx *));
372 static rtx known_cond PARAMS ((rtx, enum rtx_code, rtx, rtx));
373 static int rtx_equal_for_field_assignment_p PARAMS ((rtx, rtx));
374 static rtx make_field_assignment PARAMS ((rtx));
375 static rtx apply_distributive_law PARAMS ((rtx));
376 static rtx simplify_and_const_int PARAMS ((rtx, enum machine_mode, rtx,
377 unsigned HOST_WIDE_INT));
378 static unsigned HOST_WIDE_INT nonzero_bits PARAMS ((rtx, enum machine_mode));
379 static unsigned int num_sign_bit_copies PARAMS ((rtx, enum machine_mode));
380 static int merge_outer_ops PARAMS ((enum rtx_code *, HOST_WIDE_INT *,
381 enum rtx_code, HOST_WIDE_INT,
382 enum machine_mode, int *));
383 static rtx simplify_shift_const PARAMS ((rtx, enum rtx_code, enum machine_mode,
385 static int recog_for_combine PARAMS ((rtx *, rtx, rtx *));
386 static rtx gen_lowpart_for_combine PARAMS ((enum machine_mode, rtx));
387 static rtx gen_binary PARAMS ((enum rtx_code, enum machine_mode,
389 static enum rtx_code simplify_comparison PARAMS ((enum rtx_code, rtx *, rtx *));
390 static void update_table_tick PARAMS ((rtx));
391 static void record_value_for_reg PARAMS ((rtx, rtx, rtx));
392 static void check_promoted_subreg PARAMS ((rtx, rtx));
393 static void record_dead_and_set_regs_1 PARAMS ((rtx, rtx, void *));
394 static void record_dead_and_set_regs PARAMS ((rtx));
395 static int get_last_value_validate PARAMS ((rtx *, rtx, int, int));
396 static rtx get_last_value PARAMS ((rtx));
397 static int use_crosses_set_p PARAMS ((rtx, int));
398 static void reg_dead_at_p_1 PARAMS ((rtx, rtx, void *));
399 static int reg_dead_at_p PARAMS ((rtx, rtx));
400 static void move_deaths PARAMS ((rtx, rtx, int, rtx, rtx *));
401 static int reg_bitfield_target_p PARAMS ((rtx, rtx));
402 static void distribute_notes PARAMS ((rtx, rtx, rtx, rtx, rtx, rtx));
403 static void distribute_links PARAMS ((rtx));
404 static void mark_used_regs_combine PARAMS ((rtx));
405 static int insn_cuid PARAMS ((rtx));
406 static void record_promoted_value PARAMS ((rtx, rtx));
407 static rtx reversed_comparison PARAMS ((rtx, enum machine_mode, rtx, rtx));
408 static enum rtx_code combine_reversed_comparison_code PARAMS ((rtx));
410 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
411 insn. The substitution can be undone by undo_all. If INTO is already
412 set to NEWVAL, do not record this change. Because computing NEWVAL might
413 also call SUBST, we have to compute it before we put anything into
417 do_SUBST (into, newval)
423 if (oldval == newval)
426 /* We'd like to catch as many invalid transformations here as
427 possible. Unfortunately, there are way too many mode changes
428 that are perfectly valid, so we'd waste too much effort for
429 little gain doing the checks here. Focus on catching invalid
430 transformations involving integer constants. */
431 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
432 && GET_CODE (newval) == CONST_INT)
434 /* Sanity check that we're replacing oldval with a CONST_INT
435 that is a valid sign-extension for the original mode. */
436 if (INTVAL (newval) != trunc_int_for_mode (INTVAL (newval),
440 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
441 CONST_INT is not valid, because after the replacement, the
442 original mode would be gone. Unfortunately, we can't tell
443 when do_SUBST is called to replace the operand thereof, so we
444 perform this test on oldval instead, checking whether an
445 invalid replacement took place before we got here. */
446 if ((GET_CODE (oldval) == SUBREG
447 && GET_CODE (SUBREG_REG (oldval)) == CONST_INT)
448 || (GET_CODE (oldval) == ZERO_EXTEND
449 && GET_CODE (XEXP (oldval, 0)) == CONST_INT))
454 buf = undobuf.frees, undobuf.frees = buf->next;
456 buf = (struct undo *) xmalloc (sizeof (struct undo));
460 buf->old_contents.r = oldval;
463 buf->next = undobuf.undos, undobuf.undos = buf;
466 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
468 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
469 for the value of a HOST_WIDE_INT value (including CONST_INT) is
473 do_SUBST_INT (into, newval)
479 if (oldval == newval)
483 buf = undobuf.frees, undobuf.frees = buf->next;
485 buf = (struct undo *) xmalloc (sizeof (struct undo));
489 buf->old_contents.i = oldval;
492 buf->next = undobuf.undos, undobuf.undos = buf;
495 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
497 /* Main entry point for combiner. F is the first insn of the function.
498 NREGS is the first unused pseudo-reg number.
500 Return nonzero if the combiner has turned an indirect jump
501 instruction into a direct jump. */
503 combine_instructions (f, nregs)
512 rtx links, nextlinks;
514 int new_direct_jump_p = 0;
516 combine_attempts = 0;
519 combine_successes = 0;
521 combine_max_regno = nregs;
523 reg_nonzero_bits = ((unsigned HOST_WIDE_INT *)
524 xcalloc (nregs, sizeof (unsigned HOST_WIDE_INT)));
526 = (unsigned char *) xcalloc (nregs, sizeof (unsigned char));
528 reg_last_death = (rtx *) xmalloc (nregs * sizeof (rtx));
529 reg_last_set = (rtx *) xmalloc (nregs * sizeof (rtx));
530 reg_last_set_value = (rtx *) xmalloc (nregs * sizeof (rtx));
531 reg_last_set_table_tick = (int *) xmalloc (nregs * sizeof (int));
532 reg_last_set_label = (int *) xmalloc (nregs * sizeof (int));
533 reg_last_set_invalid = (char *) xmalloc (nregs * sizeof (char));
535 = (enum machine_mode *) xmalloc (nregs * sizeof (enum machine_mode));
536 reg_last_set_nonzero_bits
537 = (unsigned HOST_WIDE_INT *) xmalloc (nregs * sizeof (HOST_WIDE_INT));
538 reg_last_set_sign_bit_copies
539 = (char *) xmalloc (nregs * sizeof (char));
541 init_reg_last_arrays ();
543 init_recog_no_volatile ();
545 /* Compute maximum uid value so uid_cuid can be allocated. */
547 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
548 if (INSN_UID (insn) > i)
551 uid_cuid = (int *) xmalloc ((i + 1) * sizeof (int));
554 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
556 /* Don't use reg_nonzero_bits when computing it. This can cause problems
557 when, for example, we have j <<= 1 in a loop. */
559 nonzero_sign_valid = 0;
561 /* Compute the mapping from uids to cuids.
562 Cuids are numbers assigned to insns, like uids,
563 except that cuids increase monotonically through the code.
565 Scan all SETs and see if we can deduce anything about what
566 bits are known to be zero for some registers and how many copies
567 of the sign bit are known to exist for those registers.
569 Also set any known values so that we can use it while searching
570 for what bits are known to be set. */
574 /* We need to initialize it here, because record_dead_and_set_regs may call
576 subst_prev_insn = NULL_RTX;
578 setup_incoming_promotions ();
580 refresh_blocks = sbitmap_alloc (last_basic_block);
581 sbitmap_zero (refresh_blocks);
584 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
586 uid_cuid[INSN_UID (insn)] = ++i;
592 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
594 record_dead_and_set_regs (insn);
597 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
598 if (REG_NOTE_KIND (links) == REG_INC)
599 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
604 if (GET_CODE (insn) == CODE_LABEL)
608 nonzero_sign_valid = 1;
610 /* Now scan all the insns in forward order. */
615 init_reg_last_arrays ();
616 setup_incoming_promotions ();
618 FOR_EACH_BB (this_basic_block)
620 for (insn = this_basic_block->head;
621 insn != NEXT_INSN (this_basic_block->end);
622 insn = next ? next : NEXT_INSN (insn))
626 if (GET_CODE (insn) == CODE_LABEL)
629 else if (INSN_P (insn))
631 /* See if we know about function return values before this
632 insn based upon SUBREG flags. */
633 check_promoted_subreg (insn, PATTERN (insn));
635 /* Try this insn with each insn it links back to. */
637 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
638 if ((next = try_combine (insn, XEXP (links, 0),
639 NULL_RTX, &new_direct_jump_p)) != 0)
642 /* Try each sequence of three linked insns ending with this one. */
644 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
646 rtx link = XEXP (links, 0);
648 /* If the linked insn has been replaced by a note, then there
649 is no point in pursuing this chain any further. */
650 if (GET_CODE (link) == NOTE)
653 for (nextlinks = LOG_LINKS (link);
655 nextlinks = XEXP (nextlinks, 1))
656 if ((next = try_combine (insn, link,
658 &new_direct_jump_p)) != 0)
663 /* Try to combine a jump insn that uses CC0
664 with a preceding insn that sets CC0, and maybe with its
665 logical predecessor as well.
666 This is how we make decrement-and-branch insns.
667 We need this special code because data flow connections
668 via CC0 do not get entered in LOG_LINKS. */
670 if (GET_CODE (insn) == JUMP_INSN
671 && (prev = prev_nonnote_insn (insn)) != 0
672 && GET_CODE (prev) == INSN
673 && sets_cc0_p (PATTERN (prev)))
675 if ((next = try_combine (insn, prev,
676 NULL_RTX, &new_direct_jump_p)) != 0)
679 for (nextlinks = LOG_LINKS (prev); nextlinks;
680 nextlinks = XEXP (nextlinks, 1))
681 if ((next = try_combine (insn, prev,
683 &new_direct_jump_p)) != 0)
687 /* Do the same for an insn that explicitly references CC0. */
688 if (GET_CODE (insn) == INSN
689 && (prev = prev_nonnote_insn (insn)) != 0
690 && GET_CODE (prev) == INSN
691 && sets_cc0_p (PATTERN (prev))
692 && GET_CODE (PATTERN (insn)) == SET
693 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
695 if ((next = try_combine (insn, prev,
696 NULL_RTX, &new_direct_jump_p)) != 0)
699 for (nextlinks = LOG_LINKS (prev); nextlinks;
700 nextlinks = XEXP (nextlinks, 1))
701 if ((next = try_combine (insn, prev,
703 &new_direct_jump_p)) != 0)
707 /* Finally, see if any of the insns that this insn links to
708 explicitly references CC0. If so, try this insn, that insn,
709 and its predecessor if it sets CC0. */
710 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
711 if (GET_CODE (XEXP (links, 0)) == INSN
712 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
713 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
714 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
715 && GET_CODE (prev) == INSN
716 && sets_cc0_p (PATTERN (prev))
717 && (next = try_combine (insn, XEXP (links, 0),
718 prev, &new_direct_jump_p)) != 0)
722 /* Try combining an insn with two different insns whose results it
724 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
725 for (nextlinks = XEXP (links, 1); nextlinks;
726 nextlinks = XEXP (nextlinks, 1))
727 if ((next = try_combine (insn, XEXP (links, 0),
729 &new_direct_jump_p)) != 0)
732 if (GET_CODE (insn) != NOTE)
733 record_dead_and_set_regs (insn);
742 EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks, 0, i,
743 BASIC_BLOCK (i)->flags |= BB_DIRTY);
744 new_direct_jump_p |= purge_all_dead_edges (0);
745 delete_noop_moves (f);
747 update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES,
748 PROP_DEATH_NOTES | PROP_SCAN_DEAD_CODE
749 | PROP_KILL_DEAD_CODE);
752 sbitmap_free (refresh_blocks);
753 free (reg_nonzero_bits);
754 free (reg_sign_bit_copies);
755 free (reg_last_death);
757 free (reg_last_set_value);
758 free (reg_last_set_table_tick);
759 free (reg_last_set_label);
760 free (reg_last_set_invalid);
761 free (reg_last_set_mode);
762 free (reg_last_set_nonzero_bits);
763 free (reg_last_set_sign_bit_copies);
767 struct undo *undo, *next;
768 for (undo = undobuf.frees; undo; undo = next)
776 total_attempts += combine_attempts;
777 total_merges += combine_merges;
778 total_extras += combine_extras;
779 total_successes += combine_successes;
781 nonzero_sign_valid = 0;
783 /* Make recognizer allow volatile MEMs again. */
786 return new_direct_jump_p;
789 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
792 init_reg_last_arrays ()
794 unsigned int nregs = combine_max_regno;
796 memset ((char *) reg_last_death, 0, nregs * sizeof (rtx));
797 memset ((char *) reg_last_set, 0, nregs * sizeof (rtx));
798 memset ((char *) reg_last_set_value, 0, nregs * sizeof (rtx));
799 memset ((char *) reg_last_set_table_tick, 0, nregs * sizeof (int));
800 memset ((char *) reg_last_set_label, 0, nregs * sizeof (int));
801 memset (reg_last_set_invalid, 0, nregs * sizeof (char));
802 memset ((char *) reg_last_set_mode, 0, nregs * sizeof (enum machine_mode));
803 memset ((char *) reg_last_set_nonzero_bits, 0, nregs * sizeof (HOST_WIDE_INT));
804 memset (reg_last_set_sign_bit_copies, 0, nregs * sizeof (char));
807 /* Set up any promoted values for incoming argument registers. */
810 setup_incoming_promotions ()
812 #ifdef PROMOTE_FUNCTION_ARGS
815 enum machine_mode mode;
817 rtx first = get_insns ();
819 #ifndef OUTGOING_REGNO
820 #define OUTGOING_REGNO(N) N
822 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
823 /* Check whether this register can hold an incoming pointer
824 argument. FUNCTION_ARG_REGNO_P tests outgoing register
825 numbers, so translate if necessary due to register windows. */
826 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
827 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
830 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
833 gen_rtx_CLOBBER (mode, const0_rtx)));
838 /* Called via note_stores. If X is a pseudo that is narrower than
839 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
841 If we are setting only a portion of X and we can't figure out what
842 portion, assume all bits will be used since we don't know what will
845 Similarly, set how many bits of X are known to be copies of the sign bit
846 at all locations in the function. This is the smallest number implied
850 set_nonzero_bits_and_sign_copies (x, set, data)
853 void *data ATTRIBUTE_UNUSED;
857 if (GET_CODE (x) == REG
858 && REGNO (x) >= FIRST_PSEUDO_REGISTER
859 /* If this register is undefined at the start of the file, we can't
860 say what its contents were. */
861 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, REGNO (x))
862 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
864 if (set == 0 || GET_CODE (set) == CLOBBER)
866 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
867 reg_sign_bit_copies[REGNO (x)] = 1;
871 /* If this is a complex assignment, see if we can convert it into a
872 simple assignment. */
873 set = expand_field_assignment (set);
875 /* If this is a simple assignment, or we have a paradoxical SUBREG,
876 set what we know about X. */
878 if (SET_DEST (set) == x
879 || (GET_CODE (SET_DEST (set)) == SUBREG
880 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
881 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
882 && SUBREG_REG (SET_DEST (set)) == x))
884 rtx src = SET_SRC (set);
886 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
887 /* If X is narrower than a word and SRC is a non-negative
888 constant that would appear negative in the mode of X,
889 sign-extend it for use in reg_nonzero_bits because some
890 machines (maybe most) will actually do the sign-extension
891 and this is the conservative approach.
893 ??? For 2.5, try to tighten up the MD files in this regard
894 instead of this kludge. */
896 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
897 && GET_CODE (src) == CONST_INT
899 && 0 != (INTVAL (src)
901 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
902 src = GEN_INT (INTVAL (src)
903 | ((HOST_WIDE_INT) (-1)
904 << GET_MODE_BITSIZE (GET_MODE (x))));
907 /* Don't call nonzero_bits if it cannot change anything. */
908 if (reg_nonzero_bits[REGNO (x)] != ~(unsigned HOST_WIDE_INT) 0)
909 reg_nonzero_bits[REGNO (x)]
910 |= nonzero_bits (src, nonzero_bits_mode);
911 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
912 if (reg_sign_bit_copies[REGNO (x)] == 0
913 || reg_sign_bit_copies[REGNO (x)] > num)
914 reg_sign_bit_copies[REGNO (x)] = num;
918 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
919 reg_sign_bit_copies[REGNO (x)] = 1;
924 /* See if INSN can be combined into I3. PRED and SUCC are optionally
925 insns that were previously combined into I3 or that will be combined
926 into the merger of INSN and I3.
928 Return 0 if the combination is not allowed for any reason.
930 If the combination is allowed, *PDEST will be set to the single
931 destination of INSN and *PSRC to the single source, and this function
935 can_combine_p (insn, i3, pred, succ, pdest, psrc)
938 rtx pred ATTRIBUTE_UNUSED;
943 rtx set = 0, src, dest;
948 int all_adjacent = (succ ? (next_active_insn (insn) == succ
949 && next_active_insn (succ) == i3)
950 : next_active_insn (insn) == i3);
952 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
953 or a PARALLEL consisting of such a SET and CLOBBERs.
955 If INSN has CLOBBER parallel parts, ignore them for our processing.
956 By definition, these happen during the execution of the insn. When it
957 is merged with another insn, all bets are off. If they are, in fact,
958 needed and aren't also supplied in I3, they may be added by
959 recog_for_combine. Otherwise, it won't match.
961 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
964 Get the source and destination of INSN. If more than one, can't
967 if (GET_CODE (PATTERN (insn)) == SET)
968 set = PATTERN (insn);
969 else if (GET_CODE (PATTERN (insn)) == PARALLEL
970 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
972 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
974 rtx elt = XVECEXP (PATTERN (insn), 0, i);
976 switch (GET_CODE (elt))
978 /* This is important to combine floating point insns
981 /* Combining an isolated USE doesn't make sense.
982 We depend here on combinable_i3pat to reject them. */
983 /* The code below this loop only verifies that the inputs of
984 the SET in INSN do not change. We call reg_set_between_p
985 to verify that the REG in the USE does not change between
987 If the USE in INSN was for a pseudo register, the matching
988 insn pattern will likely match any register; combining this
989 with any other USE would only be safe if we knew that the
990 used registers have identical values, or if there was
991 something to tell them apart, e.g. different modes. For
992 now, we forgo such complicated tests and simply disallow
993 combining of USES of pseudo registers with any other USE. */
994 if (GET_CODE (XEXP (elt, 0)) == REG
995 && GET_CODE (PATTERN (i3)) == PARALLEL)
997 rtx i3pat = PATTERN (i3);
998 int i = XVECLEN (i3pat, 0) - 1;
999 unsigned int regno = REGNO (XEXP (elt, 0));
1003 rtx i3elt = XVECEXP (i3pat, 0, i);
1005 if (GET_CODE (i3elt) == USE
1006 && GET_CODE (XEXP (i3elt, 0)) == REG
1007 && (REGNO (XEXP (i3elt, 0)) == regno
1008 ? reg_set_between_p (XEXP (elt, 0),
1009 PREV_INSN (insn), i3)
1010 : regno >= FIRST_PSEUDO_REGISTER))
1017 /* We can ignore CLOBBERs. */
1022 /* Ignore SETs whose result isn't used but not those that
1023 have side-effects. */
1024 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1025 && ! side_effects_p (elt))
1028 /* If we have already found a SET, this is a second one and
1029 so we cannot combine with this insn. */
1037 /* Anything else means we can't combine. */
1043 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1044 so don't do anything with it. */
1045 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1054 set = expand_field_assignment (set);
1055 src = SET_SRC (set), dest = SET_DEST (set);
1057 /* Don't eliminate a store in the stack pointer. */
1058 if (dest == stack_pointer_rtx
1059 /* If we couldn't eliminate a field assignment, we can't combine. */
1060 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
1061 /* Don't combine with an insn that sets a register to itself if it has
1062 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1063 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1064 /* Can't merge an ASM_OPERANDS. */
1065 || GET_CODE (src) == ASM_OPERANDS
1066 /* Can't merge a function call. */
1067 || GET_CODE (src) == CALL
1068 /* Don't eliminate a function call argument. */
1069 || (GET_CODE (i3) == CALL_INSN
1070 && (find_reg_fusage (i3, USE, dest)
1071 || (GET_CODE (dest) == REG
1072 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1073 && global_regs[REGNO (dest)])))
1074 /* Don't substitute into an incremented register. */
1075 || FIND_REG_INC_NOTE (i3, dest)
1076 || (succ && FIND_REG_INC_NOTE (succ, dest))
1078 /* Don't combine the end of a libcall into anything. */
1079 /* ??? This gives worse code, and appears to be unnecessary, since no
1080 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1081 use REG_RETVAL notes for noconflict blocks, but other code here
1082 makes sure that those insns don't disappear. */
1083 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1085 /* Make sure that DEST is not used after SUCC but before I3. */
1086 || (succ && ! all_adjacent
1087 && reg_used_between_p (dest, succ, i3))
1088 /* Make sure that the value that is to be substituted for the register
1089 does not use any registers whose values alter in between. However,
1090 If the insns are adjacent, a use can't cross a set even though we
1091 think it might (this can happen for a sequence of insns each setting
1092 the same destination; reg_last_set of that register might point to
1093 a NOTE). If INSN has a REG_EQUIV note, the register is always
1094 equivalent to the memory so the substitution is valid even if there
1095 are intervening stores. Also, don't move a volatile asm or
1096 UNSPEC_VOLATILE across any other insns. */
1098 && (((GET_CODE (src) != MEM
1099 || ! find_reg_note (insn, REG_EQUIV, src))
1100 && use_crosses_set_p (src, INSN_CUID (insn)))
1101 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1102 || GET_CODE (src) == UNSPEC_VOLATILE))
1103 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1104 better register allocation by not doing the combine. */
1105 || find_reg_note (i3, REG_NO_CONFLICT, dest)
1106 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1107 /* Don't combine across a CALL_INSN, because that would possibly
1108 change whether the life span of some REGs crosses calls or not,
1109 and it is a pain to update that information.
1110 Exception: if source is a constant, moving it later can't hurt.
1111 Accept that special case, because it helps -fforce-addr a lot. */
1112 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1115 /* DEST must either be a REG or CC0. */
1116 if (GET_CODE (dest) == REG)
1118 /* If register alignment is being enforced for multi-word items in all
1119 cases except for parameters, it is possible to have a register copy
1120 insn referencing a hard register that is not allowed to contain the
1121 mode being copied and which would not be valid as an operand of most
1122 insns. Eliminate this problem by not combining with such an insn.
1124 Also, on some machines we don't want to extend the life of a hard
1127 if (GET_CODE (src) == REG
1128 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1129 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1130 /* Don't extend the life of a hard register unless it is
1131 user variable (if we have few registers) or it can't
1132 fit into the desired register (meaning something special
1134 Also avoid substituting a return register into I3, because
1135 reload can't handle a conflict with constraints of other
1137 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1138 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1141 else if (GET_CODE (dest) != CC0)
1144 /* Don't substitute for a register intended as a clobberable operand.
1145 Similarly, don't substitute an expression containing a register that
1146 will be clobbered in I3. */
1147 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1148 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1149 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
1150 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
1152 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
1155 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1156 or not), reject, unless nothing volatile comes between it and I3 */
1158 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1160 /* Make sure succ doesn't contain a volatile reference. */
1161 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1164 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1165 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1169 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1170 to be an explicit register variable, and was chosen for a reason. */
1172 if (GET_CODE (src) == ASM_OPERANDS
1173 && GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1176 /* If there are any volatile insns between INSN and I3, reject, because
1177 they might affect machine state. */
1179 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1180 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1183 /* If INSN or I2 contains an autoincrement or autodecrement,
1184 make sure that register is not used between there and I3,
1185 and not already used in I3 either.
1186 Also insist that I3 not be a jump; if it were one
1187 and the incremented register were spilled, we would lose. */
1190 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1191 if (REG_NOTE_KIND (link) == REG_INC
1192 && (GET_CODE (i3) == JUMP_INSN
1193 || reg_used_between_p (XEXP (link, 0), insn, i3)
1194 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1199 /* Don't combine an insn that follows a CC0-setting insn.
1200 An insn that uses CC0 must not be separated from the one that sets it.
1201 We do, however, allow I2 to follow a CC0-setting insn if that insn
1202 is passed as I1; in that case it will be deleted also.
1203 We also allow combining in this case if all the insns are adjacent
1204 because that would leave the two CC0 insns adjacent as well.
1205 It would be more logical to test whether CC0 occurs inside I1 or I2,
1206 but that would be much slower, and this ought to be equivalent. */
1208 p = prev_nonnote_insn (insn);
1209 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
1214 /* If we get here, we have passed all the tests and the combination is
1223 /* Check if PAT is an insn - or a part of it - used to set up an
1224 argument for a function in a hard register. */
1227 sets_function_arg_p (pat)
1233 switch (GET_CODE (pat))
1236 return sets_function_arg_p (PATTERN (pat));
1239 for (i = XVECLEN (pat, 0); --i >= 0;)
1240 if (sets_function_arg_p (XVECEXP (pat, 0, i)))
1246 inner_dest = SET_DEST (pat);
1247 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1248 || GET_CODE (inner_dest) == SUBREG
1249 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1250 inner_dest = XEXP (inner_dest, 0);
1252 return (GET_CODE (inner_dest) == REG
1253 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1254 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest)));
1263 /* LOC is the location within I3 that contains its pattern or the component
1264 of a PARALLEL of the pattern. We validate that it is valid for combining.
1266 One problem is if I3 modifies its output, as opposed to replacing it
1267 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1268 so would produce an insn that is not equivalent to the original insns.
1272 (set (reg:DI 101) (reg:DI 100))
1273 (set (subreg:SI (reg:DI 101) 0) <foo>)
1275 This is NOT equivalent to:
1277 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1278 (set (reg:DI 101) (reg:DI 100))])
1280 Not only does this modify 100 (in which case it might still be valid
1281 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1283 We can also run into a problem if I2 sets a register that I1
1284 uses and I1 gets directly substituted into I3 (not via I2). In that
1285 case, we would be getting the wrong value of I2DEST into I3, so we
1286 must reject the combination. This case occurs when I2 and I1 both
1287 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1288 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1289 of a SET must prevent combination from occurring.
1291 Before doing the above check, we first try to expand a field assignment
1292 into a set of logical operations.
1294 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1295 we place a register that is both set and used within I3. If more than one
1296 such register is detected, we fail.
1298 Return 1 if the combination is valid, zero otherwise. */
1301 combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
1307 rtx *pi3dest_killed;
1311 if (GET_CODE (x) == SET)
1313 rtx set = expand_field_assignment (x);
1314 rtx dest = SET_DEST (set);
1315 rtx src = SET_SRC (set);
1316 rtx inner_dest = dest;
1319 rtx inner_src = src;
1324 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1325 || GET_CODE (inner_dest) == SUBREG
1326 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1327 inner_dest = XEXP (inner_dest, 0);
1329 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1332 while (GET_CODE (inner_src) == STRICT_LOW_PART
1333 || GET_CODE (inner_src) == SUBREG
1334 || GET_CODE (inner_src) == ZERO_EXTRACT)
1335 inner_src = XEXP (inner_src, 0);
1337 /* If it is better that two different modes keep two different pseudos,
1338 avoid combining them. This avoids producing the following pattern
1340 (set (subreg:SI (reg/v:QI 21) 0)
1341 (lshiftrt:SI (reg/v:SI 20)
1343 If that were made, reload could not handle the pair of
1344 reg 20/21, since it would try to get any GENERAL_REGS
1345 but some of them don't handle QImode. */
1347 if (rtx_equal_p (inner_src, i2dest)
1348 && GET_CODE (inner_dest) == REG
1349 && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
1353 /* Check for the case where I3 modifies its output, as
1355 if ((inner_dest != dest
1356 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1357 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1359 /* This is the same test done in can_combine_p except we can't test
1360 all_adjacent; we don't have to, since this instruction will stay
1361 in place, thus we are not considering increasing the lifetime of
1364 Also, if this insn sets a function argument, combining it with
1365 something that might need a spill could clobber a previous
1366 function argument; the all_adjacent test in can_combine_p also
1367 checks this; here, we do a more specific test for this case. */
1369 || (GET_CODE (inner_dest) == REG
1370 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1371 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1372 GET_MODE (inner_dest))))
1373 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1376 /* If DEST is used in I3, it is being killed in this insn,
1377 so record that for later.
1378 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1379 STACK_POINTER_REGNUM, since these are always considered to be
1380 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1381 if (pi3dest_killed && GET_CODE (dest) == REG
1382 && reg_referenced_p (dest, PATTERN (i3))
1383 && REGNO (dest) != FRAME_POINTER_REGNUM
1384 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1385 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1387 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1388 && (REGNO (dest) != ARG_POINTER_REGNUM
1389 || ! fixed_regs [REGNO (dest)])
1391 && REGNO (dest) != STACK_POINTER_REGNUM)
1393 if (*pi3dest_killed)
1396 *pi3dest_killed = dest;
1400 else if (GET_CODE (x) == PARALLEL)
1404 for (i = 0; i < XVECLEN (x, 0); i++)
1405 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1406 i1_not_in_src, pi3dest_killed))
1413 /* Return 1 if X is an arithmetic expression that contains a multiplication
1414 and division. We don't count multiplications by powers of two here. */
1420 switch (GET_CODE (x))
1422 case MOD: case DIV: case UMOD: case UDIV:
1426 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1427 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1429 switch (GET_RTX_CLASS (GET_CODE (x)))
1431 case 'c': case '<': case '2':
1432 return contains_muldiv (XEXP (x, 0))
1433 || contains_muldiv (XEXP (x, 1));
1436 return contains_muldiv (XEXP (x, 0));
1444 /* Determine whether INSN can be used in a combination. Return nonzero if
1445 not. This is used in try_combine to detect early some cases where we
1446 can't perform combinations. */
1449 cant_combine_insn_p (insn)
1455 /* If this isn't really an insn, we can't do anything.
1456 This can occur when flow deletes an insn that it has merged into an
1457 auto-increment address. */
1458 if (! INSN_P (insn))
1461 /* Never combine loads and stores involving hard regs. The register
1462 allocator can usually handle such reg-reg moves by tying. If we allow
1463 the combiner to make substitutions of hard regs, we risk aborting in
1464 reload on machines that have SMALL_REGISTER_CLASSES.
1465 As an exception, we allow combinations involving fixed regs; these are
1466 not available to the register allocator so there's no risk involved. */
1468 set = single_set (insn);
1471 src = SET_SRC (set);
1472 dest = SET_DEST (set);
1473 if (GET_CODE (src) == SUBREG)
1474 src = SUBREG_REG (src);
1475 if (GET_CODE (dest) == SUBREG)
1476 dest = SUBREG_REG (dest);
1477 if (REG_P (src) && REG_P (dest)
1478 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
1479 && ! fixed_regs[REGNO (src)])
1480 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
1481 && ! fixed_regs[REGNO (dest)])))
1487 /* Try to combine the insns I1 and I2 into I3.
1488 Here I1 and I2 appear earlier than I3.
1489 I1 can be zero; then we combine just I2 into I3.
1491 If we are combining three insns and the resulting insn is not recognized,
1492 try splitting it into two insns. If that happens, I2 and I3 are retained
1493 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1496 Return 0 if the combination does not work. Then nothing is changed.
1497 If we did the combination, return the insn at which combine should
1500 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1501 new direct jump instruction. */
1504 try_combine (i3, i2, i1, new_direct_jump_p)
1506 int *new_direct_jump_p;
1508 /* New patterns for I3 and I2, respectively. */
1509 rtx newpat, newi2pat = 0;
1510 int substed_i2 = 0, substed_i1 = 0;
1511 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1512 int added_sets_1, added_sets_2;
1513 /* Total number of SETs to put into I3. */
1515 /* Nonzero is I2's body now appears in I3. */
1517 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1518 int insn_code_number, i2_code_number = 0, other_code_number = 0;
1519 /* Contains I3 if the destination of I3 is used in its source, which means
1520 that the old life of I3 is being killed. If that usage is placed into
1521 I2 and not in I3, a REG_DEAD note must be made. */
1522 rtx i3dest_killed = 0;
1523 /* SET_DEST and SET_SRC of I2 and I1. */
1524 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1525 /* PATTERN (I2), or a copy of it in certain cases. */
1527 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1528 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1529 int i1_feeds_i3 = 0;
1530 /* Notes that must be added to REG_NOTES in I3 and I2. */
1531 rtx new_i3_notes, new_i2_notes;
1532 /* Notes that we substituted I3 into I2 instead of the normal case. */
1533 int i3_subst_into_i2 = 0;
1534 /* Notes that I1, I2 or I3 is a MULT operation. */
1542 /* Exit early if one of the insns involved can't be used for
1544 if (cant_combine_insn_p (i3)
1545 || cant_combine_insn_p (i2)
1546 || (i1 && cant_combine_insn_p (i1))
1547 /* We also can't do anything if I3 has a
1548 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1551 /* ??? This gives worse code, and appears to be unnecessary, since no
1552 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1553 || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1559 undobuf.other_insn = 0;
1561 /* Reset the hard register usage information. */
1562 CLEAR_HARD_REG_SET (newpat_used_regs);
1564 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1565 code below, set I1 to be the earlier of the two insns. */
1566 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1567 temp = i1, i1 = i2, i2 = temp;
1569 added_links_insn = 0;
1571 /* First check for one important special-case that the code below will
1572 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1573 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1574 we may be able to replace that destination with the destination of I3.
1575 This occurs in the common code where we compute both a quotient and
1576 remainder into a structure, in which case we want to do the computation
1577 directly into the structure to avoid register-register copies.
1579 Note that this case handles both multiple sets in I2 and also
1580 cases where I2 has a number of CLOBBER or PARALLELs.
1582 We make very conservative checks below and only try to handle the
1583 most common cases of this. For example, we only handle the case
1584 where I2 and I3 are adjacent to avoid making difficult register
1587 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1588 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1589 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1590 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1591 && GET_CODE (PATTERN (i2)) == PARALLEL
1592 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1593 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1594 below would need to check what is inside (and reg_overlap_mentioned_p
1595 doesn't support those codes anyway). Don't allow those destinations;
1596 the resulting insn isn't likely to be recognized anyway. */
1597 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1598 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1599 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1600 SET_DEST (PATTERN (i3)))
1601 && next_real_insn (i2) == i3)
1603 rtx p2 = PATTERN (i2);
1605 /* Make sure that the destination of I3,
1606 which we are going to substitute into one output of I2,
1607 is not used within another output of I2. We must avoid making this:
1608 (parallel [(set (mem (reg 69)) ...)
1609 (set (reg 69) ...)])
1610 which is not well-defined as to order of actions.
1611 (Besides, reload can't handle output reloads for this.)
1613 The problem can also happen if the dest of I3 is a memory ref,
1614 if another dest in I2 is an indirect memory ref. */
1615 for (i = 0; i < XVECLEN (p2, 0); i++)
1616 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1617 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1618 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1619 SET_DEST (XVECEXP (p2, 0, i))))
1622 if (i == XVECLEN (p2, 0))
1623 for (i = 0; i < XVECLEN (p2, 0); i++)
1624 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1625 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1626 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1631 subst_low_cuid = INSN_CUID (i2);
1633 added_sets_2 = added_sets_1 = 0;
1634 i2dest = SET_SRC (PATTERN (i3));
1636 /* Replace the dest in I2 with our dest and make the resulting
1637 insn the new pattern for I3. Then skip to where we
1638 validate the pattern. Everything was set up above. */
1639 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1640 SET_DEST (PATTERN (i3)));
1643 i3_subst_into_i2 = 1;
1644 goto validate_replacement;
1648 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1649 one of those words to another constant, merge them by making a new
1652 && (temp = single_set (i2)) != 0
1653 && (GET_CODE (SET_SRC (temp)) == CONST_INT
1654 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1655 && GET_CODE (SET_DEST (temp)) == REG
1656 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp))) == MODE_INT
1657 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp))) == 2 * UNITS_PER_WORD
1658 && GET_CODE (PATTERN (i3)) == SET
1659 && GET_CODE (SET_DEST (PATTERN (i3))) == SUBREG
1660 && SUBREG_REG (SET_DEST (PATTERN (i3))) == SET_DEST (temp)
1661 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3)))) == MODE_INT
1662 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3)))) == UNITS_PER_WORD
1663 && GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT)
1665 HOST_WIDE_INT lo, hi;
1667 if (GET_CODE (SET_SRC (temp)) == CONST_INT)
1668 lo = INTVAL (SET_SRC (temp)), hi = lo < 0 ? -1 : 0;
1671 lo = CONST_DOUBLE_LOW (SET_SRC (temp));
1672 hi = CONST_DOUBLE_HIGH (SET_SRC (temp));
1675 if (subreg_lowpart_p (SET_DEST (PATTERN (i3))))
1677 /* We don't handle the case of the target word being wider
1678 than a host wide int. */
1679 if (HOST_BITS_PER_WIDE_INT < BITS_PER_WORD)
1682 lo &= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1683 lo |= (INTVAL (SET_SRC (PATTERN (i3)))
1684 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1686 else if (HOST_BITS_PER_WIDE_INT == BITS_PER_WORD)
1687 hi = INTVAL (SET_SRC (PATTERN (i3)));
1688 else if (HOST_BITS_PER_WIDE_INT >= 2 * BITS_PER_WORD)
1690 int sign = -(int) ((unsigned HOST_WIDE_INT) lo
1691 >> (HOST_BITS_PER_WIDE_INT - 1));
1693 lo &= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1694 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1695 lo |= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1696 (INTVAL (SET_SRC (PATTERN (i3)))));
1698 hi = lo < 0 ? -1 : 0;
1701 /* We don't handle the case of the higher word not fitting
1702 entirely in either hi or lo. */
1707 subst_low_cuid = INSN_CUID (i2);
1708 added_sets_2 = added_sets_1 = 0;
1709 i2dest = SET_DEST (temp);
1711 SUBST (SET_SRC (temp),
1712 immed_double_const (lo, hi, GET_MODE (SET_DEST (temp))));
1714 newpat = PATTERN (i2);
1715 goto validate_replacement;
1719 /* If we have no I1 and I2 looks like:
1720 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1722 make up a dummy I1 that is
1725 (set (reg:CC X) (compare:CC Y (const_int 0)))
1727 (We can ignore any trailing CLOBBERs.)
1729 This undoes a previous combination and allows us to match a branch-and-
1732 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1733 && XVECLEN (PATTERN (i2), 0) >= 2
1734 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1735 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1737 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1738 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1739 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1740 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1741 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1742 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1744 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1745 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1750 /* We make I1 with the same INSN_UID as I2. This gives it
1751 the same INSN_CUID for value tracking. Our fake I1 will
1752 never appear in the insn stream so giving it the same INSN_UID
1753 as I2 will not cause a problem. */
1755 subst_prev_insn = i1
1756 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1757 BLOCK_FOR_INSN (i2), INSN_SCOPE (i2),
1758 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
1761 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1762 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1763 SET_DEST (PATTERN (i1)));
1768 /* Verify that I2 and I1 are valid for combining. */
1769 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1770 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1776 /* Record whether I2DEST is used in I2SRC and similarly for the other
1777 cases. Knowing this will help in register status updating below. */
1778 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1779 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1780 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1782 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1784 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1786 /* Ensure that I3's pattern can be the destination of combines. */
1787 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1788 i1 && i2dest_in_i1src && i1_feeds_i3,
1795 /* See if any of the insns is a MULT operation. Unless one is, we will
1796 reject a combination that is, since it must be slower. Be conservative
1798 if (GET_CODE (i2src) == MULT
1799 || (i1 != 0 && GET_CODE (i1src) == MULT)
1800 || (GET_CODE (PATTERN (i3)) == SET
1801 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1804 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1805 We used to do this EXCEPT in one case: I3 has a post-inc in an
1806 output operand. However, that exception can give rise to insns like
1808 which is a famous insn on the PDP-11 where the value of r3 used as the
1809 source was model-dependent. Avoid this sort of thing. */
1812 if (!(GET_CODE (PATTERN (i3)) == SET
1813 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1814 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1815 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1816 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1817 /* It's not the exception. */
1820 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1821 if (REG_NOTE_KIND (link) == REG_INC
1822 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1824 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1831 /* See if the SETs in I1 or I2 need to be kept around in the merged
1832 instruction: whenever the value set there is still needed past I3.
1833 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1835 For the SET in I1, we have two cases: If I1 and I2 independently
1836 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1837 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1838 in I1 needs to be kept around unless I1DEST dies or is set in either
1839 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1840 I1DEST. If so, we know I1 feeds into I2. */
1842 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1845 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1846 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1848 /* If the set in I2 needs to be kept around, we must make a copy of
1849 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1850 PATTERN (I2), we are only substituting for the original I1DEST, not into
1851 an already-substituted copy. This also prevents making self-referential
1852 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1855 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1856 ? gen_rtx_SET (VOIDmode, i2dest, i2src)
1860 i2pat = copy_rtx (i2pat);
1864 /* Substitute in the latest insn for the regs set by the earlier ones. */
1866 maxreg = max_reg_num ();
1870 /* It is possible that the source of I2 or I1 may be performing an
1871 unneeded operation, such as a ZERO_EXTEND of something that is known
1872 to have the high part zero. Handle that case by letting subst look at
1873 the innermost one of them.
1875 Another way to do this would be to have a function that tries to
1876 simplify a single insn instead of merging two or more insns. We don't
1877 do this because of the potential of infinite loops and because
1878 of the potential extra memory required. However, doing it the way
1879 we are is a bit of a kludge and doesn't catch all cases.
1881 But only do this if -fexpensive-optimizations since it slows things down
1882 and doesn't usually win. */
1884 if (flag_expensive_optimizations)
1886 /* Pass pc_rtx so no substitutions are done, just simplifications.
1887 The cases that we are interested in here do not involve the few
1888 cases were is_replaced is checked. */
1891 subst_low_cuid = INSN_CUID (i1);
1892 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1896 subst_low_cuid = INSN_CUID (i2);
1897 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1902 /* Many machines that don't use CC0 have insns that can both perform an
1903 arithmetic operation and set the condition code. These operations will
1904 be represented as a PARALLEL with the first element of the vector
1905 being a COMPARE of an arithmetic operation with the constant zero.
1906 The second element of the vector will set some pseudo to the result
1907 of the same arithmetic operation. If we simplify the COMPARE, we won't
1908 match such a pattern and so will generate an extra insn. Here we test
1909 for this case, where both the comparison and the operation result are
1910 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1911 I2SRC. Later we will make the PARALLEL that contains I2. */
1913 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1914 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1915 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1916 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1918 #ifdef EXTRA_CC_MODES
1920 enum machine_mode compare_mode;
1923 newpat = PATTERN (i3);
1924 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1928 #ifdef EXTRA_CC_MODES
1929 /* See if a COMPARE with the operand we substituted in should be done
1930 with the mode that is currently being used. If not, do the same
1931 processing we do in `subst' for a SET; namely, if the destination
1932 is used only once, try to replace it with a register of the proper
1933 mode and also replace the COMPARE. */
1934 if (undobuf.other_insn == 0
1935 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1936 &undobuf.other_insn))
1937 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1939 != GET_MODE (SET_DEST (newpat))))
1941 unsigned int regno = REGNO (SET_DEST (newpat));
1942 rtx new_dest = gen_rtx_REG (compare_mode, regno);
1944 if (regno < FIRST_PSEUDO_REGISTER
1945 || (REG_N_SETS (regno) == 1 && ! added_sets_2
1946 && ! REG_USERVAR_P (SET_DEST (newpat))))
1948 if (regno >= FIRST_PSEUDO_REGISTER)
1949 SUBST (regno_reg_rtx[regno], new_dest);
1951 SUBST (SET_DEST (newpat), new_dest);
1952 SUBST (XEXP (*cc_use, 0), new_dest);
1953 SUBST (SET_SRC (newpat),
1954 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
1957 undobuf.other_insn = 0;
1964 n_occurrences = 0; /* `subst' counts here */
1966 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1967 need to make a unique copy of I2SRC each time we substitute it
1968 to avoid self-referential rtl. */
1970 subst_low_cuid = INSN_CUID (i2);
1971 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1972 ! i1_feeds_i3 && i1dest_in_i1src);
1975 /* Record whether i2's body now appears within i3's body. */
1976 i2_is_used = n_occurrences;
1979 /* If we already got a failure, don't try to do more. Otherwise,
1980 try to substitute in I1 if we have it. */
1982 if (i1 && GET_CODE (newpat) != CLOBBER)
1984 /* Before we can do this substitution, we must redo the test done
1985 above (see detailed comments there) that ensures that I1DEST
1986 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1988 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1996 subst_low_cuid = INSN_CUID (i1);
1997 newpat = subst (newpat, i1dest, i1src, 0, 0);
2001 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2002 to count all the ways that I2SRC and I1SRC can be used. */
2003 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
2004 && i2_is_used + added_sets_2 > 1)
2005 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2006 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
2008 /* Fail if we tried to make a new register (we used to abort, but there's
2009 really no reason to). */
2010 || max_reg_num () != maxreg
2011 /* Fail if we couldn't do something and have a CLOBBER. */
2012 || GET_CODE (newpat) == CLOBBER
2013 /* Fail if this new pattern is a MULT and we didn't have one before
2014 at the outer level. */
2015 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
2022 /* If the actions of the earlier insns must be kept
2023 in addition to substituting them into the latest one,
2024 we must make a new PARALLEL for the latest insn
2025 to hold additional the SETs. */
2027 if (added_sets_1 || added_sets_2)
2031 if (GET_CODE (newpat) == PARALLEL)
2033 rtvec old = XVEC (newpat, 0);
2034 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2035 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2036 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
2037 sizeof (old->elem[0]) * old->num_elem);
2042 total_sets = 1 + added_sets_1 + added_sets_2;
2043 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2044 XVECEXP (newpat, 0, 0) = old;
2048 XVECEXP (newpat, 0, --total_sets)
2049 = (GET_CODE (PATTERN (i1)) == PARALLEL
2050 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
2054 /* If there is no I1, use I2's body as is. We used to also not do
2055 the subst call below if I2 was substituted into I3,
2056 but that could lose a simplification. */
2058 XVECEXP (newpat, 0, --total_sets) = i2pat;
2060 /* See comment where i2pat is assigned. */
2061 XVECEXP (newpat, 0, --total_sets)
2062 = subst (i2pat, i1dest, i1src, 0, 0);
2066 /* We come here when we are replacing a destination in I2 with the
2067 destination of I3. */
2068 validate_replacement:
2070 /* Note which hard regs this insn has as inputs. */
2071 mark_used_regs_combine (newpat);
2073 /* Is the result of combination a valid instruction? */
2074 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2076 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2077 the second SET's destination is a register that is unused. In that case,
2078 we just need the first SET. This can occur when simplifying a divmod
2079 insn. We *must* test for this case here because the code below that
2080 splits two independent SETs doesn't handle this case correctly when it
2081 updates the register status. Also check the case where the first
2082 SET's destination is unused. That would not cause incorrect code, but
2083 does cause an unneeded insn to remain. */
2085 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2086 && XVECLEN (newpat, 0) == 2
2087 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2088 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2089 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
2090 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
2091 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
2092 && asm_noperands (newpat) < 0)
2094 newpat = XVECEXP (newpat, 0, 0);
2095 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2098 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2099 && XVECLEN (newpat, 0) == 2
2100 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2101 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2102 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
2103 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
2104 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
2105 && asm_noperands (newpat) < 0)
2107 newpat = XVECEXP (newpat, 0, 1);
2108 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2111 /* If we were combining three insns and the result is a simple SET
2112 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2113 insns. There are two ways to do this. It can be split using a
2114 machine-specific method (like when you have an addition of a large
2115 constant) or by combine in the function find_split_point. */
2117 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2118 && asm_noperands (newpat) < 0)
2120 rtx m_split, *split;
2121 rtx ni2dest = i2dest;
2123 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2124 use I2DEST as a scratch register will help. In the latter case,
2125 convert I2DEST to the mode of the source of NEWPAT if we can. */
2127 m_split = split_insns (newpat, i3);
2129 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2130 inputs of NEWPAT. */
2132 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2133 possible to try that as a scratch reg. This would require adding
2134 more code to make it work though. */
2136 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
2138 /* If I2DEST is a hard register or the only use of a pseudo,
2139 we can change its mode. */
2140 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
2141 && GET_MODE (SET_DEST (newpat)) != VOIDmode
2142 && GET_CODE (i2dest) == REG
2143 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2144 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2145 && ! REG_USERVAR_P (i2dest))))
2146 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
2149 m_split = split_insns (gen_rtx_PARALLEL
2151 gen_rtvec (2, newpat,
2152 gen_rtx_CLOBBER (VOIDmode,
2155 /* If the split with the mode-changed register didn't work, try
2156 the original register. */
2157 if (! m_split && ni2dest != i2dest)
2160 m_split = split_insns (gen_rtx_PARALLEL
2162 gen_rtvec (2, newpat,
2163 gen_rtx_CLOBBER (VOIDmode,
2169 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
2171 m_split = PATTERN (m_split);
2172 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
2173 if (insn_code_number >= 0)
2176 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
2177 && (next_real_insn (i2) == i3
2178 || ! use_crosses_set_p (PATTERN (m_split), INSN_CUID (i2))))
2181 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
2182 newi2pat = PATTERN (m_split);
2184 i3set = single_set (NEXT_INSN (m_split));
2185 i2set = single_set (m_split);
2187 /* In case we changed the mode of I2DEST, replace it in the
2188 pseudo-register table here. We can't do it above in case this
2189 code doesn't get executed and we do a split the other way. */
2191 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2192 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
2194 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2196 /* If I2 or I3 has multiple SETs, we won't know how to track
2197 register status, so don't use these insns. If I2's destination
2198 is used between I2 and I3, we also can't use these insns. */
2200 if (i2_code_number >= 0 && i2set && i3set
2201 && (next_real_insn (i2) == i3
2202 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2203 insn_code_number = recog_for_combine (&newi3pat, i3,
2205 if (insn_code_number >= 0)
2208 /* It is possible that both insns now set the destination of I3.
2209 If so, we must show an extra use of it. */
2211 if (insn_code_number >= 0)
2213 rtx new_i3_dest = SET_DEST (i3set);
2214 rtx new_i2_dest = SET_DEST (i2set);
2216 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2217 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2218 || GET_CODE (new_i3_dest) == SUBREG)
2219 new_i3_dest = XEXP (new_i3_dest, 0);
2221 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2222 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2223 || GET_CODE (new_i2_dest) == SUBREG)
2224 new_i2_dest = XEXP (new_i2_dest, 0);
2226 if (GET_CODE (new_i3_dest) == REG
2227 && GET_CODE (new_i2_dest) == REG
2228 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2229 REG_N_SETS (REGNO (new_i2_dest))++;
2233 /* If we can split it and use I2DEST, go ahead and see if that
2234 helps things be recognized. Verify that none of the registers
2235 are set between I2 and I3. */
2236 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2238 && GET_CODE (i2dest) == REG
2240 /* We need I2DEST in the proper mode. If it is a hard register
2241 or the only use of a pseudo, we can change its mode. */
2242 && (GET_MODE (*split) == GET_MODE (i2dest)
2243 || GET_MODE (*split) == VOIDmode
2244 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2245 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2246 && ! REG_USERVAR_P (i2dest)))
2247 && (next_real_insn (i2) == i3
2248 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2249 /* We can't overwrite I2DEST if its value is still used by
2251 && ! reg_referenced_p (i2dest, newpat))
2253 rtx newdest = i2dest;
2254 enum rtx_code split_code = GET_CODE (*split);
2255 enum machine_mode split_mode = GET_MODE (*split);
2257 /* Get NEWDEST as a register in the proper mode. We have already
2258 validated that we can do this. */
2259 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2261 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2263 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2264 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
2267 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2268 an ASHIFT. This can occur if it was inside a PLUS and hence
2269 appeared to be a memory address. This is a kludge. */
2270 if (split_code == MULT
2271 && GET_CODE (XEXP (*split, 1)) == CONST_INT
2272 && INTVAL (XEXP (*split, 1)) > 0
2273 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2275 SUBST (*split, gen_rtx_ASHIFT (split_mode,
2276 XEXP (*split, 0), GEN_INT (i)));
2277 /* Update split_code because we may not have a multiply
2279 split_code = GET_CODE (*split);
2282 #ifdef INSN_SCHEDULING
2283 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2284 be written as a ZERO_EXTEND. */
2285 if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM)
2287 #ifdef LOAD_EXTEND_OP
2288 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2289 what it really is. */
2290 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
2292 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
2293 SUBREG_REG (*split)));
2296 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
2297 SUBREG_REG (*split)));
2301 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
2302 SUBST (*split, newdest);
2303 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2305 /* If the split point was a MULT and we didn't have one before,
2306 don't use one now. */
2307 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2308 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2312 /* Check for a case where we loaded from memory in a narrow mode and
2313 then sign extended it, but we need both registers. In that case,
2314 we have a PARALLEL with both loads from the same memory location.
2315 We can split this into a load from memory followed by a register-register
2316 copy. This saves at least one insn, more if register allocation can
2319 We cannot do this if the destination of the first assignment is a
2320 condition code register or cc0. We eliminate this case by making sure
2321 the SET_DEST and SET_SRC have the same mode.
2323 We cannot do this if the destination of the second assignment is
2324 a register that we have already assumed is zero-extended. Similarly
2325 for a SUBREG of such a register. */
2327 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2328 && GET_CODE (newpat) == PARALLEL
2329 && XVECLEN (newpat, 0) == 2
2330 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2331 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2332 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
2333 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
2334 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2335 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2336 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2337 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2339 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2340 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2341 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2342 (GET_CODE (temp) == REG
2343 && reg_nonzero_bits[REGNO (temp)] != 0
2344 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2345 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2346 && (reg_nonzero_bits[REGNO (temp)]
2347 != GET_MODE_MASK (word_mode))))
2348 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2349 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2350 (GET_CODE (temp) == REG
2351 && reg_nonzero_bits[REGNO (temp)] != 0
2352 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2353 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2354 && (reg_nonzero_bits[REGNO (temp)]
2355 != GET_MODE_MASK (word_mode)))))
2356 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2357 SET_SRC (XVECEXP (newpat, 0, 1)))
2358 && ! find_reg_note (i3, REG_UNUSED,
2359 SET_DEST (XVECEXP (newpat, 0, 0))))
2363 newi2pat = XVECEXP (newpat, 0, 0);
2364 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2365 newpat = XVECEXP (newpat, 0, 1);
2366 SUBST (SET_SRC (newpat),
2367 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
2368 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2370 if (i2_code_number >= 0)
2371 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2373 if (insn_code_number >= 0)
2378 /* If we will be able to accept this, we have made a change to the
2379 destination of I3. This can invalidate a LOG_LINKS pointing
2380 to I3. No other part of combine.c makes such a transformation.
2382 The new I3 will have a destination that was previously the
2383 destination of I1 or I2 and which was used in i2 or I3. Call
2384 distribute_links to make a LOG_LINK from the next use of
2385 that destination. */
2387 PATTERN (i3) = newpat;
2388 distribute_links (gen_rtx_INSN_LIST (VOIDmode, i3, NULL_RTX));
2390 /* I3 now uses what used to be its destination and which is
2391 now I2's destination. That means we need a LOG_LINK from
2392 I3 to I2. But we used to have one, so we still will.
2394 However, some later insn might be using I2's dest and have
2395 a LOG_LINK pointing at I3. We must remove this link.
2396 The simplest way to remove the link is to point it at I1,
2397 which we know will be a NOTE. */
2399 for (insn = NEXT_INSN (i3);
2400 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
2401 || insn != this_basic_block->next_bb->head);
2402 insn = NEXT_INSN (insn))
2404 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
2406 for (link = LOG_LINKS (insn); link;
2407 link = XEXP (link, 1))
2408 if (XEXP (link, 0) == i3)
2409 XEXP (link, 0) = i1;
2417 /* Similarly, check for a case where we have a PARALLEL of two independent
2418 SETs but we started with three insns. In this case, we can do the sets
2419 as two separate insns. This case occurs when some SET allows two
2420 other insns to combine, but the destination of that SET is still live. */
2422 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2423 && GET_CODE (newpat) == PARALLEL
2424 && XVECLEN (newpat, 0) == 2
2425 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2426 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2427 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2428 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2429 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2430 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2431 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2433 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2434 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2435 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2436 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2437 XVECEXP (newpat, 0, 0))
2438 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2439 XVECEXP (newpat, 0, 1))
2440 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2441 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
2443 /* Normally, it doesn't matter which of the two is done first,
2444 but it does if one references cc0. In that case, it has to
2447 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2449 newi2pat = XVECEXP (newpat, 0, 0);
2450 newpat = XVECEXP (newpat, 0, 1);
2455 newi2pat = XVECEXP (newpat, 0, 1);
2456 newpat = XVECEXP (newpat, 0, 0);
2459 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2461 if (i2_code_number >= 0)
2462 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2465 /* If it still isn't recognized, fail and change things back the way they
2467 if ((insn_code_number < 0
2468 /* Is the result a reasonable ASM_OPERANDS? */
2469 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2475 /* If we had to change another insn, make sure it is valid also. */
2476 if (undobuf.other_insn)
2478 rtx other_pat = PATTERN (undobuf.other_insn);
2479 rtx new_other_notes;
2482 CLEAR_HARD_REG_SET (newpat_used_regs);
2484 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2487 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2493 PATTERN (undobuf.other_insn) = other_pat;
2495 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2496 are still valid. Then add any non-duplicate notes added by
2497 recog_for_combine. */
2498 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2500 next = XEXP (note, 1);
2502 if (REG_NOTE_KIND (note) == REG_UNUSED
2503 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2505 if (GET_CODE (XEXP (note, 0)) == REG)
2506 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2508 remove_note (undobuf.other_insn, note);
2512 for (note = new_other_notes; note; note = XEXP (note, 1))
2513 if (GET_CODE (XEXP (note, 0)) == REG)
2514 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2516 distribute_notes (new_other_notes, undobuf.other_insn,
2517 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2520 /* If I2 is the setter CC0 and I3 is the user CC0 then check whether
2521 they are adjacent to each other or not. */
2523 rtx p = prev_nonnote_insn (i3);
2524 if (p && p != i2 && GET_CODE (p) == INSN && newi2pat
2525 && sets_cc0_p (newi2pat))
2533 /* We now know that we can do this combination. Merge the insns and
2534 update the status of registers and LOG_LINKS. */
2537 rtx i3notes, i2notes, i1notes = 0;
2538 rtx i3links, i2links, i1links = 0;
2541 /* Compute which registers we expect to eliminate. newi2pat may be setting
2542 either i3dest or i2dest, so we must check it. Also, i1dest may be the
2543 same as i3dest, in which case newi2pat may be setting i1dest. */
2544 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
2545 || i2dest_in_i2src || i2dest_in_i1src
2547 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
2548 || (newi2pat && reg_set_p (i1dest, newi2pat))
2551 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2553 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2554 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2556 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2558 /* Ensure that we do not have something that should not be shared but
2559 occurs multiple times in the new insns. Check this by first
2560 resetting all the `used' flags and then copying anything is shared. */
2562 reset_used_flags (i3notes);
2563 reset_used_flags (i2notes);
2564 reset_used_flags (i1notes);
2565 reset_used_flags (newpat);
2566 reset_used_flags (newi2pat);
2567 if (undobuf.other_insn)
2568 reset_used_flags (PATTERN (undobuf.other_insn));
2570 i3notes = copy_rtx_if_shared (i3notes);
2571 i2notes = copy_rtx_if_shared (i2notes);
2572 i1notes = copy_rtx_if_shared (i1notes);
2573 newpat = copy_rtx_if_shared (newpat);
2574 newi2pat = copy_rtx_if_shared (newi2pat);
2575 if (undobuf.other_insn)
2576 reset_used_flags (PATTERN (undobuf.other_insn));
2578 INSN_CODE (i3) = insn_code_number;
2579 PATTERN (i3) = newpat;
2581 if (GET_CODE (i3) == CALL_INSN && CALL_INSN_FUNCTION_USAGE (i3))
2583 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
2585 reset_used_flags (call_usage);
2586 call_usage = copy_rtx (call_usage);
2589 replace_rtx (call_usage, i2dest, i2src);
2592 replace_rtx (call_usage, i1dest, i1src);
2594 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
2597 if (undobuf.other_insn)
2598 INSN_CODE (undobuf.other_insn) = other_code_number;
2600 /* We had one special case above where I2 had more than one set and
2601 we replaced a destination of one of those sets with the destination
2602 of I3. In that case, we have to update LOG_LINKS of insns later
2603 in this basic block. Note that this (expensive) case is rare.
2605 Also, in this case, we must pretend that all REG_NOTEs for I2
2606 actually came from I3, so that REG_UNUSED notes from I2 will be
2607 properly handled. */
2609 if (i3_subst_into_i2)
2611 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2612 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != USE
2613 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
2614 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2615 && ! find_reg_note (i2, REG_UNUSED,
2616 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2617 for (temp = NEXT_INSN (i2);
2618 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
2619 || this_basic_block->head != temp);
2620 temp = NEXT_INSN (temp))
2621 if (temp != i3 && INSN_P (temp))
2622 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2623 if (XEXP (link, 0) == i2)
2624 XEXP (link, 0) = i3;
2629 while (XEXP (link, 1))
2630 link = XEXP (link, 1);
2631 XEXP (link, 1) = i2notes;
2645 INSN_CODE (i2) = i2_code_number;
2646 PATTERN (i2) = newi2pat;
2650 PUT_CODE (i2, NOTE);
2651 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2652 NOTE_SOURCE_FILE (i2) = 0;
2659 PUT_CODE (i1, NOTE);
2660 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2661 NOTE_SOURCE_FILE (i1) = 0;
2664 /* Get death notes for everything that is now used in either I3 or
2665 I2 and used to die in a previous insn. If we built two new
2666 patterns, move from I1 to I2 then I2 to I3 so that we get the
2667 proper movement on registers that I2 modifies. */
2671 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2672 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2675 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2678 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2680 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
2683 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
2686 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
2689 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2692 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2693 know these are REG_UNUSED and want them to go to the desired insn,
2694 so we always pass it as i3. We have not counted the notes in
2695 reg_n_deaths yet, so we need to do so now. */
2697 if (newi2pat && new_i2_notes)
2699 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2700 if (GET_CODE (XEXP (temp, 0)) == REG)
2701 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2703 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2708 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2709 if (GET_CODE (XEXP (temp, 0)) == REG)
2710 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2712 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
2715 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2716 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2717 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2718 in that case, it might delete I2. Similarly for I2 and I1.
2719 Show an additional death due to the REG_DEAD note we make here. If
2720 we discard it in distribute_notes, we will decrement it again. */
2724 if (GET_CODE (i3dest_killed) == REG)
2725 REG_N_DEATHS (REGNO (i3dest_killed))++;
2727 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
2728 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2730 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
2732 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2734 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2738 if (i2dest_in_i2src)
2740 if (GET_CODE (i2dest) == REG)
2741 REG_N_DEATHS (REGNO (i2dest))++;
2743 if (newi2pat && reg_set_p (i2dest, newi2pat))
2744 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2745 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2747 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2748 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2749 NULL_RTX, NULL_RTX);
2752 if (i1dest_in_i1src)
2754 if (GET_CODE (i1dest) == REG)
2755 REG_N_DEATHS (REGNO (i1dest))++;
2757 if (newi2pat && reg_set_p (i1dest, newi2pat))
2758 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2759 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2761 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2762 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2763 NULL_RTX, NULL_RTX);
2766 distribute_links (i3links);
2767 distribute_links (i2links);
2768 distribute_links (i1links);
2770 if (GET_CODE (i2dest) == REG)
2773 rtx i2_insn = 0, i2_val = 0, set;
2775 /* The insn that used to set this register doesn't exist, and
2776 this life of the register may not exist either. See if one of
2777 I3's links points to an insn that sets I2DEST. If it does,
2778 that is now the last known value for I2DEST. If we don't update
2779 this and I2 set the register to a value that depended on its old
2780 contents, we will get confused. If this insn is used, thing
2781 will be set correctly in combine_instructions. */
2783 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2784 if ((set = single_set (XEXP (link, 0))) != 0
2785 && rtx_equal_p (i2dest, SET_DEST (set)))
2786 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2788 record_value_for_reg (i2dest, i2_insn, i2_val);
2790 /* If the reg formerly set in I2 died only once and that was in I3,
2791 zero its use count so it won't make `reload' do any work. */
2793 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2794 && ! i2dest_in_i2src)
2796 regno = REGNO (i2dest);
2797 REG_N_SETS (regno)--;
2801 if (i1 && GET_CODE (i1dest) == REG)
2804 rtx i1_insn = 0, i1_val = 0, set;
2806 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2807 if ((set = single_set (XEXP (link, 0))) != 0
2808 && rtx_equal_p (i1dest, SET_DEST (set)))
2809 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2811 record_value_for_reg (i1dest, i1_insn, i1_val);
2813 regno = REGNO (i1dest);
2814 if (! added_sets_1 && ! i1dest_in_i1src)
2815 REG_N_SETS (regno)--;
2818 /* Update reg_nonzero_bits et al for any changes that may have been made
2819 to this insn. The order of set_nonzero_bits_and_sign_copies() is
2820 important. Because newi2pat can affect nonzero_bits of newpat */
2822 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
2823 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
2825 /* Set new_direct_jump_p if a new return or simple jump instruction
2828 If I3 is now an unconditional jump, ensure that it has a
2829 BARRIER following it since it may have initially been a
2830 conditional jump. It may also be the last nonnote insn. */
2832 if (returnjump_p (i3) || any_uncondjump_p (i3))
2834 *new_direct_jump_p = 1;
2836 if ((temp = next_nonnote_insn (i3)) == NULL_RTX
2837 || GET_CODE (temp) != BARRIER)
2838 emit_barrier_after (i3);
2841 if (undobuf.other_insn != NULL_RTX
2842 && (returnjump_p (undobuf.other_insn)
2843 || any_uncondjump_p (undobuf.other_insn)))
2845 *new_direct_jump_p = 1;
2847 if ((temp = next_nonnote_insn (undobuf.other_insn)) == NULL_RTX
2848 || GET_CODE (temp) != BARRIER)
2849 emit_barrier_after (undobuf.other_insn);
2852 /* An NOOP jump does not need barrier, but it does need cleaning up
2854 if (GET_CODE (newpat) == SET
2855 && SET_SRC (newpat) == pc_rtx
2856 && SET_DEST (newpat) == pc_rtx)
2857 *new_direct_jump_p = 1;
2860 combine_successes++;
2863 /* Clear this here, so that subsequent get_last_value calls are not
2865 subst_prev_insn = NULL_RTX;
2867 if (added_links_insn
2868 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2869 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2870 return added_links_insn;
2872 return newi2pat ? i2 : i3;
2875 /* Undo all the modifications recorded in undobuf. */
2880 struct undo *undo, *next;
2882 for (undo = undobuf.undos; undo; undo = next)
2886 *undo->where.i = undo->old_contents.i;
2888 *undo->where.r = undo->old_contents.r;
2890 undo->next = undobuf.frees;
2891 undobuf.frees = undo;
2896 /* Clear this here, so that subsequent get_last_value calls are not
2898 subst_prev_insn = NULL_RTX;
2901 /* We've committed to accepting the changes we made. Move all
2902 of the undos to the free list. */
2907 struct undo *undo, *next;
2909 for (undo = undobuf.undos; undo; undo = next)
2912 undo->next = undobuf.frees;
2913 undobuf.frees = undo;
2919 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2920 where we have an arithmetic expression and return that point. LOC will
2923 try_combine will call this function to see if an insn can be split into
2927 find_split_point (loc, insn)
2932 enum rtx_code code = GET_CODE (x);
2934 unsigned HOST_WIDE_INT len = 0;
2935 HOST_WIDE_INT pos = 0;
2937 rtx inner = NULL_RTX;
2939 /* First special-case some codes. */
2943 #ifdef INSN_SCHEDULING
2944 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2946 if (GET_CODE (SUBREG_REG (x)) == MEM)
2949 return find_split_point (&SUBREG_REG (x), insn);
2953 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2954 using LO_SUM and HIGH. */
2955 if (GET_CODE (XEXP (x, 0)) == CONST
2956 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2959 gen_rtx_LO_SUM (Pmode,
2960 gen_rtx_HIGH (Pmode, XEXP (x, 0)),
2962 return &XEXP (XEXP (x, 0), 0);
2966 /* If we have a PLUS whose second operand is a constant and the
2967 address is not valid, perhaps will can split it up using
2968 the machine-specific way to split large constants. We use
2969 the first pseudo-reg (one of the virtual regs) as a placeholder;
2970 it will not remain in the result. */
2971 if (GET_CODE (XEXP (x, 0)) == PLUS
2972 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2973 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2975 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2976 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
2979 /* This should have produced two insns, each of which sets our
2980 placeholder. If the source of the second is a valid address,
2981 we can make put both sources together and make a split point
2985 && NEXT_INSN (seq) != NULL_RTX
2986 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
2987 && GET_CODE (seq) == INSN
2988 && GET_CODE (PATTERN (seq)) == SET
2989 && SET_DEST (PATTERN (seq)) == reg
2990 && ! reg_mentioned_p (reg,
2991 SET_SRC (PATTERN (seq)))
2992 && GET_CODE (NEXT_INSN (seq)) == INSN
2993 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
2994 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
2995 && memory_address_p (GET_MODE (x),
2996 SET_SRC (PATTERN (NEXT_INSN (seq)))))
2998 rtx src1 = SET_SRC (PATTERN (seq));
2999 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
3001 /* Replace the placeholder in SRC2 with SRC1. If we can
3002 find where in SRC2 it was placed, that can become our
3003 split point and we can replace this address with SRC2.
3004 Just try two obvious places. */
3006 src2 = replace_rtx (src2, reg, src1);
3008 if (XEXP (src2, 0) == src1)
3009 split = &XEXP (src2, 0);
3010 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
3011 && XEXP (XEXP (src2, 0), 0) == src1)
3012 split = &XEXP (XEXP (src2, 0), 0);
3016 SUBST (XEXP (x, 0), src2);
3021 /* If that didn't work, perhaps the first operand is complex and
3022 needs to be computed separately, so make a split point there.
3023 This will occur on machines that just support REG + CONST
3024 and have a constant moved through some previous computation. */
3026 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
3027 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
3028 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
3030 return &XEXP (XEXP (x, 0), 0);
3036 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3037 ZERO_EXTRACT, the most likely reason why this doesn't match is that
3038 we need to put the operand into a register. So split at that
3041 if (SET_DEST (x) == cc0_rtx
3042 && GET_CODE (SET_SRC (x)) != COMPARE
3043 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
3044 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
3045 && ! (GET_CODE (SET_SRC (x)) == SUBREG
3046 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
3047 return &SET_SRC (x);
3050 /* See if we can split SET_SRC as it stands. */
3051 split = find_split_point (&SET_SRC (x), insn);
3052 if (split && split != &SET_SRC (x))
3055 /* See if we can split SET_DEST as it stands. */
3056 split = find_split_point (&SET_DEST (x), insn);
3057 if (split && split != &SET_DEST (x))
3060 /* See if this is a bitfield assignment with everything constant. If
3061 so, this is an IOR of an AND, so split it into that. */
3062 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
3063 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
3064 <= HOST_BITS_PER_WIDE_INT)
3065 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
3066 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
3067 && GET_CODE (SET_SRC (x)) == CONST_INT
3068 && ((INTVAL (XEXP (SET_DEST (x), 1))
3069 + INTVAL (XEXP (SET_DEST (x), 2)))
3070 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
3071 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
3073 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
3074 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
3075 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
3076 rtx dest = XEXP (SET_DEST (x), 0);
3077 enum machine_mode mode = GET_MODE (dest);
3078 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
3080 if (BITS_BIG_ENDIAN)
3081 pos = GET_MODE_BITSIZE (mode) - len - pos;
3085 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
3088 gen_binary (IOR, mode,
3089 gen_binary (AND, mode, dest,
3090 gen_int_mode (~(mask << pos),
3092 GEN_INT (src << pos)));
3094 SUBST (SET_DEST (x), dest);
3096 split = find_split_point (&SET_SRC (x), insn);
3097 if (split && split != &SET_SRC (x))
3101 /* Otherwise, see if this is an operation that we can split into two.
3102 If so, try to split that. */
3103 code = GET_CODE (SET_SRC (x));
3108 /* If we are AND'ing with a large constant that is only a single
3109 bit and the result is only being used in a context where we
3110 need to know if it is zero or nonzero, replace it with a bit
3111 extraction. This will avoid the large constant, which might
3112 have taken more than one insn to make. If the constant were
3113 not a valid argument to the AND but took only one insn to make,
3114 this is no worse, but if it took more than one insn, it will
3117 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3118 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
3119 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
3120 && GET_CODE (SET_DEST (x)) == REG
3121 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
3122 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
3123 && XEXP (*split, 0) == SET_DEST (x)
3124 && XEXP (*split, 1) == const0_rtx)
3126 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
3127 XEXP (SET_SRC (x), 0),
3128 pos, NULL_RTX, 1, 1, 0, 0);
3129 if (extraction != 0)
3131 SUBST (SET_SRC (x), extraction);
3132 return find_split_point (loc, insn);
3138 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3139 is known to be on, this can be converted into a NEG of a shift. */
3140 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
3141 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
3142 && 1 <= (pos = exact_log2
3143 (nonzero_bits (XEXP (SET_SRC (x), 0),
3144 GET_MODE (XEXP (SET_SRC (x), 0))))))
3146 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
3150 gen_rtx_LSHIFTRT (mode,
3151 XEXP (SET_SRC (x), 0),
3154 split = find_split_point (&SET_SRC (x), insn);
3155 if (split && split != &SET_SRC (x))
3161 inner = XEXP (SET_SRC (x), 0);
3163 /* We can't optimize if either mode is a partial integer
3164 mode as we don't know how many bits are significant
3166 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3167 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3171 len = GET_MODE_BITSIZE (GET_MODE (inner));
3177 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3178 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3180 inner = XEXP (SET_SRC (x), 0);
3181 len = INTVAL (XEXP (SET_SRC (x), 1));
3182 pos = INTVAL (XEXP (SET_SRC (x), 2));
3184 if (BITS_BIG_ENDIAN)
3185 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3186 unsignedp = (code == ZERO_EXTRACT);
3194 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3196 enum machine_mode mode = GET_MODE (SET_SRC (x));
3198 /* For unsigned, we have a choice of a shift followed by an
3199 AND or two shifts. Use two shifts for field sizes where the
3200 constant might be too large. We assume here that we can
3201 always at least get 8-bit constants in an AND insn, which is
3202 true for every current RISC. */
3204 if (unsignedp && len <= 8)
3209 (mode, gen_lowpart_for_combine (mode, inner),
3211 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3213 split = find_split_point (&SET_SRC (x), insn);
3214 if (split && split != &SET_SRC (x))
3221 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3222 gen_rtx_ASHIFT (mode,
3223 gen_lowpart_for_combine (mode, inner),
3224 GEN_INT (GET_MODE_BITSIZE (mode)
3226 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3228 split = find_split_point (&SET_SRC (x), insn);
3229 if (split && split != &SET_SRC (x))
3234 /* See if this is a simple operation with a constant as the second
3235 operand. It might be that this constant is out of range and hence
3236 could be used as a split point. */
3237 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3238 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3239 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
3240 && CONSTANT_P (XEXP (SET_SRC (x), 1))
3241 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
3242 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3243 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
3245 return &XEXP (SET_SRC (x), 1);
3247 /* Finally, see if this is a simple operation with its first operand
3248 not in a register. The operation might require this operand in a
3249 register, so return it as a split point. We can always do this
3250 because if the first operand were another operation, we would have
3251 already found it as a split point. */
3252 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3253 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3254 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
3255 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
3256 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3257 return &XEXP (SET_SRC (x), 0);
3263 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3264 it is better to write this as (not (ior A B)) so we can split it.
3265 Similarly for IOR. */
3266 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3269 gen_rtx_NOT (GET_MODE (x),
3270 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
3272 XEXP (XEXP (x, 0), 0),
3273 XEXP (XEXP (x, 1), 0))));
3274 return find_split_point (loc, insn);
3277 /* Many RISC machines have a large set of logical insns. If the
3278 second operand is a NOT, put it first so we will try to split the
3279 other operand first. */
3280 if (GET_CODE (XEXP (x, 1)) == NOT)
3282 rtx tem = XEXP (x, 0);
3283 SUBST (XEXP (x, 0), XEXP (x, 1));
3284 SUBST (XEXP (x, 1), tem);
3292 /* Otherwise, select our actions depending on our rtx class. */
3293 switch (GET_RTX_CLASS (code))
3295 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3297 split = find_split_point (&XEXP (x, 2), insn);
3300 /* ... fall through ... */
3304 split = find_split_point (&XEXP (x, 1), insn);
3307 /* ... fall through ... */
3309 /* Some machines have (and (shift ...) ...) insns. If X is not
3310 an AND, but XEXP (X, 0) is, use it as our split point. */
3311 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3312 return &XEXP (x, 0);
3314 split = find_split_point (&XEXP (x, 0), insn);
3320 /* Otherwise, we don't have a split point. */
3324 /* Throughout X, replace FROM with TO, and return the result.
3325 The result is TO if X is FROM;
3326 otherwise the result is X, but its contents may have been modified.
3327 If they were modified, a record was made in undobuf so that
3328 undo_all will (among other things) return X to its original state.
3330 If the number of changes necessary is too much to record to undo,
3331 the excess changes are not made, so the result is invalid.
3332 The changes already made can still be undone.
3333 undobuf.num_undo is incremented for such changes, so by testing that
3334 the caller can tell whether the result is valid.
3336 `n_occurrences' is incremented each time FROM is replaced.
3338 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3340 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
3341 by copying if `n_occurrences' is nonzero. */
3344 subst (x, from, to, in_dest, unique_copy)
3349 enum rtx_code code = GET_CODE (x);
3350 enum machine_mode op0_mode = VOIDmode;
3355 /* Two expressions are equal if they are identical copies of a shared
3356 RTX or if they are both registers with the same register number
3359 #define COMBINE_RTX_EQUAL_P(X,Y) \
3361 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3362 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3364 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3367 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3370 /* If X and FROM are the same register but different modes, they will
3371 not have been seen as equal above. However, flow.c will make a
3372 LOG_LINKS entry for that case. If we do nothing, we will try to
3373 rerecognize our original insn and, when it succeeds, we will
3374 delete the feeding insn, which is incorrect.
3376 So force this insn not to match in this (rare) case. */
3377 if (! in_dest && code == REG && GET_CODE (from) == REG
3378 && REGNO (x) == REGNO (from))
3379 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3381 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3382 of which may contain things that can be combined. */
3383 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
3386 /* It is possible to have a subexpression appear twice in the insn.
3387 Suppose that FROM is a register that appears within TO.
3388 Then, after that subexpression has been scanned once by `subst',
3389 the second time it is scanned, TO may be found. If we were
3390 to scan TO here, we would find FROM within it and create a
3391 self-referent rtl structure which is completely wrong. */
3392 if (COMBINE_RTX_EQUAL_P (x, to))
3395 /* Parallel asm_operands need special attention because all of the
3396 inputs are shared across the arms. Furthermore, unsharing the
3397 rtl results in recognition failures. Failure to handle this case
3398 specially can result in circular rtl.
3400 Solve this by doing a normal pass across the first entry of the
3401 parallel, and only processing the SET_DESTs of the subsequent
3404 if (code == PARALLEL
3405 && GET_CODE (XVECEXP (x, 0, 0)) == SET
3406 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3408 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3410 /* If this substitution failed, this whole thing fails. */
3411 if (GET_CODE (new) == CLOBBER
3412 && XEXP (new, 0) == const0_rtx)
3415 SUBST (XVECEXP (x, 0, 0), new);
3417 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3419 rtx dest = SET_DEST (XVECEXP (x, 0, i));
3421 if (GET_CODE (dest) != REG
3422 && GET_CODE (dest) != CC0
3423 && GET_CODE (dest) != PC)
3425 new = subst (dest, from, to, 0, unique_copy);
3427 /* If this substitution failed, this whole thing fails. */
3428 if (GET_CODE (new) == CLOBBER
3429 && XEXP (new, 0) == const0_rtx)
3432 SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3438 len = GET_RTX_LENGTH (code);
3439 fmt = GET_RTX_FORMAT (code);
3441 /* We don't need to process a SET_DEST that is a register, CC0,
3442 or PC, so set up to skip this common case. All other cases
3443 where we want to suppress replacing something inside a
3444 SET_SRC are handled via the IN_DEST operand. */
3446 && (GET_CODE (SET_DEST (x)) == REG
3447 || GET_CODE (SET_DEST (x)) == CC0
3448 || GET_CODE (SET_DEST (x)) == PC))
3451 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3454 op0_mode = GET_MODE (XEXP (x, 0));
3456 for (i = 0; i < len; i++)
3461 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3463 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3465 new = (unique_copy && n_occurrences
3466 ? copy_rtx (to) : to);
3471 new = subst (XVECEXP (x, i, j), from, to, 0,
3474 /* If this substitution failed, this whole thing
3476 if (GET_CODE (new) == CLOBBER
3477 && XEXP (new, 0) == const0_rtx)
3481 SUBST (XVECEXP (x, i, j), new);
3484 else if (fmt[i] == 'e')
3486 /* If this is a register being set, ignore it. */
3489 && (code == SUBREG || code == STRICT_LOW_PART
3490 || code == ZERO_EXTRACT)
3492 && GET_CODE (new) == REG)
3495 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3497 /* In general, don't install a subreg involving two
3498 modes not tieable. It can worsen register
3499 allocation, and can even make invalid reload
3500 insns, since the reg inside may need to be copied
3501 from in the outside mode, and that may be invalid
3502 if it is an fp reg copied in integer mode.
3504 We allow two exceptions to this: It is valid if
3505 it is inside another SUBREG and the mode of that
3506 SUBREG and the mode of the inside of TO is
3507 tieable and it is valid if X is a SET that copies
3510 if (GET_CODE (to) == SUBREG
3511 && ! MODES_TIEABLE_P (GET_MODE (to),
3512 GET_MODE (SUBREG_REG (to)))
3513 && ! (code == SUBREG
3514 && MODES_TIEABLE_P (GET_MODE (x),
3515 GET_MODE (SUBREG_REG (to))))
3517 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3520 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3522 #ifdef CANNOT_CHANGE_MODE_CLASS
3524 && GET_CODE (to) == REG
3525 && REGNO (to) < FIRST_PSEUDO_REGISTER
3526 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
3529 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3532 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3536 /* If we are in a SET_DEST, suppress most cases unless we
3537 have gone inside a MEM, in which case we want to
3538 simplify the address. We assume here that things that
3539 are actually part of the destination have their inner
3540 parts in the first expression. This is true for SUBREG,
3541 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3542 things aside from REG and MEM that should appear in a
3544 new = subst (XEXP (x, i), from, to,
3546 && (code == SUBREG || code == STRICT_LOW_PART
3547 || code == ZERO_EXTRACT))
3549 && i == 0), unique_copy);
3551 /* If we found that we will have to reject this combination,
3552 indicate that by returning the CLOBBER ourselves, rather than
3553 an expression containing it. This will speed things up as
3554 well as prevent accidents where two CLOBBERs are considered
3555 to be equal, thus producing an incorrect simplification. */
3557 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3560 if (GET_CODE (new) == CONST_INT && GET_CODE (x) == SUBREG)
3562 enum machine_mode mode = GET_MODE (x);
3564 x = simplify_subreg (GET_MODE (x), new,
3565 GET_MODE (SUBREG_REG (x)),
3568 x = gen_rtx_CLOBBER (mode, const0_rtx);
3570 else if (GET_CODE (new) == CONST_INT
3571 && GET_CODE (x) == ZERO_EXTEND)
3573 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
3574 new, GET_MODE (XEXP (x, 0)));
3579 SUBST (XEXP (x, i), new);
3584 /* Try to simplify X. If the simplification changed the code, it is likely
3585 that further simplification will help, so loop, but limit the number
3586 of repetitions that will be performed. */
3588 for (i = 0; i < 4; i++)
3590 /* If X is sufficiently simple, don't bother trying to do anything
3592 if (code != CONST_INT && code != REG && code != CLOBBER)
3593 x = combine_simplify_rtx (x, op0_mode, i == 3, in_dest);
3595 if (GET_CODE (x) == code)
3598 code = GET_CODE (x);
3600 /* We no longer know the original mode of operand 0 since we
3601 have changed the form of X) */
3602 op0_mode = VOIDmode;
3608 /* Simplify X, a piece of RTL. We just operate on the expression at the
3609 outer level; call `subst' to simplify recursively. Return the new
3612 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3613 will be the iteration even if an expression with a code different from
3614 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3617 combine_simplify_rtx (x, op0_mode, last, in_dest)
3619 enum machine_mode op0_mode;
3623 enum rtx_code code = GET_CODE (x);
3624 enum machine_mode mode = GET_MODE (x);
3629 /* If this is a commutative operation, put a constant last and a complex
3630 expression first. We don't need to do this for comparisons here. */
3631 if (GET_RTX_CLASS (code) == 'c'
3632 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
3635 SUBST (XEXP (x, 0), XEXP (x, 1));
3636 SUBST (XEXP (x, 1), temp);
3639 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3640 sign extension of a PLUS with a constant, reverse the order of the sign
3641 extension and the addition. Note that this not the same as the original
3642 code, but overflow is undefined for signed values. Also note that the
3643 PLUS will have been partially moved "inside" the sign-extension, so that
3644 the first operand of X will really look like:
3645 (ashiftrt (plus (ashift A C4) C5) C4).
3647 (plus (ashiftrt (ashift A C4) C2) C4)
3648 and replace the first operand of X with that expression. Later parts
3649 of this function may simplify the expression further.
3651 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3652 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3653 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3655 We do this to simplify address expressions. */
3657 if ((code == PLUS || code == MINUS || code == MULT)
3658 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3659 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3660 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3661 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3662 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3663 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3664 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3665 && (temp = simplify_binary_operation (ASHIFTRT, mode,
3666 XEXP (XEXP (XEXP (x, 0), 0), 1),
3667 XEXP (XEXP (x, 0), 1))) != 0)
3670 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3671 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3672 INTVAL (XEXP (XEXP (x, 0), 1)));
3674 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3675 INTVAL (XEXP (XEXP (x, 0), 1)));
3677 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3680 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3681 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3682 things. Check for cases where both arms are testing the same
3685 Don't do anything if all operands are very simple. */
3687 if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c'
3688 || GET_RTX_CLASS (code) == '<')
3689 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3690 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3691 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3693 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'
3694 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3695 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1))))
3697 || (GET_RTX_CLASS (code) == '1'
3698 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3699 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3700 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3703 rtx cond, true_rtx, false_rtx;
3705 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
3707 /* If everything is a comparison, what we have is highly unlikely
3708 to be simpler, so don't use it. */
3709 && ! (GET_RTX_CLASS (code) == '<'
3710 && (GET_RTX_CLASS (GET_CODE (true_rtx)) == '<'
3711 || GET_RTX_CLASS (GET_CODE (false_rtx)) == '<')))
3713 rtx cop1 = const0_rtx;
3714 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3716 if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<')
3719 /* Simplify the alternative arms; this may collapse the true and
3720 false arms to store-flag values. */
3721 true_rtx = subst (true_rtx, pc_rtx, pc_rtx, 0, 0);
3722 false_rtx = subst (false_rtx, pc_rtx, pc_rtx, 0, 0);
3724 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3725 is unlikely to be simpler. */
3726 if (general_operand (true_rtx, VOIDmode)
3727 && general_operand (false_rtx, VOIDmode))
3729 /* Restarting if we generate a store-flag expression will cause
3730 us to loop. Just drop through in this case. */
3732 /* If the result values are STORE_FLAG_VALUE and zero, we can
3733 just make the comparison operation. */
3734 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
3735 x = gen_binary (cond_code, mode, cond, cop1);
3736 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
3737 && reverse_condition (cond_code) != UNKNOWN)
3738 x = gen_binary (reverse_condition (cond_code),
3741 /* Likewise, we can make the negate of a comparison operation
3742 if the result values are - STORE_FLAG_VALUE and zero. */
3743 else if (GET_CODE (true_rtx) == CONST_INT
3744 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
3745 && false_rtx == const0_rtx)
3746 x = simplify_gen_unary (NEG, mode,
3747 gen_binary (cond_code, mode, cond,
3750 else if (GET_CODE (false_rtx) == CONST_INT
3751 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
3752 && true_rtx == const0_rtx)
3753 x = simplify_gen_unary (NEG, mode,
3754 gen_binary (reverse_condition
3759 return gen_rtx_IF_THEN_ELSE (mode,
3760 gen_binary (cond_code, VOIDmode,
3762 true_rtx, false_rtx);
3764 code = GET_CODE (x);
3765 op0_mode = VOIDmode;
3770 /* Try to fold this expression in case we have constants that weren't
3773 switch (GET_RTX_CLASS (code))
3776 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3780 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
3781 if (cmp_mode == VOIDmode)
3783 cmp_mode = GET_MODE (XEXP (x, 1));
3784 if (cmp_mode == VOIDmode)
3785 cmp_mode = op0_mode;
3787 temp = simplify_relational_operation (code, cmp_mode,
3788 XEXP (x, 0), XEXP (x, 1));
3790 #ifdef FLOAT_STORE_FLAG_VALUE
3791 if (temp != 0 && GET_MODE_CLASS (mode) == MODE_FLOAT)
3793 if (temp == const0_rtx)
3794 temp = CONST0_RTX (mode);
3796 temp = CONST_DOUBLE_FROM_REAL_VALUE (FLOAT_STORE_FLAG_VALUE (mode),
3803 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3807 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3808 XEXP (x, 1), XEXP (x, 2));
3815 code = GET_CODE (temp);
3816 op0_mode = VOIDmode;
3817 mode = GET_MODE (temp);
3820 /* First see if we can apply the inverse distributive law. */
3821 if (code == PLUS || code == MINUS
3822 || code == AND || code == IOR || code == XOR)
3824 x = apply_distributive_law (x);
3825 code = GET_CODE (x);
3826 op0_mode = VOIDmode;
3829 /* If CODE is an associative operation not otherwise handled, see if we
3830 can associate some operands. This can win if they are constants or
3831 if they are logically related (i.e. (a & b) & a). */
3832 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
3833 || code == AND || code == IOR || code == XOR
3834 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3835 && ((INTEGRAL_MODE_P (mode) && code != DIV)
3836 || (flag_unsafe_math_optimizations && FLOAT_MODE_P (mode))))
3838 if (GET_CODE (XEXP (x, 0)) == code)
3840 rtx other = XEXP (XEXP (x, 0), 0);
3841 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3842 rtx inner_op1 = XEXP (x, 1);
3845 /* Make sure we pass the constant operand if any as the second
3846 one if this is a commutative operation. */
3847 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
3849 rtx tem = inner_op0;
3850 inner_op0 = inner_op1;
3853 inner = simplify_binary_operation (code == MINUS ? PLUS
3854 : code == DIV ? MULT
3856 mode, inner_op0, inner_op1);
3858 /* For commutative operations, try the other pair if that one
3860 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
3862 other = XEXP (XEXP (x, 0), 1);
3863 inner = simplify_binary_operation (code, mode,
3864 XEXP (XEXP (x, 0), 0),
3869 return gen_binary (code, mode, other, inner);
3873 /* A little bit of algebraic simplification here. */
3877 /* Ensure that our address has any ASHIFTs converted to MULT in case
3878 address-recognizing predicates are called later. */
3879 temp = make_compound_operation (XEXP (x, 0), MEM);
3880 SUBST (XEXP (x, 0), temp);
3884 if (op0_mode == VOIDmode)
3885 op0_mode = GET_MODE (SUBREG_REG (x));
3887 /* simplify_subreg can't use gen_lowpart_for_combine. */
3888 if (CONSTANT_P (SUBREG_REG (x))
3889 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
3890 /* Don't call gen_lowpart_for_combine if the inner mode
3891 is VOIDmode and we cannot simplify it, as SUBREG without
3892 inner mode is invalid. */
3893 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
3894 || gen_lowpart_common (mode, SUBREG_REG (x))))
3895 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3897 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
3901 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
3907 /* Don't change the mode of the MEM if that would change the meaning
3909 if (GET_CODE (SUBREG_REG (x)) == MEM
3910 && (MEM_VOLATILE_P (SUBREG_REG (x))
3911 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
3912 return gen_rtx_CLOBBER (mode, const0_rtx);
3914 /* Note that we cannot do any narrowing for non-constants since
3915 we might have been counting on using the fact that some bits were
3916 zero. We now do this in the SET. */
3921 /* (not (plus X -1)) can become (neg X). */
3922 if (GET_CODE (XEXP (x, 0)) == PLUS
3923 && XEXP (XEXP (x, 0), 1) == constm1_rtx)
3924 return gen_rtx_NEG (mode, XEXP (XEXP (x, 0), 0));
3926 /* Similarly, (not (neg X)) is (plus X -1). */
3927 if (GET_CODE (XEXP (x, 0)) == NEG)
3928 return gen_rtx_PLUS (mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3930 /* (not (xor X C)) for C constant is (xor X D) with D = ~C. */
3931 if (GET_CODE (XEXP (x, 0)) == XOR
3932 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3933 && (temp = simplify_unary_operation (NOT, mode,
3934 XEXP (XEXP (x, 0), 1),
3936 return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp);
3938 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3939 other than 1, but that is not valid. We could do a similar
3940 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3941 but this doesn't seem common enough to bother with. */
3942 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3943 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3944 return gen_rtx_ROTATE (mode, simplify_gen_unary (NOT, mode,
3946 XEXP (XEXP (x, 0), 1));
3948 if (GET_CODE (XEXP (x, 0)) == SUBREG
3949 && subreg_lowpart_p (XEXP (x, 0))
3950 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3951 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3952 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3953 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3955 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3957 x = gen_rtx_ROTATE (inner_mode,
3958 simplify_gen_unary (NOT, inner_mode, const1_rtx,
3960 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3961 return gen_lowpart_for_combine (mode, x);
3964 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3965 reversing the comparison code if valid. */
3966 if (STORE_FLAG_VALUE == -1
3967 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3968 && (reversed = reversed_comparison (x, mode, XEXP (XEXP (x, 0), 0),
3969 XEXP (XEXP (x, 0), 1))))
3972 /* (not (ashiftrt foo C)) where C is the number of bits in FOO minus 1
3973 is (ge foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3974 perform the above simplification. */
3976 if (STORE_FLAG_VALUE == -1
3977 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3978 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3979 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3980 return gen_rtx_GE (mode, XEXP (XEXP (x, 0), 0), const0_rtx);
3982 /* Apply De Morgan's laws to reduce number of patterns for machines
3983 with negating logical insns (and-not, nand, etc.). If result has
3984 only one NOT, put it first, since that is how the patterns are
3987 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3989 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3990 enum machine_mode op_mode;
3992 op_mode = GET_MODE (in1);
3993 in1 = simplify_gen_unary (NOT, op_mode, in1, op_mode);
3995 op_mode = GET_MODE (in2);
3996 if (op_mode == VOIDmode)
3998 in2 = simplify_gen_unary (NOT, op_mode, in2, op_mode);
4000 if (GET_CODE (in2) == NOT && GET_CODE (in1) != NOT)
4003 in2 = in1; in1 = tem;
4006 return gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
4012 /* (neg (plus X 1)) can become (not X). */
4013 if (GET_CODE (XEXP (x, 0)) == PLUS
4014 && XEXP (XEXP (x, 0), 1) == const1_rtx)
4015 return gen_rtx_NOT (mode, XEXP (XEXP (x, 0), 0));
4017 /* Similarly, (neg (not X)) is (plus X 1). */
4018 if (GET_CODE (XEXP (x, 0)) == NOT)
4019 return plus_constant (XEXP (XEXP (x, 0), 0), 1);
4021 /* (neg (minus X Y)) can become (minus Y X). This transformation
4022 isn't safe for modes with signed zeros, since if X and Y are
4023 both +0, (minus Y X) is the same as (minus X Y). If the rounding
4024 mode is towards +infinity (or -infinity) then the two expressions
4025 will be rounded differently. */
4026 if (GET_CODE (XEXP (x, 0)) == MINUS
4027 && !HONOR_SIGNED_ZEROS (mode)
4028 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode))
4029 return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
4030 XEXP (XEXP (x, 0), 0));
4032 /* (neg (plus A B)) is canonicalized to (minus (neg A) B). */
4033 if (GET_CODE (XEXP (x, 0)) == PLUS
4034 && !HONOR_SIGNED_ZEROS (mode)
4035 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode))
4037 temp = simplify_gen_unary (NEG, mode, XEXP (XEXP (x, 0), 0), mode);
4038 temp = combine_simplify_rtx (temp, mode, last, in_dest);
4039 return gen_binary (MINUS, mode, temp, XEXP (XEXP (x, 0), 1));
4042 /* (neg (mult A B)) becomes (mult (neg A) B).
4043 This works even for floating-point values. */
4044 if (GET_CODE (XEXP (x, 0)) == MULT)
4046 temp = simplify_gen_unary (NEG, mode, XEXP (XEXP (x, 0), 0), mode);
4047 return gen_binary (MULT, mode, temp, XEXP (XEXP (x, 0), 1));
4050 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
4051 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
4052 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
4053 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
4055 /* NEG commutes with ASHIFT since it is multiplication. Only do this
4056 if we can then eliminate the NEG (e.g.,
4057 if the operand is a constant). */
4059 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
4061 temp = simplify_unary_operation (NEG, mode,
4062 XEXP (XEXP (x, 0), 0), mode);
4064 return gen_binary (ASHIFT, mode, temp, XEXP (XEXP (x, 0), 1));
4067 temp = expand_compound_operation (XEXP (x, 0));
4069 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4070 replaced by (lshiftrt X C). This will convert
4071 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4073 if (GET_CODE (temp) == ASHIFTRT
4074 && GET_CODE (XEXP (temp, 1)) == CONST_INT
4075 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4076 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
4077 INTVAL (XEXP (temp, 1)));
4079 /* If X has only a single bit that might be nonzero, say, bit I, convert
4080 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4081 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4082 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4083 or a SUBREG of one since we'd be making the expression more
4084 complex if it was just a register. */
4086 if (GET_CODE (temp) != REG
4087 && ! (GET_CODE (temp) == SUBREG
4088 && GET_CODE (SUBREG_REG (temp)) == REG)
4089 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4091 rtx temp1 = simplify_shift_const
4092 (NULL_RTX, ASHIFTRT, mode,
4093 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4094 GET_MODE_BITSIZE (mode) - 1 - i),
4095 GET_MODE_BITSIZE (mode) - 1 - i);
4097 /* If all we did was surround TEMP with the two shifts, we
4098 haven't improved anything, so don't use it. Otherwise,
4099 we are better off with TEMP1. */
4100 if (GET_CODE (temp1) != ASHIFTRT
4101 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4102 || XEXP (XEXP (temp1, 0), 0) != temp)
4108 /* We can't handle truncation to a partial integer mode here
4109 because we don't know the real bitsize of the partial
4111 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4114 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4115 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4116 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4118 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4119 GET_MODE_MASK (mode), NULL_RTX, 0));
4121 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
4122 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4123 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4124 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4125 return XEXP (XEXP (x, 0), 0);
4127 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
4128 (OP:SI foo:SI) if OP is NEG or ABS. */
4129 if ((GET_CODE (XEXP (x, 0)) == ABS
4130 || GET_CODE (XEXP (x, 0)) == NEG)
4131 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
4132 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
4133 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4134 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4135 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4137 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4139 if (GET_CODE (XEXP (x, 0)) == SUBREG
4140 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
4141 && subreg_lowpart_p (XEXP (x, 0)))
4142 return SUBREG_REG (XEXP (x, 0));
4144 /* If we know that the value is already truncated, we can
4145 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4146 is nonzero for the corresponding modes. But don't do this
4147 for an (LSHIFTRT (MULT ...)) since this will cause problems
4148 with the umulXi3_highpart patterns. */
4149 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4150 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
4151 && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4152 >= (unsigned int) (GET_MODE_BITSIZE (mode) + 1)
4153 && ! (GET_CODE (XEXP (x, 0)) == LSHIFTRT
4154 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT))
4155 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4157 /* A truncate of a comparison can be replaced with a subreg if
4158 STORE_FLAG_VALUE permits. This is like the previous test,
4159 but it works even if the comparison is done in a mode larger
4160 than HOST_BITS_PER_WIDE_INT. */
4161 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4162 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4163 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0)
4164 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4166 /* Similarly, a truncate of a register whose value is a
4167 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4169 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4170 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4171 && (temp = get_last_value (XEXP (x, 0)))
4172 && GET_RTX_CLASS (GET_CODE (temp)) == '<')
4173 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4177 case FLOAT_TRUNCATE:
4178 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4179 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4180 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4181 return XEXP (XEXP (x, 0), 0);
4183 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4184 (OP:SF foo:SF) if OP is NEG or ABS. */
4185 if ((GET_CODE (XEXP (x, 0)) == ABS
4186 || GET_CODE (XEXP (x, 0)) == NEG)
4187 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
4188 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4189 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4190 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4192 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4193 is (float_truncate:SF x). */
4194 if (GET_CODE (XEXP (x, 0)) == SUBREG
4195 && subreg_lowpart_p (XEXP (x, 0))
4196 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
4197 return SUBREG_REG (XEXP (x, 0));
4202 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4203 using cc0, in which case we want to leave it as a COMPARE
4204 so we can distinguish it from a register-register-copy. */
4205 if (XEXP (x, 1) == const0_rtx)
4208 /* x - 0 is the same as x unless x's mode has signed zeros and
4209 allows rounding towards -infinity. Under those conditions,
4211 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0)))
4212 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0))))
4213 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4219 /* (const (const X)) can become (const X). Do it this way rather than
4220 returning the inner CONST since CONST can be shared with a
4222 if (GET_CODE (XEXP (x, 0)) == CONST)
4223 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4228 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4229 can add in an offset. find_split_point will split this address up
4230 again if it doesn't match. */
4231 if (GET_CODE (XEXP (x, 0)) == HIGH
4232 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4238 /* Canonicalize (plus (mult (neg B) C) A) to (minus A (mult B C)).
4240 if (GET_CODE (XEXP (x, 0)) == MULT
4241 && GET_CODE (XEXP (XEXP (x, 0), 0)) == NEG)
4245 in1 = XEXP (XEXP (XEXP (x, 0), 0), 0);
4246 in2 = XEXP (XEXP (x, 0), 1);
4247 return gen_binary (MINUS, mode, XEXP (x, 1),
4248 gen_binary (MULT, mode, in1, in2));
4251 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4252 outermost. That's because that's the way indexed addresses are
4253 supposed to appear. This code used to check many more cases, but
4254 they are now checked elsewhere. */
4255 if (GET_CODE (XEXP (x, 0)) == PLUS
4256 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
4257 return gen_binary (PLUS, mode,
4258 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
4260 XEXP (XEXP (x, 0), 1));
4262 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4263 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4264 bit-field and can be replaced by either a sign_extend or a
4265 sign_extract. The `and' may be a zero_extend and the two
4266 <c>, -<c> constants may be reversed. */
4267 if (GET_CODE (XEXP (x, 0)) == XOR
4268 && GET_CODE (XEXP (x, 1)) == CONST_INT
4269 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4270 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4271 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4272 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4273 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4274 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4275 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4276 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4277 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4278 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4279 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4280 == (unsigned int) i + 1))))
4281 return simplify_shift_const
4282 (NULL_RTX, ASHIFTRT, mode,
4283 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4284 XEXP (XEXP (XEXP (x, 0), 0), 0),
4285 GET_MODE_BITSIZE (mode) - (i + 1)),
4286 GET_MODE_BITSIZE (mode) - (i + 1));
4288 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4289 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4290 is 1. This produces better code than the alternative immediately
4292 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4293 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
4294 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx))
4295 && (reversed = reversed_comparison (XEXP (x, 0), mode,
4296 XEXP (XEXP (x, 0), 0),
4297 XEXP (XEXP (x, 0), 1))))
4299 simplify_gen_unary (NEG, mode, reversed, mode);
4301 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4302 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4303 the bitsize of the mode - 1. This allows simplification of
4304 "a = (b & 8) == 0;" */
4305 if (XEXP (x, 1) == constm1_rtx
4306 && GET_CODE (XEXP (x, 0)) != REG
4307 && ! (GET_CODE (XEXP (x,0)) == SUBREG
4308 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
4309 && nonzero_bits (XEXP (x, 0), mode) == 1)
4310 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4311 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4312 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4313 GET_MODE_BITSIZE (mode) - 1),
4314 GET_MODE_BITSIZE (mode) - 1);
4316 /* If we are adding two things that have no bits in common, convert
4317 the addition into an IOR. This will often be further simplified,
4318 for example in cases like ((a & 1) + (a & 2)), which can
4321 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4322 && (nonzero_bits (XEXP (x, 0), mode)
4323 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4325 /* Try to simplify the expression further. */
4326 rtx tor = gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4327 temp = combine_simplify_rtx (tor, mode, last, in_dest);
4329 /* If we could, great. If not, do not go ahead with the IOR
4330 replacement, since PLUS appears in many special purpose
4331 address arithmetic instructions. */
4332 if (GET_CODE (temp) != CLOBBER && temp != tor)
4338 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4339 by reversing the comparison code if valid. */
4340 if (STORE_FLAG_VALUE == 1
4341 && XEXP (x, 0) == const1_rtx
4342 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
4343 && (reversed = reversed_comparison (XEXP (x, 1), mode,
4344 XEXP (XEXP (x, 1), 0),
4345 XEXP (XEXP (x, 1), 1))))
4348 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4349 (and <foo> (const_int pow2-1)) */
4350 if (GET_CODE (XEXP (x, 1)) == AND
4351 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4352 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4353 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4354 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4355 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4357 /* Canonicalize (minus A (mult (neg B) C)) to (plus (mult B C) A).
4359 if (GET_CODE (XEXP (x, 1)) == MULT
4360 && GET_CODE (XEXP (XEXP (x, 1), 0)) == NEG)
4364 in1 = XEXP (XEXP (XEXP (x, 1), 0), 0);
4365 in2 = XEXP (XEXP (x, 1), 1);
4366 return gen_binary (PLUS, mode, gen_binary (MULT, mode, in1, in2),
4370 /* Canonicalize (minus (neg A) (mult B C)) to
4371 (minus (mult (neg B) C) A). */
4372 if (GET_CODE (XEXP (x, 1)) == MULT
4373 && GET_CODE (XEXP (x, 0)) == NEG)
4377 in1 = simplify_gen_unary (NEG, mode, XEXP (XEXP (x, 1), 0), mode);
4378 in2 = XEXP (XEXP (x, 1), 1);
4379 return gen_binary (MINUS, mode, gen_binary (MULT, mode, in1, in2),
4380 XEXP (XEXP (x, 0), 0));
4383 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4385 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
4386 return gen_binary (MINUS, mode,
4387 gen_binary (MINUS, mode, XEXP (x, 0),
4388 XEXP (XEXP (x, 1), 0)),
4389 XEXP (XEXP (x, 1), 1));
4393 /* If we have (mult (plus A B) C), apply the distributive law and then
4394 the inverse distributive law to see if things simplify. This
4395 occurs mostly in addresses, often when unrolling loops. */
4397 if (GET_CODE (XEXP (x, 0)) == PLUS)
4399 x = apply_distributive_law
4400 (gen_binary (PLUS, mode,
4401 gen_binary (MULT, mode,
4402 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4403 gen_binary (MULT, mode,
4404 XEXP (XEXP (x, 0), 1),
4405 copy_rtx (XEXP (x, 1)))));
4407 if (GET_CODE (x) != MULT)
4410 /* Try simplify a*(b/c) as (a*b)/c. */
4411 if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations
4412 && GET_CODE (XEXP (x, 0)) == DIV)
4414 rtx tem = simplify_binary_operation (MULT, mode,
4415 XEXP (XEXP (x, 0), 0),
4418 return gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
4423 /* If this is a divide by a power of two, treat it as a shift if
4424 its first operand is a shift. */
4425 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4426 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4427 && (GET_CODE (XEXP (x, 0)) == ASHIFT
4428 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4429 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4430 || GET_CODE (XEXP (x, 0)) == ROTATE
4431 || GET_CODE (XEXP (x, 0)) == ROTATERT))
4432 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4436 case GT: case GTU: case GE: case GEU:
4437 case LT: case LTU: case LE: case LEU:
4438 case UNEQ: case LTGT:
4439 case UNGT: case UNGE:
4440 case UNLT: case UNLE:
4441 case UNORDERED: case ORDERED:
4442 /* If the first operand is a condition code, we can't do anything
4444 if (GET_CODE (XEXP (x, 0)) == COMPARE
4445 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4447 && XEXP (x, 0) != cc0_rtx
4451 rtx op0 = XEXP (x, 0);
4452 rtx op1 = XEXP (x, 1);
4453 enum rtx_code new_code;
4455 if (GET_CODE (op0) == COMPARE)
4456 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4458 /* Simplify our comparison, if possible. */
4459 new_code = simplify_comparison (code, &op0, &op1);
4461 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4462 if only the low-order bit is possibly nonzero in X (such as when
4463 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4464 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4465 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4468 Remove any ZERO_EXTRACT we made when thinking this was a
4469 comparison. It may now be simpler to use, e.g., an AND. If a
4470 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4471 the call to make_compound_operation in the SET case. */
4473 if (STORE_FLAG_VALUE == 1
4474 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4475 && op1 == const0_rtx
4476 && mode == GET_MODE (op0)
4477 && nonzero_bits (op0, mode) == 1)
4478 return gen_lowpart_for_combine (mode,
4479 expand_compound_operation (op0));
4481 else if (STORE_FLAG_VALUE == 1
4482 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4483 && op1 == const0_rtx
4484 && mode == GET_MODE (op0)
4485 && (num_sign_bit_copies (op0, mode)
4486 == GET_MODE_BITSIZE (mode)))
4488 op0 = expand_compound_operation (op0);
4489 return simplify_gen_unary (NEG, mode,
4490 gen_lowpart_for_combine (mode, op0),
4494 else if (STORE_FLAG_VALUE == 1
4495 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4496 && op1 == const0_rtx
4497 && mode == GET_MODE (op0)
4498 && nonzero_bits (op0, mode) == 1)
4500 op0 = expand_compound_operation (op0);
4501 return gen_binary (XOR, mode,
4502 gen_lowpart_for_combine (mode, op0),
4506 else if (STORE_FLAG_VALUE == 1
4507 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4508 && op1 == const0_rtx
4509 && mode == GET_MODE (op0)
4510 && (num_sign_bit_copies (op0, mode)
4511 == GET_MODE_BITSIZE (mode)))
4513 op0 = expand_compound_operation (op0);
4514 return plus_constant (gen_lowpart_for_combine (mode, op0), 1);
4517 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4519 if (STORE_FLAG_VALUE == -1
4520 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4521 && op1 == const0_rtx
4522 && (num_sign_bit_copies (op0, mode)
4523 == GET_MODE_BITSIZE (mode)))
4524 return gen_lowpart_for_combine (mode,
4525 expand_compound_operation (op0));
4527 else if (STORE_FLAG_VALUE == -1
4528 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4529 && op1 == const0_rtx
4530 && mode == GET_MODE (op0)
4531 && nonzero_bits (op0, mode) == 1)
4533 op0 = expand_compound_operation (op0);
4534 return simplify_gen_unary (NEG, mode,
4535 gen_lowpart_for_combine (mode, op0),
4539 else if (STORE_FLAG_VALUE == -1
4540 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4541 && op1 == const0_rtx
4542 && mode == GET_MODE (op0)
4543 && (num_sign_bit_copies (op0, mode)
4544 == GET_MODE_BITSIZE (mode)))
4546 op0 = expand_compound_operation (op0);
4547 return simplify_gen_unary (NOT, mode,
4548 gen_lowpart_for_combine (mode, op0),
4552 /* If X is 0/1, (eq X 0) is X-1. */
4553 else if (STORE_FLAG_VALUE == -1
4554 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4555 && op1 == const0_rtx
4556 && mode == GET_MODE (op0)
4557 && nonzero_bits (op0, mode) == 1)
4559 op0 = expand_compound_operation (op0);
4560 return plus_constant (gen_lowpart_for_combine (mode, op0), -1);
4563 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4564 one bit that might be nonzero, we can convert (ne x 0) to
4565 (ashift x c) where C puts the bit in the sign bit. Remove any
4566 AND with STORE_FLAG_VALUE when we are done, since we are only
4567 going to test the sign bit. */
4568 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4569 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4570 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4571 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE(mode)-1))
4572 && op1 == const0_rtx
4573 && mode == GET_MODE (op0)
4574 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4576 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4577 expand_compound_operation (op0),
4578 GET_MODE_BITSIZE (mode) - 1 - i);
4579 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4585 /* If the code changed, return a whole new comparison. */
4586 if (new_code != code)
4587 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
4589 /* Otherwise, keep this operation, but maybe change its operands.
4590 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4591 SUBST (XEXP (x, 0), op0);
4592 SUBST (XEXP (x, 1), op1);
4597 return simplify_if_then_else (x);
4603 /* If we are processing SET_DEST, we are done. */
4607 return expand_compound_operation (x);
4610 return simplify_set (x);
4615 return simplify_logical (x, last);
4618 /* (abs (neg <foo>)) -> (abs <foo>) */
4619 if (GET_CODE (XEXP (x, 0)) == NEG)
4620 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4622 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4624 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
4627 /* If operand is something known to be positive, ignore the ABS. */
4628 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4629 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4630 <= HOST_BITS_PER_WIDE_INT)
4631 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4632 & ((HOST_WIDE_INT) 1
4633 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4637 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4638 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4639 return gen_rtx_NEG (mode, XEXP (x, 0));
4644 /* (ffs (*_extend <X>)) = (ffs <X>) */
4645 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4646 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4647 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4651 /* (float (sign_extend <X>)) = (float <X>). */
4652 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4653 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4661 /* If this is a shift by a constant amount, simplify it. */
4662 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4663 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4664 INTVAL (XEXP (x, 1)));
4666 #ifdef SHIFT_COUNT_TRUNCATED
4667 else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG)
4669 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
4671 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4680 rtx op0 = XEXP (x, 0);
4681 rtx op1 = XEXP (x, 1);
4684 if (GET_CODE (op1) != PARALLEL)
4686 len = XVECLEN (op1, 0);
4688 && GET_CODE (XVECEXP (op1, 0, 0)) == CONST_INT
4689 && GET_CODE (op0) == VEC_CONCAT)
4691 int offset = INTVAL (XVECEXP (op1, 0, 0)) * GET_MODE_SIZE (GET_MODE (x));
4693 /* Try to find the element in the VEC_CONCAT. */
4696 if (GET_MODE (op0) == GET_MODE (x))
4698 if (GET_CODE (op0) == VEC_CONCAT)
4700 HOST_WIDE_INT op0_size = GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)));
4701 if (op0_size < offset)
4702 op0 = XEXP (op0, 0);
4706 op0 = XEXP (op0, 1);
4724 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4727 simplify_if_then_else (x)
4730 enum machine_mode mode = GET_MODE (x);
4731 rtx cond = XEXP (x, 0);
4732 rtx true_rtx = XEXP (x, 1);
4733 rtx false_rtx = XEXP (x, 2);
4734 enum rtx_code true_code = GET_CODE (cond);
4735 int comparison_p = GET_RTX_CLASS (true_code) == '<';
4738 enum rtx_code false_code;
4741 /* Simplify storing of the truth value. */
4742 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
4743 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
4745 /* Also when the truth value has to be reversed. */
4747 && true_rtx == const0_rtx && false_rtx == const_true_rtx
4748 && (reversed = reversed_comparison (cond, mode, XEXP (cond, 0),
4752 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4753 in it is being compared against certain values. Get the true and false
4754 comparisons and see if that says anything about the value of each arm. */
4757 && ((false_code = combine_reversed_comparison_code (cond))
4759 && GET_CODE (XEXP (cond, 0)) == REG)
4762 rtx from = XEXP (cond, 0);
4763 rtx true_val = XEXP (cond, 1);
4764 rtx false_val = true_val;
4767 /* If FALSE_CODE is EQ, swap the codes and arms. */
4769 if (false_code == EQ)
4771 swapped = 1, true_code = EQ, false_code = NE;
4772 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4775 /* If we are comparing against zero and the expression being tested has
4776 only a single bit that might be nonzero, that is its value when it is
4777 not equal to zero. Similarly if it is known to be -1 or 0. */
4779 if (true_code == EQ && true_val == const0_rtx
4780 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4781 false_code = EQ, false_val = GEN_INT (nzb);
4782 else if (true_code == EQ && true_val == const0_rtx
4783 && (num_sign_bit_copies (from, GET_MODE (from))
4784 == GET_MODE_BITSIZE (GET_MODE (from))))
4785 false_code = EQ, false_val = constm1_rtx;
4787 /* Now simplify an arm if we know the value of the register in the
4788 branch and it is used in the arm. Be careful due to the potential
4789 of locally-shared RTL. */
4791 if (reg_mentioned_p (from, true_rtx))
4792 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
4794 pc_rtx, pc_rtx, 0, 0);
4795 if (reg_mentioned_p (from, false_rtx))
4796 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
4798 pc_rtx, pc_rtx, 0, 0);
4800 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
4801 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
4803 true_rtx = XEXP (x, 1);
4804 false_rtx = XEXP (x, 2);
4805 true_code = GET_CODE (cond);
4808 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4809 reversed, do so to avoid needing two sets of patterns for
4810 subtract-and-branch insns. Similarly if we have a constant in the true
4811 arm, the false arm is the same as the first operand of the comparison, or
4812 the false arm is more complicated than the true arm. */
4815 && combine_reversed_comparison_code (cond) != UNKNOWN
4816 && (true_rtx == pc_rtx
4817 || (CONSTANT_P (true_rtx)
4818 && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
4819 || true_rtx == const0_rtx
4820 || (GET_RTX_CLASS (GET_CODE (true_rtx)) == 'o'
4821 && GET_RTX_CLASS (GET_CODE (false_rtx)) != 'o')
4822 || (GET_CODE (true_rtx) == SUBREG
4823 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true_rtx))) == 'o'
4824 && GET_RTX_CLASS (GET_CODE (false_rtx)) != 'o')
4825 || reg_mentioned_p (true_rtx, false_rtx)
4826 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
4828 true_code = reversed_comparison_code (cond, NULL);
4830 reversed_comparison (cond, GET_MODE (cond), XEXP (cond, 0),
4833 SUBST (XEXP (x, 1), false_rtx);
4834 SUBST (XEXP (x, 2), true_rtx);
4836 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4839 /* It is possible that the conditional has been simplified out. */
4840 true_code = GET_CODE (cond);
4841 comparison_p = GET_RTX_CLASS (true_code) == '<';
4844 /* If the two arms are identical, we don't need the comparison. */
4846 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
4849 /* Convert a == b ? b : a to "a". */
4850 if (true_code == EQ && ! side_effects_p (cond)
4851 && !HONOR_NANS (mode)
4852 && rtx_equal_p (XEXP (cond, 0), false_rtx)
4853 && rtx_equal_p (XEXP (cond, 1), true_rtx))
4855 else if (true_code == NE && ! side_effects_p (cond)
4856 && !HONOR_NANS (mode)
4857 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4858 && rtx_equal_p (XEXP (cond, 1), false_rtx))
4861 /* Look for cases where we have (abs x) or (neg (abs X)). */
4863 if (GET_MODE_CLASS (mode) == MODE_INT
4864 && GET_CODE (false_rtx) == NEG
4865 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
4867 && rtx_equal_p (true_rtx, XEXP (cond, 0))
4868 && ! side_effects_p (true_rtx))
4873 return simplify_gen_unary (ABS, mode, true_rtx, mode);
4877 simplify_gen_unary (NEG, mode,
4878 simplify_gen_unary (ABS, mode, true_rtx, mode),
4884 /* Look for MIN or MAX. */
4886 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4888 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4889 && rtx_equal_p (XEXP (cond, 1), false_rtx)
4890 && ! side_effects_p (cond))
4895 return gen_binary (SMAX, mode, true_rtx, false_rtx);
4898 return gen_binary (SMIN, mode, true_rtx, false_rtx);
4901 return gen_binary (UMAX, mode, true_rtx, false_rtx);
4904 return gen_binary (UMIN, mode, true_rtx, false_rtx);
4909 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4910 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4911 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4912 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4913 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4914 neither 1 or -1, but it isn't worth checking for. */
4916 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4917 && comparison_p && mode != VOIDmode && ! side_effects_p (x))
4919 rtx t = make_compound_operation (true_rtx, SET);
4920 rtx f = make_compound_operation (false_rtx, SET);
4921 rtx cond_op0 = XEXP (cond, 0);
4922 rtx cond_op1 = XEXP (cond, 1);
4923 enum rtx_code op = NIL, extend_op = NIL;
4924 enum machine_mode m = mode;
4925 rtx z = 0, c1 = NULL_RTX;
4927 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4928 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4929 || GET_CODE (t) == ASHIFT
4930 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4931 && rtx_equal_p (XEXP (t, 0), f))
4932 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4934 /* If an identity-zero op is commutative, check whether there
4935 would be a match if we swapped the operands. */
4936 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4937 || GET_CODE (t) == XOR)
4938 && rtx_equal_p (XEXP (t, 1), f))
4939 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4940 else if (GET_CODE (t) == SIGN_EXTEND
4941 && (GET_CODE (XEXP (t, 0)) == PLUS
4942 || GET_CODE (XEXP (t, 0)) == MINUS
4943 || GET_CODE (XEXP (t, 0)) == IOR
4944 || GET_CODE (XEXP (t, 0)) == XOR
4945 || GET_CODE (XEXP (t, 0)) == ASHIFT
4946 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4947 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4948 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4949 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4950 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4951 && (num_sign_bit_copies (f, GET_MODE (f))
4953 (GET_MODE_BITSIZE (mode)
4954 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4956 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4957 extend_op = SIGN_EXTEND;
4958 m = GET_MODE (XEXP (t, 0));
4960 else if (GET_CODE (t) == SIGN_EXTEND
4961 && (GET_CODE (XEXP (t, 0)) == PLUS
4962 || GET_CODE (XEXP (t, 0)) == IOR
4963 || GET_CODE (XEXP (t, 0)) == XOR)
4964 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4965 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4966 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4967 && (num_sign_bit_copies (f, GET_MODE (f))
4969 (GET_MODE_BITSIZE (mode)
4970 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4972 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4973 extend_op = SIGN_EXTEND;
4974 m = GET_MODE (XEXP (t, 0));
4976 else if (GET_CODE (t) == ZERO_EXTEND
4977 && (GET_CODE (XEXP (t, 0)) == PLUS
4978 || GET_CODE (XEXP (t, 0)) == MINUS
4979 || GET_CODE (XEXP (t, 0)) == IOR
4980 || GET_CODE (XEXP (t, 0)) == XOR
4981 || GET_CODE (XEXP (t, 0)) == ASHIFT
4982 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4983 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4984 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4985 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4986 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4987 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4988 && ((nonzero_bits (f, GET_MODE (f))
4989 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
4992 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4993 extend_op = ZERO_EXTEND;
4994 m = GET_MODE (XEXP (t, 0));
4996 else if (GET_CODE (t) == ZERO_EXTEND
4997 && (GET_CODE (XEXP (t, 0)) == PLUS
4998 || GET_CODE (XEXP (t, 0)) == IOR
4999 || GET_CODE (XEXP (t, 0)) == XOR)
5000 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5001 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5002 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5003 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5004 && ((nonzero_bits (f, GET_MODE (f))
5005 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
5008 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5009 extend_op = ZERO_EXTEND;
5010 m = GET_MODE (XEXP (t, 0));
5015 temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
5016 pc_rtx, pc_rtx, 0, 0);
5017 temp = gen_binary (MULT, m, temp,
5018 gen_binary (MULT, m, c1, const_true_rtx));
5019 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
5020 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
5022 if (extend_op != NIL)
5023 temp = simplify_gen_unary (extend_op, mode, temp, m);
5029 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5030 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5031 negation of a single bit, we can convert this operation to a shift. We
5032 can actually do this more generally, but it doesn't seem worth it. */
5034 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5035 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5036 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
5037 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
5038 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
5039 == GET_MODE_BITSIZE (mode))
5040 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
5042 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5043 gen_lowpart_for_combine (mode, XEXP (cond, 0)), i);
5048 /* Simplify X, a SET expression. Return the new expression. */
5054 rtx src = SET_SRC (x);
5055 rtx dest = SET_DEST (x);
5056 enum machine_mode mode
5057 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
5061 /* (set (pc) (return)) gets written as (return). */
5062 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
5065 /* Now that we know for sure which bits of SRC we are using, see if we can
5066 simplify the expression for the object knowing that we only need the
5069 if (GET_MODE_CLASS (mode) == MODE_INT
5070 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5072 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, NULL_RTX, 0);
5073 SUBST (SET_SRC (x), src);
5076 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5077 the comparison result and try to simplify it unless we already have used
5078 undobuf.other_insn. */
5079 if ((GET_MODE_CLASS (mode) == MODE_CC
5080 || GET_CODE (src) == COMPARE
5082 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5083 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5084 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
5085 && rtx_equal_p (XEXP (*cc_use, 0), dest))
5087 enum rtx_code old_code = GET_CODE (*cc_use);
5088 enum rtx_code new_code;
5090 int other_changed = 0;
5091 enum machine_mode compare_mode = GET_MODE (dest);
5092 enum machine_mode tmp_mode;
5094 if (GET_CODE (src) == COMPARE)
5095 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5097 op0 = src, op1 = const0_rtx;
5099 /* Check whether the comparison is known at compile time. */
5100 if (GET_MODE (op0) != VOIDmode)
5101 tmp_mode = GET_MODE (op0);
5102 else if (GET_MODE (op1) != VOIDmode)
5103 tmp_mode = GET_MODE (op1);
5105 tmp_mode = compare_mode;
5106 tmp = simplify_relational_operation (old_code, tmp_mode, op0, op1);
5107 if (tmp != NULL_RTX)
5109 rtx pat = PATTERN (other_insn);
5110 undobuf.other_insn = other_insn;
5111 SUBST (*cc_use, tmp);
5113 /* Attempt to simplify CC user. */
5114 if (GET_CODE (pat) == SET)
5116 rtx new = simplify_rtx (SET_SRC (pat));
5117 if (new != NULL_RTX)
5118 SUBST (SET_SRC (pat), new);
5121 /* Convert X into a no-op move. */
5122 SUBST (SET_DEST (x), pc_rtx);
5123 SUBST (SET_SRC (x), pc_rtx);
5127 /* Simplify our comparison, if possible. */
5128 new_code = simplify_comparison (old_code, &op0, &op1);
5130 #ifdef EXTRA_CC_MODES
5131 /* If this machine has CC modes other than CCmode, check to see if we
5132 need to use a different CC mode here. */
5133 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5134 #endif /* EXTRA_CC_MODES */
5136 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
5137 /* If the mode changed, we have to change SET_DEST, the mode in the
5138 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5139 a hard register, just build new versions with the proper mode. If it
5140 is a pseudo, we lose unless it is only time we set the pseudo, in
5141 which case we can safely change its mode. */
5142 if (compare_mode != GET_MODE (dest))
5144 unsigned int regno = REGNO (dest);
5145 rtx new_dest = gen_rtx_REG (compare_mode, regno);
5147 if (regno < FIRST_PSEUDO_REGISTER
5148 || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
5150 if (regno >= FIRST_PSEUDO_REGISTER)
5151 SUBST (regno_reg_rtx[regno], new_dest);
5153 SUBST (SET_DEST (x), new_dest);
5154 SUBST (XEXP (*cc_use, 0), new_dest);
5162 /* If the code changed, we have to build a new comparison in
5163 undobuf.other_insn. */
5164 if (new_code != old_code)
5166 unsigned HOST_WIDE_INT mask;
5168 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5171 /* If the only change we made was to change an EQ into an NE or
5172 vice versa, OP0 has only one bit that might be nonzero, and OP1
5173 is zero, check if changing the user of the condition code will
5174 produce a valid insn. If it won't, we can keep the original code
5175 in that insn by surrounding our operation with an XOR. */
5177 if (((old_code == NE && new_code == EQ)
5178 || (old_code == EQ && new_code == NE))
5179 && ! other_changed && op1 == const0_rtx
5180 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5181 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5183 rtx pat = PATTERN (other_insn), note = 0;
5185 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
5186 && ! check_asm_operands (pat)))
5188 PUT_CODE (*cc_use, old_code);
5191 op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
5199 undobuf.other_insn = other_insn;
5202 /* If we are now comparing against zero, change our source if
5203 needed. If we do not use cc0, we always have a COMPARE. */
5204 if (op1 == const0_rtx && dest == cc0_rtx)
5206 SUBST (SET_SRC (x), op0);
5212 /* Otherwise, if we didn't previously have a COMPARE in the
5213 correct mode, we need one. */
5214 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5216 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5221 /* Otherwise, update the COMPARE if needed. */
5222 SUBST (XEXP (src, 0), op0);
5223 SUBST (XEXP (src, 1), op1);
5228 /* Get SET_SRC in a form where we have placed back any
5229 compound expressions. Then do the checks below. */
5230 src = make_compound_operation (src, SET);
5231 SUBST (SET_SRC (x), src);
5234 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5235 and X being a REG or (subreg (reg)), we may be able to convert this to
5236 (set (subreg:m2 x) (op)).
5238 We can always do this if M1 is narrower than M2 because that means that
5239 we only care about the low bits of the result.
5241 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5242 perform a narrower operation than requested since the high-order bits will
5243 be undefined. On machine where it is defined, this transformation is safe
5244 as long as M1 and M2 have the same number of words. */
5246 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5247 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o'
5248 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5250 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5251 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5252 #ifndef WORD_REGISTER_OPERATIONS
5253 && (GET_MODE_SIZE (GET_MODE (src))
5254 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5256 #ifdef CANNOT_CHANGE_MODE_CLASS
5257 && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER
5258 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
5260 GET_MODE (SUBREG_REG (src))))
5262 && (GET_CODE (dest) == REG
5263 || (GET_CODE (dest) == SUBREG
5264 && GET_CODE (SUBREG_REG (dest)) == REG)))
5266 SUBST (SET_DEST (x),
5267 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)),
5269 SUBST (SET_SRC (x), SUBREG_REG (src));
5271 src = SET_SRC (x), dest = SET_DEST (x);
5275 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5278 && GET_CODE (src) == SUBREG
5279 && subreg_lowpart_p (src)
5280 && (GET_MODE_BITSIZE (GET_MODE (src))
5281 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
5283 rtx inner = SUBREG_REG (src);
5284 enum machine_mode inner_mode = GET_MODE (inner);
5286 /* Here we make sure that we don't have a sign bit on. */
5287 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
5288 && (nonzero_bits (inner, inner_mode)
5289 < ((unsigned HOST_WIDE_INT) 1
5290 << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
5292 SUBST (SET_SRC (x), inner);
5298 #ifdef LOAD_EXTEND_OP
5299 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5300 would require a paradoxical subreg. Replace the subreg with a
5301 zero_extend to avoid the reload that would otherwise be required. */
5303 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5304 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
5305 && SUBREG_BYTE (src) == 0
5306 && (GET_MODE_SIZE (GET_MODE (src))
5307 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5308 && GET_CODE (SUBREG_REG (src)) == MEM)
5311 gen_rtx (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5312 GET_MODE (src), SUBREG_REG (src)));
5318 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5319 are comparing an item known to be 0 or -1 against 0, use a logical
5320 operation instead. Check for one of the arms being an IOR of the other
5321 arm with some value. We compute three terms to be IOR'ed together. In
5322 practice, at most two will be nonzero. Then we do the IOR's. */
5324 if (GET_CODE (dest) != PC
5325 && GET_CODE (src) == IF_THEN_ELSE
5326 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5327 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5328 && XEXP (XEXP (src, 0), 1) == const0_rtx
5329 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5330 #ifdef HAVE_conditional_move
5331 && ! can_conditionally_move_p (GET_MODE (src))
5333 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5334 GET_MODE (XEXP (XEXP (src, 0), 0)))
5335 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5336 && ! side_effects_p (src))
5338 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5339 ? XEXP (src, 1) : XEXP (src, 2));
5340 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5341 ? XEXP (src, 2) : XEXP (src, 1));
5342 rtx term1 = const0_rtx, term2, term3;
5344 if (GET_CODE (true_rtx) == IOR
5345 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5346 term1 = false_rtx, true_rtx = XEXP(true_rtx, 1), false_rtx = const0_rtx;
5347 else if (GET_CODE (true_rtx) == IOR
5348 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5349 term1 = false_rtx, true_rtx = XEXP(true_rtx, 0), false_rtx = const0_rtx;
5350 else if (GET_CODE (false_rtx) == IOR
5351 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5352 term1 = true_rtx, false_rtx = XEXP(false_rtx, 1), true_rtx = const0_rtx;
5353 else if (GET_CODE (false_rtx) == IOR
5354 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5355 term1 = true_rtx, false_rtx = XEXP(false_rtx, 0), true_rtx = const0_rtx;
5357 term2 = gen_binary (AND, GET_MODE (src),
5358 XEXP (XEXP (src, 0), 0), true_rtx);
5359 term3 = gen_binary (AND, GET_MODE (src),
5360 simplify_gen_unary (NOT, GET_MODE (src),
5361 XEXP (XEXP (src, 0), 0),
5366 gen_binary (IOR, GET_MODE (src),
5367 gen_binary (IOR, GET_MODE (src), term1, term2),
5373 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5374 whole thing fail. */
5375 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5377 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5380 /* Convert this into a field assignment operation, if possible. */
5381 return make_field_assignment (x);
5384 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5385 result. LAST is nonzero if this is the last retry. */
5388 simplify_logical (x, last)
5392 enum machine_mode mode = GET_MODE (x);
5393 rtx op0 = XEXP (x, 0);
5394 rtx op1 = XEXP (x, 1);
5397 switch (GET_CODE (x))
5400 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5401 insn (and may simplify more). */
5402 if (GET_CODE (op0) == XOR
5403 && rtx_equal_p (XEXP (op0, 0), op1)
5404 && ! side_effects_p (op1))
5405 x = gen_binary (AND, mode,
5406 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
5409 if (GET_CODE (op0) == XOR
5410 && rtx_equal_p (XEXP (op0, 1), op1)
5411 && ! side_effects_p (op1))
5412 x = gen_binary (AND, mode,
5413 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
5416 /* Similarly for (~(A ^ B)) & A. */
5417 if (GET_CODE (op0) == NOT
5418 && GET_CODE (XEXP (op0, 0)) == XOR
5419 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
5420 && ! side_effects_p (op1))
5421 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
5423 if (GET_CODE (op0) == NOT
5424 && GET_CODE (XEXP (op0, 0)) == XOR
5425 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
5426 && ! side_effects_p (op1))
5427 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
5429 /* We can call simplify_and_const_int only if we don't lose
5430 any (sign) bits when converting INTVAL (op1) to
5431 "unsigned HOST_WIDE_INT". */
5432 if (GET_CODE (op1) == CONST_INT
5433 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5434 || INTVAL (op1) > 0))
5436 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5438 /* If we have (ior (and (X C1) C2)) and the next restart would be
5439 the last, simplify this by making C1 as small as possible
5442 && GET_CODE (x) == IOR && GET_CODE (op0) == AND
5443 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5444 && GET_CODE (op1) == CONST_INT)
5445 return gen_binary (IOR, mode,
5446 gen_binary (AND, mode, XEXP (op0, 0),
5447 GEN_INT (INTVAL (XEXP (op0, 1))
5448 & ~INTVAL (op1))), op1);
5450 if (GET_CODE (x) != AND)
5453 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
5454 || GET_RTX_CLASS (GET_CODE (x)) == '2')
5455 op0 = XEXP (x, 0), op1 = XEXP (x, 1);
5458 /* Convert (A | B) & A to A. */
5459 if (GET_CODE (op0) == IOR
5460 && (rtx_equal_p (XEXP (op0, 0), op1)
5461 || rtx_equal_p (XEXP (op0, 1), op1))
5462 && ! side_effects_p (XEXP (op0, 0))
5463 && ! side_effects_p (XEXP (op0, 1)))
5466 /* In the following group of tests (and those in case IOR below),
5467 we start with some combination of logical operations and apply
5468 the distributive law followed by the inverse distributive law.
5469 Most of the time, this results in no change. However, if some of
5470 the operands are the same or inverses of each other, simplifications
5473 For example, (and (ior A B) (not B)) can occur as the result of
5474 expanding a bit field assignment. When we apply the distributive
5475 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5476 which then simplifies to (and (A (not B))).
5478 If we have (and (ior A B) C), apply the distributive law and then
5479 the inverse distributive law to see if things simplify. */
5481 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5483 x = apply_distributive_law
5484 (gen_binary (GET_CODE (op0), mode,
5485 gen_binary (AND, mode, XEXP (op0, 0), op1),
5486 gen_binary (AND, mode, XEXP (op0, 1),
5488 if (GET_CODE (x) != AND)
5492 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5493 return apply_distributive_law
5494 (gen_binary (GET_CODE (op1), mode,
5495 gen_binary (AND, mode, XEXP (op1, 0), op0),
5496 gen_binary (AND, mode, XEXP (op1, 1),
5499 /* Similarly, taking advantage of the fact that
5500 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5502 if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
5503 return apply_distributive_law
5504 (gen_binary (XOR, mode,
5505 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
5506 gen_binary (IOR, mode, copy_rtx (XEXP (op0, 0)),
5509 else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
5510 return apply_distributive_law
5511 (gen_binary (XOR, mode,
5512 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
5513 gen_binary (IOR, mode, copy_rtx (XEXP (op1, 0)), XEXP (op0, 1))));
5517 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5518 if (GET_CODE (op1) == CONST_INT
5519 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5520 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
5523 /* Convert (A & B) | A to A. */
5524 if (GET_CODE (op0) == AND
5525 && (rtx_equal_p (XEXP (op0, 0), op1)
5526 || rtx_equal_p (XEXP (op0, 1), op1))
5527 && ! side_effects_p (XEXP (op0, 0))
5528 && ! side_effects_p (XEXP (op0, 1)))
5531 /* If we have (ior (and A B) C), apply the distributive law and then
5532 the inverse distributive law to see if things simplify. */
5534 if (GET_CODE (op0) == AND)
5536 x = apply_distributive_law
5537 (gen_binary (AND, mode,
5538 gen_binary (IOR, mode, XEXP (op0, 0), op1),
5539 gen_binary (IOR, mode, XEXP (op0, 1),
5542 if (GET_CODE (x) != IOR)
5546 if (GET_CODE (op1) == AND)
5548 x = apply_distributive_law
5549 (gen_binary (AND, mode,
5550 gen_binary (IOR, mode, XEXP (op1, 0), op0),
5551 gen_binary (IOR, mode, XEXP (op1, 1),
5554 if (GET_CODE (x) != IOR)
5558 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5559 mode size to (rotate A CX). */
5561 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
5562 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
5563 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
5564 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5565 && GET_CODE (XEXP (op1, 1)) == CONST_INT
5566 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
5567 == GET_MODE_BITSIZE (mode)))
5568 return gen_rtx_ROTATE (mode, XEXP (op0, 0),
5569 (GET_CODE (op0) == ASHIFT
5570 ? XEXP (op0, 1) : XEXP (op1, 1)));
5572 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5573 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5574 does not affect any of the bits in OP1, it can really be done
5575 as a PLUS and we can associate. We do this by seeing if OP1
5576 can be safely shifted left C bits. */
5577 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
5578 && GET_CODE (XEXP (op0, 0)) == PLUS
5579 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
5580 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5581 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
5583 int count = INTVAL (XEXP (op0, 1));
5584 HOST_WIDE_INT mask = INTVAL (op1) << count;
5586 if (mask >> count == INTVAL (op1)
5587 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
5589 SUBST (XEXP (XEXP (op0, 0), 1),
5590 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
5597 /* If we are XORing two things that have no bits in common,
5598 convert them into an IOR. This helps to detect rotation encoded
5599 using those methods and possibly other simplifications. */
5601 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5602 && (nonzero_bits (op0, mode)
5603 & nonzero_bits (op1, mode)) == 0)
5604 return (gen_binary (IOR, mode, op0, op1));
5606 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5607 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5610 int num_negated = 0;
5612 if (GET_CODE (op0) == NOT)
5613 num_negated++, op0 = XEXP (op0, 0);
5614 if (GET_CODE (op1) == NOT)
5615 num_negated++, op1 = XEXP (op1, 0);
5617 if (num_negated == 2)
5619 SUBST (XEXP (x, 0), op0);
5620 SUBST (XEXP (x, 1), op1);
5622 else if (num_negated == 1)
5624 simplify_gen_unary (NOT, mode, gen_binary (XOR, mode, op0, op1),
5628 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5629 correspond to a machine insn or result in further simplifications
5630 if B is a constant. */
5632 if (GET_CODE (op0) == AND
5633 && rtx_equal_p (XEXP (op0, 1), op1)
5634 && ! side_effects_p (op1))
5635 return gen_binary (AND, mode,
5636 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
5639 else if (GET_CODE (op0) == AND
5640 && rtx_equal_p (XEXP (op0, 0), op1)
5641 && ! side_effects_p (op1))
5642 return gen_binary (AND, mode,
5643 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
5646 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5647 comparison if STORE_FLAG_VALUE is 1. */
5648 if (STORE_FLAG_VALUE == 1
5649 && op1 == const1_rtx
5650 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5651 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5655 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5656 is (lt foo (const_int 0)), so we can perform the above
5657 simplification if STORE_FLAG_VALUE is 1. */
5659 if (STORE_FLAG_VALUE == 1
5660 && op1 == const1_rtx
5661 && GET_CODE (op0) == LSHIFTRT
5662 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5663 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
5664 return gen_rtx_GE (mode, XEXP (op0, 0), const0_rtx);
5666 /* (xor (comparison foo bar) (const_int sign-bit))
5667 when STORE_FLAG_VALUE is the sign bit. */
5668 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5669 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5670 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5671 && op1 == const_true_rtx
5672 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5673 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5686 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5687 operations" because they can be replaced with two more basic operations.
5688 ZERO_EXTEND is also considered "compound" because it can be replaced with
5689 an AND operation, which is simpler, though only one operation.
5691 The function expand_compound_operation is called with an rtx expression
5692 and will convert it to the appropriate shifts and AND operations,
5693 simplifying at each stage.
5695 The function make_compound_operation is called to convert an expression
5696 consisting of shifts and ANDs into the equivalent compound expression.
5697 It is the inverse of this function, loosely speaking. */
5700 expand_compound_operation (x)
5703 unsigned HOST_WIDE_INT pos = 0, len;
5705 unsigned int modewidth;
5708 switch (GET_CODE (x))
5713 /* We can't necessarily use a const_int for a multiword mode;
5714 it depends on implicitly extending the value.
5715 Since we don't know the right way to extend it,
5716 we can't tell whether the implicit way is right.
5718 Even for a mode that is no wider than a const_int,
5719 we can't win, because we need to sign extend one of its bits through
5720 the rest of it, and we don't know which bit. */
5721 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5724 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5725 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5726 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5727 reloaded. If not for that, MEM's would very rarely be safe.
5729 Reject MODEs bigger than a word, because we might not be able
5730 to reference a two-register group starting with an arbitrary register
5731 (and currently gen_lowpart might crash for a SUBREG). */
5733 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5736 /* Reject MODEs that aren't scalar integers because turning vector
5737 or complex modes into shifts causes problems. */
5739 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5742 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5743 /* If the inner object has VOIDmode (the only way this can happen
5744 is if it is an ASM_OPERANDS), we can't do anything since we don't
5745 know how much masking to do. */
5754 /* If the operand is a CLOBBER, just return it. */
5755 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5758 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5759 || GET_CODE (XEXP (x, 2)) != CONST_INT
5760 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5763 /* Reject MODEs that aren't scalar integers because turning vector
5764 or complex modes into shifts causes problems. */
5766 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5769 len = INTVAL (XEXP (x, 1));
5770 pos = INTVAL (XEXP (x, 2));
5772 /* If this goes outside the object being extracted, replace the object
5773 with a (use (mem ...)) construct that only combine understands
5774 and is used only for this purpose. */
5775 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5776 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
5778 if (BITS_BIG_ENDIAN)
5779 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5786 /* Convert sign extension to zero extension, if we know that the high
5787 bit is not set, as this is easier to optimize. It will be converted
5788 back to cheaper alternative in make_extraction. */
5789 if (GET_CODE (x) == SIGN_EXTEND
5790 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5791 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5792 & ~(((unsigned HOST_WIDE_INT)
5793 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5797 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5798 return expand_compound_operation (temp);
5801 /* We can optimize some special cases of ZERO_EXTEND. */
5802 if (GET_CODE (x) == ZERO_EXTEND)
5804 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5805 know that the last value didn't have any inappropriate bits
5807 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5808 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5809 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5810 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5811 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5812 return XEXP (XEXP (x, 0), 0);
5814 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5815 if (GET_CODE (XEXP (x, 0)) == SUBREG
5816 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5817 && subreg_lowpart_p (XEXP (x, 0))
5818 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5819 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5820 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5821 return SUBREG_REG (XEXP (x, 0));
5823 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5824 is a comparison and STORE_FLAG_VALUE permits. This is like
5825 the first case, but it works even when GET_MODE (x) is larger
5826 than HOST_WIDE_INT. */
5827 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5828 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5829 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<'
5830 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5831 <= HOST_BITS_PER_WIDE_INT)
5832 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5833 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5834 return XEXP (XEXP (x, 0), 0);
5836 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5837 if (GET_CODE (XEXP (x, 0)) == SUBREG
5838 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5839 && subreg_lowpart_p (XEXP (x, 0))
5840 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<'
5841 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5842 <= HOST_BITS_PER_WIDE_INT)
5843 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5844 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5845 return SUBREG_REG (XEXP (x, 0));
5849 /* If we reach here, we want to return a pair of shifts. The inner
5850 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5851 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5852 logical depending on the value of UNSIGNEDP.
5854 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5855 converted into an AND of a shift.
5857 We must check for the case where the left shift would have a negative
5858 count. This can happen in a case like (x >> 31) & 255 on machines
5859 that can't shift by a constant. On those machines, we would first
5860 combine the shift with the AND to produce a variable-position
5861 extraction. Then the constant of 31 would be substituted in to produce
5862 a such a position. */
5864 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5865 if (modewidth + len >= pos)
5866 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5868 simplify_shift_const (NULL_RTX, ASHIFT,
5871 modewidth - pos - len),
5874 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5875 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5876 simplify_shift_const (NULL_RTX, LSHIFTRT,
5879 ((HOST_WIDE_INT) 1 << len) - 1);
5881 /* Any other cases we can't handle. */
5884 /* If we couldn't do this for some reason, return the original
5886 if (GET_CODE (tem) == CLOBBER)
5892 /* X is a SET which contains an assignment of one object into
5893 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5894 or certain SUBREGS). If possible, convert it into a series of
5897 We half-heartedly support variable positions, but do not at all
5898 support variable lengths. */
5901 expand_field_assignment (x)
5905 rtx pos; /* Always counts from low bit. */
5908 enum machine_mode compute_mode;
5910 /* Loop until we find something we can't simplify. */
5913 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5914 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5916 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5917 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5918 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
5920 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5921 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5923 inner = XEXP (SET_DEST (x), 0);
5924 len = INTVAL (XEXP (SET_DEST (x), 1));
5925 pos = XEXP (SET_DEST (x), 2);
5927 /* If the position is constant and spans the width of INNER,
5928 surround INNER with a USE to indicate this. */
5929 if (GET_CODE (pos) == CONST_INT
5930 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5931 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
5933 if (BITS_BIG_ENDIAN)
5935 if (GET_CODE (pos) == CONST_INT)
5936 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5938 else if (GET_CODE (pos) == MINUS
5939 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5940 && (INTVAL (XEXP (pos, 1))
5941 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5942 /* If position is ADJUST - X, new position is X. */
5943 pos = XEXP (pos, 0);
5945 pos = gen_binary (MINUS, GET_MODE (pos),
5946 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
5952 /* A SUBREG between two modes that occupy the same numbers of words
5953 can be done by moving the SUBREG to the source. */
5954 else if (GET_CODE (SET_DEST (x)) == SUBREG
5955 /* We need SUBREGs to compute nonzero_bits properly. */
5956 && nonzero_sign_valid
5957 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5958 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5959 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5960 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5962 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5963 gen_lowpart_for_combine
5964 (GET_MODE (SUBREG_REG (SET_DEST (x))),
5971 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5972 inner = SUBREG_REG (inner);
5974 compute_mode = GET_MODE (inner);
5976 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
5977 if (! SCALAR_INT_MODE_P (compute_mode))
5979 enum machine_mode imode;
5981 /* Don't do anything for vector or complex integral types. */
5982 if (! FLOAT_MODE_P (compute_mode))
5985 /* Try to find an integral mode to pun with. */
5986 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
5987 if (imode == BLKmode)
5990 compute_mode = imode;
5991 inner = gen_lowpart_for_combine (imode, inner);
5994 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5995 if (len < HOST_BITS_PER_WIDE_INT)
5996 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
6000 /* Now compute the equivalent expression. Make a copy of INNER
6001 for the SET_DEST in case it is a MEM into which we will substitute;
6002 we don't want shared RTL in that case. */
6004 (VOIDmode, copy_rtx (inner),
6005 gen_binary (IOR, compute_mode,
6006 gen_binary (AND, compute_mode,
6007 simplify_gen_unary (NOT, compute_mode,
6013 gen_binary (ASHIFT, compute_mode,
6014 gen_binary (AND, compute_mode,
6015 gen_lowpart_for_combine
6016 (compute_mode, SET_SRC (x)),
6024 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6025 it is an RTX that represents a variable starting position; otherwise,
6026 POS is the (constant) starting bit position (counted from the LSB).
6028 INNER may be a USE. This will occur when we started with a bitfield
6029 that went outside the boundary of the object in memory, which is
6030 allowed on most machines. To isolate this case, we produce a USE
6031 whose mode is wide enough and surround the MEM with it. The only
6032 code that understands the USE is this routine. If it is not removed,
6033 it will cause the resulting insn not to match.
6035 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6038 IN_DEST is nonzero if this is a reference in the destination of a
6039 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6040 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6043 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6044 ZERO_EXTRACT should be built even for bits starting at bit 0.
6046 MODE is the desired mode of the result (if IN_DEST == 0).
6048 The result is an RTX for the extraction or NULL_RTX if the target
6052 make_extraction (mode, inner, pos, pos_rtx, len,
6053 unsignedp, in_dest, in_compare)
6054 enum machine_mode mode;
6058 unsigned HOST_WIDE_INT len;
6060 int in_dest, in_compare;
6062 /* This mode describes the size of the storage area
6063 to fetch the overall value from. Within that, we
6064 ignore the POS lowest bits, etc. */
6065 enum machine_mode is_mode = GET_MODE (inner);
6066 enum machine_mode inner_mode;
6067 enum machine_mode wanted_inner_mode = byte_mode;
6068 enum machine_mode wanted_inner_reg_mode = word_mode;
6069 enum machine_mode pos_mode = word_mode;
6070 enum machine_mode extraction_mode = word_mode;
6071 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
6074 rtx orig_pos_rtx = pos_rtx;
6075 HOST_WIDE_INT orig_pos;
6077 /* Get some information about INNER and get the innermost object. */
6078 if (GET_CODE (inner) == USE)
6079 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
6080 /* We don't need to adjust the position because we set up the USE
6081 to pretend that it was a full-word object. */
6082 spans_byte = 1, inner = XEXP (inner, 0);
6083 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6085 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6086 consider just the QI as the memory to extract from.
6087 The subreg adds or removes high bits; its mode is
6088 irrelevant to the meaning of this extraction,
6089 since POS and LEN count from the lsb. */
6090 if (GET_CODE (SUBREG_REG (inner)) == MEM)
6091 is_mode = GET_MODE (SUBREG_REG (inner));
6092 inner = SUBREG_REG (inner);
6094 else if (GET_CODE (inner) == ASHIFT
6095 && GET_CODE (XEXP (inner, 1)) == CONST_INT
6096 && pos_rtx == 0 && pos == 0
6097 && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
6099 /* We're extracting the least significant bits of an rtx
6100 (ashift X (const_int C)), where LEN > C. Extract the
6101 least significant (LEN - C) bits of X, giving an rtx
6102 whose mode is MODE, then shift it left C times. */
6103 new = make_extraction (mode, XEXP (inner, 0),
6104 0, 0, len - INTVAL (XEXP (inner, 1)),
6105 unsignedp, in_dest, in_compare);
6107 return gen_rtx_ASHIFT (mode, new, XEXP (inner, 1));
6110 inner_mode = GET_MODE (inner);
6112 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
6113 pos = INTVAL (pos_rtx), pos_rtx = 0;
6115 /* See if this can be done without an extraction. We never can if the
6116 width of the field is not the same as that of some integer mode. For
6117 registers, we can only avoid the extraction if the position is at the
6118 low-order bit and this is either not in the destination or we have the
6119 appropriate STRICT_LOW_PART operation available.
6121 For MEM, we can avoid an extract if the field starts on an appropriate
6122 boundary and we can change the mode of the memory reference. However,
6123 we cannot directly access the MEM if we have a USE and the underlying
6124 MEM is not TMODE. This combination means that MEM was being used in a
6125 context where bits outside its mode were being referenced; that is only
6126 valid in bit-field insns. */
6128 if (tmode != BLKmode
6129 && ! (spans_byte && inner_mode != tmode)
6130 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
6131 && GET_CODE (inner) != MEM
6133 || (GET_CODE (inner) == REG
6134 && have_insn_for (STRICT_LOW_PART, tmode))))
6135 || (GET_CODE (inner) == MEM && pos_rtx == 0
6137 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
6138 : BITS_PER_UNIT)) == 0
6139 /* We can't do this if we are widening INNER_MODE (it
6140 may not be aligned, for one thing). */
6141 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
6142 && (inner_mode == tmode
6143 || (! mode_dependent_address_p (XEXP (inner, 0))
6144 && ! MEM_VOLATILE_P (inner))))))
6146 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6147 field. If the original and current mode are the same, we need not
6148 adjust the offset. Otherwise, we do if bytes big endian.
6150 If INNER is not a MEM, get a piece consisting of just the field
6151 of interest (in this case POS % BITS_PER_WORD must be 0). */
6153 if (GET_CODE (inner) == MEM)
6155 HOST_WIDE_INT offset;
6157 /* POS counts from lsb, but make OFFSET count in memory order. */
6158 if (BYTES_BIG_ENDIAN)
6159 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6161 offset = pos / BITS_PER_UNIT;
6163 new = adjust_address_nv (inner, tmode, offset);
6165 else if (GET_CODE (inner) == REG)
6167 /* We can't call gen_lowpart_for_combine here since we always want
6168 a SUBREG and it would sometimes return a new hard register. */
6169 if (tmode != inner_mode)
6171 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6173 if (WORDS_BIG_ENDIAN
6174 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6175 final_word = ((GET_MODE_SIZE (inner_mode)
6176 - GET_MODE_SIZE (tmode))
6177 / UNITS_PER_WORD) - final_word;
6179 final_word *= UNITS_PER_WORD;
6180 if (BYTES_BIG_ENDIAN &&
6181 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6182 final_word += (GET_MODE_SIZE (inner_mode)
6183 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6185 /* Avoid creating invalid subregs, for example when
6186 simplifying (x>>32)&255. */
6187 if (final_word >= GET_MODE_SIZE (inner_mode))
6190 new = gen_rtx_SUBREG (tmode, inner, final_word);
6196 new = force_to_mode (inner, tmode,
6197 len >= HOST_BITS_PER_WIDE_INT
6198 ? ~(unsigned HOST_WIDE_INT) 0
6199 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6202 /* If this extraction is going into the destination of a SET,
6203 make a STRICT_LOW_PART unless we made a MEM. */
6206 return (GET_CODE (new) == MEM ? new
6207 : (GET_CODE (new) != SUBREG
6208 ? gen_rtx_CLOBBER (tmode, const0_rtx)
6209 : gen_rtx_STRICT_LOW_PART (VOIDmode, new)));
6214 if (GET_CODE (new) == CONST_INT)
6215 return gen_int_mode (INTVAL (new), mode);
6217 /* If we know that no extraneous bits are set, and that the high
6218 bit is not set, convert the extraction to the cheaper of
6219 sign and zero extension, that are equivalent in these cases. */
6220 if (flag_expensive_optimizations
6221 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6222 && ((nonzero_bits (new, tmode)
6223 & ~(((unsigned HOST_WIDE_INT)
6224 GET_MODE_MASK (tmode))
6228 rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
6229 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
6231 /* Prefer ZERO_EXTENSION, since it gives more information to
6233 if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
6238 /* Otherwise, sign- or zero-extend unless we already are in the
6241 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6245 /* Unless this is a COMPARE or we have a funny memory reference,
6246 don't do anything with zero-extending field extracts starting at
6247 the low-order bit since they are simple AND operations. */
6248 if (pos_rtx == 0 && pos == 0 && ! in_dest
6249 && ! in_compare && ! spans_byte && unsignedp)
6252 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6253 we would be spanning bytes or if the position is not a constant and the
6254 length is not 1. In all other cases, we would only be going outside
6255 our object in cases when an original shift would have been
6257 if (! spans_byte && GET_CODE (inner) == MEM
6258 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6259 || (pos_rtx != 0 && len != 1)))
6262 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6263 and the mode for the result. */
6264 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6266 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6267 pos_mode = mode_for_extraction (EP_insv, 2);
6268 extraction_mode = mode_for_extraction (EP_insv, 3);
6271 if (! in_dest && unsignedp
6272 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6274 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6275 pos_mode = mode_for_extraction (EP_extzv, 3);
6276 extraction_mode = mode_for_extraction (EP_extzv, 0);
6279 if (! in_dest && ! unsignedp
6280 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6282 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6283 pos_mode = mode_for_extraction (EP_extv, 3);
6284 extraction_mode = mode_for_extraction (EP_extv, 0);
6287 /* Never narrow an object, since that might not be safe. */
6289 if (mode != VOIDmode
6290 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6291 extraction_mode = mode;
6293 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6294 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6295 pos_mode = GET_MODE (pos_rtx);
6297 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6298 if we have to change the mode of memory and cannot, the desired mode is
6300 if (GET_CODE (inner) != MEM)
6301 wanted_inner_mode = wanted_inner_reg_mode;
6302 else if (inner_mode != wanted_inner_mode
6303 && (mode_dependent_address_p (XEXP (inner, 0))
6304 || MEM_VOLATILE_P (inner)))
6305 wanted_inner_mode = extraction_mode;
6309 if (BITS_BIG_ENDIAN)
6311 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6312 BITS_BIG_ENDIAN style. If position is constant, compute new
6313 position. Otherwise, build subtraction.
6314 Note that POS is relative to the mode of the original argument.
6315 If it's a MEM we need to recompute POS relative to that.
6316 However, if we're extracting from (or inserting into) a register,
6317 we want to recompute POS relative to wanted_inner_mode. */
6318 int width = (GET_CODE (inner) == MEM
6319 ? GET_MODE_BITSIZE (is_mode)
6320 : GET_MODE_BITSIZE (wanted_inner_mode));
6323 pos = width - len - pos;
6326 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6327 /* POS may be less than 0 now, but we check for that below.
6328 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6331 /* If INNER has a wider mode, make it smaller. If this is a constant
6332 extract, try to adjust the byte to point to the byte containing
6334 if (wanted_inner_mode != VOIDmode
6335 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6336 && ((GET_CODE (inner) == MEM
6337 && (inner_mode == wanted_inner_mode
6338 || (! mode_dependent_address_p (XEXP (inner, 0))
6339 && ! MEM_VOLATILE_P (inner))))))
6343 /* The computations below will be correct if the machine is big
6344 endian in both bits and bytes or little endian in bits and bytes.
6345 If it is mixed, we must adjust. */
6347 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6348 adjust OFFSET to compensate. */
6349 if (BYTES_BIG_ENDIAN
6351 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6352 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6354 /* If this is a constant position, we can move to the desired byte. */
6357 offset += pos / BITS_PER_UNIT;
6358 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6361 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6363 && is_mode != wanted_inner_mode)
6364 offset = (GET_MODE_SIZE (is_mode)
6365 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6367 if (offset != 0 || inner_mode != wanted_inner_mode)
6368 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6371 /* If INNER is not memory, we can always get it into the proper mode. If we
6372 are changing its mode, POS must be a constant and smaller than the size
6374 else if (GET_CODE (inner) != MEM)
6376 if (GET_MODE (inner) != wanted_inner_mode
6378 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6381 inner = force_to_mode (inner, wanted_inner_mode,
6383 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6384 ? ~(unsigned HOST_WIDE_INT) 0
6385 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6390 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6391 have to zero extend. Otherwise, we can just use a SUBREG. */
6393 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6395 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6397 /* If we know that no extraneous bits are set, and that the high
6398 bit is not set, convert extraction to cheaper one - either
6399 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6401 if (flag_expensive_optimizations
6402 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6403 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6404 & ~(((unsigned HOST_WIDE_INT)
6405 GET_MODE_MASK (GET_MODE (pos_rtx)))
6409 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6411 /* Prefer ZERO_EXTENSION, since it gives more information to
6413 if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6418 else if (pos_rtx != 0
6419 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6420 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
6422 /* Make POS_RTX unless we already have it and it is correct. If we don't
6423 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6425 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6426 pos_rtx = orig_pos_rtx;
6428 else if (pos_rtx == 0)
6429 pos_rtx = GEN_INT (pos);
6431 /* Make the required operation. See if we can use existing rtx. */
6432 new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6433 extraction_mode, inner, GEN_INT (len), pos_rtx);
6435 new = gen_lowpart_for_combine (mode, new);
6440 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6441 with any other operations in X. Return X without that shift if so. */
6444 extract_left_shift (x, count)
6448 enum rtx_code code = GET_CODE (x);
6449 enum machine_mode mode = GET_MODE (x);
6455 /* This is the shift itself. If it is wide enough, we will return
6456 either the value being shifted if the shift count is equal to
6457 COUNT or a shift for the difference. */
6458 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6459 && INTVAL (XEXP (x, 1)) >= count)
6460 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6461 INTVAL (XEXP (x, 1)) - count);
6465 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6466 return simplify_gen_unary (code, mode, tem, mode);
6470 case PLUS: case IOR: case XOR: case AND:
6471 /* If we can safely shift this constant and we find the inner shift,
6472 make a new operation. */
6473 if (GET_CODE (XEXP (x,1)) == CONST_INT
6474 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6475 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6476 return gen_binary (code, mode, tem,
6477 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6488 /* Look at the expression rooted at X. Look for expressions
6489 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6490 Form these expressions.
6492 Return the new rtx, usually just X.
6494 Also, for machines like the VAX that don't have logical shift insns,
6495 try to convert logical to arithmetic shift operations in cases where
6496 they are equivalent. This undoes the canonicalizations to logical
6497 shifts done elsewhere.
6499 We try, as much as possible, to re-use rtl expressions to save memory.
6501 IN_CODE says what kind of expression we are processing. Normally, it is
6502 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6503 being kludges), it is MEM. When processing the arguments of a comparison
6504 or a COMPARE against zero, it is COMPARE. */
6507 make_compound_operation (x, in_code)
6509 enum rtx_code in_code;
6511 enum rtx_code code = GET_CODE (x);
6512 enum machine_mode mode = GET_MODE (x);
6513 int mode_width = GET_MODE_BITSIZE (mode);
6515 enum rtx_code next_code;
6521 /* Select the code to be used in recursive calls. Once we are inside an
6522 address, we stay there. If we have a comparison, set to COMPARE,
6523 but once inside, go back to our default of SET. */
6525 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6526 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
6527 && XEXP (x, 1) == const0_rtx) ? COMPARE
6528 : in_code == COMPARE ? SET : in_code);
6530 /* Process depending on the code of this operation. If NEW is set
6531 nonzero, it will be returned. */
6536 /* Convert shifts by constants into multiplications if inside
6538 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6539 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6540 && INTVAL (XEXP (x, 1)) >= 0)
6542 new = make_compound_operation (XEXP (x, 0), next_code);
6543 new = gen_rtx_MULT (mode, new,
6544 GEN_INT ((HOST_WIDE_INT) 1
6545 << INTVAL (XEXP (x, 1))));
6550 /* If the second operand is not a constant, we can't do anything
6552 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6555 /* If the constant is a power of two minus one and the first operand
6556 is a logical right shift, make an extraction. */
6557 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6558 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6560 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6561 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6562 0, in_code == COMPARE);
6565 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6566 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6567 && subreg_lowpart_p (XEXP (x, 0))
6568 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6569 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6571 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6573 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6574 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6575 0, in_code == COMPARE);
6577 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6578 else if ((GET_CODE (XEXP (x, 0)) == XOR
6579 || GET_CODE (XEXP (x, 0)) == IOR)
6580 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6581 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6582 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6584 /* Apply the distributive law, and then try to make extractions. */
6585 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6586 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6588 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6590 new = make_compound_operation (new, in_code);
6593 /* If we are have (and (rotate X C) M) and C is larger than the number
6594 of bits in M, this is an extraction. */
6596 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6597 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6598 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6599 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6601 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6602 new = make_extraction (mode, new,
6603 (GET_MODE_BITSIZE (mode)
6604 - INTVAL (XEXP (XEXP (x, 0), 1))),
6605 NULL_RTX, i, 1, 0, in_code == COMPARE);
6608 /* On machines without logical shifts, if the operand of the AND is
6609 a logical shift and our mask turns off all the propagated sign
6610 bits, we can replace the logical shift with an arithmetic shift. */
6611 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6612 && !have_insn_for (LSHIFTRT, mode)
6613 && have_insn_for (ASHIFTRT, mode)
6614 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6615 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6616 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6617 && mode_width <= HOST_BITS_PER_WIDE_INT)
6619 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6621 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6622 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6624 gen_rtx_ASHIFTRT (mode,
6625 make_compound_operation
6626 (XEXP (XEXP (x, 0), 0), next_code),
6627 XEXP (XEXP (x, 0), 1)));
6630 /* If the constant is one less than a power of two, this might be
6631 representable by an extraction even if no shift is present.
6632 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6633 we are in a COMPARE. */
6634 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6635 new = make_extraction (mode,
6636 make_compound_operation (XEXP (x, 0),
6638 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6640 /* If we are in a comparison and this is an AND with a power of two,
6641 convert this into the appropriate bit extract. */
6642 else if (in_code == COMPARE
6643 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6644 new = make_extraction (mode,
6645 make_compound_operation (XEXP (x, 0),
6647 i, NULL_RTX, 1, 1, 0, 1);
6652 /* If the sign bit is known to be zero, replace this with an
6653 arithmetic shift. */
6654 if (have_insn_for (ASHIFTRT, mode)
6655 && ! have_insn_for (LSHIFTRT, mode)
6656 && mode_width <= HOST_BITS_PER_WIDE_INT
6657 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6659 new = gen_rtx_ASHIFTRT (mode,
6660 make_compound_operation (XEXP (x, 0),
6666 /* ... fall through ... */
6672 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6673 this is a SIGN_EXTRACT. */
6674 if (GET_CODE (rhs) == CONST_INT
6675 && GET_CODE (lhs) == ASHIFT
6676 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6677 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6679 new = make_compound_operation (XEXP (lhs, 0), next_code);
6680 new = make_extraction (mode, new,
6681 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6682 NULL_RTX, mode_width - INTVAL (rhs),
6683 code == LSHIFTRT, 0, in_code == COMPARE);
6687 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6688 If so, try to merge the shifts into a SIGN_EXTEND. We could
6689 also do this for some cases of SIGN_EXTRACT, but it doesn't
6690 seem worth the effort; the case checked for occurs on Alpha. */
6692 if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o'
6693 && ! (GET_CODE (lhs) == SUBREG
6694 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o'))
6695 && GET_CODE (rhs) == CONST_INT
6696 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6697 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6698 new = make_extraction (mode, make_compound_operation (new, next_code),
6699 0, NULL_RTX, mode_width - INTVAL (rhs),
6700 code == LSHIFTRT, 0, in_code == COMPARE);
6705 /* Call ourselves recursively on the inner expression. If we are
6706 narrowing the object and it has a different RTL code from
6707 what it originally did, do this SUBREG as a force_to_mode. */
6709 tem = make_compound_operation (SUBREG_REG (x), in_code);
6710 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6711 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6712 && subreg_lowpart_p (x))
6714 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
6717 /* If we have something other than a SUBREG, we might have
6718 done an expansion, so rerun ourselves. */
6719 if (GET_CODE (newer) != SUBREG)
6720 newer = make_compound_operation (newer, in_code);
6725 /* If this is a paradoxical subreg, and the new code is a sign or
6726 zero extension, omit the subreg and widen the extension. If it
6727 is a regular subreg, we can still get rid of the subreg by not
6728 widening so much, or in fact removing the extension entirely. */
6729 if ((GET_CODE (tem) == SIGN_EXTEND
6730 || GET_CODE (tem) == ZERO_EXTEND)
6731 && subreg_lowpart_p (x))
6733 if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (tem))
6734 || (GET_MODE_SIZE (mode) >
6735 GET_MODE_SIZE (GET_MODE (XEXP (tem, 0)))))
6737 if (! INTEGRAL_MODE_P (mode))
6739 tem = gen_rtx_fmt_e (GET_CODE (tem), mode, XEXP (tem, 0));
6742 tem = gen_lowpart_for_combine (mode, XEXP (tem, 0));
6753 x = gen_lowpart_for_combine (mode, new);
6754 code = GET_CODE (x);
6757 /* Now recursively process each operand of this operation. */
6758 fmt = GET_RTX_FORMAT (code);
6759 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6762 new = make_compound_operation (XEXP (x, i), next_code);
6763 SUBST (XEXP (x, i), new);
6769 /* Given M see if it is a value that would select a field of bits
6770 within an item, but not the entire word. Return -1 if not.
6771 Otherwise, return the starting position of the field, where 0 is the
6774 *PLEN is set to the length of the field. */
6777 get_pos_from_mask (m, plen)
6778 unsigned HOST_WIDE_INT m;
6779 unsigned HOST_WIDE_INT *plen;
6781 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6782 int pos = exact_log2 (m & -m);
6788 /* Now shift off the low-order zero bits and see if we have a power of
6790 len = exact_log2 ((m >> pos) + 1);
6799 /* See if X can be simplified knowing that we will only refer to it in
6800 MODE and will only refer to those bits that are nonzero in MASK.
6801 If other bits are being computed or if masking operations are done
6802 that select a superset of the bits in MASK, they can sometimes be
6805 Return a possibly simplified expression, but always convert X to
6806 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6808 Also, if REG is nonzero and X is a register equal in value to REG,
6811 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6812 are all off in X. This is used when X will be complemented, by either
6813 NOT, NEG, or XOR. */
6816 force_to_mode (x, mode, mask, reg, just_select)
6818 enum machine_mode mode;
6819 unsigned HOST_WIDE_INT mask;
6823 enum rtx_code code = GET_CODE (x);
6824 int next_select = just_select || code == XOR || code == NOT || code == NEG;
6825 enum machine_mode op_mode;
6826 unsigned HOST_WIDE_INT fuller_mask, nonzero;
6829 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6830 code below will do the wrong thing since the mode of such an
6831 expression is VOIDmode.
6833 Also do nothing if X is a CLOBBER; this can happen if X was
6834 the return value from a call to gen_lowpart_for_combine. */
6835 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6838 /* We want to perform the operation is its present mode unless we know
6839 that the operation is valid in MODE, in which case we do the operation
6841 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6842 && have_insn_for (code, mode))
6843 ? mode : GET_MODE (x));
6845 /* It is not valid to do a right-shift in a narrower mode
6846 than the one it came in with. */
6847 if ((code == LSHIFTRT || code == ASHIFTRT)
6848 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6849 op_mode = GET_MODE (x);
6851 /* Truncate MASK to fit OP_MODE. */
6853 mask &= GET_MODE_MASK (op_mode);
6855 /* When we have an arithmetic operation, or a shift whose count we
6856 do not know, we need to assume that all bit the up to the highest-order
6857 bit in MASK will be needed. This is how we form such a mask. */
6859 fuller_mask = (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT
6860 ? GET_MODE_MASK (op_mode)
6861 : (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
6864 fuller_mask = ~(HOST_WIDE_INT) 0;
6866 /* Determine what bits of X are guaranteed to be (non)zero. */
6867 nonzero = nonzero_bits (x, mode);
6869 /* If none of the bits in X are needed, return a zero. */
6870 if (! just_select && (nonzero & mask) == 0)
6873 /* If X is a CONST_INT, return a new one. Do this here since the
6874 test below will fail. */
6875 if (GET_CODE (x) == CONST_INT)
6877 if (SCALAR_INT_MODE_P (mode))
6878 return gen_int_mode (INTVAL (x) & mask, mode);
6881 x = GEN_INT (INTVAL (x) & mask);
6882 return gen_lowpart_common (mode, x);
6886 /* If X is narrower than MODE and we want all the bits in X's mode, just
6887 get X in the proper mode. */
6888 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6889 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
6890 return gen_lowpart_for_combine (mode, x);
6892 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6893 MASK are already known to be zero in X, we need not do anything. */
6894 if (GET_MODE (x) == mode && code != SUBREG && (~mask & nonzero) == 0)
6900 /* If X is a (clobber (const_int)), return it since we know we are
6901 generating something that won't match. */
6905 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6906 spanned the boundary of the MEM. If we are now masking so it is
6907 within that boundary, we don't need the USE any more. */
6908 if (! BITS_BIG_ENDIAN
6909 && (mask & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6910 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6917 x = expand_compound_operation (x);
6918 if (GET_CODE (x) != code)
6919 return force_to_mode (x, mode, mask, reg, next_select);
6923 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6924 || rtx_equal_p (reg, get_last_value (x))))
6929 if (subreg_lowpart_p (x)
6930 /* We can ignore the effect of this SUBREG if it narrows the mode or
6931 if the constant masks to zero all the bits the mode doesn't
6933 && ((GET_MODE_SIZE (GET_MODE (x))
6934 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6936 & GET_MODE_MASK (GET_MODE (x))
6937 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6938 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
6942 /* If this is an AND with a constant, convert it into an AND
6943 whose constant is the AND of that constant with MASK. If it
6944 remains an AND of MASK, delete it since it is redundant. */
6946 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6948 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6949 mask & INTVAL (XEXP (x, 1)));
6951 /* If X is still an AND, see if it is an AND with a mask that
6952 is just some low-order bits. If so, and it is MASK, we don't
6955 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6956 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
6960 /* If it remains an AND, try making another AND with the bits
6961 in the mode mask that aren't in MASK turned on. If the
6962 constant in the AND is wide enough, this might make a
6963 cheaper constant. */
6965 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6966 && GET_MODE_MASK (GET_MODE (x)) != mask
6967 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6969 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6970 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
6971 int width = GET_MODE_BITSIZE (GET_MODE (x));
6974 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6975 number, sign extend it. */
6976 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6977 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6978 cval |= (HOST_WIDE_INT) -1 << width;
6980 y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
6981 if (rtx_cost (y, SET) < rtx_cost (x, SET))
6991 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6992 low-order bits (as in an alignment operation) and FOO is already
6993 aligned to that boundary, mask C1 to that boundary as well.
6994 This may eliminate that PLUS and, later, the AND. */
6997 unsigned int width = GET_MODE_BITSIZE (mode);
6998 unsigned HOST_WIDE_INT smask = mask;
7000 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
7001 number, sign extend it. */
7003 if (width < HOST_BITS_PER_WIDE_INT
7004 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7005 smask |= (HOST_WIDE_INT) -1 << width;
7007 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7008 && exact_log2 (- smask) >= 0
7009 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
7010 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
7011 return force_to_mode (plus_constant (XEXP (x, 0),
7012 (INTVAL (XEXP (x, 1)) & smask)),
7013 mode, smask, reg, next_select);
7016 /* ... fall through ... */
7019 /* For PLUS, MINUS and MULT, we need any bits less significant than the
7020 most significant bit in MASK since carries from those bits will
7021 affect the bits we are interested in. */
7026 /* If X is (minus C Y) where C's least set bit is larger than any bit
7027 in the mask, then we may replace with (neg Y). */
7028 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7029 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
7030 & -INTVAL (XEXP (x, 0))))
7033 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
7035 return force_to_mode (x, mode, mask, reg, next_select);
7038 /* Similarly, if C contains every bit in the fuller_mask, then we may
7039 replace with (not Y). */
7040 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7041 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
7042 == INTVAL (XEXP (x, 0))))
7044 x = simplify_gen_unary (NOT, GET_MODE (x),
7045 XEXP (x, 1), GET_MODE (x));
7046 return force_to_mode (x, mode, mask, reg, next_select);
7054 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7055 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7056 operation which may be a bitfield extraction. Ensure that the
7057 constant we form is not wider than the mode of X. */
7059 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7060 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7061 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7062 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7063 && GET_CODE (XEXP (x, 1)) == CONST_INT
7064 && ((INTVAL (XEXP (XEXP (x, 0), 1))
7065 + floor_log2 (INTVAL (XEXP (x, 1))))
7066 < GET_MODE_BITSIZE (GET_MODE (x)))
7067 && (INTVAL (XEXP (x, 1))
7068 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
7070 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
7071 << INTVAL (XEXP (XEXP (x, 0), 1)));
7072 temp = gen_binary (GET_CODE (x), GET_MODE (x),
7073 XEXP (XEXP (x, 0), 0), temp);
7074 x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
7075 XEXP (XEXP (x, 0), 1));
7076 return force_to_mode (x, mode, mask, reg, next_select);
7080 /* For most binary operations, just propagate into the operation and
7081 change the mode if we have an operation of that mode. */
7083 op0 = gen_lowpart_for_combine (op_mode,
7084 force_to_mode (XEXP (x, 0), mode, mask,
7086 op1 = gen_lowpart_for_combine (op_mode,
7087 force_to_mode (XEXP (x, 1), mode, mask,
7090 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7091 x = gen_binary (code, op_mode, op0, op1);
7095 /* For left shifts, do the same, but just for the first operand.
7096 However, we cannot do anything with shifts where we cannot
7097 guarantee that the counts are smaller than the size of the mode
7098 because such a count will have a different meaning in a
7101 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
7102 && INTVAL (XEXP (x, 1)) >= 0
7103 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
7104 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
7105 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
7106 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
7109 /* If the shift count is a constant and we can do arithmetic in
7110 the mode of the shift, refine which bits we need. Otherwise, use the
7111 conservative form of the mask. */
7112 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7113 && INTVAL (XEXP (x, 1)) >= 0
7114 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
7115 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7116 mask >>= INTVAL (XEXP (x, 1));
7120 op0 = gen_lowpart_for_combine (op_mode,
7121 force_to_mode (XEXP (x, 0), op_mode,
7122 mask, reg, next_select));
7124 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7125 x = gen_binary (code, op_mode, op0, XEXP (x, 1));
7129 /* Here we can only do something if the shift count is a constant,
7130 this shift constant is valid for the host, and we can do arithmetic
7133 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7134 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7135 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7137 rtx inner = XEXP (x, 0);
7138 unsigned HOST_WIDE_INT inner_mask;
7140 /* Select the mask of the bits we need for the shift operand. */
7141 inner_mask = mask << INTVAL (XEXP (x, 1));
7143 /* We can only change the mode of the shift if we can do arithmetic
7144 in the mode of the shift and INNER_MASK is no wider than the
7145 width of OP_MODE. */
7146 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT
7147 || (inner_mask & ~GET_MODE_MASK (op_mode)) != 0)
7148 op_mode = GET_MODE (x);
7150 inner = force_to_mode (inner, op_mode, inner_mask, reg, next_select);
7152 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7153 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7156 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7157 shift and AND produces only copies of the sign bit (C2 is one less
7158 than a power of two), we can do this with just a shift. */
7160 if (GET_CODE (x) == LSHIFTRT
7161 && GET_CODE (XEXP (x, 1)) == CONST_INT
7162 /* The shift puts one of the sign bit copies in the least significant
7164 && ((INTVAL (XEXP (x, 1))
7165 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7166 >= GET_MODE_BITSIZE (GET_MODE (x)))
7167 && exact_log2 (mask + 1) >= 0
7168 /* Number of bits left after the shift must be more than the mask
7170 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7171 <= GET_MODE_BITSIZE (GET_MODE (x)))
7172 /* Must be more sign bit copies than the mask needs. */
7173 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7174 >= exact_log2 (mask + 1)))
7175 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7176 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7177 - exact_log2 (mask + 1)));
7182 /* If we are just looking for the sign bit, we don't need this shift at
7183 all, even if it has a variable count. */
7184 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7185 && (mask == ((unsigned HOST_WIDE_INT) 1
7186 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7187 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7189 /* If this is a shift by a constant, get a mask that contains those bits
7190 that are not copies of the sign bit. We then have two cases: If
7191 MASK only includes those bits, this can be a logical shift, which may
7192 allow simplifications. If MASK is a single-bit field not within
7193 those bits, we are requesting a copy of the sign bit and hence can
7194 shift the sign bit to the appropriate location. */
7196 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7197 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7201 /* If the considered data is wider than HOST_WIDE_INT, we can't
7202 represent a mask for all its bits in a single scalar.
7203 But we only care about the lower bits, so calculate these. */
7205 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7207 nonzero = ~(HOST_WIDE_INT) 0;
7209 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7210 is the number of bits a full-width mask would have set.
7211 We need only shift if these are fewer than nonzero can
7212 hold. If not, we must keep all bits set in nonzero. */
7214 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7215 < HOST_BITS_PER_WIDE_INT)
7216 nonzero >>= INTVAL (XEXP (x, 1))
7217 + HOST_BITS_PER_WIDE_INT
7218 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7222 nonzero = GET_MODE_MASK (GET_MODE (x));
7223 nonzero >>= INTVAL (XEXP (x, 1));
7226 if ((mask & ~nonzero) == 0
7227 || (i = exact_log2 (mask)) >= 0)
7229 x = simplify_shift_const
7230 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7231 i < 0 ? INTVAL (XEXP (x, 1))
7232 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7234 if (GET_CODE (x) != ASHIFTRT)
7235 return force_to_mode (x, mode, mask, reg, next_select);
7239 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7240 even if the shift count isn't a constant. */
7242 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
7246 /* If this is a zero- or sign-extension operation that just affects bits
7247 we don't care about, remove it. Be sure the call above returned
7248 something that is still a shift. */
7250 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7251 && GET_CODE (XEXP (x, 1)) == CONST_INT
7252 && INTVAL (XEXP (x, 1)) >= 0
7253 && (INTVAL (XEXP (x, 1))
7254 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7255 && GET_CODE (XEXP (x, 0)) == ASHIFT
7256 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7257 && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1)))
7258 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7265 /* If the shift count is constant and we can do computations
7266 in the mode of X, compute where the bits we care about are.
7267 Otherwise, we can't do anything. Don't change the mode of
7268 the shift or propagate MODE into the shift, though. */
7269 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7270 && INTVAL (XEXP (x, 1)) >= 0)
7272 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7273 GET_MODE (x), GEN_INT (mask),
7275 if (temp && GET_CODE(temp) == CONST_INT)
7277 force_to_mode (XEXP (x, 0), GET_MODE (x),
7278 INTVAL (temp), reg, next_select));
7283 /* If we just want the low-order bit, the NEG isn't needed since it
7284 won't change the low-order bit. */
7286 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
7288 /* We need any bits less significant than the most significant bit in
7289 MASK since carries from those bits will affect the bits we are
7295 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7296 same as the XOR case above. Ensure that the constant we form is not
7297 wider than the mode of X. */
7299 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7300 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7301 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7302 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7303 < GET_MODE_BITSIZE (GET_MODE (x)))
7304 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7306 temp = GEN_INT (mask << INTVAL (XEXP (XEXP (x, 0), 1)));
7307 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
7308 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
7310 return force_to_mode (x, mode, mask, reg, next_select);
7313 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7314 use the full mask inside the NOT. */
7318 op0 = gen_lowpart_for_combine (op_mode,
7319 force_to_mode (XEXP (x, 0), mode, mask,
7321 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7322 x = simplify_gen_unary (code, op_mode, op0, op_mode);
7326 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7327 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7328 which is equal to STORE_FLAG_VALUE. */
7329 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7330 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7331 && nonzero_bits (XEXP (x, 0), mode) == STORE_FLAG_VALUE)
7332 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7337 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7338 written in a narrower mode. We play it safe and do not do so. */
7341 gen_lowpart_for_combine (GET_MODE (x),
7342 force_to_mode (XEXP (x, 1), mode,
7343 mask, reg, next_select)));
7345 gen_lowpart_for_combine (GET_MODE (x),
7346 force_to_mode (XEXP (x, 2), mode,
7347 mask, reg,next_select)));
7354 /* Ensure we return a value of the proper mode. */
7355 return gen_lowpart_for_combine (mode, x);
7358 /* Return nonzero if X is an expression that has one of two values depending on
7359 whether some other value is zero or nonzero. In that case, we return the
7360 value that is being tested, *PTRUE is set to the value if the rtx being
7361 returned has a nonzero value, and *PFALSE is set to the other alternative.
7363 If we return zero, we set *PTRUE and *PFALSE to X. */
7366 if_then_else_cond (x, ptrue, pfalse)
7368 rtx *ptrue, *pfalse;
7370 enum machine_mode mode = GET_MODE (x);
7371 enum rtx_code code = GET_CODE (x);
7372 rtx cond0, cond1, true0, true1, false0, false1;
7373 unsigned HOST_WIDE_INT nz;
7375 /* If we are comparing a value against zero, we are done. */
7376 if ((code == NE || code == EQ)
7377 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 0)
7379 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7380 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7384 /* If this is a unary operation whose operand has one of two values, apply
7385 our opcode to compute those values. */
7386 else if (GET_RTX_CLASS (code) == '1'
7387 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7389 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7390 *pfalse = simplify_gen_unary (code, mode, false0,
7391 GET_MODE (XEXP (x, 0)));
7395 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7396 make can't possibly match and would suppress other optimizations. */
7397 else if (code == COMPARE)
7400 /* If this is a binary operation, see if either side has only one of two
7401 values. If either one does or if both do and they are conditional on
7402 the same value, compute the new true and false values. */
7403 else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2'
7404 || GET_RTX_CLASS (code) == '<')
7406 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7407 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7409 if ((cond0 != 0 || cond1 != 0)
7410 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7412 /* If if_then_else_cond returned zero, then true/false are the
7413 same rtl. We must copy one of them to prevent invalid rtl
7416 true0 = copy_rtx (true0);
7417 else if (cond1 == 0)
7418 true1 = copy_rtx (true1);
7420 *ptrue = gen_binary (code, mode, true0, true1);
7421 *pfalse = gen_binary (code, mode, false0, false1);
7422 return cond0 ? cond0 : cond1;
7425 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7426 operands is zero when the other is nonzero, and vice-versa,
7427 and STORE_FLAG_VALUE is 1 or -1. */
7429 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7430 && (code == PLUS || code == IOR || code == XOR || code == MINUS
7432 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7434 rtx op0 = XEXP (XEXP (x, 0), 1);
7435 rtx op1 = XEXP (XEXP (x, 1), 1);
7437 cond0 = XEXP (XEXP (x, 0), 0);
7438 cond1 = XEXP (XEXP (x, 1), 0);
7440 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7441 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7442 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7443 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7444 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7445 || ((swap_condition (GET_CODE (cond0))
7446 == combine_reversed_comparison_code (cond1))
7447 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7448 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7449 && ! side_effects_p (x))
7451 *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
7452 *pfalse = gen_binary (MULT, mode,
7454 ? simplify_gen_unary (NEG, mode, op1,
7462 /* Similarly for MULT, AND and UMIN, except that for these the result
7464 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7465 && (code == MULT || code == AND || code == UMIN)
7466 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7468 cond0 = XEXP (XEXP (x, 0), 0);
7469 cond1 = XEXP (XEXP (x, 1), 0);
7471 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7472 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7473 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7474 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7475 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7476 || ((swap_condition (GET_CODE (cond0))
7477 == combine_reversed_comparison_code (cond1))
7478 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7479 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7480 && ! side_effects_p (x))
7482 *ptrue = *pfalse = const0_rtx;
7488 else if (code == IF_THEN_ELSE)
7490 /* If we have IF_THEN_ELSE already, extract the condition and
7491 canonicalize it if it is NE or EQ. */
7492 cond0 = XEXP (x, 0);
7493 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7494 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7495 return XEXP (cond0, 0);
7496 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7498 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7499 return XEXP (cond0, 0);
7505 /* If X is a SUBREG, we can narrow both the true and false values
7506 if the inner expression, if there is a condition. */
7507 else if (code == SUBREG
7508 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7511 *ptrue = simplify_gen_subreg (mode, true0,
7512 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7513 *pfalse = simplify_gen_subreg (mode, false0,
7514 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7519 /* If X is a constant, this isn't special and will cause confusions
7520 if we treat it as such. Likewise if it is equivalent to a constant. */
7521 else if (CONSTANT_P (x)
7522 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7525 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7526 will be least confusing to the rest of the compiler. */
7527 else if (mode == BImode)
7529 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7533 /* If X is known to be either 0 or -1, those are the true and
7534 false values when testing X. */
7535 else if (x == constm1_rtx || x == const0_rtx
7536 || (mode != VOIDmode
7537 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7539 *ptrue = constm1_rtx, *pfalse = const0_rtx;
7543 /* Likewise for 0 or a single bit. */
7544 else if (mode != VOIDmode
7545 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7546 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7548 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
7552 /* Otherwise fail; show no condition with true and false values the same. */
7553 *ptrue = *pfalse = x;
7557 /* Return the value of expression X given the fact that condition COND
7558 is known to be true when applied to REG as its first operand and VAL
7559 as its second. X is known to not be shared and so can be modified in
7562 We only handle the simplest cases, and specifically those cases that
7563 arise with IF_THEN_ELSE expressions. */
7566 known_cond (x, cond, reg, val)
7571 enum rtx_code code = GET_CODE (x);
7576 if (side_effects_p (x))
7579 /* If either operand of the condition is a floating point value,
7580 then we have to avoid collapsing an EQ comparison. */
7582 && rtx_equal_p (x, reg)
7583 && ! FLOAT_MODE_P (GET_MODE (x))
7584 && ! FLOAT_MODE_P (GET_MODE (val)))
7587 if (cond == UNEQ && rtx_equal_p (x, reg))
7590 /* If X is (abs REG) and we know something about REG's relationship
7591 with zero, we may be able to simplify this. */
7593 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7596 case GE: case GT: case EQ:
7599 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
7601 GET_MODE (XEXP (x, 0)));
7606 /* The only other cases we handle are MIN, MAX, and comparisons if the
7607 operands are the same as REG and VAL. */
7609 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
7611 if (rtx_equal_p (XEXP (x, 0), val))
7612 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7614 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7616 if (GET_RTX_CLASS (code) == '<')
7618 if (comparison_dominates_p (cond, code))
7619 return const_true_rtx;
7621 code = combine_reversed_comparison_code (x);
7623 && comparison_dominates_p (cond, code))
7628 else if (code == SMAX || code == SMIN
7629 || code == UMIN || code == UMAX)
7631 int unsignedp = (code == UMIN || code == UMAX);
7633 /* Do not reverse the condition when it is NE or EQ.
7634 This is because we cannot conclude anything about
7635 the value of 'SMAX (x, y)' when x is not equal to y,
7636 but we can when x equals y. */
7637 if ((code == SMAX || code == UMAX)
7638 && ! (cond == EQ || cond == NE))
7639 cond = reverse_condition (cond);
7644 return unsignedp ? x : XEXP (x, 1);
7646 return unsignedp ? x : XEXP (x, 0);
7648 return unsignedp ? XEXP (x, 1) : x;
7650 return unsignedp ? XEXP (x, 0) : x;
7657 else if (code == SUBREG)
7659 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
7660 rtx new, r = known_cond (SUBREG_REG (x), cond, reg, val);
7662 if (SUBREG_REG (x) != r)
7664 /* We must simplify subreg here, before we lose track of the
7665 original inner_mode. */
7666 new = simplify_subreg (GET_MODE (x), r,
7667 inner_mode, SUBREG_BYTE (x));
7671 SUBST (SUBREG_REG (x), r);
7676 /* We don't have to handle SIGN_EXTEND here, because even in the
7677 case of replacing something with a modeless CONST_INT, a
7678 CONST_INT is already (supposed to be) a valid sign extension for
7679 its narrower mode, which implies it's already properly
7680 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7681 story is different. */
7682 else if (code == ZERO_EXTEND)
7684 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
7685 rtx new, r = known_cond (XEXP (x, 0), cond, reg, val);
7687 if (XEXP (x, 0) != r)
7689 /* We must simplify the zero_extend here, before we lose
7690 track of the original inner_mode. */
7691 new = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
7696 SUBST (XEXP (x, 0), r);
7702 fmt = GET_RTX_FORMAT (code);
7703 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7706 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7707 else if (fmt[i] == 'E')
7708 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7709 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7716 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7717 assignment as a field assignment. */
7720 rtx_equal_for_field_assignment_p (x, y)
7724 if (x == y || rtx_equal_p (x, y))
7727 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7730 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7731 Note that all SUBREGs of MEM are paradoxical; otherwise they
7732 would have been rewritten. */
7733 if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG
7734 && GET_CODE (SUBREG_REG (y)) == MEM
7735 && rtx_equal_p (SUBREG_REG (y),
7736 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x)))
7739 if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG
7740 && GET_CODE (SUBREG_REG (x)) == MEM
7741 && rtx_equal_p (SUBREG_REG (x),
7742 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y)))
7745 /* We used to see if get_last_value of X and Y were the same but that's
7746 not correct. In one direction, we'll cause the assignment to have
7747 the wrong destination and in the case, we'll import a register into this
7748 insn that might have already have been dead. So fail if none of the
7749 above cases are true. */
7753 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7754 Return that assignment if so.
7756 We only handle the most common cases. */
7759 make_field_assignment (x)
7762 rtx dest = SET_DEST (x);
7763 rtx src = SET_SRC (x);
7768 unsigned HOST_WIDE_INT len;
7770 enum machine_mode mode;
7772 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7773 a clear of a one-bit field. We will have changed it to
7774 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7777 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7778 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7779 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7780 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7782 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7785 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7789 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7790 && subreg_lowpart_p (XEXP (src, 0))
7791 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7792 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7793 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7794 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7795 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7797 assign = make_extraction (VOIDmode, dest, 0,
7798 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7801 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7805 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7807 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7808 && XEXP (XEXP (src, 0), 0) == const1_rtx
7809 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7811 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7814 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7818 /* The other case we handle is assignments into a constant-position
7819 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7820 a mask that has all one bits except for a group of zero bits and
7821 OTHER is known to have zeros where C1 has ones, this is such an
7822 assignment. Compute the position and length from C1. Shift OTHER
7823 to the appropriate position, force it to the required mode, and
7824 make the extraction. Check for the AND in both operands. */
7826 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7829 rhs = expand_compound_operation (XEXP (src, 0));
7830 lhs = expand_compound_operation (XEXP (src, 1));
7832 if (GET_CODE (rhs) == AND
7833 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7834 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7835 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7836 else if (GET_CODE (lhs) == AND
7837 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7838 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7839 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7843 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7844 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7845 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7846 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7849 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7853 /* The mode to use for the source is the mode of the assignment, or of
7854 what is inside a possible STRICT_LOW_PART. */
7855 mode = (GET_CODE (assign) == STRICT_LOW_PART
7856 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7858 /* Shift OTHER right POS places and make it the source, restricting it
7859 to the proper length and mode. */
7861 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
7862 GET_MODE (src), other, pos),
7864 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7865 ? ~(unsigned HOST_WIDE_INT) 0
7866 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7869 return gen_rtx_SET (VOIDmode, assign, src);
7872 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7876 apply_distributive_law (x)
7879 enum rtx_code code = GET_CODE (x);
7880 rtx lhs, rhs, other;
7882 enum rtx_code inner_code;
7884 /* Distributivity is not true for floating point.
7885 It can change the value. So don't do it.
7886 -- rms and moshier@world.std.com. */
7887 if (FLOAT_MODE_P (GET_MODE (x)))
7890 /* The outer operation can only be one of the following: */
7891 if (code != IOR && code != AND && code != XOR
7892 && code != PLUS && code != MINUS)
7895 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
7897 /* If either operand is a primitive we can't do anything, so get out
7899 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
7900 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
7903 lhs = expand_compound_operation (lhs);
7904 rhs = expand_compound_operation (rhs);
7905 inner_code = GET_CODE (lhs);
7906 if (inner_code != GET_CODE (rhs))
7909 /* See if the inner and outer operations distribute. */
7916 /* These all distribute except over PLUS. */
7917 if (code == PLUS || code == MINUS)
7922 if (code != PLUS && code != MINUS)
7927 /* This is also a multiply, so it distributes over everything. */
7931 /* Non-paradoxical SUBREGs distributes over all operations, provided
7932 the inner modes and byte offsets are the same, this is an extraction
7933 of a low-order part, we don't convert an fp operation to int or
7934 vice versa, and we would not be converting a single-word
7935 operation into a multi-word operation. The latter test is not
7936 required, but it prevents generating unneeded multi-word operations.
7937 Some of the previous tests are redundant given the latter test, but
7938 are retained because they are required for correctness.
7940 We produce the result slightly differently in this case. */
7942 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7943 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
7944 || ! subreg_lowpart_p (lhs)
7945 || (GET_MODE_CLASS (GET_MODE (lhs))
7946 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7947 || (GET_MODE_SIZE (GET_MODE (lhs))
7948 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7949 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
7952 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7953 SUBREG_REG (lhs), SUBREG_REG (rhs));
7954 return gen_lowpart_for_combine (GET_MODE (x), tem);
7960 /* Set LHS and RHS to the inner operands (A and B in the example
7961 above) and set OTHER to the common operand (C in the example).
7962 These is only one way to do this unless the inner operation is
7964 if (GET_RTX_CLASS (inner_code) == 'c'
7965 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
7966 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
7967 else if (GET_RTX_CLASS (inner_code) == 'c'
7968 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7969 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7970 else if (GET_RTX_CLASS (inner_code) == 'c'
7971 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
7972 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
7973 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
7974 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
7978 /* Form the new inner operation, seeing if it simplifies first. */
7979 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
7981 /* There is one exception to the general way of distributing:
7982 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
7983 if (code == XOR && inner_code == IOR)
7986 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
7989 /* We may be able to continuing distributing the result, so call
7990 ourselves recursively on the inner operation before forming the
7991 outer operation, which we return. */
7992 return gen_binary (inner_code, GET_MODE (x),
7993 apply_distributive_law (tem), other);
7996 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7999 Return an equivalent form, if different from X. Otherwise, return X. If
8000 X is zero, we are to always construct the equivalent form. */
8003 simplify_and_const_int (x, mode, varop, constop)
8005 enum machine_mode mode;
8007 unsigned HOST_WIDE_INT constop;
8009 unsigned HOST_WIDE_INT nonzero;
8012 /* Simplify VAROP knowing that we will be only looking at some of the
8015 Note by passing in CONSTOP, we guarantee that the bits not set in
8016 CONSTOP are not significant and will never be examined. We must
8017 ensure that is the case by explicitly masking out those bits
8018 before returning. */
8019 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
8021 /* If VAROP is a CLOBBER, we will fail so return it. */
8022 if (GET_CODE (varop) == CLOBBER)
8025 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8026 to VAROP and return the new constant. */
8027 if (GET_CODE (varop) == CONST_INT)
8028 return GEN_INT (trunc_int_for_mode (INTVAL (varop) & constop, mode));
8030 /* See what bits may be nonzero in VAROP. Unlike the general case of
8031 a call to nonzero_bits, here we don't care about bits outside
8034 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
8036 /* Turn off all bits in the constant that are known to already be zero.
8037 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8038 which is tested below. */
8042 /* If we don't have any bits left, return zero. */
8046 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8047 a power of two, we can replace this with an ASHIFT. */
8048 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
8049 && (i = exact_log2 (constop)) >= 0)
8050 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
8052 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8053 or XOR, then try to apply the distributive law. This may eliminate
8054 operations if either branch can be simplified because of the AND.
8055 It may also make some cases more complex, but those cases probably
8056 won't match a pattern either with or without this. */
8058 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
8060 gen_lowpart_for_combine
8062 apply_distributive_law
8063 (gen_binary (GET_CODE (varop), GET_MODE (varop),
8064 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
8065 XEXP (varop, 0), constop),
8066 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
8067 XEXP (varop, 1), constop))));
8069 /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
8070 the AND and see if one of the operands simplifies to zero. If so, we
8071 may eliminate it. */
8073 if (GET_CODE (varop) == PLUS
8074 && exact_log2 (constop + 1) >= 0)
8078 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
8079 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
8080 if (o0 == const0_rtx)
8082 if (o1 == const0_rtx)
8086 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
8087 if we already had one (just check for the simplest cases). */
8088 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
8089 && GET_MODE (XEXP (x, 0)) == mode
8090 && SUBREG_REG (XEXP (x, 0)) == varop)
8091 varop = XEXP (x, 0);
8093 varop = gen_lowpart_for_combine (mode, varop);
8095 /* If we can't make the SUBREG, try to return what we were given. */
8096 if (GET_CODE (varop) == CLOBBER)
8097 return x ? x : varop;
8099 /* If we are only masking insignificant bits, return VAROP. */
8100 if (constop == nonzero)
8104 /* Otherwise, return an AND. */
8105 constop = trunc_int_for_mode (constop, mode);
8106 /* See how much, if any, of X we can use. */
8107 if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
8108 x = gen_binary (AND, mode, varop, GEN_INT (constop));
8112 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8113 || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop)
8114 SUBST (XEXP (x, 1), GEN_INT (constop));
8116 SUBST (XEXP (x, 0), varop);
8123 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
8124 We don't let nonzero_bits recur into num_sign_bit_copies, because that
8125 is less useful. We can't allow both, because that results in exponential
8126 run time recursion. There is a nullstone testcase that triggered
8127 this. This macro avoids accidental uses of num_sign_bit_copies. */
8128 #define num_sign_bit_copies()
8130 /* Given an expression, X, compute which bits in X can be nonzero.
8131 We don't care about bits outside of those defined in MODE.
8133 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8134 a shift, AND, or zero_extract, we can do better. */
8136 static unsigned HOST_WIDE_INT
8137 nonzero_bits (x, mode)
8139 enum machine_mode mode;
8141 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
8142 unsigned HOST_WIDE_INT inner_nz;
8144 unsigned int mode_width = GET_MODE_BITSIZE (mode);
8147 /* For floating-point values, assume all bits are needed. */
8148 if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode))
8151 /* If X is wider than MODE, use its mode instead. */
8152 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
8154 mode = GET_MODE (x);
8155 nonzero = GET_MODE_MASK (mode);
8156 mode_width = GET_MODE_BITSIZE (mode);
8159 if (mode_width > HOST_BITS_PER_WIDE_INT)
8160 /* Our only callers in this case look for single bit values. So
8161 just return the mode mask. Those tests will then be false. */
8164 #ifndef WORD_REGISTER_OPERATIONS
8165 /* If MODE is wider than X, but both are a single word for both the host
8166 and target machines, we can compute this from which bits of the
8167 object might be nonzero in its own mode, taking into account the fact
8168 that on many CISC machines, accessing an object in a wider mode
8169 causes the high-order bits to become undefined. So they are
8170 not known to be zero. */
8172 if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
8173 && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD
8174 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
8175 && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x)))
8177 nonzero &= nonzero_bits (x, GET_MODE (x));
8178 nonzero |= GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x));
8183 code = GET_CODE (x);
8187 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8188 /* If pointers extend unsigned and this is a pointer in Pmode, say that
8189 all the bits above ptr_mode are known to be zero. */
8190 if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
8192 nonzero &= GET_MODE_MASK (ptr_mode);
8195 /* Include declared information about alignment of pointers. */
8196 /* ??? We don't properly preserve REG_POINTER changes across
8197 pointer-to-integer casts, so we can't trust it except for
8198 things that we know must be pointers. See execute/960116-1.c. */
8199 if ((x == stack_pointer_rtx
8200 || x == frame_pointer_rtx
8201 || x == arg_pointer_rtx)
8202 && REGNO_POINTER_ALIGN (REGNO (x)))
8204 unsigned HOST_WIDE_INT alignment
8205 = REGNO_POINTER_ALIGN (REGNO (x)) / BITS_PER_UNIT;
8207 #ifdef PUSH_ROUNDING
8208 /* If PUSH_ROUNDING is defined, it is possible for the
8209 stack to be momentarily aligned only to that amount,
8210 so we pick the least alignment. */
8211 if (x == stack_pointer_rtx && PUSH_ARGS)
8212 alignment = MIN (PUSH_ROUNDING (1), alignment);
8215 nonzero &= ~(alignment - 1);
8218 /* If X is a register whose nonzero bits value is current, use it.
8219 Otherwise, if X is a register whose value we can find, use that
8220 value. Otherwise, use the previously-computed global nonzero bits
8221 for this register. */
8223 if (reg_last_set_value[REGNO (x)] != 0
8224 && (reg_last_set_mode[REGNO (x)] == mode
8225 || (GET_MODE_CLASS (reg_last_set_mode[REGNO (x)]) == MODE_INT
8226 && GET_MODE_CLASS (mode) == MODE_INT))
8227 && (reg_last_set_label[REGNO (x)] == label_tick
8228 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8229 && REG_N_SETS (REGNO (x)) == 1
8230 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start,
8232 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8233 return reg_last_set_nonzero_bits[REGNO (x)] & nonzero;
8235 tem = get_last_value (x);
8239 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8240 /* If X is narrower than MODE and TEM is a non-negative
8241 constant that would appear negative in the mode of X,
8242 sign-extend it for use in reg_nonzero_bits because some
8243 machines (maybe most) will actually do the sign-extension
8244 and this is the conservative approach.
8246 ??? For 2.5, try to tighten up the MD files in this regard
8247 instead of this kludge. */
8249 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width
8250 && GET_CODE (tem) == CONST_INT
8252 && 0 != (INTVAL (tem)
8253 & ((HOST_WIDE_INT) 1
8254 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8255 tem = GEN_INT (INTVAL (tem)
8256 | ((HOST_WIDE_INT) (-1)
8257 << GET_MODE_BITSIZE (GET_MODE (x))));
8259 return nonzero_bits (tem, mode) & nonzero;
8261 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
8263 unsigned HOST_WIDE_INT mask = reg_nonzero_bits[REGNO (x)];
8265 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width)
8266 /* We don't know anything about the upper bits. */
8267 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
8268 return nonzero & mask;
8274 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8275 /* If X is negative in MODE, sign-extend the value. */
8276 if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD
8277 && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1))))
8278 return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width));
8284 #ifdef LOAD_EXTEND_OP
8285 /* In many, if not most, RISC machines, reading a byte from memory
8286 zeros the rest of the register. Noticing that fact saves a lot
8287 of extra zero-extends. */
8288 if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND)
8289 nonzero &= GET_MODE_MASK (GET_MODE (x));
8294 case UNEQ: case LTGT:
8295 case GT: case GTU: case UNGT:
8296 case LT: case LTU: case UNLT:
8297 case GE: case GEU: case UNGE:
8298 case LE: case LEU: case UNLE:
8299 case UNORDERED: case ORDERED:
8301 /* If this produces an integer result, we know which bits are set.
8302 Code here used to clear bits outside the mode of X, but that is
8305 if (GET_MODE_CLASS (mode) == MODE_INT
8306 && mode_width <= HOST_BITS_PER_WIDE_INT)
8307 nonzero = STORE_FLAG_VALUE;
8312 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8313 and num_sign_bit_copies. */
8314 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8315 == GET_MODE_BITSIZE (GET_MODE (x)))
8319 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
8320 nonzero |= (GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x)));
8325 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8326 and num_sign_bit_copies. */
8327 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8328 == GET_MODE_BITSIZE (GET_MODE (x)))
8334 nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode));
8338 nonzero &= nonzero_bits (XEXP (x, 0), mode);
8339 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8340 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8344 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
8345 Otherwise, show all the bits in the outer mode but not the inner
8347 inner_nz = nonzero_bits (XEXP (x, 0), mode);
8348 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8350 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8352 & (((HOST_WIDE_INT) 1
8353 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
8354 inner_nz |= (GET_MODE_MASK (mode)
8355 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
8358 nonzero &= inner_nz;
8362 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
8363 & nonzero_bits (XEXP (x, 1), mode));
8367 case UMIN: case UMAX: case SMIN: case SMAX:
8369 unsigned HOST_WIDE_INT nonzero0 = nonzero_bits (XEXP (x, 0), mode);
8371 /* Don't call nonzero_bits for the second time if it cannot change
8373 if ((nonzero & nonzero0) != nonzero)
8374 nonzero &= (nonzero0 | nonzero_bits (XEXP (x, 1), mode));
8378 case PLUS: case MINUS:
8380 case DIV: case UDIV:
8381 case MOD: case UMOD:
8382 /* We can apply the rules of arithmetic to compute the number of
8383 high- and low-order zero bits of these operations. We start by
8384 computing the width (position of the highest-order nonzero bit)
8385 and the number of low-order zero bits for each value. */
8387 unsigned HOST_WIDE_INT nz0 = nonzero_bits (XEXP (x, 0), mode);
8388 unsigned HOST_WIDE_INT nz1 = nonzero_bits (XEXP (x, 1), mode);
8389 int width0 = floor_log2 (nz0) + 1;
8390 int width1 = floor_log2 (nz1) + 1;
8391 int low0 = floor_log2 (nz0 & -nz0);
8392 int low1 = floor_log2 (nz1 & -nz1);
8393 HOST_WIDE_INT op0_maybe_minusp
8394 = (nz0 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
8395 HOST_WIDE_INT op1_maybe_minusp
8396 = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
8397 unsigned int result_width = mode_width;
8403 result_width = MAX (width0, width1) + 1;
8404 result_low = MIN (low0, low1);
8407 result_low = MIN (low0, low1);
8410 result_width = width0 + width1;
8411 result_low = low0 + low1;
8416 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8417 result_width = width0;
8422 result_width = width0;
8427 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8428 result_width = MIN (width0, width1);
8429 result_low = MIN (low0, low1);
8434 result_width = MIN (width0, width1);
8435 result_low = MIN (low0, low1);
8441 if (result_width < mode_width)
8442 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
8445 nonzero &= ~(((HOST_WIDE_INT) 1 << result_low) - 1);
8447 #ifdef POINTERS_EXTEND_UNSIGNED
8448 /* If pointers extend unsigned and this is an addition or subtraction
8449 to a pointer in Pmode, all the bits above ptr_mode are known to be
8451 if (POINTERS_EXTEND_UNSIGNED > 0 && GET_MODE (x) == Pmode
8452 && (code == PLUS || code == MINUS)
8453 && GET_CODE (XEXP (x, 0)) == REG && REG_POINTER (XEXP (x, 0)))
8454 nonzero &= GET_MODE_MASK (ptr_mode);
8460 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8461 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8462 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
8466 /* If this is a SUBREG formed for a promoted variable that has
8467 been zero-extended, we know that at least the high-order bits
8468 are zero, though others might be too. */
8470 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x) > 0)
8471 nonzero = (GET_MODE_MASK (GET_MODE (x))
8472 & nonzero_bits (SUBREG_REG (x), GET_MODE (x)));
8474 /* If the inner mode is a single word for both the host and target
8475 machines, we can compute this from which bits of the inner
8476 object might be nonzero. */
8477 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
8478 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8479 <= HOST_BITS_PER_WIDE_INT))
8481 nonzero &= nonzero_bits (SUBREG_REG (x), mode);
8483 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8484 /* If this is a typical RISC machine, we only have to worry
8485 about the way loads are extended. */
8486 if ((LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
8488 & (((unsigned HOST_WIDE_INT) 1
8489 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) - 1))))
8491 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) != ZERO_EXTEND)
8492 || GET_CODE (SUBREG_REG (x)) != MEM)
8495 /* On many CISC machines, accessing an object in a wider mode
8496 causes the high-order bits to become undefined. So they are
8497 not known to be zero. */
8498 if (GET_MODE_SIZE (GET_MODE (x))
8499 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8500 nonzero |= (GET_MODE_MASK (GET_MODE (x))
8501 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
8510 /* The nonzero bits are in two classes: any bits within MODE
8511 that aren't in GET_MODE (x) are always significant. The rest of the
8512 nonzero bits are those that are significant in the operand of
8513 the shift when shifted the appropriate number of bits. This
8514 shows that high-order bits are cleared by the right shift and
8515 low-order bits by left shifts. */
8516 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8517 && INTVAL (XEXP (x, 1)) >= 0
8518 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8520 enum machine_mode inner_mode = GET_MODE (x);
8521 unsigned int width = GET_MODE_BITSIZE (inner_mode);
8522 int count = INTVAL (XEXP (x, 1));
8523 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
8524 unsigned HOST_WIDE_INT op_nonzero = nonzero_bits (XEXP (x, 0), mode);
8525 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
8526 unsigned HOST_WIDE_INT outer = 0;
8528 if (mode_width > width)
8529 outer = (op_nonzero & nonzero & ~mode_mask);
8531 if (code == LSHIFTRT)
8533 else if (code == ASHIFTRT)
8537 /* If the sign bit may have been nonzero before the shift, we
8538 need to mark all the places it could have been copied to
8539 by the shift as possibly nonzero. */
8540 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
8541 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
8543 else if (code == ASHIFT)
8546 inner = ((inner << (count % width)
8547 | (inner >> (width - (count % width)))) & mode_mask);
8549 nonzero &= (outer | inner);
8554 /* This is at most the number of bits in the mode. */
8555 nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1;
8559 nonzero &= (nonzero_bits (XEXP (x, 1), mode)
8560 | nonzero_bits (XEXP (x, 2), mode));
8570 /* See the macro definition above. */
8571 #undef num_sign_bit_copies
8573 /* Return the number of bits at the high-order end of X that are known to
8574 be equal to the sign bit. X will be used in mode MODE; if MODE is
8575 VOIDmode, X will be used in its own mode. The returned value will always
8576 be between 1 and the number of bits in MODE. */
8579 num_sign_bit_copies (x, mode)
8581 enum machine_mode mode;
8583 enum rtx_code code = GET_CODE (x);
8584 unsigned int bitwidth;
8585 int num0, num1, result;
8586 unsigned HOST_WIDE_INT nonzero;
8589 /* If we weren't given a mode, use the mode of X. If the mode is still
8590 VOIDmode, we don't know anything. Likewise if one of the modes is
8593 if (mode == VOIDmode)
8594 mode = GET_MODE (x);
8596 if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)))
8599 bitwidth = GET_MODE_BITSIZE (mode);
8601 /* For a smaller object, just ignore the high bits. */
8602 if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
8604 num0 = num_sign_bit_copies (x, GET_MODE (x));
8606 num0 - (int) (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth));
8609 if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x)))
8611 #ifndef WORD_REGISTER_OPERATIONS
8612 /* If this machine does not do all register operations on the entire
8613 register and MODE is wider than the mode of X, we can say nothing
8614 at all about the high-order bits. */
8617 /* Likewise on machines that do, if the mode of the object is smaller
8618 than a word and loads of that size don't sign extend, we can say
8619 nothing about the high order bits. */
8620 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
8621 #ifdef LOAD_EXTEND_OP
8622 && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND
8633 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8634 /* If pointers extend signed and this is a pointer in Pmode, say that
8635 all the bits above ptr_mode are known to be sign bit copies. */
8636 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
8638 return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1;
8641 if (reg_last_set_value[REGNO (x)] != 0
8642 && reg_last_set_mode[REGNO (x)] == mode
8643 && (reg_last_set_label[REGNO (x)] == label_tick
8644 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8645 && REG_N_SETS (REGNO (x)) == 1
8646 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start,
8648 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8649 return reg_last_set_sign_bit_copies[REGNO (x)];
8651 tem = get_last_value (x);
8653 return num_sign_bit_copies (tem, mode);
8655 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0
8656 && GET_MODE_BITSIZE (GET_MODE (x)) == bitwidth)
8657 return reg_sign_bit_copies[REGNO (x)];
8661 #ifdef LOAD_EXTEND_OP
8662 /* Some RISC machines sign-extend all loads of smaller than a word. */
8663 if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
8664 return MAX (1, ((int) bitwidth
8665 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1));
8670 /* If the constant is negative, take its 1's complement and remask.
8671 Then see how many zero bits we have. */
8672 nonzero = INTVAL (x) & GET_MODE_MASK (mode);
8673 if (bitwidth <= HOST_BITS_PER_WIDE_INT
8674 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8675 nonzero = (~nonzero) & GET_MODE_MASK (mode);
8677 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
8680 /* If this is a SUBREG for a promoted object that is sign-extended
8681 and we are looking at it in a wider mode, we know that at least the
8682 high-order bits are known to be sign bit copies. */
8684 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
8686 num0 = num_sign_bit_copies (SUBREG_REG (x), mode);
8687 return MAX ((int) bitwidth
8688 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1,
8692 /* For a smaller object, just ignore the high bits. */
8693 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
8695 num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode);
8696 return MAX (1, (num0
8697 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8701 #ifdef WORD_REGISTER_OPERATIONS
8702 #ifdef LOAD_EXTEND_OP
8703 /* For paradoxical SUBREGs on machines where all register operations
8704 affect the entire register, just look inside. Note that we are
8705 passing MODE to the recursive call, so the number of sign bit copies
8706 will remain relative to that mode, not the inner mode. */
8708 /* This works only if loads sign extend. Otherwise, if we get a
8709 reload for the inner part, it may be loaded from the stack, and
8710 then we lose all sign bit copies that existed before the store
8713 if ((GET_MODE_SIZE (GET_MODE (x))
8714 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8715 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
8716 && GET_CODE (SUBREG_REG (x)) == MEM)
8717 return num_sign_bit_copies (SUBREG_REG (x), mode);
8723 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
8724 return MAX (1, (int) bitwidth - INTVAL (XEXP (x, 1)));
8728 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8729 + num_sign_bit_copies (XEXP (x, 0), VOIDmode));
8732 /* For a smaller object, just ignore the high bits. */
8733 num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode);
8734 return MAX (1, (num0 - (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8738 return num_sign_bit_copies (XEXP (x, 0), mode);
8740 case ROTATE: case ROTATERT:
8741 /* If we are rotating left by a number of bits less than the number
8742 of sign bit copies, we can just subtract that amount from the
8744 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8745 && INTVAL (XEXP (x, 1)) >= 0
8746 && INTVAL (XEXP (x, 1)) < (int) bitwidth)
8748 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8749 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
8750 : (int) bitwidth - INTVAL (XEXP (x, 1))));
8755 /* In general, this subtracts one sign bit copy. But if the value
8756 is known to be positive, the number of sign bit copies is the
8757 same as that of the input. Finally, if the input has just one bit
8758 that might be nonzero, all the bits are copies of the sign bit. */
8759 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8760 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8761 return num0 > 1 ? num0 - 1 : 1;
8763 nonzero = nonzero_bits (XEXP (x, 0), mode);
8768 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
8773 case IOR: case AND: case XOR:
8774 case SMIN: case SMAX: case UMIN: case UMAX:
8775 /* Logical operations will preserve the number of sign-bit copies.
8776 MIN and MAX operations always return one of the operands. */
8777 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8778 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8779 return MIN (num0, num1);
8781 case PLUS: case MINUS:
8782 /* For addition and subtraction, we can have a 1-bit carry. However,
8783 if we are subtracting 1 from a positive number, there will not
8784 be such a carry. Furthermore, if the positive number is known to
8785 be 0 or 1, we know the result is either -1 or 0. */
8787 if (code == PLUS && XEXP (x, 1) == constm1_rtx
8788 && bitwidth <= HOST_BITS_PER_WIDE_INT)
8790 nonzero = nonzero_bits (XEXP (x, 0), mode);
8791 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
8792 return (nonzero == 1 || nonzero == 0 ? bitwidth
8793 : bitwidth - floor_log2 (nonzero) - 1);
8796 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8797 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8798 result = MAX (1, MIN (num0, num1) - 1);
8800 #ifdef POINTERS_EXTEND_UNSIGNED
8801 /* If pointers extend signed and this is an addition or subtraction
8802 to a pointer in Pmode, all the bits above ptr_mode are known to be
8804 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
8805 && (code == PLUS || code == MINUS)
8806 && GET_CODE (XEXP (x, 0)) == REG && REG_POINTER (XEXP (x, 0)))
8807 result = MAX ((int) (GET_MODE_BITSIZE (Pmode)
8808 - GET_MODE_BITSIZE (ptr_mode) + 1),
8814 /* The number of bits of the product is the sum of the number of
8815 bits of both terms. However, unless one of the terms if known
8816 to be positive, we must allow for an additional bit since negating
8817 a negative number can remove one sign bit copy. */
8819 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8820 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8822 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
8824 && (bitwidth > HOST_BITS_PER_WIDE_INT
8825 || (((nonzero_bits (XEXP (x, 0), mode)
8826 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8827 && ((nonzero_bits (XEXP (x, 1), mode)
8828 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))))
8831 return MAX (1, result);
8834 /* The result must be <= the first operand. If the first operand
8835 has the high bit set, we know nothing about the number of sign
8837 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8839 else if ((nonzero_bits (XEXP (x, 0), mode)
8840 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8843 return num_sign_bit_copies (XEXP (x, 0), mode);
8846 /* The result must be <= the second operand. */
8847 return num_sign_bit_copies (XEXP (x, 1), mode);
8850 /* Similar to unsigned division, except that we have to worry about
8851 the case where the divisor is negative, in which case we have
8853 result = num_sign_bit_copies (XEXP (x, 0), mode);
8855 && (bitwidth > HOST_BITS_PER_WIDE_INT
8856 || (nonzero_bits (XEXP (x, 1), mode)
8857 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8863 result = num_sign_bit_copies (XEXP (x, 1), mode);
8865 && (bitwidth > HOST_BITS_PER_WIDE_INT
8866 || (nonzero_bits (XEXP (x, 1), mode)
8867 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8873 /* Shifts by a constant add to the number of bits equal to the
8875 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8876 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8877 && INTVAL (XEXP (x, 1)) > 0)
8878 num0 = MIN ((int) bitwidth, num0 + INTVAL (XEXP (x, 1)));
8883 /* Left shifts destroy copies. */
8884 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8885 || INTVAL (XEXP (x, 1)) < 0
8886 || INTVAL (XEXP (x, 1)) >= (int) bitwidth)
8889 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8890 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
8893 num0 = num_sign_bit_copies (XEXP (x, 1), mode);
8894 num1 = num_sign_bit_copies (XEXP (x, 2), mode);
8895 return MIN (num0, num1);
8897 case EQ: case NE: case GE: case GT: case LE: case LT:
8898 case UNEQ: case LTGT: case UNGE: case UNGT: case UNLE: case UNLT:
8899 case GEU: case GTU: case LEU: case LTU:
8900 case UNORDERED: case ORDERED:
8901 /* If the constant is negative, take its 1's complement and remask.
8902 Then see how many zero bits we have. */
8903 nonzero = STORE_FLAG_VALUE;
8904 if (bitwidth <= HOST_BITS_PER_WIDE_INT
8905 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8906 nonzero = (~nonzero) & GET_MODE_MASK (mode);
8908 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
8915 /* If we haven't been able to figure it out by one of the above rules,
8916 see if some of the high-order bits are known to be zero. If so,
8917 count those bits and return one less than that amount. If we can't
8918 safely compute the mask for this mode, always return BITWIDTH. */
8920 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8923 nonzero = nonzero_bits (x, mode);
8924 return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
8925 ? 1 : bitwidth - floor_log2 (nonzero) - 1);
8928 /* Return the number of "extended" bits there are in X, when interpreted
8929 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8930 unsigned quantities, this is the number of high-order zero bits.
8931 For signed quantities, this is the number of copies of the sign bit
8932 minus 1. In both case, this function returns the number of "spare"
8933 bits. For example, if two quantities for which this function returns
8934 at least 1 are added, the addition is known not to overflow.
8936 This function will always return 0 unless called during combine, which
8937 implies that it must be called from a define_split. */
8940 extended_count (x, mode, unsignedp)
8942 enum machine_mode mode;
8945 if (nonzero_sign_valid == 0)
8949 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8950 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
8951 - floor_log2 (nonzero_bits (x, mode)))
8953 : num_sign_bit_copies (x, mode) - 1);
8956 /* This function is called from `simplify_shift_const' to merge two
8957 outer operations. Specifically, we have already found that we need
8958 to perform operation *POP0 with constant *PCONST0 at the outermost
8959 position. We would now like to also perform OP1 with constant CONST1
8960 (with *POP0 being done last).
8962 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8963 the resulting operation. *PCOMP_P is set to 1 if we would need to
8964 complement the innermost operand, otherwise it is unchanged.
8966 MODE is the mode in which the operation will be done. No bits outside
8967 the width of this mode matter. It is assumed that the width of this mode
8968 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8970 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8971 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8972 result is simply *PCONST0.
8974 If the resulting operation cannot be expressed as one operation, we
8975 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8978 merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
8979 enum rtx_code *pop0;
8980 HOST_WIDE_INT *pconst0;
8982 HOST_WIDE_INT const1;
8983 enum machine_mode mode;
8986 enum rtx_code op0 = *pop0;
8987 HOST_WIDE_INT const0 = *pconst0;
8989 const0 &= GET_MODE_MASK (mode);
8990 const1 &= GET_MODE_MASK (mode);
8992 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8996 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
8999 if (op1 == NIL || op0 == SET)
9002 else if (op0 == NIL)
9003 op0 = op1, const0 = const1;
9005 else if (op0 == op1)
9029 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9030 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
9033 /* If the two constants aren't the same, we can't do anything. The
9034 remaining six cases can all be done. */
9035 else if (const0 != const1)
9043 /* (a & b) | b == b */
9045 else /* op1 == XOR */
9046 /* (a ^ b) | b == a | b */
9052 /* (a & b) ^ b == (~a) & b */
9053 op0 = AND, *pcomp_p = 1;
9054 else /* op1 == IOR */
9055 /* (a | b) ^ b == a & ~b */
9056 op0 = AND, *pconst0 = ~const0;
9061 /* (a | b) & b == b */
9063 else /* op1 == XOR */
9064 /* (a ^ b) & b) == (~a) & b */
9071 /* Check for NO-OP cases. */
9072 const0 &= GET_MODE_MASK (mode);
9074 && (op0 == IOR || op0 == XOR || op0 == PLUS))
9076 else if (const0 == 0 && op0 == AND)
9078 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
9082 /* ??? Slightly redundant with the above mask, but not entirely.
9083 Moving this above means we'd have to sign-extend the mode mask
9084 for the final test. */
9085 const0 = trunc_int_for_mode (const0, mode);
9093 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9094 The result of the shift is RESULT_MODE. X, if nonzero, is an expression
9095 that we started with.
9097 The shift is normally computed in the widest mode we find in VAROP, as
9098 long as it isn't a different number of words than RESULT_MODE. Exceptions
9099 are ASHIFTRT and ROTATE, which are always done in their original mode, */
9102 simplify_shift_const (x, code, result_mode, varop, orig_count)
9105 enum machine_mode result_mode;
9109 enum rtx_code orig_code = code;
9112 enum machine_mode mode = result_mode;
9113 enum machine_mode shift_mode, tmode;
9114 unsigned int mode_words
9115 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
9116 /* We form (outer_op (code varop count) (outer_const)). */
9117 enum rtx_code outer_op = NIL;
9118 HOST_WIDE_INT outer_const = 0;
9120 int complement_p = 0;
9123 /* Make sure and truncate the "natural" shift on the way in. We don't
9124 want to do this inside the loop as it makes it more difficult to
9126 #ifdef SHIFT_COUNT_TRUNCATED
9127 if (SHIFT_COUNT_TRUNCATED)
9128 orig_count &= GET_MODE_BITSIZE (mode) - 1;
9131 /* If we were given an invalid count, don't do anything except exactly
9132 what was requested. */
9134 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
9139 return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (orig_count));
9144 /* Unless one of the branches of the `if' in this loop does a `continue',
9145 we will `break' the loop after the `if'. */
9149 /* If we have an operand of (clobber (const_int 0)), just return that
9151 if (GET_CODE (varop) == CLOBBER)
9154 /* If we discovered we had to complement VAROP, leave. Making a NOT
9155 here would cause an infinite loop. */
9159 /* Convert ROTATERT to ROTATE. */
9160 if (code == ROTATERT)
9162 unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
9164 if (VECTOR_MODE_P (result_mode))
9165 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
9167 count = bitsize - count;
9170 /* We need to determine what mode we will do the shift in. If the
9171 shift is a right shift or a ROTATE, we must always do it in the mode
9172 it was originally done in. Otherwise, we can do it in MODE, the
9173 widest mode encountered. */
9175 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9176 ? result_mode : mode);
9178 /* Handle cases where the count is greater than the size of the mode
9179 minus 1. For ASHIFT, use the size minus one as the count (this can
9180 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9181 take the count modulo the size. For other shifts, the result is
9184 Since these shifts are being produced by the compiler by combining
9185 multiple operations, each of which are defined, we know what the
9186 result is supposed to be. */
9188 if (count > (unsigned int) (GET_MODE_BITSIZE (shift_mode) - 1))
9190 if (code == ASHIFTRT)
9191 count = GET_MODE_BITSIZE (shift_mode) - 1;
9192 else if (code == ROTATE || code == ROTATERT)
9193 count %= GET_MODE_BITSIZE (shift_mode);
9196 /* We can't simply return zero because there may be an
9204 /* An arithmetic right shift of a quantity known to be -1 or 0
9206 if (code == ASHIFTRT
9207 && (num_sign_bit_copies (varop, shift_mode)
9208 == GET_MODE_BITSIZE (shift_mode)))
9214 /* If we are doing an arithmetic right shift and discarding all but
9215 the sign bit copies, this is equivalent to doing a shift by the
9216 bitsize minus one. Convert it into that shift because it will often
9217 allow other simplifications. */
9219 if (code == ASHIFTRT
9220 && (count + num_sign_bit_copies (varop, shift_mode)
9221 >= GET_MODE_BITSIZE (shift_mode)))
9222 count = GET_MODE_BITSIZE (shift_mode) - 1;
9224 /* We simplify the tests below and elsewhere by converting
9225 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9226 `make_compound_operation' will convert it to an ASHIFTRT for
9227 those machines (such as VAX) that don't have an LSHIFTRT. */
9228 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9230 && ((nonzero_bits (varop, shift_mode)
9231 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
9235 switch (GET_CODE (varop))
9241 new = expand_compound_operation (varop);
9250 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9251 minus the width of a smaller mode, we can do this with a
9252 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9253 if ((code == ASHIFTRT || code == LSHIFTRT)
9254 && ! mode_dependent_address_p (XEXP (varop, 0))
9255 && ! MEM_VOLATILE_P (varop)
9256 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9257 MODE_INT, 1)) != BLKmode)
9259 new = adjust_address_nv (varop, tmode,
9260 BYTES_BIG_ENDIAN ? 0
9261 : count / BITS_PER_UNIT);
9263 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9264 : ZERO_EXTEND, mode, new);
9271 /* Similar to the case above, except that we can only do this if
9272 the resulting mode is the same as that of the underlying
9273 MEM and adjust the address depending on the *bits* endianness
9274 because of the way that bit-field extract insns are defined. */
9275 if ((code == ASHIFTRT || code == LSHIFTRT)
9276 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9277 MODE_INT, 1)) != BLKmode
9278 && tmode == GET_MODE (XEXP (varop, 0)))
9280 if (BITS_BIG_ENDIAN)
9281 new = XEXP (varop, 0);
9284 new = copy_rtx (XEXP (varop, 0));
9285 SUBST (XEXP (new, 0),
9286 plus_constant (XEXP (new, 0),
9287 count / BITS_PER_UNIT));
9290 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9291 : ZERO_EXTEND, mode, new);
9298 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9299 the same number of words as what we've seen so far. Then store
9300 the widest mode in MODE. */
9301 if (subreg_lowpart_p (varop)
9302 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9303 > GET_MODE_SIZE (GET_MODE (varop)))
9304 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9305 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9308 varop = SUBREG_REG (varop);
9309 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9310 mode = GET_MODE (varop);
9316 /* Some machines use MULT instead of ASHIFT because MULT
9317 is cheaper. But it is still better on those machines to
9318 merge two shifts into one. */
9319 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9320 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9323 = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
9324 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9330 /* Similar, for when divides are cheaper. */
9331 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9332 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9335 = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
9336 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9342 /* If we are extracting just the sign bit of an arithmetic
9343 right shift, that shift is not needed. However, the sign
9344 bit of a wider mode may be different from what would be
9345 interpreted as the sign bit in a narrower mode, so, if
9346 the result is narrower, don't discard the shift. */
9347 if (code == LSHIFTRT
9348 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9349 && (GET_MODE_BITSIZE (result_mode)
9350 >= GET_MODE_BITSIZE (GET_MODE (varop))))
9352 varop = XEXP (varop, 0);
9356 /* ... fall through ... */
9361 /* Here we have two nested shifts. The result is usually the
9362 AND of a new shift with a mask. We compute the result below. */
9363 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9364 && INTVAL (XEXP (varop, 1)) >= 0
9365 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
9366 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9367 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9369 enum rtx_code first_code = GET_CODE (varop);
9370 unsigned int first_count = INTVAL (XEXP (varop, 1));
9371 unsigned HOST_WIDE_INT mask;
9374 /* We have one common special case. We can't do any merging if
9375 the inner code is an ASHIFTRT of a smaller mode. However, if
9376 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9377 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9378 we can convert it to
9379 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9380 This simplifies certain SIGN_EXTEND operations. */
9381 if (code == ASHIFT && first_code == ASHIFTRT
9382 && count == (unsigned int)
9383 (GET_MODE_BITSIZE (result_mode)
9384 - GET_MODE_BITSIZE (GET_MODE (varop))))
9386 /* C3 has the low-order C1 bits zero. */
9388 mask = (GET_MODE_MASK (mode)
9389 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
9391 varop = simplify_and_const_int (NULL_RTX, result_mode,
9392 XEXP (varop, 0), mask);
9393 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
9395 count = first_count;
9400 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9401 than C1 high-order bits equal to the sign bit, we can convert
9402 this to either an ASHIFT or an ASHIFTRT depending on the
9405 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9407 if (code == ASHIFTRT && first_code == ASHIFT
9408 && GET_MODE (varop) == shift_mode
9409 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
9412 varop = XEXP (varop, 0);
9414 signed_count = count - first_count;
9415 if (signed_count < 0)
9416 count = -signed_count, code = ASHIFT;
9418 count = signed_count;
9423 /* There are some cases we can't do. If CODE is ASHIFTRT,
9424 we can only do this if FIRST_CODE is also ASHIFTRT.
9426 We can't do the case when CODE is ROTATE and FIRST_CODE is
9429 If the mode of this shift is not the mode of the outer shift,
9430 we can't do this if either shift is a right shift or ROTATE.
9432 Finally, we can't do any of these if the mode is too wide
9433 unless the codes are the same.
9435 Handle the case where the shift codes are the same
9438 if (code == first_code)
9440 if (GET_MODE (varop) != result_mode
9441 && (code == ASHIFTRT || code == LSHIFTRT
9445 count += first_count;
9446 varop = XEXP (varop, 0);
9450 if (code == ASHIFTRT
9451 || (code == ROTATE && first_code == ASHIFTRT)
9452 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
9453 || (GET_MODE (varop) != result_mode
9454 && (first_code == ASHIFTRT || first_code == LSHIFTRT
9455 || first_code == ROTATE
9456 || code == ROTATE)))
9459 /* To compute the mask to apply after the shift, shift the
9460 nonzero bits of the inner shift the same way the
9461 outer shift will. */
9463 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
9466 = simplify_binary_operation (code, result_mode, mask_rtx,
9469 /* Give up if we can't compute an outer operation to use. */
9471 || GET_CODE (mask_rtx) != CONST_INT
9472 || ! merge_outer_ops (&outer_op, &outer_const, AND,
9474 result_mode, &complement_p))
9477 /* If the shifts are in the same direction, we add the
9478 counts. Otherwise, we subtract them. */
9479 signed_count = count;
9480 if ((code == ASHIFTRT || code == LSHIFTRT)
9481 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
9482 signed_count += first_count;
9484 signed_count -= first_count;
9486 /* If COUNT is positive, the new shift is usually CODE,
9487 except for the two exceptions below, in which case it is
9488 FIRST_CODE. If the count is negative, FIRST_CODE should
9490 if (signed_count > 0
9491 && ((first_code == ROTATE && code == ASHIFT)
9492 || (first_code == ASHIFTRT && code == LSHIFTRT)))
9493 code = first_code, count = signed_count;
9494 else if (signed_count < 0)
9495 code = first_code, count = -signed_count;
9497 count = signed_count;
9499 varop = XEXP (varop, 0);
9503 /* If we have (A << B << C) for any shift, we can convert this to
9504 (A << C << B). This wins if A is a constant. Only try this if
9505 B is not a constant. */
9507 else if (GET_CODE (varop) == code
9508 && GET_CODE (XEXP (varop, 1)) != CONST_INT
9510 = simplify_binary_operation (code, mode,
9514 varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1));
9521 /* Make this fit the case below. */
9522 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
9523 GEN_INT (GET_MODE_MASK (mode)));
9529 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9530 with C the size of VAROP - 1 and the shift is logical if
9531 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9532 we have an (le X 0) operation. If we have an arithmetic shift
9533 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9534 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9536 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9537 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9538 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9539 && (code == LSHIFTRT || code == ASHIFTRT)
9540 && count == (unsigned int)
9541 (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9542 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9545 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
9548 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9549 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9554 /* If we have (shift (logical)), move the logical to the outside
9555 to allow it to possibly combine with another logical and the
9556 shift to combine with another shift. This also canonicalizes to
9557 what a ZERO_EXTRACT looks like. Also, some machines have
9558 (and (shift)) insns. */
9560 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9561 && (new = simplify_binary_operation (code, result_mode,
9563 GEN_INT (count))) != 0
9564 && GET_CODE (new) == CONST_INT
9565 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9566 INTVAL (new), result_mode, &complement_p))
9568 varop = XEXP (varop, 0);
9572 /* If we can't do that, try to simplify the shift in each arm of the
9573 logical expression, make a new logical expression, and apply
9574 the inverse distributive law. */
9576 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9577 XEXP (varop, 0), count);
9578 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9579 XEXP (varop, 1), count);
9581 varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
9582 varop = apply_distributive_law (varop);
9589 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9590 says that the sign bit can be tested, FOO has mode MODE, C is
9591 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9592 that may be nonzero. */
9593 if (code == LSHIFTRT
9594 && XEXP (varop, 1) == const0_rtx
9595 && GET_MODE (XEXP (varop, 0)) == result_mode
9596 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9597 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9598 && ((STORE_FLAG_VALUE
9599 & ((HOST_WIDE_INT) 1
9600 < (GET_MODE_BITSIZE (result_mode) - 1))))
9601 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9602 && merge_outer_ops (&outer_op, &outer_const, XOR,
9603 (HOST_WIDE_INT) 1, result_mode,
9606 varop = XEXP (varop, 0);
9613 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9614 than the number of bits in the mode is equivalent to A. */
9615 if (code == LSHIFTRT
9616 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9617 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9619 varop = XEXP (varop, 0);
9624 /* NEG commutes with ASHIFT since it is multiplication. Move the
9625 NEG outside to allow shifts to combine. */
9627 && merge_outer_ops (&outer_op, &outer_const, NEG,
9628 (HOST_WIDE_INT) 0, result_mode,
9631 varop = XEXP (varop, 0);
9637 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9638 is one less than the number of bits in the mode is
9639 equivalent to (xor A 1). */
9640 if (code == LSHIFTRT
9641 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9642 && XEXP (varop, 1) == constm1_rtx
9643 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9644 && merge_outer_ops (&outer_op, &outer_const, XOR,
9645 (HOST_WIDE_INT) 1, result_mode,
9649 varop = XEXP (varop, 0);
9653 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9654 that might be nonzero in BAR are those being shifted out and those
9655 bits are known zero in FOO, we can replace the PLUS with FOO.
9656 Similarly in the other operand order. This code occurs when
9657 we are computing the size of a variable-size array. */
9659 if ((code == ASHIFTRT || code == LSHIFTRT)
9660 && count < HOST_BITS_PER_WIDE_INT
9661 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9662 && (nonzero_bits (XEXP (varop, 1), result_mode)
9663 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9665 varop = XEXP (varop, 0);
9668 else if ((code == ASHIFTRT || code == LSHIFTRT)
9669 && count < HOST_BITS_PER_WIDE_INT
9670 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9671 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9673 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9674 & nonzero_bits (XEXP (varop, 1),
9677 varop = XEXP (varop, 1);
9681 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9683 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9684 && (new = simplify_binary_operation (ASHIFT, result_mode,
9686 GEN_INT (count))) != 0
9687 && GET_CODE (new) == CONST_INT
9688 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9689 INTVAL (new), result_mode, &complement_p))
9691 varop = XEXP (varop, 0);
9697 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9698 with C the size of VAROP - 1 and the shift is logical if
9699 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9700 we have a (gt X 0) operation. If the shift is arithmetic with
9701 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9702 we have a (neg (gt X 0)) operation. */
9704 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9705 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9706 && count == (unsigned int)
9707 (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9708 && (code == LSHIFTRT || code == ASHIFTRT)
9709 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9710 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (varop, 0), 1))
9712 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9715 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9718 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9719 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9726 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9727 if the truncate does not affect the value. */
9728 if (code == LSHIFTRT
9729 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9730 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9731 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9732 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9733 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9735 rtx varop_inner = XEXP (varop, 0);
9738 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9739 XEXP (varop_inner, 0),
9741 (count + INTVAL (XEXP (varop_inner, 1))));
9742 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9755 /* We need to determine what mode to do the shift in. If the shift is
9756 a right shift or ROTATE, we must always do it in the mode it was
9757 originally done in. Otherwise, we can do it in MODE, the widest mode
9758 encountered. The code we care about is that of the shift that will
9759 actually be done, not the shift that was originally requested. */
9761 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9762 ? result_mode : mode);
9764 /* We have now finished analyzing the shift. The result should be
9765 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9766 OUTER_OP is non-NIL, it is an operation that needs to be applied
9767 to the result of the shift. OUTER_CONST is the relevant constant,
9768 but we must turn off all bits turned off in the shift.
9770 If we were passed a value for X, see if we can use any pieces of
9771 it. If not, make new rtx. */
9773 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
9774 && GET_CODE (XEXP (x, 1)) == CONST_INT
9775 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) == count)
9776 const_rtx = XEXP (x, 1);
9778 const_rtx = GEN_INT (count);
9780 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
9781 && GET_MODE (XEXP (x, 0)) == shift_mode
9782 && SUBREG_REG (XEXP (x, 0)) == varop)
9783 varop = XEXP (x, 0);
9784 else if (GET_MODE (varop) != shift_mode)
9785 varop = gen_lowpart_for_combine (shift_mode, varop);
9787 /* If we can't make the SUBREG, try to return what we were given. */
9788 if (GET_CODE (varop) == CLOBBER)
9789 return x ? x : varop;
9791 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
9795 x = gen_rtx_fmt_ee (code, shift_mode, varop, const_rtx);
9797 /* If we have an outer operation and we just made a shift, it is
9798 possible that we could have simplified the shift were it not
9799 for the outer operation. So try to do the simplification
9802 if (outer_op != NIL && GET_CODE (x) == code
9803 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9804 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
9805 INTVAL (XEXP (x, 1)));
9807 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9808 turn off all the bits that the shift would have turned off. */
9809 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9810 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9811 GET_MODE_MASK (result_mode) >> orig_count);
9813 /* Do the remainder of the processing in RESULT_MODE. */
9814 x = gen_lowpart_for_combine (result_mode, x);
9816 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9819 x =simplify_gen_unary (NOT, result_mode, x, result_mode);
9821 if (outer_op != NIL)
9823 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9824 outer_const = trunc_int_for_mode (outer_const, result_mode);
9826 if (outer_op == AND)
9827 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9828 else if (outer_op == SET)
9829 /* This means that we have determined that the result is
9830 equivalent to a constant. This should be rare. */
9831 x = GEN_INT (outer_const);
9832 else if (GET_RTX_CLASS (outer_op) == '1')
9833 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
9835 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
9841 /* Like recog, but we receive the address of a pointer to a new pattern.
9842 We try to match the rtx that the pointer points to.
9843 If that fails, we may try to modify or replace the pattern,
9844 storing the replacement into the same pointer object.
9846 Modifications include deletion or addition of CLOBBERs.
9848 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9849 the CLOBBERs are placed.
9851 The value is the final insn code from the pattern ultimately matched,
9855 recog_for_combine (pnewpat, insn, pnotes)
9861 int insn_code_number;
9862 int num_clobbers_to_add = 0;
9867 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9868 we use to indicate that something didn't match. If we find such a
9869 thing, force rejection. */
9870 if (GET_CODE (pat) == PARALLEL)
9871 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9872 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9873 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9876 /* *pnewpat does not have to be actual PATTERN (insn), so make a dummy
9877 instruction for pattern recognition. */
9878 dummy_insn = shallow_copy_rtx (insn);
9879 PATTERN (dummy_insn) = pat;
9880 REG_NOTES (dummy_insn) = 0;
9882 insn_code_number = recog (pat, dummy_insn, &num_clobbers_to_add);
9884 /* If it isn't, there is the possibility that we previously had an insn
9885 that clobbered some register as a side effect, but the combined
9886 insn doesn't need to do that. So try once more without the clobbers
9887 unless this represents an ASM insn. */
9889 if (insn_code_number < 0 && ! check_asm_operands (pat)
9890 && GET_CODE (pat) == PARALLEL)
9894 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9895 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9898 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9902 SUBST_INT (XVECLEN (pat, 0), pos);
9905 pat = XVECEXP (pat, 0, 0);
9907 PATTERN (dummy_insn) = pat;
9908 insn_code_number = recog (pat, dummy_insn, &num_clobbers_to_add);
9911 /* Recognize all noop sets, these will be killed by followup pass. */
9912 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
9913 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
9915 /* If we had any clobbers to add, make a new pattern than contains
9916 them. Then check to make sure that all of them are dead. */
9917 if (num_clobbers_to_add)
9919 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9920 rtvec_alloc (GET_CODE (pat) == PARALLEL
9922 + num_clobbers_to_add)
9923 : num_clobbers_to_add + 1));
9925 if (GET_CODE (pat) == PARALLEL)
9926 for (i = 0; i < XVECLEN (pat, 0); i++)
9927 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9929 XVECEXP (newpat, 0, 0) = pat;
9931 add_clobbers (newpat, insn_code_number);
9933 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9934 i < XVECLEN (newpat, 0); i++)
9936 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
9937 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9939 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9940 XEXP (XVECEXP (newpat, 0, i), 0), notes);
9948 return insn_code_number;
9951 /* Like gen_lowpart but for use by combine. In combine it is not possible
9952 to create any new pseudoregs. However, it is safe to create
9953 invalid memory addresses, because combine will try to recognize
9954 them and all they will do is make the combine attempt fail.
9956 If for some reason this cannot do its job, an rtx
9957 (clobber (const_int 0)) is returned.
9958 An insn containing that will not be recognized. */
9963 gen_lowpart_for_combine (mode, x)
9964 enum machine_mode mode;
9969 if (GET_MODE (x) == mode)
9972 /* We can only support MODE being wider than a word if X is a
9973 constant integer or has a mode the same size. */
9975 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
9976 && ! ((GET_MODE (x) == VOIDmode
9977 && (GET_CODE (x) == CONST_INT
9978 || GET_CODE (x) == CONST_DOUBLE))
9979 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
9980 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9982 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9983 won't know what to do. So we will strip off the SUBREG here and
9984 process normally. */
9985 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
9988 if (GET_MODE (x) == mode)
9992 result = gen_lowpart_common (mode, x);
9993 #ifdef CANNOT_CHANGE_MODE_CLASS
9995 && GET_CODE (result) == SUBREG
9996 && GET_CODE (SUBREG_REG (result)) == REG
9997 && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER)
9998 SET_REGNO_REG_SET (&subregs_of_mode[GET_MODE (result)],
9999 REGNO (SUBREG_REG (result)));
10005 if (GET_CODE (x) == MEM)
10009 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10011 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
10012 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
10014 /* If we want to refer to something bigger than the original memref,
10015 generate a perverse subreg instead. That will force a reload
10016 of the original memref X. */
10017 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
10018 return gen_rtx_SUBREG (mode, x, 0);
10020 if (WORDS_BIG_ENDIAN)
10021 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
10022 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
10024 if (BYTES_BIG_ENDIAN)
10026 /* Adjust the address so that the address-after-the-data is
10028 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
10029 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
10032 return adjust_address_nv (x, mode, offset);
10035 /* If X is a comparison operator, rewrite it in a new mode. This
10036 probably won't match, but may allow further simplifications. */
10037 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
10038 return gen_rtx_fmt_ee (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
10040 /* If we couldn't simplify X any other way, just enclose it in a
10041 SUBREG. Normally, this SUBREG won't match, but some patterns may
10042 include an explicit SUBREG or we may simplify it further in combine. */
10047 enum machine_mode sub_mode = GET_MODE (x);
10049 offset = subreg_lowpart_offset (mode, sub_mode);
10050 if (sub_mode == VOIDmode)
10052 sub_mode = int_mode_for_mode (mode);
10053 x = gen_lowpart_common (sub_mode, x);
10055 res = simplify_gen_subreg (mode, x, sub_mode, offset);
10058 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
10062 /* These routines make binary and unary operations by first seeing if they
10063 fold; if not, a new expression is allocated. */
10066 gen_binary (code, mode, op0, op1)
10067 enum rtx_code code;
10068 enum machine_mode mode;
10074 if (GET_RTX_CLASS (code) == 'c'
10075 && swap_commutative_operands_p (op0, op1))
10076 tem = op0, op0 = op1, op1 = tem;
10078 if (GET_RTX_CLASS (code) == '<')
10080 enum machine_mode op_mode = GET_MODE (op0);
10082 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
10083 just (REL_OP X Y). */
10084 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
10086 op1 = XEXP (op0, 1);
10087 op0 = XEXP (op0, 0);
10088 op_mode = GET_MODE (op0);
10091 if (op_mode == VOIDmode)
10092 op_mode = GET_MODE (op1);
10093 result = simplify_relational_operation (code, op_mode, op0, op1);
10096 result = simplify_binary_operation (code, mode, op0, op1);
10101 /* Put complex operands first and constants second. */
10102 if (GET_RTX_CLASS (code) == 'c'
10103 && swap_commutative_operands_p (op0, op1))
10104 return gen_rtx_fmt_ee (code, mode, op1, op0);
10106 /* If we are turning off bits already known off in OP0, we need not do
10108 else if (code == AND && GET_CODE (op1) == CONST_INT
10109 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
10110 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
10113 return gen_rtx_fmt_ee (code, mode, op0, op1);
10116 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10117 comparison code that will be tested.
10119 The result is a possibly different comparison code to use. *POP0 and
10120 *POP1 may be updated.
10122 It is possible that we might detect that a comparison is either always
10123 true or always false. However, we do not perform general constant
10124 folding in combine, so this knowledge isn't useful. Such tautologies
10125 should have been detected earlier. Hence we ignore all such cases. */
10127 static enum rtx_code
10128 simplify_comparison (code, pop0, pop1)
10129 enum rtx_code code;
10137 enum machine_mode mode, tmode;
10139 /* Try a few ways of applying the same transformation to both operands. */
10142 #ifndef WORD_REGISTER_OPERATIONS
10143 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10144 so check specially. */
10145 if (code != GTU && code != GEU && code != LTU && code != LEU
10146 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
10147 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10148 && GET_CODE (XEXP (op1, 0)) == ASHIFT
10149 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
10150 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
10151 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
10152 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
10153 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10154 && GET_CODE (XEXP (op1, 1)) == CONST_INT
10155 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10156 && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT
10157 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (op1, 1))
10158 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op0, 0), 1))
10159 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op1, 0), 1))
10160 && (INTVAL (XEXP (op0, 1))
10161 == (GET_MODE_BITSIZE (GET_MODE (op0))
10162 - (GET_MODE_BITSIZE
10163 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
10165 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
10166 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
10170 /* If both operands are the same constant shift, see if we can ignore the
10171 shift. We can if the shift is a rotate or if the bits shifted out of
10172 this shift are known to be zero for both inputs and if the type of
10173 comparison is compatible with the shift. */
10174 if (GET_CODE (op0) == GET_CODE (op1)
10175 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10176 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
10177 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
10178 && (code != GT && code != LT && code != GE && code != LE))
10179 || (GET_CODE (op0) == ASHIFTRT
10180 && (code != GTU && code != LTU
10181 && code != GEU && code != LEU)))
10182 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10183 && INTVAL (XEXP (op0, 1)) >= 0
10184 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10185 && XEXP (op0, 1) == XEXP (op1, 1))
10187 enum machine_mode mode = GET_MODE (op0);
10188 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10189 int shift_count = INTVAL (XEXP (op0, 1));
10191 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
10192 mask &= (mask >> shift_count) << shift_count;
10193 else if (GET_CODE (op0) == ASHIFT)
10194 mask = (mask & (mask << shift_count)) >> shift_count;
10196 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
10197 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
10198 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
10203 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10204 SUBREGs are of the same mode, and, in both cases, the AND would
10205 be redundant if the comparison was done in the narrower mode,
10206 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10207 and the operand's possibly nonzero bits are 0xffffff01; in that case
10208 if we only care about QImode, we don't need the AND). This case
10209 occurs if the output mode of an scc insn is not SImode and
10210 STORE_FLAG_VALUE == 1 (e.g., the 386).
10212 Similarly, check for a case where the AND's are ZERO_EXTEND
10213 operations from some narrower mode even though a SUBREG is not
10216 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
10217 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10218 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
10220 rtx inner_op0 = XEXP (op0, 0);
10221 rtx inner_op1 = XEXP (op1, 0);
10222 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
10223 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
10226 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
10227 && (GET_MODE_SIZE (GET_MODE (inner_op0))
10228 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
10229 && (GET_MODE (SUBREG_REG (inner_op0))
10230 == GET_MODE (SUBREG_REG (inner_op1)))
10231 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
10232 <= HOST_BITS_PER_WIDE_INT)
10233 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
10234 GET_MODE (SUBREG_REG (inner_op0)))))
10235 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
10236 GET_MODE (SUBREG_REG (inner_op1))))))
10238 op0 = SUBREG_REG (inner_op0);
10239 op1 = SUBREG_REG (inner_op1);
10241 /* The resulting comparison is always unsigned since we masked
10242 off the original sign bit. */
10243 code = unsigned_condition (code);
10249 for (tmode = GET_CLASS_NARROWEST_MODE
10250 (GET_MODE_CLASS (GET_MODE (op0)));
10251 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
10252 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
10254 op0 = gen_lowpart_for_combine (tmode, inner_op0);
10255 op1 = gen_lowpart_for_combine (tmode, inner_op1);
10256 code = unsigned_condition (code);
10265 /* If both operands are NOT, we can strip off the outer operation
10266 and adjust the comparison code for swapped operands; similarly for
10267 NEG, except that this must be an equality comparison. */
10268 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
10269 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
10270 && (code == EQ || code == NE)))
10271 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
10277 /* If the first operand is a constant, swap the operands and adjust the
10278 comparison code appropriately, but don't do this if the second operand
10279 is already a constant integer. */
10280 if (swap_commutative_operands_p (op0, op1))
10282 tem = op0, op0 = op1, op1 = tem;
10283 code = swap_condition (code);
10286 /* We now enter a loop during which we will try to simplify the comparison.
10287 For the most part, we only are concerned with comparisons with zero,
10288 but some things may really be comparisons with zero but not start
10289 out looking that way. */
10291 while (GET_CODE (op1) == CONST_INT)
10293 enum machine_mode mode = GET_MODE (op0);
10294 unsigned int mode_width = GET_MODE_BITSIZE (mode);
10295 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10296 int equality_comparison_p;
10297 int sign_bit_comparison_p;
10298 int unsigned_comparison_p;
10299 HOST_WIDE_INT const_op;
10301 /* We only want to handle integral modes. This catches VOIDmode,
10302 CCmode, and the floating-point modes. An exception is that we
10303 can handle VOIDmode if OP0 is a COMPARE or a comparison
10306 if (GET_MODE_CLASS (mode) != MODE_INT
10307 && ! (mode == VOIDmode
10308 && (GET_CODE (op0) == COMPARE
10309 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
10312 /* Get the constant we are comparing against and turn off all bits
10313 not on in our mode. */
10314 const_op = INTVAL (op1);
10315 if (mode != VOIDmode)
10316 const_op = trunc_int_for_mode (const_op, mode);
10317 op1 = GEN_INT (const_op);
10319 /* If we are comparing against a constant power of two and the value
10320 being compared can only have that single bit nonzero (e.g., it was
10321 `and'ed with that bit), we can replace this with a comparison
10324 && (code == EQ || code == NE || code == GE || code == GEU
10325 || code == LT || code == LTU)
10326 && mode_width <= HOST_BITS_PER_WIDE_INT
10327 && exact_log2 (const_op) >= 0
10328 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10330 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10331 op1 = const0_rtx, const_op = 0;
10334 /* Similarly, if we are comparing a value known to be either -1 or
10335 0 with -1, change it to the opposite comparison against zero. */
10338 && (code == EQ || code == NE || code == GT || code == LE
10339 || code == GEU || code == LTU)
10340 && num_sign_bit_copies (op0, mode) == mode_width)
10342 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10343 op1 = const0_rtx, const_op = 0;
10346 /* Do some canonicalizations based on the comparison code. We prefer
10347 comparisons against zero and then prefer equality comparisons.
10348 If we can reduce the size of a constant, we will do that too. */
10353 /* < C is equivalent to <= (C - 1) */
10357 op1 = GEN_INT (const_op);
10359 /* ... fall through to LE case below. */
10365 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10369 op1 = GEN_INT (const_op);
10373 /* If we are doing a <= 0 comparison on a value known to have
10374 a zero sign bit, we can replace this with == 0. */
10375 else if (const_op == 0
10376 && mode_width <= HOST_BITS_PER_WIDE_INT
10377 && (nonzero_bits (op0, mode)
10378 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10383 /* >= C is equivalent to > (C - 1). */
10387 op1 = GEN_INT (const_op);
10389 /* ... fall through to GT below. */
10395 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10399 op1 = GEN_INT (const_op);
10403 /* If we are doing a > 0 comparison on a value known to have
10404 a zero sign bit, we can replace this with != 0. */
10405 else if (const_op == 0
10406 && mode_width <= HOST_BITS_PER_WIDE_INT
10407 && (nonzero_bits (op0, mode)
10408 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10413 /* < C is equivalent to <= (C - 1). */
10417 op1 = GEN_INT (const_op);
10419 /* ... fall through ... */
10422 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10423 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10424 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10426 const_op = 0, op1 = const0_rtx;
10434 /* unsigned <= 0 is equivalent to == 0 */
10438 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10439 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10440 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10442 const_op = 0, op1 = const0_rtx;
10448 /* >= C is equivalent to < (C - 1). */
10452 op1 = GEN_INT (const_op);
10454 /* ... fall through ... */
10457 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10458 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10459 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10461 const_op = 0, op1 = const0_rtx;
10469 /* unsigned > 0 is equivalent to != 0 */
10473 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10474 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10475 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10477 const_op = 0, op1 = const0_rtx;
10486 /* Compute some predicates to simplify code below. */
10488 equality_comparison_p = (code == EQ || code == NE);
10489 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
10490 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
10493 /* If this is a sign bit comparison and we can do arithmetic in
10494 MODE, say that we will only be needing the sign bit of OP0. */
10495 if (sign_bit_comparison_p
10496 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10497 op0 = force_to_mode (op0, mode,
10499 << (GET_MODE_BITSIZE (mode) - 1)),
10502 /* Now try cases based on the opcode of OP0. If none of the cases
10503 does a "continue", we exit this loop immediately after the
10506 switch (GET_CODE (op0))
10509 /* If we are extracting a single bit from a variable position in
10510 a constant that has only a single bit set and are comparing it
10511 with zero, we can convert this into an equality comparison
10512 between the position and the location of the single bit. */
10514 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
10515 && XEXP (op0, 1) == const1_rtx
10516 && equality_comparison_p && const_op == 0
10517 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
10519 if (BITS_BIG_ENDIAN)
10521 enum machine_mode new_mode
10522 = mode_for_extraction (EP_extzv, 1);
10523 if (new_mode == MAX_MACHINE_MODE)
10524 i = BITS_PER_WORD - 1 - i;
10528 i = (GET_MODE_BITSIZE (mode) - 1 - i);
10532 op0 = XEXP (op0, 2);
10536 /* Result is nonzero iff shift count is equal to I. */
10537 code = reverse_condition (code);
10541 /* ... fall through ... */
10544 tem = expand_compound_operation (op0);
10553 /* If testing for equality, we can take the NOT of the constant. */
10554 if (equality_comparison_p
10555 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10557 op0 = XEXP (op0, 0);
10562 /* If just looking at the sign bit, reverse the sense of the
10564 if (sign_bit_comparison_p)
10566 op0 = XEXP (op0, 0);
10567 code = (code == GE ? LT : GE);
10573 /* If testing for equality, we can take the NEG of the constant. */
10574 if (equality_comparison_p
10575 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10577 op0 = XEXP (op0, 0);
10582 /* The remaining cases only apply to comparisons with zero. */
10586 /* When X is ABS or is known positive,
10587 (neg X) is < 0 if and only if X != 0. */
10589 if (sign_bit_comparison_p
10590 && (GET_CODE (XEXP (op0, 0)) == ABS
10591 || (mode_width <= HOST_BITS_PER_WIDE_INT
10592 && (nonzero_bits (XEXP (op0, 0), mode)
10593 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10595 op0 = XEXP (op0, 0);
10596 code = (code == LT ? NE : EQ);
10600 /* If we have NEG of something whose two high-order bits are the
10601 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10602 if (num_sign_bit_copies (op0, mode) >= 2)
10604 op0 = XEXP (op0, 0);
10605 code = swap_condition (code);
10611 /* If we are testing equality and our count is a constant, we
10612 can perform the inverse operation on our RHS. */
10613 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10614 && (tem = simplify_binary_operation (ROTATERT, mode,
10615 op1, XEXP (op0, 1))) != 0)
10617 op0 = XEXP (op0, 0);
10622 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10623 a particular bit. Convert it to an AND of a constant of that
10624 bit. This will be converted into a ZERO_EXTRACT. */
10625 if (const_op == 0 && sign_bit_comparison_p
10626 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10627 && mode_width <= HOST_BITS_PER_WIDE_INT)
10629 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10632 - INTVAL (XEXP (op0, 1)))));
10633 code = (code == LT ? NE : EQ);
10637 /* Fall through. */
10640 /* ABS is ignorable inside an equality comparison with zero. */
10641 if (const_op == 0 && equality_comparison_p)
10643 op0 = XEXP (op0, 0);
10649 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10650 to (compare FOO CONST) if CONST fits in FOO's mode and we
10651 are either testing inequality or have an unsigned comparison
10652 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10653 if (! unsigned_comparison_p
10654 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10655 <= HOST_BITS_PER_WIDE_INT)
10656 && ((unsigned HOST_WIDE_INT) const_op
10657 < (((unsigned HOST_WIDE_INT) 1
10658 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
10660 op0 = XEXP (op0, 0);
10666 /* Check for the case where we are comparing A - C1 with C2,
10667 both constants are smaller than 1/2 the maximum positive
10668 value in MODE, and the comparison is equality or unsigned.
10669 In that case, if A is either zero-extended to MODE or has
10670 sufficient sign bits so that the high-order bit in MODE
10671 is a copy of the sign in the inner mode, we can prove that it is
10672 safe to do the operation in the wider mode. This simplifies
10673 many range checks. */
10675 if (mode_width <= HOST_BITS_PER_WIDE_INT
10676 && subreg_lowpart_p (op0)
10677 && GET_CODE (SUBREG_REG (op0)) == PLUS
10678 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
10679 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
10680 && (-INTVAL (XEXP (SUBREG_REG (op0), 1))
10681 < (HOST_WIDE_INT) (GET_MODE_MASK (mode) / 2))
10682 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
10683 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
10684 GET_MODE (SUBREG_REG (op0)))
10685 & ~GET_MODE_MASK (mode))
10686 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
10687 GET_MODE (SUBREG_REG (op0)))
10689 (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10690 - GET_MODE_BITSIZE (mode)))))
10692 op0 = SUBREG_REG (op0);
10696 /* If the inner mode is narrower and we are extracting the low part,
10697 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10698 if (subreg_lowpart_p (op0)
10699 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10700 /* Fall through */ ;
10704 /* ... fall through ... */
10707 if ((unsigned_comparison_p || equality_comparison_p)
10708 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10709 <= HOST_BITS_PER_WIDE_INT)
10710 && ((unsigned HOST_WIDE_INT) const_op
10711 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
10713 op0 = XEXP (op0, 0);
10719 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10720 this for equality comparisons due to pathological cases involving
10722 if (equality_comparison_p
10723 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10724 op1, XEXP (op0, 1))))
10726 op0 = XEXP (op0, 0);
10731 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10732 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10733 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10735 op0 = XEXP (XEXP (op0, 0), 0);
10736 code = (code == LT ? EQ : NE);
10742 /* We used to optimize signed comparisons against zero, but that
10743 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10744 arrive here as equality comparisons, or (GEU, LTU) are
10745 optimized away. No need to special-case them. */
10747 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10748 (eq B (minus A C)), whichever simplifies. We can only do
10749 this for equality comparisons due to pathological cases involving
10751 if (equality_comparison_p
10752 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10753 XEXP (op0, 1), op1)))
10755 op0 = XEXP (op0, 0);
10760 if (equality_comparison_p
10761 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10762 XEXP (op0, 0), op1)))
10764 op0 = XEXP (op0, 1);
10769 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10770 of bits in X minus 1, is one iff X > 0. */
10771 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10772 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10773 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
10775 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10777 op0 = XEXP (op0, 1);
10778 code = (code == GE ? LE : GT);
10784 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10785 if C is zero or B is a constant. */
10786 if (equality_comparison_p
10787 && 0 != (tem = simplify_binary_operation (XOR, mode,
10788 XEXP (op0, 1), op1)))
10790 op0 = XEXP (op0, 0);
10797 case UNEQ: case LTGT:
10798 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
10799 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
10800 case UNORDERED: case ORDERED:
10801 /* We can't do anything if OP0 is a condition code value, rather
10802 than an actual data value. */
10805 || XEXP (op0, 0) == cc0_rtx
10807 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10810 /* Get the two operands being compared. */
10811 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10812 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10814 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10816 /* Check for the cases where we simply want the result of the
10817 earlier test or the opposite of that result. */
10818 if (code == NE || code == EQ
10819 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10820 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10821 && (STORE_FLAG_VALUE
10822 & (((HOST_WIDE_INT) 1
10823 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10824 && (code == LT || code == GE)))
10826 enum rtx_code new_code;
10827 if (code == LT || code == NE)
10828 new_code = GET_CODE (op0);
10830 new_code = combine_reversed_comparison_code (op0);
10832 if (new_code != UNKNOWN)
10843 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10845 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10846 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10847 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10849 op0 = XEXP (op0, 1);
10850 code = (code == GE ? GT : LE);
10856 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10857 will be converted to a ZERO_EXTRACT later. */
10858 if (const_op == 0 && equality_comparison_p
10859 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10860 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10862 op0 = simplify_and_const_int
10863 (op0, mode, gen_rtx_LSHIFTRT (mode,
10865 XEXP (XEXP (op0, 0), 1)),
10866 (HOST_WIDE_INT) 1);
10870 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10871 zero and X is a comparison and C1 and C2 describe only bits set
10872 in STORE_FLAG_VALUE, we can compare with X. */
10873 if (const_op == 0 && equality_comparison_p
10874 && mode_width <= HOST_BITS_PER_WIDE_INT
10875 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10876 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10877 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10878 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10879 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10881 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10882 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10883 if ((~STORE_FLAG_VALUE & mask) == 0
10884 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
10885 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10886 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
10888 op0 = XEXP (XEXP (op0, 0), 0);
10893 /* If we are doing an equality comparison of an AND of a bit equal
10894 to the sign bit, replace this with a LT or GE comparison of
10895 the underlying value. */
10896 if (equality_comparison_p
10898 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10899 && mode_width <= HOST_BITS_PER_WIDE_INT
10900 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10901 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10903 op0 = XEXP (op0, 0);
10904 code = (code == EQ ? GE : LT);
10908 /* If this AND operation is really a ZERO_EXTEND from a narrower
10909 mode, the constant fits within that mode, and this is either an
10910 equality or unsigned comparison, try to do this comparison in
10911 the narrower mode. */
10912 if ((equality_comparison_p || unsigned_comparison_p)
10913 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10914 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10915 & GET_MODE_MASK (mode))
10917 && const_op >> i == 0
10918 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
10920 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
10924 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 fits
10925 in both M1 and M2 and the SUBREG is either paradoxical or
10926 represents the low part, permute the SUBREG and the AND and
10928 if (GET_CODE (XEXP (op0, 0)) == SUBREG
10930 #ifdef WORD_REGISTER_OPERATIONS
10932 > (GET_MODE_BITSIZE
10933 (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10934 && mode_width <= BITS_PER_WORD)
10937 <= (GET_MODE_BITSIZE
10938 (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10939 && subreg_lowpart_p (XEXP (op0, 0))))
10940 #ifndef WORD_REGISTER_OPERATIONS
10941 /* It is unsafe to commute the AND into the SUBREG if the SUBREG
10942 is paradoxical and WORD_REGISTER_OPERATIONS is not defined.
10943 As originally written the upper bits have a defined value
10944 due to the AND operation. However, if we commute the AND
10945 inside the SUBREG then they no longer have defined values
10946 and the meaning of the code has been changed. */
10947 && (GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)))
10948 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))
10950 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10951 && mode_width <= HOST_BITS_PER_WIDE_INT
10952 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10953 <= HOST_BITS_PER_WIDE_INT)
10954 && (INTVAL (XEXP (op0, 1)) & ~mask) == 0
10955 && 0 == (~GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10956 & INTVAL (XEXP (op0, 1)))
10957 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1)) != mask
10958 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10959 != GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10963 = gen_lowpart_for_combine
10965 gen_binary (AND, GET_MODE (SUBREG_REG (XEXP (op0, 0))),
10966 SUBREG_REG (XEXP (op0, 0)), XEXP (op0, 1)));
10970 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10971 (eq (and (lshiftrt X) 1) 0). */
10972 if (const_op == 0 && equality_comparison_p
10973 && XEXP (op0, 1) == const1_rtx
10974 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10975 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == NOT)
10977 op0 = simplify_and_const_int
10979 gen_rtx_LSHIFTRT (mode, XEXP (XEXP (XEXP (op0, 0), 0), 0),
10980 XEXP (XEXP (op0, 0), 1)),
10981 (HOST_WIDE_INT) 1);
10982 code = (code == NE ? EQ : NE);
10988 /* If we have (compare (ashift FOO N) (const_int C)) and
10989 the high order N bits of FOO (N+1 if an inequality comparison)
10990 are known to be zero, we can do this by comparing FOO with C
10991 shifted right N bits so long as the low-order N bits of C are
10993 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10994 && INTVAL (XEXP (op0, 1)) >= 0
10995 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10996 < HOST_BITS_PER_WIDE_INT)
10998 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10999 && mode_width <= HOST_BITS_PER_WIDE_INT
11000 && (nonzero_bits (XEXP (op0, 0), mode)
11001 & ~(mask >> (INTVAL (XEXP (op0, 1))
11002 + ! equality_comparison_p))) == 0)
11004 /* We must perform a logical shift, not an arithmetic one,
11005 as we want the top N bits of C to be zero. */
11006 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
11008 temp >>= INTVAL (XEXP (op0, 1));
11009 op1 = gen_int_mode (temp, mode);
11010 op0 = XEXP (op0, 0);
11014 /* If we are doing a sign bit comparison, it means we are testing
11015 a particular bit. Convert it to the appropriate AND. */
11016 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
11017 && mode_width <= HOST_BITS_PER_WIDE_INT)
11019 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11022 - INTVAL (XEXP (op0, 1)))));
11023 code = (code == LT ? NE : EQ);
11027 /* If this an equality comparison with zero and we are shifting
11028 the low bit to the sign bit, we can convert this to an AND of the
11030 if (const_op == 0 && equality_comparison_p
11031 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11032 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11035 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11036 (HOST_WIDE_INT) 1);
11042 /* If this is an equality comparison with zero, we can do this
11043 as a logical shift, which might be much simpler. */
11044 if (equality_comparison_p && const_op == 0
11045 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
11047 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
11049 INTVAL (XEXP (op0, 1)));
11053 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11054 do the comparison in a narrower mode. */
11055 if (! unsigned_comparison_p
11056 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11057 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11058 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11059 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11060 MODE_INT, 1)) != BLKmode
11061 && (((unsigned HOST_WIDE_INT) const_op
11062 + (GET_MODE_MASK (tmode) >> 1) + 1)
11063 <= GET_MODE_MASK (tmode)))
11065 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
11069 /* Likewise if OP0 is a PLUS of a sign extension with a
11070 constant, which is usually represented with the PLUS
11071 between the shifts. */
11072 if (! unsigned_comparison_p
11073 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11074 && GET_CODE (XEXP (op0, 0)) == PLUS
11075 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
11076 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
11077 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
11078 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11079 MODE_INT, 1)) != BLKmode
11080 && (((unsigned HOST_WIDE_INT) const_op
11081 + (GET_MODE_MASK (tmode) >> 1) + 1)
11082 <= GET_MODE_MASK (tmode)))
11084 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
11085 rtx add_const = XEXP (XEXP (op0, 0), 1);
11086 rtx new_const = gen_binary (ASHIFTRT, GET_MODE (op0), add_const,
11089 op0 = gen_binary (PLUS, tmode,
11090 gen_lowpart_for_combine (tmode, inner),
11095 /* ... fall through ... */
11097 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11098 the low order N bits of FOO are known to be zero, we can do this
11099 by comparing FOO with C shifted left N bits so long as no
11100 overflow occurs. */
11101 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
11102 && INTVAL (XEXP (op0, 1)) >= 0
11103 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11104 && mode_width <= HOST_BITS_PER_WIDE_INT
11105 && (nonzero_bits (XEXP (op0, 0), mode)
11106 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
11107 && (((unsigned HOST_WIDE_INT) const_op
11108 + (GET_CODE (op0) != LSHIFTRT
11109 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
11112 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
11114 /* If the shift was logical, then we must make the condition
11116 if (GET_CODE (op0) == LSHIFTRT)
11117 code = unsigned_condition (code);
11119 const_op <<= INTVAL (XEXP (op0, 1));
11120 op1 = GEN_INT (const_op);
11121 op0 = XEXP (op0, 0);
11125 /* If we are using this shift to extract just the sign bit, we
11126 can replace this with an LT or GE comparison. */
11128 && (equality_comparison_p || sign_bit_comparison_p)
11129 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11130 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11133 op0 = XEXP (op0, 0);
11134 code = (code == NE || code == GT ? LT : GE);
11146 /* Now make any compound operations involved in this comparison. Then,
11147 check for an outmost SUBREG on OP0 that is not doing anything or is
11148 paradoxical. The latter transformation must only be performed when
11149 it is known that the "extra" bits will be the same in op0 and op1 or
11150 that they don't matter. There are three cases to consider:
11152 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11153 care bits and we can assume they have any convenient value. So
11154 making the transformation is safe.
11156 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11157 In this case the upper bits of op0 are undefined. We should not make
11158 the simplification in that case as we do not know the contents of
11161 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11162 NIL. In that case we know those bits are zeros or ones. We must
11163 also be sure that they are the same as the upper bits of op1.
11165 We can never remove a SUBREG for a non-equality comparison because
11166 the sign bit is in a different place in the underlying object. */
11168 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
11169 op1 = make_compound_operation (op1, SET);
11171 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11172 /* Case 3 above, to sometimes allow (subreg (mem x)), isn't
11174 && GET_CODE (SUBREG_REG (op0)) == REG
11175 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11176 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
11177 && (code == NE || code == EQ))
11179 if (GET_MODE_SIZE (GET_MODE (op0))
11180 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
11182 op0 = SUBREG_REG (op0);
11183 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
11185 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
11186 <= HOST_BITS_PER_WIDE_INT)
11187 && (nonzero_bits (SUBREG_REG (op0),
11188 GET_MODE (SUBREG_REG (op0)))
11189 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11191 tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)), op1);
11193 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11194 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11195 op0 = SUBREG_REG (op0), op1 = tem;
11199 /* We now do the opposite procedure: Some machines don't have compare
11200 insns in all modes. If OP0's mode is an integer mode smaller than a
11201 word and we can't do a compare in that mode, see if there is a larger
11202 mode for which we can do the compare. There are a number of cases in
11203 which we can use the wider mode. */
11205 mode = GET_MODE (op0);
11206 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11207 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11208 && ! have_insn_for (COMPARE, mode))
11209 for (tmode = GET_MODE_WIDER_MODE (mode);
11211 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
11212 tmode = GET_MODE_WIDER_MODE (tmode))
11213 if (have_insn_for (COMPARE, tmode))
11217 /* If the only nonzero bits in OP0 and OP1 are those in the
11218 narrower mode and this is an equality or unsigned comparison,
11219 we can use the wider mode. Similarly for sign-extended
11220 values, in which case it is true for all comparisons. */
11221 zero_extended = ((code == EQ || code == NE
11222 || code == GEU || code == GTU
11223 || code == LEU || code == LTU)
11224 && (nonzero_bits (op0, tmode)
11225 & ~GET_MODE_MASK (mode)) == 0
11226 && ((GET_CODE (op1) == CONST_INT
11227 || (nonzero_bits (op1, tmode)
11228 & ~GET_MODE_MASK (mode)) == 0)));
11231 || ((num_sign_bit_copies (op0, tmode)
11232 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11233 - GET_MODE_BITSIZE (mode)))
11234 && (num_sign_bit_copies (op1, tmode)
11235 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11236 - GET_MODE_BITSIZE (mode)))))
11238 /* If OP0 is an AND and we don't have an AND in MODE either,
11239 make a new AND in the proper mode. */
11240 if (GET_CODE (op0) == AND
11241 && !have_insn_for (AND, mode))
11242 op0 = gen_binary (AND, tmode,
11243 gen_lowpart_for_combine (tmode,
11245 gen_lowpart_for_combine (tmode,
11248 op0 = gen_lowpart_for_combine (tmode, op0);
11249 if (zero_extended && GET_CODE (op1) == CONST_INT)
11250 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
11251 op1 = gen_lowpart_for_combine (tmode, op1);
11255 /* If this is a test for negative, we can make an explicit
11256 test of the sign bit. */
11258 if (op1 == const0_rtx && (code == LT || code == GE)
11259 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11261 op0 = gen_binary (AND, tmode,
11262 gen_lowpart_for_combine (tmode, op0),
11263 GEN_INT ((HOST_WIDE_INT) 1
11264 << (GET_MODE_BITSIZE (mode) - 1)));
11265 code = (code == LT) ? NE : EQ;
11270 #ifdef CANONICALIZE_COMPARISON
11271 /* If this machine only supports a subset of valid comparisons, see if we
11272 can convert an unsupported one into a supported one. */
11273 CANONICALIZE_COMPARISON (code, op0, op1);
11282 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
11283 searching backward. */
11284 static enum rtx_code
11285 combine_reversed_comparison_code (exp)
11288 enum rtx_code code1 = reversed_comparison_code (exp, NULL);
11291 if (code1 != UNKNOWN
11292 || GET_MODE_CLASS (GET_MODE (XEXP (exp, 0))) != MODE_CC)
11294 /* Otherwise try and find where the condition codes were last set and
11296 x = get_last_value (XEXP (exp, 0));
11297 if (!x || GET_CODE (x) != COMPARE)
11299 return reversed_comparison_code_parts (GET_CODE (exp),
11300 XEXP (x, 0), XEXP (x, 1), NULL);
11302 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
11303 Return NULL_RTX in case we fail to do the reversal. */
11305 reversed_comparison (exp, mode, op0, op1)
11307 enum machine_mode mode;
11309 enum rtx_code reversed_code = combine_reversed_comparison_code (exp);
11310 if (reversed_code == UNKNOWN)
11313 return gen_binary (reversed_code, mode, op0, op1);
11316 /* Utility function for following routine. Called when X is part of a value
11317 being stored into reg_last_set_value. Sets reg_last_set_table_tick
11318 for each register mentioned. Similar to mention_regs in cse.c */
11321 update_table_tick (x)
11324 enum rtx_code code = GET_CODE (x);
11325 const char *fmt = GET_RTX_FORMAT (code);
11330 unsigned int regno = REGNO (x);
11331 unsigned int endregno
11332 = regno + (regno < FIRST_PSEUDO_REGISTER
11333 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11336 for (r = regno; r < endregno; r++)
11337 reg_last_set_table_tick[r] = label_tick;
11342 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11343 /* Note that we can't have an "E" in values stored; see
11344 get_last_value_validate. */
11346 update_table_tick (XEXP (x, i));
11349 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11350 are saying that the register is clobbered and we no longer know its
11351 value. If INSN is zero, don't update reg_last_set; this is only permitted
11352 with VALUE also zero and is used to invalidate the register. */
11355 record_value_for_reg (reg, insn, value)
11360 unsigned int regno = REGNO (reg);
11361 unsigned int endregno
11362 = regno + (regno < FIRST_PSEUDO_REGISTER
11363 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
11366 /* If VALUE contains REG and we have a previous value for REG, substitute
11367 the previous value. */
11368 if (value && insn && reg_overlap_mentioned_p (reg, value))
11372 /* Set things up so get_last_value is allowed to see anything set up to
11374 subst_low_cuid = INSN_CUID (insn);
11375 tem = get_last_value (reg);
11377 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11378 it isn't going to be useful and will take a lot of time to process,
11379 so just use the CLOBBER. */
11383 if ((GET_RTX_CLASS (GET_CODE (tem)) == '2'
11384 || GET_RTX_CLASS (GET_CODE (tem)) == 'c')
11385 && GET_CODE (XEXP (tem, 0)) == CLOBBER
11386 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
11387 tem = XEXP (tem, 0);
11389 value = replace_rtx (copy_rtx (value), reg, tem);
11393 /* For each register modified, show we don't know its value, that
11394 we don't know about its bitwise content, that its value has been
11395 updated, and that we don't know the location of the death of the
11397 for (i = regno; i < endregno; i++)
11400 reg_last_set[i] = insn;
11402 reg_last_set_value[i] = 0;
11403 reg_last_set_mode[i] = 0;
11404 reg_last_set_nonzero_bits[i] = 0;
11405 reg_last_set_sign_bit_copies[i] = 0;
11406 reg_last_death[i] = 0;
11409 /* Mark registers that are being referenced in this value. */
11411 update_table_tick (value);
11413 /* Now update the status of each register being set.
11414 If someone is using this register in this block, set this register
11415 to invalid since we will get confused between the two lives in this
11416 basic block. This makes using this register always invalid. In cse, we
11417 scan the table to invalidate all entries using this register, but this
11418 is too much work for us. */
11420 for (i = regno; i < endregno; i++)
11422 reg_last_set_label[i] = label_tick;
11423 if (value && reg_last_set_table_tick[i] == label_tick)
11424 reg_last_set_invalid[i] = 1;
11426 reg_last_set_invalid[i] = 0;
11429 /* The value being assigned might refer to X (like in "x++;"). In that
11430 case, we must replace it with (clobber (const_int 0)) to prevent
11432 if (value && ! get_last_value_validate (&value, insn,
11433 reg_last_set_label[regno], 0))
11435 value = copy_rtx (value);
11436 if (! get_last_value_validate (&value, insn,
11437 reg_last_set_label[regno], 1))
11441 /* For the main register being modified, update the value, the mode, the
11442 nonzero bits, and the number of sign bit copies. */
11444 reg_last_set_value[regno] = value;
11448 enum machine_mode mode = GET_MODE (reg);
11449 subst_low_cuid = INSN_CUID (insn);
11450 reg_last_set_mode[regno] = mode;
11451 if (GET_MODE_CLASS (mode) == MODE_INT
11452 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11453 mode = nonzero_bits_mode;
11454 reg_last_set_nonzero_bits[regno] = nonzero_bits (value, mode);
11455 reg_last_set_sign_bit_copies[regno]
11456 = num_sign_bit_copies (value, GET_MODE (reg));
11460 /* Called via note_stores from record_dead_and_set_regs to handle one
11461 SET or CLOBBER in an insn. DATA is the instruction in which the
11462 set is occurring. */
11465 record_dead_and_set_regs_1 (dest, setter, data)
11469 rtx record_dead_insn = (rtx) data;
11471 if (GET_CODE (dest) == SUBREG)
11472 dest = SUBREG_REG (dest);
11474 if (GET_CODE (dest) == REG)
11476 /* If we are setting the whole register, we know its value. Otherwise
11477 show that we don't know the value. We can handle SUBREG in
11479 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11480 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11481 else if (GET_CODE (setter) == SET
11482 && GET_CODE (SET_DEST (setter)) == SUBREG
11483 && SUBREG_REG (SET_DEST (setter)) == dest
11484 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11485 && subreg_lowpart_p (SET_DEST (setter)))
11486 record_value_for_reg (dest, record_dead_insn,
11487 gen_lowpart_for_combine (GET_MODE (dest),
11488 SET_SRC (setter)));
11490 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11492 else if (GET_CODE (dest) == MEM
11493 /* Ignore pushes, they clobber nothing. */
11494 && ! push_operand (dest, GET_MODE (dest)))
11495 mem_last_set = INSN_CUID (record_dead_insn);
11498 /* Update the records of when each REG was most recently set or killed
11499 for the things done by INSN. This is the last thing done in processing
11500 INSN in the combiner loop.
11502 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
11503 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
11504 and also the similar information mem_last_set (which insn most recently
11505 modified memory) and last_call_cuid (which insn was the most recent
11506 subroutine call). */
11509 record_dead_and_set_regs (insn)
11515 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11517 if (REG_NOTE_KIND (link) == REG_DEAD
11518 && GET_CODE (XEXP (link, 0)) == REG)
11520 unsigned int regno = REGNO (XEXP (link, 0));
11521 unsigned int endregno
11522 = regno + (regno < FIRST_PSEUDO_REGISTER
11523 ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0)))
11526 for (i = regno; i < endregno; i++)
11527 reg_last_death[i] = insn;
11529 else if (REG_NOTE_KIND (link) == REG_INC)
11530 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11533 if (GET_CODE (insn) == CALL_INSN)
11535 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11536 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11538 reg_last_set_value[i] = 0;
11539 reg_last_set_mode[i] = 0;
11540 reg_last_set_nonzero_bits[i] = 0;
11541 reg_last_set_sign_bit_copies[i] = 0;
11542 reg_last_death[i] = 0;
11545 last_call_cuid = mem_last_set = INSN_CUID (insn);
11547 /* Don't bother recording what this insn does. It might set the
11548 return value register, but we can't combine into a call
11549 pattern anyway, so there's no point trying (and it may cause
11550 a crash, if e.g. we wind up asking for last_set_value of a
11551 SUBREG of the return value register). */
11555 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11558 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11559 register present in the SUBREG, so for each such SUBREG go back and
11560 adjust nonzero and sign bit information of the registers that are
11561 known to have some zero/sign bits set.
11563 This is needed because when combine blows the SUBREGs away, the
11564 information on zero/sign bits is lost and further combines can be
11565 missed because of that. */
11568 record_promoted_value (insn, subreg)
11573 unsigned int regno = REGNO (SUBREG_REG (subreg));
11574 enum machine_mode mode = GET_MODE (subreg);
11576 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11579 for (links = LOG_LINKS (insn); links;)
11581 insn = XEXP (links, 0);
11582 set = single_set (insn);
11584 if (! set || GET_CODE (SET_DEST (set)) != REG
11585 || REGNO (SET_DEST (set)) != regno
11586 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11588 links = XEXP (links, 1);
11592 if (reg_last_set[regno] == insn)
11594 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11595 reg_last_set_nonzero_bits[regno] &= GET_MODE_MASK (mode);
11598 if (GET_CODE (SET_SRC (set)) == REG)
11600 regno = REGNO (SET_SRC (set));
11601 links = LOG_LINKS (insn);
11608 /* Scan X for promoted SUBREGs. For each one found,
11609 note what it implies to the registers used in it. */
11612 check_promoted_subreg (insn, x)
11616 if (GET_CODE (x) == SUBREG && SUBREG_PROMOTED_VAR_P (x)
11617 && GET_CODE (SUBREG_REG (x)) == REG)
11618 record_promoted_value (insn, x);
11621 const char *format = GET_RTX_FORMAT (GET_CODE (x));
11624 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11628 check_promoted_subreg (insn, XEXP (x, i));
11632 if (XVEC (x, i) != 0)
11633 for (j = 0; j < XVECLEN (x, i); j++)
11634 check_promoted_subreg (insn, XVECEXP (x, i, j));
11640 /* Utility routine for the following function. Verify that all the registers
11641 mentioned in *LOC are valid when *LOC was part of a value set when
11642 label_tick == TICK. Return 0 if some are not.
11644 If REPLACE is nonzero, replace the invalid reference with
11645 (clobber (const_int 0)) and return 1. This replacement is useful because
11646 we often can get useful information about the form of a value (e.g., if
11647 it was produced by a shift that always produces -1 or 0) even though
11648 we don't know exactly what registers it was produced from. */
11651 get_last_value_validate (loc, insn, tick, replace)
11658 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11659 int len = GET_RTX_LENGTH (GET_CODE (x));
11662 if (GET_CODE (x) == REG)
11664 unsigned int regno = REGNO (x);
11665 unsigned int endregno
11666 = regno + (regno < FIRST_PSEUDO_REGISTER
11667 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11670 for (j = regno; j < endregno; j++)
11671 if (reg_last_set_invalid[j]
11672 /* If this is a pseudo-register that was only set once and not
11673 live at the beginning of the function, it is always valid. */
11674 || (! (regno >= FIRST_PSEUDO_REGISTER
11675 && REG_N_SETS (regno) == 1
11676 && (! REGNO_REG_SET_P
11677 (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, regno)))
11678 && reg_last_set_label[j] > tick))
11681 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11687 /* If this is a memory reference, make sure that there were
11688 no stores after it that might have clobbered the value. We don't
11689 have alias info, so we assume any store invalidates it. */
11690 else if (GET_CODE (x) == MEM && ! RTX_UNCHANGING_P (x)
11691 && INSN_CUID (insn) <= mem_last_set)
11694 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11698 for (i = 0; i < len; i++)
11700 && get_last_value_validate (&XEXP (x, i), insn, tick, replace) == 0)
11701 /* Don't bother with these. They shouldn't occur anyway. */
11705 /* If we haven't found a reason for it to be invalid, it is valid. */
11709 /* Get the last value assigned to X, if known. Some registers
11710 in the value may be replaced with (clobber (const_int 0)) if their value
11711 is known longer known reliably. */
11717 unsigned int regno;
11720 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11721 then convert it to the desired mode. If this is a paradoxical SUBREG,
11722 we cannot predict what values the "extra" bits might have. */
11723 if (GET_CODE (x) == SUBREG
11724 && subreg_lowpart_p (x)
11725 && (GET_MODE_SIZE (GET_MODE (x))
11726 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11727 && (value = get_last_value (SUBREG_REG (x))) != 0)
11728 return gen_lowpart_for_combine (GET_MODE (x), value);
11730 if (GET_CODE (x) != REG)
11734 value = reg_last_set_value[regno];
11736 /* If we don't have a value, or if it isn't for this basic block and
11737 it's either a hard register, set more than once, or it's a live
11738 at the beginning of the function, return 0.
11740 Because if it's not live at the beginning of the function then the reg
11741 is always set before being used (is never used without being set).
11742 And, if it's set only once, and it's always set before use, then all
11743 uses must have the same last value, even if it's not from this basic
11747 || (reg_last_set_label[regno] != label_tick
11748 && (regno < FIRST_PSEUDO_REGISTER
11749 || REG_N_SETS (regno) != 1
11750 || (REGNO_REG_SET_P
11751 (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, regno)))))
11754 /* If the value was set in a later insn than the ones we are processing,
11755 we can't use it even if the register was only set once. */
11756 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
11759 /* If the value has all its registers valid, return it. */
11760 if (get_last_value_validate (&value, reg_last_set[regno],
11761 reg_last_set_label[regno], 0))
11764 /* Otherwise, make a copy and replace any invalid register with
11765 (clobber (const_int 0)). If that fails for some reason, return 0. */
11767 value = copy_rtx (value);
11768 if (get_last_value_validate (&value, reg_last_set[regno],
11769 reg_last_set_label[regno], 1))
11775 /* Return nonzero if expression X refers to a REG or to memory
11776 that is set in an instruction more recent than FROM_CUID. */
11779 use_crosses_set_p (x, from_cuid)
11785 enum rtx_code code = GET_CODE (x);
11789 unsigned int regno = REGNO (x);
11790 unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER
11791 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11793 #ifdef PUSH_ROUNDING
11794 /* Don't allow uses of the stack pointer to be moved,
11795 because we don't know whether the move crosses a push insn. */
11796 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11799 for (; regno < endreg; regno++)
11800 if (reg_last_set[regno]
11801 && INSN_CUID (reg_last_set[regno]) > from_cuid)
11806 if (code == MEM && mem_last_set > from_cuid)
11809 fmt = GET_RTX_FORMAT (code);
11811 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11816 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11817 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11820 else if (fmt[i] == 'e'
11821 && use_crosses_set_p (XEXP (x, i), from_cuid))
11827 /* Define three variables used for communication between the following
11830 static unsigned int reg_dead_regno, reg_dead_endregno;
11831 static int reg_dead_flag;
11833 /* Function called via note_stores from reg_dead_at_p.
11835 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11836 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11839 reg_dead_at_p_1 (dest, x, data)
11842 void *data ATTRIBUTE_UNUSED;
11844 unsigned int regno, endregno;
11846 if (GET_CODE (dest) != REG)
11849 regno = REGNO (dest);
11850 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11851 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
11853 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11854 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11857 /* Return nonzero if REG is known to be dead at INSN.
11859 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11860 referencing REG, it is dead. If we hit a SET referencing REG, it is
11861 live. Otherwise, see if it is live or dead at the start of the basic
11862 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11863 must be assumed to be always live. */
11866 reg_dead_at_p (reg, insn)
11873 /* Set variables for reg_dead_at_p_1. */
11874 reg_dead_regno = REGNO (reg);
11875 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
11876 ? HARD_REGNO_NREGS (reg_dead_regno,
11882 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11883 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11885 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11886 if (TEST_HARD_REG_BIT (newpat_used_regs, i))
11890 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11891 beginning of function. */
11892 for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER;
11893 insn = prev_nonnote_insn (insn))
11895 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11897 return reg_dead_flag == 1 ? 1 : 0;
11899 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11903 /* Get the basic block that we were in. */
11905 block = ENTRY_BLOCK_PTR->next_bb;
11908 FOR_EACH_BB (block)
11909 if (insn == block->head)
11912 if (block == EXIT_BLOCK_PTR)
11916 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11917 if (REGNO_REG_SET_P (block->global_live_at_start, i))
11923 /* Note hard registers in X that are used. This code is similar to
11924 that in flow.c, but much simpler since we don't care about pseudos. */
11927 mark_used_regs_combine (x)
11930 RTX_CODE code = GET_CODE (x);
11931 unsigned int regno;
11944 case ADDR_DIFF_VEC:
11947 /* CC0 must die in the insn after it is set, so we don't need to take
11948 special note of it here. */
11954 /* If we are clobbering a MEM, mark any hard registers inside the
11955 address as used. */
11956 if (GET_CODE (XEXP (x, 0)) == MEM)
11957 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11962 /* A hard reg in a wide mode may really be multiple registers.
11963 If so, mark all of them just like the first. */
11964 if (regno < FIRST_PSEUDO_REGISTER)
11966 unsigned int endregno, r;
11968 /* None of this applies to the stack, frame or arg pointers. */
11969 if (regno == STACK_POINTER_REGNUM
11970 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11971 || regno == HARD_FRAME_POINTER_REGNUM
11973 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11974 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11976 || regno == FRAME_POINTER_REGNUM)
11979 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11980 for (r = regno; r < endregno; r++)
11981 SET_HARD_REG_BIT (newpat_used_regs, r);
11987 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11989 rtx testreg = SET_DEST (x);
11991 while (GET_CODE (testreg) == SUBREG
11992 || GET_CODE (testreg) == ZERO_EXTRACT
11993 || GET_CODE (testreg) == SIGN_EXTRACT
11994 || GET_CODE (testreg) == STRICT_LOW_PART)
11995 testreg = XEXP (testreg, 0);
11997 if (GET_CODE (testreg) == MEM)
11998 mark_used_regs_combine (XEXP (testreg, 0));
12000 mark_used_regs_combine (SET_SRC (x));
12008 /* Recursively scan the operands of this expression. */
12011 const char *fmt = GET_RTX_FORMAT (code);
12013 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12016 mark_used_regs_combine (XEXP (x, i));
12017 else if (fmt[i] == 'E')
12021 for (j = 0; j < XVECLEN (x, i); j++)
12022 mark_used_regs_combine (XVECEXP (x, i, j));
12028 /* Remove register number REGNO from the dead registers list of INSN.
12030 Return the note used to record the death, if there was one. */
12033 remove_death (regno, insn)
12034 unsigned int regno;
12037 rtx note = find_regno_note (insn, REG_DEAD, regno);
12041 REG_N_DEATHS (regno)--;
12042 remove_note (insn, note);
12048 /* For each register (hardware or pseudo) used within expression X, if its
12049 death is in an instruction with cuid between FROM_CUID (inclusive) and
12050 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12051 list headed by PNOTES.
12053 That said, don't move registers killed by maybe_kill_insn.
12055 This is done when X is being merged by combination into TO_INSN. These
12056 notes will then be distributed as needed. */
12059 move_deaths (x, maybe_kill_insn, from_cuid, to_insn, pnotes)
12061 rtx maybe_kill_insn;
12068 enum rtx_code code = GET_CODE (x);
12072 unsigned int regno = REGNO (x);
12073 rtx where_dead = reg_last_death[regno];
12074 rtx before_dead, after_dead;
12076 /* Don't move the register if it gets killed in between from and to. */
12077 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
12078 && ! reg_referenced_p (x, maybe_kill_insn))
12081 /* WHERE_DEAD could be a USE insn made by combine, so first we
12082 make sure that we have insns with valid INSN_CUID values. */
12083 before_dead = where_dead;
12084 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
12085 before_dead = PREV_INSN (before_dead);
12087 after_dead = where_dead;
12088 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
12089 after_dead = NEXT_INSN (after_dead);
12091 if (before_dead && after_dead
12092 && INSN_CUID (before_dead) >= from_cuid
12093 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
12094 || (where_dead != after_dead
12095 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
12097 rtx note = remove_death (regno, where_dead);
12099 /* It is possible for the call above to return 0. This can occur
12100 when reg_last_death points to I2 or I1 that we combined with.
12101 In that case make a new note.
12103 We must also check for the case where X is a hard register
12104 and NOTE is a death note for a range of hard registers
12105 including X. In that case, we must put REG_DEAD notes for
12106 the remaining registers in place of NOTE. */
12108 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
12109 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12110 > GET_MODE_SIZE (GET_MODE (x))))
12112 unsigned int deadregno = REGNO (XEXP (note, 0));
12113 unsigned int deadend
12114 = (deadregno + HARD_REGNO_NREGS (deadregno,
12115 GET_MODE (XEXP (note, 0))));
12116 unsigned int ourend
12117 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
12120 for (i = deadregno; i < deadend; i++)
12121 if (i < regno || i >= ourend)
12122 REG_NOTES (where_dead)
12123 = gen_rtx_EXPR_LIST (REG_DEAD,
12125 REG_NOTES (where_dead));
12128 /* If we didn't find any note, or if we found a REG_DEAD note that
12129 covers only part of the given reg, and we have a multi-reg hard
12130 register, then to be safe we must check for REG_DEAD notes
12131 for each register other than the first. They could have
12132 their own REG_DEAD notes lying around. */
12133 else if ((note == 0
12135 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12136 < GET_MODE_SIZE (GET_MODE (x)))))
12137 && regno < FIRST_PSEUDO_REGISTER
12138 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
12140 unsigned int ourend
12141 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
12142 unsigned int i, offset;
12146 offset = HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0)));
12150 for (i = regno + offset; i < ourend; i++)
12151 move_deaths (regno_reg_rtx[i],
12152 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
12155 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
12157 XEXP (note, 1) = *pnotes;
12161 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
12163 REG_N_DEATHS (regno)++;
12169 else if (GET_CODE (x) == SET)
12171 rtx dest = SET_DEST (x);
12173 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
12175 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12176 that accesses one word of a multi-word item, some
12177 piece of everything register in the expression is used by
12178 this insn, so remove any old death. */
12179 /* ??? So why do we test for equality of the sizes? */
12181 if (GET_CODE (dest) == ZERO_EXTRACT
12182 || GET_CODE (dest) == STRICT_LOW_PART
12183 || (GET_CODE (dest) == SUBREG
12184 && (((GET_MODE_SIZE (GET_MODE (dest))
12185 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
12186 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
12187 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
12189 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
12193 /* If this is some other SUBREG, we know it replaces the entire
12194 value, so use that as the destination. */
12195 if (GET_CODE (dest) == SUBREG)
12196 dest = SUBREG_REG (dest);
12198 /* If this is a MEM, adjust deaths of anything used in the address.
12199 For a REG (the only other possibility), the entire value is
12200 being replaced so the old value is not used in this insn. */
12202 if (GET_CODE (dest) == MEM)
12203 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
12208 else if (GET_CODE (x) == CLOBBER)
12211 len = GET_RTX_LENGTH (code);
12212 fmt = GET_RTX_FORMAT (code);
12214 for (i = 0; i < len; i++)
12219 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12220 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
12223 else if (fmt[i] == 'e')
12224 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
12228 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12229 pattern of an insn. X must be a REG. */
12232 reg_bitfield_target_p (x, body)
12238 if (GET_CODE (body) == SET)
12240 rtx dest = SET_DEST (body);
12242 unsigned int regno, tregno, endregno, endtregno;
12244 if (GET_CODE (dest) == ZERO_EXTRACT)
12245 target = XEXP (dest, 0);
12246 else if (GET_CODE (dest) == STRICT_LOW_PART)
12247 target = SUBREG_REG (XEXP (dest, 0));
12251 if (GET_CODE (target) == SUBREG)
12252 target = SUBREG_REG (target);
12254 if (GET_CODE (target) != REG)
12257 tregno = REGNO (target), regno = REGNO (x);
12258 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
12259 return target == x;
12261 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
12262 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
12264 return endregno > tregno && regno < endtregno;
12267 else if (GET_CODE (body) == PARALLEL)
12268 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
12269 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
12275 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12276 as appropriate. I3 and I2 are the insns resulting from the combination
12277 insns including FROM (I2 may be zero).
12279 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
12280 not need REG_DEAD notes because they are being substituted for. This
12281 saves searching in the most common cases.
12283 Each note in the list is either ignored or placed on some insns, depending
12284 on the type of note. */
12287 distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
12291 rtx elim_i2, elim_i1;
12293 rtx note, next_note;
12296 for (note = notes; note; note = next_note)
12298 rtx place = 0, place2 = 0;
12300 /* If this NOTE references a pseudo register, ensure it references
12301 the latest copy of that register. */
12302 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
12303 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
12304 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
12306 next_note = XEXP (note, 1);
12307 switch (REG_NOTE_KIND (note))
12311 case REG_EXEC_COUNT:
12312 /* Doesn't matter much where we put this, as long as it's somewhere.
12313 It is preferable to keep these notes on branches, which is most
12314 likely to be i3. */
12318 case REG_VTABLE_REF:
12319 /* ??? Should remain with *a particular* memory load. Given the
12320 nature of vtable data, the last insn seems relatively safe. */
12324 case REG_NON_LOCAL_GOTO:
12325 if (GET_CODE (i3) == JUMP_INSN)
12327 else if (i2 && GET_CODE (i2) == JUMP_INSN)
12333 case REG_EH_REGION:
12334 /* These notes must remain with the call or trapping instruction. */
12335 if (GET_CODE (i3) == CALL_INSN)
12337 else if (i2 && GET_CODE (i2) == CALL_INSN)
12339 else if (flag_non_call_exceptions)
12341 if (may_trap_p (i3))
12343 else if (i2 && may_trap_p (i2))
12345 /* ??? Otherwise assume we've combined things such that we
12346 can now prove that the instructions can't trap. Drop the
12347 note in this case. */
12355 /* These notes must remain with the call. It should not be
12356 possible for both I2 and I3 to be a call. */
12357 if (GET_CODE (i3) == CALL_INSN)
12359 else if (i2 && GET_CODE (i2) == CALL_INSN)
12366 /* Any clobbers for i3 may still exist, and so we must process
12367 REG_UNUSED notes from that insn.
12369 Any clobbers from i2 or i1 can only exist if they were added by
12370 recog_for_combine. In that case, recog_for_combine created the
12371 necessary REG_UNUSED notes. Trying to keep any original
12372 REG_UNUSED notes from these insns can cause incorrect output
12373 if it is for the same register as the original i3 dest.
12374 In that case, we will notice that the register is set in i3,
12375 and then add a REG_UNUSED note for the destination of i3, which
12376 is wrong. However, it is possible to have REG_UNUSED notes from
12377 i2 or i1 for register which were both used and clobbered, so
12378 we keep notes from i2 or i1 if they will turn into REG_DEAD
12381 /* If this register is set or clobbered in I3, put the note there
12382 unless there is one already. */
12383 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
12385 if (from_insn != i3)
12388 if (! (GET_CODE (XEXP (note, 0)) == REG
12389 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
12390 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
12393 /* Otherwise, if this register is used by I3, then this register
12394 now dies here, so we must put a REG_DEAD note here unless there
12396 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
12397 && ! (GET_CODE (XEXP (note, 0)) == REG
12398 ? find_regno_note (i3, REG_DEAD,
12399 REGNO (XEXP (note, 0)))
12400 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
12402 PUT_REG_NOTE_KIND (note, REG_DEAD);
12410 /* These notes say something about results of an insn. We can
12411 only support them if they used to be on I3 in which case they
12412 remain on I3. Otherwise they are ignored.
12414 If the note refers to an expression that is not a constant, we
12415 must also ignore the note since we cannot tell whether the
12416 equivalence is still true. It might be possible to do
12417 slightly better than this (we only have a problem if I2DEST
12418 or I1DEST is present in the expression), but it doesn't
12419 seem worth the trouble. */
12421 if (from_insn == i3
12422 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
12427 case REG_NO_CONFLICT:
12428 /* These notes say something about how a register is used. They must
12429 be present on any use of the register in I2 or I3. */
12430 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12433 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12443 /* This can show up in several ways -- either directly in the
12444 pattern, or hidden off in the constant pool with (or without?)
12445 a REG_EQUAL note. */
12446 /* ??? Ignore the without-reg_equal-note problem for now. */
12447 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12448 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12449 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12450 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12454 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12455 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12456 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12457 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12465 /* Don't attach REG_LABEL note to a JUMP_INSN which has
12466 JUMP_LABEL already. Instead, decrement LABEL_NUSES. */
12467 if (place && GET_CODE (place) == JUMP_INSN && JUMP_LABEL (place))
12469 if (JUMP_LABEL (place) != XEXP (note, 0))
12471 if (GET_CODE (JUMP_LABEL (place)) == CODE_LABEL)
12472 LABEL_NUSES (JUMP_LABEL (place))--;
12475 if (place2 && GET_CODE (place2) == JUMP_INSN && JUMP_LABEL (place2))
12477 if (JUMP_LABEL (place2) != XEXP (note, 0))
12479 if (GET_CODE (JUMP_LABEL (place2)) == CODE_LABEL)
12480 LABEL_NUSES (JUMP_LABEL (place2))--;
12487 /* These notes say something about the value of a register prior
12488 to the execution of an insn. It is too much trouble to see
12489 if the note is still correct in all situations. It is better
12490 to simply delete it. */
12494 /* If the insn previously containing this note still exists,
12495 put it back where it was. Otherwise move it to the previous
12496 insn. Adjust the corresponding REG_LIBCALL note. */
12497 if (GET_CODE (from_insn) != NOTE)
12501 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
12502 place = prev_real_insn (from_insn);
12504 XEXP (tem, 0) = place;
12505 /* If we're deleting the last remaining instruction of a
12506 libcall sequence, don't add the notes. */
12507 else if (XEXP (note, 0) == from_insn)
12513 /* This is handled similarly to REG_RETVAL. */
12514 if (GET_CODE (from_insn) != NOTE)
12518 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
12519 place = next_real_insn (from_insn);
12521 XEXP (tem, 0) = place;
12522 /* If we're deleting the last remaining instruction of a
12523 libcall sequence, don't add the notes. */
12524 else if (XEXP (note, 0) == from_insn)
12530 /* If the register is used as an input in I3, it dies there.
12531 Similarly for I2, if it is nonzero and adjacent to I3.
12533 If the register is not used as an input in either I3 or I2
12534 and it is not one of the registers we were supposed to eliminate,
12535 there are two possibilities. We might have a non-adjacent I2
12536 or we might have somehow eliminated an additional register
12537 from a computation. For example, we might have had A & B where
12538 we discover that B will always be zero. In this case we will
12539 eliminate the reference to A.
12541 In both cases, we must search to see if we can find a previous
12542 use of A and put the death note there. */
12545 && GET_CODE (from_insn) == CALL_INSN
12546 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12548 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12550 else if (i2 != 0 && next_nonnote_insn (i2) == i3
12551 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12554 if (rtx_equal_p (XEXP (note, 0), elim_i2)
12555 || rtx_equal_p (XEXP (note, 0), elim_i1))
12560 basic_block bb = this_basic_block;
12562 for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem))
12564 if (! INSN_P (tem))
12566 if (tem == bb->head)
12571 /* If the register is being set at TEM, see if that is all
12572 TEM is doing. If so, delete TEM. Otherwise, make this
12573 into a REG_UNUSED note instead. */
12574 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
12576 rtx set = single_set (tem);
12577 rtx inner_dest = 0;
12579 rtx cc0_setter = NULL_RTX;
12583 for (inner_dest = SET_DEST (set);
12584 (GET_CODE (inner_dest) == STRICT_LOW_PART
12585 || GET_CODE (inner_dest) == SUBREG
12586 || GET_CODE (inner_dest) == ZERO_EXTRACT);
12587 inner_dest = XEXP (inner_dest, 0))
12590 /* Verify that it was the set, and not a clobber that
12591 modified the register.
12593 CC0 targets must be careful to maintain setter/user
12594 pairs. If we cannot delete the setter due to side
12595 effects, mark the user with an UNUSED note instead
12598 if (set != 0 && ! side_effects_p (SET_SRC (set))
12599 && rtx_equal_p (XEXP (note, 0), inner_dest)
12601 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12602 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12603 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12607 /* Move the notes and links of TEM elsewhere.
12608 This might delete other dead insns recursively.
12609 First set the pattern to something that won't use
12612 PATTERN (tem) = pc_rtx;
12614 distribute_notes (REG_NOTES (tem), tem, tem,
12615 NULL_RTX, NULL_RTX, NULL_RTX);
12616 distribute_links (LOG_LINKS (tem));
12618 PUT_CODE (tem, NOTE);
12619 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
12620 NOTE_SOURCE_FILE (tem) = 0;
12623 /* Delete the setter too. */
12626 PATTERN (cc0_setter) = pc_rtx;
12628 distribute_notes (REG_NOTES (cc0_setter),
12629 cc0_setter, cc0_setter,
12630 NULL_RTX, NULL_RTX, NULL_RTX);
12631 distribute_links (LOG_LINKS (cc0_setter));
12633 PUT_CODE (cc0_setter, NOTE);
12634 NOTE_LINE_NUMBER (cc0_setter)
12635 = NOTE_INSN_DELETED;
12636 NOTE_SOURCE_FILE (cc0_setter) = 0;
12640 /* If the register is both set and used here, put the
12641 REG_DEAD note here, but place a REG_UNUSED note
12642 here too unless there already is one. */
12643 else if (reg_referenced_p (XEXP (note, 0),
12648 if (! find_regno_note (tem, REG_UNUSED,
12649 REGNO (XEXP (note, 0))))
12651 = gen_rtx_EXPR_LIST (REG_UNUSED, XEXP (note, 0),
12656 PUT_REG_NOTE_KIND (note, REG_UNUSED);
12658 /* If there isn't already a REG_UNUSED note, put one
12660 if (! find_regno_note (tem, REG_UNUSED,
12661 REGNO (XEXP (note, 0))))
12666 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12667 || (GET_CODE (tem) == CALL_INSN
12668 && find_reg_fusage (tem, USE, XEXP (note, 0))))
12672 /* If we are doing a 3->2 combination, and we have a
12673 register which formerly died in i3 and was not used
12674 by i2, which now no longer dies in i3 and is used in
12675 i2 but does not die in i2, and place is between i2
12676 and i3, then we may need to move a link from place to
12678 if (i2 && INSN_UID (place) <= max_uid_cuid
12679 && INSN_CUID (place) > INSN_CUID (i2)
12681 && INSN_CUID (from_insn) > INSN_CUID (i2)
12682 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12684 rtx links = LOG_LINKS (place);
12685 LOG_LINKS (place) = 0;
12686 distribute_links (links);
12691 if (tem == bb->head)
12695 /* We haven't found an insn for the death note and it
12696 is still a REG_DEAD note, but we have hit the beginning
12697 of the block. If the existing life info says the reg
12698 was dead, there's nothing left to do. Otherwise, we'll
12699 need to do a global life update after combine. */
12700 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
12701 && REGNO_REG_SET_P (bb->global_live_at_start,
12702 REGNO (XEXP (note, 0))))
12704 SET_BIT (refresh_blocks, this_basic_block->index);
12709 /* If the register is set or already dead at PLACE, we needn't do
12710 anything with this note if it is still a REG_DEAD note.
12711 We can here if it is set at all, not if is it totally replace,
12712 which is what `dead_or_set_p' checks, so also check for it being
12715 if (place && REG_NOTE_KIND (note) == REG_DEAD)
12717 unsigned int regno = REGNO (XEXP (note, 0));
12719 /* Similarly, if the instruction on which we want to place
12720 the note is a noop, we'll need do a global live update
12721 after we remove them in delete_noop_moves. */
12722 if (noop_move_p (place))
12724 SET_BIT (refresh_blocks, this_basic_block->index);
12728 if (dead_or_set_p (place, XEXP (note, 0))
12729 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12731 /* Unless the register previously died in PLACE, clear
12732 reg_last_death. [I no longer understand why this is
12734 if (reg_last_death[regno] != place)
12735 reg_last_death[regno] = 0;
12739 reg_last_death[regno] = place;
12741 /* If this is a death note for a hard reg that is occupying
12742 multiple registers, ensure that we are still using all
12743 parts of the object. If we find a piece of the object
12744 that is unused, we must arrange for an appropriate REG_DEAD
12745 note to be added for it. However, we can't just emit a USE
12746 and tag the note to it, since the register might actually
12747 be dead; so we recourse, and the recursive call then finds
12748 the previous insn that used this register. */
12750 if (place && regno < FIRST_PSEUDO_REGISTER
12751 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
12753 unsigned int endregno
12754 = regno + HARD_REGNO_NREGS (regno,
12755 GET_MODE (XEXP (note, 0)));
12759 for (i = regno; i < endregno; i++)
12760 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12761 && ! find_regno_fusage (place, USE, i))
12762 || dead_or_set_regno_p (place, i))
12767 /* Put only REG_DEAD notes for pieces that are
12768 not already dead or set. */
12770 for (i = regno; i < endregno;
12771 i += HARD_REGNO_NREGS (i, reg_raw_mode[i]))
12773 rtx piece = regno_reg_rtx[i];
12774 basic_block bb = this_basic_block;
12776 if (! dead_or_set_p (place, piece)
12777 && ! reg_bitfield_target_p (piece,
12781 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
12783 distribute_notes (new_note, place, place,
12784 NULL_RTX, NULL_RTX, NULL_RTX);
12786 else if (! refers_to_regno_p (i, i + 1,
12787 PATTERN (place), 0)
12788 && ! find_regno_fusage (place, USE, i))
12789 for (tem = PREV_INSN (place); ;
12790 tem = PREV_INSN (tem))
12792 if (! INSN_P (tem))
12794 if (tem == bb->head)
12796 SET_BIT (refresh_blocks,
12797 this_basic_block->index);
12803 if (dead_or_set_p (tem, piece)
12804 || reg_bitfield_target_p (piece,
12808 = gen_rtx_EXPR_LIST (REG_UNUSED, piece,
12823 /* Any other notes should not be present at this point in the
12830 XEXP (note, 1) = REG_NOTES (place);
12831 REG_NOTES (place) = note;
12833 else if ((REG_NOTE_KIND (note) == REG_DEAD
12834 || REG_NOTE_KIND (note) == REG_UNUSED)
12835 && GET_CODE (XEXP (note, 0)) == REG)
12836 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
12840 if ((REG_NOTE_KIND (note) == REG_DEAD
12841 || REG_NOTE_KIND (note) == REG_UNUSED)
12842 && GET_CODE (XEXP (note, 0)) == REG)
12843 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
12845 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
12846 REG_NOTE_KIND (note),
12848 REG_NOTES (place2));
12853 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12854 I3, I2, and I1 to new locations. This is also called in one case to
12855 add a link pointing at I3 when I3's destination is changed. */
12858 distribute_links (links)
12861 rtx link, next_link;
12863 for (link = links; link; link = next_link)
12869 next_link = XEXP (link, 1);
12871 /* If the insn that this link points to is a NOTE or isn't a single
12872 set, ignore it. In the latter case, it isn't clear what we
12873 can do other than ignore the link, since we can't tell which
12874 register it was for. Such links wouldn't be used by combine
12877 It is not possible for the destination of the target of the link to
12878 have been changed by combine. The only potential of this is if we
12879 replace I3, I2, and I1 by I3 and I2. But in that case the
12880 destination of I2 also remains unchanged. */
12882 if (GET_CODE (XEXP (link, 0)) == NOTE
12883 || (set = single_set (XEXP (link, 0))) == 0)
12886 reg = SET_DEST (set);
12887 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12888 || GET_CODE (reg) == SIGN_EXTRACT
12889 || GET_CODE (reg) == STRICT_LOW_PART)
12890 reg = XEXP (reg, 0);
12892 /* A LOG_LINK is defined as being placed on the first insn that uses
12893 a register and points to the insn that sets the register. Start
12894 searching at the next insn after the target of the link and stop
12895 when we reach a set of the register or the end of the basic block.
12897 Note that this correctly handles the link that used to point from
12898 I3 to I2. Also note that not much searching is typically done here
12899 since most links don't point very far away. */
12901 for (insn = NEXT_INSN (XEXP (link, 0));
12902 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
12903 || this_basic_block->next_bb->head != insn));
12904 insn = NEXT_INSN (insn))
12905 if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12907 if (reg_referenced_p (reg, PATTERN (insn)))
12911 else if (GET_CODE (insn) == CALL_INSN
12912 && find_reg_fusage (insn, USE, reg))
12918 /* If we found a place to put the link, place it there unless there
12919 is already a link to the same insn as LINK at that point. */
12925 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12926 if (XEXP (link2, 0) == XEXP (link, 0))
12931 XEXP (link, 1) = LOG_LINKS (place);
12932 LOG_LINKS (place) = link;
12934 /* Set added_links_insn to the earliest insn we added a
12936 if (added_links_insn == 0
12937 || INSN_CUID (added_links_insn) > INSN_CUID (place))
12938 added_links_insn = place;
12944 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12950 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
12951 && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE)
12952 insn = NEXT_INSN (insn);
12954 if (INSN_UID (insn) > max_uid_cuid)
12957 return INSN_CUID (insn);
12961 dump_combine_stats (file)
12966 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12967 combine_attempts, combine_merges, combine_extras, combine_successes);
12971 dump_combine_total_stats (file)
12976 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12977 total_attempts, total_merges, total_extras, total_successes);