1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
4 2011 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
87 #include "hard-reg-set.h"
88 #include "basic-block.h"
89 #include "insn-config.h"
91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
93 #include "insn-attr.h"
95 #include "diagnostic-core.h"
98 #include "insn-codes.h"
99 #include "rtlhooks-def.h"
100 /* Include output.h for dump_file. */
104 #include "tree-pass.h"
109 /* Number of attempts to combine instructions in this function. */
111 static int combine_attempts;
113 /* Number of attempts that got as far as substitution in this function. */
115 static int combine_merges;
117 /* Number of instructions combined with added SETs in this function. */
119 static int combine_extras;
121 /* Number of instructions combined in this function. */
123 static int combine_successes;
125 /* Totals over entire compilation. */
127 static int total_attempts, total_merges, total_extras, total_successes;
129 /* combine_instructions may try to replace the right hand side of the
130 second instruction with the value of an associated REG_EQUAL note
131 before throwing it at try_combine. That is problematic when there
132 is a REG_DEAD note for a register used in the old right hand side
133 and can cause distribute_notes to do wrong things. This is the
134 second instruction if it has been so modified, null otherwise. */
138 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
140 static rtx i2mod_old_rhs;
142 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
144 static rtx i2mod_new_rhs;
146 typedef struct reg_stat_struct {
147 /* Record last point of death of (hard or pseudo) register n. */
150 /* Record last point of modification of (hard or pseudo) register n. */
153 /* The next group of fields allows the recording of the last value assigned
154 to (hard or pseudo) register n. We use this information to see if an
155 operation being processed is redundant given a prior operation performed
156 on the register. For example, an `and' with a constant is redundant if
157 all the zero bits are already known to be turned off.
159 We use an approach similar to that used by cse, but change it in the
162 (1) We do not want to reinitialize at each label.
163 (2) It is useful, but not critical, to know the actual value assigned
164 to a register. Often just its form is helpful.
166 Therefore, we maintain the following fields:
168 last_set_value the last value assigned
169 last_set_label records the value of label_tick when the
170 register was assigned
171 last_set_table_tick records the value of label_tick when a
172 value using the register is assigned
173 last_set_invalid set to nonzero when it is not valid
174 to use the value of this register in some
177 To understand the usage of these tables, it is important to understand
178 the distinction between the value in last_set_value being valid and
179 the register being validly contained in some other expression in the
182 (The next two parameters are out of date).
184 reg_stat[i].last_set_value is valid if it is nonzero, and either
185 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
187 Register I may validly appear in any expression returned for the value
188 of another register if reg_n_sets[i] is 1. It may also appear in the
189 value for register J if reg_stat[j].last_set_invalid is zero, or
190 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
192 If an expression is found in the table containing a register which may
193 not validly appear in an expression, the register is replaced by
194 something that won't match, (clobber (const_int 0)). */
196 /* Record last value assigned to (hard or pseudo) register n. */
200 /* Record the value of label_tick when an expression involving register n
201 is placed in last_set_value. */
203 int last_set_table_tick;
205 /* Record the value of label_tick when the value for register n is placed in
210 /* These fields are maintained in parallel with last_set_value and are
211 used to store the mode in which the register was last set, the bits
212 that were known to be zero when it was last set, and the number of
213 sign bits copies it was known to have when it was last set. */
215 unsigned HOST_WIDE_INT last_set_nonzero_bits;
216 char last_set_sign_bit_copies;
217 ENUM_BITFIELD(machine_mode) last_set_mode : 8;
219 /* Set nonzero if references to register n in expressions should not be
220 used. last_set_invalid is set nonzero when this register is being
221 assigned to and last_set_table_tick == label_tick. */
223 char last_set_invalid;
225 /* Some registers that are set more than once and used in more than one
226 basic block are nevertheless always set in similar ways. For example,
227 a QImode register may be loaded from memory in two places on a machine
228 where byte loads zero extend.
230 We record in the following fields if a register has some leading bits
231 that are always equal to the sign bit, and what we know about the
232 nonzero bits of a register, specifically which bits are known to be
235 If an entry is zero, it means that we don't know anything special. */
237 unsigned char sign_bit_copies;
239 unsigned HOST_WIDE_INT nonzero_bits;
241 /* Record the value of the label_tick when the last truncation
242 happened. The field truncated_to_mode is only valid if
243 truncation_label == label_tick. */
245 int truncation_label;
247 /* Record the last truncation seen for this register. If truncation
248 is not a nop to this mode we might be able to save an explicit
249 truncation if we know that value already contains a truncated
252 ENUM_BITFIELD(machine_mode) truncated_to_mode : 8;
255 DEF_VEC_O(reg_stat_type);
256 DEF_VEC_ALLOC_O(reg_stat_type,heap);
258 static VEC(reg_stat_type,heap) *reg_stat;
260 /* Record the luid of the last insn that invalidated memory
261 (anything that writes memory, and subroutine calls, but not pushes). */
263 static int mem_last_set;
265 /* Record the luid of the last CALL_INSN
266 so we can tell whether a potential combination crosses any calls. */
268 static int last_call_luid;
270 /* When `subst' is called, this is the insn that is being modified
271 (by combining in a previous insn). The PATTERN of this insn
272 is still the old pattern partially modified and it should not be
273 looked at, but this may be used to examine the successors of the insn
274 to judge whether a simplification is valid. */
276 static rtx subst_insn;
278 /* This is the lowest LUID that `subst' is currently dealing with.
279 get_last_value will not return a value if the register was set at or
280 after this LUID. If not for this mechanism, we could get confused if
281 I2 or I1 in try_combine were an insn that used the old value of a register
282 to obtain a new value. In that case, we might erroneously get the
283 new value of the register when we wanted the old one. */
285 static int subst_low_luid;
287 /* This contains any hard registers that are used in newpat; reg_dead_at_p
288 must consider all these registers to be always live. */
290 static HARD_REG_SET newpat_used_regs;
292 /* This is an insn to which a LOG_LINKS entry has been added. If this
293 insn is the earlier than I2 or I3, combine should rescan starting at
296 static rtx added_links_insn;
298 /* Basic block in which we are performing combines. */
299 static basic_block this_basic_block;
300 static bool optimize_this_for_speed_p;
303 /* Length of the currently allocated uid_insn_cost array. */
305 static int max_uid_known;
307 /* The following array records the insn_rtx_cost for every insn
308 in the instruction stream. */
310 static int *uid_insn_cost;
312 /* The following array records the LOG_LINKS for every insn in the
313 instruction stream as struct insn_link pointers. */
317 struct insn_link *next;
320 static struct insn_link **uid_log_links;
322 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
323 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
325 #define FOR_EACH_LOG_LINK(L, INSN) \
326 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
328 /* Links for LOG_LINKS are allocated from this obstack. */
330 static struct obstack insn_link_obstack;
332 /* Allocate a link. */
334 static inline struct insn_link *
335 alloc_insn_link (rtx insn, struct insn_link *next)
338 = (struct insn_link *) obstack_alloc (&insn_link_obstack,
339 sizeof (struct insn_link));
345 /* Incremented for each basic block. */
347 static int label_tick;
349 /* Reset to label_tick for each extended basic block in scanning order. */
351 static int label_tick_ebb_start;
353 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
354 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
356 static enum machine_mode nonzero_bits_mode;
358 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
359 be safely used. It is zero while computing them and after combine has
360 completed. This former test prevents propagating values based on
361 previously set values, which can be incorrect if a variable is modified
364 static int nonzero_sign_valid;
367 /* Record one modification to rtl structure
368 to be undone by storing old_contents into *where. */
370 enum undo_kind { UNDO_RTX, UNDO_INT, UNDO_MODE };
376 union { rtx r; int i; enum machine_mode m; } old_contents;
377 union { rtx *r; int *i; } where;
380 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
381 num_undo says how many are currently recorded.
383 other_insn is nonzero if we have modified some other insn in the process
384 of working on subst_insn. It must be verified too. */
393 static struct undobuf undobuf;
395 /* Number of times the pseudo being substituted for
396 was found and replaced. */
398 static int n_occurrences;
400 static rtx reg_nonzero_bits_for_combine (const_rtx, enum machine_mode, const_rtx,
402 unsigned HOST_WIDE_INT,
403 unsigned HOST_WIDE_INT *);
404 static rtx reg_num_sign_bit_copies_for_combine (const_rtx, enum machine_mode, const_rtx,
406 unsigned int, unsigned int *);
407 static void do_SUBST (rtx *, rtx);
408 static void do_SUBST_INT (int *, int);
409 static void init_reg_last (void);
410 static void setup_incoming_promotions (rtx);
411 static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *);
412 static int cant_combine_insn_p (rtx);
413 static int can_combine_p (rtx, rtx, rtx, rtx, rtx, rtx, rtx *, rtx *);
414 static int combinable_i3pat (rtx, rtx *, rtx, rtx, rtx, int, int, rtx *);
415 static int contains_muldiv (rtx);
416 static rtx try_combine (rtx, rtx, rtx, rtx, int *);
417 static void undo_all (void);
418 static void undo_commit (void);
419 static rtx *find_split_point (rtx *, rtx, bool);
420 static rtx subst (rtx, rtx, rtx, int, int);
421 static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
422 static rtx simplify_if_then_else (rtx);
423 static rtx simplify_set (rtx);
424 static rtx simplify_logical (rtx);
425 static rtx expand_compound_operation (rtx);
426 static const_rtx expand_field_assignment (const_rtx);
427 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
428 rtx, unsigned HOST_WIDE_INT, int, int, int);
429 static rtx extract_left_shift (rtx, int);
430 static rtx make_compound_operation (rtx, enum rtx_code);
431 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
432 unsigned HOST_WIDE_INT *);
433 static rtx canon_reg_for_combine (rtx, rtx);
434 static rtx force_to_mode (rtx, enum machine_mode,
435 unsigned HOST_WIDE_INT, int);
436 static rtx if_then_else_cond (rtx, rtx *, rtx *);
437 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
438 static int rtx_equal_for_field_assignment_p (rtx, rtx);
439 static rtx make_field_assignment (rtx);
440 static rtx apply_distributive_law (rtx);
441 static rtx distribute_and_simplify_rtx (rtx, int);
442 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
443 unsigned HOST_WIDE_INT);
444 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
445 unsigned HOST_WIDE_INT);
446 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
447 HOST_WIDE_INT, enum machine_mode, int *);
448 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
449 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
451 static int recog_for_combine (rtx *, rtx, rtx *);
452 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
453 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
454 static void update_table_tick (rtx);
455 static void record_value_for_reg (rtx, rtx, rtx);
456 static void check_promoted_subreg (rtx, rtx);
457 static void record_dead_and_set_regs_1 (rtx, const_rtx, void *);
458 static void record_dead_and_set_regs (rtx);
459 static int get_last_value_validate (rtx *, rtx, int, int);
460 static rtx get_last_value (const_rtx);
461 static int use_crosses_set_p (const_rtx, int);
462 static void reg_dead_at_p_1 (rtx, const_rtx, void *);
463 static int reg_dead_at_p (rtx, rtx);
464 static void move_deaths (rtx, rtx, int, rtx, rtx *);
465 static int reg_bitfield_target_p (rtx, rtx);
466 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx, rtx);
467 static void distribute_links (struct insn_link *);
468 static void mark_used_regs_combine (rtx);
469 static void record_promoted_value (rtx, rtx);
470 static int unmentioned_reg_p_1 (rtx *, void *);
471 static bool unmentioned_reg_p (rtx, rtx);
472 static int record_truncated_value (rtx *, void *);
473 static void record_truncated_values (rtx *, void *);
474 static bool reg_truncated_to_mode (enum machine_mode, const_rtx);
475 static rtx gen_lowpart_or_truncate (enum machine_mode, rtx);
478 /* It is not safe to use ordinary gen_lowpart in combine.
479 See comments in gen_lowpart_for_combine. */
480 #undef RTL_HOOKS_GEN_LOWPART
481 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
483 /* Our implementation of gen_lowpart never emits a new pseudo. */
484 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
485 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
487 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
488 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
490 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
491 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
493 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
494 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
496 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
499 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
500 PATTERN can not be split. Otherwise, it returns an insn sequence.
501 This is a wrapper around split_insns which ensures that the
502 reg_stat vector is made larger if the splitter creates a new
506 combine_split_insns (rtx pattern, rtx insn)
511 ret = split_insns (pattern, insn);
512 nregs = max_reg_num ();
513 if (nregs > VEC_length (reg_stat_type, reg_stat))
514 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
518 /* This is used by find_single_use to locate an rtx in LOC that
519 contains exactly one use of DEST, which is typically either a REG
520 or CC0. It returns a pointer to the innermost rtx expression
521 containing DEST. Appearances of DEST that are being used to
522 totally replace it are not counted. */
525 find_single_use_1 (rtx dest, rtx *loc)
528 enum rtx_code code = GET_CODE (x);
546 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
547 of a REG that occupies all of the REG, the insn uses DEST if
548 it is mentioned in the destination or the source. Otherwise, we
549 need just check the source. */
550 if (GET_CODE (SET_DEST (x)) != CC0
551 && GET_CODE (SET_DEST (x)) != PC
552 && !REG_P (SET_DEST (x))
553 && ! (GET_CODE (SET_DEST (x)) == SUBREG
554 && REG_P (SUBREG_REG (SET_DEST (x)))
555 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
556 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
557 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
558 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
561 return find_single_use_1 (dest, &SET_SRC (x));
565 return find_single_use_1 (dest, &XEXP (x, 0));
571 /* If it wasn't one of the common cases above, check each expression and
572 vector of this code. Look for a unique usage of DEST. */
574 fmt = GET_RTX_FORMAT (code);
575 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
579 if (dest == XEXP (x, i)
580 || (REG_P (dest) && REG_P (XEXP (x, i))
581 && REGNO (dest) == REGNO (XEXP (x, i))))
584 this_result = find_single_use_1 (dest, &XEXP (x, i));
587 result = this_result;
588 else if (this_result)
589 /* Duplicate usage. */
592 else if (fmt[i] == 'E')
596 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
598 if (XVECEXP (x, i, j) == dest
600 && REG_P (XVECEXP (x, i, j))
601 && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
604 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
607 result = this_result;
608 else if (this_result)
618 /* See if DEST, produced in INSN, is used only a single time in the
619 sequel. If so, return a pointer to the innermost rtx expression in which
622 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
624 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
625 care about REG_DEAD notes or LOG_LINKS.
627 Otherwise, we find the single use by finding an insn that has a
628 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
629 only referenced once in that insn, we know that it must be the first
630 and last insn referencing DEST. */
633 find_single_use (rtx dest, rtx insn, rtx *ploc)
638 struct insn_link *link;
643 next = NEXT_INSN (insn);
645 || (!NONJUMP_INSN_P (next) && !JUMP_P (next)))
648 result = find_single_use_1 (dest, &PATTERN (next));
658 bb = BLOCK_FOR_INSN (insn);
659 for (next = NEXT_INSN (insn);
660 next && BLOCK_FOR_INSN (next) == bb;
661 next = NEXT_INSN (next))
662 if (INSN_P (next) && dead_or_set_p (next, dest))
664 FOR_EACH_LOG_LINK (link, next)
665 if (link->insn == insn)
670 result = find_single_use_1 (dest, &PATTERN (next));
680 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
681 insn. The substitution can be undone by undo_all. If INTO is already
682 set to NEWVAL, do not record this change. Because computing NEWVAL might
683 also call SUBST, we have to compute it before we put anything into
687 do_SUBST (rtx *into, rtx newval)
692 if (oldval == newval)
695 /* We'd like to catch as many invalid transformations here as
696 possible. Unfortunately, there are way too many mode changes
697 that are perfectly valid, so we'd waste too much effort for
698 little gain doing the checks here. Focus on catching invalid
699 transformations involving integer constants. */
700 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
701 && CONST_INT_P (newval))
703 /* Sanity check that we're replacing oldval with a CONST_INT
704 that is a valid sign-extension for the original mode. */
705 gcc_assert (INTVAL (newval)
706 == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
708 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
709 CONST_INT is not valid, because after the replacement, the
710 original mode would be gone. Unfortunately, we can't tell
711 when do_SUBST is called to replace the operand thereof, so we
712 perform this test on oldval instead, checking whether an
713 invalid replacement took place before we got here. */
714 gcc_assert (!(GET_CODE (oldval) == SUBREG
715 && CONST_INT_P (SUBREG_REG (oldval))));
716 gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
717 && CONST_INT_P (XEXP (oldval, 0))));
721 buf = undobuf.frees, undobuf.frees = buf->next;
723 buf = XNEW (struct undo);
725 buf->kind = UNDO_RTX;
727 buf->old_contents.r = oldval;
730 buf->next = undobuf.undos, undobuf.undos = buf;
733 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
735 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
736 for the value of a HOST_WIDE_INT value (including CONST_INT) is
740 do_SUBST_INT (int *into, int newval)
745 if (oldval == newval)
749 buf = undobuf.frees, undobuf.frees = buf->next;
751 buf = XNEW (struct undo);
753 buf->kind = UNDO_INT;
755 buf->old_contents.i = oldval;
758 buf->next = undobuf.undos, undobuf.undos = buf;
761 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
763 /* Similar to SUBST, but just substitute the mode. This is used when
764 changing the mode of a pseudo-register, so that any other
765 references to the entry in the regno_reg_rtx array will change as
769 do_SUBST_MODE (rtx *into, enum machine_mode newval)
772 enum machine_mode oldval = GET_MODE (*into);
774 if (oldval == newval)
778 buf = undobuf.frees, undobuf.frees = buf->next;
780 buf = XNEW (struct undo);
782 buf->kind = UNDO_MODE;
784 buf->old_contents.m = oldval;
785 adjust_reg_mode (*into, newval);
787 buf->next = undobuf.undos, undobuf.undos = buf;
790 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE(&(INTO), (NEWVAL))
792 /* Subroutine of try_combine. Determine whether the combine replacement
793 patterns NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to
794 insn_rtx_cost that the original instruction sequence I0, I1, I2, I3 and
795 undobuf.other_insn. Note that I1 and/or NEWI2PAT may be NULL_RTX.
796 NEWOTHERPAT and undobuf.other_insn may also both be NULL_RTX. This
797 function returns false, if the costs of all instructions can be
798 estimated, and the replacements are more expensive than the original
802 combine_validate_cost (rtx i0, rtx i1, rtx i2, rtx i3, rtx newpat,
803 rtx newi2pat, rtx newotherpat)
805 int i0_cost, i1_cost, i2_cost, i3_cost;
806 int new_i2_cost, new_i3_cost;
807 int old_cost, new_cost;
809 /* Lookup the original insn_rtx_costs. */
810 i2_cost = INSN_COST (i2);
811 i3_cost = INSN_COST (i3);
815 i1_cost = INSN_COST (i1);
818 i0_cost = INSN_COST (i0);
819 old_cost = (i0_cost > 0 && i1_cost > 0 && i2_cost > 0 && i3_cost > 0
820 ? i0_cost + i1_cost + i2_cost + i3_cost : 0);
824 old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0
825 ? i1_cost + i2_cost + i3_cost : 0);
831 old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
832 i1_cost = i0_cost = 0;
835 /* Calculate the replacement insn_rtx_costs. */
836 new_i3_cost = insn_rtx_cost (newpat, optimize_this_for_speed_p);
839 new_i2_cost = insn_rtx_cost (newi2pat, optimize_this_for_speed_p);
840 new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
841 ? new_i2_cost + new_i3_cost : 0;
845 new_cost = new_i3_cost;
849 if (undobuf.other_insn)
851 int old_other_cost, new_other_cost;
853 old_other_cost = INSN_COST (undobuf.other_insn);
854 new_other_cost = insn_rtx_cost (newotherpat, optimize_this_for_speed_p);
855 if (old_other_cost > 0 && new_other_cost > 0)
857 old_cost += old_other_cost;
858 new_cost += new_other_cost;
864 /* Disallow this recombination if both new_cost and old_cost are
865 greater than zero, and new_cost is greater than old cost. */
867 && new_cost > old_cost)
874 "rejecting combination of insns %d, %d, %d and %d\n",
875 INSN_UID (i0), INSN_UID (i1), INSN_UID (i2),
877 fprintf (dump_file, "original costs %d + %d + %d + %d = %d\n",
878 i0_cost, i1_cost, i2_cost, i3_cost, old_cost);
883 "rejecting combination of insns %d, %d and %d\n",
884 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
885 fprintf (dump_file, "original costs %d + %d + %d = %d\n",
886 i1_cost, i2_cost, i3_cost, old_cost);
891 "rejecting combination of insns %d and %d\n",
892 INSN_UID (i2), INSN_UID (i3));
893 fprintf (dump_file, "original costs %d + %d = %d\n",
894 i2_cost, i3_cost, old_cost);
899 fprintf (dump_file, "replacement costs %d + %d = %d\n",
900 new_i2_cost, new_i3_cost, new_cost);
903 fprintf (dump_file, "replacement cost %d\n", new_cost);
909 /* Update the uid_insn_cost array with the replacement costs. */
910 INSN_COST (i2) = new_i2_cost;
911 INSN_COST (i3) = new_i3_cost;
919 /* Delete any insns that copy a register to itself. */
922 delete_noop_moves (void)
929 for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
931 next = NEXT_INSN (insn);
932 if (INSN_P (insn) && noop_move_p (insn))
935 fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn));
937 delete_insn_and_edges (insn);
944 /* Fill in log links field for all insns. */
947 create_log_links (void)
951 df_ref *def_vec, *use_vec;
953 next_use = XCNEWVEC (rtx, max_reg_num ());
955 /* Pass through each block from the end, recording the uses of each
956 register and establishing log links when def is encountered.
957 Note that we do not clear next_use array in order to save time,
958 so we have to test whether the use is in the same basic block as def.
960 There are a few cases below when we do not consider the definition or
961 usage -- these are taken from original flow.c did. Don't ask me why it is
962 done this way; I don't know and if it works, I don't want to know. */
966 FOR_BB_INSNS_REVERSE (bb, insn)
968 if (!NONDEBUG_INSN_P (insn))
971 /* Log links are created only once. */
972 gcc_assert (!LOG_LINKS (insn));
974 for (def_vec = DF_INSN_DEFS (insn); *def_vec; def_vec++)
976 df_ref def = *def_vec;
977 int regno = DF_REF_REGNO (def);
980 if (!next_use[regno])
983 /* Do not consider if it is pre/post modification in MEM. */
984 if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY)
987 /* Do not make the log link for frame pointer. */
988 if ((regno == FRAME_POINTER_REGNUM
989 && (! reload_completed || frame_pointer_needed))
990 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
991 || (regno == HARD_FRAME_POINTER_REGNUM
992 && (! reload_completed || frame_pointer_needed))
994 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
995 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
1000 use_insn = next_use[regno];
1001 if (BLOCK_FOR_INSN (use_insn) == bb)
1005 We don't build a LOG_LINK for hard registers contained
1006 in ASM_OPERANDs. If these registers get replaced,
1007 we might wind up changing the semantics of the insn,
1008 even if reload can make what appear to be valid
1009 assignments later. */
1010 if (regno >= FIRST_PSEUDO_REGISTER
1011 || asm_noperands (PATTERN (use_insn)) < 0)
1013 /* Don't add duplicate links between instructions. */
1014 struct insn_link *links;
1015 FOR_EACH_LOG_LINK (links, use_insn)
1016 if (insn == links->insn)
1020 LOG_LINKS (use_insn)
1021 = alloc_insn_link (insn, LOG_LINKS (use_insn));
1024 next_use[regno] = NULL_RTX;
1027 for (use_vec = DF_INSN_USES (insn); *use_vec; use_vec++)
1029 df_ref use = *use_vec;
1030 int regno = DF_REF_REGNO (use);
1032 /* Do not consider the usage of the stack pointer
1033 by function call. */
1034 if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE)
1037 next_use[regno] = insn;
1045 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1046 true if we found a LOG_LINK that proves that A feeds B. This only works
1047 if there are no instructions between A and B which could have a link
1048 depending on A, since in that case we would not record a link for B.
1049 We also check the implicit dependency created by a cc0 setter/user
1053 insn_a_feeds_b (rtx a, rtx b)
1055 struct insn_link *links;
1056 FOR_EACH_LOG_LINK (links, b)
1057 if (links->insn == a)
1066 /* Main entry point for combiner. F is the first insn of the function.
1067 NREGS is the first unused pseudo-reg number.
1069 Return nonzero if the combiner has turned an indirect jump
1070 instruction into a direct jump. */
1072 combine_instructions (rtx f, unsigned int nregs)
1078 struct insn_link *links, *nextlinks;
1080 basic_block last_bb;
1082 int new_direct_jump_p = 0;
1084 for (first = f; first && !INSN_P (first); )
1085 first = NEXT_INSN (first);
1089 combine_attempts = 0;
1092 combine_successes = 0;
1094 rtl_hooks = combine_rtl_hooks;
1096 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
1098 init_recog_no_volatile ();
1100 /* Allocate array for insn info. */
1101 max_uid_known = get_max_uid ();
1102 uid_log_links = XCNEWVEC (struct insn_link *, max_uid_known + 1);
1103 uid_insn_cost = XCNEWVEC (int, max_uid_known + 1);
1104 gcc_obstack_init (&insn_link_obstack);
1106 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
1108 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1109 problems when, for example, we have j <<= 1 in a loop. */
1111 nonzero_sign_valid = 0;
1112 label_tick = label_tick_ebb_start = 1;
1114 /* Scan all SETs and see if we can deduce anything about what
1115 bits are known to be zero for some registers and how many copies
1116 of the sign bit are known to exist for those registers.
1118 Also set any known values so that we can use it while searching
1119 for what bits are known to be set. */
1121 setup_incoming_promotions (first);
1122 /* Allow the entry block and the first block to fall into the same EBB.
1123 Conceptually the incoming promotions are assigned to the entry block. */
1124 last_bb = ENTRY_BLOCK_PTR;
1126 create_log_links ();
1127 FOR_EACH_BB (this_basic_block)
1129 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1134 if (!single_pred_p (this_basic_block)
1135 || single_pred (this_basic_block) != last_bb)
1136 label_tick_ebb_start = label_tick;
1137 last_bb = this_basic_block;
1139 FOR_BB_INSNS (this_basic_block, insn)
1140 if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
1146 subst_low_luid = DF_INSN_LUID (insn);
1149 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
1151 record_dead_and_set_regs (insn);
1154 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
1155 if (REG_NOTE_KIND (links) == REG_INC)
1156 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
1160 /* Record the current insn_rtx_cost of this instruction. */
1161 if (NONJUMP_INSN_P (insn))
1162 INSN_COST (insn) = insn_rtx_cost (PATTERN (insn),
1163 optimize_this_for_speed_p);
1165 fprintf(dump_file, "insn_cost %d: %d\n",
1166 INSN_UID (insn), INSN_COST (insn));
1170 nonzero_sign_valid = 1;
1172 /* Now scan all the insns in forward order. */
1173 label_tick = label_tick_ebb_start = 1;
1175 setup_incoming_promotions (first);
1176 last_bb = ENTRY_BLOCK_PTR;
1178 FOR_EACH_BB (this_basic_block)
1180 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1185 if (!single_pred_p (this_basic_block)
1186 || single_pred (this_basic_block) != last_bb)
1187 label_tick_ebb_start = label_tick;
1188 last_bb = this_basic_block;
1190 rtl_profile_for_bb (this_basic_block);
1191 for (insn = BB_HEAD (this_basic_block);
1192 insn != NEXT_INSN (BB_END (this_basic_block));
1193 insn = next ? next : NEXT_INSN (insn))
1196 if (NONDEBUG_INSN_P (insn))
1198 /* See if we know about function return values before this
1199 insn based upon SUBREG flags. */
1200 check_promoted_subreg (insn, PATTERN (insn));
1202 /* See if we can find hardregs and subreg of pseudos in
1203 narrower modes. This could help turning TRUNCATEs
1205 note_uses (&PATTERN (insn), record_truncated_values, NULL);
1207 /* Try this insn with each insn it links back to. */
1209 FOR_EACH_LOG_LINK (links, insn)
1210 if ((next = try_combine (insn, links->insn, NULL_RTX,
1211 NULL_RTX, &new_direct_jump_p)) != 0)
1214 /* Try each sequence of three linked insns ending with this one. */
1216 FOR_EACH_LOG_LINK (links, insn)
1218 rtx link = links->insn;
1220 /* If the linked insn has been replaced by a note, then there
1221 is no point in pursuing this chain any further. */
1225 FOR_EACH_LOG_LINK (nextlinks, link)
1226 if ((next = try_combine (insn, link, nextlinks->insn,
1228 &new_direct_jump_p)) != 0)
1233 /* Try to combine a jump insn that uses CC0
1234 with a preceding insn that sets CC0, and maybe with its
1235 logical predecessor as well.
1236 This is how we make decrement-and-branch insns.
1237 We need this special code because data flow connections
1238 via CC0 do not get entered in LOG_LINKS. */
1241 && (prev = prev_nonnote_insn (insn)) != 0
1242 && NONJUMP_INSN_P (prev)
1243 && sets_cc0_p (PATTERN (prev)))
1245 if ((next = try_combine (insn, prev, NULL_RTX, NULL_RTX,
1246 &new_direct_jump_p)) != 0)
1249 FOR_EACH_LOG_LINK (nextlinks, prev)
1250 if ((next = try_combine (insn, prev, nextlinks->insn,
1252 &new_direct_jump_p)) != 0)
1256 /* Do the same for an insn that explicitly references CC0. */
1257 if (NONJUMP_INSN_P (insn)
1258 && (prev = prev_nonnote_insn (insn)) != 0
1259 && NONJUMP_INSN_P (prev)
1260 && sets_cc0_p (PATTERN (prev))
1261 && GET_CODE (PATTERN (insn)) == SET
1262 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
1264 if ((next = try_combine (insn, prev, NULL_RTX, NULL_RTX,
1265 &new_direct_jump_p)) != 0)
1268 FOR_EACH_LOG_LINK (nextlinks, prev)
1269 if ((next = try_combine (insn, prev, nextlinks->insn,
1271 &new_direct_jump_p)) != 0)
1275 /* Finally, see if any of the insns that this insn links to
1276 explicitly references CC0. If so, try this insn, that insn,
1277 and its predecessor if it sets CC0. */
1278 FOR_EACH_LOG_LINK (links, insn)
1279 if (NONJUMP_INSN_P (links->insn)
1280 && GET_CODE (PATTERN (links->insn)) == SET
1281 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (links->insn)))
1282 && (prev = prev_nonnote_insn (links->insn)) != 0
1283 && NONJUMP_INSN_P (prev)
1284 && sets_cc0_p (PATTERN (prev))
1285 && (next = try_combine (insn, links->insn,
1287 &new_direct_jump_p)) != 0)
1291 /* Try combining an insn with two different insns whose results it
1293 FOR_EACH_LOG_LINK (links, insn)
1294 for (nextlinks = links->next; nextlinks;
1295 nextlinks = nextlinks->next)
1296 if ((next = try_combine (insn, links->insn,
1297 nextlinks->insn, NULL_RTX,
1298 &new_direct_jump_p)) != 0)
1301 /* Try four-instruction combinations. */
1302 FOR_EACH_LOG_LINK (links, insn)
1304 struct insn_link *next1;
1305 rtx link = links->insn;
1307 /* If the linked insn has been replaced by a note, then there
1308 is no point in pursuing this chain any further. */
1312 FOR_EACH_LOG_LINK (next1, link)
1314 rtx link1 = next1->insn;
1317 /* I0 -> I1 -> I2 -> I3. */
1318 FOR_EACH_LOG_LINK (nextlinks, link1)
1319 if ((next = try_combine (insn, link, link1,
1321 &new_direct_jump_p)) != 0)
1323 /* I0, I1 -> I2, I2 -> I3. */
1324 for (nextlinks = next1->next; nextlinks;
1325 nextlinks = nextlinks->next)
1326 if ((next = try_combine (insn, link, link1,
1328 &new_direct_jump_p)) != 0)
1332 for (next1 = links->next; next1; next1 = next1->next)
1334 rtx link1 = next1->insn;
1337 /* I0 -> I2; I1, I2 -> I3. */
1338 FOR_EACH_LOG_LINK (nextlinks, link)
1339 if ((next = try_combine (insn, link, link1,
1341 &new_direct_jump_p)) != 0)
1343 /* I0 -> I1; I1, I2 -> I3. */
1344 FOR_EACH_LOG_LINK (nextlinks, link1)
1345 if ((next = try_combine (insn, link, link1,
1347 &new_direct_jump_p)) != 0)
1352 /* Try this insn with each REG_EQUAL note it links back to. */
1353 FOR_EACH_LOG_LINK (links, insn)
1356 rtx temp = links->insn;
1357 if ((set = single_set (temp)) != 0
1358 && (note = find_reg_equal_equiv_note (temp)) != 0
1359 && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
1360 /* Avoid using a register that may already been marked
1361 dead by an earlier instruction. */
1362 && ! unmentioned_reg_p (note, SET_SRC (set))
1363 && (GET_MODE (note) == VOIDmode
1364 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
1365 : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
1367 /* Temporarily replace the set's source with the
1368 contents of the REG_EQUAL note. The insn will
1369 be deleted or recognized by try_combine. */
1370 rtx orig = SET_SRC (set);
1371 SET_SRC (set) = note;
1373 i2mod_old_rhs = copy_rtx (orig);
1374 i2mod_new_rhs = copy_rtx (note);
1375 next = try_combine (insn, i2mod, NULL_RTX, NULL_RTX,
1376 &new_direct_jump_p);
1380 SET_SRC (set) = orig;
1385 record_dead_and_set_regs (insn);
1393 default_rtl_profile ();
1395 new_direct_jump_p |= purge_all_dead_edges ();
1396 delete_noop_moves ();
1399 obstack_free (&insn_link_obstack, NULL);
1400 free (uid_log_links);
1401 free (uid_insn_cost);
1402 VEC_free (reg_stat_type, heap, reg_stat);
1405 struct undo *undo, *next;
1406 for (undo = undobuf.frees; undo; undo = next)
1414 total_attempts += combine_attempts;
1415 total_merges += combine_merges;
1416 total_extras += combine_extras;
1417 total_successes += combine_successes;
1419 nonzero_sign_valid = 0;
1420 rtl_hooks = general_rtl_hooks;
1422 /* Make recognizer allow volatile MEMs again. */
1425 return new_direct_jump_p;
1428 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1431 init_reg_last (void)
1436 FOR_EACH_VEC_ELT (reg_stat_type, reg_stat, i, p)
1437 memset (p, 0, offsetof (reg_stat_type, sign_bit_copies));
1440 /* Set up any promoted values for incoming argument registers. */
1443 setup_incoming_promotions (rtx first)
1446 bool strictly_local = false;
1448 for (arg = DECL_ARGUMENTS (current_function_decl); arg;
1449 arg = DECL_CHAIN (arg))
1451 rtx x, reg = DECL_INCOMING_RTL (arg);
1453 enum machine_mode mode1, mode2, mode3, mode4;
1455 /* Only continue if the incoming argument is in a register. */
1459 /* Determine, if possible, whether all call sites of the current
1460 function lie within the current compilation unit. (This does
1461 take into account the exporting of a function via taking its
1462 address, and so forth.) */
1463 strictly_local = cgraph_local_info (current_function_decl)->local;
1465 /* The mode and signedness of the argument before any promotions happen
1466 (equal to the mode of the pseudo holding it at that stage). */
1467 mode1 = TYPE_MODE (TREE_TYPE (arg));
1468 uns1 = TYPE_UNSIGNED (TREE_TYPE (arg));
1470 /* The mode and signedness of the argument after any source language and
1471 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1472 mode2 = TYPE_MODE (DECL_ARG_TYPE (arg));
1473 uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg));
1475 /* The mode and signedness of the argument as it is actually passed,
1476 after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */
1477 mode3 = promote_function_mode (DECL_ARG_TYPE (arg), mode2, &uns3,
1478 TREE_TYPE (cfun->decl), 0);
1480 /* The mode of the register in which the argument is being passed. */
1481 mode4 = GET_MODE (reg);
1483 /* Eliminate sign extensions in the callee when:
1484 (a) A mode promotion has occurred; */
1487 /* (b) The mode of the register is the same as the mode of
1488 the argument as it is passed; */
1491 /* (c) There's no language level extension; */
1494 /* (c.1) All callers are from the current compilation unit. If that's
1495 the case we don't have to rely on an ABI, we only have to know
1496 what we're generating right now, and we know that we will do the
1497 mode1 to mode2 promotion with the given sign. */
1498 else if (!strictly_local)
1500 /* (c.2) The combination of the two promotions is useful. This is
1501 true when the signs match, or if the first promotion is unsigned.
1502 In the later case, (sign_extend (zero_extend x)) is the same as
1503 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1509 /* Record that the value was promoted from mode1 to mode3,
1510 so that any sign extension at the head of the current
1511 function may be eliminated. */
1512 x = gen_rtx_CLOBBER (mode1, const0_rtx);
1513 x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x);
1514 record_value_for_reg (reg, first, x);
1518 /* Called via note_stores. If X is a pseudo that is narrower than
1519 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1521 If we are setting only a portion of X and we can't figure out what
1522 portion, assume all bits will be used since we don't know what will
1525 Similarly, set how many bits of X are known to be copies of the sign bit
1526 at all locations in the function. This is the smallest number implied
1530 set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data)
1532 rtx insn = (rtx) data;
1536 && REGNO (x) >= FIRST_PSEUDO_REGISTER
1537 /* If this register is undefined at the start of the file, we can't
1538 say what its contents were. */
1539 && ! REGNO_REG_SET_P
1540 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x))
1541 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
1543 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
1545 if (set == 0 || GET_CODE (set) == CLOBBER)
1547 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1548 rsp->sign_bit_copies = 1;
1552 /* If this register is being initialized using itself, and the
1553 register is uninitialized in this basic block, and there are
1554 no LOG_LINKS which set the register, then part of the
1555 register is uninitialized. In that case we can't assume
1556 anything about the number of nonzero bits.
1558 ??? We could do better if we checked this in
1559 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1560 could avoid making assumptions about the insn which initially
1561 sets the register, while still using the information in other
1562 insns. We would have to be careful to check every insn
1563 involved in the combination. */
1566 && reg_referenced_p (x, PATTERN (insn))
1567 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)),
1570 struct insn_link *link;
1572 FOR_EACH_LOG_LINK (link, insn)
1573 if (dead_or_set_p (link->insn, x))
1577 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1578 rsp->sign_bit_copies = 1;
1583 /* If this is a complex assignment, see if we can convert it into a
1584 simple assignment. */
1585 set = expand_field_assignment (set);
1587 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1588 set what we know about X. */
1590 if (SET_DEST (set) == x
1591 || (GET_CODE (SET_DEST (set)) == SUBREG
1592 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
1593 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
1594 && SUBREG_REG (SET_DEST (set)) == x))
1596 rtx src = SET_SRC (set);
1598 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1599 /* If X is narrower than a word and SRC is a non-negative
1600 constant that would appear negative in the mode of X,
1601 sign-extend it for use in reg_stat[].nonzero_bits because some
1602 machines (maybe most) will actually do the sign-extension
1603 and this is the conservative approach.
1605 ??? For 2.5, try to tighten up the MD files in this regard
1606 instead of this kludge. */
1608 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
1609 && CONST_INT_P (src)
1611 && 0 != (UINTVAL (src)
1612 & ((unsigned HOST_WIDE_INT) 1
1613 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
1614 src = GEN_INT (UINTVAL (src)
1615 | ((unsigned HOST_WIDE_INT) (-1)
1616 << GET_MODE_BITSIZE (GET_MODE (x))));
1619 /* Don't call nonzero_bits if it cannot change anything. */
1620 if (rsp->nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1621 rsp->nonzero_bits |= nonzero_bits (src, nonzero_bits_mode);
1622 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1623 if (rsp->sign_bit_copies == 0
1624 || rsp->sign_bit_copies > num)
1625 rsp->sign_bit_copies = num;
1629 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1630 rsp->sign_bit_copies = 1;
1635 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1636 optionally insns that were previously combined into I3 or that will be
1637 combined into the merger of INSN and I3. The order is PRED, PRED2,
1638 INSN, SUCC, SUCC2, I3.
1640 Return 0 if the combination is not allowed for any reason.
1642 If the combination is allowed, *PDEST will be set to the single
1643 destination of INSN and *PSRC to the single source, and this function
1647 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED,
1648 rtx pred2 ATTRIBUTE_UNUSED, rtx succ, rtx succ2,
1649 rtx *pdest, rtx *psrc)
1658 bool all_adjacent = true;
1664 if (next_active_insn (succ2) != i3)
1665 all_adjacent = false;
1666 if (next_active_insn (succ) != succ2)
1667 all_adjacent = false;
1669 else if (next_active_insn (succ) != i3)
1670 all_adjacent = false;
1671 if (next_active_insn (insn) != succ)
1672 all_adjacent = false;
1674 else if (next_active_insn (insn) != i3)
1675 all_adjacent = false;
1677 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1678 or a PARALLEL consisting of such a SET and CLOBBERs.
1680 If INSN has CLOBBER parallel parts, ignore them for our processing.
1681 By definition, these happen during the execution of the insn. When it
1682 is merged with another insn, all bets are off. If they are, in fact,
1683 needed and aren't also supplied in I3, they may be added by
1684 recog_for_combine. Otherwise, it won't match.
1686 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1689 Get the source and destination of INSN. If more than one, can't
1692 if (GET_CODE (PATTERN (insn)) == SET)
1693 set = PATTERN (insn);
1694 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1695 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1697 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1699 rtx elt = XVECEXP (PATTERN (insn), 0, i);
1701 switch (GET_CODE (elt))
1703 /* This is important to combine floating point insns
1704 for the SH4 port. */
1706 /* Combining an isolated USE doesn't make sense.
1707 We depend here on combinable_i3pat to reject them. */
1708 /* The code below this loop only verifies that the inputs of
1709 the SET in INSN do not change. We call reg_set_between_p
1710 to verify that the REG in the USE does not change between
1712 If the USE in INSN was for a pseudo register, the matching
1713 insn pattern will likely match any register; combining this
1714 with any other USE would only be safe if we knew that the
1715 used registers have identical values, or if there was
1716 something to tell them apart, e.g. different modes. For
1717 now, we forgo such complicated tests and simply disallow
1718 combining of USES of pseudo registers with any other USE. */
1719 if (REG_P (XEXP (elt, 0))
1720 && GET_CODE (PATTERN (i3)) == PARALLEL)
1722 rtx i3pat = PATTERN (i3);
1723 int i = XVECLEN (i3pat, 0) - 1;
1724 unsigned int regno = REGNO (XEXP (elt, 0));
1728 rtx i3elt = XVECEXP (i3pat, 0, i);
1730 if (GET_CODE (i3elt) == USE
1731 && REG_P (XEXP (i3elt, 0))
1732 && (REGNO (XEXP (i3elt, 0)) == regno
1733 ? reg_set_between_p (XEXP (elt, 0),
1734 PREV_INSN (insn), i3)
1735 : regno >= FIRST_PSEUDO_REGISTER))
1742 /* We can ignore CLOBBERs. */
1747 /* Ignore SETs whose result isn't used but not those that
1748 have side-effects. */
1749 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1750 && insn_nothrow_p (insn)
1751 && !side_effects_p (elt))
1754 /* If we have already found a SET, this is a second one and
1755 so we cannot combine with this insn. */
1763 /* Anything else means we can't combine. */
1769 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1770 so don't do anything with it. */
1771 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1780 set = expand_field_assignment (set);
1781 src = SET_SRC (set), dest = SET_DEST (set);
1783 /* Don't eliminate a store in the stack pointer. */
1784 if (dest == stack_pointer_rtx
1785 /* Don't combine with an insn that sets a register to itself if it has
1786 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1787 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1788 /* Can't merge an ASM_OPERANDS. */
1789 || GET_CODE (src) == ASM_OPERANDS
1790 /* Can't merge a function call. */
1791 || GET_CODE (src) == CALL
1792 /* Don't eliminate a function call argument. */
1794 && (find_reg_fusage (i3, USE, dest)
1796 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1797 && global_regs[REGNO (dest)])))
1798 /* Don't substitute into an incremented register. */
1799 || FIND_REG_INC_NOTE (i3, dest)
1800 || (succ && FIND_REG_INC_NOTE (succ, dest))
1801 || (succ2 && FIND_REG_INC_NOTE (succ2, dest))
1802 /* Don't substitute into a non-local goto, this confuses CFG. */
1803 || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1804 /* Make sure that DEST is not used after SUCC but before I3. */
1807 && (reg_used_between_p (dest, succ2, i3)
1808 || reg_used_between_p (dest, succ, succ2)))
1809 || (!succ2 && succ && reg_used_between_p (dest, succ, i3))))
1810 /* Make sure that the value that is to be substituted for the register
1811 does not use any registers whose values alter in between. However,
1812 If the insns are adjacent, a use can't cross a set even though we
1813 think it might (this can happen for a sequence of insns each setting
1814 the same destination; last_set of that register might point to
1815 a NOTE). If INSN has a REG_EQUIV note, the register is always
1816 equivalent to the memory so the substitution is valid even if there
1817 are intervening stores. Also, don't move a volatile asm or
1818 UNSPEC_VOLATILE across any other insns. */
1821 || ! find_reg_note (insn, REG_EQUIV, src))
1822 && use_crosses_set_p (src, DF_INSN_LUID (insn)))
1823 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1824 || GET_CODE (src) == UNSPEC_VOLATILE))
1825 /* Don't combine across a CALL_INSN, because that would possibly
1826 change whether the life span of some REGs crosses calls or not,
1827 and it is a pain to update that information.
1828 Exception: if source is a constant, moving it later can't hurt.
1829 Accept that as a special case. */
1830 || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src)))
1833 /* DEST must either be a REG or CC0. */
1836 /* If register alignment is being enforced for multi-word items in all
1837 cases except for parameters, it is possible to have a register copy
1838 insn referencing a hard register that is not allowed to contain the
1839 mode being copied and which would not be valid as an operand of most
1840 insns. Eliminate this problem by not combining with such an insn.
1842 Also, on some machines we don't want to extend the life of a hard
1846 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1847 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1848 /* Don't extend the life of a hard register unless it is
1849 user variable (if we have few registers) or it can't
1850 fit into the desired register (meaning something special
1852 Also avoid substituting a return register into I3, because
1853 reload can't handle a conflict with constraints of other
1855 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1856 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1859 else if (GET_CODE (dest) != CC0)
1863 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1864 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1865 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1867 /* Don't substitute for a register intended as a clobberable
1869 rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1870 if (rtx_equal_p (reg, dest))
1873 /* If the clobber represents an earlyclobber operand, we must not
1874 substitute an expression containing the clobbered register.
1875 As we do not analyze the constraint strings here, we have to
1876 make the conservative assumption. However, if the register is
1877 a fixed hard reg, the clobber cannot represent any operand;
1878 we leave it up to the machine description to either accept or
1879 reject use-and-clobber patterns. */
1881 || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1882 || !fixed_regs[REGNO (reg)])
1883 if (reg_overlap_mentioned_p (reg, src))
1887 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1888 or not), reject, unless nothing volatile comes between it and I3 */
1890 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1892 /* Make sure neither succ nor succ2 contains a volatile reference. */
1893 if (succ2 != 0 && volatile_refs_p (PATTERN (succ2)))
1895 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1897 /* We'll check insns between INSN and I3 below. */
1900 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1901 to be an explicit register variable, and was chosen for a reason. */
1903 if (GET_CODE (src) == ASM_OPERANDS
1904 && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1907 /* If there are any volatile insns between INSN and I3, reject, because
1908 they might affect machine state. */
1910 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1911 if (INSN_P (p) && p != succ && p != succ2 && volatile_insn_p (PATTERN (p)))
1914 /* If INSN contains an autoincrement or autodecrement, make sure that
1915 register is not used between there and I3, and not already used in
1916 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1917 Also insist that I3 not be a jump; if it were one
1918 and the incremented register were spilled, we would lose. */
1921 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1922 if (REG_NOTE_KIND (link) == REG_INC
1924 || reg_used_between_p (XEXP (link, 0), insn, i3)
1925 || (pred != NULL_RTX
1926 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1927 || (pred2 != NULL_RTX
1928 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred2)))
1929 || (succ != NULL_RTX
1930 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1931 || (succ2 != NULL_RTX
1932 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ2)))
1933 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1938 /* Don't combine an insn that follows a CC0-setting insn.
1939 An insn that uses CC0 must not be separated from the one that sets it.
1940 We do, however, allow I2 to follow a CC0-setting insn if that insn
1941 is passed as I1; in that case it will be deleted also.
1942 We also allow combining in this case if all the insns are adjacent
1943 because that would leave the two CC0 insns adjacent as well.
1944 It would be more logical to test whether CC0 occurs inside I1 or I2,
1945 but that would be much slower, and this ought to be equivalent. */
1947 p = prev_nonnote_insn (insn);
1948 if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
1953 /* If we get here, we have passed all the tests and the combination is
1962 /* LOC is the location within I3 that contains its pattern or the component
1963 of a PARALLEL of the pattern. We validate that it is valid for combining.
1965 One problem is if I3 modifies its output, as opposed to replacing it
1966 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
1967 doing so would produce an insn that is not equivalent to the original insns.
1971 (set (reg:DI 101) (reg:DI 100))
1972 (set (subreg:SI (reg:DI 101) 0) <foo>)
1974 This is NOT equivalent to:
1976 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1977 (set (reg:DI 101) (reg:DI 100))])
1979 Not only does this modify 100 (in which case it might still be valid
1980 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1982 We can also run into a problem if I2 sets a register that I1
1983 uses and I1 gets directly substituted into I3 (not via I2). In that
1984 case, we would be getting the wrong value of I2DEST into I3, so we
1985 must reject the combination. This case occurs when I2 and I1 both
1986 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1987 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1988 of a SET must prevent combination from occurring. The same situation
1989 can occur for I0, in which case I0_NOT_IN_SRC is set.
1991 Before doing the above check, we first try to expand a field assignment
1992 into a set of logical operations.
1994 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1995 we place a register that is both set and used within I3. If more than one
1996 such register is detected, we fail.
1998 Return 1 if the combination is valid, zero otherwise. */
2001 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest, rtx i0dest,
2002 int i1_not_in_src, int i0_not_in_src, rtx *pi3dest_killed)
2006 if (GET_CODE (x) == SET)
2009 rtx dest = SET_DEST (set);
2010 rtx src = SET_SRC (set);
2011 rtx inner_dest = dest;
2014 while (GET_CODE (inner_dest) == STRICT_LOW_PART
2015 || GET_CODE (inner_dest) == SUBREG
2016 || GET_CODE (inner_dest) == ZERO_EXTRACT)
2017 inner_dest = XEXP (inner_dest, 0);
2019 /* Check for the case where I3 modifies its output, as discussed
2020 above. We don't want to prevent pseudos from being combined
2021 into the address of a MEM, so only prevent the combination if
2022 i1 or i2 set the same MEM. */
2023 if ((inner_dest != dest &&
2024 (!MEM_P (inner_dest)
2025 || rtx_equal_p (i2dest, inner_dest)
2026 || (i1dest && rtx_equal_p (i1dest, inner_dest))
2027 || (i0dest && rtx_equal_p (i0dest, inner_dest)))
2028 && (reg_overlap_mentioned_p (i2dest, inner_dest)
2029 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))
2030 || (i0dest && reg_overlap_mentioned_p (i0dest, inner_dest))))
2032 /* This is the same test done in can_combine_p except we can't test
2033 all_adjacent; we don't have to, since this instruction will stay
2034 in place, thus we are not considering increasing the lifetime of
2037 Also, if this insn sets a function argument, combining it with
2038 something that might need a spill could clobber a previous
2039 function argument; the all_adjacent test in can_combine_p also
2040 checks this; here, we do a more specific test for this case. */
2042 || (REG_P (inner_dest)
2043 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
2044 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
2045 GET_MODE (inner_dest))))
2046 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src))
2047 || (i0_not_in_src && reg_overlap_mentioned_p (i0dest, src)))
2050 /* If DEST is used in I3, it is being killed in this insn, so
2051 record that for later. We have to consider paradoxical
2052 subregs here, since they kill the whole register, but we
2053 ignore partial subregs, STRICT_LOW_PART, etc.
2054 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2055 STACK_POINTER_REGNUM, since these are always considered to be
2056 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2058 if (GET_CODE (subdest) == SUBREG
2059 && (GET_MODE_SIZE (GET_MODE (subdest))
2060 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
2061 subdest = SUBREG_REG (subdest);
2064 && reg_referenced_p (subdest, PATTERN (i3))
2065 && REGNO (subdest) != FRAME_POINTER_REGNUM
2066 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2067 && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
2069 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2070 && (REGNO (subdest) != ARG_POINTER_REGNUM
2071 || ! fixed_regs [REGNO (subdest)])
2073 && REGNO (subdest) != STACK_POINTER_REGNUM)
2075 if (*pi3dest_killed)
2078 *pi3dest_killed = subdest;
2082 else if (GET_CODE (x) == PARALLEL)
2086 for (i = 0; i < XVECLEN (x, 0); i++)
2087 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest, i0dest,
2088 i1_not_in_src, i0_not_in_src, pi3dest_killed))
2095 /* Return 1 if X is an arithmetic expression that contains a multiplication
2096 and division. We don't count multiplications by powers of two here. */
2099 contains_muldiv (rtx x)
2101 switch (GET_CODE (x))
2103 case MOD: case DIV: case UMOD: case UDIV:
2107 return ! (CONST_INT_P (XEXP (x, 1))
2108 && exact_log2 (UINTVAL (XEXP (x, 1))) >= 0);
2111 return contains_muldiv (XEXP (x, 0))
2112 || contains_muldiv (XEXP (x, 1));
2115 return contains_muldiv (XEXP (x, 0));
2121 /* Determine whether INSN can be used in a combination. Return nonzero if
2122 not. This is used in try_combine to detect early some cases where we
2123 can't perform combinations. */
2126 cant_combine_insn_p (rtx insn)
2131 /* If this isn't really an insn, we can't do anything.
2132 This can occur when flow deletes an insn that it has merged into an
2133 auto-increment address. */
2134 if (! INSN_P (insn))
2137 /* Never combine loads and stores involving hard regs that are likely
2138 to be spilled. The register allocator can usually handle such
2139 reg-reg moves by tying. If we allow the combiner to make
2140 substitutions of likely-spilled regs, reload might die.
2141 As an exception, we allow combinations involving fixed regs; these are
2142 not available to the register allocator so there's no risk involved. */
2144 set = single_set (insn);
2147 src = SET_SRC (set);
2148 dest = SET_DEST (set);
2149 if (GET_CODE (src) == SUBREG)
2150 src = SUBREG_REG (src);
2151 if (GET_CODE (dest) == SUBREG)
2152 dest = SUBREG_REG (dest);
2153 if (REG_P (src) && REG_P (dest)
2154 && ((HARD_REGISTER_P (src)
2155 && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (src))
2156 && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src))))
2157 || (HARD_REGISTER_P (dest)
2158 && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (dest))
2159 && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest))))))
2165 struct likely_spilled_retval_info
2167 unsigned regno, nregs;
2171 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2172 hard registers that are known to be written to / clobbered in full. */
2174 likely_spilled_retval_1 (rtx x, const_rtx set, void *data)
2176 struct likely_spilled_retval_info *const info =
2177 (struct likely_spilled_retval_info *) data;
2178 unsigned regno, nregs;
2181 if (!REG_P (XEXP (set, 0)))
2184 if (regno >= info->regno + info->nregs)
2186 nregs = hard_regno_nregs[regno][GET_MODE (x)];
2187 if (regno + nregs <= info->regno)
2189 new_mask = (2U << (nregs - 1)) - 1;
2190 if (regno < info->regno)
2191 new_mask >>= info->regno - regno;
2193 new_mask <<= regno - info->regno;
2194 info->mask &= ~new_mask;
2197 /* Return nonzero iff part of the return value is live during INSN, and
2198 it is likely spilled. This can happen when more than one insn is needed
2199 to copy the return value, e.g. when we consider to combine into the
2200 second copy insn for a complex value. */
2203 likely_spilled_retval_p (rtx insn)
2205 rtx use = BB_END (this_basic_block);
2207 unsigned regno, nregs;
2208 /* We assume here that no machine mode needs more than
2209 32 hard registers when the value overlaps with a register
2210 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2212 struct likely_spilled_retval_info info;
2214 if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
2216 reg = XEXP (PATTERN (use), 0);
2217 if (!REG_P (reg) || !targetm.calls.function_value_regno_p (REGNO (reg)))
2219 regno = REGNO (reg);
2220 nregs = hard_regno_nregs[regno][GET_MODE (reg)];
2223 mask = (2U << (nregs - 1)) - 1;
2225 /* Disregard parts of the return value that are set later. */
2229 for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
2231 note_stores (PATTERN (p), likely_spilled_retval_1, &info);
2234 /* Check if any of the (probably) live return value registers is
2239 if ((mask & 1 << nregs)
2240 && targetm.class_likely_spilled_p (REGNO_REG_CLASS (regno + nregs)))
2246 /* Adjust INSN after we made a change to its destination.
2248 Changing the destination can invalidate notes that say something about
2249 the results of the insn and a LOG_LINK pointing to the insn. */
2252 adjust_for_new_dest (rtx insn)
2254 /* For notes, be conservative and simply remove them. */
2255 remove_reg_equal_equiv_notes (insn);
2257 /* The new insn will have a destination that was previously the destination
2258 of an insn just above it. Call distribute_links to make a LOG_LINK from
2259 the next use of that destination. */
2260 distribute_links (alloc_insn_link (insn, NULL));
2262 df_insn_rescan (insn);
2265 /* Return TRUE if combine can reuse reg X in mode MODE.
2266 ADDED_SETS is nonzero if the original set is still required. */
2268 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
2276 /* Allow hard registers if the new mode is legal, and occupies no more
2277 registers than the old mode. */
2278 if (regno < FIRST_PSEUDO_REGISTER)
2279 return (HARD_REGNO_MODE_OK (regno, mode)
2280 && (hard_regno_nregs[regno][GET_MODE (x)]
2281 >= hard_regno_nregs[regno][mode]));
2283 /* Or a pseudo that is only used once. */
2284 return (REG_N_SETS (regno) == 1 && !added_sets
2285 && !REG_USERVAR_P (x));
2289 /* Check whether X, the destination of a set, refers to part of
2290 the register specified by REG. */
2293 reg_subword_p (rtx x, rtx reg)
2295 /* Check that reg is an integer mode register. */
2296 if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
2299 if (GET_CODE (x) == STRICT_LOW_PART
2300 || GET_CODE (x) == ZERO_EXTRACT)
2303 return GET_CODE (x) == SUBREG
2304 && SUBREG_REG (x) == reg
2305 && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
2309 /* Replace auto-increment addressing modes with explicit operations to access
2310 the same addresses without modifying the corresponding registers. */
2313 cleanup_auto_inc_dec (rtx src, enum machine_mode mem_mode)
2316 const RTX_CODE code = GET_CODE (x);
2332 /* SCRATCH must be shared because they represent distinct values. */
2335 if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
2340 if (shared_const_p (x))
2345 mem_mode = GET_MODE (x);
2350 gcc_assert (mem_mode != VOIDmode && mem_mode != BLKmode);
2351 return gen_rtx_PLUS (GET_MODE (x),
2352 cleanup_auto_inc_dec (XEXP (x, 0), mem_mode),
2353 GEN_INT (code == PRE_INC
2354 ? GET_MODE_SIZE (mem_mode)
2355 : -GET_MODE_SIZE (mem_mode)));
2361 return cleanup_auto_inc_dec (code == PRE_MODIFY
2362 ? XEXP (x, 1) : XEXP (x, 0),
2369 /* Copy the various flags, fields, and other information. We assume
2370 that all fields need copying, and then clear the fields that should
2371 not be copied. That is the sensible default behavior, and forces
2372 us to explicitly document why we are *not* copying a flag. */
2373 x = shallow_copy_rtx (x);
2375 /* We do not copy the USED flag, which is used as a mark bit during
2376 walks over the RTL. */
2377 RTX_FLAG (x, used) = 0;
2379 /* We do not copy FRAME_RELATED for INSNs. */
2381 RTX_FLAG (x, frame_related) = 0;
2383 fmt = GET_RTX_FORMAT (code);
2384 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2386 XEXP (x, i) = cleanup_auto_inc_dec (XEXP (x, i), mem_mode);
2387 else if (fmt[i] == 'E' || fmt[i] == 'V')
2390 XVEC (x, i) = rtvec_alloc (XVECLEN (x, i));
2391 for (j = 0; j < XVECLEN (x, i); j++)
2393 = cleanup_auto_inc_dec (XVECEXP (src, i, j), mem_mode);
2400 /* Auxiliary data structure for propagate_for_debug_stmt. */
2402 struct rtx_subst_pair
2408 /* DATA points to an rtx_subst_pair. Return the value that should be
2412 propagate_for_debug_subst (rtx from, const_rtx old_rtx, void *data)
2414 struct rtx_subst_pair *pair = (struct rtx_subst_pair *)data;
2416 if (!rtx_equal_p (from, old_rtx))
2418 if (!pair->adjusted)
2420 pair->adjusted = true;
2422 pair->to = cleanup_auto_inc_dec (pair->to, VOIDmode);
2424 pair->to = copy_rtx (pair->to);
2426 pair->to = make_compound_operation (pair->to, SET);
2429 return copy_rtx (pair->to);
2432 /* Replace all the occurrences of DEST with SRC in DEBUG_INSNs between INSN
2436 propagate_for_debug (rtx insn, rtx last, rtx dest, rtx src)
2440 struct rtx_subst_pair p;
2444 next = NEXT_INSN (insn);
2445 while (next != last)
2448 next = NEXT_INSN (insn);
2449 if (DEBUG_INSN_P (insn))
2451 loc = simplify_replace_fn_rtx (INSN_VAR_LOCATION_LOC (insn),
2452 dest, propagate_for_debug_subst, &p);
2453 if (loc == INSN_VAR_LOCATION_LOC (insn))
2455 INSN_VAR_LOCATION_LOC (insn) = loc;
2456 df_insn_rescan (insn);
2461 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2462 Note that the INSN should be deleted *after* removing dead edges, so
2463 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2464 but not for a (set (pc) (label_ref FOO)). */
2467 update_cfg_for_uncondjump (rtx insn)
2469 basic_block bb = BLOCK_FOR_INSN (insn);
2470 bool at_end = (BB_END (bb) == insn);
2473 purge_dead_edges (bb);
2476 if (at_end && EDGE_COUNT (bb->succs) == 1)
2480 single_succ_edge (bb)->flags |= EDGE_FALLTHRU;
2482 /* Remove barriers from the footer if there are any. */
2483 for (insn = bb->il.rtl->footer; insn; insn = NEXT_INSN (insn))
2484 if (BARRIER_P (insn))
2486 if (PREV_INSN (insn))
2487 NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
2489 bb->il.rtl->footer = NEXT_INSN (insn);
2490 if (NEXT_INSN (insn))
2491 PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
2493 else if (LABEL_P (insn))
2498 /* Try to combine the insns I0, I1 and I2 into I3.
2499 Here I0, I1 and I2 appear earlier than I3.
2500 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2503 If we are combining more than two insns and the resulting insn is not
2504 recognized, try splitting it into two insns. If that happens, I2 and I3
2505 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2506 Otherwise, I0, I1 and I2 are pseudo-deleted.
2508 Return 0 if the combination does not work. Then nothing is changed.
2509 If we did the combination, return the insn at which combine should
2512 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2513 new direct jump instruction. */
2516 try_combine (rtx i3, rtx i2, rtx i1, rtx i0, int *new_direct_jump_p)
2518 /* New patterns for I3 and I2, respectively. */
2519 rtx newpat, newi2pat = 0;
2520 rtvec newpat_vec_with_clobbers = 0;
2521 int substed_i2 = 0, substed_i1 = 0, substed_i0 = 0;
2522 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2524 int added_sets_0, added_sets_1, added_sets_2;
2525 /* Total number of SETs to put into I3. */
2527 /* Nonzero if I2's or I1's body now appears in I3. */
2528 int i2_is_used = 0, i1_is_used = 0;
2529 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2530 int insn_code_number, i2_code_number = 0, other_code_number = 0;
2531 /* Contains I3 if the destination of I3 is used in its source, which means
2532 that the old life of I3 is being killed. If that usage is placed into
2533 I2 and not in I3, a REG_DEAD note must be made. */
2534 rtx i3dest_killed = 0;
2535 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2536 rtx i2dest = 0, i2src = 0, i1dest = 0, i1src = 0, i0dest = 0, i0src = 0;
2537 /* Copy of SET_SRC of I1, if needed. */
2539 /* Set if I2DEST was reused as a scratch register. */
2540 bool i2scratch = false;
2541 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2542 rtx i0pat = 0, i1pat = 0, i2pat = 0;
2543 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2544 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
2545 int i0dest_in_i0src = 0, i1dest_in_i0src = 0, i2dest_in_i0src = 0;
2546 int i2dest_killed = 0, i1dest_killed = 0, i0dest_killed = 0;
2547 int i1_feeds_i2_n = 0, i0_feeds_i2_n = 0, i0_feeds_i1_n = 0;
2548 /* Notes that must be added to REG_NOTES in I3 and I2. */
2549 rtx new_i3_notes, new_i2_notes;
2550 /* Notes that we substituted I3 into I2 instead of the normal case. */
2551 int i3_subst_into_i2 = 0;
2552 /* Notes that I1, I2 or I3 is a MULT operation. */
2555 int changed_i3_dest = 0;
2559 struct insn_link *link;
2561 rtx new_other_notes;
2564 /* Only try four-insn combinations when there's high likelihood of
2565 success. Look for simple insns, such as loads of constants or
2566 binary operations involving a constant. */
2573 if (!flag_expensive_optimizations)
2576 for (i = 0; i < 4; i++)
2578 rtx insn = i == 0 ? i0 : i == 1 ? i1 : i == 2 ? i2 : i3;
2579 rtx set = single_set (insn);
2583 src = SET_SRC (set);
2584 if (CONSTANT_P (src))
2589 else if (BINARY_P (src) && CONSTANT_P (XEXP (src, 1)))
2591 else if (GET_CODE (src) == ASHIFT || GET_CODE (src) == ASHIFTRT
2592 || GET_CODE (src) == LSHIFTRT)
2595 if (ngood < 2 && nshift < 2)
2599 /* Exit early if one of the insns involved can't be used for
2601 if (cant_combine_insn_p (i3)
2602 || cant_combine_insn_p (i2)
2603 || (i1 && cant_combine_insn_p (i1))
2604 || (i0 && cant_combine_insn_p (i0))
2605 || likely_spilled_retval_p (i3))
2609 undobuf.other_insn = 0;
2611 /* Reset the hard register usage information. */
2612 CLEAR_HARD_REG_SET (newpat_used_regs);
2614 if (dump_file && (dump_flags & TDF_DETAILS))
2617 fprintf (dump_file, "\nTrying %d, %d, %d -> %d:\n",
2618 INSN_UID (i0), INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2620 fprintf (dump_file, "\nTrying %d, %d -> %d:\n",
2621 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2623 fprintf (dump_file, "\nTrying %d -> %d:\n",
2624 INSN_UID (i2), INSN_UID (i3));
2627 /* If multiple insns feed into one of I2 or I3, they can be in any
2628 order. To simplify the code below, reorder them in sequence. */
2629 if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i2))
2630 temp = i2, i2 = i0, i0 = temp;
2631 if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i1))
2632 temp = i1, i1 = i0, i0 = temp;
2633 if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2))
2634 temp = i1, i1 = i2, i2 = temp;
2636 added_links_insn = 0;
2638 /* First check for one important special case that the code below will
2639 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2640 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2641 we may be able to replace that destination with the destination of I3.
2642 This occurs in the common code where we compute both a quotient and
2643 remainder into a structure, in which case we want to do the computation
2644 directly into the structure to avoid register-register copies.
2646 Note that this case handles both multiple sets in I2 and also cases
2647 where I2 has a number of CLOBBERs inside the PARALLEL.
2649 We make very conservative checks below and only try to handle the
2650 most common cases of this. For example, we only handle the case
2651 where I2 and I3 are adjacent to avoid making difficult register
2654 if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
2655 && REG_P (SET_SRC (PATTERN (i3)))
2656 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
2657 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
2658 && GET_CODE (PATTERN (i2)) == PARALLEL
2659 && ! side_effects_p (SET_DEST (PATTERN (i3)))
2660 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2661 below would need to check what is inside (and reg_overlap_mentioned_p
2662 doesn't support those codes anyway). Don't allow those destinations;
2663 the resulting insn isn't likely to be recognized anyway. */
2664 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
2665 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
2666 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
2667 SET_DEST (PATTERN (i3)))
2668 && next_active_insn (i2) == i3)
2670 rtx p2 = PATTERN (i2);
2672 /* Make sure that the destination of I3,
2673 which we are going to substitute into one output of I2,
2674 is not used within another output of I2. We must avoid making this:
2675 (parallel [(set (mem (reg 69)) ...)
2676 (set (reg 69) ...)])
2677 which is not well-defined as to order of actions.
2678 (Besides, reload can't handle output reloads for this.)
2680 The problem can also happen if the dest of I3 is a memory ref,
2681 if another dest in I2 is an indirect memory ref. */
2682 for (i = 0; i < XVECLEN (p2, 0); i++)
2683 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2684 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2685 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
2686 SET_DEST (XVECEXP (p2, 0, i))))
2689 if (i == XVECLEN (p2, 0))
2690 for (i = 0; i < XVECLEN (p2, 0); i++)
2691 if (GET_CODE (XVECEXP (p2, 0, i)) == SET
2692 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
2697 subst_low_luid = DF_INSN_LUID (i2);
2699 added_sets_2 = added_sets_1 = added_sets_0 = 0;
2700 i2src = SET_SRC (XVECEXP (p2, 0, i));
2701 i2dest = SET_DEST (XVECEXP (p2, 0, i));
2702 i2dest_killed = dead_or_set_p (i2, i2dest);
2704 /* Replace the dest in I2 with our dest and make the resulting
2705 insn the new pattern for I3. Then skip to where we validate
2706 the pattern. Everything was set up above. */
2707 SUBST (SET_DEST (XVECEXP (p2, 0, i)), SET_DEST (PATTERN (i3)));
2709 i3_subst_into_i2 = 1;
2710 goto validate_replacement;
2714 /* If I2 is setting a pseudo to a constant and I3 is setting some
2715 sub-part of it to another constant, merge them by making a new
2718 && (temp = single_set (i2)) != 0
2719 && (CONST_INT_P (SET_SRC (temp))
2720 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
2721 && GET_CODE (PATTERN (i3)) == SET
2722 && (CONST_INT_P (SET_SRC (PATTERN (i3)))
2723 || GET_CODE (SET_SRC (PATTERN (i3))) == CONST_DOUBLE)
2724 && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
2726 rtx dest = SET_DEST (PATTERN (i3));
2730 if (GET_CODE (dest) == ZERO_EXTRACT)
2732 if (CONST_INT_P (XEXP (dest, 1))
2733 && CONST_INT_P (XEXP (dest, 2)))
2735 width = INTVAL (XEXP (dest, 1));
2736 offset = INTVAL (XEXP (dest, 2));
2737 dest = XEXP (dest, 0);
2738 if (BITS_BIG_ENDIAN)
2739 offset = GET_MODE_BITSIZE (GET_MODE (dest)) - width - offset;
2744 if (GET_CODE (dest) == STRICT_LOW_PART)
2745 dest = XEXP (dest, 0);
2746 width = GET_MODE_BITSIZE (GET_MODE (dest));
2752 /* If this is the low part, we're done. */
2753 if (subreg_lowpart_p (dest))
2755 /* Handle the case where inner is twice the size of outer. */
2756 else if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2757 == 2 * GET_MODE_BITSIZE (GET_MODE (dest)))
2758 offset += GET_MODE_BITSIZE (GET_MODE (dest));
2759 /* Otherwise give up for now. */
2765 && (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2766 <= HOST_BITS_PER_DOUBLE_INT))
2769 rtx inner = SET_SRC (PATTERN (i3));
2770 rtx outer = SET_SRC (temp);
2772 o = rtx_to_double_int (outer);
2773 i = rtx_to_double_int (inner);
2775 m = double_int_mask (width);
2776 i = double_int_and (i, m);
2777 m = double_int_lshift (m, offset, HOST_BITS_PER_DOUBLE_INT, false);
2778 i = double_int_lshift (i, offset, HOST_BITS_PER_DOUBLE_INT, false);
2779 o = double_int_ior (double_int_and_not (o, m), i);
2783 subst_low_luid = DF_INSN_LUID (i2);
2784 added_sets_2 = added_sets_1 = added_sets_0 = 0;
2785 i2dest = SET_DEST (temp);
2786 i2dest_killed = dead_or_set_p (i2, i2dest);
2788 /* Replace the source in I2 with the new constant and make the
2789 resulting insn the new pattern for I3. Then skip to where we
2790 validate the pattern. Everything was set up above. */
2791 SUBST (SET_SRC (temp),
2792 immed_double_int_const (o, GET_MODE (SET_DEST (temp))));
2794 newpat = PATTERN (i2);
2796 /* The dest of I3 has been replaced with the dest of I2. */
2797 changed_i3_dest = 1;
2798 goto validate_replacement;
2803 /* If we have no I1 and I2 looks like:
2804 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2806 make up a dummy I1 that is
2809 (set (reg:CC X) (compare:CC Y (const_int 0)))
2811 (We can ignore any trailing CLOBBERs.)
2813 This undoes a previous combination and allows us to match a branch-and-
2816 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2817 && XVECLEN (PATTERN (i2), 0) >= 2
2818 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2819 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2821 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2822 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2823 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2824 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2825 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2826 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2828 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2829 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2834 /* We make I1 with the same INSN_UID as I2. This gives it
2835 the same DF_INSN_LUID for value tracking. Our fake I1 will
2836 never appear in the insn stream so giving it the same INSN_UID
2837 as I2 will not cause a problem. */
2839 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
2840 BLOCK_FOR_INSN (i2), XVECEXP (PATTERN (i2), 0, 1),
2841 INSN_LOCATOR (i2), -1, NULL_RTX);
2843 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2844 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2845 SET_DEST (PATTERN (i1)));
2850 /* Verify that I2 and I1 are valid for combining. */
2851 if (! can_combine_p (i2, i3, i0, i1, NULL_RTX, NULL_RTX, &i2dest, &i2src)
2852 || (i1 && ! can_combine_p (i1, i3, i0, NULL_RTX, i2, NULL_RTX,
2854 || (i0 && ! can_combine_p (i0, i3, NULL_RTX, NULL_RTX, i1, i2,
2861 /* Record whether I2DEST is used in I2SRC and similarly for the other
2862 cases. Knowing this will help in register status updating below. */
2863 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2864 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2865 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2866 i0dest_in_i0src = i0 && reg_overlap_mentioned_p (i0dest, i0src);
2867 i1dest_in_i0src = i0 && reg_overlap_mentioned_p (i1dest, i0src);
2868 i2dest_in_i0src = i0 && reg_overlap_mentioned_p (i2dest, i0src);
2869 i2dest_killed = dead_or_set_p (i2, i2dest);
2870 i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2871 i0dest_killed = i0 && dead_or_set_p (i0, i0dest);
2873 /* For the earlier insns, determine which of the subsequent ones they
2875 i1_feeds_i2_n = i1 && insn_a_feeds_b (i1, i2);
2876 i0_feeds_i1_n = i0 && insn_a_feeds_b (i0, i1);
2877 i0_feeds_i2_n = (i0 && (!i0_feeds_i1_n ? insn_a_feeds_b (i0, i2)
2878 : (!reg_overlap_mentioned_p (i1dest, i0dest)
2879 && reg_overlap_mentioned_p (i0dest, i2src))));
2881 /* Ensure that I3's pattern can be the destination of combines. */
2882 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest, i0dest,
2883 i1 && i2dest_in_i1src && !i1_feeds_i2_n,
2884 i0 && ((i2dest_in_i0src && !i0_feeds_i2_n)
2885 || (i1dest_in_i0src && !i0_feeds_i1_n)),
2892 /* See if any of the insns is a MULT operation. Unless one is, we will
2893 reject a combination that is, since it must be slower. Be conservative
2895 if (GET_CODE (i2src) == MULT
2896 || (i1 != 0 && GET_CODE (i1src) == MULT)
2897 || (i0 != 0 && GET_CODE (i0src) == MULT)
2898 || (GET_CODE (PATTERN (i3)) == SET
2899 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2902 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2903 We used to do this EXCEPT in one case: I3 has a post-inc in an
2904 output operand. However, that exception can give rise to insns like
2906 which is a famous insn on the PDP-11 where the value of r3 used as the
2907 source was model-dependent. Avoid this sort of thing. */
2910 if (!(GET_CODE (PATTERN (i3)) == SET
2911 && REG_P (SET_SRC (PATTERN (i3)))
2912 && MEM_P (SET_DEST (PATTERN (i3)))
2913 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2914 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2915 /* It's not the exception. */
2920 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2921 if (REG_NOTE_KIND (link) == REG_INC
2922 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2924 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2932 /* See if the SETs in I1 or I2 need to be kept around in the merged
2933 instruction: whenever the value set there is still needed past I3.
2934 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2936 For the SET in I1, we have two cases: If I1 and I2 independently
2937 feed into I3, the set in I1 needs to be kept around if I1DEST dies
2938 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2939 in I1 needs to be kept around unless I1DEST dies or is set in either
2940 I2 or I3. The same consideration applies to I0. */
2942 added_sets_2 = !dead_or_set_p (i3, i2dest);
2945 added_sets_1 = !(dead_or_set_p (i3, i1dest)
2946 || (i1_feeds_i2_n && dead_or_set_p (i2, i1dest)));
2951 added_sets_0 = !(dead_or_set_p (i3, i0dest)
2952 || (i0_feeds_i2_n && dead_or_set_p (i2, i0dest))
2953 || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest)));
2957 /* We are about to copy insns for the case where they need to be kept
2958 around. Check that they can be copied in the merged instruction. */
2960 if (targetm.cannot_copy_insn_p
2961 && ((added_sets_2 && targetm.cannot_copy_insn_p (i2))
2962 || (i1 && added_sets_1 && targetm.cannot_copy_insn_p (i1))
2963 || (i0 && added_sets_0 && targetm.cannot_copy_insn_p (i0))))
2969 /* If the set in I2 needs to be kept around, we must make a copy of
2970 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2971 PATTERN (I2), we are only substituting for the original I1DEST, not into
2972 an already-substituted copy. This also prevents making self-referential
2973 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2978 if (GET_CODE (PATTERN (i2)) == PARALLEL)
2979 i2pat = gen_rtx_SET (VOIDmode, i2dest, copy_rtx (i2src));
2981 i2pat = copy_rtx (PATTERN (i2));
2986 if (GET_CODE (PATTERN (i1)) == PARALLEL)
2987 i1pat = gen_rtx_SET (VOIDmode, i1dest, copy_rtx (i1src));
2989 i1pat = copy_rtx (PATTERN (i1));
2994 if (GET_CODE (PATTERN (i0)) == PARALLEL)
2995 i0pat = gen_rtx_SET (VOIDmode, i0dest, copy_rtx (i0src));
2997 i0pat = copy_rtx (PATTERN (i0));
3002 /* Substitute in the latest insn for the regs set by the earlier ones. */
3004 maxreg = max_reg_num ();
3009 /* Many machines that don't use CC0 have insns that can both perform an
3010 arithmetic operation and set the condition code. These operations will
3011 be represented as a PARALLEL with the first element of the vector
3012 being a COMPARE of an arithmetic operation with the constant zero.
3013 The second element of the vector will set some pseudo to the result
3014 of the same arithmetic operation. If we simplify the COMPARE, we won't
3015 match such a pattern and so will generate an extra insn. Here we test
3016 for this case, where both the comparison and the operation result are
3017 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3018 I2SRC. Later we will make the PARALLEL that contains I2. */
3020 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
3021 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
3022 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
3023 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
3025 #ifdef SELECT_CC_MODE
3027 enum machine_mode compare_mode;
3030 newpat = PATTERN (i3);
3031 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
3035 #ifdef SELECT_CC_MODE
3036 /* See if a COMPARE with the operand we substituted in should be done
3037 with the mode that is currently being used. If not, do the same
3038 processing we do in `subst' for a SET; namely, if the destination
3039 is used only once, try to replace it with a register of the proper
3040 mode and also replace the COMPARE. */
3041 if (undobuf.other_insn == 0
3042 && (cc_use = find_single_use (SET_DEST (newpat), i3,
3043 &undobuf.other_insn))
3044 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
3046 != GET_MODE (SET_DEST (newpat))))
3048 if (can_change_dest_mode (SET_DEST (newpat), added_sets_2,
3051 unsigned int regno = REGNO (SET_DEST (newpat));
3054 if (regno < FIRST_PSEUDO_REGISTER)
3055 new_dest = gen_rtx_REG (compare_mode, regno);
3058 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
3059 new_dest = regno_reg_rtx[regno];
3062 SUBST (SET_DEST (newpat), new_dest);
3063 SUBST (XEXP (*cc_use, 0), new_dest);
3064 SUBST (SET_SRC (newpat),
3065 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
3068 undobuf.other_insn = 0;
3075 /* It is possible that the source of I2 or I1 may be performing
3076 an unneeded operation, such as a ZERO_EXTEND of something
3077 that is known to have the high part zero. Handle that case
3078 by letting subst look at the inner insns.
3080 Another way to do this would be to have a function that tries
3081 to simplify a single insn instead of merging two or more
3082 insns. We don't do this because of the potential of infinite
3083 loops and because of the potential extra memory required.
3084 However, doing it the way we are is a bit of a kludge and
3085 doesn't catch all cases.
3087 But only do this if -fexpensive-optimizations since it slows
3088 things down and doesn't usually win.
3090 This is not done in the COMPARE case above because the
3091 unmodified I2PAT is used in the PARALLEL and so a pattern
3092 with a modified I2SRC would not match. */
3094 if (flag_expensive_optimizations)
3096 /* Pass pc_rtx so no substitutions are done, just
3100 subst_low_luid = DF_INSN_LUID (i1);
3101 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
3104 subst_low_luid = DF_INSN_LUID (i2);
3105 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
3108 n_occurrences = 0; /* `subst' counts here */
3109 subst_low_luid = DF_INSN_LUID (i2);
3111 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3112 copy of I2SRC each time we substitute it, in order to avoid creating
3113 self-referential RTL when we will be substituting I1SRC for I1DEST
3114 later. Likewise if I0 feeds into I2, either directly or indirectly
3115 through I1, and I0DEST is in I0SRC. */
3116 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
3117 (i1_feeds_i2_n && i1dest_in_i1src)
3118 || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
3119 && i0dest_in_i0src));
3122 /* Record whether I2's body now appears within I3's body. */
3123 i2_is_used = n_occurrences;
3126 /* If we already got a failure, don't try to do more. Otherwise, try to
3127 substitute I1 if we have it. */
3129 if (i1 && GET_CODE (newpat) != CLOBBER)
3131 /* Check that an autoincrement side-effect on I1 has not been lost.
3132 This happens if I1DEST is mentioned in I2 and dies there, and
3133 has disappeared from the new pattern. */
3134 if ((FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3136 && dead_or_set_p (i2, i1dest)
3137 && !reg_overlap_mentioned_p (i1dest, newpat))
3138 /* Before we can do this substitution, we must redo the test done
3139 above (see detailed comments there) that ensures I1DEST isn't
3140 mentioned in any SETs in NEWPAT that are field assignments. */
3141 || !combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX, NULL_RTX,
3149 subst_low_luid = DF_INSN_LUID (i1);
3151 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3152 copy of I1SRC each time we substitute it, in order to avoid creating
3153 self-referential RTL when we will be substituting I0SRC for I0DEST
3155 newpat = subst (newpat, i1dest, i1src, 0,
3156 i0_feeds_i1_n && i0dest_in_i0src);
3159 /* Record whether I1's body now appears within I3's body. */
3160 i1_is_used = n_occurrences;
3163 /* Likewise for I0 if we have it. */
3165 if (i0 && GET_CODE (newpat) != CLOBBER)
3167 if ((FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3168 && ((i0_feeds_i2_n && dead_or_set_p (i2, i0dest))
3169 || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest)))
3170 && !reg_overlap_mentioned_p (i0dest, newpat))
3171 || !combinable_i3pat (NULL_RTX, &newpat, i0dest, NULL_RTX, NULL_RTX,
3178 /* If the following substitution will modify I1SRC, make a copy of it
3179 for the case where it is substituted for I1DEST in I2PAT later. */
3180 if (i0_feeds_i1_n && added_sets_2 && i1_feeds_i2_n)
3181 i1src_copy = copy_rtx (i1src);
3184 subst_low_luid = DF_INSN_LUID (i0);
3185 newpat = subst (newpat, i0dest, i0src, 0, 0);
3189 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3190 to count all the ways that I2SRC and I1SRC can be used. */
3191 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
3192 && i2_is_used + added_sets_2 > 1)
3193 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3194 && (i1_is_used + added_sets_1 + (added_sets_2 && i1_feeds_i2_n)
3196 || (i0 != 0 && FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3197 && (n_occurrences + added_sets_0
3198 + (added_sets_1 && i0_feeds_i1_n)
3199 + (added_sets_2 && i0_feeds_i2_n)
3201 /* Fail if we tried to make a new register. */
3202 || max_reg_num () != maxreg
3203 /* Fail if we couldn't do something and have a CLOBBER. */
3204 || GET_CODE (newpat) == CLOBBER
3205 /* Fail if this new pattern is a MULT and we didn't have one before
3206 at the outer level. */
3207 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
3214 /* If the actions of the earlier insns must be kept
3215 in addition to substituting them into the latest one,
3216 we must make a new PARALLEL for the latest insn
3217 to hold additional the SETs. */
3219 if (added_sets_0 || added_sets_1 || added_sets_2)
3221 int extra_sets = added_sets_0 + added_sets_1 + added_sets_2;
3224 if (GET_CODE (newpat) == PARALLEL)
3226 rtvec old = XVEC (newpat, 0);
3227 total_sets = XVECLEN (newpat, 0) + extra_sets;
3228 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3229 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
3230 sizeof (old->elem[0]) * old->num_elem);
3235 total_sets = 1 + extra_sets;
3236 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3237 XVECEXP (newpat, 0, 0) = old;
3241 XVECEXP (newpat, 0, --total_sets) = i0pat;
3247 t = subst (t, i0dest, i0src, 0, 0);
3249 XVECEXP (newpat, 0, --total_sets) = t;
3255 t = subst (t, i1dest, i1src_copy ? i1src_copy : i1src, 0,
3256 i0_feeds_i1_n && i0dest_in_i0src);
3257 if ((i0_feeds_i1_n && i1_feeds_i2_n) || i0_feeds_i2_n)
3258 t = subst (t, i0dest, i0src, 0, 0);
3260 XVECEXP (newpat, 0, --total_sets) = t;
3264 validate_replacement:
3266 /* Note which hard regs this insn has as inputs. */
3267 mark_used_regs_combine (newpat);
3269 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3270 consider splitting this pattern, we might need these clobbers. */
3271 if (i1 && GET_CODE (newpat) == PARALLEL
3272 && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
3274 int len = XVECLEN (newpat, 0);
3276 newpat_vec_with_clobbers = rtvec_alloc (len);
3277 for (i = 0; i < len; i++)
3278 RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
3281 /* Is the result of combination a valid instruction? */
3282 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3284 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
3285 the second SET's destination is a register that is unused and isn't
3286 marked as an instruction that might trap in an EH region. In that case,
3287 we just need the first SET. This can occur when simplifying a divmod
3288 insn. We *must* test for this case here because the code below that
3289 splits two independent SETs doesn't handle this case correctly when it
3290 updates the register status.
3292 It's pointless doing this if we originally had two sets, one from
3293 i3, and one from i2. Combining then splitting the parallel results
3294 in the original i2 again plus an invalid insn (which we delete).
3295 The net effect is only to move instructions around, which makes
3296 debug info less accurate.
3298 Also check the case where the first SET's destination is unused.
3299 That would not cause incorrect code, but does cause an unneeded
3302 if (insn_code_number < 0
3303 && !(added_sets_2 && i1 == 0)
3304 && GET_CODE (newpat) == PARALLEL
3305 && XVECLEN (newpat, 0) == 2
3306 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3307 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3308 && asm_noperands (newpat) < 0)
3310 rtx set0 = XVECEXP (newpat, 0, 0);
3311 rtx set1 = XVECEXP (newpat, 0, 1);
3313 if (((REG_P (SET_DEST (set1))
3314 && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
3315 || (GET_CODE (SET_DEST (set1)) == SUBREG
3316 && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
3317 && insn_nothrow_p (i3)
3318 && !side_effects_p (SET_SRC (set1)))
3321 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3324 else if (((REG_P (SET_DEST (set0))
3325 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
3326 || (GET_CODE (SET_DEST (set0)) == SUBREG
3327 && find_reg_note (i3, REG_UNUSED,
3328 SUBREG_REG (SET_DEST (set0)))))
3329 && insn_nothrow_p (i3)
3330 && !side_effects_p (SET_SRC (set0)))
3333 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3335 if (insn_code_number >= 0)
3336 changed_i3_dest = 1;
3340 /* If we were combining three insns and the result is a simple SET
3341 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3342 insns. There are two ways to do this. It can be split using a
3343 machine-specific method (like when you have an addition of a large
3344 constant) or by combine in the function find_split_point. */
3346 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
3347 && asm_noperands (newpat) < 0)
3349 rtx parallel, m_split, *split;
3351 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3352 use I2DEST as a scratch register will help. In the latter case,
3353 convert I2DEST to the mode of the source of NEWPAT if we can. */
3355 m_split = combine_split_insns (newpat, i3);
3357 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3358 inputs of NEWPAT. */
3360 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3361 possible to try that as a scratch reg. This would require adding
3362 more code to make it work though. */
3364 if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
3366 enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
3368 /* First try to split using the original register as a
3369 scratch register. */
3370 parallel = gen_rtx_PARALLEL (VOIDmode,
3371 gen_rtvec (2, newpat,
3372 gen_rtx_CLOBBER (VOIDmode,
3374 m_split = combine_split_insns (parallel, i3);
3376 /* If that didn't work, try changing the mode of I2DEST if
3379 && new_mode != GET_MODE (i2dest)
3380 && new_mode != VOIDmode
3381 && can_change_dest_mode (i2dest, added_sets_2, new_mode))
3383 enum machine_mode old_mode = GET_MODE (i2dest);
3386 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3387 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
3390 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
3391 ni2dest = regno_reg_rtx[REGNO (i2dest)];
3394 parallel = (gen_rtx_PARALLEL
3396 gen_rtvec (2, newpat,
3397 gen_rtx_CLOBBER (VOIDmode,
3399 m_split = combine_split_insns (parallel, i3);
3402 && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
3406 adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode);
3407 buf = undobuf.undos;
3408 undobuf.undos = buf->next;
3409 buf->next = undobuf.frees;
3410 undobuf.frees = buf;
3414 i2scratch = m_split != 0;
3417 /* If recog_for_combine has discarded clobbers, try to use them
3418 again for the split. */
3419 if (m_split == 0 && newpat_vec_with_clobbers)
3421 parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers);
3422 m_split = combine_split_insns (parallel, i3);
3425 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
3427 m_split = PATTERN (m_split);
3428 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
3429 if (insn_code_number >= 0)
3432 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
3433 && (next_real_insn (i2) == i3
3434 || ! use_crosses_set_p (PATTERN (m_split), DF_INSN_LUID (i2))))
3437 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
3438 newi2pat = PATTERN (m_split);
3440 i3set = single_set (NEXT_INSN (m_split));
3441 i2set = single_set (m_split);
3443 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3445 /* If I2 or I3 has multiple SETs, we won't know how to track
3446 register status, so don't use these insns. If I2's destination
3447 is used between I2 and I3, we also can't use these insns. */
3449 if (i2_code_number >= 0 && i2set && i3set
3450 && (next_real_insn (i2) == i3
3451 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
3452 insn_code_number = recog_for_combine (&newi3pat, i3,
3454 if (insn_code_number >= 0)
3457 /* It is possible that both insns now set the destination of I3.
3458 If so, we must show an extra use of it. */
3460 if (insn_code_number >= 0)
3462 rtx new_i3_dest = SET_DEST (i3set);
3463 rtx new_i2_dest = SET_DEST (i2set);
3465 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
3466 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
3467 || GET_CODE (new_i3_dest) == SUBREG)
3468 new_i3_dest = XEXP (new_i3_dest, 0);
3470 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
3471 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
3472 || GET_CODE (new_i2_dest) == SUBREG)
3473 new_i2_dest = XEXP (new_i2_dest, 0);
3475 if (REG_P (new_i3_dest)
3476 && REG_P (new_i2_dest)
3477 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
3478 INC_REG_N_SETS (REGNO (new_i2_dest), 1);
3482 /* If we can split it and use I2DEST, go ahead and see if that
3483 helps things be recognized. Verify that none of the registers
3484 are set between I2 and I3. */
3485 if (insn_code_number < 0
3486 && (split = find_split_point (&newpat, i3, false)) != 0
3490 /* We need I2DEST in the proper mode. If it is a hard register
3491 or the only use of a pseudo, we can change its mode.
3492 Make sure we don't change a hard register to have a mode that
3493 isn't valid for it, or change the number of registers. */
3494 && (GET_MODE (*split) == GET_MODE (i2dest)
3495 || GET_MODE (*split) == VOIDmode
3496 || can_change_dest_mode (i2dest, added_sets_2,
3498 && (next_real_insn (i2) == i3
3499 || ! use_crosses_set_p (*split, DF_INSN_LUID (i2)))
3500 /* We can't overwrite I2DEST if its value is still used by
3502 && ! reg_referenced_p (i2dest, newpat))
3504 rtx newdest = i2dest;
3505 enum rtx_code split_code = GET_CODE (*split);
3506 enum machine_mode split_mode = GET_MODE (*split);
3507 bool subst_done = false;
3508 newi2pat = NULL_RTX;
3512 /* *SPLIT may be part of I2SRC, so make sure we have the
3513 original expression around for later debug processing.
3514 We should not need I2SRC any more in other cases. */
3515 if (MAY_HAVE_DEBUG_INSNS)
3516 i2src = copy_rtx (i2src);
3520 /* Get NEWDEST as a register in the proper mode. We have already
3521 validated that we can do this. */
3522 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
3524 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3525 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
3528 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
3529 newdest = regno_reg_rtx[REGNO (i2dest)];
3533 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3534 an ASHIFT. This can occur if it was inside a PLUS and hence
3535 appeared to be a memory address. This is a kludge. */
3536 if (split_code == MULT
3537 && CONST_INT_P (XEXP (*split, 1))
3538 && INTVAL (XEXP (*split, 1)) > 0
3539 && (i = exact_log2 (UINTVAL (XEXP (*split, 1)))) >= 0)
3541 SUBST (*split, gen_rtx_ASHIFT (split_mode,
3542 XEXP (*split, 0), GEN_INT (i)));
3543 /* Update split_code because we may not have a multiply
3545 split_code = GET_CODE (*split);
3548 #ifdef INSN_SCHEDULING
3549 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3550 be written as a ZERO_EXTEND. */
3551 if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
3553 #ifdef LOAD_EXTEND_OP
3554 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3555 what it really is. */
3556 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
3558 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
3559 SUBREG_REG (*split)));
3562 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
3563 SUBREG_REG (*split)));
3567 /* Attempt to split binary operators using arithmetic identities. */
3568 if (BINARY_P (SET_SRC (newpat))
3569 && split_mode == GET_MODE (SET_SRC (newpat))
3570 && ! side_effects_p (SET_SRC (newpat)))
3572 rtx setsrc = SET_SRC (newpat);
3573 enum machine_mode mode = GET_MODE (setsrc);
3574 enum rtx_code code = GET_CODE (setsrc);
3575 rtx src_op0 = XEXP (setsrc, 0);
3576 rtx src_op1 = XEXP (setsrc, 1);
3578 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3579 if (rtx_equal_p (src_op0, src_op1))
3581 newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
3582 SUBST (XEXP (setsrc, 0), newdest);
3583 SUBST (XEXP (setsrc, 1), newdest);
3586 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3587 else if ((code == PLUS || code == MULT)
3588 && GET_CODE (src_op0) == code
3589 && GET_CODE (XEXP (src_op0, 0)) == code
3590 && (INTEGRAL_MODE_P (mode)
3591 || (FLOAT_MODE_P (mode)
3592 && flag_unsafe_math_optimizations)))
3594 rtx p = XEXP (XEXP (src_op0, 0), 0);
3595 rtx q = XEXP (XEXP (src_op0, 0), 1);
3596 rtx r = XEXP (src_op0, 1);
3599 /* Split both "((X op Y) op X) op Y" and
3600 "((X op Y) op Y) op X" as "T op T" where T is
3602 if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
3603 || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
3605 newi2pat = gen_rtx_SET (VOIDmode, newdest,
3607 SUBST (XEXP (setsrc, 0), newdest);
3608 SUBST (XEXP (setsrc, 1), newdest);
3611 /* Split "((X op X) op Y) op Y)" as "T op T" where
3613 else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
3615 rtx tmp = simplify_gen_binary (code, mode, p, r);
3616 newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
3617 SUBST (XEXP (setsrc, 0), newdest);
3618 SUBST (XEXP (setsrc, 1), newdest);
3626 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
3627 SUBST (*split, newdest);
3630 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3632 /* recog_for_combine might have added CLOBBERs to newi2pat.
3633 Make sure NEWPAT does not depend on the clobbered regs. */
3634 if (GET_CODE (newi2pat) == PARALLEL)
3635 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3636 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3638 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3639 if (reg_overlap_mentioned_p (reg, newpat))
3646 /* If the split point was a MULT and we didn't have one before,
3647 don't use one now. */
3648 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
3649 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3653 /* Check for a case where we loaded from memory in a narrow mode and
3654 then sign extended it, but we need both registers. In that case,
3655 we have a PARALLEL with both loads from the same memory location.
3656 We can split this into a load from memory followed by a register-register
3657 copy. This saves at least one insn, more if register allocation can
3660 We cannot do this if the destination of the first assignment is a
3661 condition code register or cc0. We eliminate this case by making sure
3662 the SET_DEST and SET_SRC have the same mode.
3664 We cannot do this if the destination of the second assignment is
3665 a register that we have already assumed is zero-extended. Similarly
3666 for a SUBREG of such a register. */
3668 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3669 && GET_CODE (newpat) == PARALLEL
3670 && XVECLEN (newpat, 0) == 2
3671 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3672 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
3673 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
3674 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
3675 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3676 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3677 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
3678 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3680 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3681 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3682 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
3684 && VEC_index (reg_stat_type, reg_stat,
3685 REGNO (temp))->nonzero_bits != 0
3686 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3687 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3688 && (VEC_index (reg_stat_type, reg_stat,
3689 REGNO (temp))->nonzero_bits
3690 != GET_MODE_MASK (word_mode))))
3691 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
3692 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
3694 && VEC_index (reg_stat_type, reg_stat,
3695 REGNO (temp))->nonzero_bits != 0
3696 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3697 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3698 && (VEC_index (reg_stat_type, reg_stat,
3699 REGNO (temp))->nonzero_bits
3700 != GET_MODE_MASK (word_mode)))))
3701 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3702 SET_SRC (XVECEXP (newpat, 0, 1)))
3703 && ! find_reg_note (i3, REG_UNUSED,
3704 SET_DEST (XVECEXP (newpat, 0, 0))))
3708 newi2pat = XVECEXP (newpat, 0, 0);
3709 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
3710 newpat = XVECEXP (newpat, 0, 1);
3711 SUBST (SET_SRC (newpat),
3712 gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
3713 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3715 if (i2_code_number >= 0)
3716 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3718 if (insn_code_number >= 0)
3722 /* Similarly, check for a case where we have a PARALLEL of two independent
3723 SETs but we started with three insns. In this case, we can do the sets
3724 as two separate insns. This case occurs when some SET allows two
3725 other insns to combine, but the destination of that SET is still live. */
3727 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3728 && GET_CODE (newpat) == PARALLEL
3729 && XVECLEN (newpat, 0) == 2
3730 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3731 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
3732 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
3733 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3734 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3735 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3736 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3737 XVECEXP (newpat, 0, 0))
3738 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
3739 XVECEXP (newpat, 0, 1))
3740 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
3741 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
3743 /* Normally, it doesn't matter which of the two is done first,
3744 but the one that references cc0 can't be the second, and
3745 one which uses any regs/memory set in between i2 and i3 can't
3747 if (!use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3750 && !reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0))
3754 newi2pat = XVECEXP (newpat, 0, 1);
3755 newpat = XVECEXP (newpat, 0, 0);
3757 else if (!use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 0)),
3760 && !reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 1))
3764 newi2pat = XVECEXP (newpat, 0, 0);
3765 newpat = XVECEXP (newpat, 0, 1);
3773 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3775 if (i2_code_number >= 0)
3777 /* recog_for_combine might have added CLOBBERs to newi2pat.
3778 Make sure NEWPAT does not depend on the clobbered regs. */
3779 if (GET_CODE (newi2pat) == PARALLEL)
3781 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3782 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3784 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3785 if (reg_overlap_mentioned_p (reg, newpat))
3793 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3797 /* If it still isn't recognized, fail and change things back the way they
3799 if ((insn_code_number < 0
3800 /* Is the result a reasonable ASM_OPERANDS? */
3801 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
3807 /* If we had to change another insn, make sure it is valid also. */
3808 if (undobuf.other_insn)
3810 CLEAR_HARD_REG_SET (newpat_used_regs);
3812 other_pat = PATTERN (undobuf.other_insn);
3813 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
3816 if (other_code_number < 0 && ! check_asm_operands (other_pat))
3824 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3825 they are adjacent to each other or not. */
3827 rtx p = prev_nonnote_insn (i3);
3828 if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
3829 && sets_cc0_p (newi2pat))
3837 /* Only allow this combination if insn_rtx_costs reports that the
3838 replacement instructions are cheaper than the originals. */
3839 if (!combine_validate_cost (i0, i1, i2, i3, newpat, newi2pat, other_pat))
3845 if (MAY_HAVE_DEBUG_INSNS)
3849 for (undo = undobuf.undos; undo; undo = undo->next)
3850 if (undo->kind == UNDO_MODE)
3852 rtx reg = *undo->where.r;
3853 enum machine_mode new_mode = GET_MODE (reg);
3854 enum machine_mode old_mode = undo->old_contents.m;
3856 /* Temporarily revert mode back. */
3857 adjust_reg_mode (reg, old_mode);
3859 if (reg == i2dest && i2scratch)
3861 /* If we used i2dest as a scratch register with a
3862 different mode, substitute it for the original
3863 i2src while its original mode is temporarily
3864 restored, and then clear i2scratch so that we don't
3865 do it again later. */
3866 propagate_for_debug (i2, i3, reg, i2src);
3868 /* Put back the new mode. */
3869 adjust_reg_mode (reg, new_mode);
3873 rtx tempreg = gen_raw_REG (old_mode, REGNO (reg));
3884 last = undobuf.other_insn;
3888 /* We're dealing with a reg that changed mode but not
3889 meaning, so we want to turn it into a subreg for
3890 the new mode. However, because of REG sharing and
3891 because its mode had already changed, we have to do
3892 it in two steps. First, replace any debug uses of
3893 reg, with its original mode temporarily restored,
3894 with this copy we have created; then, replace the
3895 copy with the SUBREG of the original shared reg,
3896 once again changed to the new mode. */
3897 propagate_for_debug (first, last, reg, tempreg);
3898 adjust_reg_mode (reg, new_mode);
3899 propagate_for_debug (first, last, tempreg,
3900 lowpart_subreg (old_mode, reg, new_mode));
3905 /* If we will be able to accept this, we have made a
3906 change to the destination of I3. This requires us to
3907 do a few adjustments. */
3909 if (changed_i3_dest)
3911 PATTERN (i3) = newpat;
3912 adjust_for_new_dest (i3);
3915 /* We now know that we can do this combination. Merge the insns and
3916 update the status of registers and LOG_LINKS. */
3918 if (undobuf.other_insn)
3922 PATTERN (undobuf.other_insn) = other_pat;
3924 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
3925 are still valid. Then add any non-duplicate notes added by
3926 recog_for_combine. */
3927 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
3929 next = XEXP (note, 1);
3931 if (REG_NOTE_KIND (note) == REG_UNUSED
3932 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
3933 remove_note (undobuf.other_insn, note);
3936 distribute_notes (new_other_notes, undobuf.other_insn,
3937 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX,
3944 struct insn_link *link;
3947 /* I3 now uses what used to be its destination and which is now
3948 I2's destination. This requires us to do a few adjustments. */
3949 PATTERN (i3) = newpat;
3950 adjust_for_new_dest (i3);
3952 /* We need a LOG_LINK from I3 to I2. But we used to have one,
3955 However, some later insn might be using I2's dest and have
3956 a LOG_LINK pointing at I3. We must remove this link.
3957 The simplest way to remove the link is to point it at I1,
3958 which we know will be a NOTE. */
3960 /* newi2pat is usually a SET here; however, recog_for_combine might
3961 have added some clobbers. */
3962 if (GET_CODE (newi2pat) == PARALLEL)
3963 ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
3965 ni2dest = SET_DEST (newi2pat);
3967 for (insn = NEXT_INSN (i3);
3968 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3969 || insn != BB_HEAD (this_basic_block->next_bb));
3970 insn = NEXT_INSN (insn))
3972 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
3974 FOR_EACH_LOG_LINK (link, insn)
3975 if (link->insn == i3)
3984 rtx i3notes, i2notes, i1notes = 0, i0notes = 0;
3985 struct insn_link *i3links, *i2links, *i1links = 0, *i0links = 0;
3988 /* Compute which registers we expect to eliminate. newi2pat may be setting
3989 either i3dest or i2dest, so we must check it. Also, i1dest may be the
3990 same as i3dest, in which case newi2pat may be setting i1dest. */
3991 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
3992 || i2dest_in_i2src || i2dest_in_i1src || i2dest_in_i0src
3995 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src || i1dest_in_i0src
3996 || (newi2pat && reg_set_p (i1dest, newi2pat))
3999 rtx elim_i0 = (i0 == 0 || i0dest_in_i0src
4000 || (newi2pat && reg_set_p (i0dest, newi2pat))
4004 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4006 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
4007 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
4009 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
4011 i0notes = REG_NOTES (i0), i0links = LOG_LINKS (i0);
4013 /* Ensure that we do not have something that should not be shared but
4014 occurs multiple times in the new insns. Check this by first
4015 resetting all the `used' flags and then copying anything is shared. */
4017 reset_used_flags (i3notes);
4018 reset_used_flags (i2notes);
4019 reset_used_flags (i1notes);
4020 reset_used_flags (i0notes);
4021 reset_used_flags (newpat);
4022 reset_used_flags (newi2pat);
4023 if (undobuf.other_insn)
4024 reset_used_flags (PATTERN (undobuf.other_insn));
4026 i3notes = copy_rtx_if_shared (i3notes);
4027 i2notes = copy_rtx_if_shared (i2notes);
4028 i1notes = copy_rtx_if_shared (i1notes);
4029 i0notes = copy_rtx_if_shared (i0notes);
4030 newpat = copy_rtx_if_shared (newpat);
4031 newi2pat = copy_rtx_if_shared (newi2pat);
4032 if (undobuf.other_insn)
4033 reset_used_flags (PATTERN (undobuf.other_insn));
4035 INSN_CODE (i3) = insn_code_number;
4036 PATTERN (i3) = newpat;
4038 if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
4040 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
4042 reset_used_flags (call_usage);
4043 call_usage = copy_rtx (call_usage);
4047 /* I2SRC must still be meaningful at this point. Some splitting
4048 operations can invalidate I2SRC, but those operations do not
4051 replace_rtx (call_usage, i2dest, i2src);
4055 replace_rtx (call_usage, i1dest, i1src);
4057 replace_rtx (call_usage, i0dest, i0src);
4059 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
4062 if (undobuf.other_insn)
4063 INSN_CODE (undobuf.other_insn) = other_code_number;
4065 /* We had one special case above where I2 had more than one set and
4066 we replaced a destination of one of those sets with the destination
4067 of I3. In that case, we have to update LOG_LINKS of insns later
4068 in this basic block. Note that this (expensive) case is rare.
4070 Also, in this case, we must pretend that all REG_NOTEs for I2
4071 actually came from I3, so that REG_UNUSED notes from I2 will be
4072 properly handled. */
4074 if (i3_subst_into_i2)
4076 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
4077 if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
4078 || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
4079 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
4080 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
4081 && ! find_reg_note (i2, REG_UNUSED,
4082 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
4083 for (temp = NEXT_INSN (i2);
4084 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
4085 || BB_HEAD (this_basic_block) != temp);
4086 temp = NEXT_INSN (temp))
4087 if (temp != i3 && INSN_P (temp))
4088 FOR_EACH_LOG_LINK (link, temp)
4089 if (link->insn == i2)
4095 while (XEXP (link, 1))
4096 link = XEXP (link, 1);
4097 XEXP (link, 1) = i2notes;
4104 LOG_LINKS (i3) = NULL;
4106 LOG_LINKS (i2) = NULL;
4111 if (MAY_HAVE_DEBUG_INSNS && i2scratch)
4112 propagate_for_debug (i2, i3, i2dest, i2src);
4113 INSN_CODE (i2) = i2_code_number;
4114 PATTERN (i2) = newi2pat;
4118 if (MAY_HAVE_DEBUG_INSNS && i2src)
4119 propagate_for_debug (i2, i3, i2dest, i2src);
4120 SET_INSN_DELETED (i2);
4125 LOG_LINKS (i1) = NULL;
4127 if (MAY_HAVE_DEBUG_INSNS)
4128 propagate_for_debug (i1, i3, i1dest, i1src);
4129 SET_INSN_DELETED (i1);
4134 LOG_LINKS (i0) = NULL;
4136 if (MAY_HAVE_DEBUG_INSNS)
4137 propagate_for_debug (i0, i3, i0dest, i0src);
4138 SET_INSN_DELETED (i0);
4141 /* Get death notes for everything that is now used in either I3 or
4142 I2 and used to die in a previous insn. If we built two new
4143 patterns, move from I1 to I2 then I2 to I3 so that we get the
4144 proper movement on registers that I2 modifies. */
4147 from_luid = DF_INSN_LUID (i0);
4149 from_luid = DF_INSN_LUID (i1);
4151 from_luid = DF_INSN_LUID (i2);
4153 move_deaths (newi2pat, NULL_RTX, from_luid, i2, &midnotes);
4154 move_deaths (newpat, newi2pat, from_luid, i3, &midnotes);
4156 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4158 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
4159 elim_i2, elim_i1, elim_i0);
4161 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
4162 elim_i2, elim_i1, elim_i0);
4164 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
4165 elim_i2, elim_i1, elim_i0);
4167 distribute_notes (i0notes, i0, i3, newi2pat ? i2 : NULL_RTX,
4168 elim_i2, elim_i1, elim_i0);
4170 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4171 elim_i2, elim_i1, elim_i0);
4173 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4174 know these are REG_UNUSED and want them to go to the desired insn,
4175 so we always pass it as i3. */
4177 if (newi2pat && new_i2_notes)
4178 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX,
4182 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX,
4185 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4186 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4187 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4188 in that case, it might delete I2. Similarly for I2 and I1.
4189 Show an additional death due to the REG_DEAD note we make here. If
4190 we discard it in distribute_notes, we will decrement it again. */
4194 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
4195 distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
4197 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1, elim_i0);
4199 distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
4201 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4202 elim_i2, elim_i1, elim_i0);
4205 if (i2dest_in_i2src)
4207 rtx new_note = alloc_reg_note (REG_DEAD, i2dest, NULL_RTX);
4208 if (newi2pat && reg_set_p (i2dest, newi2pat))
4209 distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4210 NULL_RTX, NULL_RTX);
4212 distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4213 NULL_RTX, NULL_RTX, NULL_RTX);
4216 if (i1dest_in_i1src)
4218 rtx new_note = alloc_reg_note (REG_DEAD, i1dest, NULL_RTX);
4219 if (newi2pat && reg_set_p (i1dest, newi2pat))
4220 distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4221 NULL_RTX, NULL_RTX);
4223 distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4224 NULL_RTX, NULL_RTX, NULL_RTX);
4227 if (i0dest_in_i0src)
4229 rtx new_note = alloc_reg_note (REG_DEAD, i0dest, NULL_RTX);
4230 if (newi2pat && reg_set_p (i0dest, newi2pat))
4231 distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4232 NULL_RTX, NULL_RTX);
4234 distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4235 NULL_RTX, NULL_RTX, NULL_RTX);
4238 distribute_links (i3links);
4239 distribute_links (i2links);
4240 distribute_links (i1links);
4241 distribute_links (i0links);
4245 struct insn_link *link;
4246 rtx i2_insn = 0, i2_val = 0, set;
4248 /* The insn that used to set this register doesn't exist, and
4249 this life of the register may not exist either. See if one of
4250 I3's links points to an insn that sets I2DEST. If it does,
4251 that is now the last known value for I2DEST. If we don't update
4252 this and I2 set the register to a value that depended on its old
4253 contents, we will get confused. If this insn is used, thing
4254 will be set correctly in combine_instructions. */
4255 FOR_EACH_LOG_LINK (link, i3)
4256 if ((set = single_set (link->insn)) != 0
4257 && rtx_equal_p (i2dest, SET_DEST (set)))
4258 i2_insn = link->insn, i2_val = SET_SRC (set);
4260 record_value_for_reg (i2dest, i2_insn, i2_val);
4262 /* If the reg formerly set in I2 died only once and that was in I3,
4263 zero its use count so it won't make `reload' do any work. */
4265 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
4266 && ! i2dest_in_i2src)
4267 INC_REG_N_SETS (REGNO (i2dest), -1);
4270 if (i1 && REG_P (i1dest))
4272 struct insn_link *link;
4273 rtx i1_insn = 0, i1_val = 0, set;
4275 FOR_EACH_LOG_LINK (link, i3)
4276 if ((set = single_set (link->insn)) != 0
4277 && rtx_equal_p (i1dest, SET_DEST (set)))
4278 i1_insn = link->insn, i1_val = SET_SRC (set);
4280 record_value_for_reg (i1dest, i1_insn, i1_val);
4282 if (! added_sets_1 && ! i1dest_in_i1src)
4283 INC_REG_N_SETS (REGNO (i1dest), -1);
4286 if (i0 && REG_P (i0dest))
4288 struct insn_link *link;
4289 rtx i0_insn = 0, i0_val = 0, set;
4291 FOR_EACH_LOG_LINK (link, i3)
4292 if ((set = single_set (link->insn)) != 0
4293 && rtx_equal_p (i0dest, SET_DEST (set)))
4294 i0_insn = link->insn, i0_val = SET_SRC (set);
4296 record_value_for_reg (i0dest, i0_insn, i0_val);
4298 if (! added_sets_0 && ! i0dest_in_i0src)
4299 INC_REG_N_SETS (REGNO (i0dest), -1);
4302 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4303 been made to this insn. The order of
4304 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
4305 can affect nonzero_bits of newpat */
4307 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
4308 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
4311 if (undobuf.other_insn != NULL_RTX)
4315 fprintf (dump_file, "modifying other_insn ");
4316 dump_insn_slim (dump_file, undobuf.other_insn);
4318 df_insn_rescan (undobuf.other_insn);
4321 if (i0 && !(NOTE_P(i0) && (NOTE_KIND (i0) == NOTE_INSN_DELETED)))
4325 fprintf (dump_file, "modifying insn i1 ");
4326 dump_insn_slim (dump_file, i0);
4328 df_insn_rescan (i0);
4331 if (i1 && !(NOTE_P(i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED)))
4335 fprintf (dump_file, "modifying insn i1 ");
4336 dump_insn_slim (dump_file, i1);
4338 df_insn_rescan (i1);
4341 if (i2 && !(NOTE_P(i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED)))
4345 fprintf (dump_file, "modifying insn i2 ");
4346 dump_insn_slim (dump_file, i2);
4348 df_insn_rescan (i2);
4351 if (i3 && !(NOTE_P(i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED)))
4355 fprintf (dump_file, "modifying insn i3 ");
4356 dump_insn_slim (dump_file, i3);
4358 df_insn_rescan (i3);
4361 /* Set new_direct_jump_p if a new return or simple jump instruction
4362 has been created. Adjust the CFG accordingly. */
4364 if (returnjump_p (i3) || any_uncondjump_p (i3))
4366 *new_direct_jump_p = 1;
4367 mark_jump_label (PATTERN (i3), i3, 0);
4368 update_cfg_for_uncondjump (i3);
4371 if (undobuf.other_insn != NULL_RTX
4372 && (returnjump_p (undobuf.other_insn)
4373 || any_uncondjump_p (undobuf.other_insn)))
4375 *new_direct_jump_p = 1;
4376 update_cfg_for_uncondjump (undobuf.other_insn);
4379 /* A noop might also need cleaning up of CFG, if it comes from the
4380 simplification of a jump. */
4381 if (GET_CODE (newpat) == SET
4382 && SET_SRC (newpat) == pc_rtx
4383 && SET_DEST (newpat) == pc_rtx)
4385 *new_direct_jump_p = 1;
4386 update_cfg_for_uncondjump (i3);
4389 if (undobuf.other_insn != NULL_RTX
4390 && GET_CODE (PATTERN (undobuf.other_insn)) == SET
4391 && SET_SRC (PATTERN (undobuf.other_insn)) == pc_rtx
4392 && SET_DEST (PATTERN (undobuf.other_insn)) == pc_rtx)
4394 *new_direct_jump_p = 1;
4395 update_cfg_for_uncondjump (undobuf.other_insn);
4398 combine_successes++;
4401 if (added_links_insn
4402 && (newi2pat == 0 || DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i2))
4403 && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i3))
4404 return added_links_insn;
4406 return newi2pat ? i2 : i3;
4409 /* Undo all the modifications recorded in undobuf. */
4414 struct undo *undo, *next;
4416 for (undo = undobuf.undos; undo; undo = next)
4422 *undo->where.r = undo->old_contents.r;
4425 *undo->where.i = undo->old_contents.i;
4428 adjust_reg_mode (*undo->where.r, undo->old_contents.m);
4434 undo->next = undobuf.frees;
4435 undobuf.frees = undo;
4441 /* We've committed to accepting the changes we made. Move all
4442 of the undos to the free list. */
4447 struct undo *undo, *next;
4449 for (undo = undobuf.undos; undo; undo = next)
4452 undo->next = undobuf.frees;
4453 undobuf.frees = undo;
4458 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4459 where we have an arithmetic expression and return that point. LOC will
4462 try_combine will call this function to see if an insn can be split into
4466 find_split_point (rtx *loc, rtx insn, bool set_src)
4469 enum rtx_code code = GET_CODE (x);
4471 unsigned HOST_WIDE_INT len = 0;
4472 HOST_WIDE_INT pos = 0;
4474 rtx inner = NULL_RTX;
4476 /* First special-case some codes. */
4480 #ifdef INSN_SCHEDULING
4481 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4483 if (MEM_P (SUBREG_REG (x)))
4486 return find_split_point (&SUBREG_REG (x), insn, false);
4490 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4491 using LO_SUM and HIGH. */
4492 if (GET_CODE (XEXP (x, 0)) == CONST
4493 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
4495 enum machine_mode address_mode
4496 = targetm.addr_space.address_mode (MEM_ADDR_SPACE (x));
4499 gen_rtx_LO_SUM (address_mode,
4500 gen_rtx_HIGH (address_mode, XEXP (x, 0)),
4502 return &XEXP (XEXP (x, 0), 0);
4506 /* If we have a PLUS whose second operand is a constant and the
4507 address is not valid, perhaps will can split it up using
4508 the machine-specific way to split large constants. We use
4509 the first pseudo-reg (one of the virtual regs) as a placeholder;
4510 it will not remain in the result. */
4511 if (GET_CODE (XEXP (x, 0)) == PLUS
4512 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
4513 && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4514 MEM_ADDR_SPACE (x)))
4516 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
4517 rtx seq = combine_split_insns (gen_rtx_SET (VOIDmode, reg,
4521 /* This should have produced two insns, each of which sets our
4522 placeholder. If the source of the second is a valid address,
4523 we can make put both sources together and make a split point
4527 && NEXT_INSN (seq) != NULL_RTX
4528 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
4529 && NONJUMP_INSN_P (seq)
4530 && GET_CODE (PATTERN (seq)) == SET
4531 && SET_DEST (PATTERN (seq)) == reg
4532 && ! reg_mentioned_p (reg,
4533 SET_SRC (PATTERN (seq)))
4534 && NONJUMP_INSN_P (NEXT_INSN (seq))
4535 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
4536 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
4537 && memory_address_addr_space_p
4538 (GET_MODE (x), SET_SRC (PATTERN (NEXT_INSN (seq))),
4539 MEM_ADDR_SPACE (x)))
4541 rtx src1 = SET_SRC (PATTERN (seq));
4542 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
4544 /* Replace the placeholder in SRC2 with SRC1. If we can
4545 find where in SRC2 it was placed, that can become our
4546 split point and we can replace this address with SRC2.
4547 Just try two obvious places. */
4549 src2 = replace_rtx (src2, reg, src1);
4551 if (XEXP (src2, 0) == src1)
4552 split = &XEXP (src2, 0);
4553 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
4554 && XEXP (XEXP (src2, 0), 0) == src1)
4555 split = &XEXP (XEXP (src2, 0), 0);
4559 SUBST (XEXP (x, 0), src2);
4564 /* If that didn't work, perhaps the first operand is complex and
4565 needs to be computed separately, so make a split point there.
4566 This will occur on machines that just support REG + CONST
4567 and have a constant moved through some previous computation. */
4569 else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
4570 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4571 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4572 return &XEXP (XEXP (x, 0), 0);
4575 /* If we have a PLUS whose first operand is complex, try computing it
4576 separately by making a split there. */
4577 if (GET_CODE (XEXP (x, 0)) == PLUS
4578 && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4580 && ! OBJECT_P (XEXP (XEXP (x, 0), 0))
4581 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4582 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4583 return &XEXP (XEXP (x, 0), 0);
4588 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4589 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4590 we need to put the operand into a register. So split at that
4593 if (SET_DEST (x) == cc0_rtx
4594 && GET_CODE (SET_SRC (x)) != COMPARE
4595 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
4596 && !OBJECT_P (SET_SRC (x))
4597 && ! (GET_CODE (SET_SRC (x)) == SUBREG
4598 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
4599 return &SET_SRC (x);
4602 /* See if we can split SET_SRC as it stands. */
4603 split = find_split_point (&SET_SRC (x), insn, true);
4604 if (split && split != &SET_SRC (x))
4607 /* See if we can split SET_DEST as it stands. */
4608 split = find_split_point (&SET_DEST (x), insn, false);
4609 if (split && split != &SET_DEST (x))
4612 /* See if this is a bitfield assignment with everything constant. If
4613 so, this is an IOR of an AND, so split it into that. */
4614 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
4615 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
4616 <= HOST_BITS_PER_WIDE_INT)
4617 && CONST_INT_P (XEXP (SET_DEST (x), 1))
4618 && CONST_INT_P (XEXP (SET_DEST (x), 2))
4619 && CONST_INT_P (SET_SRC (x))
4620 && ((INTVAL (XEXP (SET_DEST (x), 1))
4621 + INTVAL (XEXP (SET_DEST (x), 2)))
4622 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
4623 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
4625 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
4626 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
4627 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
4628 rtx dest = XEXP (SET_DEST (x), 0);
4629 enum machine_mode mode = GET_MODE (dest);
4630 unsigned HOST_WIDE_INT mask
4631 = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
4634 if (BITS_BIG_ENDIAN)
4635 pos = GET_MODE_BITSIZE (mode) - len - pos;
4637 or_mask = gen_int_mode (src << pos, mode);
4640 simplify_gen_binary (IOR, mode, dest, or_mask));
4643 rtx negmask = gen_int_mode (~(mask << pos), mode);
4645 simplify_gen_binary (IOR, mode,
4646 simplify_gen_binary (AND, mode,
4651 SUBST (SET_DEST (x), dest);
4653 split = find_split_point (&SET_SRC (x), insn, true);
4654 if (split && split != &SET_SRC (x))
4658 /* Otherwise, see if this is an operation that we can split into two.
4659 If so, try to split that. */
4660 code = GET_CODE (SET_SRC (x));
4665 /* If we are AND'ing with a large constant that is only a single
4666 bit and the result is only being used in a context where we
4667 need to know if it is zero or nonzero, replace it with a bit
4668 extraction. This will avoid the large constant, which might
4669 have taken more than one insn to make. If the constant were
4670 not a valid argument to the AND but took only one insn to make,
4671 this is no worse, but if it took more than one insn, it will
4674 if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4675 && REG_P (XEXP (SET_SRC (x), 0))
4676 && (pos = exact_log2 (UINTVAL (XEXP (SET_SRC (x), 1)))) >= 7
4677 && REG_P (SET_DEST (x))
4678 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
4679 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
4680 && XEXP (*split, 0) == SET_DEST (x)
4681 && XEXP (*split, 1) == const0_rtx)
4683 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
4684 XEXP (SET_SRC (x), 0),
4685 pos, NULL_RTX, 1, 1, 0, 0);
4686 if (extraction != 0)
4688 SUBST (SET_SRC (x), extraction);
4689 return find_split_point (loc, insn, false);
4695 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4696 is known to be on, this can be converted into a NEG of a shift. */
4697 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
4698 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
4699 && 1 <= (pos = exact_log2
4700 (nonzero_bits (XEXP (SET_SRC (x), 0),
4701 GET_MODE (XEXP (SET_SRC (x), 0))))))
4703 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
4707 gen_rtx_LSHIFTRT (mode,
4708 XEXP (SET_SRC (x), 0),
4711 split = find_split_point (&SET_SRC (x), insn, true);
4712 if (split && split != &SET_SRC (x))
4718 inner = XEXP (SET_SRC (x), 0);
4720 /* We can't optimize if either mode is a partial integer
4721 mode as we don't know how many bits are significant
4723 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
4724 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
4728 len = GET_MODE_BITSIZE (GET_MODE (inner));
4734 if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4735 && CONST_INT_P (XEXP (SET_SRC (x), 2)))
4737 inner = XEXP (SET_SRC (x), 0);
4738 len = INTVAL (XEXP (SET_SRC (x), 1));
4739 pos = INTVAL (XEXP (SET_SRC (x), 2));
4741 if (BITS_BIG_ENDIAN)
4742 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
4743 unsignedp = (code == ZERO_EXTRACT);
4751 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
4753 enum machine_mode mode = GET_MODE (SET_SRC (x));
4755 /* For unsigned, we have a choice of a shift followed by an
4756 AND or two shifts. Use two shifts for field sizes where the
4757 constant might be too large. We assume here that we can
4758 always at least get 8-bit constants in an AND insn, which is
4759 true for every current RISC. */
4761 if (unsignedp && len <= 8)
4766 (mode, gen_lowpart (mode, inner),
4768 GEN_INT (((unsigned HOST_WIDE_INT) 1 << len)
4771 split = find_split_point (&SET_SRC (x), insn, true);
4772 if (split && split != &SET_SRC (x))
4779 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
4780 gen_rtx_ASHIFT (mode,
4781 gen_lowpart (mode, inner),
4782 GEN_INT (GET_MODE_BITSIZE (mode)
4784 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
4786 split = find_split_point (&SET_SRC (x), insn, true);
4787 if (split && split != &SET_SRC (x))
4792 /* See if this is a simple operation with a constant as the second
4793 operand. It might be that this constant is out of range and hence
4794 could be used as a split point. */
4795 if (BINARY_P (SET_SRC (x))
4796 && CONSTANT_P (XEXP (SET_SRC (x), 1))
4797 && (OBJECT_P (XEXP (SET_SRC (x), 0))
4798 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
4799 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
4800 return &XEXP (SET_SRC (x), 1);
4802 /* Finally, see if this is a simple operation with its first operand
4803 not in a register. The operation might require this operand in a
4804 register, so return it as a split point. We can always do this
4805 because if the first operand were another operation, we would have
4806 already found it as a split point. */
4807 if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
4808 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
4809 return &XEXP (SET_SRC (x), 0);
4815 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4816 it is better to write this as (not (ior A B)) so we can split it.
4817 Similarly for IOR. */
4818 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
4821 gen_rtx_NOT (GET_MODE (x),
4822 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
4824 XEXP (XEXP (x, 0), 0),
4825 XEXP (XEXP (x, 1), 0))));
4826 return find_split_point (loc, insn, set_src);
4829 /* Many RISC machines have a large set of logical insns. If the
4830 second operand is a NOT, put it first so we will try to split the
4831 other operand first. */
4832 if (GET_CODE (XEXP (x, 1)) == NOT)
4834 rtx tem = XEXP (x, 0);
4835 SUBST (XEXP (x, 0), XEXP (x, 1));
4836 SUBST (XEXP (x, 1), tem);
4842 /* Canonicalization can produce (minus A (mult B C)), where C is a
4843 constant. It may be better to try splitting (plus (mult B -C) A)
4844 instead if this isn't a multiply by a power of two. */
4845 if (set_src && code == MINUS && GET_CODE (XEXP (x, 1)) == MULT
4846 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4847 && exact_log2 (INTVAL (XEXP (XEXP (x, 1), 1))) < 0)
4849 enum machine_mode mode = GET_MODE (x);
4850 unsigned HOST_WIDE_INT this_int = INTVAL (XEXP (XEXP (x, 1), 1));
4851 HOST_WIDE_INT other_int = trunc_int_for_mode (-this_int, mode);
4852 SUBST (*loc, gen_rtx_PLUS (mode, gen_rtx_MULT (mode,
4853 XEXP (XEXP (x, 1), 0),
4854 GEN_INT (other_int)),
4856 return find_split_point (loc, insn, set_src);
4859 /* Split at a multiply-accumulate instruction. However if this is
4860 the SET_SRC, we likely do not have such an instruction and it's
4861 worthless to try this split. */
4862 if (!set_src && GET_CODE (XEXP (x, 0)) == MULT)
4869 /* Otherwise, select our actions depending on our rtx class. */
4870 switch (GET_RTX_CLASS (code))
4872 case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
4874 split = find_split_point (&XEXP (x, 2), insn, false);
4877 /* ... fall through ... */
4879 case RTX_COMM_ARITH:
4881 case RTX_COMM_COMPARE:
4882 split = find_split_point (&XEXP (x, 1), insn, false);
4885 /* ... fall through ... */
4887 /* Some machines have (and (shift ...) ...) insns. If X is not
4888 an AND, but XEXP (X, 0) is, use it as our split point. */
4889 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
4890 return &XEXP (x, 0);
4892 split = find_split_point (&XEXP (x, 0), insn, false);
4898 /* Otherwise, we don't have a split point. */
4903 /* Throughout X, replace FROM with TO, and return the result.
4904 The result is TO if X is FROM;
4905 otherwise the result is X, but its contents may have been modified.
4906 If they were modified, a record was made in undobuf so that
4907 undo_all will (among other things) return X to its original state.
4909 If the number of changes necessary is too much to record to undo,
4910 the excess changes are not made, so the result is invalid.
4911 The changes already made can still be undone.
4912 undobuf.num_undo is incremented for such changes, so by testing that
4913 the caller can tell whether the result is valid.
4915 `n_occurrences' is incremented each time FROM is replaced.
4917 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4919 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
4920 by copying if `n_occurrences' is nonzero. */
4923 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
4925 enum rtx_code code = GET_CODE (x);
4926 enum machine_mode op0_mode = VOIDmode;
4931 /* Two expressions are equal if they are identical copies of a shared
4932 RTX or if they are both registers with the same register number
4935 #define COMBINE_RTX_EQUAL_P(X,Y) \
4937 || (REG_P (X) && REG_P (Y) \
4938 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4940 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
4943 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
4946 /* If X and FROM are the same register but different modes, they
4947 will not have been seen as equal above. However, the log links code
4948 will make a LOG_LINKS entry for that case. If we do nothing, we
4949 will try to rerecognize our original insn and, when it succeeds,
4950 we will delete the feeding insn, which is incorrect.
4952 So force this insn not to match in this (rare) case. */
4953 if (! in_dest && code == REG && REG_P (from)
4954 && reg_overlap_mentioned_p (x, from))
4955 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
4957 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4958 of which may contain things that can be combined. */
4959 if (code != MEM && code != LO_SUM && OBJECT_P (x))
4962 /* It is possible to have a subexpression appear twice in the insn.
4963 Suppose that FROM is a register that appears within TO.
4964 Then, after that subexpression has been scanned once by `subst',
4965 the second time it is scanned, TO may be found. If we were
4966 to scan TO here, we would find FROM within it and create a
4967 self-referent rtl structure which is completely wrong. */
4968 if (COMBINE_RTX_EQUAL_P (x, to))
4971 /* Parallel asm_operands need special attention because all of the
4972 inputs are shared across the arms. Furthermore, unsharing the
4973 rtl results in recognition failures. Failure to handle this case
4974 specially can result in circular rtl.
4976 Solve this by doing a normal pass across the first entry of the
4977 parallel, and only processing the SET_DESTs of the subsequent
4980 if (code == PARALLEL
4981 && GET_CODE (XVECEXP (x, 0, 0)) == SET
4982 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
4984 new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
4986 /* If this substitution failed, this whole thing fails. */
4987 if (GET_CODE (new_rtx) == CLOBBER
4988 && XEXP (new_rtx, 0) == const0_rtx)
4991 SUBST (XVECEXP (x, 0, 0), new_rtx);
4993 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
4995 rtx dest = SET_DEST (XVECEXP (x, 0, i));
4998 && GET_CODE (dest) != CC0
4999 && GET_CODE (dest) != PC)
5001 new_rtx = subst (dest, from, to, 0, unique_copy);
5003 /* If this substitution failed, this whole thing fails. */
5004 if (GET_CODE (new_rtx) == CLOBBER
5005 && XEXP (new_rtx, 0) == const0_rtx)
5008 SUBST (SET_DEST (XVECEXP (x, 0, i)), new_rtx);
5014 len = GET_RTX_LENGTH (code);
5015 fmt = GET_RTX_FORMAT (code);
5017 /* We don't need to process a SET_DEST that is a register, CC0,
5018 or PC, so set up to skip this common case. All other cases
5019 where we want to suppress replacing something inside a
5020 SET_SRC are handled via the IN_DEST operand. */
5022 && (REG_P (SET_DEST (x))
5023 || GET_CODE (SET_DEST (x)) == CC0
5024 || GET_CODE (SET_DEST (x)) == PC))
5027 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5030 op0_mode = GET_MODE (XEXP (x, 0));
5032 for (i = 0; i < len; i++)
5037 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5039 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
5041 new_rtx = (unique_copy && n_occurrences
5042 ? copy_rtx (to) : to);
5047 new_rtx = subst (XVECEXP (x, i, j), from, to, 0,
5050 /* If this substitution failed, this whole thing
5052 if (GET_CODE (new_rtx) == CLOBBER
5053 && XEXP (new_rtx, 0) == const0_rtx)
5057 SUBST (XVECEXP (x, i, j), new_rtx);
5060 else if (fmt[i] == 'e')
5062 /* If this is a register being set, ignore it. */
5063 new_rtx = XEXP (x, i);
5066 && (((code == SUBREG || code == ZERO_EXTRACT)
5068 || code == STRICT_LOW_PART))
5071 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
5073 /* In general, don't install a subreg involving two
5074 modes not tieable. It can worsen register
5075 allocation, and can even make invalid reload
5076 insns, since the reg inside may need to be copied
5077 from in the outside mode, and that may be invalid
5078 if it is an fp reg copied in integer mode.
5080 We allow two exceptions to this: It is valid if
5081 it is inside another SUBREG and the mode of that
5082 SUBREG and the mode of the inside of TO is
5083 tieable and it is valid if X is a SET that copies
5086 if (GET_CODE (to) == SUBREG
5087 && ! MODES_TIEABLE_P (GET_MODE (to),
5088 GET_MODE (SUBREG_REG (to)))
5089 && ! (code == SUBREG
5090 && MODES_TIEABLE_P (GET_MODE (x),
5091 GET_MODE (SUBREG_REG (to))))
5093 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
5096 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5098 #ifdef CANNOT_CHANGE_MODE_CLASS
5101 && REGNO (to) < FIRST_PSEUDO_REGISTER
5102 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
5105 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5108 new_rtx = (unique_copy && n_occurrences ? copy_rtx (to) : to);
5112 /* If we are in a SET_DEST, suppress most cases unless we
5113 have gone inside a MEM, in which case we want to
5114 simplify the address. We assume here that things that
5115 are actually part of the destination have their inner
5116 parts in the first expression. This is true for SUBREG,
5117 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5118 things aside from REG and MEM that should appear in a
5120 new_rtx = subst (XEXP (x, i), from, to,
5122 && (code == SUBREG || code == STRICT_LOW_PART
5123 || code == ZERO_EXTRACT))
5125 && i == 0), unique_copy);
5127 /* If we found that we will have to reject this combination,
5128 indicate that by returning the CLOBBER ourselves, rather than
5129 an expression containing it. This will speed things up as
5130 well as prevent accidents where two CLOBBERs are considered
5131 to be equal, thus producing an incorrect simplification. */
5133 if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx)
5136 if (GET_CODE (x) == SUBREG
5137 && (CONST_INT_P (new_rtx)
5138 || GET_CODE (new_rtx) == CONST_DOUBLE))
5140 enum machine_mode mode = GET_MODE (x);
5142 x = simplify_subreg (GET_MODE (x), new_rtx,
5143 GET_MODE (SUBREG_REG (x)),
5146 x = gen_rtx_CLOBBER (mode, const0_rtx);
5148 else if (CONST_INT_P (new_rtx)
5149 && GET_CODE (x) == ZERO_EXTEND)
5151 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
5152 new_rtx, GET_MODE (XEXP (x, 0)));
5156 SUBST (XEXP (x, i), new_rtx);
5161 /* Check if we are loading something from the constant pool via float
5162 extension; in this case we would undo compress_float_constant
5163 optimization and degenerate constant load to an immediate value. */
5164 if (GET_CODE (x) == FLOAT_EXTEND
5165 && MEM_P (XEXP (x, 0))
5166 && MEM_READONLY_P (XEXP (x, 0)))
5168 rtx tmp = avoid_constant_pool_reference (x);
5173 /* Try to simplify X. If the simplification changed the code, it is likely
5174 that further simplification will help, so loop, but limit the number
5175 of repetitions that will be performed. */
5177 for (i = 0; i < 4; i++)
5179 /* If X is sufficiently simple, don't bother trying to do anything
5181 if (code != CONST_INT && code != REG && code != CLOBBER)
5182 x = combine_simplify_rtx (x, op0_mode, in_dest);
5184 if (GET_CODE (x) == code)
5187 code = GET_CODE (x);
5189 /* We no longer know the original mode of operand 0 since we
5190 have changed the form of X) */
5191 op0_mode = VOIDmode;
5197 /* Simplify X, a piece of RTL. We just operate on the expression at the
5198 outer level; call `subst' to simplify recursively. Return the new
5201 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5202 if we are inside a SET_DEST. */
5205 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
5207 enum rtx_code code = GET_CODE (x);
5208 enum machine_mode mode = GET_MODE (x);
5212 /* If this is a commutative operation, put a constant last and a complex
5213 expression first. We don't need to do this for comparisons here. */
5214 if (COMMUTATIVE_ARITH_P (x)
5215 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
5218 SUBST (XEXP (x, 0), XEXP (x, 1));
5219 SUBST (XEXP (x, 1), temp);
5222 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5223 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5224 things. Check for cases where both arms are testing the same
5227 Don't do anything if all operands are very simple. */
5230 && ((!OBJECT_P (XEXP (x, 0))
5231 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5232 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
5233 || (!OBJECT_P (XEXP (x, 1))
5234 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
5235 && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
5237 && (!OBJECT_P (XEXP (x, 0))
5238 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5239 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
5241 rtx cond, true_rtx, false_rtx;
5243 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
5245 /* If everything is a comparison, what we have is highly unlikely
5246 to be simpler, so don't use it. */
5247 && ! (COMPARISON_P (x)
5248 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
5250 rtx cop1 = const0_rtx;
5251 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
5253 if (cond_code == NE && COMPARISON_P (cond))
5256 /* Simplify the alternative arms; this may collapse the true and
5257 false arms to store-flag values. Be careful to use copy_rtx
5258 here since true_rtx or false_rtx might share RTL with x as a
5259 result of the if_then_else_cond call above. */
5260 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
5261 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
5263 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5264 is unlikely to be simpler. */
5265 if (general_operand (true_rtx, VOIDmode)
5266 && general_operand (false_rtx, VOIDmode))
5268 enum rtx_code reversed;
5270 /* Restarting if we generate a store-flag expression will cause
5271 us to loop. Just drop through in this case. */
5273 /* If the result values are STORE_FLAG_VALUE and zero, we can
5274 just make the comparison operation. */
5275 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
5276 x = simplify_gen_relational (cond_code, mode, VOIDmode,
5278 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
5279 && ((reversed = reversed_comparison_code_parts
5280 (cond_code, cond, cop1, NULL))
5282 x = simplify_gen_relational (reversed, mode, VOIDmode,
5285 /* Likewise, we can make the negate of a comparison operation
5286 if the result values are - STORE_FLAG_VALUE and zero. */
5287 else if (CONST_INT_P (true_rtx)
5288 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
5289 && false_rtx == const0_rtx)
5290 x = simplify_gen_unary (NEG, mode,
5291 simplify_gen_relational (cond_code,
5295 else if (CONST_INT_P (false_rtx)
5296 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
5297 && true_rtx == const0_rtx
5298 && ((reversed = reversed_comparison_code_parts
5299 (cond_code, cond, cop1, NULL))
5301 x = simplify_gen_unary (NEG, mode,
5302 simplify_gen_relational (reversed,
5307 return gen_rtx_IF_THEN_ELSE (mode,
5308 simplify_gen_relational (cond_code,
5313 true_rtx, false_rtx);
5315 code = GET_CODE (x);
5316 op0_mode = VOIDmode;
5321 /* Try to fold this expression in case we have constants that weren't
5324 switch (GET_RTX_CLASS (code))
5327 if (op0_mode == VOIDmode)
5328 op0_mode = GET_MODE (XEXP (x, 0));
5329 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
5332 case RTX_COMM_COMPARE:
5334 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
5335 if (cmp_mode == VOIDmode)
5337 cmp_mode = GET_MODE (XEXP (x, 1));
5338 if (cmp_mode == VOIDmode)
5339 cmp_mode = op0_mode;
5341 temp = simplify_relational_operation (code, mode, cmp_mode,
5342 XEXP (x, 0), XEXP (x, 1));
5345 case RTX_COMM_ARITH:
5347 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
5349 case RTX_BITFIELD_OPS:
5351 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
5352 XEXP (x, 1), XEXP (x, 2));
5361 code = GET_CODE (temp);
5362 op0_mode = VOIDmode;
5363 mode = GET_MODE (temp);
5366 /* First see if we can apply the inverse distributive law. */
5367 if (code == PLUS || code == MINUS
5368 || code == AND || code == IOR || code == XOR)
5370 x = apply_distributive_law (x);
5371 code = GET_CODE (x);
5372 op0_mode = VOIDmode;
5375 /* If CODE is an associative operation not otherwise handled, see if we
5376 can associate some operands. This can win if they are constants or
5377 if they are logically related (i.e. (a & b) & a). */
5378 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
5379 || code == AND || code == IOR || code == XOR
5380 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
5381 && ((INTEGRAL_MODE_P (mode) && code != DIV)
5382 || (flag_associative_math && FLOAT_MODE_P (mode))))
5384 if (GET_CODE (XEXP (x, 0)) == code)
5386 rtx other = XEXP (XEXP (x, 0), 0);
5387 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
5388 rtx inner_op1 = XEXP (x, 1);
5391 /* Make sure we pass the constant operand if any as the second
5392 one if this is a commutative operation. */
5393 if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
5395 rtx tem = inner_op0;
5396 inner_op0 = inner_op1;
5399 inner = simplify_binary_operation (code == MINUS ? PLUS
5400 : code == DIV ? MULT
5402 mode, inner_op0, inner_op1);
5404 /* For commutative operations, try the other pair if that one
5406 if (inner == 0 && COMMUTATIVE_ARITH_P (x))
5408 other = XEXP (XEXP (x, 0), 1);
5409 inner = simplify_binary_operation (code, mode,
5410 XEXP (XEXP (x, 0), 0),
5415 return simplify_gen_binary (code, mode, other, inner);
5419 /* A little bit of algebraic simplification here. */
5423 /* Ensure that our address has any ASHIFTs converted to MULT in case
5424 address-recognizing predicates are called later. */
5425 temp = make_compound_operation (XEXP (x, 0), MEM);
5426 SUBST (XEXP (x, 0), temp);
5430 if (op0_mode == VOIDmode)
5431 op0_mode = GET_MODE (SUBREG_REG (x));
5433 /* See if this can be moved to simplify_subreg. */
5434 if (CONSTANT_P (SUBREG_REG (x))
5435 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
5436 /* Don't call gen_lowpart if the inner mode
5437 is VOIDmode and we cannot simplify it, as SUBREG without
5438 inner mode is invalid. */
5439 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
5440 || gen_lowpart_common (mode, SUBREG_REG (x))))
5441 return gen_lowpart (mode, SUBREG_REG (x));
5443 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
5447 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
5453 /* Don't change the mode of the MEM if that would change the meaning
5455 if (MEM_P (SUBREG_REG (x))
5456 && (MEM_VOLATILE_P (SUBREG_REG (x))
5457 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
5458 return gen_rtx_CLOBBER (mode, const0_rtx);
5460 /* Note that we cannot do any narrowing for non-constants since
5461 we might have been counting on using the fact that some bits were
5462 zero. We now do this in the SET. */
5467 temp = expand_compound_operation (XEXP (x, 0));
5469 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5470 replaced by (lshiftrt X C). This will convert
5471 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5473 if (GET_CODE (temp) == ASHIFTRT
5474 && CONST_INT_P (XEXP (temp, 1))
5475 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
5476 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
5477 INTVAL (XEXP (temp, 1)));
5479 /* If X has only a single bit that might be nonzero, say, bit I, convert
5480 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5481 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5482 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5483 or a SUBREG of one since we'd be making the expression more
5484 complex if it was just a register. */
5487 && ! (GET_CODE (temp) == SUBREG
5488 && REG_P (SUBREG_REG (temp)))
5489 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
5491 rtx temp1 = simplify_shift_const
5492 (NULL_RTX, ASHIFTRT, mode,
5493 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
5494 GET_MODE_BITSIZE (mode) - 1 - i),
5495 GET_MODE_BITSIZE (mode) - 1 - i);
5497 /* If all we did was surround TEMP with the two shifts, we
5498 haven't improved anything, so don't use it. Otherwise,
5499 we are better off with TEMP1. */
5500 if (GET_CODE (temp1) != ASHIFTRT
5501 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
5502 || XEXP (XEXP (temp1, 0), 0) != temp)
5508 /* We can't handle truncation to a partial integer mode here
5509 because we don't know the real bitsize of the partial
5511 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
5514 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5516 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
5517 GET_MODE_MASK (mode), 0));
5519 /* We can truncate a constant value and return it. */
5520 if (CONST_INT_P (XEXP (x, 0)))
5521 return gen_int_mode (INTVAL (XEXP (x, 0)), mode);
5523 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5524 whose value is a comparison can be replaced with a subreg if
5525 STORE_FLAG_VALUE permits. */
5526 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5527 && (STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
5528 && (temp = get_last_value (XEXP (x, 0)))
5529 && COMPARISON_P (temp))
5530 return gen_lowpart (mode, XEXP (x, 0));
5534 /* (const (const X)) can become (const X). Do it this way rather than
5535 returning the inner CONST since CONST can be shared with a
5537 if (GET_CODE (XEXP (x, 0)) == CONST)
5538 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
5543 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5544 can add in an offset. find_split_point will split this address up
5545 again if it doesn't match. */
5546 if (GET_CODE (XEXP (x, 0)) == HIGH
5547 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
5553 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5554 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5555 bit-field and can be replaced by either a sign_extend or a
5556 sign_extract. The `and' may be a zero_extend and the two
5557 <c>, -<c> constants may be reversed. */
5558 if (GET_CODE (XEXP (x, 0)) == XOR
5559 && CONST_INT_P (XEXP (x, 1))
5560 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
5561 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
5562 && ((i = exact_log2 (UINTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
5563 || (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0)
5564 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5565 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
5566 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
5567 && (UINTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
5568 == ((unsigned HOST_WIDE_INT) 1 << (i + 1)) - 1))
5569 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
5570 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
5571 == (unsigned int) i + 1))))
5572 return simplify_shift_const
5573 (NULL_RTX, ASHIFTRT, mode,
5574 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5575 XEXP (XEXP (XEXP (x, 0), 0), 0),
5576 GET_MODE_BITSIZE (mode) - (i + 1)),
5577 GET_MODE_BITSIZE (mode) - (i + 1));
5579 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5580 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5581 the bitsize of the mode - 1. This allows simplification of
5582 "a = (b & 8) == 0;" */
5583 if (XEXP (x, 1) == constm1_rtx
5584 && !REG_P (XEXP (x, 0))
5585 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5586 && REG_P (SUBREG_REG (XEXP (x, 0))))
5587 && nonzero_bits (XEXP (x, 0), mode) == 1)
5588 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
5589 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5590 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
5591 GET_MODE_BITSIZE (mode) - 1),
5592 GET_MODE_BITSIZE (mode) - 1);
5594 /* If we are adding two things that have no bits in common, convert
5595 the addition into an IOR. This will often be further simplified,
5596 for example in cases like ((a & 1) + (a & 2)), which can
5599 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5600 && (nonzero_bits (XEXP (x, 0), mode)
5601 & nonzero_bits (XEXP (x, 1), mode)) == 0)
5603 /* Try to simplify the expression further. */
5604 rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
5605 temp = combine_simplify_rtx (tor, mode, in_dest);
5607 /* If we could, great. If not, do not go ahead with the IOR
5608 replacement, since PLUS appears in many special purpose
5609 address arithmetic instructions. */
5610 if (GET_CODE (temp) != CLOBBER && temp != tor)
5616 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5617 (and <foo> (const_int pow2-1)) */
5618 if (GET_CODE (XEXP (x, 1)) == AND
5619 && CONST_INT_P (XEXP (XEXP (x, 1), 1))
5620 && exact_log2 (-UINTVAL (XEXP (XEXP (x, 1), 1))) >= 0
5621 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
5622 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
5623 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
5627 /* If we have (mult (plus A B) C), apply the distributive law and then
5628 the inverse distributive law to see if things simplify. This
5629 occurs mostly in addresses, often when unrolling loops. */
5631 if (GET_CODE (XEXP (x, 0)) == PLUS)
5633 rtx result = distribute_and_simplify_rtx (x, 0);
5638 /* Try simplify a*(b/c) as (a*b)/c. */
5639 if (FLOAT_MODE_P (mode) && flag_associative_math
5640 && GET_CODE (XEXP (x, 0)) == DIV)
5642 rtx tem = simplify_binary_operation (MULT, mode,
5643 XEXP (XEXP (x, 0), 0),
5646 return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
5651 /* If this is a divide by a power of two, treat it as a shift if
5652 its first operand is a shift. */
5653 if (CONST_INT_P (XEXP (x, 1))
5654 && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0
5655 && (GET_CODE (XEXP (x, 0)) == ASHIFT
5656 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
5657 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
5658 || GET_CODE (XEXP (x, 0)) == ROTATE
5659 || GET_CODE (XEXP (x, 0)) == ROTATERT))
5660 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
5664 case GT: case GTU: case GE: case GEU:
5665 case LT: case LTU: case LE: case LEU:
5666 case UNEQ: case LTGT:
5667 case UNGT: case UNGE:
5668 case UNLT: case UNLE:
5669 case UNORDERED: case ORDERED:
5670 /* If the first operand is a condition code, we can't do anything
5672 if (GET_CODE (XEXP (x, 0)) == COMPARE
5673 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
5674 && ! CC0_P (XEXP (x, 0))))
5676 rtx op0 = XEXP (x, 0);
5677 rtx op1 = XEXP (x, 1);
5678 enum rtx_code new_code;
5680 if (GET_CODE (op0) == COMPARE)
5681 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
5683 /* Simplify our comparison, if possible. */
5684 new_code = simplify_comparison (code, &op0, &op1);
5686 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5687 if only the low-order bit is possibly nonzero in X (such as when
5688 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5689 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5690 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5693 Remove any ZERO_EXTRACT we made when thinking this was a
5694 comparison. It may now be simpler to use, e.g., an AND. If a
5695 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5696 the call to make_compound_operation in the SET case. */
5698 if (STORE_FLAG_VALUE == 1
5699 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5700 && op1 == const0_rtx
5701 && mode == GET_MODE (op0)
5702 && nonzero_bits (op0, mode) == 1)
5703 return gen_lowpart (mode,
5704 expand_compound_operation (op0));
5706 else if (STORE_FLAG_VALUE == 1
5707 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5708 && op1 == const0_rtx
5709 && mode == GET_MODE (op0)
5710 && (num_sign_bit_copies (op0, mode)
5711 == GET_MODE_BITSIZE (mode)))
5713 op0 = expand_compound_operation (op0);
5714 return simplify_gen_unary (NEG, mode,
5715 gen_lowpart (mode, op0),
5719 else if (STORE_FLAG_VALUE == 1
5720 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5721 && op1 == const0_rtx
5722 && mode == GET_MODE (op0)
5723 && nonzero_bits (op0, mode) == 1)
5725 op0 = expand_compound_operation (op0);
5726 return simplify_gen_binary (XOR, mode,
5727 gen_lowpart (mode, op0),
5731 else if (STORE_FLAG_VALUE == 1
5732 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5733 && op1 == const0_rtx
5734 && mode == GET_MODE (op0)
5735 && (num_sign_bit_copies (op0, mode)
5736 == GET_MODE_BITSIZE (mode)))
5738 op0 = expand_compound_operation (op0);
5739 return plus_constant (gen_lowpart (mode, op0), 1);
5742 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5744 if (STORE_FLAG_VALUE == -1
5745 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5746 && op1 == const0_rtx
5747 && (num_sign_bit_copies (op0, mode)
5748 == GET_MODE_BITSIZE (mode)))
5749 return gen_lowpart (mode,
5750 expand_compound_operation (op0));
5752 else if (STORE_FLAG_VALUE == -1
5753 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5754 && op1 == const0_rtx
5755 && mode == GET_MODE (op0)
5756 && nonzero_bits (op0, mode) == 1)
5758 op0 = expand_compound_operation (op0);
5759 return simplify_gen_unary (NEG, mode,
5760 gen_lowpart (mode, op0),
5764 else if (STORE_FLAG_VALUE == -1
5765 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5766 && op1 == const0_rtx
5767 && mode == GET_MODE (op0)
5768 && (num_sign_bit_copies (op0, mode)
5769 == GET_MODE_BITSIZE (mode)))
5771 op0 = expand_compound_operation (op0);
5772 return simplify_gen_unary (NOT, mode,
5773 gen_lowpart (mode, op0),
5777 /* If X is 0/1, (eq X 0) is X-1. */
5778 else if (STORE_FLAG_VALUE == -1
5779 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5780 && op1 == const0_rtx
5781 && mode == GET_MODE (op0)
5782 && nonzero_bits (op0, mode) == 1)
5784 op0 = expand_compound_operation (op0);
5785 return plus_constant (gen_lowpart (mode, op0), -1);
5788 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5789 one bit that might be nonzero, we can convert (ne x 0) to
5790 (ashift x c) where C puts the bit in the sign bit. Remove any
5791 AND with STORE_FLAG_VALUE when we are done, since we are only
5792 going to test the sign bit. */
5793 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5794 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5795 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5796 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5797 && op1 == const0_rtx
5798 && mode == GET_MODE (op0)
5799 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
5801 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
5802 expand_compound_operation (op0),
5803 GET_MODE_BITSIZE (mode) - 1 - i);
5804 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
5810 /* If the code changed, return a whole new comparison. */
5811 if (new_code != code)
5812 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
5814 /* Otherwise, keep this operation, but maybe change its operands.
5815 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5816 SUBST (XEXP (x, 0), op0);
5817 SUBST (XEXP (x, 1), op1);
5822 return simplify_if_then_else (x);
5828 /* If we are processing SET_DEST, we are done. */
5832 return expand_compound_operation (x);
5835 return simplify_set (x);
5839 return simplify_logical (x);
5846 /* If this is a shift by a constant amount, simplify it. */
5847 if (CONST_INT_P (XEXP (x, 1)))
5848 return simplify_shift_const (x, code, mode, XEXP (x, 0),
5849 INTVAL (XEXP (x, 1)));
5851 else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
5853 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
5854 ((unsigned HOST_WIDE_INT) 1
5855 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
5867 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5870 simplify_if_then_else (rtx x)
5872 enum machine_mode mode = GET_MODE (x);
5873 rtx cond = XEXP (x, 0);
5874 rtx true_rtx = XEXP (x, 1);
5875 rtx false_rtx = XEXP (x, 2);
5876 enum rtx_code true_code = GET_CODE (cond);
5877 int comparison_p = COMPARISON_P (cond);
5880 enum rtx_code false_code;
5883 /* Simplify storing of the truth value. */
5884 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
5885 return simplify_gen_relational (true_code, mode, VOIDmode,
5886 XEXP (cond, 0), XEXP (cond, 1));
5888 /* Also when the truth value has to be reversed. */
5890 && true_rtx == const0_rtx && false_rtx == const_true_rtx
5891 && (reversed = reversed_comparison (cond, mode)))
5894 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5895 in it is being compared against certain values. Get the true and false
5896 comparisons and see if that says anything about the value of each arm. */
5899 && ((false_code = reversed_comparison_code (cond, NULL))
5901 && REG_P (XEXP (cond, 0)))
5904 rtx from = XEXP (cond, 0);
5905 rtx true_val = XEXP (cond, 1);
5906 rtx false_val = true_val;
5909 /* If FALSE_CODE is EQ, swap the codes and arms. */
5911 if (false_code == EQ)
5913 swapped = 1, true_code = EQ, false_code = NE;
5914 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5917 /* If we are comparing against zero and the expression being tested has
5918 only a single bit that might be nonzero, that is its value when it is
5919 not equal to zero. Similarly if it is known to be -1 or 0. */
5921 if (true_code == EQ && true_val == const0_rtx
5922 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
5925 false_val = GEN_INT (trunc_int_for_mode (nzb, GET_MODE (from)));
5927 else if (true_code == EQ && true_val == const0_rtx
5928 && (num_sign_bit_copies (from, GET_MODE (from))
5929 == GET_MODE_BITSIZE (GET_MODE (from))))
5932 false_val = constm1_rtx;
5935 /* Now simplify an arm if we know the value of the register in the
5936 branch and it is used in the arm. Be careful due to the potential
5937 of locally-shared RTL. */
5939 if (reg_mentioned_p (from, true_rtx))
5940 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
5942 pc_rtx, pc_rtx, 0, 0);
5943 if (reg_mentioned_p (from, false_rtx))
5944 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
5946 pc_rtx, pc_rtx, 0, 0);
5948 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
5949 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
5951 true_rtx = XEXP (x, 1);
5952 false_rtx = XEXP (x, 2);
5953 true_code = GET_CODE (cond);
5956 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
5957 reversed, do so to avoid needing two sets of patterns for
5958 subtract-and-branch insns. Similarly if we have a constant in the true
5959 arm, the false arm is the same as the first operand of the comparison, or
5960 the false arm is more complicated than the true arm. */
5963 && reversed_comparison_code (cond, NULL) != UNKNOWN
5964 && (true_rtx == pc_rtx
5965 || (CONSTANT_P (true_rtx)
5966 && !CONST_INT_P (false_rtx) && false_rtx != pc_rtx)
5967 || true_rtx == const0_rtx
5968 || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
5969 || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
5970 && !OBJECT_P (false_rtx))
5971 || reg_mentioned_p (true_rtx, false_rtx)
5972 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
5974 true_code = reversed_comparison_code (cond, NULL);
5975 SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
5976 SUBST (XEXP (x, 1), false_rtx);
5977 SUBST (XEXP (x, 2), true_rtx);
5979 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5982 /* It is possible that the conditional has been simplified out. */
5983 true_code = GET_CODE (cond);
5984 comparison_p = COMPARISON_P (cond);
5987 /* If the two arms are identical, we don't need the comparison. */
5989 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
5992 /* Convert a == b ? b : a to "a". */
5993 if (true_code == EQ && ! side_effects_p (cond)
5994 && !HONOR_NANS (mode)
5995 && rtx_equal_p (XEXP (cond, 0), false_rtx)
5996 && rtx_equal_p (XEXP (cond, 1), true_rtx))
5998 else if (true_code == NE && ! side_effects_p (cond)
5999 && !HONOR_NANS (mode)
6000 && rtx_equal_p (XEXP (cond, 0), true_rtx)
6001 && rtx_equal_p (XEXP (cond, 1), false_rtx))
6004 /* Look for cases where we have (abs x) or (neg (abs X)). */
6006 if (GET_MODE_CLASS (mode) == MODE_INT
6008 && XEXP (cond, 1) == const0_rtx
6009 && GET_CODE (false_rtx) == NEG
6010 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
6011 && rtx_equal_p (true_rtx, XEXP (cond, 0))
6012 && ! side_effects_p (true_rtx))
6017 return simplify_gen_unary (ABS, mode, true_rtx, mode);
6021 simplify_gen_unary (NEG, mode,
6022 simplify_gen_unary (ABS, mode, true_rtx, mode),
6028 /* Look for MIN or MAX. */
6030 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
6032 && rtx_equal_p (XEXP (cond, 0), true_rtx)
6033 && rtx_equal_p (XEXP (cond, 1), false_rtx)
6034 && ! side_effects_p (cond))
6039 return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
6042 return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
6045 return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
6048 return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
6053 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6054 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6055 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6056 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6057 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6058 neither 1 or -1, but it isn't worth checking for. */
6060 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6062 && GET_MODE_CLASS (mode) == MODE_INT
6063 && ! side_effects_p (x))
6065 rtx t = make_compound_operation (true_rtx, SET);
6066 rtx f = make_compound_operation (false_rtx, SET);
6067 rtx cond_op0 = XEXP (cond, 0);
6068 rtx cond_op1 = XEXP (cond, 1);
6069 enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
6070 enum machine_mode m = mode;
6071 rtx z = 0, c1 = NULL_RTX;
6073 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
6074 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
6075 || GET_CODE (t) == ASHIFT
6076 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
6077 && rtx_equal_p (XEXP (t, 0), f))
6078 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
6080 /* If an identity-zero op is commutative, check whether there
6081 would be a match if we swapped the operands. */
6082 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
6083 || GET_CODE (t) == XOR)
6084 && rtx_equal_p (XEXP (t, 1), f))
6085 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
6086 else if (GET_CODE (t) == SIGN_EXTEND
6087 && (GET_CODE (XEXP (t, 0)) == PLUS
6088 || GET_CODE (XEXP (t, 0)) == MINUS
6089 || GET_CODE (XEXP (t, 0)) == IOR
6090 || GET_CODE (XEXP (t, 0)) == XOR
6091 || GET_CODE (XEXP (t, 0)) == ASHIFT
6092 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6093 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6094 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6095 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6096 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6097 && (num_sign_bit_copies (f, GET_MODE (f))
6099 (GET_MODE_BITSIZE (mode)
6100 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
6102 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6103 extend_op = SIGN_EXTEND;
6104 m = GET_MODE (XEXP (t, 0));
6106 else if (GET_CODE (t) == SIGN_EXTEND
6107 && (GET_CODE (XEXP (t, 0)) == PLUS
6108 || GET_CODE (XEXP (t, 0)) == IOR
6109 || GET_CODE (XEXP (t, 0)) == XOR)
6110 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6111 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6112 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6113 && (num_sign_bit_copies (f, GET_MODE (f))
6115 (GET_MODE_BITSIZE (mode)
6116 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
6118 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6119 extend_op = SIGN_EXTEND;
6120 m = GET_MODE (XEXP (t, 0));
6122 else if (GET_CODE (t) == ZERO_EXTEND
6123 && (GET_CODE (XEXP (t, 0)) == PLUS
6124 || GET_CODE (XEXP (t, 0)) == MINUS
6125 || GET_CODE (XEXP (t, 0)) == IOR
6126 || GET_CODE (XEXP (t, 0)) == XOR
6127 || GET_CODE (XEXP (t, 0)) == ASHIFT
6128 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6129 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6130 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6131 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
6132 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6133 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6134 && ((nonzero_bits (f, GET_MODE (f))
6135 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
6138 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6139 extend_op = ZERO_EXTEND;
6140 m = GET_MODE (XEXP (t, 0));
6142 else if (GET_CODE (t) == ZERO_EXTEND
6143 && (GET_CODE (XEXP (t, 0)) == PLUS
6144 || GET_CODE (XEXP (t, 0)) == IOR
6145 || GET_CODE (XEXP (t, 0)) == XOR)
6146 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6147 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
6148 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6149 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6150 && ((nonzero_bits (f, GET_MODE (f))
6151 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
6154 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6155 extend_op = ZERO_EXTEND;
6156 m = GET_MODE (XEXP (t, 0));
6161 temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
6162 cond_op0, cond_op1),
6163 pc_rtx, pc_rtx, 0, 0);
6164 temp = simplify_gen_binary (MULT, m, temp,
6165 simplify_gen_binary (MULT, m, c1,
6167 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
6168 temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
6170 if (extend_op != UNKNOWN)
6171 temp = simplify_gen_unary (extend_op, mode, temp, m);
6177 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6178 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6179 negation of a single bit, we can convert this operation to a shift. We
6180 can actually do this more generally, but it doesn't seem worth it. */
6182 if (true_code == NE && XEXP (cond, 1) == const0_rtx
6183 && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6184 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
6185 && (i = exact_log2 (UINTVAL (true_rtx))) >= 0)
6186 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
6187 == GET_MODE_BITSIZE (mode))
6188 && (i = exact_log2 (-UINTVAL (true_rtx))) >= 0)))
6190 simplify_shift_const (NULL_RTX, ASHIFT, mode,
6191 gen_lowpart (mode, XEXP (cond, 0)), i);
6193 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
6194 if (true_code == NE && XEXP (cond, 1) == const0_rtx
6195 && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6196 && GET_MODE (XEXP (cond, 0)) == mode
6197 && (UINTVAL (true_rtx) & GET_MODE_MASK (mode))
6198 == nonzero_bits (XEXP (cond, 0), mode)
6199 && (i = exact_log2 (UINTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
6200 return XEXP (cond, 0);
6205 /* Simplify X, a SET expression. Return the new expression. */
6208 simplify_set (rtx x)
6210 rtx src = SET_SRC (x);
6211 rtx dest = SET_DEST (x);
6212 enum machine_mode mode
6213 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
6217 /* (set (pc) (return)) gets written as (return). */
6218 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
6221 /* Now that we know for sure which bits of SRC we are using, see if we can
6222 simplify the expression for the object knowing that we only need the
6225 if (GET_MODE_CLASS (mode) == MODE_INT
6226 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
6228 src = force_to_mode (src, mode, ~(unsigned HOST_WIDE_INT) 0, 0);
6229 SUBST (SET_SRC (x), src);
6232 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6233 the comparison result and try to simplify it unless we already have used
6234 undobuf.other_insn. */
6235 if ((GET_MODE_CLASS (mode) == MODE_CC
6236 || GET_CODE (src) == COMPARE
6238 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
6239 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
6240 && COMPARISON_P (*cc_use)
6241 && rtx_equal_p (XEXP (*cc_use, 0), dest))
6243 enum rtx_code old_code = GET_CODE (*cc_use);
6244 enum rtx_code new_code;
6246 int other_changed = 0;
6247 rtx inner_compare = NULL_RTX;
6248 enum machine_mode compare_mode = GET_MODE (dest);
6250 if (GET_CODE (src) == COMPARE)
6252 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
6253 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
6255 inner_compare = op0;
6256 op0 = XEXP (inner_compare, 0), op1 = XEXP (inner_compare, 1);
6260 op0 = src, op1 = CONST0_RTX (GET_MODE (src));
6262 tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
6265 new_code = old_code;
6266 else if (!CONSTANT_P (tmp))
6268 new_code = GET_CODE (tmp);
6269 op0 = XEXP (tmp, 0);
6270 op1 = XEXP (tmp, 1);
6274 rtx pat = PATTERN (other_insn);
6275 undobuf.other_insn = other_insn;
6276 SUBST (*cc_use, tmp);
6278 /* Attempt to simplify CC user. */
6279 if (GET_CODE (pat) == SET)
6281 rtx new_rtx = simplify_rtx (SET_SRC (pat));
6282 if (new_rtx != NULL_RTX)
6283 SUBST (SET_SRC (pat), new_rtx);
6286 /* Convert X into a no-op move. */
6287 SUBST (SET_DEST (x), pc_rtx);
6288 SUBST (SET_SRC (x), pc_rtx);
6292 /* Simplify our comparison, if possible. */
6293 new_code = simplify_comparison (new_code, &op0, &op1);
6295 #ifdef SELECT_CC_MODE
6296 /* If this machine has CC modes other than CCmode, check to see if we
6297 need to use a different CC mode here. */
6298 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
6299 compare_mode = GET_MODE (op0);
6300 else if (inner_compare
6301 && GET_MODE_CLASS (GET_MODE (inner_compare)) == MODE_CC
6302 && new_code == old_code
6303 && op0 == XEXP (inner_compare, 0)
6304 && op1 == XEXP (inner_compare, 1))
6305 compare_mode = GET_MODE (inner_compare);
6307 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
6310 /* If the mode changed, we have to change SET_DEST, the mode in the
6311 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6312 a hard register, just build new versions with the proper mode. If it
6313 is a pseudo, we lose unless it is only time we set the pseudo, in
6314 which case we can safely change its mode. */
6315 if (compare_mode != GET_MODE (dest))
6317 if (can_change_dest_mode (dest, 0, compare_mode))
6319 unsigned int regno = REGNO (dest);
6322 if (regno < FIRST_PSEUDO_REGISTER)
6323 new_dest = gen_rtx_REG (compare_mode, regno);
6326 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
6327 new_dest = regno_reg_rtx[regno];
6330 SUBST (SET_DEST (x), new_dest);
6331 SUBST (XEXP (*cc_use, 0), new_dest);
6338 #endif /* SELECT_CC_MODE */
6340 /* If the code changed, we have to build a new comparison in
6341 undobuf.other_insn. */
6342 if (new_code != old_code)
6344 int other_changed_previously = other_changed;
6345 unsigned HOST_WIDE_INT mask;
6346 rtx old_cc_use = *cc_use;
6348 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
6352 /* If the only change we made was to change an EQ into an NE or
6353 vice versa, OP0 has only one bit that might be nonzero, and OP1
6354 is zero, check if changing the user of the condition code will
6355 produce a valid insn. If it won't, we can keep the original code
6356 in that insn by surrounding our operation with an XOR. */
6358 if (((old_code == NE && new_code == EQ)
6359 || (old_code == EQ && new_code == NE))
6360 && ! other_changed_previously && op1 == const0_rtx
6361 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
6362 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
6364 rtx pat = PATTERN (other_insn), note = 0;
6366 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
6367 && ! check_asm_operands (pat)))
6369 *cc_use = old_cc_use;
6372 op0 = simplify_gen_binary (XOR, GET_MODE (op0),
6373 op0, GEN_INT (mask));
6379 undobuf.other_insn = other_insn;
6381 /* Otherwise, if we didn't previously have a COMPARE in the
6382 correct mode, we need one. */
6383 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
6385 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6388 else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
6390 SUBST (SET_SRC (x), op0);
6393 /* Otherwise, update the COMPARE if needed. */
6394 else if (XEXP (src, 0) != op0 || XEXP (src, 1) != op1)
6396 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6402 /* Get SET_SRC in a form where we have placed back any
6403 compound expressions. Then do the checks below. */
6404 src = make_compound_operation (src, SET);
6405 SUBST (SET_SRC (x), src);
6408 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6409 and X being a REG or (subreg (reg)), we may be able to convert this to
6410 (set (subreg:m2 x) (op)).
6412 We can always do this if M1 is narrower than M2 because that means that
6413 we only care about the low bits of the result.
6415 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6416 perform a narrower operation than requested since the high-order bits will
6417 be undefined. On machine where it is defined, this transformation is safe
6418 as long as M1 and M2 have the same number of words. */
6420 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6421 && !OBJECT_P (SUBREG_REG (src))
6422 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
6424 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
6425 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
6426 #ifndef WORD_REGISTER_OPERATIONS
6427 && (GET_MODE_SIZE (GET_MODE (src))
6428 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
6430 #ifdef CANNOT_CHANGE_MODE_CLASS
6431 && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
6432 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
6433 GET_MODE (SUBREG_REG (src)),
6437 || (GET_CODE (dest) == SUBREG
6438 && REG_P (SUBREG_REG (dest)))))
6440 SUBST (SET_DEST (x),
6441 gen_lowpart (GET_MODE (SUBREG_REG (src)),
6443 SUBST (SET_SRC (x), SUBREG_REG (src));
6445 src = SET_SRC (x), dest = SET_DEST (x);
6449 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6452 && GET_CODE (src) == SUBREG
6453 && subreg_lowpart_p (src)
6454 && (GET_MODE_BITSIZE (GET_MODE (src))
6455 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
6457 rtx inner = SUBREG_REG (src);
6458 enum machine_mode inner_mode = GET_MODE (inner);
6460 /* Here we make sure that we don't have a sign bit on. */
6461 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
6462 && (nonzero_bits (inner, inner_mode)
6463 < ((unsigned HOST_WIDE_INT) 1
6464 << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
6466 SUBST (SET_SRC (x), inner);
6472 #ifdef LOAD_EXTEND_OP
6473 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6474 would require a paradoxical subreg. Replace the subreg with a
6475 zero_extend to avoid the reload that would otherwise be required. */
6477 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6478 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src)))
6479 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
6480 && SUBREG_BYTE (src) == 0
6481 && (GET_MODE_SIZE (GET_MODE (src))
6482 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
6483 && MEM_P (SUBREG_REG (src)))
6486 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
6487 GET_MODE (src), SUBREG_REG (src)));
6493 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6494 are comparing an item known to be 0 or -1 against 0, use a logical
6495 operation instead. Check for one of the arms being an IOR of the other
6496 arm with some value. We compute three terms to be IOR'ed together. In
6497 practice, at most two will be nonzero. Then we do the IOR's. */
6499 if (GET_CODE (dest) != PC
6500 && GET_CODE (src) == IF_THEN_ELSE
6501 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
6502 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
6503 && XEXP (XEXP (src, 0), 1) == const0_rtx
6504 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
6505 #ifdef HAVE_conditional_move
6506 && ! can_conditionally_move_p (GET_MODE (src))
6508 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
6509 GET_MODE (XEXP (XEXP (src, 0), 0)))
6510 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
6511 && ! side_effects_p (src))
6513 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
6514 ? XEXP (src, 1) : XEXP (src, 2));
6515 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
6516 ? XEXP (src, 2) : XEXP (src, 1));
6517 rtx term1 = const0_rtx, term2, term3;
6519 if (GET_CODE (true_rtx) == IOR
6520 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
6521 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
6522 else if (GET_CODE (true_rtx) == IOR
6523 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
6524 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
6525 else if (GET_CODE (false_rtx) == IOR
6526 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
6527 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
6528 else if (GET_CODE (false_rtx) == IOR
6529 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
6530 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
6532 term2 = simplify_gen_binary (AND, GET_MODE (src),
6533 XEXP (XEXP (src, 0), 0), true_rtx);
6534 term3 = simplify_gen_binary (AND, GET_MODE (src),
6535 simplify_gen_unary (NOT, GET_MODE (src),
6536 XEXP (XEXP (src, 0), 0),
6541 simplify_gen_binary (IOR, GET_MODE (src),
6542 simplify_gen_binary (IOR, GET_MODE (src),
6549 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6550 whole thing fail. */
6551 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
6553 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
6556 /* Convert this into a field assignment operation, if possible. */
6557 return make_field_assignment (x);
6560 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6564 simplify_logical (rtx x)
6566 enum machine_mode mode = GET_MODE (x);
6567 rtx op0 = XEXP (x, 0);
6568 rtx op1 = XEXP (x, 1);
6570 switch (GET_CODE (x))
6573 /* We can call simplify_and_const_int only if we don't lose
6574 any (sign) bits when converting INTVAL (op1) to
6575 "unsigned HOST_WIDE_INT". */
6576 if (CONST_INT_P (op1)
6577 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
6578 || INTVAL (op1) > 0))
6580 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
6581 if (GET_CODE (x) != AND)
6588 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6589 apply the distributive law and then the inverse distributive
6590 law to see if things simplify. */
6591 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
6593 rtx result = distribute_and_simplify_rtx (x, 0);
6597 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
6599 rtx result = distribute_and_simplify_rtx (x, 1);
6606 /* If we have (ior (and A B) C), apply the distributive law and then
6607 the inverse distributive law to see if things simplify. */
6609 if (GET_CODE (op0) == AND)
6611 rtx result = distribute_and_simplify_rtx (x, 0);
6616 if (GET_CODE (op1) == AND)
6618 rtx result = distribute_and_simplify_rtx (x, 1);
6631 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6632 operations" because they can be replaced with two more basic operations.
6633 ZERO_EXTEND is also considered "compound" because it can be replaced with
6634 an AND operation, which is simpler, though only one operation.
6636 The function expand_compound_operation is called with an rtx expression
6637 and will convert it to the appropriate shifts and AND operations,
6638 simplifying at each stage.
6640 The function make_compound_operation is called to convert an expression
6641 consisting of shifts and ANDs into the equivalent compound expression.
6642 It is the inverse of this function, loosely speaking. */
6645 expand_compound_operation (rtx x)
6647 unsigned HOST_WIDE_INT pos = 0, len;
6649 unsigned int modewidth;
6652 switch (GET_CODE (x))
6657 /* We can't necessarily use a const_int for a multiword mode;
6658 it depends on implicitly extending the value.
6659 Since we don't know the right way to extend it,
6660 we can't tell whether the implicit way is right.
6662 Even for a mode that is no wider than a const_int,
6663 we can't win, because we need to sign extend one of its bits through
6664 the rest of it, and we don't know which bit. */
6665 if (CONST_INT_P (XEXP (x, 0)))
6668 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6669 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6670 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6671 reloaded. If not for that, MEM's would very rarely be safe.
6673 Reject MODEs bigger than a word, because we might not be able
6674 to reference a two-register group starting with an arbitrary register
6675 (and currently gen_lowpart might crash for a SUBREG). */
6677 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
6680 /* Reject MODEs that aren't scalar integers because turning vector
6681 or complex modes into shifts causes problems. */
6683 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6686 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
6687 /* If the inner object has VOIDmode (the only way this can happen
6688 is if it is an ASM_OPERANDS), we can't do anything since we don't
6689 know how much masking to do. */
6698 /* ... fall through ... */
6701 /* If the operand is a CLOBBER, just return it. */
6702 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
6705 if (!CONST_INT_P (XEXP (x, 1))
6706 || !CONST_INT_P (XEXP (x, 2))
6707 || GET_MODE (XEXP (x, 0)) == VOIDmode)
6710 /* Reject MODEs that aren't scalar integers because turning vector
6711 or complex modes into shifts causes problems. */
6713 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6716 len = INTVAL (XEXP (x, 1));
6717 pos = INTVAL (XEXP (x, 2));
6719 /* This should stay within the object being extracted, fail otherwise. */
6720 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
6723 if (BITS_BIG_ENDIAN)
6724 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
6731 /* Convert sign extension to zero extension, if we know that the high
6732 bit is not set, as this is easier to optimize. It will be converted
6733 back to cheaper alternative in make_extraction. */
6734 if (GET_CODE (x) == SIGN_EXTEND
6735 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6736 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6737 & ~(((unsigned HOST_WIDE_INT)
6738 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
6742 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
6743 rtx temp2 = expand_compound_operation (temp);
6745 /* Make sure this is a profitable operation. */
6746 if (rtx_cost (x, SET, optimize_this_for_speed_p)
6747 > rtx_cost (temp2, SET, optimize_this_for_speed_p))
6749 else if (rtx_cost (x, SET, optimize_this_for_speed_p)
6750 > rtx_cost (temp, SET, optimize_this_for_speed_p))
6756 /* We can optimize some special cases of ZERO_EXTEND. */
6757 if (GET_CODE (x) == ZERO_EXTEND)
6759 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6760 know that the last value didn't have any inappropriate bits
6762 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6763 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6764 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6765 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
6766 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6767 return XEXP (XEXP (x, 0), 0);
6769 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6770 if (GET_CODE (XEXP (x, 0)) == SUBREG
6771 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6772 && subreg_lowpart_p (XEXP (x, 0))
6773 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6774 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
6775 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6776 return SUBREG_REG (XEXP (x, 0));
6778 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6779 is a comparison and STORE_FLAG_VALUE permits. This is like
6780 the first case, but it works even when GET_MODE (x) is larger
6781 than HOST_WIDE_INT. */
6782 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6783 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6784 && COMPARISON_P (XEXP (XEXP (x, 0), 0))
6785 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6786 <= HOST_BITS_PER_WIDE_INT)
6787 && (STORE_FLAG_VALUE & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6788 return XEXP (XEXP (x, 0), 0);
6790 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6791 if (GET_CODE (XEXP (x, 0)) == SUBREG
6792 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6793 && subreg_lowpart_p (XEXP (x, 0))
6794 && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
6795 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6796 <= HOST_BITS_PER_WIDE_INT)
6797 && (STORE_FLAG_VALUE & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6798 return SUBREG_REG (XEXP (x, 0));
6802 /* If we reach here, we want to return a pair of shifts. The inner
6803 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6804 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6805 logical depending on the value of UNSIGNEDP.
6807 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6808 converted into an AND of a shift.
6810 We must check for the case where the left shift would have a negative
6811 count. This can happen in a case like (x >> 31) & 255 on machines
6812 that can't shift by a constant. On those machines, we would first
6813 combine the shift with the AND to produce a variable-position
6814 extraction. Then the constant of 31 would be substituted in
6815 to produce such a position. */
6817 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
6818 if (modewidth >= pos + len)
6820 enum machine_mode mode = GET_MODE (x);
6821 tem = gen_lowpart (mode, XEXP (x, 0));
6822 if (!tem || GET_CODE (tem) == CLOBBER)
6824 tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
6825 tem, modewidth - pos - len);
6826 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
6827 mode, tem, modewidth - len);
6829 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
6830 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
6831 simplify_shift_const (NULL_RTX, LSHIFTRT,
6834 ((unsigned HOST_WIDE_INT) 1 << len) - 1);
6836 /* Any other cases we can't handle. */
6839 /* If we couldn't do this for some reason, return the original
6841 if (GET_CODE (tem) == CLOBBER)
6847 /* X is a SET which contains an assignment of one object into
6848 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6849 or certain SUBREGS). If possible, convert it into a series of
6852 We half-heartedly support variable positions, but do not at all
6853 support variable lengths. */
6856 expand_field_assignment (const_rtx x)
6859 rtx pos; /* Always counts from low bit. */
6861 rtx mask, cleared, masked;
6862 enum machine_mode compute_mode;
6864 /* Loop until we find something we can't simplify. */
6867 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
6868 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
6870 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
6871 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
6872 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
6874 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
6875 && CONST_INT_P (XEXP (SET_DEST (x), 1)))
6877 inner = XEXP (SET_DEST (x), 0);
6878 len = INTVAL (XEXP (SET_DEST (x), 1));
6879 pos = XEXP (SET_DEST (x), 2);
6881 /* A constant position should stay within the width of INNER. */
6882 if (CONST_INT_P (pos)
6883 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
6886 if (BITS_BIG_ENDIAN)
6888 if (CONST_INT_P (pos))
6889 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
6891 else if (GET_CODE (pos) == MINUS
6892 && CONST_INT_P (XEXP (pos, 1))
6893 && (INTVAL (XEXP (pos, 1))
6894 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
6895 /* If position is ADJUST - X, new position is X. */
6896 pos = XEXP (pos, 0);
6898 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
6899 GEN_INT (GET_MODE_BITSIZE (
6906 /* A SUBREG between two modes that occupy the same numbers of words
6907 can be done by moving the SUBREG to the source. */
6908 else if (GET_CODE (SET_DEST (x)) == SUBREG
6909 /* We need SUBREGs to compute nonzero_bits properly. */
6910 && nonzero_sign_valid
6911 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
6912 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
6913 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
6914 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
6916 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
6918 (GET_MODE (SUBREG_REG (SET_DEST (x))),
6925 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6926 inner = SUBREG_REG (inner);
6928 compute_mode = GET_MODE (inner);
6930 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6931 if (! SCALAR_INT_MODE_P (compute_mode))
6933 enum machine_mode imode;
6935 /* Don't do anything for vector or complex integral types. */
6936 if (! FLOAT_MODE_P (compute_mode))
6939 /* Try to find an integral mode to pun with. */
6940 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
6941 if (imode == BLKmode)
6944 compute_mode = imode;
6945 inner = gen_lowpart (imode, inner);
6948 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6949 if (len >= HOST_BITS_PER_WIDE_INT)
6952 /* Now compute the equivalent expression. Make a copy of INNER
6953 for the SET_DEST in case it is a MEM into which we will substitute;
6954 we don't want shared RTL in that case. */
6955 mask = GEN_INT (((unsigned HOST_WIDE_INT) 1 << len) - 1);
6956 cleared = simplify_gen_binary (AND, compute_mode,
6957 simplify_gen_unary (NOT, compute_mode,
6958 simplify_gen_binary (ASHIFT,
6963 masked = simplify_gen_binary (ASHIFT, compute_mode,
6964 simplify_gen_binary (
6966 gen_lowpart (compute_mode, SET_SRC (x)),
6970 x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
6971 simplify_gen_binary (IOR, compute_mode,
6978 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6979 it is an RTX that represents a variable starting position; otherwise,
6980 POS is the (constant) starting bit position (counted from the LSB).
6982 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6985 IN_DEST is nonzero if this is a reference in the destination of a
6986 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6987 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6990 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6991 ZERO_EXTRACT should be built even for bits starting at bit 0.
6993 MODE is the desired mode of the result (if IN_DEST == 0).
6995 The result is an RTX for the extraction or NULL_RTX if the target
6999 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
7000 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
7001 int in_dest, int in_compare)
7003 /* This mode describes the size of the storage area
7004 to fetch the overall value from. Within that, we
7005 ignore the POS lowest bits, etc. */
7006 enum machine_mode is_mode = GET_MODE (inner);
7007 enum machine_mode inner_mode;
7008 enum machine_mode wanted_inner_mode;
7009 enum machine_mode wanted_inner_reg_mode = word_mode;
7010 enum machine_mode pos_mode = word_mode;
7011 enum machine_mode extraction_mode = word_mode;
7012 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
7014 rtx orig_pos_rtx = pos_rtx;
7015 HOST_WIDE_INT orig_pos;
7017 if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
7019 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7020 consider just the QI as the memory to extract from.
7021 The subreg adds or removes high bits; its mode is
7022 irrelevant to the meaning of this extraction,
7023 since POS and LEN count from the lsb. */
7024 if (MEM_P (SUBREG_REG (inner)))
7025 is_mode = GET_MODE (SUBREG_REG (inner));
7026 inner = SUBREG_REG (inner);
7028 else if (GET_CODE (inner) == ASHIFT
7029 && CONST_INT_P (XEXP (inner, 1))
7030 && pos_rtx == 0 && pos == 0
7031 && len > UINTVAL (XEXP (inner, 1)))
7033 /* We're extracting the least significant bits of an rtx
7034 (ashift X (const_int C)), where LEN > C. Extract the
7035 least significant (LEN - C) bits of X, giving an rtx
7036 whose mode is MODE, then shift it left C times. */
7037 new_rtx = make_extraction (mode, XEXP (inner, 0),
7038 0, 0, len - INTVAL (XEXP (inner, 1)),
7039 unsignedp, in_dest, in_compare);
7041 return gen_rtx_ASHIFT (mode, new_rtx, XEXP (inner, 1));
7044 inner_mode = GET_MODE (inner);
7046 if (pos_rtx && CONST_INT_P (pos_rtx))
7047 pos = INTVAL (pos_rtx), pos_rtx = 0;
7049 /* See if this can be done without an extraction. We never can if the
7050 width of the field is not the same as that of some integer mode. For
7051 registers, we can only avoid the extraction if the position is at the
7052 low-order bit and this is either not in the destination or we have the
7053 appropriate STRICT_LOW_PART operation available.
7055 For MEM, we can avoid an extract if the field starts on an appropriate
7056 boundary and we can change the mode of the memory reference. */
7058 if (tmode != BLKmode
7059 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
7061 && (inner_mode == tmode
7063 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
7064 GET_MODE_BITSIZE (inner_mode))
7065 || reg_truncated_to_mode (tmode, inner))
7068 && have_insn_for (STRICT_LOW_PART, tmode))))
7069 || (MEM_P (inner) && pos_rtx == 0
7071 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
7072 : BITS_PER_UNIT)) == 0
7073 /* We can't do this if we are widening INNER_MODE (it
7074 may not be aligned, for one thing). */
7075 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
7076 && (inner_mode == tmode
7077 || (! mode_dependent_address_p (XEXP (inner, 0))
7078 && ! MEM_VOLATILE_P (inner))))))
7080 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7081 field. If the original and current mode are the same, we need not
7082 adjust the offset. Otherwise, we do if bytes big endian.
7084 If INNER is not a MEM, get a piece consisting of just the field
7085 of interest (in this case POS % BITS_PER_WORD must be 0). */
7089 HOST_WIDE_INT offset;
7091 /* POS counts from lsb, but make OFFSET count in memory order. */
7092 if (BYTES_BIG_ENDIAN)
7093 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
7095 offset = pos / BITS_PER_UNIT;
7097 new_rtx = adjust_address_nv (inner, tmode, offset);
7099 else if (REG_P (inner))
7101 if (tmode != inner_mode)
7103 /* We can't call gen_lowpart in a DEST since we
7104 always want a SUBREG (see below) and it would sometimes
7105 return a new hard register. */
7108 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
7110 if (WORDS_BIG_ENDIAN
7111 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
7112 final_word = ((GET_MODE_SIZE (inner_mode)
7113 - GET_MODE_SIZE (tmode))
7114 / UNITS_PER_WORD) - final_word;
7116 final_word *= UNITS_PER_WORD;
7117 if (BYTES_BIG_ENDIAN &&
7118 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
7119 final_word += (GET_MODE_SIZE (inner_mode)
7120 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
7122 /* Avoid creating invalid subregs, for example when
7123 simplifying (x>>32)&255. */
7124 if (!validate_subreg (tmode, inner_mode, inner, final_word))
7127 new_rtx = gen_rtx_SUBREG (tmode, inner, final_word);
7130 new_rtx = gen_lowpart (tmode, inner);
7136 new_rtx = force_to_mode (inner, tmode,
7137 len >= HOST_BITS_PER_WIDE_INT
7138 ? ~(unsigned HOST_WIDE_INT) 0
7139 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7142 /* If this extraction is going into the destination of a SET,
7143 make a STRICT_LOW_PART unless we made a MEM. */
7146 return (MEM_P (new_rtx) ? new_rtx
7147 : (GET_CODE (new_rtx) != SUBREG
7148 ? gen_rtx_CLOBBER (tmode, const0_rtx)
7149 : gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx)));
7154 if (CONST_INT_P (new_rtx)
7155 || GET_CODE (new_rtx) == CONST_DOUBLE)
7156 return simplify_unary_operation (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7157 mode, new_rtx, tmode);
7159 /* If we know that no extraneous bits are set, and that the high
7160 bit is not set, convert the extraction to the cheaper of
7161 sign and zero extension, that are equivalent in these cases. */
7162 if (flag_expensive_optimizations
7163 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
7164 && ((nonzero_bits (new_rtx, tmode)
7165 & ~(((unsigned HOST_WIDE_INT)
7166 GET_MODE_MASK (tmode))
7170 rtx temp = gen_rtx_ZERO_EXTEND (mode, new_rtx);
7171 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new_rtx);
7173 /* Prefer ZERO_EXTENSION, since it gives more information to
7175 if (rtx_cost (temp, SET, optimize_this_for_speed_p)
7176 <= rtx_cost (temp1, SET, optimize_this_for_speed_p))
7181 /* Otherwise, sign- or zero-extend unless we already are in the
7184 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7188 /* Unless this is a COMPARE or we have a funny memory reference,
7189 don't do anything with zero-extending field extracts starting at
7190 the low-order bit since they are simple AND operations. */
7191 if (pos_rtx == 0 && pos == 0 && ! in_dest
7192 && ! in_compare && unsignedp)
7195 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7196 if the position is not a constant and the length is not 1. In all
7197 other cases, we would only be going outside our object in cases when
7198 an original shift would have been undefined. */
7200 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
7201 || (pos_rtx != 0 && len != 1)))
7204 /* Get the mode to use should INNER not be a MEM, the mode for the position,
7205 and the mode for the result. */
7206 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
7208 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
7209 pos_mode = mode_for_extraction (EP_insv, 2);
7210 extraction_mode = mode_for_extraction (EP_insv, 3);
7213 if (! in_dest && unsignedp
7214 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
7216 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
7217 pos_mode = mode_for_extraction (EP_extzv, 3);
7218 extraction_mode = mode_for_extraction (EP_extzv, 0);
7221 if (! in_dest && ! unsignedp
7222 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
7224 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
7225 pos_mode = mode_for_extraction (EP_extv, 3);
7226 extraction_mode = mode_for_extraction (EP_extv, 0);
7229 /* Never narrow an object, since that might not be safe. */
7231 if (mode != VOIDmode
7232 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
7233 extraction_mode = mode;
7235 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
7236 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
7237 pos_mode = GET_MODE (pos_rtx);
7239 /* If this is not from memory, the desired mode is the preferred mode
7240 for an extraction pattern's first input operand, or word_mode if there
7243 wanted_inner_mode = wanted_inner_reg_mode;
7246 /* Be careful not to go beyond the extracted object and maintain the
7247 natural alignment of the memory. */
7248 wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
7249 while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
7250 > GET_MODE_BITSIZE (wanted_inner_mode))
7252 wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
7253 gcc_assert (wanted_inner_mode != VOIDmode);
7256 /* If we have to change the mode of memory and cannot, the desired mode
7257 is EXTRACTION_MODE. */
7258 if (inner_mode != wanted_inner_mode
7259 && (mode_dependent_address_p (XEXP (inner, 0))
7260 || MEM_VOLATILE_P (inner)
7262 wanted_inner_mode = extraction_mode;
7267 if (BITS_BIG_ENDIAN)
7269 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7270 BITS_BIG_ENDIAN style. If position is constant, compute new
7271 position. Otherwise, build subtraction.
7272 Note that POS is relative to the mode of the original argument.
7273 If it's a MEM we need to recompute POS relative to that.
7274 However, if we're extracting from (or inserting into) a register,
7275 we want to recompute POS relative to wanted_inner_mode. */
7276 int width = (MEM_P (inner)
7277 ? GET_MODE_BITSIZE (is_mode)
7278 : GET_MODE_BITSIZE (wanted_inner_mode));
7281 pos = width - len - pos;
7284 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
7285 /* POS may be less than 0 now, but we check for that below.
7286 Note that it can only be less than 0 if !MEM_P (inner). */
7289 /* If INNER has a wider mode, and this is a constant extraction, try to
7290 make it smaller and adjust the byte to point to the byte containing
7292 if (wanted_inner_mode != VOIDmode
7293 && inner_mode != wanted_inner_mode
7295 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
7297 && ! mode_dependent_address_p (XEXP (inner, 0))
7298 && ! MEM_VOLATILE_P (inner))
7302 /* The computations below will be correct if the machine is big
7303 endian in both bits and bytes or little endian in bits and bytes.
7304 If it is mixed, we must adjust. */
7306 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7307 adjust OFFSET to compensate. */
7308 if (BYTES_BIG_ENDIAN
7309 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
7310 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
7312 /* We can now move to the desired byte. */
7313 offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
7314 * GET_MODE_SIZE (wanted_inner_mode);
7315 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
7317 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
7318 && is_mode != wanted_inner_mode)
7319 offset = (GET_MODE_SIZE (is_mode)
7320 - GET_MODE_SIZE (wanted_inner_mode) - offset);
7322 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
7325 /* If INNER is not memory, get it into the proper mode. If we are changing
7326 its mode, POS must be a constant and smaller than the size of the new
7328 else if (!MEM_P (inner))
7330 /* On the LHS, don't create paradoxical subregs implicitely truncating
7331 the register unless TRULY_NOOP_TRUNCATION. */
7333 && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE (inner)),
7334 GET_MODE_BITSIZE (wanted_inner_mode)))
7337 if (GET_MODE (inner) != wanted_inner_mode
7339 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
7345 inner = force_to_mode (inner, wanted_inner_mode,
7347 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
7348 ? ~(unsigned HOST_WIDE_INT) 0
7349 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
7354 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7355 have to zero extend. Otherwise, we can just use a SUBREG. */
7357 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
7359 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
7361 /* If we know that no extraneous bits are set, and that the high
7362 bit is not set, convert extraction to cheaper one - either
7363 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7365 if (flag_expensive_optimizations
7366 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
7367 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
7368 & ~(((unsigned HOST_WIDE_INT)
7369 GET_MODE_MASK (GET_MODE (pos_rtx)))
7373 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
7375 /* Prefer ZERO_EXTENSION, since it gives more information to
7377 if (rtx_cost (temp1, SET, optimize_this_for_speed_p)
7378 < rtx_cost (temp, SET, optimize_this_for_speed_p))
7383 else if (pos_rtx != 0
7384 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
7385 pos_rtx = gen_lowpart (pos_mode, pos_rtx);
7387 /* Make POS_RTX unless we already have it and it is correct. If we don't
7388 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7390 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
7391 pos_rtx = orig_pos_rtx;
7393 else if (pos_rtx == 0)
7394 pos_rtx = GEN_INT (pos);
7396 /* Make the required operation. See if we can use existing rtx. */
7397 new_rtx = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
7398 extraction_mode, inner, GEN_INT (len), pos_rtx);
7400 new_rtx = gen_lowpart (mode, new_rtx);
7405 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7406 with any other operations in X. Return X without that shift if so. */
7409 extract_left_shift (rtx x, int count)
7411 enum rtx_code code = GET_CODE (x);
7412 enum machine_mode mode = GET_MODE (x);
7418 /* This is the shift itself. If it is wide enough, we will return
7419 either the value being shifted if the shift count is equal to
7420 COUNT or a shift for the difference. */
7421 if (CONST_INT_P (XEXP (x, 1))
7422 && INTVAL (XEXP (x, 1)) >= count)
7423 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
7424 INTVAL (XEXP (x, 1)) - count);
7428 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7429 return simplify_gen_unary (code, mode, tem, mode);
7433 case PLUS: case IOR: case XOR: case AND:
7434 /* If we can safely shift this constant and we find the inner shift,
7435 make a new operation. */
7436 if (CONST_INT_P (XEXP (x, 1))
7437 && (UINTVAL (XEXP (x, 1))
7438 & ((((unsigned HOST_WIDE_INT) 1 << count)) - 1)) == 0
7439 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7440 return simplify_gen_binary (code, mode, tem,
7441 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
7452 /* Look at the expression rooted at X. Look for expressions
7453 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7454 Form these expressions.
7456 Return the new rtx, usually just X.
7458 Also, for machines like the VAX that don't have logical shift insns,
7459 try to convert logical to arithmetic shift operations in cases where
7460 they are equivalent. This undoes the canonicalizations to logical
7461 shifts done elsewhere.
7463 We try, as much as possible, to re-use rtl expressions to save memory.
7465 IN_CODE says what kind of expression we are processing. Normally, it is
7466 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
7467 being kludges), it is MEM. When processing the arguments of a comparison
7468 or a COMPARE against zero, it is COMPARE. */
7471 make_compound_operation (rtx x, enum rtx_code in_code)
7473 enum rtx_code code = GET_CODE (x);
7474 enum machine_mode mode = GET_MODE (x);
7475 int mode_width = GET_MODE_BITSIZE (mode);
7477 enum rtx_code next_code;
7483 /* Select the code to be used in recursive calls. Once we are inside an
7484 address, we stay there. If we have a comparison, set to COMPARE,
7485 but once inside, go back to our default of SET. */
7487 next_code = (code == MEM ? MEM
7488 : ((code == PLUS || code == MINUS)
7489 && SCALAR_INT_MODE_P (mode)) ? MEM
7490 : ((code == COMPARE || COMPARISON_P (x))
7491 && XEXP (x, 1) == const0_rtx) ? COMPARE
7492 : in_code == COMPARE ? SET : in_code);
7494 /* Process depending on the code of this operation. If NEW is set
7495 nonzero, it will be returned. */
7500 /* Convert shifts by constants into multiplications if inside
7502 if (in_code == MEM && CONST_INT_P (XEXP (x, 1))
7503 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7504 && INTVAL (XEXP (x, 1)) >= 0
7505 && SCALAR_INT_MODE_P (mode))
7507 HOST_WIDE_INT count = INTVAL (XEXP (x, 1));
7508 HOST_WIDE_INT multval = (HOST_WIDE_INT) 1 << count;
7510 new_rtx = make_compound_operation (XEXP (x, 0), next_code);
7511 if (GET_CODE (new_rtx) == NEG)
7513 new_rtx = XEXP (new_rtx, 0);
7516 multval = trunc_int_for_mode (multval, mode);
7517 new_rtx = gen_rtx_MULT (mode, new_rtx, GEN_INT (multval));
7524 lhs = make_compound_operation (lhs, next_code);
7525 rhs = make_compound_operation (rhs, next_code);
7526 if (GET_CODE (lhs) == MULT && GET_CODE (XEXP (lhs, 0)) == NEG
7527 && SCALAR_INT_MODE_P (mode))
7529 tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (lhs, 0), 0),
7531 new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
7533 else if (GET_CODE (lhs) == MULT
7534 && (CONST_INT_P (XEXP (lhs, 1)) && INTVAL (XEXP (lhs, 1)) < 0))
7536 tem = simplify_gen_binary (MULT, mode, XEXP (lhs, 0),
7537 simplify_gen_unary (NEG, mode,
7540 new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
7544 SUBST (XEXP (x, 0), lhs);
7545 SUBST (XEXP (x, 1), rhs);
7548 x = gen_lowpart (mode, new_rtx);
7554 lhs = make_compound_operation (lhs, next_code);
7555 rhs = make_compound_operation (rhs, next_code);
7556 if (GET_CODE (rhs) == MULT && GET_CODE (XEXP (rhs, 0)) == NEG
7557 && SCALAR_INT_MODE_P (mode))
7559 tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (rhs, 0), 0),
7561 new_rtx = simplify_gen_binary (PLUS, mode, tem, lhs);
7563 else if (GET_CODE (rhs) == MULT
7564 && (CONST_INT_P (XEXP (rhs, 1)) && INTVAL (XEXP (rhs, 1)) < 0))
7566 tem = simplify_gen_binary (MULT, mode, XEXP (rhs, 0),
7567 simplify_gen_unary (NEG, mode,
7570 new_rtx = simplify_gen_binary (PLUS, mode, tem, lhs);
7574 SUBST (XEXP (x, 0), lhs);
7575 SUBST (XEXP (x, 1), rhs);
7578 return gen_lowpart (mode, new_rtx);
7581 /* If the second operand is not a constant, we can't do anything
7583 if (!CONST_INT_P (XEXP (x, 1)))
7586 /* If the constant is a power of two minus one and the first operand
7587 is a logical right shift, make an extraction. */
7588 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7589 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7591 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7592 new_rtx = make_extraction (mode, new_rtx, 0, XEXP (XEXP (x, 0), 1), i, 1,
7593 0, in_code == COMPARE);
7596 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7597 else if (GET_CODE (XEXP (x, 0)) == SUBREG
7598 && subreg_lowpart_p (XEXP (x, 0))
7599 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
7600 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7602 new_rtx = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
7604 new_rtx = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new_rtx, 0,
7605 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
7606 0, in_code == COMPARE);
7608 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7609 else if ((GET_CODE (XEXP (x, 0)) == XOR
7610 || GET_CODE (XEXP (x, 0)) == IOR)
7611 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
7612 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
7613 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7615 /* Apply the distributive law, and then try to make extractions. */
7616 new_rtx = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
7617 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
7619 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
7621 new_rtx = make_compound_operation (new_rtx, in_code);
7624 /* If we are have (and (rotate X C) M) and C is larger than the number
7625 of bits in M, this is an extraction. */
7627 else if (GET_CODE (XEXP (x, 0)) == ROTATE
7628 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7629 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0
7630 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
7632 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7633 new_rtx = make_extraction (mode, new_rtx,
7634 (GET_MODE_BITSIZE (mode)
7635 - INTVAL (XEXP (XEXP (x, 0), 1))),
7636 NULL_RTX, i, 1, 0, in_code == COMPARE);
7639 /* On machines without logical shifts, if the operand of the AND is
7640 a logical shift and our mask turns off all the propagated sign
7641 bits, we can replace the logical shift with an arithmetic shift. */
7642 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7643 && !have_insn_for (LSHIFTRT, mode)
7644 && have_insn_for (ASHIFTRT, mode)
7645 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7646 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7647 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7648 && mode_width <= HOST_BITS_PER_WIDE_INT)
7650 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
7652 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
7653 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
7655 gen_rtx_ASHIFTRT (mode,
7656 make_compound_operation
7657 (XEXP (XEXP (x, 0), 0), next_code),
7658 XEXP (XEXP (x, 0), 1)));
7661 /* If the constant is one less than a power of two, this might be
7662 representable by an extraction even if no shift is present.
7663 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7664 we are in a COMPARE. */
7665 else if ((i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7666 new_rtx = make_extraction (mode,
7667 make_compound_operation (XEXP (x, 0),
7669 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
7671 /* If we are in a comparison and this is an AND with a power of two,
7672 convert this into the appropriate bit extract. */
7673 else if (in_code == COMPARE
7674 && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0)
7675 new_rtx = make_extraction (mode,
7676 make_compound_operation (XEXP (x, 0),
7678 i, NULL_RTX, 1, 1, 0, 1);
7683 /* If the sign bit is known to be zero, replace this with an
7684 arithmetic shift. */
7685 if (have_insn_for (ASHIFTRT, mode)
7686 && ! have_insn_for (LSHIFTRT, mode)
7687 && mode_width <= HOST_BITS_PER_WIDE_INT
7688 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
7690 new_rtx = gen_rtx_ASHIFTRT (mode,
7691 make_compound_operation (XEXP (x, 0),
7697 /* ... fall through ... */
7703 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7704 this is a SIGN_EXTRACT. */
7705 if (CONST_INT_P (rhs)
7706 && GET_CODE (lhs) == ASHIFT
7707 && CONST_INT_P (XEXP (lhs, 1))
7708 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))
7709 && INTVAL (rhs) < mode_width)
7711 new_rtx = make_compound_operation (XEXP (lhs, 0), next_code);
7712 new_rtx = make_extraction (mode, new_rtx,
7713 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
7714 NULL_RTX, mode_width - INTVAL (rhs),
7715 code == LSHIFTRT, 0, in_code == COMPARE);
7719 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7720 If so, try to merge the shifts into a SIGN_EXTEND. We could
7721 also do this for some cases of SIGN_EXTRACT, but it doesn't
7722 seem worth the effort; the case checked for occurs on Alpha. */
7725 && ! (GET_CODE (lhs) == SUBREG
7726 && (OBJECT_P (SUBREG_REG (lhs))))
7727 && CONST_INT_P (rhs)
7728 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
7729 && INTVAL (rhs) < mode_width
7730 && (new_rtx = extract_left_shift (lhs, INTVAL (rhs))) != 0)
7731 new_rtx = make_extraction (mode, make_compound_operation (new_rtx, next_code),
7732 0, NULL_RTX, mode_width - INTVAL (rhs),
7733 code == LSHIFTRT, 0, in_code == COMPARE);
7738 /* Call ourselves recursively on the inner expression. If we are
7739 narrowing the object and it has a different RTL code from
7740 what it originally did, do this SUBREG as a force_to_mode. */
7742 rtx inner = SUBREG_REG (x), simplified;
7744 tem = make_compound_operation (inner, in_code);
7747 = simplify_subreg (mode, tem, GET_MODE (inner), SUBREG_BYTE (x));
7751 if (GET_CODE (tem) != GET_CODE (inner)
7752 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (inner))
7753 && subreg_lowpart_p (x))
7756 = force_to_mode (tem, mode, ~(unsigned HOST_WIDE_INT) 0, 0);
7758 /* If we have something other than a SUBREG, we might have
7759 done an expansion, so rerun ourselves. */
7760 if (GET_CODE (newer) != SUBREG)
7761 newer = make_compound_operation (newer, in_code);
7763 /* force_to_mode can expand compounds. If it just re-expanded the
7764 compound, use gen_lowpart to convert to the desired mode. */
7765 if (rtx_equal_p (newer, x)
7766 /* Likewise if it re-expanded the compound only partially.
7767 This happens for SUBREG of ZERO_EXTRACT if they extract
7768 the same number of bits. */
7769 || (GET_CODE (newer) == SUBREG
7770 && (GET_CODE (SUBREG_REG (newer)) == LSHIFTRT
7771 || GET_CODE (SUBREG_REG (newer)) == ASHIFTRT)
7772 && GET_CODE (inner) == AND
7773 && rtx_equal_p (SUBREG_REG (newer), XEXP (inner, 0))))
7774 return gen_lowpart (GET_MODE (x), tem);
7790 x = gen_lowpart (mode, new_rtx);
7791 code = GET_CODE (x);
7794 /* Now recursively process each operand of this operation. */
7795 fmt = GET_RTX_FORMAT (code);
7796 for (i = 0; i < GET_RTX_LENGTH (code); i++)
7799 new_rtx = make_compound_operation (XEXP (x, i), next_code);
7800 SUBST (XEXP (x, i), new_rtx);
7802 else if (fmt[i] == 'E')
7803 for (j = 0; j < XVECLEN (x, i); j++)
7805 new_rtx = make_compound_operation (XVECEXP (x, i, j), next_code);
7806 SUBST (XVECEXP (x, i, j), new_rtx);
7810 /* If this is a commutative operation, the changes to the operands
7811 may have made it noncanonical. */
7812 if (COMMUTATIVE_ARITH_P (x)
7813 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
7816 SUBST (XEXP (x, 0), XEXP (x, 1));
7817 SUBST (XEXP (x, 1), tem);
7823 /* Given M see if it is a value that would select a field of bits
7824 within an item, but not the entire word. Return -1 if not.
7825 Otherwise, return the starting position of the field, where 0 is the
7828 *PLEN is set to the length of the field. */
7831 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
7833 /* Get the bit number of the first 1 bit from the right, -1 if none. */
7834 int pos = m ? ctz_hwi (m) : -1;
7838 /* Now shift off the low-order zero bits and see if we have a
7839 power of two minus 1. */
7840 len = exact_log2 ((m >> pos) + 1);
7849 /* If X refers to a register that equals REG in value, replace these
7850 references with REG. */
7852 canon_reg_for_combine (rtx x, rtx reg)
7859 enum rtx_code code = GET_CODE (x);
7860 switch (GET_RTX_CLASS (code))
7863 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7864 if (op0 != XEXP (x, 0))
7865 return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
7870 case RTX_COMM_ARITH:
7871 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7872 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7873 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7874 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
7878 case RTX_COMM_COMPARE:
7879 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7880 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7881 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7882 return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
7883 GET_MODE (op0), op0, op1);
7887 case RTX_BITFIELD_OPS:
7888 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7889 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7890 op2 = canon_reg_for_combine (XEXP (x, 2), reg);
7891 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
7892 return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
7893 GET_MODE (op0), op0, op1, op2);
7898 if (rtx_equal_p (get_last_value (reg), x)
7899 || rtx_equal_p (reg, get_last_value (x)))
7908 fmt = GET_RTX_FORMAT (code);
7910 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7913 rtx op = canon_reg_for_combine (XEXP (x, i), reg);
7914 if (op != XEXP (x, i))
7924 else if (fmt[i] == 'E')
7927 for (j = 0; j < XVECLEN (x, i); j++)
7929 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
7930 if (op != XVECEXP (x, i, j))
7937 XVECEXP (x, i, j) = op;
7948 /* Return X converted to MODE. If the value is already truncated to
7949 MODE we can just return a subreg even though in the general case we
7950 would need an explicit truncation. */
7953 gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
7955 if (!CONST_INT_P (x)
7956 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
7957 && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
7958 GET_MODE_BITSIZE (GET_MODE (x)))
7959 && !(REG_P (x) && reg_truncated_to_mode (mode, x)))
7961 /* Bit-cast X into an integer mode. */
7962 if (!SCALAR_INT_MODE_P (GET_MODE (x)))
7963 x = gen_lowpart (int_mode_for_mode (GET_MODE (x)), x);
7964 x = simplify_gen_unary (TRUNCATE, int_mode_for_mode (mode),
7968 return gen_lowpart (mode, x);
7971 /* See if X can be simplified knowing that we will only refer to it in
7972 MODE and will only refer to those bits that are nonzero in MASK.
7973 If other bits are being computed or if masking operations are done
7974 that select a superset of the bits in MASK, they can sometimes be
7977 Return a possibly simplified expression, but always convert X to
7978 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
7980 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
7981 are all off in X. This is used when X will be complemented, by either
7982 NOT, NEG, or XOR. */
7985 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
7988 enum rtx_code code = GET_CODE (x);
7989 int next_select = just_select || code == XOR || code == NOT || code == NEG;
7990 enum machine_mode op_mode;
7991 unsigned HOST_WIDE_INT fuller_mask, nonzero;
7994 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
7995 code below will do the wrong thing since the mode of such an
7996 expression is VOIDmode.
7998 Also do nothing if X is a CLOBBER; this can happen if X was
7999 the return value from a call to gen_lowpart. */
8000 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
8003 /* We want to perform the operation is its present mode unless we know
8004 that the operation is valid in MODE, in which case we do the operation
8006 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
8007 && have_insn_for (code, mode))
8008 ? mode : GET_MODE (x));
8010 /* It is not valid to do a right-shift in a narrower mode
8011 than the one it came in with. */
8012 if ((code == LSHIFTRT || code == ASHIFTRT)
8013 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
8014 op_mode = GET_MODE (x);
8016 /* Truncate MASK to fit OP_MODE. */
8018 mask &= GET_MODE_MASK (op_mode);
8020 /* When we have an arithmetic operation, or a shift whose count we
8021 do not know, we need to assume that all bits up to the highest-order
8022 bit in MASK will be needed. This is how we form such a mask. */
8023 if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
8024 fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
8026 fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
8029 /* Determine what bits of X are guaranteed to be (non)zero. */
8030 nonzero = nonzero_bits (x, mode);
8032 /* If none of the bits in X are needed, return a zero. */
8033 if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
8036 /* If X is a CONST_INT, return a new one. Do this here since the
8037 test below will fail. */
8038 if (CONST_INT_P (x))
8040 if (SCALAR_INT_MODE_P (mode))
8041 return gen_int_mode (INTVAL (x) & mask, mode);
8044 x = GEN_INT (INTVAL (x) & mask);
8045 return gen_lowpart_common (mode, x);
8049 /* If X is narrower than MODE and we want all the bits in X's mode, just
8050 get X in the proper mode. */
8051 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
8052 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
8053 return gen_lowpart (mode, x);
8055 /* We can ignore the effect of a SUBREG if it narrows the mode or
8056 if the constant masks to zero all the bits the mode doesn't have. */
8057 if (GET_CODE (x) == SUBREG
8058 && subreg_lowpart_p (x)
8059 && ((GET_MODE_SIZE (GET_MODE (x))
8060 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8062 & GET_MODE_MASK (GET_MODE (x))
8063 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
8064 return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
8066 /* The arithmetic simplifications here only work for scalar integer modes. */
8067 if (!SCALAR_INT_MODE_P (mode) || !SCALAR_INT_MODE_P (GET_MODE (x)))
8068 return gen_lowpart_or_truncate (mode, x);
8073 /* If X is a (clobber (const_int)), return it since we know we are
8074 generating something that won't match. */
8081 x = expand_compound_operation (x);
8082 if (GET_CODE (x) != code)
8083 return force_to_mode (x, mode, mask, next_select);
8087 /* Similarly for a truncate. */
8088 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8091 /* If this is an AND with a constant, convert it into an AND
8092 whose constant is the AND of that constant with MASK. If it
8093 remains an AND of MASK, delete it since it is redundant. */
8095 if (CONST_INT_P (XEXP (x, 1)))
8097 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
8098 mask & INTVAL (XEXP (x, 1)));
8100 /* If X is still an AND, see if it is an AND with a mask that
8101 is just some low-order bits. If so, and it is MASK, we don't
8104 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8105 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
8109 /* If it remains an AND, try making another AND with the bits
8110 in the mode mask that aren't in MASK turned on. If the
8111 constant in the AND is wide enough, this might make a
8112 cheaper constant. */
8114 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8115 && GET_MODE_MASK (GET_MODE (x)) != mask
8116 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
8118 unsigned HOST_WIDE_INT cval
8119 = UINTVAL (XEXP (x, 1))
8120 | (GET_MODE_MASK (GET_MODE (x)) & ~mask);
8121 int width = GET_MODE_BITSIZE (GET_MODE (x));
8124 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
8125 number, sign extend it. */
8126 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
8127 && (cval & ((unsigned HOST_WIDE_INT) 1 << (width - 1))) != 0)
8128 cval |= (unsigned HOST_WIDE_INT) -1 << width;
8130 y = simplify_gen_binary (AND, GET_MODE (x),
8131 XEXP (x, 0), GEN_INT (cval));
8132 if (rtx_cost (y, SET, optimize_this_for_speed_p)
8133 < rtx_cost (x, SET, optimize_this_for_speed_p))
8143 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8144 low-order bits (as in an alignment operation) and FOO is already
8145 aligned to that boundary, mask C1 to that boundary as well.
8146 This may eliminate that PLUS and, later, the AND. */
8149 unsigned int width = GET_MODE_BITSIZE (mode);
8150 unsigned HOST_WIDE_INT smask = mask;
8152 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8153 number, sign extend it. */
8155 if (width < HOST_BITS_PER_WIDE_INT
8156 && (smask & ((unsigned HOST_WIDE_INT) 1 << (width - 1))) != 0)
8157 smask |= (unsigned HOST_WIDE_INT) (-1) << width;
8159 if (CONST_INT_P (XEXP (x, 1))
8160 && exact_log2 (- smask) >= 0
8161 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
8162 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
8163 return force_to_mode (plus_constant (XEXP (x, 0),
8164 (INTVAL (XEXP (x, 1)) & smask)),
8165 mode, smask, next_select);
8168 /* ... fall through ... */
8171 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8172 most significant bit in MASK since carries from those bits will
8173 affect the bits we are interested in. */
8178 /* If X is (minus C Y) where C's least set bit is larger than any bit
8179 in the mask, then we may replace with (neg Y). */
8180 if (CONST_INT_P (XEXP (x, 0))
8181 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
8182 & -INTVAL (XEXP (x, 0))))
8185 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
8187 return force_to_mode (x, mode, mask, next_select);
8190 /* Similarly, if C contains every bit in the fuller_mask, then we may
8191 replace with (not Y). */
8192 if (CONST_INT_P (XEXP (x, 0))
8193 && ((UINTVAL (XEXP (x, 0)) | fuller_mask) == UINTVAL (XEXP (x, 0))))
8195 x = simplify_gen_unary (NOT, GET_MODE (x),
8196 XEXP (x, 1), GET_MODE (x));
8197 return force_to_mode (x, mode, mask, next_select);
8205 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8206 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8207 operation which may be a bitfield extraction. Ensure that the
8208 constant we form is not wider than the mode of X. */
8210 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8211 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8212 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8213 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
8214 && CONST_INT_P (XEXP (x, 1))
8215 && ((INTVAL (XEXP (XEXP (x, 0), 1))
8216 + floor_log2 (INTVAL (XEXP (x, 1))))
8217 < GET_MODE_BITSIZE (GET_MODE (x)))
8218 && (UINTVAL (XEXP (x, 1))
8219 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
8221 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
8222 << INTVAL (XEXP (XEXP (x, 0), 1)));
8223 temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
8224 XEXP (XEXP (x, 0), 0), temp);
8225 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
8226 XEXP (XEXP (x, 0), 1));
8227 return force_to_mode (x, mode, mask, next_select);
8231 /* For most binary operations, just propagate into the operation and
8232 change the mode if we have an operation of that mode. */
8234 op0 = force_to_mode (XEXP (x, 0), mode, mask, next_select);
8235 op1 = force_to_mode (XEXP (x, 1), mode, mask, next_select);
8237 /* If we ended up truncating both operands, truncate the result of the
8238 operation instead. */
8239 if (GET_CODE (op0) == TRUNCATE
8240 && GET_CODE (op1) == TRUNCATE)
8242 op0 = XEXP (op0, 0);
8243 op1 = XEXP (op1, 0);
8246 op0 = gen_lowpart_or_truncate (op_mode, op0);
8247 op1 = gen_lowpart_or_truncate (op_mode, op1);
8249 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8250 x = simplify_gen_binary (code, op_mode, op0, op1);
8254 /* For left shifts, do the same, but just for the first operand.
8255 However, we cannot do anything with shifts where we cannot
8256 guarantee that the counts are smaller than the size of the mode
8257 because such a count will have a different meaning in a
8260 if (! (CONST_INT_P (XEXP (x, 1))
8261 && INTVAL (XEXP (x, 1)) >= 0
8262 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
8263 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
8264 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
8265 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
8268 /* If the shift count is a constant and we can do arithmetic in
8269 the mode of the shift, refine which bits we need. Otherwise, use the
8270 conservative form of the mask. */
8271 if (CONST_INT_P (XEXP (x, 1))
8272 && INTVAL (XEXP (x, 1)) >= 0
8273 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
8274 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
8275 mask >>= INTVAL (XEXP (x, 1));
8279 op0 = gen_lowpart_or_truncate (op_mode,
8280 force_to_mode (XEXP (x, 0), op_mode,
8281 mask, next_select));
8283 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8284 x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
8288 /* Here we can only do something if the shift count is a constant,
8289 this shift constant is valid for the host, and we can do arithmetic
8292 if (CONST_INT_P (XEXP (x, 1))
8293 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
8294 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
8296 rtx inner = XEXP (x, 0);
8297 unsigned HOST_WIDE_INT inner_mask;
8299 /* Select the mask of the bits we need for the shift operand. */
8300 inner_mask = mask << INTVAL (XEXP (x, 1));
8302 /* We can only change the mode of the shift if we can do arithmetic
8303 in the mode of the shift and INNER_MASK is no wider than the
8304 width of X's mode. */
8305 if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
8306 op_mode = GET_MODE (x);
8308 inner = force_to_mode (inner, op_mode, inner_mask, next_select);
8310 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
8311 x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
8314 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8315 shift and AND produces only copies of the sign bit (C2 is one less
8316 than a power of two), we can do this with just a shift. */
8318 if (GET_CODE (x) == LSHIFTRT
8319 && CONST_INT_P (XEXP (x, 1))
8320 /* The shift puts one of the sign bit copies in the least significant
8322 && ((INTVAL (XEXP (x, 1))
8323 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
8324 >= GET_MODE_BITSIZE (GET_MODE (x)))
8325 && exact_log2 (mask + 1) >= 0
8326 /* Number of bits left after the shift must be more than the mask
8328 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
8329 <= GET_MODE_BITSIZE (GET_MODE (x)))
8330 /* Must be more sign bit copies than the mask needs. */
8331 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
8332 >= exact_log2 (mask + 1)))
8333 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
8334 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
8335 - exact_log2 (mask + 1)));
8340 /* If we are just looking for the sign bit, we don't need this shift at
8341 all, even if it has a variable count. */
8342 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
8343 && (mask == ((unsigned HOST_WIDE_INT) 1
8344 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8345 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8347 /* If this is a shift by a constant, get a mask that contains those bits
8348 that are not copies of the sign bit. We then have two cases: If
8349 MASK only includes those bits, this can be a logical shift, which may
8350 allow simplifications. If MASK is a single-bit field not within
8351 those bits, we are requesting a copy of the sign bit and hence can
8352 shift the sign bit to the appropriate location. */
8354 if (CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) >= 0
8355 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8359 /* If the considered data is wider than HOST_WIDE_INT, we can't
8360 represent a mask for all its bits in a single scalar.
8361 But we only care about the lower bits, so calculate these. */
8363 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
8365 nonzero = ~(unsigned HOST_WIDE_INT) 0;
8367 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8368 is the number of bits a full-width mask would have set.
8369 We need only shift if these are fewer than nonzero can
8370 hold. If not, we must keep all bits set in nonzero. */
8372 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8373 < HOST_BITS_PER_WIDE_INT)
8374 nonzero >>= INTVAL (XEXP (x, 1))
8375 + HOST_BITS_PER_WIDE_INT
8376 - GET_MODE_BITSIZE (GET_MODE (x)) ;
8380 nonzero = GET_MODE_MASK (GET_MODE (x));
8381 nonzero >>= INTVAL (XEXP (x, 1));
8384 if ((mask & ~nonzero) == 0)
8386 x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
8387 XEXP (x, 0), INTVAL (XEXP (x, 1)));
8388 if (GET_CODE (x) != ASHIFTRT)
8389 return force_to_mode (x, mode, mask, next_select);
8392 else if ((i = exact_log2 (mask)) >= 0)
8394 x = simplify_shift_const
8395 (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
8396 GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
8398 if (GET_CODE (x) != ASHIFTRT)
8399 return force_to_mode (x, mode, mask, next_select);
8403 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8404 even if the shift count isn't a constant. */
8406 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8407 XEXP (x, 0), XEXP (x, 1));
8411 /* If this is a zero- or sign-extension operation that just affects bits
8412 we don't care about, remove it. Be sure the call above returned
8413 something that is still a shift. */
8415 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
8416 && CONST_INT_P (XEXP (x, 1))
8417 && INTVAL (XEXP (x, 1)) >= 0
8418 && (INTVAL (XEXP (x, 1))
8419 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
8420 && GET_CODE (XEXP (x, 0)) == ASHIFT
8421 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
8422 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
8429 /* If the shift count is constant and we can do computations
8430 in the mode of X, compute where the bits we care about are.
8431 Otherwise, we can't do anything. Don't change the mode of
8432 the shift or propagate MODE into the shift, though. */
8433 if (CONST_INT_P (XEXP (x, 1))
8434 && INTVAL (XEXP (x, 1)) >= 0)
8436 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
8437 GET_MODE (x), GEN_INT (mask),
8439 if (temp && CONST_INT_P (temp))
8441 force_to_mode (XEXP (x, 0), GET_MODE (x),
8442 INTVAL (temp), next_select));
8447 /* If we just want the low-order bit, the NEG isn't needed since it
8448 won't change the low-order bit. */
8450 return force_to_mode (XEXP (x, 0), mode, mask, just_select);
8452 /* We need any bits less significant than the most significant bit in
8453 MASK since carries from those bits will affect the bits we are
8459 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8460 same as the XOR case above. Ensure that the constant we form is not
8461 wider than the mode of X. */
8463 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8464 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8465 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8466 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
8467 < GET_MODE_BITSIZE (GET_MODE (x)))
8468 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
8470 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
8472 temp = simplify_gen_binary (XOR, GET_MODE (x),
8473 XEXP (XEXP (x, 0), 0), temp);
8474 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8475 temp, XEXP (XEXP (x, 0), 1));
8477 return force_to_mode (x, mode, mask, next_select);
8480 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8481 use the full mask inside the NOT. */
8485 op0 = gen_lowpart_or_truncate (op_mode,
8486 force_to_mode (XEXP (x, 0), mode, mask,
8488 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8489 x = simplify_gen_unary (code, op_mode, op0, op_mode);
8493 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8494 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8495 which is equal to STORE_FLAG_VALUE. */
8496 if ((mask & ~STORE_FLAG_VALUE) == 0
8497 && XEXP (x, 1) == const0_rtx
8498 && GET_MODE (XEXP (x, 0)) == mode
8499 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
8500 && (nonzero_bits (XEXP (x, 0), mode)
8501 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
8502 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8507 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8508 written in a narrower mode. We play it safe and do not do so. */
8511 gen_lowpart_or_truncate (GET_MODE (x),
8512 force_to_mode (XEXP (x, 1), mode,
8513 mask, next_select)));
8515 gen_lowpart_or_truncate (GET_MODE (x),
8516 force_to_mode (XEXP (x, 2), mode,
8517 mask, next_select)));
8524 /* Ensure we return a value of the proper mode. */
8525 return gen_lowpart_or_truncate (mode, x);
8528 /* Return nonzero if X is an expression that has one of two values depending on
8529 whether some other value is zero or nonzero. In that case, we return the
8530 value that is being tested, *PTRUE is set to the value if the rtx being
8531 returned has a nonzero value, and *PFALSE is set to the other alternative.
8533 If we return zero, we set *PTRUE and *PFALSE to X. */
8536 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
8538 enum machine_mode mode = GET_MODE (x);
8539 enum rtx_code code = GET_CODE (x);
8540 rtx cond0, cond1, true0, true1, false0, false1;
8541 unsigned HOST_WIDE_INT nz;
8543 /* If we are comparing a value against zero, we are done. */
8544 if ((code == NE || code == EQ)
8545 && XEXP (x, 1) == const0_rtx)
8547 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
8548 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
8552 /* If this is a unary operation whose operand has one of two values, apply
8553 our opcode to compute those values. */
8554 else if (UNARY_P (x)
8555 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
8557 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
8558 *pfalse = simplify_gen_unary (code, mode, false0,
8559 GET_MODE (XEXP (x, 0)));
8563 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8564 make can't possibly match and would suppress other optimizations. */
8565 else if (code == COMPARE)
8568 /* If this is a binary operation, see if either side has only one of two
8569 values. If either one does or if both do and they are conditional on
8570 the same value, compute the new true and false values. */
8571 else if (BINARY_P (x))
8573 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
8574 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
8576 if ((cond0 != 0 || cond1 != 0)
8577 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
8579 /* If if_then_else_cond returned zero, then true/false are the
8580 same rtl. We must copy one of them to prevent invalid rtl
8583 true0 = copy_rtx (true0);
8584 else if (cond1 == 0)
8585 true1 = copy_rtx (true1);
8587 if (COMPARISON_P (x))
8589 *ptrue = simplify_gen_relational (code, mode, VOIDmode,
8591 *pfalse = simplify_gen_relational (code, mode, VOIDmode,
8596 *ptrue = simplify_gen_binary (code, mode, true0, true1);
8597 *pfalse = simplify_gen_binary (code, mode, false0, false1);
8600 return cond0 ? cond0 : cond1;
8603 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8604 operands is zero when the other is nonzero, and vice-versa,
8605 and STORE_FLAG_VALUE is 1 or -1. */
8607 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8608 && (code == PLUS || code == IOR || code == XOR || code == MINUS
8610 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8612 rtx op0 = XEXP (XEXP (x, 0), 1);
8613 rtx op1 = XEXP (XEXP (x, 1), 1);
8615 cond0 = XEXP (XEXP (x, 0), 0);
8616 cond1 = XEXP (XEXP (x, 1), 0);
8618 if (COMPARISON_P (cond0)
8619 && COMPARISON_P (cond1)
8620 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8621 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8622 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8623 || ((swap_condition (GET_CODE (cond0))
8624 == reversed_comparison_code (cond1, NULL))
8625 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8626 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8627 && ! side_effects_p (x))
8629 *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
8630 *pfalse = simplify_gen_binary (MULT, mode,
8632 ? simplify_gen_unary (NEG, mode,
8640 /* Similarly for MULT, AND and UMIN, except that for these the result
8642 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8643 && (code == MULT || code == AND || code == UMIN)
8644 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8646 cond0 = XEXP (XEXP (x, 0), 0);
8647 cond1 = XEXP (XEXP (x, 1), 0);
8649 if (COMPARISON_P (cond0)
8650 && COMPARISON_P (cond1)
8651 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8652 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8653 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8654 || ((swap_condition (GET_CODE (cond0))
8655 == reversed_comparison_code (cond1, NULL))
8656 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8657 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8658 && ! side_effects_p (x))
8660 *ptrue = *pfalse = const0_rtx;
8666 else if (code == IF_THEN_ELSE)
8668 /* If we have IF_THEN_ELSE already, extract the condition and
8669 canonicalize it if it is NE or EQ. */
8670 cond0 = XEXP (x, 0);
8671 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
8672 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
8673 return XEXP (cond0, 0);
8674 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
8676 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
8677 return XEXP (cond0, 0);
8683 /* If X is a SUBREG, we can narrow both the true and false values
8684 if the inner expression, if there is a condition. */
8685 else if (code == SUBREG
8686 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
8689 true0 = simplify_gen_subreg (mode, true0,
8690 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8691 false0 = simplify_gen_subreg (mode, false0,
8692 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8693 if (true0 && false0)
8701 /* If X is a constant, this isn't special and will cause confusions
8702 if we treat it as such. Likewise if it is equivalent to a constant. */
8703 else if (CONSTANT_P (x)
8704 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
8707 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8708 will be least confusing to the rest of the compiler. */
8709 else if (mode == BImode)
8711 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
8715 /* If X is known to be either 0 or -1, those are the true and
8716 false values when testing X. */
8717 else if (x == constm1_rtx || x == const0_rtx
8718 || (mode != VOIDmode
8719 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
8721 *ptrue = constm1_rtx, *pfalse = const0_rtx;
8725 /* Likewise for 0 or a single bit. */
8726 else if (SCALAR_INT_MODE_P (mode)
8727 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8728 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
8730 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
8734 /* Otherwise fail; show no condition with true and false values the same. */
8735 *ptrue = *pfalse = x;
8739 /* Return the value of expression X given the fact that condition COND
8740 is known to be true when applied to REG as its first operand and VAL
8741 as its second. X is known to not be shared and so can be modified in
8744 We only handle the simplest cases, and specifically those cases that
8745 arise with IF_THEN_ELSE expressions. */
8748 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
8750 enum rtx_code code = GET_CODE (x);
8755 if (side_effects_p (x))
8758 /* If either operand of the condition is a floating point value,
8759 then we have to avoid collapsing an EQ comparison. */
8761 && rtx_equal_p (x, reg)
8762 && ! FLOAT_MODE_P (GET_MODE (x))
8763 && ! FLOAT_MODE_P (GET_MODE (val)))
8766 if (cond == UNEQ && rtx_equal_p (x, reg))
8769 /* If X is (abs REG) and we know something about REG's relationship
8770 with zero, we may be able to simplify this. */
8772 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
8775 case GE: case GT: case EQ:
8778 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
8780 GET_MODE (XEXP (x, 0)));
8785 /* The only other cases we handle are MIN, MAX, and comparisons if the
8786 operands are the same as REG and VAL. */
8788 else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
8790 if (rtx_equal_p (XEXP (x, 0), val))
8791 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
8793 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
8795 if (COMPARISON_P (x))
8797 if (comparison_dominates_p (cond, code))
8798 return const_true_rtx;
8800 code = reversed_comparison_code (x, NULL);
8802 && comparison_dominates_p (cond, code))
8807 else if (code == SMAX || code == SMIN
8808 || code == UMIN || code == UMAX)
8810 int unsignedp = (code == UMIN || code == UMAX);
8812 /* Do not reverse the condition when it is NE or EQ.
8813 This is because we cannot conclude anything about
8814 the value of 'SMAX (x, y)' when x is not equal to y,
8815 but we can when x equals y. */
8816 if ((code == SMAX || code == UMAX)
8817 && ! (cond == EQ || cond == NE))
8818 cond = reverse_condition (cond);
8823 return unsignedp ? x : XEXP (x, 1);
8825 return unsignedp ? x : XEXP (x, 0);
8827 return unsignedp ? XEXP (x, 1) : x;
8829 return unsignedp ? XEXP (x, 0) : x;
8836 else if (code == SUBREG)
8838 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
8839 rtx new_rtx, r = known_cond (SUBREG_REG (x), cond, reg, val);
8841 if (SUBREG_REG (x) != r)
8843 /* We must simplify subreg here, before we lose track of the
8844 original inner_mode. */
8845 new_rtx = simplify_subreg (GET_MODE (x), r,
8846 inner_mode, SUBREG_BYTE (x));
8850 SUBST (SUBREG_REG (x), r);
8855 /* We don't have to handle SIGN_EXTEND here, because even in the
8856 case of replacing something with a modeless CONST_INT, a
8857 CONST_INT is already (supposed to be) a valid sign extension for
8858 its narrower mode, which implies it's already properly
8859 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
8860 story is different. */
8861 else if (code == ZERO_EXTEND)
8863 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
8864 rtx new_rtx, r = known_cond (XEXP (x, 0), cond, reg, val);
8866 if (XEXP (x, 0) != r)
8868 /* We must simplify the zero_extend here, before we lose
8869 track of the original inner_mode. */
8870 new_rtx = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
8875 SUBST (XEXP (x, 0), r);
8881 fmt = GET_RTX_FORMAT (code);
8882 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8885 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
8886 else if (fmt[i] == 'E')
8887 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8888 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
8895 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8896 assignment as a field assignment. */
8899 rtx_equal_for_field_assignment_p (rtx x, rtx y)
8901 if (x == y || rtx_equal_p (x, y))
8904 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
8907 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8908 Note that all SUBREGs of MEM are paradoxical; otherwise they
8909 would have been rewritten. */
8910 if (MEM_P (x) && GET_CODE (y) == SUBREG
8911 && MEM_P (SUBREG_REG (y))
8912 && rtx_equal_p (SUBREG_REG (y),
8913 gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
8916 if (MEM_P (y) && GET_CODE (x) == SUBREG
8917 && MEM_P (SUBREG_REG (x))
8918 && rtx_equal_p (SUBREG_REG (x),
8919 gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
8922 /* We used to see if get_last_value of X and Y were the same but that's
8923 not correct. In one direction, we'll cause the assignment to have
8924 the wrong destination and in the case, we'll import a register into this
8925 insn that might have already have been dead. So fail if none of the
8926 above cases are true. */
8930 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8931 Return that assignment if so.
8933 We only handle the most common cases. */
8936 make_field_assignment (rtx x)
8938 rtx dest = SET_DEST (x);
8939 rtx src = SET_SRC (x);
8944 unsigned HOST_WIDE_INT len;
8946 enum machine_mode mode;
8948 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
8949 a clear of a one-bit field. We will have changed it to
8950 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
8953 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
8954 && CONST_INT_P (XEXP (XEXP (src, 0), 0))
8955 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
8956 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8958 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8961 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8965 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
8966 && subreg_lowpart_p (XEXP (src, 0))
8967 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
8968 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
8969 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
8970 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src, 0)), 0))
8971 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
8972 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8974 assign = make_extraction (VOIDmode, dest, 0,
8975 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
8978 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8982 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
8984 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
8985 && XEXP (XEXP (src, 0), 0) == const1_rtx
8986 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8988 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8991 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
8995 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
8996 SRC is an AND with all bits of that field set, then we can discard
8998 if (GET_CODE (dest) == ZERO_EXTRACT
8999 && CONST_INT_P (XEXP (dest, 1))
9000 && GET_CODE (src) == AND
9001 && CONST_INT_P (XEXP (src, 1)))
9003 HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
9004 unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
9005 unsigned HOST_WIDE_INT ze_mask;
9007 if (width >= HOST_BITS_PER_WIDE_INT)
9010 ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
9012 /* Complete overlap. We can remove the source AND. */
9013 if ((and_mask & ze_mask) == ze_mask)
9014 return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
9016 /* Partial overlap. We can reduce the source AND. */
9017 if ((and_mask & ze_mask) != and_mask)
9019 mode = GET_MODE (src);
9020 src = gen_rtx_AND (mode, XEXP (src, 0),
9021 gen_int_mode (and_mask & ze_mask, mode));
9022 return gen_rtx_SET (VOIDmode, dest, src);
9026 /* The other case we handle is assignments into a constant-position
9027 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9028 a mask that has all one bits except for a group of zero bits and
9029 OTHER is known to have zeros where C1 has ones, this is such an
9030 assignment. Compute the position and length from C1. Shift OTHER
9031 to the appropriate position, force it to the required mode, and
9032 make the extraction. Check for the AND in both operands. */
9034 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
9037 rhs = expand_compound_operation (XEXP (src, 0));
9038 lhs = expand_compound_operation (XEXP (src, 1));
9040 if (GET_CODE (rhs) == AND
9041 && CONST_INT_P (XEXP (rhs, 1))
9042 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
9043 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
9044 else if (GET_CODE (lhs) == AND
9045 && CONST_INT_P (XEXP (lhs, 1))
9046 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
9047 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
9051 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
9052 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
9053 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
9054 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
9057 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
9061 /* The mode to use for the source is the mode of the assignment, or of
9062 what is inside a possible STRICT_LOW_PART. */
9063 mode = (GET_CODE (assign) == STRICT_LOW_PART
9064 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
9066 /* Shift OTHER right POS places and make it the source, restricting it
9067 to the proper length and mode. */
9069 src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
9073 src = force_to_mode (src, mode,
9074 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
9075 ? ~(unsigned HOST_WIDE_INT) 0
9076 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
9079 /* If SRC is masked by an AND that does not make a difference in
9080 the value being stored, strip it. */
9081 if (GET_CODE (assign) == ZERO_EXTRACT
9082 && CONST_INT_P (XEXP (assign, 1))
9083 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
9084 && GET_CODE (src) == AND
9085 && CONST_INT_P (XEXP (src, 1))
9086 && UINTVAL (XEXP (src, 1))
9087 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1)
9088 src = XEXP (src, 0);
9090 return gen_rtx_SET (VOIDmode, assign, src);
9093 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9097 apply_distributive_law (rtx x)
9099 enum rtx_code code = GET_CODE (x);
9100 enum rtx_code inner_code;
9101 rtx lhs, rhs, other;
9104 /* Distributivity is not true for floating point as it can change the
9105 value. So we don't do it unless -funsafe-math-optimizations. */
9106 if (FLOAT_MODE_P (GET_MODE (x))
9107 && ! flag_unsafe_math_optimizations)
9110 /* The outer operation can only be one of the following: */
9111 if (code != IOR && code != AND && code != XOR
9112 && code != PLUS && code != MINUS)
9118 /* If either operand is a primitive we can't do anything, so get out
9120 if (OBJECT_P (lhs) || OBJECT_P (rhs))
9123 lhs = expand_compound_operation (lhs);
9124 rhs = expand_compound_operation (rhs);
9125 inner_code = GET_CODE (lhs);
9126 if (inner_code != GET_CODE (rhs))
9129 /* See if the inner and outer operations distribute. */
9136 /* These all distribute except over PLUS. */
9137 if (code == PLUS || code == MINUS)
9142 if (code != PLUS && code != MINUS)
9147 /* This is also a multiply, so it distributes over everything. */
9151 /* Non-paradoxical SUBREGs distributes over all operations,
9152 provided the inner modes and byte offsets are the same, this
9153 is an extraction of a low-order part, we don't convert an fp
9154 operation to int or vice versa, this is not a vector mode,
9155 and we would not be converting a single-word operation into a
9156 multi-word operation. The latter test is not required, but
9157 it prevents generating unneeded multi-word operations. Some
9158 of the previous tests are redundant given the latter test,
9159 but are retained because they are required for correctness.
9161 We produce the result slightly differently in this case. */
9163 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
9164 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
9165 || ! subreg_lowpart_p (lhs)
9166 || (GET_MODE_CLASS (GET_MODE (lhs))
9167 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
9168 || (GET_MODE_SIZE (GET_MODE (lhs))
9169 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
9170 || VECTOR_MODE_P (GET_MODE (lhs))
9171 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD
9172 /* Result might need to be truncated. Don't change mode if
9173 explicit truncation is needed. */
9174 || !TRULY_NOOP_TRUNCATION
9175 (GET_MODE_BITSIZE (GET_MODE (x)),
9176 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (lhs)))))
9179 tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
9180 SUBREG_REG (lhs), SUBREG_REG (rhs));
9181 return gen_lowpart (GET_MODE (x), tem);
9187 /* Set LHS and RHS to the inner operands (A and B in the example
9188 above) and set OTHER to the common operand (C in the example).
9189 There is only one way to do this unless the inner operation is
9191 if (COMMUTATIVE_ARITH_P (lhs)
9192 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
9193 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
9194 else if (COMMUTATIVE_ARITH_P (lhs)
9195 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
9196 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
9197 else if (COMMUTATIVE_ARITH_P (lhs)
9198 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
9199 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
9200 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
9201 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
9205 /* Form the new inner operation, seeing if it simplifies first. */
9206 tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
9208 /* There is one exception to the general way of distributing:
9209 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9210 if (code == XOR && inner_code == IOR)
9213 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
9216 /* We may be able to continuing distributing the result, so call
9217 ourselves recursively on the inner operation before forming the
9218 outer operation, which we return. */
9219 return simplify_gen_binary (inner_code, GET_MODE (x),
9220 apply_distributive_law (tem), other);
9223 /* See if X is of the form (* (+ A B) C), and if so convert to
9224 (+ (* A C) (* B C)) and try to simplify.
9226 Most of the time, this results in no change. However, if some of
9227 the operands are the same or inverses of each other, simplifications
9230 For example, (and (ior A B) (not B)) can occur as the result of
9231 expanding a bit field assignment. When we apply the distributive
9232 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9233 which then simplifies to (and (A (not B))).
9235 Note that no checks happen on the validity of applying the inverse
9236 distributive law. This is pointless since we can do it in the
9237 few places where this routine is called.
9239 N is the index of the term that is decomposed (the arithmetic operation,
9240 i.e. (+ A B) in the first example above). !N is the index of the term that
9241 is distributed, i.e. of C in the first example above. */
9243 distribute_and_simplify_rtx (rtx x, int n)
9245 enum machine_mode mode;
9246 enum rtx_code outer_code, inner_code;
9247 rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
9249 /* Distributivity is not true for floating point as it can change the
9250 value. So we don't do it unless -funsafe-math-optimizations. */
9251 if (FLOAT_MODE_P (GET_MODE (x))
9252 && ! flag_unsafe_math_optimizations)
9255 decomposed = XEXP (x, n);
9256 if (!ARITHMETIC_P (decomposed))
9259 mode = GET_MODE (x);
9260 outer_code = GET_CODE (x);
9261 distributed = XEXP (x, !n);
9263 inner_code = GET_CODE (decomposed);
9264 inner_op0 = XEXP (decomposed, 0);
9265 inner_op1 = XEXP (decomposed, 1);
9267 /* Special case (and (xor B C) (not A)), which is equivalent to
9268 (xor (ior A B) (ior A C)) */
9269 if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
9271 distributed = XEXP (distributed, 0);
9277 /* Distribute the second term. */
9278 new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
9279 new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
9283 /* Distribute the first term. */
9284 new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
9285 new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
9288 tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
9290 if (GET_CODE (tmp) != outer_code
9291 && rtx_cost (tmp, SET, optimize_this_for_speed_p)
9292 < rtx_cost (x, SET, optimize_this_for_speed_p))
9298 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9299 in MODE. Return an equivalent form, if different from (and VAROP
9300 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9303 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
9304 unsigned HOST_WIDE_INT constop)
9306 unsigned HOST_WIDE_INT nonzero;
9307 unsigned HOST_WIDE_INT orig_constop;
9312 orig_constop = constop;
9313 if (GET_CODE (varop) == CLOBBER)
9316 /* Simplify VAROP knowing that we will be only looking at some of the
9319 Note by passing in CONSTOP, we guarantee that the bits not set in
9320 CONSTOP are not significant and will never be examined. We must
9321 ensure that is the case by explicitly masking out those bits
9322 before returning. */
9323 varop = force_to_mode (varop, mode, constop, 0);
9325 /* If VAROP is a CLOBBER, we will fail so return it. */
9326 if (GET_CODE (varop) == CLOBBER)
9329 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9330 to VAROP and return the new constant. */
9331 if (CONST_INT_P (varop))
9332 return gen_int_mode (INTVAL (varop) & constop, mode);
9334 /* See what bits may be nonzero in VAROP. Unlike the general case of
9335 a call to nonzero_bits, here we don't care about bits outside
9338 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
9340 /* Turn off all bits in the constant that are known to already be zero.
9341 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9342 which is tested below. */
9346 /* If we don't have any bits left, return zero. */
9350 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9351 a power of two, we can replace this with an ASHIFT. */
9352 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
9353 && (i = exact_log2 (constop)) >= 0)
9354 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
9356 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9357 or XOR, then try to apply the distributive law. This may eliminate
9358 operations if either branch can be simplified because of the AND.
9359 It may also make some cases more complex, but those cases probably
9360 won't match a pattern either with or without this. */
9362 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
9366 apply_distributive_law
9367 (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
9368 simplify_and_const_int (NULL_RTX,
9372 simplify_and_const_int (NULL_RTX,
9377 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9378 the AND and see if one of the operands simplifies to zero. If so, we
9379 may eliminate it. */
9381 if (GET_CODE (varop) == PLUS
9382 && exact_log2 (constop + 1) >= 0)
9386 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
9387 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
9388 if (o0 == const0_rtx)
9390 if (o1 == const0_rtx)
9394 /* Make a SUBREG if necessary. If we can't make it, fail. */
9395 varop = gen_lowpart (mode, varop);
9396 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
9399 /* If we are only masking insignificant bits, return VAROP. */
9400 if (constop == nonzero)
9403 if (varop == orig_varop && constop == orig_constop)
9406 /* Otherwise, return an AND. */
9407 return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
9411 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9414 Return an equivalent form, if different from X. Otherwise, return X. If
9415 X is zero, we are to always construct the equivalent form. */
9418 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
9419 unsigned HOST_WIDE_INT constop)
9421 rtx tem = simplify_and_const_int_1 (mode, varop, constop);
9426 x = simplify_gen_binary (AND, GET_MODE (varop), varop,
9427 gen_int_mode (constop, mode));
9428 if (GET_MODE (x) != mode)
9429 x = gen_lowpart (mode, x);
9433 /* Given a REG, X, compute which bits in X can be nonzero.
9434 We don't care about bits outside of those defined in MODE.
9436 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9437 a shift, AND, or zero_extract, we can do better. */
9440 reg_nonzero_bits_for_combine (const_rtx x, enum machine_mode mode,
9441 const_rtx known_x ATTRIBUTE_UNUSED,
9442 enum machine_mode known_mode ATTRIBUTE_UNUSED,
9443 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
9444 unsigned HOST_WIDE_INT *nonzero)
9449 /* If X is a register whose nonzero bits value is current, use it.
9450 Otherwise, if X is a register whose value we can find, use that
9451 value. Otherwise, use the previously-computed global nonzero bits
9452 for this register. */
9454 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
9455 if (rsp->last_set_value != 0
9456 && (rsp->last_set_mode == mode
9457 || (GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT
9458 && GET_MODE_CLASS (mode) == MODE_INT))
9459 && ((rsp->last_set_label >= label_tick_ebb_start
9460 && rsp->last_set_label < label_tick)
9461 || (rsp->last_set_label == label_tick
9462 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9463 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9464 && REG_N_SETS (REGNO (x)) == 1
9466 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9468 *nonzero &= rsp->last_set_nonzero_bits;
9472 tem = get_last_value (x);
9476 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9477 /* If X is narrower than MODE and TEM is a non-negative
9478 constant that would appear negative in the mode of X,
9479 sign-extend it for use in reg_nonzero_bits because some
9480 machines (maybe most) will actually do the sign-extension
9481 and this is the conservative approach.
9483 ??? For 2.5, try to tighten up the MD files in this regard
9484 instead of this kludge. */
9486 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)
9487 && CONST_INT_P (tem)
9489 && 0 != (UINTVAL (tem)
9490 & ((unsigned HOST_WIDE_INT) 1
9491 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
9492 tem = GEN_INT (UINTVAL (tem)
9493 | ((unsigned HOST_WIDE_INT) (-1)
9494 << GET_MODE_BITSIZE (GET_MODE (x))));
9498 else if (nonzero_sign_valid && rsp->nonzero_bits)
9500 unsigned HOST_WIDE_INT mask = rsp->nonzero_bits;
9502 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode))
9503 /* We don't know anything about the upper bits. */
9504 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
9511 /* Return the number of bits at the high-order end of X that are known to
9512 be equal to the sign bit. X will be used in mode MODE; if MODE is
9513 VOIDmode, X will be used in its own mode. The returned value will always
9514 be between 1 and the number of bits in MODE. */
9517 reg_num_sign_bit_copies_for_combine (const_rtx x, enum machine_mode mode,
9518 const_rtx known_x ATTRIBUTE_UNUSED,
9519 enum machine_mode known_mode
9521 unsigned int known_ret ATTRIBUTE_UNUSED,
9522 unsigned int *result)
9527 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
9528 if (rsp->last_set_value != 0
9529 && rsp->last_set_mode == mode
9530 && ((rsp->last_set_label >= label_tick_ebb_start
9531 && rsp->last_set_label < label_tick)
9532 || (rsp->last_set_label == label_tick
9533 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9534 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9535 && REG_N_SETS (REGNO (x)) == 1
9537 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9539 *result = rsp->last_set_sign_bit_copies;
9543 tem = get_last_value (x);
9547 if (nonzero_sign_valid && rsp->sign_bit_copies != 0
9548 && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode))
9549 *result = rsp->sign_bit_copies;
9554 /* Return the number of "extended" bits there are in X, when interpreted
9555 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9556 unsigned quantities, this is the number of high-order zero bits.
9557 For signed quantities, this is the number of copies of the sign bit
9558 minus 1. In both case, this function returns the number of "spare"
9559 bits. For example, if two quantities for which this function returns
9560 at least 1 are added, the addition is known not to overflow.
9562 This function will always return 0 unless called during combine, which
9563 implies that it must be called from a define_split. */
9566 extended_count (const_rtx x, enum machine_mode mode, int unsignedp)
9568 if (nonzero_sign_valid == 0)
9572 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9573 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
9574 - floor_log2 (nonzero_bits (x, mode)))
9576 : num_sign_bit_copies (x, mode) - 1);
9579 /* This function is called from `simplify_shift_const' to merge two
9580 outer operations. Specifically, we have already found that we need
9581 to perform operation *POP0 with constant *PCONST0 at the outermost
9582 position. We would now like to also perform OP1 with constant CONST1
9583 (with *POP0 being done last).
9585 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9586 the resulting operation. *PCOMP_P is set to 1 if we would need to
9587 complement the innermost operand, otherwise it is unchanged.
9589 MODE is the mode in which the operation will be done. No bits outside
9590 the width of this mode matter. It is assumed that the width of this mode
9591 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9593 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9594 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9595 result is simply *PCONST0.
9597 If the resulting operation cannot be expressed as one operation, we
9598 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9601 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
9603 enum rtx_code op0 = *pop0;
9604 HOST_WIDE_INT const0 = *pconst0;
9606 const0 &= GET_MODE_MASK (mode);
9607 const1 &= GET_MODE_MASK (mode);
9609 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9613 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9616 if (op1 == UNKNOWN || op0 == SET)
9619 else if (op0 == UNKNOWN)
9620 op0 = op1, const0 = const1;
9622 else if (op0 == op1)
9646 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9647 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
9650 /* If the two constants aren't the same, we can't do anything. The
9651 remaining six cases can all be done. */
9652 else if (const0 != const1)
9660 /* (a & b) | b == b */
9662 else /* op1 == XOR */
9663 /* (a ^ b) | b == a | b */
9669 /* (a & b) ^ b == (~a) & b */
9670 op0 = AND, *pcomp_p = 1;
9671 else /* op1 == IOR */
9672 /* (a | b) ^ b == a & ~b */
9673 op0 = AND, const0 = ~const0;
9678 /* (a | b) & b == b */
9680 else /* op1 == XOR */
9681 /* (a ^ b) & b) == (~a) & b */
9688 /* Check for NO-OP cases. */
9689 const0 &= GET_MODE_MASK (mode);
9691 && (op0 == IOR || op0 == XOR || op0 == PLUS))
9693 else if (const0 == 0 && op0 == AND)
9695 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
9701 /* ??? Slightly redundant with the above mask, but not entirely.
9702 Moving this above means we'd have to sign-extend the mode mask
9703 for the final test. */
9704 if (op0 != UNKNOWN && op0 != NEG)
9705 *pconst0 = trunc_int_for_mode (const0, mode);
9710 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9711 the shift in. The original shift operation CODE is performed on OP in
9712 ORIG_MODE. Return the wider mode MODE if we can perform the operation
9713 in that mode. Return ORIG_MODE otherwise. We can also assume that the
9714 result of the shift is subject to operation OUTER_CODE with operand
9717 static enum machine_mode
9718 try_widen_shift_mode (enum rtx_code code, rtx op, int count,
9719 enum machine_mode orig_mode, enum machine_mode mode,
9720 enum rtx_code outer_code, HOST_WIDE_INT outer_const)
9722 if (orig_mode == mode)
9724 gcc_assert (GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (orig_mode));
9726 /* In general we can't perform in wider mode for right shift and rotate. */
9730 /* We can still widen if the bits brought in from the left are identical
9731 to the sign bit of ORIG_MODE. */
9732 if (num_sign_bit_copies (op, mode)
9733 > (unsigned) (GET_MODE_BITSIZE (mode)
9734 - GET_MODE_BITSIZE (orig_mode)))
9739 /* Similarly here but with zero bits. */
9740 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9741 && (nonzero_bits (op, mode) & ~GET_MODE_MASK (orig_mode)) == 0)
9744 /* We can also widen if the bits brought in will be masked off. This
9745 operation is performed in ORIG_MODE. */
9746 if (outer_code == AND)
9748 int care_bits = low_bitmask_len (orig_mode, outer_const);
9751 && GET_MODE_BITSIZE (orig_mode) - care_bits >= count)
9767 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9768 The result of the shift is RESULT_MODE. Return NULL_RTX if we cannot
9769 simplify it. Otherwise, return a simplified value.
9771 The shift is normally computed in the widest mode we find in VAROP, as
9772 long as it isn't a different number of words than RESULT_MODE. Exceptions
9773 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9776 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
9777 rtx varop, int orig_count)
9779 enum rtx_code orig_code = code;
9780 rtx orig_varop = varop;
9782 enum machine_mode mode = result_mode;
9783 enum machine_mode shift_mode, tmode;
9784 unsigned int mode_words
9785 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
9786 /* We form (outer_op (code varop count) (outer_const)). */
9787 enum rtx_code outer_op = UNKNOWN;
9788 HOST_WIDE_INT outer_const = 0;
9789 int complement_p = 0;
9792 /* Make sure and truncate the "natural" shift on the way in. We don't
9793 want to do this inside the loop as it makes it more difficult to
9795 if (SHIFT_COUNT_TRUNCATED)
9796 orig_count &= GET_MODE_BITSIZE (mode) - 1;
9798 /* If we were given an invalid count, don't do anything except exactly
9799 what was requested. */
9801 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
9806 /* Unless one of the branches of the `if' in this loop does a `continue',
9807 we will `break' the loop after the `if'. */
9811 /* If we have an operand of (clobber (const_int 0)), fail. */
9812 if (GET_CODE (varop) == CLOBBER)
9815 /* Convert ROTATERT to ROTATE. */
9816 if (code == ROTATERT)
9818 unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
9820 if (VECTOR_MODE_P (result_mode))
9821 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
9823 count = bitsize - count;
9826 shift_mode = try_widen_shift_mode (code, varop, count, result_mode,
9827 mode, outer_op, outer_const);
9829 /* Handle cases where the count is greater than the size of the mode
9830 minus 1. For ASHIFT, use the size minus one as the count (this can
9831 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9832 take the count modulo the size. For other shifts, the result is
9835 Since these shifts are being produced by the compiler by combining
9836 multiple operations, each of which are defined, we know what the
9837 result is supposed to be. */
9839 if (count > (GET_MODE_BITSIZE (shift_mode) - 1))
9841 if (code == ASHIFTRT)
9842 count = GET_MODE_BITSIZE (shift_mode) - 1;
9843 else if (code == ROTATE || code == ROTATERT)
9844 count %= GET_MODE_BITSIZE (shift_mode);
9847 /* We can't simply return zero because there may be an
9855 /* If we discovered we had to complement VAROP, leave. Making a NOT
9856 here would cause an infinite loop. */
9860 /* An arithmetic right shift of a quantity known to be -1 or 0
9862 if (code == ASHIFTRT
9863 && (num_sign_bit_copies (varop, shift_mode)
9864 == GET_MODE_BITSIZE (shift_mode)))
9870 /* If we are doing an arithmetic right shift and discarding all but
9871 the sign bit copies, this is equivalent to doing a shift by the
9872 bitsize minus one. Convert it into that shift because it will often
9873 allow other simplifications. */
9875 if (code == ASHIFTRT
9876 && (count + num_sign_bit_copies (varop, shift_mode)
9877 >= GET_MODE_BITSIZE (shift_mode)))
9878 count = GET_MODE_BITSIZE (shift_mode) - 1;
9880 /* We simplify the tests below and elsewhere by converting
9881 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9882 `make_compound_operation' will convert it to an ASHIFTRT for
9883 those machines (such as VAX) that don't have an LSHIFTRT. */
9884 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9886 && ((nonzero_bits (varop, shift_mode)
9887 & ((unsigned HOST_WIDE_INT) 1
9888 << (GET_MODE_BITSIZE (shift_mode) - 1))) == 0))
9891 if (((code == LSHIFTRT
9892 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9893 && !(nonzero_bits (varop, shift_mode) >> count))
9895 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9896 && !((nonzero_bits (varop, shift_mode) << count)
9897 & GET_MODE_MASK (shift_mode))))
9898 && !side_effects_p (varop))
9901 switch (GET_CODE (varop))
9907 new_rtx = expand_compound_operation (varop);
9908 if (new_rtx != varop)
9916 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9917 minus the width of a smaller mode, we can do this with a
9918 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9919 if ((code == ASHIFTRT || code == LSHIFTRT)
9920 && ! mode_dependent_address_p (XEXP (varop, 0))
9921 && ! MEM_VOLATILE_P (varop)
9922 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9923 MODE_INT, 1)) != BLKmode)
9925 new_rtx = adjust_address_nv (varop, tmode,
9926 BYTES_BIG_ENDIAN ? 0
9927 : count / BITS_PER_UNIT);
9929 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9930 : ZERO_EXTEND, mode, new_rtx);
9937 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9938 the same number of words as what we've seen so far. Then store
9939 the widest mode in MODE. */
9940 if (subreg_lowpart_p (varop)
9941 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9942 > GET_MODE_SIZE (GET_MODE (varop)))
9943 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9944 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9946 && GET_MODE_CLASS (GET_MODE (varop)) == MODE_INT
9947 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (varop))) == MODE_INT)
9949 varop = SUBREG_REG (varop);
9950 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9951 mode = GET_MODE (varop);
9957 /* Some machines use MULT instead of ASHIFT because MULT
9958 is cheaper. But it is still better on those machines to
9959 merge two shifts into one. */
9960 if (CONST_INT_P (XEXP (varop, 1))
9961 && exact_log2 (UINTVAL (XEXP (varop, 1))) >= 0)
9964 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
9966 GEN_INT (exact_log2 (
9967 UINTVAL (XEXP (varop, 1)))));
9973 /* Similar, for when divides are cheaper. */
9974 if (CONST_INT_P (XEXP (varop, 1))
9975 && exact_log2 (UINTVAL (XEXP (varop, 1))) >= 0)
9978 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
9980 GEN_INT (exact_log2 (
9981 UINTVAL (XEXP (varop, 1)))));
9987 /* If we are extracting just the sign bit of an arithmetic
9988 right shift, that shift is not needed. However, the sign
9989 bit of a wider mode may be different from what would be
9990 interpreted as the sign bit in a narrower mode, so, if
9991 the result is narrower, don't discard the shift. */
9992 if (code == LSHIFTRT
9993 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9994 && (GET_MODE_BITSIZE (result_mode)
9995 >= GET_MODE_BITSIZE (GET_MODE (varop))))
9997 varop = XEXP (varop, 0);
10001 /* ... fall through ... */
10006 /* Here we have two nested shifts. The result is usually the
10007 AND of a new shift with a mask. We compute the result below. */
10008 if (CONST_INT_P (XEXP (varop, 1))
10009 && INTVAL (XEXP (varop, 1)) >= 0
10010 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
10011 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
10012 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
10013 && !VECTOR_MODE_P (result_mode))
10015 enum rtx_code first_code = GET_CODE (varop);
10016 unsigned int first_count = INTVAL (XEXP (varop, 1));
10017 unsigned HOST_WIDE_INT mask;
10020 /* We have one common special case. We can't do any merging if
10021 the inner code is an ASHIFTRT of a smaller mode. However, if
10022 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10023 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10024 we can convert it to
10025 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
10026 This simplifies certain SIGN_EXTEND operations. */
10027 if (code == ASHIFT && first_code == ASHIFTRT
10028 && count == (GET_MODE_BITSIZE (result_mode)
10029 - GET_MODE_BITSIZE (GET_MODE (varop))))
10031 /* C3 has the low-order C1 bits zero. */
10033 mask = GET_MODE_MASK (mode)
10034 & ~(((unsigned HOST_WIDE_INT) 1 << first_count) - 1);
10036 varop = simplify_and_const_int (NULL_RTX, result_mode,
10037 XEXP (varop, 0), mask);
10038 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
10040 count = first_count;
10045 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10046 than C1 high-order bits equal to the sign bit, we can convert
10047 this to either an ASHIFT or an ASHIFTRT depending on the
10050 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10052 if (code == ASHIFTRT && first_code == ASHIFT
10053 && GET_MODE (varop) == shift_mode
10054 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
10057 varop = XEXP (varop, 0);
10058 count -= first_count;
10068 /* There are some cases we can't do. If CODE is ASHIFTRT,
10069 we can only do this if FIRST_CODE is also ASHIFTRT.
10071 We can't do the case when CODE is ROTATE and FIRST_CODE is
10074 If the mode of this shift is not the mode of the outer shift,
10075 we can't do this if either shift is a right shift or ROTATE.
10077 Finally, we can't do any of these if the mode is too wide
10078 unless the codes are the same.
10080 Handle the case where the shift codes are the same
10083 if (code == first_code)
10085 if (GET_MODE (varop) != result_mode
10086 && (code == ASHIFTRT || code == LSHIFTRT
10087 || code == ROTATE))
10090 count += first_count;
10091 varop = XEXP (varop, 0);
10095 if (code == ASHIFTRT
10096 || (code == ROTATE && first_code == ASHIFTRT)
10097 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
10098 || (GET_MODE (varop) != result_mode
10099 && (first_code == ASHIFTRT || first_code == LSHIFTRT
10100 || first_code == ROTATE
10101 || code == ROTATE)))
10104 /* To compute the mask to apply after the shift, shift the
10105 nonzero bits of the inner shift the same way the
10106 outer shift will. */
10108 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
10111 = simplify_const_binary_operation (code, result_mode, mask_rtx,
10114 /* Give up if we can't compute an outer operation to use. */
10116 || !CONST_INT_P (mask_rtx)
10117 || ! merge_outer_ops (&outer_op, &outer_const, AND,
10119 result_mode, &complement_p))
10122 /* If the shifts are in the same direction, we add the
10123 counts. Otherwise, we subtract them. */
10124 if ((code == ASHIFTRT || code == LSHIFTRT)
10125 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
10126 count += first_count;
10128 count -= first_count;
10130 /* If COUNT is positive, the new shift is usually CODE,
10131 except for the two exceptions below, in which case it is
10132 FIRST_CODE. If the count is negative, FIRST_CODE should
10135 && ((first_code == ROTATE && code == ASHIFT)
10136 || (first_code == ASHIFTRT && code == LSHIFTRT)))
10138 else if (count < 0)
10139 code = first_code, count = -count;
10141 varop = XEXP (varop, 0);
10145 /* If we have (A << B << C) for any shift, we can convert this to
10146 (A << C << B). This wins if A is a constant. Only try this if
10147 B is not a constant. */
10149 else if (GET_CODE (varop) == code
10150 && CONST_INT_P (XEXP (varop, 0))
10151 && !CONST_INT_P (XEXP (varop, 1)))
10153 rtx new_rtx = simplify_const_binary_operation (code, mode,
10156 varop = gen_rtx_fmt_ee (code, mode, new_rtx, XEXP (varop, 1));
10163 if (VECTOR_MODE_P (mode))
10166 /* Make this fit the case below. */
10167 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
10168 GEN_INT (GET_MODE_MASK (mode)));
10174 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10175 with C the size of VAROP - 1 and the shift is logical if
10176 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10177 we have an (le X 0) operation. If we have an arithmetic shift
10178 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10179 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10181 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
10182 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
10183 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
10184 && (code == LSHIFTRT || code == ASHIFTRT)
10185 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
10186 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
10189 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
10192 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
10193 varop = gen_rtx_NEG (GET_MODE (varop), varop);
10198 /* If we have (shift (logical)), move the logical to the outside
10199 to allow it to possibly combine with another logical and the
10200 shift to combine with another shift. This also canonicalizes to
10201 what a ZERO_EXTRACT looks like. Also, some machines have
10202 (and (shift)) insns. */
10204 if (CONST_INT_P (XEXP (varop, 1))
10205 /* We can't do this if we have (ashiftrt (xor)) and the
10206 constant has its sign bit set in shift_mode. */
10207 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
10208 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
10210 && (new_rtx = simplify_const_binary_operation (code, result_mode,
10212 GEN_INT (count))) != 0
10213 && CONST_INT_P (new_rtx)
10214 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
10215 INTVAL (new_rtx), result_mode, &complement_p))
10217 varop = XEXP (varop, 0);
10221 /* If we can't do that, try to simplify the shift in each arm of the
10222 logical expression, make a new logical expression, and apply
10223 the inverse distributive law. This also can't be done
10224 for some (ashiftrt (xor)). */
10225 if (CONST_INT_P (XEXP (varop, 1))
10226 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
10227 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
10230 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
10231 XEXP (varop, 0), count);
10232 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
10233 XEXP (varop, 1), count);
10235 varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
10237 varop = apply_distributive_law (varop);
10245 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10246 says that the sign bit can be tested, FOO has mode MODE, C is
10247 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
10248 that may be nonzero. */
10249 if (code == LSHIFTRT
10250 && XEXP (varop, 1) == const0_rtx
10251 && GET_MODE (XEXP (varop, 0)) == result_mode
10252 && count == (GET_MODE_BITSIZE (result_mode) - 1)
10253 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
10254 && STORE_FLAG_VALUE == -1
10255 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
10256 && merge_outer_ops (&outer_op, &outer_const, XOR, 1, result_mode,
10259 varop = XEXP (varop, 0);
10266 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10267 than the number of bits in the mode is equivalent to A. */
10268 if (code == LSHIFTRT
10269 && count == (GET_MODE_BITSIZE (result_mode) - 1)
10270 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
10272 varop = XEXP (varop, 0);
10277 /* NEG commutes with ASHIFT since it is multiplication. Move the
10278 NEG outside to allow shifts to combine. */
10280 && merge_outer_ops (&outer_op, &outer_const, NEG, 0, result_mode,
10283 varop = XEXP (varop, 0);
10289 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10290 is one less than the number of bits in the mode is
10291 equivalent to (xor A 1). */
10292 if (code == LSHIFTRT
10293 && count == (GET_MODE_BITSIZE (result_mode) - 1)
10294 && XEXP (varop, 1) == constm1_rtx
10295 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
10296 && merge_outer_ops (&outer_op, &outer_const, XOR, 1, result_mode,
10300 varop = XEXP (varop, 0);
10304 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10305 that might be nonzero in BAR are those being shifted out and those
10306 bits are known zero in FOO, we can replace the PLUS with FOO.
10307 Similarly in the other operand order. This code occurs when
10308 we are computing the size of a variable-size array. */
10310 if ((code == ASHIFTRT || code == LSHIFTRT)
10311 && count < HOST_BITS_PER_WIDE_INT
10312 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
10313 && (nonzero_bits (XEXP (varop, 1), result_mode)
10314 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
10316 varop = XEXP (varop, 0);
10319 else if ((code == ASHIFTRT || code == LSHIFTRT)
10320 && count < HOST_BITS_PER_WIDE_INT
10321 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
10322 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
10324 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
10325 & nonzero_bits (XEXP (varop, 1),
10328 varop = XEXP (varop, 1);
10332 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10334 && CONST_INT_P (XEXP (varop, 1))
10335 && (new_rtx = simplify_const_binary_operation (ASHIFT, result_mode,
10337 GEN_INT (count))) != 0
10338 && CONST_INT_P (new_rtx)
10339 && merge_outer_ops (&outer_op, &outer_const, PLUS,
10340 INTVAL (new_rtx), result_mode, &complement_p))
10342 varop = XEXP (varop, 0);
10346 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10347 signbit', and attempt to change the PLUS to an XOR and move it to
10348 the outer operation as is done above in the AND/IOR/XOR case
10349 leg for shift(logical). See details in logical handling above
10350 for reasoning in doing so. */
10351 if (code == LSHIFTRT
10352 && CONST_INT_P (XEXP (varop, 1))
10353 && mode_signbit_p (result_mode, XEXP (varop, 1))
10354 && (new_rtx = simplify_const_binary_operation (code, result_mode,
10356 GEN_INT (count))) != 0
10357 && CONST_INT_P (new_rtx)
10358 && merge_outer_ops (&outer_op, &outer_const, XOR,
10359 INTVAL (new_rtx), result_mode, &complement_p))
10361 varop = XEXP (varop, 0);
10368 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10369 with C the size of VAROP - 1 and the shift is logical if
10370 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10371 we have a (gt X 0) operation. If the shift is arithmetic with
10372 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10373 we have a (neg (gt X 0)) operation. */
10375 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
10376 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
10377 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
10378 && (code == LSHIFTRT || code == ASHIFTRT)
10379 && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
10380 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
10381 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
10384 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
10387 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
10388 varop = gen_rtx_NEG (GET_MODE (varop), varop);
10395 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10396 if the truncate does not affect the value. */
10397 if (code == LSHIFTRT
10398 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
10399 && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
10400 && (INTVAL (XEXP (XEXP (varop, 0), 1))
10401 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
10402 - GET_MODE_BITSIZE (GET_MODE (varop)))))
10404 rtx varop_inner = XEXP (varop, 0);
10407 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
10408 XEXP (varop_inner, 0),
10410 (count + INTVAL (XEXP (varop_inner, 1))));
10411 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
10424 shift_mode = try_widen_shift_mode (code, varop, count, result_mode, mode,
10425 outer_op, outer_const);
10427 /* We have now finished analyzing the shift. The result should be
10428 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10429 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10430 to the result of the shift. OUTER_CONST is the relevant constant,
10431 but we must turn off all bits turned off in the shift. */
10433 if (outer_op == UNKNOWN
10434 && orig_code == code && orig_count == count
10435 && varop == orig_varop
10436 && shift_mode == GET_MODE (varop))
10439 /* Make a SUBREG if necessary. If we can't make it, fail. */
10440 varop = gen_lowpart (shift_mode, varop);
10441 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
10444 /* If we have an outer operation and we just made a shift, it is
10445 possible that we could have simplified the shift were it not
10446 for the outer operation. So try to do the simplification
10449 if (outer_op != UNKNOWN)
10450 x = simplify_shift_const_1 (code, shift_mode, varop, count);
10455 x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
10457 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10458 turn off all the bits that the shift would have turned off. */
10459 if (orig_code == LSHIFTRT && result_mode != shift_mode)
10460 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
10461 GET_MODE_MASK (result_mode) >> orig_count);
10463 /* Do the remainder of the processing in RESULT_MODE. */
10464 x = gen_lowpart_or_truncate (result_mode, x);
10466 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10469 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
10471 if (outer_op != UNKNOWN)
10473 if (GET_RTX_CLASS (outer_op) != RTX_UNARY
10474 && GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
10475 outer_const = trunc_int_for_mode (outer_const, result_mode);
10477 if (outer_op == AND)
10478 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
10479 else if (outer_op == SET)
10481 /* This means that we have determined that the result is
10482 equivalent to a constant. This should be rare. */
10483 if (!side_effects_p (x))
10484 x = GEN_INT (outer_const);
10486 else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
10487 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
10489 x = simplify_gen_binary (outer_op, result_mode, x,
10490 GEN_INT (outer_const));
10496 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10497 The result of the shift is RESULT_MODE. If we cannot simplify it,
10498 return X or, if it is NULL, synthesize the expression with
10499 simplify_gen_binary. Otherwise, return a simplified value.
10501 The shift is normally computed in the widest mode we find in VAROP, as
10502 long as it isn't a different number of words than RESULT_MODE. Exceptions
10503 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10506 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
10507 rtx varop, int count)
10509 rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
10514 x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
10515 if (GET_MODE (x) != result_mode)
10516 x = gen_lowpart (result_mode, x);
10521 /* Like recog, but we receive the address of a pointer to a new pattern.
10522 We try to match the rtx that the pointer points to.
10523 If that fails, we may try to modify or replace the pattern,
10524 storing the replacement into the same pointer object.
10526 Modifications include deletion or addition of CLOBBERs.
10528 PNOTES is a pointer to a location where any REG_UNUSED notes added for
10529 the CLOBBERs are placed.
10531 The value is the final insn code from the pattern ultimately matched,
10535 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
10537 rtx pat = *pnewpat;
10538 int insn_code_number;
10539 int num_clobbers_to_add = 0;
10542 rtx old_notes, old_pat;
10544 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10545 we use to indicate that something didn't match. If we find such a
10546 thing, force rejection. */
10547 if (GET_CODE (pat) == PARALLEL)
10548 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
10549 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
10550 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
10553 old_pat = PATTERN (insn);
10554 old_notes = REG_NOTES (insn);
10555 PATTERN (insn) = pat;
10556 REG_NOTES (insn) = 0;
10558 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10559 if (dump_file && (dump_flags & TDF_DETAILS))
10561 if (insn_code_number < 0)
10562 fputs ("Failed to match this instruction:\n", dump_file);
10564 fputs ("Successfully matched this instruction:\n", dump_file);
10565 print_rtl_single (dump_file, pat);
10568 /* If it isn't, there is the possibility that we previously had an insn
10569 that clobbered some register as a side effect, but the combined
10570 insn doesn't need to do that. So try once more without the clobbers
10571 unless this represents an ASM insn. */
10573 if (insn_code_number < 0 && ! check_asm_operands (pat)
10574 && GET_CODE (pat) == PARALLEL)
10578 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
10579 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
10582 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
10586 SUBST_INT (XVECLEN (pat, 0), pos);
10589 pat = XVECEXP (pat, 0, 0);
10591 PATTERN (insn) = pat;
10592 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10593 if (dump_file && (dump_flags & TDF_DETAILS))
10595 if (insn_code_number < 0)
10596 fputs ("Failed to match this instruction:\n", dump_file);
10598 fputs ("Successfully matched this instruction:\n", dump_file);
10599 print_rtl_single (dump_file, pat);
10602 PATTERN (insn) = old_pat;
10603 REG_NOTES (insn) = old_notes;
10605 /* Recognize all noop sets, these will be killed by followup pass. */
10606 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
10607 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
10609 /* If we had any clobbers to add, make a new pattern than contains
10610 them. Then check to make sure that all of them are dead. */
10611 if (num_clobbers_to_add)
10613 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
10614 rtvec_alloc (GET_CODE (pat) == PARALLEL
10615 ? (XVECLEN (pat, 0)
10616 + num_clobbers_to_add)
10617 : num_clobbers_to_add + 1));
10619 if (GET_CODE (pat) == PARALLEL)
10620 for (i = 0; i < XVECLEN (pat, 0); i++)
10621 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
10623 XVECEXP (newpat, 0, 0) = pat;
10625 add_clobbers (newpat, insn_code_number);
10627 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
10628 i < XVECLEN (newpat, 0); i++)
10630 if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
10631 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
10633 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH)
10635 gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)));
10636 notes = alloc_reg_note (REG_UNUSED,
10637 XEXP (XVECEXP (newpat, 0, i), 0), notes);
10646 return insn_code_number;
10649 /* Like gen_lowpart_general but for use by combine. In combine it
10650 is not possible to create any new pseudoregs. However, it is
10651 safe to create invalid memory addresses, because combine will
10652 try to recognize them and all they will do is make the combine
10655 If for some reason this cannot do its job, an rtx
10656 (clobber (const_int 0)) is returned.
10657 An insn containing that will not be recognized. */
10660 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
10662 enum machine_mode imode = GET_MODE (x);
10663 unsigned int osize = GET_MODE_SIZE (omode);
10664 unsigned int isize = GET_MODE_SIZE (imode);
10667 if (omode == imode)
10670 /* Return identity if this is a CONST or symbolic reference. */
10672 && (GET_CODE (x) == CONST
10673 || GET_CODE (x) == SYMBOL_REF
10674 || GET_CODE (x) == LABEL_REF))
10677 /* We can only support MODE being wider than a word if X is a
10678 constant integer or has a mode the same size. */
10679 if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
10680 && ! ((imode == VOIDmode
10681 && (CONST_INT_P (x)
10682 || GET_CODE (x) == CONST_DOUBLE))
10683 || isize == osize))
10686 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10687 won't know what to do. So we will strip off the SUBREG here and
10688 process normally. */
10689 if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
10691 x = SUBREG_REG (x);
10693 /* For use in case we fall down into the address adjustments
10694 further below, we need to adjust the known mode and size of
10695 x; imode and isize, since we just adjusted x. */
10696 imode = GET_MODE (x);
10698 if (imode == omode)
10701 isize = GET_MODE_SIZE (imode);
10704 result = gen_lowpart_common (omode, x);
10713 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10715 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
10718 /* If we want to refer to something bigger than the original memref,
10719 generate a paradoxical subreg instead. That will force a reload
10720 of the original memref X. */
10722 return gen_rtx_SUBREG (omode, x, 0);
10724 if (WORDS_BIG_ENDIAN)
10725 offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
10727 /* Adjust the address so that the address-after-the-data is
10729 if (BYTES_BIG_ENDIAN)
10730 offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
10732 return adjust_address_nv (x, omode, offset);
10735 /* If X is a comparison operator, rewrite it in a new mode. This
10736 probably won't match, but may allow further simplifications. */
10737 else if (COMPARISON_P (x))
10738 return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
10740 /* If we couldn't simplify X any other way, just enclose it in a
10741 SUBREG. Normally, this SUBREG won't match, but some patterns may
10742 include an explicit SUBREG or we may simplify it further in combine. */
10748 offset = subreg_lowpart_offset (omode, imode);
10749 if (imode == VOIDmode)
10751 imode = int_mode_for_mode (omode);
10752 x = gen_lowpart_common (imode, x);
10756 res = simplify_gen_subreg (omode, x, imode, offset);
10762 return gen_rtx_CLOBBER (omode, const0_rtx);
10765 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10766 comparison code that will be tested.
10768 The result is a possibly different comparison code to use. *POP0 and
10769 *POP1 may be updated.
10771 It is possible that we might detect that a comparison is either always
10772 true or always false. However, we do not perform general constant
10773 folding in combine, so this knowledge isn't useful. Such tautologies
10774 should have been detected earlier. Hence we ignore all such cases. */
10776 static enum rtx_code
10777 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
10783 enum machine_mode mode, tmode;
10785 /* Try a few ways of applying the same transformation to both operands. */
10788 #ifndef WORD_REGISTER_OPERATIONS
10789 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10790 so check specially. */
10791 if (code != GTU && code != GEU && code != LTU && code != LEU
10792 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
10793 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10794 && GET_CODE (XEXP (op1, 0)) == ASHIFT
10795 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
10796 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
10797 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
10798 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
10799 && CONST_INT_P (XEXP (op0, 1))
10800 && XEXP (op0, 1) == XEXP (op1, 1)
10801 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10802 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
10803 && (INTVAL (XEXP (op0, 1))
10804 == (GET_MODE_BITSIZE (GET_MODE (op0))
10805 - (GET_MODE_BITSIZE
10806 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
10808 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
10809 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
10813 /* If both operands are the same constant shift, see if we can ignore the
10814 shift. We can if the shift is a rotate or if the bits shifted out of
10815 this shift are known to be zero for both inputs and if the type of
10816 comparison is compatible with the shift. */
10817 if (GET_CODE (op0) == GET_CODE (op1)
10818 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10819 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
10820 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
10821 && (code != GT && code != LT && code != GE && code != LE))
10822 || (GET_CODE (op0) == ASHIFTRT
10823 && (code != GTU && code != LTU
10824 && code != GEU && code != LEU)))
10825 && CONST_INT_P (XEXP (op0, 1))
10826 && INTVAL (XEXP (op0, 1)) >= 0
10827 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10828 && XEXP (op0, 1) == XEXP (op1, 1))
10830 enum machine_mode mode = GET_MODE (op0);
10831 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10832 int shift_count = INTVAL (XEXP (op0, 1));
10834 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
10835 mask &= (mask >> shift_count) << shift_count;
10836 else if (GET_CODE (op0) == ASHIFT)
10837 mask = (mask & (mask << shift_count)) >> shift_count;
10839 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
10840 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
10841 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
10846 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10847 SUBREGs are of the same mode, and, in both cases, the AND would
10848 be redundant if the comparison was done in the narrower mode,
10849 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10850 and the operand's possibly nonzero bits are 0xffffff01; in that case
10851 if we only care about QImode, we don't need the AND). This case
10852 occurs if the output mode of an scc insn is not SImode and
10853 STORE_FLAG_VALUE == 1 (e.g., the 386).
10855 Similarly, check for a case where the AND's are ZERO_EXTEND
10856 operations from some narrower mode even though a SUBREG is not
10859 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
10860 && CONST_INT_P (XEXP (op0, 1))
10861 && CONST_INT_P (XEXP (op1, 1)))
10863 rtx inner_op0 = XEXP (op0, 0);
10864 rtx inner_op1 = XEXP (op1, 0);
10865 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
10866 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
10869 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
10870 && (GET_MODE_SIZE (GET_MODE (inner_op0))
10871 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
10872 && (GET_MODE (SUBREG_REG (inner_op0))
10873 == GET_MODE (SUBREG_REG (inner_op1)))
10874 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
10875 <= HOST_BITS_PER_WIDE_INT)
10876 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
10877 GET_MODE (SUBREG_REG (inner_op0)))))
10878 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
10879 GET_MODE (SUBREG_REG (inner_op1))))))
10881 op0 = SUBREG_REG (inner_op0);
10882 op1 = SUBREG_REG (inner_op1);
10884 /* The resulting comparison is always unsigned since we masked
10885 off the original sign bit. */
10886 code = unsigned_condition (code);
10892 for (tmode = GET_CLASS_NARROWEST_MODE
10893 (GET_MODE_CLASS (GET_MODE (op0)));
10894 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
10895 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
10897 op0 = gen_lowpart (tmode, inner_op0);
10898 op1 = gen_lowpart (tmode, inner_op1);
10899 code = unsigned_condition (code);
10908 /* If both operands are NOT, we can strip off the outer operation
10909 and adjust the comparison code for swapped operands; similarly for
10910 NEG, except that this must be an equality comparison. */
10911 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
10912 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
10913 && (code == EQ || code == NE)))
10914 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
10920 /* If the first operand is a constant, swap the operands and adjust the
10921 comparison code appropriately, but don't do this if the second operand
10922 is already a constant integer. */
10923 if (swap_commutative_operands_p (op0, op1))
10925 tem = op0, op0 = op1, op1 = tem;
10926 code = swap_condition (code);
10929 /* We now enter a loop during which we will try to simplify the comparison.
10930 For the most part, we only are concerned with comparisons with zero,
10931 but some things may really be comparisons with zero but not start
10932 out looking that way. */
10934 while (CONST_INT_P (op1))
10936 enum machine_mode mode = GET_MODE (op0);
10937 unsigned int mode_width = GET_MODE_BITSIZE (mode);
10938 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10939 int equality_comparison_p;
10940 int sign_bit_comparison_p;
10941 int unsigned_comparison_p;
10942 HOST_WIDE_INT const_op;
10944 /* We only want to handle integral modes. This catches VOIDmode,
10945 CCmode, and the floating-point modes. An exception is that we
10946 can handle VOIDmode if OP0 is a COMPARE or a comparison
10949 if (GET_MODE_CLASS (mode) != MODE_INT
10950 && ! (mode == VOIDmode
10951 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
10954 /* Get the constant we are comparing against and turn off all bits
10955 not on in our mode. */
10956 const_op = INTVAL (op1);
10957 if (mode != VOIDmode)
10958 const_op = trunc_int_for_mode (const_op, mode);
10959 op1 = GEN_INT (const_op);
10961 /* If we are comparing against a constant power of two and the value
10962 being compared can only have that single bit nonzero (e.g., it was
10963 `and'ed with that bit), we can replace this with a comparison
10966 && (code == EQ || code == NE || code == GE || code == GEU
10967 || code == LT || code == LTU)
10968 && mode_width <= HOST_BITS_PER_WIDE_INT
10969 && exact_log2 (const_op) >= 0
10970 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10972 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10973 op1 = const0_rtx, const_op = 0;
10976 /* Similarly, if we are comparing a value known to be either -1 or
10977 0 with -1, change it to the opposite comparison against zero. */
10980 && (code == EQ || code == NE || code == GT || code == LE
10981 || code == GEU || code == LTU)
10982 && num_sign_bit_copies (op0, mode) == mode_width)
10984 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10985 op1 = const0_rtx, const_op = 0;
10988 /* Do some canonicalizations based on the comparison code. We prefer
10989 comparisons against zero and then prefer equality comparisons.
10990 If we can reduce the size of a constant, we will do that too. */
10995 /* < C is equivalent to <= (C - 1) */
10999 op1 = GEN_INT (const_op);
11001 /* ... fall through to LE case below. */
11007 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11011 op1 = GEN_INT (const_op);
11015 /* If we are doing a <= 0 comparison on a value known to have
11016 a zero sign bit, we can replace this with == 0. */
11017 else if (const_op == 0
11018 && mode_width <= HOST_BITS_PER_WIDE_INT
11019 && (nonzero_bits (op0, mode)
11020 & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11026 /* >= C is equivalent to > (C - 1). */
11030 op1 = GEN_INT (const_op);
11032 /* ... fall through to GT below. */
11038 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11042 op1 = GEN_INT (const_op);
11046 /* If we are doing a > 0 comparison on a value known to have
11047 a zero sign bit, we can replace this with != 0. */
11048 else if (const_op == 0
11049 && mode_width <= HOST_BITS_PER_WIDE_INT
11050 && (nonzero_bits (op0, mode)
11051 & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11057 /* < C is equivalent to <= (C - 1). */
11061 op1 = GEN_INT (const_op);
11063 /* ... fall through ... */
11066 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11067 else if (mode_width <= HOST_BITS_PER_WIDE_INT
11068 && (unsigned HOST_WIDE_INT) const_op
11069 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1))
11071 const_op = 0, op1 = const0_rtx;
11079 /* unsigned <= 0 is equivalent to == 0 */
11083 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11084 else if (mode_width <= HOST_BITS_PER_WIDE_INT
11085 && (unsigned HOST_WIDE_INT) const_op
11086 == ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
11088 const_op = 0, op1 = const0_rtx;
11094 /* >= C is equivalent to > (C - 1). */
11098 op1 = GEN_INT (const_op);
11100 /* ... fall through ... */
11103 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11104 else if (mode_width <= HOST_BITS_PER_WIDE_INT
11105 && (unsigned HOST_WIDE_INT) const_op
11106 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1))
11108 const_op = 0, op1 = const0_rtx;
11116 /* unsigned > 0 is equivalent to != 0 */
11120 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11121 else if (mode_width <= HOST_BITS_PER_WIDE_INT
11122 && (unsigned HOST_WIDE_INT) const_op
11123 == ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
11125 const_op = 0, op1 = const0_rtx;
11134 /* Compute some predicates to simplify code below. */
11136 equality_comparison_p = (code == EQ || code == NE);
11137 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
11138 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
11141 /* If this is a sign bit comparison and we can do arithmetic in
11142 MODE, say that we will only be needing the sign bit of OP0. */
11143 if (sign_bit_comparison_p
11144 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11145 op0 = force_to_mode (op0, mode,
11146 (unsigned HOST_WIDE_INT) 1
11147 << (GET_MODE_BITSIZE (mode) - 1),
11150 /* Now try cases based on the opcode of OP0. If none of the cases
11151 does a "continue", we exit this loop immediately after the
11154 switch (GET_CODE (op0))
11157 /* If we are extracting a single bit from a variable position in
11158 a constant that has only a single bit set and are comparing it
11159 with zero, we can convert this into an equality comparison
11160 between the position and the location of the single bit. */
11161 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11162 have already reduced the shift count modulo the word size. */
11163 if (!SHIFT_COUNT_TRUNCATED
11164 && CONST_INT_P (XEXP (op0, 0))
11165 && XEXP (op0, 1) == const1_rtx
11166 && equality_comparison_p && const_op == 0
11167 && (i = exact_log2 (UINTVAL (XEXP (op0, 0)))) >= 0)
11169 if (BITS_BIG_ENDIAN)
11171 enum machine_mode new_mode
11172 = mode_for_extraction (EP_extzv, 1);
11173 if (new_mode == MAX_MACHINE_MODE)
11174 i = BITS_PER_WORD - 1 - i;
11178 i = (GET_MODE_BITSIZE (mode) - 1 - i);
11182 op0 = XEXP (op0, 2);
11186 /* Result is nonzero iff shift count is equal to I. */
11187 code = reverse_condition (code);
11191 /* ... fall through ... */
11194 tem = expand_compound_operation (op0);
11203 /* If testing for equality, we can take the NOT of the constant. */
11204 if (equality_comparison_p
11205 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
11207 op0 = XEXP (op0, 0);
11212 /* If just looking at the sign bit, reverse the sense of the
11214 if (sign_bit_comparison_p)
11216 op0 = XEXP (op0, 0);
11217 code = (code == GE ? LT : GE);
11223 /* If testing for equality, we can take the NEG of the constant. */
11224 if (equality_comparison_p
11225 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
11227 op0 = XEXP (op0, 0);
11232 /* The remaining cases only apply to comparisons with zero. */
11236 /* When X is ABS or is known positive,
11237 (neg X) is < 0 if and only if X != 0. */
11239 if (sign_bit_comparison_p
11240 && (GET_CODE (XEXP (op0, 0)) == ABS
11241 || (mode_width <= HOST_BITS_PER_WIDE_INT
11242 && (nonzero_bits (XEXP (op0, 0), mode)
11243 & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11246 op0 = XEXP (op0, 0);
11247 code = (code == LT ? NE : EQ);
11251 /* If we have NEG of something whose two high-order bits are the
11252 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11253 if (num_sign_bit_copies (op0, mode) >= 2)
11255 op0 = XEXP (op0, 0);
11256 code = swap_condition (code);
11262 /* If we are testing equality and our count is a constant, we
11263 can perform the inverse operation on our RHS. */
11264 if (equality_comparison_p && CONST_INT_P (XEXP (op0, 1))
11265 && (tem = simplify_binary_operation (ROTATERT, mode,
11266 op1, XEXP (op0, 1))) != 0)
11268 op0 = XEXP (op0, 0);
11273 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11274 a particular bit. Convert it to an AND of a constant of that
11275 bit. This will be converted into a ZERO_EXTRACT. */
11276 if (const_op == 0 && sign_bit_comparison_p
11277 && CONST_INT_P (XEXP (op0, 1))
11278 && mode_width <= HOST_BITS_PER_WIDE_INT)
11280 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11281 ((unsigned HOST_WIDE_INT) 1
11283 - INTVAL (XEXP (op0, 1)))));
11284 code = (code == LT ? NE : EQ);
11288 /* Fall through. */
11291 /* ABS is ignorable inside an equality comparison with zero. */
11292 if (const_op == 0 && equality_comparison_p)
11294 op0 = XEXP (op0, 0);
11300 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11301 (compare FOO CONST) if CONST fits in FOO's mode and we
11302 are either testing inequality or have an unsigned
11303 comparison with ZERO_EXTEND or a signed comparison with
11304 SIGN_EXTEND. But don't do it if we don't have a compare
11305 insn of the given mode, since we'd have to revert it
11306 later on, and then we wouldn't know whether to sign- or
11308 mode = GET_MODE (XEXP (op0, 0));
11309 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11310 && ! unsigned_comparison_p
11311 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11312 && ((unsigned HOST_WIDE_INT) const_op
11313 < (((unsigned HOST_WIDE_INT) 1
11314 << (GET_MODE_BITSIZE (mode) - 1))))
11315 && have_insn_for (COMPARE, mode))
11317 op0 = XEXP (op0, 0);
11323 /* Check for the case where we are comparing A - C1 with C2, that is
11325 (subreg:MODE (plus (A) (-C1))) op (C2)
11327 with C1 a constant, and try to lift the SUBREG, i.e. to do the
11328 comparison in the wider mode. One of the following two conditions
11329 must be true in order for this to be valid:
11331 1. The mode extension results in the same bit pattern being added
11332 on both sides and the comparison is equality or unsigned. As
11333 C2 has been truncated to fit in MODE, the pattern can only be
11336 2. The mode extension results in the sign bit being copied on
11339 The difficulty here is that we have predicates for A but not for
11340 (A - C1) so we need to check that C1 is within proper bounds so
11341 as to perturbate A as little as possible. */
11343 if (mode_width <= HOST_BITS_PER_WIDE_INT
11344 && subreg_lowpart_p (op0)
11345 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) > mode_width
11346 && GET_CODE (SUBREG_REG (op0)) == PLUS
11347 && CONST_INT_P (XEXP (SUBREG_REG (op0), 1)))
11349 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
11350 rtx a = XEXP (SUBREG_REG (op0), 0);
11351 HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
11354 && (unsigned HOST_WIDE_INT) c1
11355 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
11356 && (equality_comparison_p || unsigned_comparison_p)
11357 /* (A - C1) zero-extends if it is positive and sign-extends
11358 if it is negative, C2 both zero- and sign-extends. */
11359 && ((0 == (nonzero_bits (a, inner_mode)
11360 & ~GET_MODE_MASK (mode))
11362 /* (A - C1) sign-extends if it is positive and 1-extends
11363 if it is negative, C2 both sign- and 1-extends. */
11364 || (num_sign_bit_copies (a, inner_mode)
11365 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
11368 || ((unsigned HOST_WIDE_INT) c1
11369 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
11370 /* (A - C1) always sign-extends, like C2. */
11371 && num_sign_bit_copies (a, inner_mode)
11372 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
11373 - (mode_width - 1))))
11375 op0 = SUBREG_REG (op0);
11380 /* If the inner mode is narrower and we are extracting the low part,
11381 we can treat the SUBREG as if it were a ZERO_EXTEND. */
11382 if (subreg_lowpart_p (op0)
11383 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
11384 /* Fall through */ ;
11388 /* ... fall through ... */
11391 mode = GET_MODE (XEXP (op0, 0));
11392 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11393 && (unsigned_comparison_p || equality_comparison_p)
11394 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11395 && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode))
11396 && have_insn_for (COMPARE, mode))
11398 op0 = XEXP (op0, 0);
11404 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
11405 this for equality comparisons due to pathological cases involving
11407 if (equality_comparison_p
11408 && 0 != (tem = simplify_binary_operation (MINUS, mode,
11409 op1, XEXP (op0, 1))))
11411 op0 = XEXP (op0, 0);
11416 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
11417 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
11418 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
11420 op0 = XEXP (XEXP (op0, 0), 0);
11421 code = (code == LT ? EQ : NE);
11427 /* We used to optimize signed comparisons against zero, but that
11428 was incorrect. Unsigned comparisons against zero (GTU, LEU)
11429 arrive here as equality comparisons, or (GEU, LTU) are
11430 optimized away. No need to special-case them. */
11432 /* (eq (minus A B) C) -> (eq A (plus B C)) or
11433 (eq B (minus A C)), whichever simplifies. We can only do
11434 this for equality comparisons due to pathological cases involving
11436 if (equality_comparison_p
11437 && 0 != (tem = simplify_binary_operation (PLUS, mode,
11438 XEXP (op0, 1), op1)))
11440 op0 = XEXP (op0, 0);
11445 if (equality_comparison_p
11446 && 0 != (tem = simplify_binary_operation (MINUS, mode,
11447 XEXP (op0, 0), op1)))
11449 op0 = XEXP (op0, 1);
11454 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11455 of bits in X minus 1, is one iff X > 0. */
11456 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
11457 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11458 && UINTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
11459 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11461 op0 = XEXP (op0, 1);
11462 code = (code == GE ? LE : GT);
11468 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11469 if C is zero or B is a constant. */
11470 if (equality_comparison_p
11471 && 0 != (tem = simplify_binary_operation (XOR, mode,
11472 XEXP (op0, 1), op1)))
11474 op0 = XEXP (op0, 0);
11481 case UNEQ: case LTGT:
11482 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
11483 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
11484 case UNORDERED: case ORDERED:
11485 /* We can't do anything if OP0 is a condition code value, rather
11486 than an actual data value. */
11488 || CC0_P (XEXP (op0, 0))
11489 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
11492 /* Get the two operands being compared. */
11493 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
11494 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
11496 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
11498 /* Check for the cases where we simply want the result of the
11499 earlier test or the opposite of that result. */
11500 if (code == NE || code == EQ
11501 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
11502 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11503 && (STORE_FLAG_VALUE
11504 & (((unsigned HOST_WIDE_INT) 1
11505 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
11506 && (code == LT || code == GE)))
11508 enum rtx_code new_code;
11509 if (code == LT || code == NE)
11510 new_code = GET_CODE (op0);
11512 new_code = reversed_comparison_code (op0, NULL);
11514 if (new_code != UNKNOWN)
11525 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11527 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
11528 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
11529 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11531 op0 = XEXP (op0, 1);
11532 code = (code == GE ? GT : LE);
11538 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11539 will be converted to a ZERO_EXTRACT later. */
11540 if (const_op == 0 && equality_comparison_p
11541 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11542 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
11544 op0 = gen_rtx_LSHIFTRT (mode, XEXP (op0, 1),
11545 XEXP (XEXP (op0, 0), 1));
11546 op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
11550 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11551 zero and X is a comparison and C1 and C2 describe only bits set
11552 in STORE_FLAG_VALUE, we can compare with X. */
11553 if (const_op == 0 && equality_comparison_p
11554 && mode_width <= HOST_BITS_PER_WIDE_INT
11555 && CONST_INT_P (XEXP (op0, 1))
11556 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
11557 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11558 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
11559 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
11561 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11562 << INTVAL (XEXP (XEXP (op0, 0), 1)));
11563 if ((~STORE_FLAG_VALUE & mask) == 0
11564 && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
11565 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
11566 && COMPARISON_P (tem))))
11568 op0 = XEXP (XEXP (op0, 0), 0);
11573 /* If we are doing an equality comparison of an AND of a bit equal
11574 to the sign bit, replace this with a LT or GE comparison of
11575 the underlying value. */
11576 if (equality_comparison_p
11578 && CONST_INT_P (XEXP (op0, 1))
11579 && mode_width <= HOST_BITS_PER_WIDE_INT
11580 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11581 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11583 op0 = XEXP (op0, 0);
11584 code = (code == EQ ? GE : LT);
11588 /* If this AND operation is really a ZERO_EXTEND from a narrower
11589 mode, the constant fits within that mode, and this is either an
11590 equality or unsigned comparison, try to do this comparison in
11595 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11596 -> (ne:DI (reg:SI 4) (const_int 0))
11598 unless TRULY_NOOP_TRUNCATION allows it or the register is
11599 known to hold a value of the required mode the
11600 transformation is invalid. */
11601 if ((equality_comparison_p || unsigned_comparison_p)
11602 && CONST_INT_P (XEXP (op0, 1))
11603 && (i = exact_log2 ((UINTVAL (XEXP (op0, 1))
11604 & GET_MODE_MASK (mode))
11606 && const_op >> i == 0
11607 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode
11608 && (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
11609 GET_MODE_BITSIZE (GET_MODE (op0)))
11610 || (REG_P (XEXP (op0, 0))
11611 && reg_truncated_to_mode (tmode, XEXP (op0, 0)))))
11613 op0 = gen_lowpart (tmode, XEXP (op0, 0));
11617 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11618 fits in both M1 and M2 and the SUBREG is either paradoxical
11619 or represents the low part, permute the SUBREG and the AND
11621 if (GET_CODE (XEXP (op0, 0)) == SUBREG)
11623 unsigned HOST_WIDE_INT c1;
11624 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
11625 /* Require an integral mode, to avoid creating something like
11627 if (SCALAR_INT_MODE_P (tmode)
11628 /* It is unsafe to commute the AND into the SUBREG if the
11629 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11630 not defined. As originally written the upper bits
11631 have a defined value due to the AND operation.
11632 However, if we commute the AND inside the SUBREG then
11633 they no longer have defined values and the meaning of
11634 the code has been changed. */
11636 #ifdef WORD_REGISTER_OPERATIONS
11637 || (mode_width > GET_MODE_BITSIZE (tmode)
11638 && mode_width <= BITS_PER_WORD)
11640 || (mode_width <= GET_MODE_BITSIZE (tmode)
11641 && subreg_lowpart_p (XEXP (op0, 0))))
11642 && CONST_INT_P (XEXP (op0, 1))
11643 && mode_width <= HOST_BITS_PER_WIDE_INT
11644 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
11645 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
11646 && (c1 & ~GET_MODE_MASK (tmode)) == 0
11648 && c1 != GET_MODE_MASK (tmode))
11650 op0 = simplify_gen_binary (AND, tmode,
11651 SUBREG_REG (XEXP (op0, 0)),
11652 gen_int_mode (c1, tmode));
11653 op0 = gen_lowpart (mode, op0);
11658 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
11659 if (const_op == 0 && equality_comparison_p
11660 && XEXP (op0, 1) == const1_rtx
11661 && GET_CODE (XEXP (op0, 0)) == NOT)
11663 op0 = simplify_and_const_int (NULL_RTX, mode,
11664 XEXP (XEXP (op0, 0), 0), 1);
11665 code = (code == NE ? EQ : NE);
11669 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11670 (eq (and (lshiftrt X) 1) 0).
11671 Also handle the case where (not X) is expressed using xor. */
11672 if (const_op == 0 && equality_comparison_p
11673 && XEXP (op0, 1) == const1_rtx
11674 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
11676 rtx shift_op = XEXP (XEXP (op0, 0), 0);
11677 rtx shift_count = XEXP (XEXP (op0, 0), 1);
11679 if (GET_CODE (shift_op) == NOT
11680 || (GET_CODE (shift_op) == XOR
11681 && CONST_INT_P (XEXP (shift_op, 1))
11682 && CONST_INT_P (shift_count)
11683 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
11684 && (UINTVAL (XEXP (shift_op, 1))
11685 == (unsigned HOST_WIDE_INT) 1
11686 << INTVAL (shift_count))))
11689 = gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count);
11690 op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
11691 code = (code == NE ? EQ : NE);
11698 /* If we have (compare (ashift FOO N) (const_int C)) and
11699 the high order N bits of FOO (N+1 if an inequality comparison)
11700 are known to be zero, we can do this by comparing FOO with C
11701 shifted right N bits so long as the low-order N bits of C are
11703 if (CONST_INT_P (XEXP (op0, 1))
11704 && INTVAL (XEXP (op0, 1)) >= 0
11705 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
11706 < HOST_BITS_PER_WIDE_INT)
11707 && (((unsigned HOST_WIDE_INT) const_op
11708 & (((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1)))
11710 && mode_width <= HOST_BITS_PER_WIDE_INT
11711 && (nonzero_bits (XEXP (op0, 0), mode)
11712 & ~(mask >> (INTVAL (XEXP (op0, 1))
11713 + ! equality_comparison_p))) == 0)
11715 /* We must perform a logical shift, not an arithmetic one,
11716 as we want the top N bits of C to be zero. */
11717 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
11719 temp >>= INTVAL (XEXP (op0, 1));
11720 op1 = gen_int_mode (temp, mode);
11721 op0 = XEXP (op0, 0);
11725 /* If we are doing a sign bit comparison, it means we are testing
11726 a particular bit. Convert it to the appropriate AND. */
11727 if (sign_bit_comparison_p && CONST_INT_P (XEXP (op0, 1))
11728 && mode_width <= HOST_BITS_PER_WIDE_INT)
11730 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11731 ((unsigned HOST_WIDE_INT) 1
11733 - INTVAL (XEXP (op0, 1)))));
11734 code = (code == LT ? NE : EQ);
11738 /* If this an equality comparison with zero and we are shifting
11739 the low bit to the sign bit, we can convert this to an AND of the
11741 if (const_op == 0 && equality_comparison_p
11742 && CONST_INT_P (XEXP (op0, 1))
11743 && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
11745 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), 1);
11751 /* If this is an equality comparison with zero, we can do this
11752 as a logical shift, which might be much simpler. */
11753 if (equality_comparison_p && const_op == 0
11754 && CONST_INT_P (XEXP (op0, 1)))
11756 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
11758 INTVAL (XEXP (op0, 1)));
11762 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11763 do the comparison in a narrower mode. */
11764 if (! unsigned_comparison_p
11765 && CONST_INT_P (XEXP (op0, 1))
11766 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11767 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11768 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11769 MODE_INT, 1)) != BLKmode
11770 && (((unsigned HOST_WIDE_INT) const_op
11771 + (GET_MODE_MASK (tmode) >> 1) + 1)
11772 <= GET_MODE_MASK (tmode)))
11774 op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
11778 /* Likewise if OP0 is a PLUS of a sign extension with a
11779 constant, which is usually represented with the PLUS
11780 between the shifts. */
11781 if (! unsigned_comparison_p
11782 && CONST_INT_P (XEXP (op0, 1))
11783 && GET_CODE (XEXP (op0, 0)) == PLUS
11784 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11785 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
11786 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
11787 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11788 MODE_INT, 1)) != BLKmode
11789 && (((unsigned HOST_WIDE_INT) const_op
11790 + (GET_MODE_MASK (tmode) >> 1) + 1)
11791 <= GET_MODE_MASK (tmode)))
11793 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
11794 rtx add_const = XEXP (XEXP (op0, 0), 1);
11795 rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
11796 add_const, XEXP (op0, 1));
11798 op0 = simplify_gen_binary (PLUS, tmode,
11799 gen_lowpart (tmode, inner),
11804 /* ... fall through ... */
11806 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11807 the low order N bits of FOO are known to be zero, we can do this
11808 by comparing FOO with C shifted left N bits so long as no
11809 overflow occurs. Even if the low order N bits of FOO aren't known
11810 to be zero, if the comparison is >= or < we can use the same
11811 optimization and for > or <= by setting all the low
11812 order N bits in the comparison constant. */
11813 if (CONST_INT_P (XEXP (op0, 1))
11814 && INTVAL (XEXP (op0, 1)) > 0
11815 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11816 && mode_width <= HOST_BITS_PER_WIDE_INT
11817 && (((unsigned HOST_WIDE_INT) const_op
11818 + (GET_CODE (op0) != LSHIFTRT
11819 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
11822 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
11824 unsigned HOST_WIDE_INT low_bits
11825 = (nonzero_bits (XEXP (op0, 0), mode)
11826 & (((unsigned HOST_WIDE_INT) 1
11827 << INTVAL (XEXP (op0, 1))) - 1));
11828 if (low_bits == 0 || !equality_comparison_p)
11830 /* If the shift was logical, then we must make the condition
11832 if (GET_CODE (op0) == LSHIFTRT)
11833 code = unsigned_condition (code);
11835 const_op <<= INTVAL (XEXP (op0, 1));
11837 && (code == GT || code == GTU
11838 || code == LE || code == LEU))
11840 |= (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1);
11841 op1 = GEN_INT (const_op);
11842 op0 = XEXP (op0, 0);
11847 /* If we are using this shift to extract just the sign bit, we
11848 can replace this with an LT or GE comparison. */
11850 && (equality_comparison_p || sign_bit_comparison_p)
11851 && CONST_INT_P (XEXP (op0, 1))
11852 && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
11854 op0 = XEXP (op0, 0);
11855 code = (code == NE || code == GT ? LT : GE);
11867 /* Now make any compound operations involved in this comparison. Then,
11868 check for an outmost SUBREG on OP0 that is not doing anything or is
11869 paradoxical. The latter transformation must only be performed when
11870 it is known that the "extra" bits will be the same in op0 and op1 or
11871 that they don't matter. There are three cases to consider:
11873 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11874 care bits and we can assume they have any convenient value. So
11875 making the transformation is safe.
11877 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11878 In this case the upper bits of op0 are undefined. We should not make
11879 the simplification in that case as we do not know the contents of
11882 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11883 UNKNOWN. In that case we know those bits are zeros or ones. We must
11884 also be sure that they are the same as the upper bits of op1.
11886 We can never remove a SUBREG for a non-equality comparison because
11887 the sign bit is in a different place in the underlying object. */
11889 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
11890 op1 = make_compound_operation (op1, SET);
11892 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11893 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11894 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
11895 && (code == NE || code == EQ))
11897 if (GET_MODE_SIZE (GET_MODE (op0))
11898 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
11900 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11902 if (REG_P (SUBREG_REG (op0)))
11904 op0 = SUBREG_REG (op0);
11905 op1 = gen_lowpart (GET_MODE (op0), op1);
11908 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
11909 <= HOST_BITS_PER_WIDE_INT)
11910 && (nonzero_bits (SUBREG_REG (op0),
11911 GET_MODE (SUBREG_REG (op0)))
11912 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11914 tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
11916 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11917 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11918 op0 = SUBREG_REG (op0), op1 = tem;
11922 /* We now do the opposite procedure: Some machines don't have compare
11923 insns in all modes. If OP0's mode is an integer mode smaller than a
11924 word and we can't do a compare in that mode, see if there is a larger
11925 mode for which we can do the compare. There are a number of cases in
11926 which we can use the wider mode. */
11928 mode = GET_MODE (op0);
11929 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11930 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11931 && ! have_insn_for (COMPARE, mode))
11932 for (tmode = GET_MODE_WIDER_MODE (mode);
11934 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
11935 tmode = GET_MODE_WIDER_MODE (tmode))
11936 if (have_insn_for (COMPARE, tmode))
11940 /* If this is a test for negative, we can make an explicit
11941 test of the sign bit. Test this first so we can use
11942 a paradoxical subreg to extend OP0. */
11944 if (op1 == const0_rtx && (code == LT || code == GE)
11945 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11947 op0 = simplify_gen_binary (AND, tmode,
11948 gen_lowpart (tmode, op0),
11949 GEN_INT ((unsigned HOST_WIDE_INT) 1
11950 << (GET_MODE_BITSIZE (mode)
11952 code = (code == LT) ? NE : EQ;
11956 /* If the only nonzero bits in OP0 and OP1 are those in the
11957 narrower mode and this is an equality or unsigned comparison,
11958 we can use the wider mode. Similarly for sign-extended
11959 values, in which case it is true for all comparisons. */
11960 zero_extended = ((code == EQ || code == NE
11961 || code == GEU || code == GTU
11962 || code == LEU || code == LTU)
11963 && (nonzero_bits (op0, tmode)
11964 & ~GET_MODE_MASK (mode)) == 0
11965 && ((CONST_INT_P (op1)
11966 || (nonzero_bits (op1, tmode)
11967 & ~GET_MODE_MASK (mode)) == 0)));
11970 || ((num_sign_bit_copies (op0, tmode)
11971 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11972 - GET_MODE_BITSIZE (mode)))
11973 && (num_sign_bit_copies (op1, tmode)
11974 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11975 - GET_MODE_BITSIZE (mode)))))
11977 /* If OP0 is an AND and we don't have an AND in MODE either,
11978 make a new AND in the proper mode. */
11979 if (GET_CODE (op0) == AND
11980 && !have_insn_for (AND, mode))
11981 op0 = simplify_gen_binary (AND, tmode,
11982 gen_lowpart (tmode,
11984 gen_lowpart (tmode,
11990 op0 = simplify_gen_unary (ZERO_EXTEND, tmode, op0, mode);
11991 op1 = simplify_gen_unary (ZERO_EXTEND, tmode, op1, mode);
11995 op0 = simplify_gen_unary (SIGN_EXTEND, tmode, op0, mode);
11996 op1 = simplify_gen_unary (SIGN_EXTEND, tmode, op1, mode);
12003 #ifdef CANONICALIZE_COMPARISON
12004 /* If this machine only supports a subset of valid comparisons, see if we
12005 can convert an unsupported one into a supported one. */
12006 CANONICALIZE_COMPARISON (code, op0, op1);
12015 /* Utility function for record_value_for_reg. Count number of
12020 enum rtx_code code = GET_CODE (x);
12024 if (GET_RTX_CLASS (code) == '2'
12025 || GET_RTX_CLASS (code) == 'c')
12027 rtx x0 = XEXP (x, 0);
12028 rtx x1 = XEXP (x, 1);
12031 return 1 + 2 * count_rtxs (x0);
12033 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
12034 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
12035 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12036 return 2 + 2 * count_rtxs (x0)
12037 + count_rtxs (x == XEXP (x1, 0)
12038 ? XEXP (x1, 1) : XEXP (x1, 0));
12040 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
12041 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
12042 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12043 return 2 + 2 * count_rtxs (x1)
12044 + count_rtxs (x == XEXP (x0, 0)
12045 ? XEXP (x0, 1) : XEXP (x0, 0));
12048 fmt = GET_RTX_FORMAT (code);
12049 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12051 ret += count_rtxs (XEXP (x, i));
12052 else if (fmt[i] == 'E')
12053 for (j = 0; j < XVECLEN (x, i); j++)
12054 ret += count_rtxs (XVECEXP (x, i, j));
12059 /* Utility function for following routine. Called when X is part of a value
12060 being stored into last_set_value. Sets last_set_table_tick
12061 for each register mentioned. Similar to mention_regs in cse.c */
12064 update_table_tick (rtx x)
12066 enum rtx_code code = GET_CODE (x);
12067 const char *fmt = GET_RTX_FORMAT (code);
12072 unsigned int regno = REGNO (x);
12073 unsigned int endregno = END_REGNO (x);
12076 for (r = regno; r < endregno; r++)
12078 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, r);
12079 rsp->last_set_table_tick = label_tick;
12085 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12088 /* Check for identical subexpressions. If x contains
12089 identical subexpression we only have to traverse one of
12091 if (i == 0 && ARITHMETIC_P (x))
12093 /* Note that at this point x1 has already been
12095 rtx x0 = XEXP (x, 0);
12096 rtx x1 = XEXP (x, 1);
12098 /* If x0 and x1 are identical then there is no need to
12103 /* If x0 is identical to a subexpression of x1 then while
12104 processing x1, x0 has already been processed. Thus we
12105 are done with x. */
12106 if (ARITHMETIC_P (x1)
12107 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12110 /* If x1 is identical to a subexpression of x0 then we
12111 still have to process the rest of x0. */
12112 if (ARITHMETIC_P (x0)
12113 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12115 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
12120 update_table_tick (XEXP (x, i));
12122 else if (fmt[i] == 'E')
12123 for (j = 0; j < XVECLEN (x, i); j++)
12124 update_table_tick (XVECEXP (x, i, j));
12127 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12128 are saying that the register is clobbered and we no longer know its
12129 value. If INSN is zero, don't update reg_stat[].last_set; this is
12130 only permitted with VALUE also zero and is used to invalidate the
12134 record_value_for_reg (rtx reg, rtx insn, rtx value)
12136 unsigned int regno = REGNO (reg);
12137 unsigned int endregno = END_REGNO (reg);
12139 reg_stat_type *rsp;
12141 /* If VALUE contains REG and we have a previous value for REG, substitute
12142 the previous value. */
12143 if (value && insn && reg_overlap_mentioned_p (reg, value))
12147 /* Set things up so get_last_value is allowed to see anything set up to
12149 subst_low_luid = DF_INSN_LUID (insn);
12150 tem = get_last_value (reg);
12152 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12153 it isn't going to be useful and will take a lot of time to process,
12154 so just use the CLOBBER. */
12158 if (ARITHMETIC_P (tem)
12159 && GET_CODE (XEXP (tem, 0)) == CLOBBER
12160 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
12161 tem = XEXP (tem, 0);
12162 else if (count_occurrences (value, reg, 1) >= 2)
12164 /* If there are two or more occurrences of REG in VALUE,
12165 prevent the value from growing too much. */
12166 if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
12167 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
12170 value = replace_rtx (copy_rtx (value), reg, tem);
12174 /* For each register modified, show we don't know its value, that
12175 we don't know about its bitwise content, that its value has been
12176 updated, and that we don't know the location of the death of the
12178 for (i = regno; i < endregno; i++)
12180 rsp = VEC_index (reg_stat_type, reg_stat, i);
12183 rsp->last_set = insn;
12185 rsp->last_set_value = 0;
12186 rsp->last_set_mode = VOIDmode;
12187 rsp->last_set_nonzero_bits = 0;
12188 rsp->last_set_sign_bit_copies = 0;
12189 rsp->last_death = 0;
12190 rsp->truncated_to_mode = VOIDmode;
12193 /* Mark registers that are being referenced in this value. */
12195 update_table_tick (value);
12197 /* Now update the status of each register being set.
12198 If someone is using this register in this block, set this register
12199 to invalid since we will get confused between the two lives in this
12200 basic block. This makes using this register always invalid. In cse, we
12201 scan the table to invalidate all entries using this register, but this
12202 is too much work for us. */
12204 for (i = regno; i < endregno; i++)
12206 rsp = VEC_index (reg_stat_type, reg_stat, i);
12207 rsp->last_set_label = label_tick;
12209 || (value && rsp->last_set_table_tick >= label_tick_ebb_start))
12210 rsp->last_set_invalid = 1;
12212 rsp->last_set_invalid = 0;
12215 /* The value being assigned might refer to X (like in "x++;"). In that
12216 case, we must replace it with (clobber (const_int 0)) to prevent
12218 rsp = VEC_index (reg_stat_type, reg_stat, regno);
12219 if (value && !get_last_value_validate (&value, insn, label_tick, 0))
12221 value = copy_rtx (value);
12222 if (!get_last_value_validate (&value, insn, label_tick, 1))
12226 /* For the main register being modified, update the value, the mode, the
12227 nonzero bits, and the number of sign bit copies. */
12229 rsp->last_set_value = value;
12233 enum machine_mode mode = GET_MODE (reg);
12234 subst_low_luid = DF_INSN_LUID (insn);
12235 rsp->last_set_mode = mode;
12236 if (GET_MODE_CLASS (mode) == MODE_INT
12237 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
12238 mode = nonzero_bits_mode;
12239 rsp->last_set_nonzero_bits = nonzero_bits (value, mode);
12240 rsp->last_set_sign_bit_copies
12241 = num_sign_bit_copies (value, GET_MODE (reg));
12245 /* Called via note_stores from record_dead_and_set_regs to handle one
12246 SET or CLOBBER in an insn. DATA is the instruction in which the
12247 set is occurring. */
12250 record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
12252 rtx record_dead_insn = (rtx) data;
12254 if (GET_CODE (dest) == SUBREG)
12255 dest = SUBREG_REG (dest);
12257 if (!record_dead_insn)
12260 record_value_for_reg (dest, NULL_RTX, NULL_RTX);
12266 /* If we are setting the whole register, we know its value. Otherwise
12267 show that we don't know the value. We can handle SUBREG in
12269 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
12270 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
12271 else if (GET_CODE (setter) == SET
12272 && GET_CODE (SET_DEST (setter)) == SUBREG
12273 && SUBREG_REG (SET_DEST (setter)) == dest
12274 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
12275 && subreg_lowpart_p (SET_DEST (setter)))
12276 record_value_for_reg (dest, record_dead_insn,
12277 gen_lowpart (GET_MODE (dest),
12278 SET_SRC (setter)));
12280 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
12282 else if (MEM_P (dest)
12283 /* Ignore pushes, they clobber nothing. */
12284 && ! push_operand (dest, GET_MODE (dest)))
12285 mem_last_set = DF_INSN_LUID (record_dead_insn);
12288 /* Update the records of when each REG was most recently set or killed
12289 for the things done by INSN. This is the last thing done in processing
12290 INSN in the combiner loop.
12292 We update reg_stat[], in particular fields last_set, last_set_value,
12293 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12294 last_death, and also the similar information mem_last_set (which insn
12295 most recently modified memory) and last_call_luid (which insn was the
12296 most recent subroutine call). */
12299 record_dead_and_set_regs (rtx insn)
12304 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
12306 if (REG_NOTE_KIND (link) == REG_DEAD
12307 && REG_P (XEXP (link, 0)))
12309 unsigned int regno = REGNO (XEXP (link, 0));
12310 unsigned int endregno = END_REGNO (XEXP (link, 0));
12312 for (i = regno; i < endregno; i++)
12314 reg_stat_type *rsp;
12316 rsp = VEC_index (reg_stat_type, reg_stat, i);
12317 rsp->last_death = insn;
12320 else if (REG_NOTE_KIND (link) == REG_INC)
12321 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
12326 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
12327 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
12329 reg_stat_type *rsp;
12331 rsp = VEC_index (reg_stat_type, reg_stat, i);
12332 rsp->last_set_invalid = 1;
12333 rsp->last_set = insn;
12334 rsp->last_set_value = 0;
12335 rsp->last_set_mode = VOIDmode;
12336 rsp->last_set_nonzero_bits = 0;
12337 rsp->last_set_sign_bit_copies = 0;
12338 rsp->last_death = 0;
12339 rsp->truncated_to_mode = VOIDmode;
12342 last_call_luid = mem_last_set = DF_INSN_LUID (insn);
12344 /* We can't combine into a call pattern. Remember, though, that
12345 the return value register is set at this LUID. We could
12346 still replace a register with the return value from the
12347 wrong subroutine call! */
12348 note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
12351 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
12354 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12355 register present in the SUBREG, so for each such SUBREG go back and
12356 adjust nonzero and sign bit information of the registers that are
12357 known to have some zero/sign bits set.
12359 This is needed because when combine blows the SUBREGs away, the
12360 information on zero/sign bits is lost and further combines can be
12361 missed because of that. */
12364 record_promoted_value (rtx insn, rtx subreg)
12366 struct insn_link *links;
12368 unsigned int regno = REGNO (SUBREG_REG (subreg));
12369 enum machine_mode mode = GET_MODE (subreg);
12371 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
12374 for (links = LOG_LINKS (insn); links;)
12376 reg_stat_type *rsp;
12378 insn = links->insn;
12379 set = single_set (insn);
12381 if (! set || !REG_P (SET_DEST (set))
12382 || REGNO (SET_DEST (set)) != regno
12383 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
12385 links = links->next;
12389 rsp = VEC_index (reg_stat_type, reg_stat, regno);
12390 if (rsp->last_set == insn)
12392 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
12393 rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode);
12396 if (REG_P (SET_SRC (set)))
12398 regno = REGNO (SET_SRC (set));
12399 links = LOG_LINKS (insn);
12406 /* Check if X, a register, is known to contain a value already
12407 truncated to MODE. In this case we can use a subreg to refer to
12408 the truncated value even though in the generic case we would need
12409 an explicit truncation. */
12412 reg_truncated_to_mode (enum machine_mode mode, const_rtx x)
12414 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
12415 enum machine_mode truncated = rsp->truncated_to_mode;
12418 || rsp->truncation_label < label_tick_ebb_start)
12420 if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
12422 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
12423 GET_MODE_BITSIZE (truncated)))
12428 /* Callback for for_each_rtx. If *P is a hard reg or a subreg record the mode
12429 that the register is accessed in. For non-TRULY_NOOP_TRUNCATION targets we
12430 might be able to turn a truncate into a subreg using this information.
12431 Return -1 if traversing *P is complete or 0 otherwise. */
12434 record_truncated_value (rtx *p, void *data ATTRIBUTE_UNUSED)
12437 enum machine_mode truncated_mode;
12438 reg_stat_type *rsp;
12440 if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
12442 enum machine_mode original_mode = GET_MODE (SUBREG_REG (x));
12443 truncated_mode = GET_MODE (x);
12445 if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
12448 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (truncated_mode),
12449 GET_MODE_BITSIZE (original_mode)))
12452 x = SUBREG_REG (x);
12454 /* ??? For hard-regs we now record everything. We might be able to
12455 optimize this using last_set_mode. */
12456 else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
12457 truncated_mode = GET_MODE (x);
12461 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
12462 if (rsp->truncated_to_mode == 0
12463 || rsp->truncation_label < label_tick_ebb_start
12464 || (GET_MODE_SIZE (truncated_mode)
12465 < GET_MODE_SIZE (rsp->truncated_to_mode)))
12467 rsp->truncated_to_mode = truncated_mode;
12468 rsp->truncation_label = label_tick;
12474 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12475 the modes they are used in. This can help truning TRUNCATEs into
12479 record_truncated_values (rtx *x, void *data ATTRIBUTE_UNUSED)
12481 for_each_rtx (x, record_truncated_value, NULL);
12484 /* Scan X for promoted SUBREGs. For each one found,
12485 note what it implies to the registers used in it. */
12488 check_promoted_subreg (rtx insn, rtx x)
12490 if (GET_CODE (x) == SUBREG
12491 && SUBREG_PROMOTED_VAR_P (x)
12492 && REG_P (SUBREG_REG (x)))
12493 record_promoted_value (insn, x);
12496 const char *format = GET_RTX_FORMAT (GET_CODE (x));
12499 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
12503 check_promoted_subreg (insn, XEXP (x, i));
12507 if (XVEC (x, i) != 0)
12508 for (j = 0; j < XVECLEN (x, i); j++)
12509 check_promoted_subreg (insn, XVECEXP (x, i, j));
12515 /* Verify that all the registers and memory references mentioned in *LOC are
12516 still valid. *LOC was part of a value set in INSN when label_tick was
12517 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12518 the invalid references with (clobber (const_int 0)) and return 1. This
12519 replacement is useful because we often can get useful information about
12520 the form of a value (e.g., if it was produced by a shift that always
12521 produces -1 or 0) even though we don't know exactly what registers it
12522 was produced from. */
12525 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
12528 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
12529 int len = GET_RTX_LENGTH (GET_CODE (x));
12534 unsigned int regno = REGNO (x);
12535 unsigned int endregno = END_REGNO (x);
12538 for (j = regno; j < endregno; j++)
12540 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, j);
12541 if (rsp->last_set_invalid
12542 /* If this is a pseudo-register that was only set once and not
12543 live at the beginning of the function, it is always valid. */
12544 || (! (regno >= FIRST_PSEUDO_REGISTER
12545 && REG_N_SETS (regno) == 1
12546 && (!REGNO_REG_SET_P
12547 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno)))
12548 && rsp->last_set_label > tick))
12551 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12558 /* If this is a memory reference, make sure that there were no stores after
12559 it that might have clobbered the value. We don't have alias info, so we
12560 assume any store invalidates it. Moreover, we only have local UIDs, so
12561 we also assume that there were stores in the intervening basic blocks. */
12562 else if (MEM_P (x) && !MEM_READONLY_P (x)
12563 && (tick != label_tick || DF_INSN_LUID (insn) <= mem_last_set))
12566 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12570 for (i = 0; i < len; i++)
12574 /* Check for identical subexpressions. If x contains
12575 identical subexpression we only have to traverse one of
12577 if (i == 1 && ARITHMETIC_P (x))
12579 /* Note that at this point x0 has already been checked
12580 and found valid. */
12581 rtx x0 = XEXP (x, 0);
12582 rtx x1 = XEXP (x, 1);
12584 /* If x0 and x1 are identical then x is also valid. */
12588 /* If x1 is identical to a subexpression of x0 then
12589 while checking x0, x1 has already been checked. Thus
12590 it is valid and so as x. */
12591 if (ARITHMETIC_P (x0)
12592 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12595 /* If x0 is identical to a subexpression of x1 then x is
12596 valid iff the rest of x1 is valid. */
12597 if (ARITHMETIC_P (x1)
12598 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12600 get_last_value_validate (&XEXP (x1,
12601 x0 == XEXP (x1, 0) ? 1 : 0),
12602 insn, tick, replace);
12605 if (get_last_value_validate (&XEXP (x, i), insn, tick,
12609 else if (fmt[i] == 'E')
12610 for (j = 0; j < XVECLEN (x, i); j++)
12611 if (get_last_value_validate (&XVECEXP (x, i, j),
12612 insn, tick, replace) == 0)
12616 /* If we haven't found a reason for it to be invalid, it is valid. */
12620 /* Get the last value assigned to X, if known. Some registers
12621 in the value may be replaced with (clobber (const_int 0)) if their value
12622 is known longer known reliably. */
12625 get_last_value (const_rtx x)
12627 unsigned int regno;
12629 reg_stat_type *rsp;
12631 /* If this is a non-paradoxical SUBREG, get the value of its operand and
12632 then convert it to the desired mode. If this is a paradoxical SUBREG,
12633 we cannot predict what values the "extra" bits might have. */
12634 if (GET_CODE (x) == SUBREG
12635 && subreg_lowpart_p (x)
12636 && (GET_MODE_SIZE (GET_MODE (x))
12637 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
12638 && (value = get_last_value (SUBREG_REG (x))) != 0)
12639 return gen_lowpart (GET_MODE (x), value);
12645 rsp = VEC_index (reg_stat_type, reg_stat, regno);
12646 value = rsp->last_set_value;
12648 /* If we don't have a value, or if it isn't for this basic block and
12649 it's either a hard register, set more than once, or it's a live
12650 at the beginning of the function, return 0.
12652 Because if it's not live at the beginning of the function then the reg
12653 is always set before being used (is never used without being set).
12654 And, if it's set only once, and it's always set before use, then all
12655 uses must have the same last value, even if it's not from this basic
12659 || (rsp->last_set_label < label_tick_ebb_start
12660 && (regno < FIRST_PSEUDO_REGISTER
12661 || REG_N_SETS (regno) != 1
12663 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno))))
12666 /* If the value was set in a later insn than the ones we are processing,
12667 we can't use it even if the register was only set once. */
12668 if (rsp->last_set_label == label_tick
12669 && DF_INSN_LUID (rsp->last_set) >= subst_low_luid)
12672 /* If the value has all its registers valid, return it. */
12673 if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 0))
12676 /* Otherwise, make a copy and replace any invalid register with
12677 (clobber (const_int 0)). If that fails for some reason, return 0. */
12679 value = copy_rtx (value);
12680 if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 1))
12686 /* Return nonzero if expression X refers to a REG or to memory
12687 that is set in an instruction more recent than FROM_LUID. */
12690 use_crosses_set_p (const_rtx x, int from_luid)
12694 enum rtx_code code = GET_CODE (x);
12698 unsigned int regno = REGNO (x);
12699 unsigned endreg = END_REGNO (x);
12701 #ifdef PUSH_ROUNDING
12702 /* Don't allow uses of the stack pointer to be moved,
12703 because we don't know whether the move crosses a push insn. */
12704 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
12707 for (; regno < endreg; regno++)
12709 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
12711 && rsp->last_set_label == label_tick
12712 && DF_INSN_LUID (rsp->last_set) > from_luid)
12718 if (code == MEM && mem_last_set > from_luid)
12721 fmt = GET_RTX_FORMAT (code);
12723 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12728 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12729 if (use_crosses_set_p (XVECEXP (x, i, j), from_luid))
12732 else if (fmt[i] == 'e'
12733 && use_crosses_set_p (XEXP (x, i), from_luid))
12739 /* Define three variables used for communication between the following
12742 static unsigned int reg_dead_regno, reg_dead_endregno;
12743 static int reg_dead_flag;
12745 /* Function called via note_stores from reg_dead_at_p.
12747 If DEST is within [reg_dead_regno, reg_dead_endregno), set
12748 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
12751 reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
12753 unsigned int regno, endregno;
12758 regno = REGNO (dest);
12759 endregno = END_REGNO (dest);
12760 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
12761 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
12764 /* Return nonzero if REG is known to be dead at INSN.
12766 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12767 referencing REG, it is dead. If we hit a SET referencing REG, it is
12768 live. Otherwise, see if it is live or dead at the start of the basic
12769 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12770 must be assumed to be always live. */
12773 reg_dead_at_p (rtx reg, rtx insn)
12778 /* Set variables for reg_dead_at_p_1. */
12779 reg_dead_regno = REGNO (reg);
12780 reg_dead_endregno = END_REGNO (reg);
12784 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
12785 we allow the machine description to decide whether use-and-clobber
12786 patterns are OK. */
12787 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
12789 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12790 if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
12794 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12795 beginning of basic block. */
12796 block = BLOCK_FOR_INSN (insn);
12801 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
12803 return reg_dead_flag == 1 ? 1 : 0;
12805 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
12809 if (insn == BB_HEAD (block))
12812 insn = PREV_INSN (insn);
12815 /* Look at live-in sets for the basic block that we were in. */
12816 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12817 if (REGNO_REG_SET_P (df_get_live_in (block), i))
12823 /* Note hard registers in X that are used. */
12826 mark_used_regs_combine (rtx x)
12828 RTX_CODE code = GET_CODE (x);
12829 unsigned int regno;
12842 case ADDR_DIFF_VEC:
12845 /* CC0 must die in the insn after it is set, so we don't need to take
12846 special note of it here. */
12852 /* If we are clobbering a MEM, mark any hard registers inside the
12853 address as used. */
12854 if (MEM_P (XEXP (x, 0)))
12855 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
12860 /* A hard reg in a wide mode may really be multiple registers.
12861 If so, mark all of them just like the first. */
12862 if (regno < FIRST_PSEUDO_REGISTER)
12864 /* None of this applies to the stack, frame or arg pointers. */
12865 if (regno == STACK_POINTER_REGNUM
12866 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
12867 || regno == HARD_FRAME_POINTER_REGNUM
12869 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12870 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
12872 || regno == FRAME_POINTER_REGNUM)
12875 add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno);
12881 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12883 rtx testreg = SET_DEST (x);
12885 while (GET_CODE (testreg) == SUBREG
12886 || GET_CODE (testreg) == ZERO_EXTRACT
12887 || GET_CODE (testreg) == STRICT_LOW_PART)
12888 testreg = XEXP (testreg, 0);
12890 if (MEM_P (testreg))
12891 mark_used_regs_combine (XEXP (testreg, 0));
12893 mark_used_regs_combine (SET_SRC (x));
12901 /* Recursively scan the operands of this expression. */
12904 const char *fmt = GET_RTX_FORMAT (code);
12906 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12909 mark_used_regs_combine (XEXP (x, i));
12910 else if (fmt[i] == 'E')
12914 for (j = 0; j < XVECLEN (x, i); j++)
12915 mark_used_regs_combine (XVECEXP (x, i, j));
12921 /* Remove register number REGNO from the dead registers list of INSN.
12923 Return the note used to record the death, if there was one. */
12926 remove_death (unsigned int regno, rtx insn)
12928 rtx note = find_regno_note (insn, REG_DEAD, regno);
12931 remove_note (insn, note);
12936 /* For each register (hardware or pseudo) used within expression X, if its
12937 death is in an instruction with luid between FROM_LUID (inclusive) and
12938 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12939 list headed by PNOTES.
12941 That said, don't move registers killed by maybe_kill_insn.
12943 This is done when X is being merged by combination into TO_INSN. These
12944 notes will then be distributed as needed. */
12947 move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx to_insn,
12952 enum rtx_code code = GET_CODE (x);
12956 unsigned int regno = REGNO (x);
12957 rtx where_dead = VEC_index (reg_stat_type, reg_stat, regno)->last_death;
12959 /* Don't move the register if it gets killed in between from and to. */
12960 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
12961 && ! reg_referenced_p (x, maybe_kill_insn))
12965 && BLOCK_FOR_INSN (where_dead) == BLOCK_FOR_INSN (to_insn)
12966 && DF_INSN_LUID (where_dead) >= from_luid
12967 && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn))
12969 rtx note = remove_death (regno, where_dead);
12971 /* It is possible for the call above to return 0. This can occur
12972 when last_death points to I2 or I1 that we combined with.
12973 In that case make a new note.
12975 We must also check for the case where X is a hard register
12976 and NOTE is a death note for a range of hard registers
12977 including X. In that case, we must put REG_DEAD notes for
12978 the remaining registers in place of NOTE. */
12980 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
12981 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12982 > GET_MODE_SIZE (GET_MODE (x))))
12984 unsigned int deadregno = REGNO (XEXP (note, 0));
12985 unsigned int deadend = END_HARD_REGNO (XEXP (note, 0));
12986 unsigned int ourend = END_HARD_REGNO (x);
12989 for (i = deadregno; i < deadend; i++)
12990 if (i < regno || i >= ourend)
12991 add_reg_note (where_dead, REG_DEAD, regno_reg_rtx[i]);
12994 /* If we didn't find any note, or if we found a REG_DEAD note that
12995 covers only part of the given reg, and we have a multi-reg hard
12996 register, then to be safe we must check for REG_DEAD notes
12997 for each register other than the first. They could have
12998 their own REG_DEAD notes lying around. */
12999 else if ((note == 0
13001 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
13002 < GET_MODE_SIZE (GET_MODE (x)))))
13003 && regno < FIRST_PSEUDO_REGISTER
13004 && hard_regno_nregs[regno][GET_MODE (x)] > 1)
13006 unsigned int ourend = END_HARD_REGNO (x);
13007 unsigned int i, offset;
13011 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
13015 for (i = regno + offset; i < ourend; i++)
13016 move_deaths (regno_reg_rtx[i],
13017 maybe_kill_insn, from_luid, to_insn, &oldnotes);
13020 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
13022 XEXP (note, 1) = *pnotes;
13026 *pnotes = alloc_reg_note (REG_DEAD, x, *pnotes);
13032 else if (GET_CODE (x) == SET)
13034 rtx dest = SET_DEST (x);
13036 move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes);
13038 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13039 that accesses one word of a multi-word item, some
13040 piece of everything register in the expression is used by
13041 this insn, so remove any old death. */
13042 /* ??? So why do we test for equality of the sizes? */
13044 if (GET_CODE (dest) == ZERO_EXTRACT
13045 || GET_CODE (dest) == STRICT_LOW_PART
13046 || (GET_CODE (dest) == SUBREG
13047 && (((GET_MODE_SIZE (GET_MODE (dest))
13048 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
13049 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
13050 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
13052 move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes);
13056 /* If this is some other SUBREG, we know it replaces the entire
13057 value, so use that as the destination. */
13058 if (GET_CODE (dest) == SUBREG)
13059 dest = SUBREG_REG (dest);
13061 /* If this is a MEM, adjust deaths of anything used in the address.
13062 For a REG (the only other possibility), the entire value is
13063 being replaced so the old value is not used in this insn. */
13066 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid,
13071 else if (GET_CODE (x) == CLOBBER)
13074 len = GET_RTX_LENGTH (code);
13075 fmt = GET_RTX_FORMAT (code);
13077 for (i = 0; i < len; i++)
13082 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
13083 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid,
13086 else if (fmt[i] == 'e')
13087 move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes);
13091 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13092 pattern of an insn. X must be a REG. */
13095 reg_bitfield_target_p (rtx x, rtx body)
13099 if (GET_CODE (body) == SET)
13101 rtx dest = SET_DEST (body);
13103 unsigned int regno, tregno, endregno, endtregno;
13105 if (GET_CODE (dest) == ZERO_EXTRACT)
13106 target = XEXP (dest, 0);
13107 else if (GET_CODE (dest) == STRICT_LOW_PART)
13108 target = SUBREG_REG (XEXP (dest, 0));
13112 if (GET_CODE (target) == SUBREG)
13113 target = SUBREG_REG (target);
13115 if (!REG_P (target))
13118 tregno = REGNO (target), regno = REGNO (x);
13119 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
13120 return target == x;
13122 endtregno = end_hard_regno (GET_MODE (target), tregno);
13123 endregno = end_hard_regno (GET_MODE (x), regno);
13125 return endregno > tregno && regno < endtregno;
13128 else if (GET_CODE (body) == PARALLEL)
13129 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
13130 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
13136 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13137 as appropriate. I3 and I2 are the insns resulting from the combination
13138 insns including FROM (I2 may be zero).
13140 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13141 not need REG_DEAD notes because they are being substituted for. This
13142 saves searching in the most common cases.
13144 Each note in the list is either ignored or placed on some insns, depending
13145 on the type of note. */
13148 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
13149 rtx elim_i1, rtx elim_i0)
13151 rtx note, next_note;
13154 for (note = notes; note; note = next_note)
13156 rtx place = 0, place2 = 0;
13158 next_note = XEXP (note, 1);
13159 switch (REG_NOTE_KIND (note))
13163 /* Doesn't matter much where we put this, as long as it's somewhere.
13164 It is preferable to keep these notes on branches, which is most
13165 likely to be i3. */
13169 case REG_NON_LOCAL_GOTO:
13174 gcc_assert (i2 && JUMP_P (i2));
13179 case REG_EH_REGION:
13180 /* These notes must remain with the call or trapping instruction. */
13183 else if (i2 && CALL_P (i2))
13187 gcc_assert (cfun->can_throw_non_call_exceptions);
13188 if (may_trap_p (i3))
13190 else if (i2 && may_trap_p (i2))
13192 /* ??? Otherwise assume we've combined things such that we
13193 can now prove that the instructions can't trap. Drop the
13194 note in this case. */
13200 /* These notes must remain with the call. It should not be
13201 possible for both I2 and I3 to be a call. */
13206 gcc_assert (i2 && CALL_P (i2));
13212 /* Any clobbers for i3 may still exist, and so we must process
13213 REG_UNUSED notes from that insn.
13215 Any clobbers from i2 or i1 can only exist if they were added by
13216 recog_for_combine. In that case, recog_for_combine created the
13217 necessary REG_UNUSED notes. Trying to keep any original
13218 REG_UNUSED notes from these insns can cause incorrect output
13219 if it is for the same register as the original i3 dest.
13220 In that case, we will notice that the register is set in i3,
13221 and then add a REG_UNUSED note for the destination of i3, which
13222 is wrong. However, it is possible to have REG_UNUSED notes from
13223 i2 or i1 for register which were both used and clobbered, so
13224 we keep notes from i2 or i1 if they will turn into REG_DEAD
13227 /* If this register is set or clobbered in I3, put the note there
13228 unless there is one already. */
13229 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
13231 if (from_insn != i3)
13234 if (! (REG_P (XEXP (note, 0))
13235 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
13236 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
13239 /* Otherwise, if this register is used by I3, then this register
13240 now dies here, so we must put a REG_DEAD note here unless there
13242 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
13243 && ! (REG_P (XEXP (note, 0))
13244 ? find_regno_note (i3, REG_DEAD,
13245 REGNO (XEXP (note, 0)))
13246 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
13248 PUT_REG_NOTE_KIND (note, REG_DEAD);
13256 /* These notes say something about results of an insn. We can
13257 only support them if they used to be on I3 in which case they
13258 remain on I3. Otherwise they are ignored.
13260 If the note refers to an expression that is not a constant, we
13261 must also ignore the note since we cannot tell whether the
13262 equivalence is still true. It might be possible to do
13263 slightly better than this (we only have a problem if I2DEST
13264 or I1DEST is present in the expression), but it doesn't
13265 seem worth the trouble. */
13267 if (from_insn == i3
13268 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
13273 /* These notes say something about how a register is used. They must
13274 be present on any use of the register in I2 or I3. */
13275 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
13278 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
13287 case REG_LABEL_TARGET:
13288 case REG_LABEL_OPERAND:
13289 /* This can show up in several ways -- either directly in the
13290 pattern, or hidden off in the constant pool with (or without?)
13291 a REG_EQUAL note. */
13292 /* ??? Ignore the without-reg_equal-note problem for now. */
13293 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
13294 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
13295 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
13296 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
13300 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
13301 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
13302 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
13303 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
13311 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13312 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13314 if (place && JUMP_P (place)
13315 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
13316 && (JUMP_LABEL (place) == NULL
13317 || JUMP_LABEL (place) == XEXP (note, 0)))
13319 rtx label = JUMP_LABEL (place);
13322 JUMP_LABEL (place) = XEXP (note, 0);
13323 else if (LABEL_P (label))
13324 LABEL_NUSES (label)--;
13327 if (place2 && JUMP_P (place2)
13328 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
13329 && (JUMP_LABEL (place2) == NULL
13330 || JUMP_LABEL (place2) == XEXP (note, 0)))
13332 rtx label = JUMP_LABEL (place2);
13335 JUMP_LABEL (place2) = XEXP (note, 0);
13336 else if (LABEL_P (label))
13337 LABEL_NUSES (label)--;
13343 /* This note says something about the value of a register prior
13344 to the execution of an insn. It is too much trouble to see
13345 if the note is still correct in all situations. It is better
13346 to simply delete it. */
13350 /* If we replaced the right hand side of FROM_INSN with a
13351 REG_EQUAL note, the original use of the dying register
13352 will not have been combined into I3 and I2. In such cases,
13353 FROM_INSN is guaranteed to be the first of the combined
13354 instructions, so we simply need to search back before
13355 FROM_INSN for the previous use or set of this register,
13356 then alter the notes there appropriately.
13358 If the register is used as an input in I3, it dies there.
13359 Similarly for I2, if it is nonzero and adjacent to I3.
13361 If the register is not used as an input in either I3 or I2
13362 and it is not one of the registers we were supposed to eliminate,
13363 there are two possibilities. We might have a non-adjacent I2
13364 or we might have somehow eliminated an additional register
13365 from a computation. For example, we might have had A & B where
13366 we discover that B will always be zero. In this case we will
13367 eliminate the reference to A.
13369 In both cases, we must search to see if we can find a previous
13370 use of A and put the death note there. */
13373 && from_insn == i2mod
13374 && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
13379 && CALL_P (from_insn)
13380 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
13382 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
13384 else if (i2 != 0 && next_nonnote_nondebug_insn (i2) == i3
13385 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13387 else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
13389 && reg_overlap_mentioned_p (XEXP (note, 0),
13391 || rtx_equal_p (XEXP (note, 0), elim_i1)
13392 || rtx_equal_p (XEXP (note, 0), elim_i0))
13399 basic_block bb = this_basic_block;
13401 for (tem = PREV_INSN (tem); place == 0; tem = PREV_INSN (tem))
13403 if (!NONDEBUG_INSN_P (tem))
13405 if (tem == BB_HEAD (bb))
13410 /* If the register is being set at TEM, see if that is all
13411 TEM is doing. If so, delete TEM. Otherwise, make this
13412 into a REG_UNUSED note instead. Don't delete sets to
13413 global register vars. */
13414 if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
13415 || !global_regs[REGNO (XEXP (note, 0))])
13416 && reg_set_p (XEXP (note, 0), PATTERN (tem)))
13418 rtx set = single_set (tem);
13419 rtx inner_dest = 0;
13421 rtx cc0_setter = NULL_RTX;
13425 for (inner_dest = SET_DEST (set);
13426 (GET_CODE (inner_dest) == STRICT_LOW_PART
13427 || GET_CODE (inner_dest) == SUBREG
13428 || GET_CODE (inner_dest) == ZERO_EXTRACT);
13429 inner_dest = XEXP (inner_dest, 0))
13432 /* Verify that it was the set, and not a clobber that
13433 modified the register.
13435 CC0 targets must be careful to maintain setter/user
13436 pairs. If we cannot delete the setter due to side
13437 effects, mark the user with an UNUSED note instead
13440 if (set != 0 && ! side_effects_p (SET_SRC (set))
13441 && rtx_equal_p (XEXP (note, 0), inner_dest)
13443 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
13444 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
13445 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
13449 /* Move the notes and links of TEM elsewhere.
13450 This might delete other dead insns recursively.
13451 First set the pattern to something that won't use
13453 rtx old_notes = REG_NOTES (tem);
13455 PATTERN (tem) = pc_rtx;
13456 REG_NOTES (tem) = NULL;
13458 distribute_notes (old_notes, tem, tem, NULL_RTX,
13459 NULL_RTX, NULL_RTX, NULL_RTX);
13460 distribute_links (LOG_LINKS (tem));
13462 SET_INSN_DELETED (tem);
13467 /* Delete the setter too. */
13470 PATTERN (cc0_setter) = pc_rtx;
13471 old_notes = REG_NOTES (cc0_setter);
13472 REG_NOTES (cc0_setter) = NULL;
13474 distribute_notes (old_notes, cc0_setter,
13475 cc0_setter, NULL_RTX,
13476 NULL_RTX, NULL_RTX, NULL_RTX);
13477 distribute_links (LOG_LINKS (cc0_setter));
13479 SET_INSN_DELETED (cc0_setter);
13480 if (cc0_setter == i2)
13487 PUT_REG_NOTE_KIND (note, REG_UNUSED);
13489 /* If there isn't already a REG_UNUSED note, put one
13490 here. Do not place a REG_DEAD note, even if
13491 the register is also used here; that would not
13492 match the algorithm used in lifetime analysis
13493 and can cause the consistency check in the
13494 scheduler to fail. */
13495 if (! find_regno_note (tem, REG_UNUSED,
13496 REGNO (XEXP (note, 0))))
13501 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
13503 && find_reg_fusage (tem, USE, XEXP (note, 0))))
13507 /* If we are doing a 3->2 combination, and we have a
13508 register which formerly died in i3 and was not used
13509 by i2, which now no longer dies in i3 and is used in
13510 i2 but does not die in i2, and place is between i2
13511 and i3, then we may need to move a link from place to
13513 if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2)
13515 && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2)
13516 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13518 struct insn_link *links = LOG_LINKS (place);
13519 LOG_LINKS (place) = NULL;
13520 distribute_links (links);
13525 if (tem == BB_HEAD (bb))
13531 /* If the register is set or already dead at PLACE, we needn't do
13532 anything with this note if it is still a REG_DEAD note.
13533 We check here if it is set at all, not if is it totally replaced,
13534 which is what `dead_or_set_p' checks, so also check for it being
13537 if (place && REG_NOTE_KIND (note) == REG_DEAD)
13539 unsigned int regno = REGNO (XEXP (note, 0));
13540 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
13542 if (dead_or_set_p (place, XEXP (note, 0))
13543 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
13545 /* Unless the register previously died in PLACE, clear
13546 last_death. [I no longer understand why this is
13548 if (rsp->last_death != place)
13549 rsp->last_death = 0;
13553 rsp->last_death = place;
13555 /* If this is a death note for a hard reg that is occupying
13556 multiple registers, ensure that we are still using all
13557 parts of the object. If we find a piece of the object
13558 that is unused, we must arrange for an appropriate REG_DEAD
13559 note to be added for it. However, we can't just emit a USE
13560 and tag the note to it, since the register might actually
13561 be dead; so we recourse, and the recursive call then finds
13562 the previous insn that used this register. */
13564 if (place && regno < FIRST_PSEUDO_REGISTER
13565 && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
13567 unsigned int endregno = END_HARD_REGNO (XEXP (note, 0));
13571 for (i = regno; i < endregno; i++)
13572 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
13573 && ! find_regno_fusage (place, USE, i))
13574 || dead_or_set_regno_p (place, i))
13579 /* Put only REG_DEAD notes for pieces that are
13580 not already dead or set. */
13582 for (i = regno; i < endregno;
13583 i += hard_regno_nregs[i][reg_raw_mode[i]])
13585 rtx piece = regno_reg_rtx[i];
13586 basic_block bb = this_basic_block;
13588 if (! dead_or_set_p (place, piece)
13589 && ! reg_bitfield_target_p (piece,
13592 rtx new_note = alloc_reg_note (REG_DEAD, piece,
13595 distribute_notes (new_note, place, place,
13596 NULL_RTX, NULL_RTX, NULL_RTX,
13599 else if (! refers_to_regno_p (i, i + 1,
13600 PATTERN (place), 0)
13601 && ! find_regno_fusage (place, USE, i))
13602 for (tem = PREV_INSN (place); ;
13603 tem = PREV_INSN (tem))
13605 if (!NONDEBUG_INSN_P (tem))
13607 if (tem == BB_HEAD (bb))
13611 if (dead_or_set_p (tem, piece)
13612 || reg_bitfield_target_p (piece,
13615 add_reg_note (tem, REG_UNUSED, piece);
13629 /* Any other notes should not be present at this point in the
13631 gcc_unreachable ();
13636 XEXP (note, 1) = REG_NOTES (place);
13637 REG_NOTES (place) = note;
13641 add_reg_note (place2, REG_NOTE_KIND (note), XEXP (note, 0));
13645 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13646 I3, I2, and I1 to new locations. This is also called to add a link
13647 pointing at I3 when I3's destination is changed. */
13650 distribute_links (struct insn_link *links)
13652 struct insn_link *link, *next_link;
13654 for (link = links; link; link = next_link)
13660 next_link = link->next;
13662 /* If the insn that this link points to is a NOTE or isn't a single
13663 set, ignore it. In the latter case, it isn't clear what we
13664 can do other than ignore the link, since we can't tell which
13665 register it was for. Such links wouldn't be used by combine
13668 It is not possible for the destination of the target of the link to
13669 have been changed by combine. The only potential of this is if we
13670 replace I3, I2, and I1 by I3 and I2. But in that case the
13671 destination of I2 also remains unchanged. */
13673 if (NOTE_P (link->insn)
13674 || (set = single_set (link->insn)) == 0)
13677 reg = SET_DEST (set);
13678 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
13679 || GET_CODE (reg) == STRICT_LOW_PART)
13680 reg = XEXP (reg, 0);
13682 /* A LOG_LINK is defined as being placed on the first insn that uses
13683 a register and points to the insn that sets the register. Start
13684 searching at the next insn after the target of the link and stop
13685 when we reach a set of the register or the end of the basic block.
13687 Note that this correctly handles the link that used to point from
13688 I3 to I2. Also note that not much searching is typically done here
13689 since most links don't point very far away. */
13691 for (insn = NEXT_INSN (link->insn);
13692 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
13693 || BB_HEAD (this_basic_block->next_bb) != insn));
13694 insn = NEXT_INSN (insn))
13695 if (DEBUG_INSN_P (insn))
13697 else if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
13699 if (reg_referenced_p (reg, PATTERN (insn)))
13703 else if (CALL_P (insn)
13704 && find_reg_fusage (insn, USE, reg))
13709 else if (INSN_P (insn) && reg_set_p (reg, insn))
13712 /* If we found a place to put the link, place it there unless there
13713 is already a link to the same insn as LINK at that point. */
13717 struct insn_link *link2;
13719 FOR_EACH_LOG_LINK (link2, place)
13720 if (link2->insn == link->insn)
13725 link->next = LOG_LINKS (place);
13726 LOG_LINKS (place) = link;
13728 /* Set added_links_insn to the earliest insn we added a
13730 if (added_links_insn == 0
13731 || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place))
13732 added_links_insn = place;
13738 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
13739 Check whether the expression pointer to by LOC is a register or
13740 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
13741 Otherwise return zero. */
13744 unmentioned_reg_p_1 (rtx *loc, void *expr)
13749 && (REG_P (x) || MEM_P (x))
13750 && ! reg_mentioned_p (x, (rtx) expr))
13755 /* Check for any register or memory mentioned in EQUIV that is not
13756 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
13757 of EXPR where some registers may have been replaced by constants. */
13760 unmentioned_reg_p (rtx equiv, rtx expr)
13762 return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
13766 dump_combine_stats (FILE *file)
13770 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13771 combine_attempts, combine_merges, combine_extras, combine_successes);
13775 dump_combine_total_stats (FILE *file)
13779 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13780 total_attempts, total_merges, total_extras, total_successes);
13784 gate_handle_combine (void)
13786 return (optimize > 0);
13789 /* Try combining insns through substitution. */
13790 static unsigned int
13791 rest_of_handle_combine (void)
13793 int rebuild_jump_labels_after_combine;
13795 df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN);
13796 df_note_add_problem ();
13799 regstat_init_n_sets_and_refs ();
13801 rebuild_jump_labels_after_combine
13802 = combine_instructions (get_insns (), max_reg_num ());
13804 /* Combining insns may have turned an indirect jump into a
13805 direct jump. Rebuild the JUMP_LABEL fields of jumping
13807 if (rebuild_jump_labels_after_combine)
13809 timevar_push (TV_JUMP);
13810 rebuild_jump_labels (get_insns ());
13812 timevar_pop (TV_JUMP);
13815 regstat_free_n_sets_and_refs ();
13819 struct rtl_opt_pass pass_combine =
13823 "combine", /* name */
13824 gate_handle_combine, /* gate */
13825 rest_of_handle_combine, /* execute */
13828 0, /* static_pass_number */
13829 TV_COMBINE, /* tv_id */
13830 PROP_cfglayout, /* properties_required */
13831 0, /* properties_provided */
13832 0, /* properties_destroyed */
13833 0, /* todo_flags_start */
13835 TODO_df_finish | TODO_verify_rtl_sharing |
13836 TODO_ggc_collect, /* todo_flags_finish */