1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
23 /* This module is essentially the "combiner" phase of the U. of Arizona
24 Portable Optimizer, but redone to work on our list-structured
25 representation for RTL instead of their string representation.
27 The LOG_LINKS of each insn identify the most recent assignment
28 to each REG used in the insn. It is a list of previous insns,
29 each of which contains a SET for a REG that is used in this insn
30 and not used or set in between. LOG_LINKs never cross basic blocks.
31 They were set up by the preceding pass (lifetime analysis).
33 We try to combine each pair of insns joined by a logical link.
34 We also try to combine triples of insns A, B and C when
35 C has a link back to B and B has a link back to A.
37 LOG_LINKS does not have links for use of the CC0. They don't
38 need to, because the insn that sets the CC0 is always immediately
39 before the insn that tests it. So we always regard a branch
40 insn as having a logical link to the preceding insn. The same is true
41 for an insn explicitly using CC0.
43 We check (with use_crosses_set_p) to avoid combining in such a way
44 as to move a computation to a place where its value would be different.
46 Combination is done by mathematically substituting the previous
47 insn(s) values for the regs they set into the expressions in
48 the later insns that refer to these regs. If the result is a valid insn
49 for our target machine, according to the machine description,
50 we install it, delete the earlier insns, and update the data flow
51 information (LOG_LINKS and REG_NOTES) for what we did.
53 There are a few exceptions where the dataflow information created by
54 flow.c aren't completely updated:
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_regnotes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
84 #include "hard-reg-set.h"
85 #include "basic-block.h"
86 #include "insn-config.h"
88 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
90 #include "insn-flags.h"
91 #include "insn-codes.h"
92 #include "insn-attr.h"
98 #ifndef ACCUMULATE_OUTGOING_ARGS
99 #define ACCUMULATE_OUTGOING_ARGS 0
102 /* Supply a default definition for PUSH_ARGS. */
105 #define PUSH_ARGS !ACCUMULATE_OUTGOING_ARGS
111 /* It is not safe to use ordinary gen_lowpart in combine.
112 Use gen_lowpart_for_combine instead. See comments there. */
113 #define gen_lowpart dont_use_gen_lowpart_you_dummy
115 /* Number of attempts to combine instructions in this function. */
117 static int combine_attempts;
119 /* Number of attempts that got as far as substitution in this function. */
121 static int combine_merges;
123 /* Number of instructions combined with added SETs in this function. */
125 static int combine_extras;
127 /* Number of instructions combined in this function. */
129 static int combine_successes;
131 /* Totals over entire compilation. */
133 static int total_attempts, total_merges, total_extras, total_successes;
135 /* Define a default value for REVERSIBLE_CC_MODE.
136 We can never assume that a condition code mode is safe to reverse unless
137 the md tells us so. */
138 #ifndef REVERSIBLE_CC_MODE
139 #define REVERSIBLE_CC_MODE(MODE) 0
142 /* Vector mapping INSN_UIDs to cuids.
143 The cuids are like uids but increase monotonically always.
144 Combine always uses cuids so that it can compare them.
145 But actually renumbering the uids, which we used to do,
146 proves to be a bad idea because it makes it hard to compare
147 the dumps produced by earlier passes with those from later passes. */
149 static int *uid_cuid;
150 static int max_uid_cuid;
152 /* Get the cuid of an insn. */
154 #define INSN_CUID(INSN) \
155 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
157 /* Maximum register number, which is the size of the tables below. */
159 static unsigned int combine_max_regno;
161 /* Record last point of death of (hard or pseudo) register n. */
163 static rtx *reg_last_death;
165 /* Record last point of modification of (hard or pseudo) register n. */
167 static rtx *reg_last_set;
169 /* Record the cuid of the last insn that invalidated memory
170 (anything that writes memory, and subroutine calls, but not pushes). */
172 static int mem_last_set;
174 /* Record the cuid of the last CALL_INSN
175 so we can tell whether a potential combination crosses any calls. */
177 static int last_call_cuid;
179 /* When `subst' is called, this is the insn that is being modified
180 (by combining in a previous insn). The PATTERN of this insn
181 is still the old pattern partially modified and it should not be
182 looked at, but this may be used to examine the successors of the insn
183 to judge whether a simplification is valid. */
185 static rtx subst_insn;
187 /* This is an insn that belongs before subst_insn, but is not currently
188 on the insn chain. */
190 static rtx subst_prev_insn;
192 /* This is the lowest CUID that `subst' is currently dealing with.
193 get_last_value will not return a value if the register was set at or
194 after this CUID. If not for this mechanism, we could get confused if
195 I2 or I1 in try_combine were an insn that used the old value of a register
196 to obtain a new value. In that case, we might erroneously get the
197 new value of the register when we wanted the old one. */
199 static int subst_low_cuid;
201 /* This contains any hard registers that are used in newpat; reg_dead_at_p
202 must consider all these registers to be always live. */
204 static HARD_REG_SET newpat_used_regs;
206 /* This is an insn to which a LOG_LINKS entry has been added. If this
207 insn is the earlier than I2 or I3, combine should rescan starting at
210 static rtx added_links_insn;
212 /* Basic block number of the block in which we are performing combines. */
213 static int this_basic_block;
215 /* A bitmap indicating which blocks had registers go dead at entry.
216 After combine, we'll need to re-do global life analysis with
217 those blocks as starting points. */
218 static sbitmap refresh_blocks;
219 static int need_refresh;
221 /* The next group of arrays allows the recording of the last value assigned
222 to (hard or pseudo) register n. We use this information to see if a
223 operation being processed is redundant given a prior operation performed
224 on the register. For example, an `and' with a constant is redundant if
225 all the zero bits are already known to be turned off.
227 We use an approach similar to that used by cse, but change it in the
230 (1) We do not want to reinitialize at each label.
231 (2) It is useful, but not critical, to know the actual value assigned
232 to a register. Often just its form is helpful.
234 Therefore, we maintain the following arrays:
236 reg_last_set_value the last value assigned
237 reg_last_set_label records the value of label_tick when the
238 register was assigned
239 reg_last_set_table_tick records the value of label_tick when a
240 value using the register is assigned
241 reg_last_set_invalid set to non-zero when it is not valid
242 to use the value of this register in some
245 To understand the usage of these tables, it is important to understand
246 the distinction between the value in reg_last_set_value being valid
247 and the register being validly contained in some other expression in the
250 Entry I in reg_last_set_value is valid if it is non-zero, and either
251 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
253 Register I may validly appear in any expression returned for the value
254 of another register if reg_n_sets[i] is 1. It may also appear in the
255 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
256 reg_last_set_invalid[j] is zero.
258 If an expression is found in the table containing a register which may
259 not validly appear in an expression, the register is replaced by
260 something that won't match, (clobber (const_int 0)).
262 reg_last_set_invalid[i] is set non-zero when register I is being assigned
263 to and reg_last_set_table_tick[i] == label_tick. */
265 /* Record last value assigned to (hard or pseudo) register n. */
267 static rtx *reg_last_set_value;
269 /* Record the value of label_tick when the value for register n is placed in
270 reg_last_set_value[n]. */
272 static int *reg_last_set_label;
274 /* Record the value of label_tick when an expression involving register n
275 is placed in reg_last_set_value. */
277 static int *reg_last_set_table_tick;
279 /* Set non-zero if references to register n in expressions should not be
282 static char *reg_last_set_invalid;
284 /* Incremented for each label. */
286 static int label_tick;
288 /* Some registers that are set more than once and used in more than one
289 basic block are nevertheless always set in similar ways. For example,
290 a QImode register may be loaded from memory in two places on a machine
291 where byte loads zero extend.
293 We record in the following array what we know about the nonzero
294 bits of a register, specifically which bits are known to be zero.
296 If an entry is zero, it means that we don't know anything special. */
298 static unsigned HOST_WIDE_INT *reg_nonzero_bits;
300 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
301 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
303 static enum machine_mode nonzero_bits_mode;
305 /* Nonzero if we know that a register has some leading bits that are always
306 equal to the sign bit. */
308 static unsigned char *reg_sign_bit_copies;
310 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
311 It is zero while computing them and after combine has completed. This
312 former test prevents propagating values based on previously set values,
313 which can be incorrect if a variable is modified in a loop. */
315 static int nonzero_sign_valid;
317 /* These arrays are maintained in parallel with reg_last_set_value
318 and are used to store the mode in which the register was last set,
319 the bits that were known to be zero when it was last set, and the
320 number of sign bits copies it was known to have when it was last set. */
322 static enum machine_mode *reg_last_set_mode;
323 static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
324 static char *reg_last_set_sign_bit_copies;
326 /* Record one modification to rtl structure
327 to be undone by storing old_contents into *where.
328 is_int is 1 if the contents are an int. */
334 union {rtx r; int i;} old_contents;
335 union {rtx *r; int *i;} where;
338 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
339 num_undo says how many are currently recorded.
341 storage is nonzero if we must undo the allocation of new storage.
342 The value of storage is what to pass to obfree.
344 other_insn is nonzero if we have modified some other insn in the process
345 of working on subst_insn. It must be verified too.
347 previous_undos is the value of undobuf.undos when we started processing
348 this substitution. This will prevent gen_rtx_combine from re-used a piece
349 from the previous expression. Doing so can produce circular rtl
357 struct undo *previous_undos;
361 static struct undobuf undobuf;
363 /* Number of times the pseudo being substituted for
364 was found and replaced. */
366 static int n_occurrences;
368 static void do_SUBST PARAMS ((rtx *, rtx));
369 static void do_SUBST_INT PARAMS ((int *, int));
370 static void init_reg_last_arrays PARAMS ((void));
371 static void setup_incoming_promotions PARAMS ((void));
372 static void set_nonzero_bits_and_sign_copies PARAMS ((rtx, rtx, void *));
373 static int can_combine_p PARAMS ((rtx, rtx, rtx, rtx, rtx *, rtx *));
374 static int sets_function_arg_p PARAMS ((rtx));
375 static int combinable_i3pat PARAMS ((rtx, rtx *, rtx, rtx, int, rtx *));
376 static int contains_muldiv PARAMS ((rtx));
377 static rtx try_combine PARAMS ((rtx, rtx, rtx, int *));
378 static void undo_all PARAMS ((void));
379 static void undo_commit PARAMS ((void));
380 static rtx *find_split_point PARAMS ((rtx *, rtx));
381 static rtx subst PARAMS ((rtx, rtx, rtx, int, int));
382 static rtx combine_simplify_rtx PARAMS ((rtx, enum machine_mode, int, int));
383 static rtx simplify_if_then_else PARAMS ((rtx));
384 static rtx simplify_set PARAMS ((rtx));
385 static rtx simplify_logical PARAMS ((rtx, int));
386 static rtx expand_compound_operation PARAMS ((rtx));
387 static rtx expand_field_assignment PARAMS ((rtx));
388 static rtx make_extraction PARAMS ((enum machine_mode, rtx, HOST_WIDE_INT,
389 rtx, unsigned HOST_WIDE_INT, int,
391 static rtx extract_left_shift PARAMS ((rtx, int));
392 static rtx make_compound_operation PARAMS ((rtx, enum rtx_code));
393 static int get_pos_from_mask PARAMS ((unsigned HOST_WIDE_INT,
394 unsigned HOST_WIDE_INT *));
395 static rtx force_to_mode PARAMS ((rtx, enum machine_mode,
396 unsigned HOST_WIDE_INT, rtx, int));
397 static rtx if_then_else_cond PARAMS ((rtx, rtx *, rtx *));
398 static rtx known_cond PARAMS ((rtx, enum rtx_code, rtx, rtx));
399 static int rtx_equal_for_field_assignment_p PARAMS ((rtx, rtx));
400 static rtx make_field_assignment PARAMS ((rtx));
401 static rtx apply_distributive_law PARAMS ((rtx));
402 static rtx simplify_and_const_int PARAMS ((rtx, enum machine_mode, rtx,
403 unsigned HOST_WIDE_INT));
404 static unsigned HOST_WIDE_INT nonzero_bits PARAMS ((rtx, enum machine_mode));
405 static unsigned int num_sign_bit_copies PARAMS ((rtx, enum machine_mode));
406 static int merge_outer_ops PARAMS ((enum rtx_code *, HOST_WIDE_INT *,
407 enum rtx_code, HOST_WIDE_INT,
408 enum machine_mode, int *));
409 static rtx simplify_shift_const PARAMS ((rtx, enum rtx_code, enum machine_mode,
411 static int recog_for_combine PARAMS ((rtx *, rtx, rtx *));
412 static rtx gen_lowpart_for_combine PARAMS ((enum machine_mode, rtx));
413 static rtx gen_rtx_combine PARAMS ((enum rtx_code code, enum machine_mode mode,
415 static rtx gen_binary PARAMS ((enum rtx_code, enum machine_mode,
417 static rtx gen_unary PARAMS ((enum rtx_code, enum machine_mode,
418 enum machine_mode, rtx));
419 static enum rtx_code simplify_comparison PARAMS ((enum rtx_code, rtx *, rtx *));
420 static int reversible_comparison_p PARAMS ((rtx));
421 static void update_table_tick PARAMS ((rtx));
422 static void record_value_for_reg PARAMS ((rtx, rtx, rtx));
423 static void check_promoted_subreg PARAMS ((rtx, rtx));
424 static void record_dead_and_set_regs_1 PARAMS ((rtx, rtx, void *));
425 static void record_dead_and_set_regs PARAMS ((rtx));
426 static int get_last_value_validate PARAMS ((rtx *, rtx, int, int));
427 static rtx get_last_value PARAMS ((rtx));
428 static int use_crosses_set_p PARAMS ((rtx, int));
429 static void reg_dead_at_p_1 PARAMS ((rtx, rtx, void *));
430 static int reg_dead_at_p PARAMS ((rtx, rtx));
431 static void move_deaths PARAMS ((rtx, rtx, int, rtx, rtx *));
432 static int reg_bitfield_target_p PARAMS ((rtx, rtx));
433 static void distribute_notes PARAMS ((rtx, rtx, rtx, rtx, rtx, rtx));
434 static void distribute_links PARAMS ((rtx));
435 static void mark_used_regs_combine PARAMS ((rtx));
436 static int insn_cuid PARAMS ((rtx));
437 static void record_promoted_value PARAMS ((rtx, rtx));
439 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
440 insn. The substitution can be undone by undo_all. If INTO is already
441 set to NEWVAL, do not record this change. Because computing NEWVAL might
442 also call SUBST, we have to compute it before we put anything into
446 do_SUBST(into, newval)
452 if (oldval == newval)
456 buf = undobuf.frees, undobuf.frees = buf->next;
458 buf = (struct undo *) xmalloc (sizeof (struct undo));
462 buf->old_contents.r = oldval;
465 buf->next = undobuf.undos, undobuf.undos = buf;
468 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
470 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
471 for the value of a HOST_WIDE_INT value (including CONST_INT) is
475 do_SUBST_INT(into, newval)
481 if (oldval == newval)
485 buf = undobuf.frees, undobuf.frees = buf->next;
487 buf = (struct undo *) xmalloc (sizeof (struct undo));
491 buf->old_contents.i = oldval;
494 buf->next = undobuf.undos, undobuf.undos = buf;
497 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
499 /* Main entry point for combiner. F is the first insn of the function.
500 NREGS is the first unused pseudo-reg number.
502 Return non-zero if the combiner has turned an indirect jump
503 instruction into a direct jump. */
505 combine_instructions (f, nregs)
509 register rtx insn, next;
514 register rtx links, nextlinks;
516 int new_direct_jump_p = 0;
518 combine_attempts = 0;
521 combine_successes = 0;
523 combine_max_regno = nregs;
525 reg_nonzero_bits = ((unsigned HOST_WIDE_INT *)
526 xcalloc (nregs, sizeof (unsigned HOST_WIDE_INT)));
528 = (unsigned char *) xcalloc (nregs, sizeof (unsigned char));
530 reg_last_death = (rtx *) xmalloc (nregs * sizeof (rtx));
531 reg_last_set = (rtx *) xmalloc (nregs * sizeof (rtx));
532 reg_last_set_value = (rtx *) xmalloc (nregs * sizeof (rtx));
533 reg_last_set_table_tick = (int *) xmalloc (nregs * sizeof (int));
534 reg_last_set_label = (int *) xmalloc (nregs * sizeof (int));
535 reg_last_set_invalid = (char *) xmalloc (nregs * sizeof (char));
537 = (enum machine_mode *) xmalloc (nregs * sizeof (enum machine_mode));
538 reg_last_set_nonzero_bits
539 = (unsigned HOST_WIDE_INT *) xmalloc (nregs * sizeof (HOST_WIDE_INT));
540 reg_last_set_sign_bit_copies
541 = (char *) xmalloc (nregs * sizeof (char));
543 init_reg_last_arrays ();
545 init_recog_no_volatile ();
547 /* Compute maximum uid value so uid_cuid can be allocated. */
549 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
550 if (INSN_UID (insn) > i)
553 uid_cuid = (int *) xmalloc ((i + 1) * sizeof (int));
556 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
558 /* Don't use reg_nonzero_bits when computing it. This can cause problems
559 when, for example, we have j <<= 1 in a loop. */
561 nonzero_sign_valid = 0;
563 /* Compute the mapping from uids to cuids.
564 Cuids are numbers assigned to insns, like uids,
565 except that cuids increase monotonically through the code.
567 Scan all SETs and see if we can deduce anything about what
568 bits are known to be zero for some registers and how many copies
569 of the sign bit are known to exist for those registers.
571 Also set any known values so that we can use it while searching
572 for what bits are known to be set. */
576 /* We need to initialize it here, because record_dead_and_set_regs may call
578 subst_prev_insn = NULL_RTX;
580 setup_incoming_promotions ();
582 refresh_blocks = sbitmap_alloc (n_basic_blocks);
583 sbitmap_zero (refresh_blocks);
586 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
588 uid_cuid[INSN_UID (insn)] = ++i;
592 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
594 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
596 record_dead_and_set_regs (insn);
599 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
600 if (REG_NOTE_KIND (links) == REG_INC)
601 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
606 if (GET_CODE (insn) == CODE_LABEL)
610 nonzero_sign_valid = 1;
612 /* Now scan all the insns in forward order. */
614 this_basic_block = -1;
618 init_reg_last_arrays ();
619 setup_incoming_promotions ();
621 for (insn = f; insn; insn = next ? next : NEXT_INSN (insn))
625 /* If INSN starts a new basic block, update our basic block number. */
626 if (this_basic_block + 1 < n_basic_blocks
627 && BLOCK_HEAD (this_basic_block + 1) == insn)
630 if (GET_CODE (insn) == CODE_LABEL)
633 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
635 /* See if we know about function return values before this
636 insn based upon SUBREG flags. */
637 check_promoted_subreg (insn, PATTERN (insn));
639 /* Try this insn with each insn it links back to. */
641 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
642 if ((next = try_combine (insn, XEXP (links, 0),
643 NULL_RTX, &new_direct_jump_p)) != 0)
646 /* Try each sequence of three linked insns ending with this one. */
648 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
650 rtx link = XEXP (links, 0);
652 /* If the linked insn has been replaced by a note, then there
653 is no point in persuing this chain any further. */
654 if (GET_CODE (link) == NOTE)
657 for (nextlinks = LOG_LINKS (link);
659 nextlinks = XEXP (nextlinks, 1))
660 if ((next = try_combine (insn, XEXP (links, 0),
662 &new_direct_jump_p)) != 0)
667 /* Try to combine a jump insn that uses CC0
668 with a preceding insn that sets CC0, and maybe with its
669 logical predecessor as well.
670 This is how we make decrement-and-branch insns.
671 We need this special code because data flow connections
672 via CC0 do not get entered in LOG_LINKS. */
674 if (GET_CODE (insn) == JUMP_INSN
675 && (prev = prev_nonnote_insn (insn)) != 0
676 && GET_CODE (prev) == INSN
677 && sets_cc0_p (PATTERN (prev)))
679 if ((next = try_combine (insn, prev,
680 NULL_RTX, &new_direct_jump_p)) != 0)
683 for (nextlinks = LOG_LINKS (prev); nextlinks;
684 nextlinks = XEXP (nextlinks, 1))
685 if ((next = try_combine (insn, prev,
687 &new_direct_jump_p)) != 0)
691 /* Do the same for an insn that explicitly references CC0. */
692 if (GET_CODE (insn) == INSN
693 && (prev = prev_nonnote_insn (insn)) != 0
694 && GET_CODE (prev) == INSN
695 && sets_cc0_p (PATTERN (prev))
696 && GET_CODE (PATTERN (insn)) == SET
697 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
699 if ((next = try_combine (insn, prev,
700 NULL_RTX, &new_direct_jump_p)) != 0)
703 for (nextlinks = LOG_LINKS (prev); nextlinks;
704 nextlinks = XEXP (nextlinks, 1))
705 if ((next = try_combine (insn, prev,
707 &new_direct_jump_p)) != 0)
711 /* Finally, see if any of the insns that this insn links to
712 explicitly references CC0. If so, try this insn, that insn,
713 and its predecessor if it sets CC0. */
714 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
715 if (GET_CODE (XEXP (links, 0)) == INSN
716 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
717 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
718 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
719 && GET_CODE (prev) == INSN
720 && sets_cc0_p (PATTERN (prev))
721 && (next = try_combine (insn, XEXP (links, 0),
722 prev, &new_direct_jump_p)) != 0)
726 /* Try combining an insn with two different insns whose results it
728 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
729 for (nextlinks = XEXP (links, 1); nextlinks;
730 nextlinks = XEXP (nextlinks, 1))
731 if ((next = try_combine (insn, XEXP (links, 0),
733 &new_direct_jump_p)) != 0)
736 if (GET_CODE (insn) != NOTE)
737 record_dead_and_set_regs (insn);
746 compute_bb_for_insn (get_max_uid ());
747 update_life_info (refresh_blocks, UPDATE_LIFE_GLOBAL_RM_NOTES,
752 sbitmap_free (refresh_blocks);
753 free (reg_nonzero_bits);
754 free (reg_sign_bit_copies);
755 free (reg_last_death);
757 free (reg_last_set_value);
758 free (reg_last_set_table_tick);
759 free (reg_last_set_label);
760 free (reg_last_set_invalid);
761 free (reg_last_set_mode);
762 free (reg_last_set_nonzero_bits);
763 free (reg_last_set_sign_bit_copies);
767 struct undo *undo, *next;
768 for (undo = undobuf.frees; undo; undo = next)
776 total_attempts += combine_attempts;
777 total_merges += combine_merges;
778 total_extras += combine_extras;
779 total_successes += combine_successes;
781 nonzero_sign_valid = 0;
783 /* Make recognizer allow volatile MEMs again. */
786 return new_direct_jump_p;
789 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
792 init_reg_last_arrays ()
794 unsigned int nregs = combine_max_regno;
796 bzero ((char *) reg_last_death, nregs * sizeof (rtx));
797 bzero ((char *) reg_last_set, nregs * sizeof (rtx));
798 bzero ((char *) reg_last_set_value, nregs * sizeof (rtx));
799 bzero ((char *) reg_last_set_table_tick, nregs * sizeof (int));
800 bzero ((char *) reg_last_set_label, nregs * sizeof (int));
801 bzero (reg_last_set_invalid, nregs * sizeof (char));
802 bzero ((char *) reg_last_set_mode, nregs * sizeof (enum machine_mode));
803 bzero ((char *) reg_last_set_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
804 bzero (reg_last_set_sign_bit_copies, nregs * sizeof (char));
807 /* Set up any promoted values for incoming argument registers. */
810 setup_incoming_promotions ()
812 #ifdef PROMOTE_FUNCTION_ARGS
815 enum machine_mode mode;
817 rtx first = get_insns ();
819 #ifndef OUTGOING_REGNO
820 #define OUTGOING_REGNO(N) N
822 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
823 /* Check whether this register can hold an incoming pointer
824 argument. FUNCTION_ARG_REGNO_P tests outgoing register
825 numbers, so translate if necessary due to register windows. */
826 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
827 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
830 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
833 gen_rtx_CLOBBER (mode, const0_rtx)));
838 /* Called via note_stores. If X is a pseudo that is narrower than
839 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
841 If we are setting only a portion of X and we can't figure out what
842 portion, assume all bits will be used since we don't know what will
845 Similarly, set how many bits of X are known to be copies of the sign bit
846 at all locations in the function. This is the smallest number implied
850 set_nonzero_bits_and_sign_copies (x, set, data)
853 void *data ATTRIBUTE_UNUSED;
857 if (GET_CODE (x) == REG
858 && REGNO (x) >= FIRST_PSEUDO_REGISTER
859 /* If this register is undefined at the start of the file, we can't
860 say what its contents were. */
861 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start, REGNO (x))
862 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
864 if (set == 0 || GET_CODE (set) == CLOBBER)
866 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
867 reg_sign_bit_copies[REGNO (x)] = 1;
871 /* If this is a complex assignment, see if we can convert it into a
872 simple assignment. */
873 set = expand_field_assignment (set);
875 /* If this is a simple assignment, or we have a paradoxical SUBREG,
876 set what we know about X. */
878 if (SET_DEST (set) == x
879 || (GET_CODE (SET_DEST (set)) == SUBREG
880 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
881 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
882 && SUBREG_REG (SET_DEST (set)) == x))
884 rtx src = SET_SRC (set);
886 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
887 /* If X is narrower than a word and SRC is a non-negative
888 constant that would appear negative in the mode of X,
889 sign-extend it for use in reg_nonzero_bits because some
890 machines (maybe most) will actually do the sign-extension
891 and this is the conservative approach.
893 ??? For 2.5, try to tighten up the MD files in this regard
894 instead of this kludge. */
896 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
897 && GET_CODE (src) == CONST_INT
899 && 0 != (INTVAL (src)
901 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
902 src = GEN_INT (INTVAL (src)
903 | ((HOST_WIDE_INT) (-1)
904 << GET_MODE_BITSIZE (GET_MODE (x))));
907 reg_nonzero_bits[REGNO (x)]
908 |= nonzero_bits (src, nonzero_bits_mode);
909 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
910 if (reg_sign_bit_copies[REGNO (x)] == 0
911 || reg_sign_bit_copies[REGNO (x)] > num)
912 reg_sign_bit_copies[REGNO (x)] = num;
916 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
917 reg_sign_bit_copies[REGNO (x)] = 1;
922 /* See if INSN can be combined into I3. PRED and SUCC are optionally
923 insns that were previously combined into I3 or that will be combined
924 into the merger of INSN and I3.
926 Return 0 if the combination is not allowed for any reason.
928 If the combination is allowed, *PDEST will be set to the single
929 destination of INSN and *PSRC to the single source, and this function
933 can_combine_p (insn, i3, pred, succ, pdest, psrc)
936 rtx pred ATTRIBUTE_UNUSED;
941 rtx set = 0, src, dest;
946 int all_adjacent = (succ ? (next_active_insn (insn) == succ
947 && next_active_insn (succ) == i3)
948 : next_active_insn (insn) == i3);
950 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
951 or a PARALLEL consisting of such a SET and CLOBBERs.
953 If INSN has CLOBBER parallel parts, ignore them for our processing.
954 By definition, these happen during the execution of the insn. When it
955 is merged with another insn, all bets are off. If they are, in fact,
956 needed and aren't also supplied in I3, they may be added by
957 recog_for_combine. Otherwise, it won't match.
959 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
962 Get the source and destination of INSN. If more than one, can't
965 if (GET_CODE (PATTERN (insn)) == SET)
966 set = PATTERN (insn);
967 else if (GET_CODE (PATTERN (insn)) == PARALLEL
968 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
970 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
972 rtx elt = XVECEXP (PATTERN (insn), 0, i);
974 switch (GET_CODE (elt))
976 /* This is important to combine floating point insns
979 /* Combining an isolated USE doesn't make sense.
980 We depend here on combinable_i3_pat to reject them. */
981 /* The code below this loop only verifies that the inputs of
982 the SET in INSN do not change. We call reg_set_between_p
983 to verify that the REG in the USE does not change betweeen
985 If the USE in INSN was for a pseudo register, the matching
986 insn pattern will likely match any register; combining this
987 with any other USE would only be safe if we knew that the
988 used registers have identical values, or if there was
989 something to tell them apart, e.g. different modes. For
990 now, we forgo such compilcated tests and simply disallow
991 combining of USES of pseudo registers with any other USE. */
992 if (GET_CODE (XEXP (elt, 0)) == REG
993 && GET_CODE (PATTERN (i3)) == PARALLEL)
995 rtx i3pat = PATTERN (i3);
996 int i = XVECLEN (i3pat, 0) - 1;
997 unsigned int regno = REGNO (XEXP (elt, 0));
1001 rtx i3elt = XVECEXP (i3pat, 0, i);
1003 if (GET_CODE (i3elt) == USE
1004 && GET_CODE (XEXP (i3elt, 0)) == REG
1005 && (REGNO (XEXP (i3elt, 0)) == regno
1006 ? reg_set_between_p (XEXP (elt, 0),
1007 PREV_INSN (insn), i3)
1008 : regno >= FIRST_PSEUDO_REGISTER))
1015 /* We can ignore CLOBBERs. */
1020 /* Ignore SETs whose result isn't used but not those that
1021 have side-effects. */
1022 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1023 && ! side_effects_p (elt))
1026 /* If we have already found a SET, this is a second one and
1027 so we cannot combine with this insn. */
1035 /* Anything else means we can't combine. */
1041 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1042 so don't do anything with it. */
1043 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1052 set = expand_field_assignment (set);
1053 src = SET_SRC (set), dest = SET_DEST (set);
1055 /* Don't eliminate a store in the stack pointer. */
1056 if (dest == stack_pointer_rtx
1057 /* If we couldn't eliminate a field assignment, we can't combine. */
1058 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
1059 /* Don't combine with an insn that sets a register to itself if it has
1060 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1061 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1062 /* Can't merge a function call. */
1063 || GET_CODE (src) == CALL
1064 /* Don't eliminate a function call argument. */
1065 || (GET_CODE (i3) == CALL_INSN
1066 && (find_reg_fusage (i3, USE, dest)
1067 || (GET_CODE (dest) == REG
1068 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1069 && global_regs[REGNO (dest)])))
1070 /* Don't substitute into an incremented register. */
1071 || FIND_REG_INC_NOTE (i3, dest)
1072 || (succ && FIND_REG_INC_NOTE (succ, dest))
1074 /* Don't combine the end of a libcall into anything. */
1075 /* ??? This gives worse code, and appears to be unnecessary, since no
1076 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1077 use REG_RETVAL notes for noconflict blocks, but other code here
1078 makes sure that those insns don't disappear. */
1079 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1081 /* Make sure that DEST is not used after SUCC but before I3. */
1082 || (succ && ! all_adjacent
1083 && reg_used_between_p (dest, succ, i3))
1084 /* Make sure that the value that is to be substituted for the register
1085 does not use any registers whose values alter in between. However,
1086 If the insns are adjacent, a use can't cross a set even though we
1087 think it might (this can happen for a sequence of insns each setting
1088 the same destination; reg_last_set of that register might point to
1089 a NOTE). If INSN has a REG_EQUIV note, the register is always
1090 equivalent to the memory so the substitution is valid even if there
1091 are intervening stores. Also, don't move a volatile asm or
1092 UNSPEC_VOLATILE across any other insns. */
1094 && (((GET_CODE (src) != MEM
1095 || ! find_reg_note (insn, REG_EQUIV, src))
1096 && use_crosses_set_p (src, INSN_CUID (insn)))
1097 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1098 || GET_CODE (src) == UNSPEC_VOLATILE))
1099 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1100 better register allocation by not doing the combine. */
1101 || find_reg_note (i3, REG_NO_CONFLICT, dest)
1102 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1103 /* Don't combine across a CALL_INSN, because that would possibly
1104 change whether the life span of some REGs crosses calls or not,
1105 and it is a pain to update that information.
1106 Exception: if source is a constant, moving it later can't hurt.
1107 Accept that special case, because it helps -fforce-addr a lot. */
1108 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1111 /* DEST must either be a REG or CC0. */
1112 if (GET_CODE (dest) == REG)
1114 /* If register alignment is being enforced for multi-word items in all
1115 cases except for parameters, it is possible to have a register copy
1116 insn referencing a hard register that is not allowed to contain the
1117 mode being copied and which would not be valid as an operand of most
1118 insns. Eliminate this problem by not combining with such an insn.
1120 Also, on some machines we don't want to extend the life of a hard
1123 This is the same test done in can_combine except that we don't test
1124 if SRC is a CALL operation to permit a hard register with
1125 SMALL_REGISTER_CLASSES, and that we have to take all_adjacent
1128 if (GET_CODE (src) == REG
1129 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1130 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1131 /* Don't extend the life of a hard register unless it is
1132 user variable (if we have few registers) or it can't
1133 fit into the desired register (meaning something special
1135 Also avoid substituting a return register into I3, because
1136 reload can't handle a conflict with constraints of other
1138 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1139 && (! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src))
1140 || (SMALL_REGISTER_CLASSES
1141 && ((! all_adjacent && ! REG_USERVAR_P (src))
1142 || (FUNCTION_VALUE_REGNO_P (REGNO (src))
1143 && ! REG_USERVAR_P (src))))))))
1146 else if (GET_CODE (dest) != CC0)
1149 /* Don't substitute for a register intended as a clobberable operand.
1150 Similarly, don't substitute an expression containing a register that
1151 will be clobbered in I3. */
1152 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1153 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1154 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
1155 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
1157 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
1160 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1161 or not), reject, unless nothing volatile comes between it and I3 */
1163 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1165 /* Make sure succ doesn't contain a volatile reference. */
1166 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1169 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1170 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
1171 && p != succ && volatile_refs_p (PATTERN (p)))
1175 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1176 to be an explicit register variable, and was chosen for a reason. */
1178 if (GET_CODE (src) == ASM_OPERANDS
1179 && GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1182 /* If there are any volatile insns between INSN and I3, reject, because
1183 they might affect machine state. */
1185 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1186 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
1187 && p != succ && volatile_insn_p (PATTERN (p)))
1190 /* If INSN or I2 contains an autoincrement or autodecrement,
1191 make sure that register is not used between there and I3,
1192 and not already used in I3 either.
1193 Also insist that I3 not be a jump; if it were one
1194 and the incremented register were spilled, we would lose. */
1197 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1198 if (REG_NOTE_KIND (link) == REG_INC
1199 && (GET_CODE (i3) == JUMP_INSN
1200 || reg_used_between_p (XEXP (link, 0), insn, i3)
1201 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1206 /* Don't combine an insn that follows a CC0-setting insn.
1207 An insn that uses CC0 must not be separated from the one that sets it.
1208 We do, however, allow I2 to follow a CC0-setting insn if that insn
1209 is passed as I1; in that case it will be deleted also.
1210 We also allow combining in this case if all the insns are adjacent
1211 because that would leave the two CC0 insns adjacent as well.
1212 It would be more logical to test whether CC0 occurs inside I1 or I2,
1213 but that would be much slower, and this ought to be equivalent. */
1215 p = prev_nonnote_insn (insn);
1216 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
1221 /* If we get here, we have passed all the tests and the combination is
1230 /* Check if PAT is an insn - or a part of it - used to set up an
1231 argument for a function in a hard register. */
1234 sets_function_arg_p (pat)
1240 switch (GET_CODE (pat))
1243 return sets_function_arg_p (PATTERN (pat));
1246 for (i = XVECLEN (pat, 0); --i >= 0;)
1247 if (sets_function_arg_p (XVECEXP (pat, 0, i)))
1253 inner_dest = SET_DEST (pat);
1254 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1255 || GET_CODE (inner_dest) == SUBREG
1256 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1257 inner_dest = XEXP (inner_dest, 0);
1259 return (GET_CODE (inner_dest) == REG
1260 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1261 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest)));
1270 /* LOC is the location within I3 that contains its pattern or the component
1271 of a PARALLEL of the pattern. We validate that it is valid for combining.
1273 One problem is if I3 modifies its output, as opposed to replacing it
1274 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1275 so would produce an insn that is not equivalent to the original insns.
1279 (set (reg:DI 101) (reg:DI 100))
1280 (set (subreg:SI (reg:DI 101) 0) <foo>)
1282 This is NOT equivalent to:
1284 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1285 (set (reg:DI 101) (reg:DI 100))])
1287 Not only does this modify 100 (in which case it might still be valid
1288 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1290 We can also run into a problem if I2 sets a register that I1
1291 uses and I1 gets directly substituted into I3 (not via I2). In that
1292 case, we would be getting the wrong value of I2DEST into I3, so we
1293 must reject the combination. This case occurs when I2 and I1 both
1294 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1295 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1296 of a SET must prevent combination from occurring.
1298 On machines where SMALL_REGISTER_CLASSES is non-zero, we don't combine
1299 if the destination of a SET is a hard register that isn't a user
1302 Before doing the above check, we first try to expand a field assignment
1303 into a set of logical operations.
1305 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1306 we place a register that is both set and used within I3. If more than one
1307 such register is detected, we fail.
1309 Return 1 if the combination is valid, zero otherwise. */
1312 combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
1318 rtx *pi3dest_killed;
1322 if (GET_CODE (x) == SET)
1324 rtx set = expand_field_assignment (x);
1325 rtx dest = SET_DEST (set);
1326 rtx src = SET_SRC (set);
1327 rtx inner_dest = dest;
1330 rtx inner_src = src;
1335 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1336 || GET_CODE (inner_dest) == SUBREG
1337 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1338 inner_dest = XEXP (inner_dest, 0);
1340 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1343 while (GET_CODE (inner_src) == STRICT_LOW_PART
1344 || GET_CODE (inner_src) == SUBREG
1345 || GET_CODE (inner_src) == ZERO_EXTRACT)
1346 inner_src = XEXP (inner_src, 0);
1348 /* If it is better that two different modes keep two different pseudos,
1349 avoid combining them. This avoids producing the following pattern
1351 (set (subreg:SI (reg/v:QI 21) 0)
1352 (lshiftrt:SI (reg/v:SI 20)
1354 If that were made, reload could not handle the pair of
1355 reg 20/21, since it would try to get any GENERAL_REGS
1356 but some of them don't handle QImode. */
1358 if (rtx_equal_p (inner_src, i2dest)
1359 && GET_CODE (inner_dest) == REG
1360 && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
1364 /* Check for the case where I3 modifies its output, as
1366 if ((inner_dest != dest
1367 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1368 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1370 /* This is the same test done in can_combine_p except that we
1371 allow a hard register with SMALL_REGISTER_CLASSES if SRC is a
1372 CALL operation. Moreover, we can't test all_adjacent; we don't
1373 have to, since this instruction will stay in place, thus we are
1374 not considering increasing the lifetime of INNER_DEST.
1376 Also, if this insn sets a function argument, combining it with
1377 something that might need a spill could clobber a previous
1378 function argument; the all_adjacent test in can_combine_p also
1379 checks this; here, we do a more specific test for this case. */
1381 || (GET_CODE (inner_dest) == REG
1382 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1383 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1384 GET_MODE (inner_dest))
1385 || (SMALL_REGISTER_CLASSES && GET_CODE (src) != CALL
1386 && ! REG_USERVAR_P (inner_dest)
1387 && (FUNCTION_VALUE_REGNO_P (REGNO (inner_dest))
1388 || (FUNCTION_ARG_REGNO_P (REGNO (inner_dest))
1390 && sets_function_arg_p (prev_nonnote_insn (i3)))))))
1391 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1394 /* If DEST is used in I3, it is being killed in this insn,
1395 so record that for later.
1396 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1397 STACK_POINTER_REGNUM, since these are always considered to be
1398 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1399 if (pi3dest_killed && GET_CODE (dest) == REG
1400 && reg_referenced_p (dest, PATTERN (i3))
1401 && REGNO (dest) != FRAME_POINTER_REGNUM
1402 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1403 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1405 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1406 && (REGNO (dest) != ARG_POINTER_REGNUM
1407 || ! fixed_regs [REGNO (dest)])
1409 && REGNO (dest) != STACK_POINTER_REGNUM)
1411 if (*pi3dest_killed)
1414 *pi3dest_killed = dest;
1418 else if (GET_CODE (x) == PARALLEL)
1422 for (i = 0; i < XVECLEN (x, 0); i++)
1423 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1424 i1_not_in_src, pi3dest_killed))
1431 /* Return 1 if X is an arithmetic expression that contains a multiplication
1432 and division. We don't count multiplications by powers of two here. */
1438 switch (GET_CODE (x))
1440 case MOD: case DIV: case UMOD: case UDIV:
1444 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1445 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1447 switch (GET_RTX_CLASS (GET_CODE (x)))
1449 case 'c': case '<': case '2':
1450 return contains_muldiv (XEXP (x, 0))
1451 || contains_muldiv (XEXP (x, 1));
1454 return contains_muldiv (XEXP (x, 0));
1462 /* Try to combine the insns I1 and I2 into I3.
1463 Here I1 and I2 appear earlier than I3.
1464 I1 can be zero; then we combine just I2 into I3.
1466 It we are combining three insns and the resulting insn is not recognized,
1467 try splitting it into two insns. If that happens, I2 and I3 are retained
1468 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1471 Return 0 if the combination does not work. Then nothing is changed.
1472 If we did the combination, return the insn at which combine should
1475 Set NEW_DIRECT_JUMP_P to a non-zero value if try_combine creates a
1476 new direct jump instruction. */
1479 try_combine (i3, i2, i1, new_direct_jump_p)
1480 register rtx i3, i2, i1;
1481 register int *new_direct_jump_p;
1483 /* New patterns for I3 and I3, respectively. */
1484 rtx newpat, newi2pat = 0;
1485 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1486 int added_sets_1, added_sets_2;
1487 /* Total number of SETs to put into I3. */
1489 /* Nonzero is I2's body now appears in I3. */
1491 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1492 int insn_code_number, i2_code_number = 0, other_code_number = 0;
1493 /* Contains I3 if the destination of I3 is used in its source, which means
1494 that the old life of I3 is being killed. If that usage is placed into
1495 I2 and not in I3, a REG_DEAD note must be made. */
1496 rtx i3dest_killed = 0;
1497 /* SET_DEST and SET_SRC of I2 and I1. */
1498 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1499 /* PATTERN (I2), or a copy of it in certain cases. */
1501 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1502 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1503 int i1_feeds_i3 = 0;
1504 /* Notes that must be added to REG_NOTES in I3 and I2. */
1505 rtx new_i3_notes, new_i2_notes;
1506 /* Notes that we substituted I3 into I2 instead of the normal case. */
1507 int i3_subst_into_i2 = 0;
1508 /* Notes that I1, I2 or I3 is a MULT operation. */
1516 /* If any of I1, I2, and I3 isn't really an insn, we can't do anything.
1517 This can occur when flow deletes an insn that it has merged into an
1518 auto-increment address. We also can't do anything if I3 has a
1519 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1522 if (GET_RTX_CLASS (GET_CODE (i3)) != 'i'
1523 || GET_RTX_CLASS (GET_CODE (i2)) != 'i'
1524 || (i1 && GET_RTX_CLASS (GET_CODE (i1)) != 'i')
1526 /* ??? This gives worse code, and appears to be unnecessary, since no
1527 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1528 || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1534 undobuf.other_insn = 0;
1536 /* Save the current high-water-mark so we can free storage if we didn't
1537 accept this combination. */
1538 undobuf.storage = (char *) oballoc (0);
1540 /* Reset the hard register usage information. */
1541 CLEAR_HARD_REG_SET (newpat_used_regs);
1543 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1544 code below, set I1 to be the earlier of the two insns. */
1545 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1546 temp = i1, i1 = i2, i2 = temp;
1548 added_links_insn = 0;
1550 /* First check for one important special-case that the code below will
1551 not handle. Namely, the case where I1 is zero, I2 has multiple sets,
1552 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1553 we may be able to replace that destination with the destination of I3.
1554 This occurs in the common code where we compute both a quotient and
1555 remainder into a structure, in which case we want to do the computation
1556 directly into the structure to avoid register-register copies.
1558 We make very conservative checks below and only try to handle the
1559 most common cases of this. For example, we only handle the case
1560 where I2 and I3 are adjacent to avoid making difficult register
1563 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1564 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1565 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1566 && (! SMALL_REGISTER_CLASSES
1567 || (GET_CODE (SET_DEST (PATTERN (i3))) != REG
1568 || REGNO (SET_DEST (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1569 || REG_USERVAR_P (SET_DEST (PATTERN (i3)))))
1570 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1571 && GET_CODE (PATTERN (i2)) == PARALLEL
1572 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1573 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1574 below would need to check what is inside (and reg_overlap_mentioned_p
1575 doesn't support those codes anyway). Don't allow those destinations;
1576 the resulting insn isn't likely to be recognized anyway. */
1577 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1578 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1579 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1580 SET_DEST (PATTERN (i3)))
1581 && next_real_insn (i2) == i3)
1583 rtx p2 = PATTERN (i2);
1585 /* Make sure that the destination of I3,
1586 which we are going to substitute into one output of I2,
1587 is not used within another output of I2. We must avoid making this:
1588 (parallel [(set (mem (reg 69)) ...)
1589 (set (reg 69) ...)])
1590 which is not well-defined as to order of actions.
1591 (Besides, reload can't handle output reloads for this.)
1593 The problem can also happen if the dest of I3 is a memory ref,
1594 if another dest in I2 is an indirect memory ref. */
1595 for (i = 0; i < XVECLEN (p2, 0); i++)
1596 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1597 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1598 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1599 SET_DEST (XVECEXP (p2, 0, i))))
1602 if (i == XVECLEN (p2, 0))
1603 for (i = 0; i < XVECLEN (p2, 0); i++)
1604 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1605 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1606 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1611 subst_low_cuid = INSN_CUID (i2);
1613 added_sets_2 = added_sets_1 = 0;
1614 i2dest = SET_SRC (PATTERN (i3));
1616 /* Replace the dest in I2 with our dest and make the resulting
1617 insn the new pattern for I3. Then skip to where we
1618 validate the pattern. Everything was set up above. */
1619 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1620 SET_DEST (PATTERN (i3)));
1623 i3_subst_into_i2 = 1;
1624 goto validate_replacement;
1628 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1629 one of those words to another constant, merge them by making a new
1632 && (temp = single_set (i2)) != 0
1633 && (GET_CODE (SET_SRC (temp)) == CONST_INT
1634 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1635 && GET_CODE (SET_DEST (temp)) == REG
1636 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp))) == MODE_INT
1637 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp))) == 2 * UNITS_PER_WORD
1638 && GET_CODE (PATTERN (i3)) == SET
1639 && GET_CODE (SET_DEST (PATTERN (i3))) == SUBREG
1640 && SUBREG_REG (SET_DEST (PATTERN (i3))) == SET_DEST (temp)
1641 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3)))) == MODE_INT
1642 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3)))) == UNITS_PER_WORD
1643 && GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT)
1645 HOST_WIDE_INT lo, hi;
1647 if (GET_CODE (SET_SRC (temp)) == CONST_INT)
1648 lo = INTVAL (SET_SRC (temp)), hi = lo < 0 ? -1 : 0;
1651 lo = CONST_DOUBLE_LOW (SET_SRC (temp));
1652 hi = CONST_DOUBLE_HIGH (SET_SRC (temp));
1655 if (subreg_lowpart_p (SET_DEST (PATTERN (i3))))
1656 lo = INTVAL (SET_SRC (PATTERN (i3)));
1658 hi = INTVAL (SET_SRC (PATTERN (i3)));
1662 subst_low_cuid = INSN_CUID (i2);
1663 added_sets_2 = added_sets_1 = 0;
1664 i2dest = SET_DEST (temp);
1666 SUBST (SET_SRC (temp),
1667 immed_double_const (lo, hi, GET_MODE (SET_DEST (temp))));
1669 newpat = PATTERN (i2);
1670 i3_subst_into_i2 = 1;
1671 goto validate_replacement;
1675 /* If we have no I1 and I2 looks like:
1676 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1678 make up a dummy I1 that is
1681 (set (reg:CC X) (compare:CC Y (const_int 0)))
1683 (We can ignore any trailing CLOBBERs.)
1685 This undoes a previous combination and allows us to match a branch-and-
1688 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1689 && XVECLEN (PATTERN (i2), 0) >= 2
1690 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1691 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1693 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1694 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1695 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1696 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1697 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1698 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1700 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1701 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1706 /* We make I1 with the same INSN_UID as I2. This gives it
1707 the same INSN_CUID for value tracking. Our fake I1 will
1708 never appear in the insn stream so giving it the same INSN_UID
1709 as I2 will not cause a problem. */
1711 subst_prev_insn = i1
1712 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1713 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
1716 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1717 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1718 SET_DEST (PATTERN (i1)));
1723 /* Verify that I2 and I1 are valid for combining. */
1724 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1725 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1731 /* Record whether I2DEST is used in I2SRC and similarly for the other
1732 cases. Knowing this will help in register status updating below. */
1733 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1734 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1735 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1737 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1739 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1741 /* Ensure that I3's pattern can be the destination of combines. */
1742 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1743 i1 && i2dest_in_i1src && i1_feeds_i3,
1750 /* See if any of the insns is a MULT operation. Unless one is, we will
1751 reject a combination that is, since it must be slower. Be conservative
1753 if (GET_CODE (i2src) == MULT
1754 || (i1 != 0 && GET_CODE (i1src) == MULT)
1755 || (GET_CODE (PATTERN (i3)) == SET
1756 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1759 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1760 We used to do this EXCEPT in one case: I3 has a post-inc in an
1761 output operand. However, that exception can give rise to insns like
1763 which is a famous insn on the PDP-11 where the value of r3 used as the
1764 source was model-dependent. Avoid this sort of thing. */
1767 if (!(GET_CODE (PATTERN (i3)) == SET
1768 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1769 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1770 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1771 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1772 /* It's not the exception. */
1775 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1776 if (REG_NOTE_KIND (link) == REG_INC
1777 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1779 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1786 /* See if the SETs in I1 or I2 need to be kept around in the merged
1787 instruction: whenever the value set there is still needed past I3.
1788 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1790 For the SET in I1, we have two cases: If I1 and I2 independently
1791 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1792 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1793 in I1 needs to be kept around unless I1DEST dies or is set in either
1794 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1795 I1DEST. If so, we know I1 feeds into I2. */
1797 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1800 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1801 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1803 /* If the set in I2 needs to be kept around, we must make a copy of
1804 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1805 PATTERN (I2), we are only substituting for the original I1DEST, not into
1806 an already-substituted copy. This also prevents making self-referential
1807 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1810 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1811 ? gen_rtx_SET (VOIDmode, i2dest, i2src)
1815 i2pat = copy_rtx (i2pat);
1819 /* Substitute in the latest insn for the regs set by the earlier ones. */
1821 maxreg = max_reg_num ();
1825 /* It is possible that the source of I2 or I1 may be performing an
1826 unneeded operation, such as a ZERO_EXTEND of something that is known
1827 to have the high part zero. Handle that case by letting subst look at
1828 the innermost one of them.
1830 Another way to do this would be to have a function that tries to
1831 simplify a single insn instead of merging two or more insns. We don't
1832 do this because of the potential of infinite loops and because
1833 of the potential extra memory required. However, doing it the way
1834 we are is a bit of a kludge and doesn't catch all cases.
1836 But only do this if -fexpensive-optimizations since it slows things down
1837 and doesn't usually win. */
1839 if (flag_expensive_optimizations)
1841 /* Pass pc_rtx so no substitutions are done, just simplifications.
1842 The cases that we are interested in here do not involve the few
1843 cases were is_replaced is checked. */
1846 subst_low_cuid = INSN_CUID (i1);
1847 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1851 subst_low_cuid = INSN_CUID (i2);
1852 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1855 undobuf.previous_undos = undobuf.undos;
1859 /* Many machines that don't use CC0 have insns that can both perform an
1860 arithmetic operation and set the condition code. These operations will
1861 be represented as a PARALLEL with the first element of the vector
1862 being a COMPARE of an arithmetic operation with the constant zero.
1863 The second element of the vector will set some pseudo to the result
1864 of the same arithmetic operation. If we simplify the COMPARE, we won't
1865 match such a pattern and so will generate an extra insn. Here we test
1866 for this case, where both the comparison and the operation result are
1867 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1868 I2SRC. Later we will make the PARALLEL that contains I2. */
1870 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1871 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1872 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1873 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1875 #ifdef EXTRA_CC_MODES
1877 enum machine_mode compare_mode;
1880 newpat = PATTERN (i3);
1881 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1885 #ifdef EXTRA_CC_MODES
1886 /* See if a COMPARE with the operand we substituted in should be done
1887 with the mode that is currently being used. If not, do the same
1888 processing we do in `subst' for a SET; namely, if the destination
1889 is used only once, try to replace it with a register of the proper
1890 mode and also replace the COMPARE. */
1891 if (undobuf.other_insn == 0
1892 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1893 &undobuf.other_insn))
1894 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1896 != GET_MODE (SET_DEST (newpat))))
1898 unsigned int regno = REGNO (SET_DEST (newpat));
1899 rtx new_dest = gen_rtx_REG (compare_mode, regno);
1901 if (regno < FIRST_PSEUDO_REGISTER
1902 || (REG_N_SETS (regno) == 1 && ! added_sets_2
1903 && ! REG_USERVAR_P (SET_DEST (newpat))))
1905 if (regno >= FIRST_PSEUDO_REGISTER)
1906 SUBST (regno_reg_rtx[regno], new_dest);
1908 SUBST (SET_DEST (newpat), new_dest);
1909 SUBST (XEXP (*cc_use, 0), new_dest);
1910 SUBST (SET_SRC (newpat),
1911 gen_rtx_combine (COMPARE, compare_mode,
1912 i2src, const0_rtx));
1915 undobuf.other_insn = 0;
1922 n_occurrences = 0; /* `subst' counts here */
1924 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1925 need to make a unique copy of I2SRC each time we substitute it
1926 to avoid self-referential rtl. */
1928 subst_low_cuid = INSN_CUID (i2);
1929 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1930 ! i1_feeds_i3 && i1dest_in_i1src);
1931 undobuf.previous_undos = undobuf.undos;
1933 /* Record whether i2's body now appears within i3's body. */
1934 i2_is_used = n_occurrences;
1937 /* If we already got a failure, don't try to do more. Otherwise,
1938 try to substitute in I1 if we have it. */
1940 if (i1 && GET_CODE (newpat) != CLOBBER)
1942 /* Before we can do this substitution, we must redo the test done
1943 above (see detailed comments there) that ensures that I1DEST
1944 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1946 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1954 subst_low_cuid = INSN_CUID (i1);
1955 newpat = subst (newpat, i1dest, i1src, 0, 0);
1956 undobuf.previous_undos = undobuf.undos;
1959 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1960 to count all the ways that I2SRC and I1SRC can be used. */
1961 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
1962 && i2_is_used + added_sets_2 > 1)
1963 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
1964 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
1966 /* Fail if we tried to make a new register (we used to abort, but there's
1967 really no reason to). */
1968 || max_reg_num () != maxreg
1969 /* Fail if we couldn't do something and have a CLOBBER. */
1970 || GET_CODE (newpat) == CLOBBER
1971 /* Fail if this new pattern is a MULT and we didn't have one before
1972 at the outer level. */
1973 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
1980 /* If the actions of the earlier insns must be kept
1981 in addition to substituting them into the latest one,
1982 we must make a new PARALLEL for the latest insn
1983 to hold additional the SETs. */
1985 if (added_sets_1 || added_sets_2)
1989 if (GET_CODE (newpat) == PARALLEL)
1991 rtvec old = XVEC (newpat, 0);
1992 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
1993 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
1994 bcopy ((char *) &old->elem[0], (char *) XVEC (newpat, 0)->elem,
1995 sizeof (old->elem[0]) * old->num_elem);
2000 total_sets = 1 + added_sets_1 + added_sets_2;
2001 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2002 XVECEXP (newpat, 0, 0) = old;
2006 XVECEXP (newpat, 0, --total_sets)
2007 = (GET_CODE (PATTERN (i1)) == PARALLEL
2008 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
2012 /* If there is no I1, use I2's body as is. We used to also not do
2013 the subst call below if I2 was substituted into I3,
2014 but that could lose a simplification. */
2016 XVECEXP (newpat, 0, --total_sets) = i2pat;
2018 /* See comment where i2pat is assigned. */
2019 XVECEXP (newpat, 0, --total_sets)
2020 = subst (i2pat, i1dest, i1src, 0, 0);
2024 /* We come here when we are replacing a destination in I2 with the
2025 destination of I3. */
2026 validate_replacement:
2028 /* Note which hard regs this insn has as inputs. */
2029 mark_used_regs_combine (newpat);
2031 /* Is the result of combination a valid instruction? */
2032 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2034 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2035 the second SET's destination is a register that is unused. In that case,
2036 we just need the first SET. This can occur when simplifying a divmod
2037 insn. We *must* test for this case here because the code below that
2038 splits two independent SETs doesn't handle this case correctly when it
2039 updates the register status. Also check the case where the first
2040 SET's destination is unused. That would not cause incorrect code, but
2041 does cause an unneeded insn to remain. */
2043 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2044 && XVECLEN (newpat, 0) == 2
2045 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2046 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2047 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
2048 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
2049 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
2050 && asm_noperands (newpat) < 0)
2052 newpat = XVECEXP (newpat, 0, 0);
2053 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2056 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2057 && XVECLEN (newpat, 0) == 2
2058 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2059 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2060 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
2061 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
2062 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
2063 && asm_noperands (newpat) < 0)
2065 newpat = XVECEXP (newpat, 0, 1);
2066 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2069 /* If we were combining three insns and the result is a simple SET
2070 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2071 insns. There are two ways to do this. It can be split using a
2072 machine-specific method (like when you have an addition of a large
2073 constant) or by combine in the function find_split_point. */
2075 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2076 && asm_noperands (newpat) < 0)
2078 rtx m_split, *split;
2079 rtx ni2dest = i2dest;
2081 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2082 use I2DEST as a scratch register will help. In the latter case,
2083 convert I2DEST to the mode of the source of NEWPAT if we can. */
2085 m_split = split_insns (newpat, i3);
2087 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2088 inputs of NEWPAT. */
2090 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2091 possible to try that as a scratch reg. This would require adding
2092 more code to make it work though. */
2094 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
2096 /* If I2DEST is a hard register or the only use of a pseudo,
2097 we can change its mode. */
2098 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
2099 && GET_MODE (SET_DEST (newpat)) != VOIDmode
2100 && GET_CODE (i2dest) == REG
2101 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2102 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2103 && ! REG_USERVAR_P (i2dest))))
2104 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
2107 m_split = split_insns (gen_rtx_PARALLEL
2109 gen_rtvec (2, newpat,
2110 gen_rtx_CLOBBER (VOIDmode,
2115 if (m_split && GET_CODE (m_split) == SEQUENCE
2116 && XVECLEN (m_split, 0) == 2
2117 && (next_real_insn (i2) == i3
2118 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)),
2122 rtx newi3pat = PATTERN (XVECEXP (m_split, 0, 1));
2123 newi2pat = PATTERN (XVECEXP (m_split, 0, 0));
2125 i3set = single_set (XVECEXP (m_split, 0, 1));
2126 i2set = single_set (XVECEXP (m_split, 0, 0));
2128 /* In case we changed the mode of I2DEST, replace it in the
2129 pseudo-register table here. We can't do it above in case this
2130 code doesn't get executed and we do a split the other way. */
2132 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2133 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
2135 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2137 /* If I2 or I3 has multiple SETs, we won't know how to track
2138 register status, so don't use these insns. If I2's destination
2139 is used between I2 and I3, we also can't use these insns. */
2141 if (i2_code_number >= 0 && i2set && i3set
2142 && (next_real_insn (i2) == i3
2143 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2144 insn_code_number = recog_for_combine (&newi3pat, i3,
2146 if (insn_code_number >= 0)
2149 /* It is possible that both insns now set the destination of I3.
2150 If so, we must show an extra use of it. */
2152 if (insn_code_number >= 0)
2154 rtx new_i3_dest = SET_DEST (i3set);
2155 rtx new_i2_dest = SET_DEST (i2set);
2157 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2158 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2159 || GET_CODE (new_i3_dest) == SUBREG)
2160 new_i3_dest = XEXP (new_i3_dest, 0);
2162 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2163 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2164 || GET_CODE (new_i2_dest) == SUBREG)
2165 new_i2_dest = XEXP (new_i2_dest, 0);
2167 if (GET_CODE (new_i3_dest) == REG
2168 && GET_CODE (new_i2_dest) == REG
2169 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2170 REG_N_SETS (REGNO (new_i2_dest))++;
2174 /* If we can split it and use I2DEST, go ahead and see if that
2175 helps things be recognized. Verify that none of the registers
2176 are set between I2 and I3. */
2177 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2179 && GET_CODE (i2dest) == REG
2181 /* We need I2DEST in the proper mode. If it is a hard register
2182 or the only use of a pseudo, we can change its mode. */
2183 && (GET_MODE (*split) == GET_MODE (i2dest)
2184 || GET_MODE (*split) == VOIDmode
2185 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2186 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2187 && ! REG_USERVAR_P (i2dest)))
2188 && (next_real_insn (i2) == i3
2189 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2190 /* We can't overwrite I2DEST if its value is still used by
2192 && ! reg_referenced_p (i2dest, newpat))
2194 rtx newdest = i2dest;
2195 enum rtx_code split_code = GET_CODE (*split);
2196 enum machine_mode split_mode = GET_MODE (*split);
2198 /* Get NEWDEST as a register in the proper mode. We have already
2199 validated that we can do this. */
2200 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2202 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2204 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2205 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
2208 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2209 an ASHIFT. This can occur if it was inside a PLUS and hence
2210 appeared to be a memory address. This is a kludge. */
2211 if (split_code == MULT
2212 && GET_CODE (XEXP (*split, 1)) == CONST_INT
2213 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2215 SUBST (*split, gen_rtx_combine (ASHIFT, split_mode,
2216 XEXP (*split, 0), GEN_INT (i)));
2217 /* Update split_code because we may not have a multiply
2219 split_code = GET_CODE (*split);
2222 #ifdef INSN_SCHEDULING
2223 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2224 be written as a ZERO_EXTEND. */
2225 if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM)
2226 SUBST (*split, gen_rtx_combine (ZERO_EXTEND, split_mode,
2230 newi2pat = gen_rtx_combine (SET, VOIDmode, newdest, *split);
2231 SUBST (*split, newdest);
2232 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2234 /* If the split point was a MULT and we didn't have one before,
2235 don't use one now. */
2236 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2237 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2241 /* Check for a case where we loaded from memory in a narrow mode and
2242 then sign extended it, but we need both registers. In that case,
2243 we have a PARALLEL with both loads from the same memory location.
2244 We can split this into a load from memory followed by a register-register
2245 copy. This saves at least one insn, more if register allocation can
2248 We cannot do this if the destination of the second assignment is
2249 a register that we have already assumed is zero-extended. Similarly
2250 for a SUBREG of such a register. */
2252 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2253 && GET_CODE (newpat) == PARALLEL
2254 && XVECLEN (newpat, 0) == 2
2255 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2256 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2257 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2258 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2259 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2260 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2262 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2263 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2264 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2265 (GET_CODE (temp) == REG
2266 && reg_nonzero_bits[REGNO (temp)] != 0
2267 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2268 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2269 && (reg_nonzero_bits[REGNO (temp)]
2270 != GET_MODE_MASK (word_mode))))
2271 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2272 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2273 (GET_CODE (temp) == REG
2274 && reg_nonzero_bits[REGNO (temp)] != 0
2275 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2276 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2277 && (reg_nonzero_bits[REGNO (temp)]
2278 != GET_MODE_MASK (word_mode)))))
2279 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2280 SET_SRC (XVECEXP (newpat, 0, 1)))
2281 && ! find_reg_note (i3, REG_UNUSED,
2282 SET_DEST (XVECEXP (newpat, 0, 0))))
2286 newi2pat = XVECEXP (newpat, 0, 0);
2287 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2288 newpat = XVECEXP (newpat, 0, 1);
2289 SUBST (SET_SRC (newpat),
2290 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
2291 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2293 if (i2_code_number >= 0)
2294 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2296 if (insn_code_number >= 0)
2301 /* If we will be able to accept this, we have made a change to the
2302 destination of I3. This can invalidate a LOG_LINKS pointing
2303 to I3. No other part of combine.c makes such a transformation.
2305 The new I3 will have a destination that was previously the
2306 destination of I1 or I2 and which was used in i2 or I3. Call
2307 distribute_links to make a LOG_LINK from the next use of
2308 that destination. */
2310 PATTERN (i3) = newpat;
2311 distribute_links (gen_rtx_INSN_LIST (VOIDmode, i3, NULL_RTX));
2313 /* I3 now uses what used to be its destination and which is
2314 now I2's destination. That means we need a LOG_LINK from
2315 I3 to I2. But we used to have one, so we still will.
2317 However, some later insn might be using I2's dest and have
2318 a LOG_LINK pointing at I3. We must remove this link.
2319 The simplest way to remove the link is to point it at I1,
2320 which we know will be a NOTE. */
2322 for (insn = NEXT_INSN (i3);
2323 insn && (this_basic_block == n_basic_blocks - 1
2324 || insn != BLOCK_HEAD (this_basic_block + 1));
2325 insn = NEXT_INSN (insn))
2327 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
2328 && reg_referenced_p (ni2dest, PATTERN (insn)))
2330 for (link = LOG_LINKS (insn); link;
2331 link = XEXP (link, 1))
2332 if (XEXP (link, 0) == i3)
2333 XEXP (link, 0) = i1;
2341 /* Similarly, check for a case where we have a PARALLEL of two independent
2342 SETs but we started with three insns. In this case, we can do the sets
2343 as two separate insns. This case occurs when some SET allows two
2344 other insns to combine, but the destination of that SET is still live. */
2346 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2347 && GET_CODE (newpat) == PARALLEL
2348 && XVECLEN (newpat, 0) == 2
2349 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2350 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2351 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2352 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2353 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2354 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2355 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2357 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2358 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2359 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2360 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2361 XVECEXP (newpat, 0, 0))
2362 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2363 XVECEXP (newpat, 0, 1))
2364 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2365 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
2367 /* Normally, it doesn't matter which of the two is done first,
2368 but it does if one references cc0. In that case, it has to
2371 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2373 newi2pat = XVECEXP (newpat, 0, 0);
2374 newpat = XVECEXP (newpat, 0, 1);
2379 newi2pat = XVECEXP (newpat, 0, 1);
2380 newpat = XVECEXP (newpat, 0, 0);
2383 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2385 if (i2_code_number >= 0)
2386 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2389 /* If it still isn't recognized, fail and change things back the way they
2391 if ((insn_code_number < 0
2392 /* Is the result a reasonable ASM_OPERANDS? */
2393 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2399 /* If we had to change another insn, make sure it is valid also. */
2400 if (undobuf.other_insn)
2402 rtx other_pat = PATTERN (undobuf.other_insn);
2403 rtx new_other_notes;
2406 CLEAR_HARD_REG_SET (newpat_used_regs);
2408 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2411 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2417 PATTERN (undobuf.other_insn) = other_pat;
2419 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2420 are still valid. Then add any non-duplicate notes added by
2421 recog_for_combine. */
2422 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2424 next = XEXP (note, 1);
2426 if (REG_NOTE_KIND (note) == REG_UNUSED
2427 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2429 if (GET_CODE (XEXP (note, 0)) == REG)
2430 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2432 remove_note (undobuf.other_insn, note);
2436 for (note = new_other_notes; note; note = XEXP (note, 1))
2437 if (GET_CODE (XEXP (note, 0)) == REG)
2438 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2440 distribute_notes (new_other_notes, undobuf.other_insn,
2441 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2444 /* If I2 is the setter CC0 and I3 is the user CC0 then check whether
2445 they are adjacent to each other or not. */
2447 rtx p = prev_nonnote_insn (i3);
2448 if (p && p != i2 && GET_CODE (p) == INSN && newi2pat && sets_cc0_p (newi2pat))
2456 /* We now know that we can do this combination. Merge the insns and
2457 update the status of registers and LOG_LINKS. */
2460 rtx i3notes, i2notes, i1notes = 0;
2461 rtx i3links, i2links, i1links = 0;
2464 /* Compute which registers we expect to eliminate. newi2pat may be setting
2465 either i3dest or i2dest, so we must check it. Also, i1dest may be the
2466 same as i3dest, in which case newi2pat may be setting i1dest. */
2467 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
2468 || i2dest_in_i2src || i2dest_in_i1src
2470 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
2471 || (newi2pat && reg_set_p (i1dest, newi2pat))
2474 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2476 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2477 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2479 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2481 /* Ensure that we do not have something that should not be shared but
2482 occurs multiple times in the new insns. Check this by first
2483 resetting all the `used' flags and then copying anything is shared. */
2485 reset_used_flags (i3notes);
2486 reset_used_flags (i2notes);
2487 reset_used_flags (i1notes);
2488 reset_used_flags (newpat);
2489 reset_used_flags (newi2pat);
2490 if (undobuf.other_insn)
2491 reset_used_flags (PATTERN (undobuf.other_insn));
2493 i3notes = copy_rtx_if_shared (i3notes);
2494 i2notes = copy_rtx_if_shared (i2notes);
2495 i1notes = copy_rtx_if_shared (i1notes);
2496 newpat = copy_rtx_if_shared (newpat);
2497 newi2pat = copy_rtx_if_shared (newi2pat);
2498 if (undobuf.other_insn)
2499 reset_used_flags (PATTERN (undobuf.other_insn));
2501 INSN_CODE (i3) = insn_code_number;
2502 PATTERN (i3) = newpat;
2503 if (undobuf.other_insn)
2504 INSN_CODE (undobuf.other_insn) = other_code_number;
2506 /* We had one special case above where I2 had more than one set and
2507 we replaced a destination of one of those sets with the destination
2508 of I3. In that case, we have to update LOG_LINKS of insns later
2509 in this basic block. Note that this (expensive) case is rare.
2511 Also, in this case, we must pretend that all REG_NOTEs for I2
2512 actually came from I3, so that REG_UNUSED notes from I2 will be
2513 properly handled. */
2515 if (i3_subst_into_i2)
2517 if (GET_CODE (PATTERN (i2)) == PARALLEL)
2519 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2520 if (GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
2521 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2522 && ! find_reg_note (i2, REG_UNUSED,
2523 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2524 for (temp = NEXT_INSN (i2);
2525 temp && (this_basic_block == n_basic_blocks - 1
2526 || BLOCK_HEAD (this_basic_block) != temp);
2527 temp = NEXT_INSN (temp))
2528 if (temp != i3 && GET_RTX_CLASS (GET_CODE (temp)) == 'i')
2529 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2530 if (XEXP (link, 0) == i2)
2531 XEXP (link, 0) = i3;
2537 while (XEXP (link, 1))
2538 link = XEXP (link, 1);
2539 XEXP (link, 1) = i2notes;
2553 INSN_CODE (i2) = i2_code_number;
2554 PATTERN (i2) = newi2pat;
2558 PUT_CODE (i2, NOTE);
2559 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2560 NOTE_SOURCE_FILE (i2) = 0;
2567 PUT_CODE (i1, NOTE);
2568 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2569 NOTE_SOURCE_FILE (i1) = 0;
2572 /* Get death notes for everything that is now used in either I3 or
2573 I2 and used to die in a previous insn. If we built two new
2574 patterns, move from I1 to I2 then I2 to I3 so that we get the
2575 proper movement on registers that I2 modifies. */
2579 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2580 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2583 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2586 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2588 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
2591 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
2594 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
2597 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2600 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2601 know these are REG_UNUSED and want them to go to the desired insn,
2602 so we always pass it as i3. We have not counted the notes in
2603 reg_n_deaths yet, so we need to do so now. */
2605 if (newi2pat && new_i2_notes)
2607 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2608 if (GET_CODE (XEXP (temp, 0)) == REG)
2609 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2611 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2616 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2617 if (GET_CODE (XEXP (temp, 0)) == REG)
2618 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2620 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
2623 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2624 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2625 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2626 in that case, it might delete I2. Similarly for I2 and I1.
2627 Show an additional death due to the REG_DEAD note we make here. If
2628 we discard it in distribute_notes, we will decrement it again. */
2632 if (GET_CODE (i3dest_killed) == REG)
2633 REG_N_DEATHS (REGNO (i3dest_killed))++;
2635 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
2636 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2638 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
2640 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2642 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2646 if (i2dest_in_i2src)
2648 if (GET_CODE (i2dest) == REG)
2649 REG_N_DEATHS (REGNO (i2dest))++;
2651 if (newi2pat && reg_set_p (i2dest, newi2pat))
2652 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2653 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2655 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2656 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2657 NULL_RTX, NULL_RTX);
2660 if (i1dest_in_i1src)
2662 if (GET_CODE (i1dest) == REG)
2663 REG_N_DEATHS (REGNO (i1dest))++;
2665 if (newi2pat && reg_set_p (i1dest, newi2pat))
2666 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2667 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2669 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2670 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2671 NULL_RTX, NULL_RTX);
2674 distribute_links (i3links);
2675 distribute_links (i2links);
2676 distribute_links (i1links);
2678 if (GET_CODE (i2dest) == REG)
2681 rtx i2_insn = 0, i2_val = 0, set;
2683 /* The insn that used to set this register doesn't exist, and
2684 this life of the register may not exist either. See if one of
2685 I3's links points to an insn that sets I2DEST. If it does,
2686 that is now the last known value for I2DEST. If we don't update
2687 this and I2 set the register to a value that depended on its old
2688 contents, we will get confused. If this insn is used, thing
2689 will be set correctly in combine_instructions. */
2691 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2692 if ((set = single_set (XEXP (link, 0))) != 0
2693 && rtx_equal_p (i2dest, SET_DEST (set)))
2694 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2696 record_value_for_reg (i2dest, i2_insn, i2_val);
2698 /* If the reg formerly set in I2 died only once and that was in I3,
2699 zero its use count so it won't make `reload' do any work. */
2701 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2702 && ! i2dest_in_i2src)
2704 regno = REGNO (i2dest);
2705 REG_N_SETS (regno)--;
2709 if (i1 && GET_CODE (i1dest) == REG)
2712 rtx i1_insn = 0, i1_val = 0, set;
2714 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2715 if ((set = single_set (XEXP (link, 0))) != 0
2716 && rtx_equal_p (i1dest, SET_DEST (set)))
2717 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2719 record_value_for_reg (i1dest, i1_insn, i1_val);
2721 regno = REGNO (i1dest);
2722 if (! added_sets_1 && ! i1dest_in_i1src)
2723 REG_N_SETS (regno)--;
2726 /* Update reg_nonzero_bits et al for any changes that may have been made
2727 to this insn. The order of set_nonzero_bits_and_sign_copies() is
2728 important. Because newi2pat can affect nonzero_bits of newpat */
2730 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
2731 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
2733 /* Set new_direct_jump_p if a new return or simple jump instruction
2736 If I3 is now an unconditional jump, ensure that it has a
2737 BARRIER following it since it may have initially been a
2738 conditional jump. It may also be the last nonnote insn. */
2740 if (GET_CODE (newpat) == RETURN || simplejump_p (i3))
2742 *new_direct_jump_p = 1;
2744 if ((temp = next_nonnote_insn (i3)) == NULL_RTX
2745 || GET_CODE (temp) != BARRIER)
2746 emit_barrier_after (i3);
2750 combine_successes++;
2753 /* Clear this here, so that subsequent get_last_value calls are not
2755 subst_prev_insn = NULL_RTX;
2757 if (added_links_insn
2758 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2759 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2760 return added_links_insn;
2762 return newi2pat ? i2 : i3;
2765 /* Undo all the modifications recorded in undobuf. */
2770 struct undo *undo, *next;
2772 for (undo = undobuf.undos; undo; undo = next)
2776 *undo->where.i = undo->old_contents.i;
2778 *undo->where.r = undo->old_contents.r;
2780 undo->next = undobuf.frees;
2781 undobuf.frees = undo;
2784 obfree (undobuf.storage);
2785 undobuf.undos = undobuf.previous_undos = 0;
2787 /* Clear this here, so that subsequent get_last_value calls are not
2789 subst_prev_insn = NULL_RTX;
2792 /* We've committed to accepting the changes we made. Move all
2793 of the undos to the free list. */
2798 struct undo *undo, *next;
2800 for (undo = undobuf.undos; undo; undo = next)
2803 undo->next = undobuf.frees;
2804 undobuf.frees = undo;
2806 undobuf.undos = undobuf.previous_undos = 0;
2810 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2811 where we have an arithmetic expression and return that point. LOC will
2814 try_combine will call this function to see if an insn can be split into
2818 find_split_point (loc, insn)
2823 enum rtx_code code = GET_CODE (x);
2825 unsigned HOST_WIDE_INT len = 0;
2826 HOST_WIDE_INT pos = 0;
2828 rtx inner = NULL_RTX;
2830 /* First special-case some codes. */
2834 #ifdef INSN_SCHEDULING
2835 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2837 if (GET_CODE (SUBREG_REG (x)) == MEM)
2840 return find_split_point (&SUBREG_REG (x), insn);
2844 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2845 using LO_SUM and HIGH. */
2846 if (GET_CODE (XEXP (x, 0)) == CONST
2847 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2850 gen_rtx_combine (LO_SUM, Pmode,
2851 gen_rtx_combine (HIGH, Pmode, XEXP (x, 0)),
2853 return &XEXP (XEXP (x, 0), 0);
2857 /* If we have a PLUS whose second operand is a constant and the
2858 address is not valid, perhaps will can split it up using
2859 the machine-specific way to split large constants. We use
2860 the first pseudo-reg (one of the virtual regs) as a placeholder;
2861 it will not remain in the result. */
2862 if (GET_CODE (XEXP (x, 0)) == PLUS
2863 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2864 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2866 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2867 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
2870 /* This should have produced two insns, each of which sets our
2871 placeholder. If the source of the second is a valid address,
2872 we can make put both sources together and make a split point
2875 if (seq && XVECLEN (seq, 0) == 2
2876 && GET_CODE (XVECEXP (seq, 0, 0)) == INSN
2877 && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET
2878 && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg
2879 && ! reg_mentioned_p (reg,
2880 SET_SRC (PATTERN (XVECEXP (seq, 0, 0))))
2881 && GET_CODE (XVECEXP (seq, 0, 1)) == INSN
2882 && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET
2883 && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg
2884 && memory_address_p (GET_MODE (x),
2885 SET_SRC (PATTERN (XVECEXP (seq, 0, 1)))))
2887 rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0)));
2888 rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1)));
2890 /* Replace the placeholder in SRC2 with SRC1. If we can
2891 find where in SRC2 it was placed, that can become our
2892 split point and we can replace this address with SRC2.
2893 Just try two obvious places. */
2895 src2 = replace_rtx (src2, reg, src1);
2897 if (XEXP (src2, 0) == src1)
2898 split = &XEXP (src2, 0);
2899 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2900 && XEXP (XEXP (src2, 0), 0) == src1)
2901 split = &XEXP (XEXP (src2, 0), 0);
2905 SUBST (XEXP (x, 0), src2);
2910 /* If that didn't work, perhaps the first operand is complex and
2911 needs to be computed separately, so make a split point there.
2912 This will occur on machines that just support REG + CONST
2913 and have a constant moved through some previous computation. */
2915 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
2916 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
2917 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
2919 return &XEXP (XEXP (x, 0), 0);
2925 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2926 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2927 we need to put the operand into a register. So split at that
2930 if (SET_DEST (x) == cc0_rtx
2931 && GET_CODE (SET_SRC (x)) != COMPARE
2932 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
2933 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
2934 && ! (GET_CODE (SET_SRC (x)) == SUBREG
2935 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
2936 return &SET_SRC (x);
2939 /* See if we can split SET_SRC as it stands. */
2940 split = find_split_point (&SET_SRC (x), insn);
2941 if (split && split != &SET_SRC (x))
2944 /* See if we can split SET_DEST as it stands. */
2945 split = find_split_point (&SET_DEST (x), insn);
2946 if (split && split != &SET_DEST (x))
2949 /* See if this is a bitfield assignment with everything constant. If
2950 so, this is an IOR of an AND, so split it into that. */
2951 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
2952 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
2953 <= HOST_BITS_PER_WIDE_INT)
2954 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
2955 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
2956 && GET_CODE (SET_SRC (x)) == CONST_INT
2957 && ((INTVAL (XEXP (SET_DEST (x), 1))
2958 + INTVAL (XEXP (SET_DEST (x), 2)))
2959 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
2960 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
2962 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
2963 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
2964 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
2965 rtx dest = XEXP (SET_DEST (x), 0);
2966 enum machine_mode mode = GET_MODE (dest);
2967 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
2969 if (BITS_BIG_ENDIAN)
2970 pos = GET_MODE_BITSIZE (mode) - len - pos;
2974 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
2977 gen_binary (IOR, mode,
2978 gen_binary (AND, mode, dest,
2979 GEN_INT (~ (mask << pos)
2980 & GET_MODE_MASK (mode))),
2981 GEN_INT (src << pos)));
2983 SUBST (SET_DEST (x), dest);
2985 split = find_split_point (&SET_SRC (x), insn);
2986 if (split && split != &SET_SRC (x))
2990 /* Otherwise, see if this is an operation that we can split into two.
2991 If so, try to split that. */
2992 code = GET_CODE (SET_SRC (x));
2997 /* If we are AND'ing with a large constant that is only a single
2998 bit and the result is only being used in a context where we
2999 need to know if it is zero or non-zero, replace it with a bit
3000 extraction. This will avoid the large constant, which might
3001 have taken more than one insn to make. If the constant were
3002 not a valid argument to the AND but took only one insn to make,
3003 this is no worse, but if it took more than one insn, it will
3006 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3007 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
3008 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
3009 && GET_CODE (SET_DEST (x)) == REG
3010 && (split = find_single_use (SET_DEST (x), insn, NULL_PTR)) != 0
3011 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
3012 && XEXP (*split, 0) == SET_DEST (x)
3013 && XEXP (*split, 1) == const0_rtx)
3015 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
3016 XEXP (SET_SRC (x), 0),
3017 pos, NULL_RTX, 1, 1, 0, 0);
3018 if (extraction != 0)
3020 SUBST (SET_SRC (x), extraction);
3021 return find_split_point (loc, insn);
3027 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3028 is known to be on, this can be converted into a NEG of a shift. */
3029 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
3030 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
3031 && 1 <= (pos = exact_log2
3032 (nonzero_bits (XEXP (SET_SRC (x), 0),
3033 GET_MODE (XEXP (SET_SRC (x), 0))))))
3035 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
3038 gen_rtx_combine (NEG, mode,
3039 gen_rtx_combine (LSHIFTRT, mode,
3040 XEXP (SET_SRC (x), 0),
3043 split = find_split_point (&SET_SRC (x), insn);
3044 if (split && split != &SET_SRC (x))
3050 inner = XEXP (SET_SRC (x), 0);
3052 /* We can't optimize if either mode is a partial integer
3053 mode as we don't know how many bits are significant
3055 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3056 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3060 len = GET_MODE_BITSIZE (GET_MODE (inner));
3066 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3067 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3069 inner = XEXP (SET_SRC (x), 0);
3070 len = INTVAL (XEXP (SET_SRC (x), 1));
3071 pos = INTVAL (XEXP (SET_SRC (x), 2));
3073 if (BITS_BIG_ENDIAN)
3074 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3075 unsignedp = (code == ZERO_EXTRACT);
3083 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3085 enum machine_mode mode = GET_MODE (SET_SRC (x));
3087 /* For unsigned, we have a choice of a shift followed by an
3088 AND or two shifts. Use two shifts for field sizes where the
3089 constant might be too large. We assume here that we can
3090 always at least get 8-bit constants in an AND insn, which is
3091 true for every current RISC. */
3093 if (unsignedp && len <= 8)
3098 gen_rtx_combine (LSHIFTRT, mode,
3099 gen_lowpart_for_combine (mode, inner),
3101 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3103 split = find_split_point (&SET_SRC (x), insn);
3104 if (split && split != &SET_SRC (x))
3111 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3112 gen_rtx_combine (ASHIFT, mode,
3113 gen_lowpart_for_combine (mode, inner),
3114 GEN_INT (GET_MODE_BITSIZE (mode)
3116 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3118 split = find_split_point (&SET_SRC (x), insn);
3119 if (split && split != &SET_SRC (x))
3124 /* See if this is a simple operation with a constant as the second
3125 operand. It might be that this constant is out of range and hence
3126 could be used as a split point. */
3127 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3128 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3129 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
3130 && CONSTANT_P (XEXP (SET_SRC (x), 1))
3131 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
3132 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3133 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
3135 return &XEXP (SET_SRC (x), 1);
3137 /* Finally, see if this is a simple operation with its first operand
3138 not in a register. The operation might require this operand in a
3139 register, so return it as a split point. We can always do this
3140 because if the first operand were another operation, we would have
3141 already found it as a split point. */
3142 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3143 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3144 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
3145 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
3146 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3147 return &XEXP (SET_SRC (x), 0);
3153 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3154 it is better to write this as (not (ior A B)) so we can split it.
3155 Similarly for IOR. */
3156 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3159 gen_rtx_combine (NOT, GET_MODE (x),
3160 gen_rtx_combine (code == IOR ? AND : IOR,
3162 XEXP (XEXP (x, 0), 0),
3163 XEXP (XEXP (x, 1), 0))));
3164 return find_split_point (loc, insn);
3167 /* Many RISC machines have a large set of logical insns. If the
3168 second operand is a NOT, put it first so we will try to split the
3169 other operand first. */
3170 if (GET_CODE (XEXP (x, 1)) == NOT)
3172 rtx tem = XEXP (x, 0);
3173 SUBST (XEXP (x, 0), XEXP (x, 1));
3174 SUBST (XEXP (x, 1), tem);
3182 /* Otherwise, select our actions depending on our rtx class. */
3183 switch (GET_RTX_CLASS (code))
3185 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3187 split = find_split_point (&XEXP (x, 2), insn);
3190 /* ... fall through ... */
3194 split = find_split_point (&XEXP (x, 1), insn);
3197 /* ... fall through ... */
3199 /* Some machines have (and (shift ...) ...) insns. If X is not
3200 an AND, but XEXP (X, 0) is, use it as our split point. */
3201 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3202 return &XEXP (x, 0);
3204 split = find_split_point (&XEXP (x, 0), insn);
3210 /* Otherwise, we don't have a split point. */
3214 /* Throughout X, replace FROM with TO, and return the result.
3215 The result is TO if X is FROM;
3216 otherwise the result is X, but its contents may have been modified.
3217 If they were modified, a record was made in undobuf so that
3218 undo_all will (among other things) return X to its original state.
3220 If the number of changes necessary is too much to record to undo,
3221 the excess changes are not made, so the result is invalid.
3222 The changes already made can still be undone.
3223 undobuf.num_undo is incremented for such changes, so by testing that
3224 the caller can tell whether the result is valid.
3226 `n_occurrences' is incremented each time FROM is replaced.
3228 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
3230 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
3231 by copying if `n_occurrences' is non-zero. */
3234 subst (x, from, to, in_dest, unique_copy)
3235 register rtx x, from, to;
3239 register enum rtx_code code = GET_CODE (x);
3240 enum machine_mode op0_mode = VOIDmode;
3241 register const char *fmt;
3242 register int len, i;
3245 /* Two expressions are equal if they are identical copies of a shared
3246 RTX or if they are both registers with the same register number
3249 #define COMBINE_RTX_EQUAL_P(X,Y) \
3251 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3252 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3254 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3257 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3260 /* If X and FROM are the same register but different modes, they will
3261 not have been seen as equal above. However, flow.c will make a
3262 LOG_LINKS entry for that case. If we do nothing, we will try to
3263 rerecognize our original insn and, when it succeeds, we will
3264 delete the feeding insn, which is incorrect.
3266 So force this insn not to match in this (rare) case. */
3267 if (! in_dest && code == REG && GET_CODE (from) == REG
3268 && REGNO (x) == REGNO (from))
3269 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3271 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3272 of which may contain things that can be combined. */
3273 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
3276 /* It is possible to have a subexpression appear twice in the insn.
3277 Suppose that FROM is a register that appears within TO.
3278 Then, after that subexpression has been scanned once by `subst',
3279 the second time it is scanned, TO may be found. If we were
3280 to scan TO here, we would find FROM within it and create a
3281 self-referent rtl structure which is completely wrong. */
3282 if (COMBINE_RTX_EQUAL_P (x, to))
3285 /* Parallel asm_operands need special attention because all of the
3286 inputs are shared across the arms. Furthermore, unsharing the
3287 rtl results in recognition failures. Failure to handle this case
3288 specially can result in circular rtl.
3290 Solve this by doing a normal pass across the first entry of the
3291 parallel, and only processing the SET_DESTs of the subsequent
3294 if (code == PARALLEL
3295 && GET_CODE (XVECEXP (x, 0, 0)) == SET
3296 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3298 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3300 /* If this substitution failed, this whole thing fails. */
3301 if (GET_CODE (new) == CLOBBER
3302 && XEXP (new, 0) == const0_rtx)
3305 SUBST (XVECEXP (x, 0, 0), new);
3307 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3309 rtx dest = SET_DEST (XVECEXP (x, 0, i));
3311 if (GET_CODE (dest) != REG
3312 && GET_CODE (dest) != CC0
3313 && GET_CODE (dest) != PC)
3315 new = subst (dest, from, to, 0, unique_copy);
3317 /* If this substitution failed, this whole thing fails. */
3318 if (GET_CODE (new) == CLOBBER
3319 && XEXP (new, 0) == const0_rtx)
3322 SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3328 len = GET_RTX_LENGTH (code);
3329 fmt = GET_RTX_FORMAT (code);
3331 /* We don't need to process a SET_DEST that is a register, CC0,
3332 or PC, so set up to skip this common case. All other cases
3333 where we want to suppress replacing something inside a
3334 SET_SRC are handled via the IN_DEST operand. */
3336 && (GET_CODE (SET_DEST (x)) == REG
3337 || GET_CODE (SET_DEST (x)) == CC0
3338 || GET_CODE (SET_DEST (x)) == PC))
3341 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3344 op0_mode = GET_MODE (XEXP (x, 0));
3346 for (i = 0; i < len; i++)
3351 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3353 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3355 new = (unique_copy && n_occurrences
3356 ? copy_rtx (to) : to);
3361 new = subst (XVECEXP (x, i, j), from, to, 0,
3364 /* If this substitution failed, this whole thing
3366 if (GET_CODE (new) == CLOBBER
3367 && XEXP (new, 0) == const0_rtx)
3371 SUBST (XVECEXP (x, i, j), new);
3374 else if (fmt[i] == 'e')
3376 if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3378 /* In general, don't install a subreg involving two
3379 modes not tieable. It can worsen register
3380 allocation, and can even make invalid reload
3381 insns, since the reg inside may need to be copied
3382 from in the outside mode, and that may be invalid
3383 if it is an fp reg copied in integer mode.
3385 We allow two exceptions to this: It is valid if
3386 it is inside another SUBREG and the mode of that
3387 SUBREG and the mode of the inside of TO is
3388 tieable and it is valid if X is a SET that copies
3391 if (GET_CODE (to) == SUBREG
3392 && ! MODES_TIEABLE_P (GET_MODE (to),
3393 GET_MODE (SUBREG_REG (to)))
3394 && ! (code == SUBREG
3395 && MODES_TIEABLE_P (GET_MODE (x),
3396 GET_MODE (SUBREG_REG (to))))
3398 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3401 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3403 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3407 /* If we are in a SET_DEST, suppress most cases unless we
3408 have gone inside a MEM, in which case we want to
3409 simplify the address. We assume here that things that
3410 are actually part of the destination have their inner
3411 parts in the first expression. This is true for SUBREG,
3412 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3413 things aside from REG and MEM that should appear in a
3415 new = subst (XEXP (x, i), from, to,
3417 && (code == SUBREG || code == STRICT_LOW_PART
3418 || code == ZERO_EXTRACT))
3420 && i == 0), unique_copy);
3422 /* If we found that we will have to reject this combination,
3423 indicate that by returning the CLOBBER ourselves, rather than
3424 an expression containing it. This will speed things up as
3425 well as prevent accidents where two CLOBBERs are considered
3426 to be equal, thus producing an incorrect simplification. */
3428 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3431 SUBST (XEXP (x, i), new);
3436 /* Try to simplify X. If the simplification changed the code, it is likely
3437 that further simplification will help, so loop, but limit the number
3438 of repetitions that will be performed. */
3440 for (i = 0; i < 4; i++)
3442 /* If X is sufficiently simple, don't bother trying to do anything
3444 if (code != CONST_INT && code != REG && code != CLOBBER)
3445 x = combine_simplify_rtx (x, op0_mode, i == 3, in_dest);
3447 if (GET_CODE (x) == code)
3450 code = GET_CODE (x);
3452 /* We no longer know the original mode of operand 0 since we
3453 have changed the form of X) */
3454 op0_mode = VOIDmode;
3460 /* Simplify X, a piece of RTL. We just operate on the expression at the
3461 outer level; call `subst' to simplify recursively. Return the new
3464 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3465 will be the iteration even if an expression with a code different from
3466 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3469 combine_simplify_rtx (x, op0_mode, last, in_dest)
3471 enum machine_mode op0_mode;
3475 enum rtx_code code = GET_CODE (x);
3476 enum machine_mode mode = GET_MODE (x);
3480 /* If this is a commutative operation, put a constant last and a complex
3481 expression first. We don't need to do this for comparisons here. */
3482 if (GET_RTX_CLASS (code) == 'c'
3483 && ((CONSTANT_P (XEXP (x, 0)) && GET_CODE (XEXP (x, 1)) != CONST_INT)
3484 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == 'o'
3485 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')
3486 || (GET_CODE (XEXP (x, 0)) == SUBREG
3487 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o'
3488 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')))
3491 SUBST (XEXP (x, 0), XEXP (x, 1));
3492 SUBST (XEXP (x, 1), temp);
3495 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3496 sign extension of a PLUS with a constant, reverse the order of the sign
3497 extension and the addition. Note that this not the same as the original
3498 code, but overflow is undefined for signed values. Also note that the
3499 PLUS will have been partially moved "inside" the sign-extension, so that
3500 the first operand of X will really look like:
3501 (ashiftrt (plus (ashift A C4) C5) C4).
3503 (plus (ashiftrt (ashift A C4) C2) C4)
3504 and replace the first operand of X with that expression. Later parts
3505 of this function may simplify the expression further.
3507 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3508 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3509 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3511 We do this to simplify address expressions. */
3513 if ((code == PLUS || code == MINUS || code == MULT)
3514 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3515 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3516 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3517 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3518 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3519 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3520 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3521 && (temp = simplify_binary_operation (ASHIFTRT, mode,
3522 XEXP (XEXP (XEXP (x, 0), 0), 1),
3523 XEXP (XEXP (x, 0), 1))) != 0)
3526 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3527 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3528 INTVAL (XEXP (XEXP (x, 0), 1)));
3530 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3531 INTVAL (XEXP (XEXP (x, 0), 1)));
3533 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3536 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3537 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3538 things. Check for cases where both arms are testing the same
3541 Don't do anything if all operands are very simple. */
3543 if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c'
3544 || GET_RTX_CLASS (code) == '<')
3545 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3546 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3547 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3549 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'
3550 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3551 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1))))
3553 || (GET_RTX_CLASS (code) == '1'
3554 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3555 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3556 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3559 rtx cond, true, false;
3561 cond = if_then_else_cond (x, &true, &false);
3563 /* If everything is a comparison, what we have is highly unlikely
3564 to be simpler, so don't use it. */
3565 && ! (GET_RTX_CLASS (code) == '<'
3566 && (GET_RTX_CLASS (GET_CODE (true)) == '<'
3567 || GET_RTX_CLASS (GET_CODE (false)) == '<')))
3569 rtx cop1 = const0_rtx;
3570 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3572 if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<')
3575 /* Simplify the alternative arms; this may collapse the true and
3576 false arms to store-flag values. */
3577 true = subst (true, pc_rtx, pc_rtx, 0, 0);
3578 false = subst (false, pc_rtx, pc_rtx, 0, 0);
3580 /* Restarting if we generate a store-flag expression will cause
3581 us to loop. Just drop through in this case. */
3583 /* If the result values are STORE_FLAG_VALUE and zero, we can
3584 just make the comparison operation. */
3585 if (true == const_true_rtx && false == const0_rtx)
3586 x = gen_binary (cond_code, mode, cond, cop1);
3587 else if (true == const0_rtx && false == const_true_rtx)
3588 x = gen_binary (reverse_condition (cond_code), mode, cond, cop1);
3590 /* Likewise, we can make the negate of a comparison operation
3591 if the result values are - STORE_FLAG_VALUE and zero. */
3592 else if (GET_CODE (true) == CONST_INT
3593 && INTVAL (true) == - STORE_FLAG_VALUE
3594 && false == const0_rtx)
3595 x = gen_unary (NEG, mode, mode,
3596 gen_binary (cond_code, mode, cond, cop1));
3597 else if (GET_CODE (false) == CONST_INT
3598 && INTVAL (false) == - STORE_FLAG_VALUE
3599 && true == const0_rtx)
3600 x = gen_unary (NEG, mode, mode,
3601 gen_binary (reverse_condition (cond_code),
3604 return gen_rtx_IF_THEN_ELSE (mode,
3605 gen_binary (cond_code, VOIDmode,
3609 code = GET_CODE (x);
3610 op0_mode = VOIDmode;
3614 /* Try to fold this expression in case we have constants that weren't
3617 switch (GET_RTX_CLASS (code))
3620 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3623 temp = simplify_relational_operation (code, op0_mode,
3624 XEXP (x, 0), XEXP (x, 1));
3625 #ifdef FLOAT_STORE_FLAG_VALUE
3626 if (temp != 0 && GET_MODE_CLASS (mode) == MODE_FLOAT)
3628 if (temp == const0_rtx)
3629 temp = CONST0_RTX (mode);
3631 temp = immed_real_const_1 (FLOAT_STORE_FLAG_VALUE (mode), mode);
3637 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3641 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3642 XEXP (x, 1), XEXP (x, 2));
3647 x = temp, code = GET_CODE (temp);
3649 /* First see if we can apply the inverse distributive law. */
3650 if (code == PLUS || code == MINUS
3651 || code == AND || code == IOR || code == XOR)
3653 x = apply_distributive_law (x);
3654 code = GET_CODE (x);
3657 /* If CODE is an associative operation not otherwise handled, see if we
3658 can associate some operands. This can win if they are constants or
3659 if they are logically related (i.e. (a & b) & a. */
3660 if ((code == PLUS || code == MINUS
3661 || code == MULT || code == AND || code == IOR || code == XOR
3662 || code == DIV || code == UDIV
3663 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3664 && INTEGRAL_MODE_P (mode))
3666 if (GET_CODE (XEXP (x, 0)) == code)
3668 rtx other = XEXP (XEXP (x, 0), 0);
3669 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3670 rtx inner_op1 = XEXP (x, 1);
3673 /* Make sure we pass the constant operand if any as the second
3674 one if this is a commutative operation. */
3675 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
3677 rtx tem = inner_op0;
3678 inner_op0 = inner_op1;
3681 inner = simplify_binary_operation (code == MINUS ? PLUS
3682 : code == DIV ? MULT
3683 : code == UDIV ? MULT
3685 mode, inner_op0, inner_op1);
3687 /* For commutative operations, try the other pair if that one
3689 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
3691 other = XEXP (XEXP (x, 0), 1);
3692 inner = simplify_binary_operation (code, mode,
3693 XEXP (XEXP (x, 0), 0),
3698 return gen_binary (code, mode, other, inner);
3702 /* A little bit of algebraic simplification here. */
3706 /* Ensure that our address has any ASHIFTs converted to MULT in case
3707 address-recognizing predicates are called later. */
3708 temp = make_compound_operation (XEXP (x, 0), MEM);
3709 SUBST (XEXP (x, 0), temp);
3713 /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG
3714 is paradoxical. If we can't do that safely, then it becomes
3715 something nonsensical so that this combination won't take place. */
3717 if (GET_CODE (SUBREG_REG (x)) == MEM
3718 && (GET_MODE_SIZE (mode)
3719 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
3721 rtx inner = SUBREG_REG (x);
3722 int endian_offset = 0;
3723 /* Don't change the mode of the MEM
3724 if that would change the meaning of the address. */
3725 if (MEM_VOLATILE_P (SUBREG_REG (x))
3726 || mode_dependent_address_p (XEXP (inner, 0)))
3727 return gen_rtx_CLOBBER (mode, const0_rtx);
3729 if (BYTES_BIG_ENDIAN)
3731 if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
3732 endian_offset += UNITS_PER_WORD - GET_MODE_SIZE (mode);
3733 if (GET_MODE_SIZE (GET_MODE (inner)) < UNITS_PER_WORD)
3734 endian_offset -= (UNITS_PER_WORD
3735 - GET_MODE_SIZE (GET_MODE (inner)));
3737 /* Note if the plus_constant doesn't make a valid address
3738 then this combination won't be accepted. */
3739 x = gen_rtx_MEM (mode,
3740 plus_constant (XEXP (inner, 0),
3741 (SUBREG_WORD (x) * UNITS_PER_WORD
3743 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (inner);
3744 MEM_COPY_ATTRIBUTES (x, inner);
3748 /* If we are in a SET_DEST, these other cases can't apply. */
3752 /* Changing mode twice with SUBREG => just change it once,
3753 or not at all if changing back to starting mode. */
3754 if (GET_CODE (SUBREG_REG (x)) == SUBREG)
3756 if (mode == GET_MODE (SUBREG_REG (SUBREG_REG (x)))
3757 && SUBREG_WORD (x) == 0 && SUBREG_WORD (SUBREG_REG (x)) == 0)
3758 return SUBREG_REG (SUBREG_REG (x));
3760 SUBST_INT (SUBREG_WORD (x),
3761 SUBREG_WORD (x) + SUBREG_WORD (SUBREG_REG (x)));
3762 SUBST (SUBREG_REG (x), SUBREG_REG (SUBREG_REG (x)));
3765 /* SUBREG of a hard register => just change the register number
3766 and/or mode. If the hard register is not valid in that mode,
3767 suppress this combination. If the hard register is the stack,
3768 frame, or argument pointer, leave this as a SUBREG. */
3770 if (GET_CODE (SUBREG_REG (x)) == REG
3771 && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER
3772 && REGNO (SUBREG_REG (x)) != FRAME_POINTER_REGNUM
3773 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3774 && REGNO (SUBREG_REG (x)) != HARD_FRAME_POINTER_REGNUM
3776 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3777 && REGNO (SUBREG_REG (x)) != ARG_POINTER_REGNUM
3779 && REGNO (SUBREG_REG (x)) != STACK_POINTER_REGNUM)
3781 if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x)) + SUBREG_WORD (x),
3783 return gen_rtx_REG (mode,
3784 REGNO (SUBREG_REG (x)) + SUBREG_WORD (x));
3786 return gen_rtx_CLOBBER (mode, const0_rtx);
3789 /* For a constant, try to pick up the part we want. Handle a full
3790 word and low-order part. Only do this if we are narrowing
3791 the constant; if it is being widened, we have no idea what
3792 the extra bits will have been set to. */
3794 if (CONSTANT_P (SUBREG_REG (x)) && op0_mode != VOIDmode
3795 && GET_MODE_SIZE (mode) == UNITS_PER_WORD
3796 && GET_MODE_SIZE (op0_mode) > UNITS_PER_WORD
3797 && GET_MODE_CLASS (mode) == MODE_INT)
3799 temp = operand_subword (SUBREG_REG (x), SUBREG_WORD (x),
3805 /* If we want a subreg of a constant, at offset 0,
3806 take the low bits. On a little-endian machine, that's
3807 always valid. On a big-endian machine, it's valid
3808 only if the constant's mode fits in one word. Note that we
3809 cannot use subreg_lowpart_p since SUBREG_REG may be VOIDmode. */
3810 if (CONSTANT_P (SUBREG_REG (x))
3811 && ((GET_MODE_SIZE (op0_mode) <= UNITS_PER_WORD
3812 || ! WORDS_BIG_ENDIAN)
3813 ? SUBREG_WORD (x) == 0
3815 == ((GET_MODE_SIZE (op0_mode)
3816 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
3818 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (op0_mode)
3819 && (! WORDS_BIG_ENDIAN
3820 || GET_MODE_BITSIZE (op0_mode) <= BITS_PER_WORD))
3821 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3823 /* A paradoxical SUBREG of a VOIDmode constant is the same constant,
3824 since we are saying that the high bits don't matter. */
3825 if (CONSTANT_P (SUBREG_REG (x)) && GET_MODE (SUBREG_REG (x)) == VOIDmode
3826 && GET_MODE_SIZE (mode) > GET_MODE_SIZE (op0_mode))
3828 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))) > UNITS_PER_WORD
3829 && (WORDS_BIG_ENDIAN || SUBREG_WORD (x) != 0))
3830 return operand_subword (SUBREG_REG (x), SUBREG_WORD (x), 0, mode);
3831 return SUBREG_REG (x);
3834 /* Note that we cannot do any narrowing for non-constants since
3835 we might have been counting on using the fact that some bits were
3836 zero. We now do this in the SET. */
3841 /* (not (plus X -1)) can become (neg X). */
3842 if (GET_CODE (XEXP (x, 0)) == PLUS
3843 && XEXP (XEXP (x, 0), 1) == constm1_rtx)
3844 return gen_rtx_combine (NEG, mode, XEXP (XEXP (x, 0), 0));
3846 /* Similarly, (not (neg X)) is (plus X -1). */
3847 if (GET_CODE (XEXP (x, 0)) == NEG)
3848 return gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0),
3851 /* (not (xor X C)) for C constant is (xor X D) with D = ~ C. */
3852 if (GET_CODE (XEXP (x, 0)) == XOR
3853 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3854 && (temp = simplify_unary_operation (NOT, mode,
3855 XEXP (XEXP (x, 0), 1),
3857 return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp);
3859 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3860 other than 1, but that is not valid. We could do a similar
3861 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3862 but this doesn't seem common enough to bother with. */
3863 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3864 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3865 return gen_rtx_ROTATE (mode, gen_unary (NOT, mode, mode, const1_rtx),
3866 XEXP (XEXP (x, 0), 1));
3868 if (GET_CODE (XEXP (x, 0)) == SUBREG
3869 && subreg_lowpart_p (XEXP (x, 0))
3870 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3871 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3872 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3873 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3875 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3877 x = gen_rtx_ROTATE (inner_mode,
3878 gen_unary (NOT, inner_mode, inner_mode,
3880 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3881 return gen_lowpart_for_combine (mode, x);
3884 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3885 reversing the comparison code if valid. */
3886 if (STORE_FLAG_VALUE == -1
3887 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3888 && reversible_comparison_p (XEXP (x, 0)))
3889 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
3890 mode, XEXP (XEXP (x, 0), 0),
3891 XEXP (XEXP (x, 0), 1));
3893 /* (ashiftrt foo C) where C is the number of bits in FOO minus 1
3894 is (lt foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3895 perform the above simplification. */
3897 if (STORE_FLAG_VALUE == -1
3898 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3899 && XEXP (x, 1) == const1_rtx
3900 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3901 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3902 return gen_rtx_combine (GE, mode, XEXP (XEXP (x, 0), 0), const0_rtx);
3904 /* Apply De Morgan's laws to reduce number of patterns for machines
3905 with negating logical insns (and-not, nand, etc.). If result has
3906 only one NOT, put it first, since that is how the patterns are
3909 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3911 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3913 if (GET_CODE (in1) == NOT)
3914 in1 = XEXP (in1, 0);
3916 in1 = gen_rtx_combine (NOT, GET_MODE (in1), in1);
3918 if (GET_CODE (in2) == NOT)
3919 in2 = XEXP (in2, 0);
3920 else if (GET_CODE (in2) == CONST_INT
3921 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3922 in2 = GEN_INT (GET_MODE_MASK (mode) & ~ INTVAL (in2));
3924 in2 = gen_rtx_combine (NOT, GET_MODE (in2), in2);
3926 if (GET_CODE (in2) == NOT)
3929 in2 = in1; in1 = tem;
3932 return gen_rtx_combine (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3938 /* (neg (plus X 1)) can become (not X). */
3939 if (GET_CODE (XEXP (x, 0)) == PLUS
3940 && XEXP (XEXP (x, 0), 1) == const1_rtx)
3941 return gen_rtx_combine (NOT, mode, XEXP (XEXP (x, 0), 0));
3943 /* Similarly, (neg (not X)) is (plus X 1). */
3944 if (GET_CODE (XEXP (x, 0)) == NOT)
3945 return plus_constant (XEXP (XEXP (x, 0), 0), 1);
3947 /* (neg (minus X Y)) can become (minus Y X). */
3948 if (GET_CODE (XEXP (x, 0)) == MINUS
3949 && (! FLOAT_MODE_P (mode)
3950 /* x-y != -(y-x) with IEEE floating point. */
3951 || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3953 return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
3954 XEXP (XEXP (x, 0), 0));
3956 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3957 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
3958 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
3959 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3961 /* NEG commutes with ASHIFT since it is multiplication. Only do this
3962 if we can then eliminate the NEG (e.g.,
3963 if the operand is a constant). */
3965 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
3967 temp = simplify_unary_operation (NEG, mode,
3968 XEXP (XEXP (x, 0), 0), mode);
3971 SUBST (XEXP (XEXP (x, 0), 0), temp);
3976 temp = expand_compound_operation (XEXP (x, 0));
3978 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3979 replaced by (lshiftrt X C). This will convert
3980 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3982 if (GET_CODE (temp) == ASHIFTRT
3983 && GET_CODE (XEXP (temp, 1)) == CONST_INT
3984 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
3985 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
3986 INTVAL (XEXP (temp, 1)));
3988 /* If X has only a single bit that might be nonzero, say, bit I, convert
3989 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3990 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
3991 (sign_extract X 1 Y). But only do this if TEMP isn't a register
3992 or a SUBREG of one since we'd be making the expression more
3993 complex if it was just a register. */
3995 if (GET_CODE (temp) != REG
3996 && ! (GET_CODE (temp) == SUBREG
3997 && GET_CODE (SUBREG_REG (temp)) == REG)
3998 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4000 rtx temp1 = simplify_shift_const
4001 (NULL_RTX, ASHIFTRT, mode,
4002 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4003 GET_MODE_BITSIZE (mode) - 1 - i),
4004 GET_MODE_BITSIZE (mode) - 1 - i);
4006 /* If all we did was surround TEMP with the two shifts, we
4007 haven't improved anything, so don't use it. Otherwise,
4008 we are better off with TEMP1. */
4009 if (GET_CODE (temp1) != ASHIFTRT
4010 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4011 || XEXP (XEXP (temp1, 0), 0) != temp)
4017 /* We can't handle truncation to a partial integer mode here
4018 because we don't know the real bitsize of the partial
4020 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4023 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4024 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4025 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4027 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4028 GET_MODE_MASK (mode), NULL_RTX, 0));
4030 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
4031 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4032 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4033 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4034 return XEXP (XEXP (x, 0), 0);
4036 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
4037 (OP:SI foo:SI) if OP is NEG or ABS. */
4038 if ((GET_CODE (XEXP (x, 0)) == ABS
4039 || GET_CODE (XEXP (x, 0)) == NEG)
4040 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
4041 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
4042 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4043 return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
4044 XEXP (XEXP (XEXP (x, 0), 0), 0));
4046 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4048 if (GET_CODE (XEXP (x, 0)) == SUBREG
4049 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
4050 && subreg_lowpart_p (XEXP (x, 0)))
4051 return SUBREG_REG (XEXP (x, 0));
4053 /* If we know that the value is already truncated, we can
4054 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4055 is nonzero for the corresponding modes. But don't do this
4056 for an (LSHIFTRT (MULT ...)) since this will cause problems
4057 with the umulXi3_highpart patterns. */
4058 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4059 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
4060 && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4061 >= GET_MODE_BITSIZE (mode) + 1
4062 && ! (GET_CODE (XEXP (x, 0)) == LSHIFTRT
4063 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT))
4064 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4066 /* A truncate of a comparison can be replaced with a subreg if
4067 STORE_FLAG_VALUE permits. This is like the previous test,
4068 but it works even if the comparison is done in a mode larger
4069 than HOST_BITS_PER_WIDE_INT. */
4070 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4071 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4072 && ((HOST_WIDE_INT) STORE_FLAG_VALUE &~ GET_MODE_MASK (mode)) == 0)
4073 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4075 /* Similarly, a truncate of a register whose value is a
4076 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4078 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4079 && ((HOST_WIDE_INT) STORE_FLAG_VALUE &~ GET_MODE_MASK (mode)) == 0
4080 && (temp = get_last_value (XEXP (x, 0)))
4081 && GET_RTX_CLASS (GET_CODE (temp)) == '<')
4082 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4086 case FLOAT_TRUNCATE:
4087 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4088 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4089 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4090 return XEXP (XEXP (x, 0), 0);
4092 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4093 (OP:SF foo:SF) if OP is NEG or ABS. */
4094 if ((GET_CODE (XEXP (x, 0)) == ABS
4095 || GET_CODE (XEXP (x, 0)) == NEG)
4096 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
4097 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4098 return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
4099 XEXP (XEXP (XEXP (x, 0), 0), 0));
4101 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4102 is (float_truncate:SF x). */
4103 if (GET_CODE (XEXP (x, 0)) == SUBREG
4104 && subreg_lowpart_p (XEXP (x, 0))
4105 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
4106 return SUBREG_REG (XEXP (x, 0));
4111 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4112 using cc0, in which case we want to leave it as a COMPARE
4113 so we can distinguish it from a register-register-copy. */
4114 if (XEXP (x, 1) == const0_rtx)
4117 /* In IEEE floating point, x-0 is not the same as x. */
4118 if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
4119 || ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0)))
4121 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4127 /* (const (const X)) can become (const X). Do it this way rather than
4128 returning the inner CONST since CONST can be shared with a
4130 if (GET_CODE (XEXP (x, 0)) == CONST)
4131 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4136 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4137 can add in an offset. find_split_point will split this address up
4138 again if it doesn't match. */
4139 if (GET_CODE (XEXP (x, 0)) == HIGH
4140 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4146 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4147 outermost. That's because that's the way indexed addresses are
4148 supposed to appear. This code used to check many more cases, but
4149 they are now checked elsewhere. */
4150 if (GET_CODE (XEXP (x, 0)) == PLUS
4151 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
4152 return gen_binary (PLUS, mode,
4153 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
4155 XEXP (XEXP (x, 0), 1));
4157 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4158 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4159 bit-field and can be replaced by either a sign_extend or a
4160 sign_extract. The `and' may be a zero_extend and the two
4161 <c>, -<c> constants may be reversed. */
4162 if (GET_CODE (XEXP (x, 0)) == XOR
4163 && GET_CODE (XEXP (x, 1)) == CONST_INT
4164 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4165 && INTVAL (XEXP (x, 1)) == - INTVAL (XEXP (XEXP (x, 0), 1))
4166 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4167 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4168 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4169 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4170 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4171 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4172 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4173 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4174 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4175 == (unsigned int) i + 1))))
4176 return simplify_shift_const
4177 (NULL_RTX, ASHIFTRT, mode,
4178 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4179 XEXP (XEXP (XEXP (x, 0), 0), 0),
4180 GET_MODE_BITSIZE (mode) - (i + 1)),
4181 GET_MODE_BITSIZE (mode) - (i + 1));
4183 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4184 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4185 is 1. This produces better code than the alternative immediately
4187 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4188 && reversible_comparison_p (XEXP (x, 0))
4189 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
4190 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx)))
4192 gen_unary (NEG, mode, mode,
4193 gen_binary (reverse_condition (GET_CODE (XEXP (x, 0))),
4194 mode, XEXP (XEXP (x, 0), 0),
4195 XEXP (XEXP (x, 0), 1)));
4197 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4198 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4199 the bitsize of the mode - 1. This allows simplification of
4200 "a = (b & 8) == 0;" */
4201 if (XEXP (x, 1) == constm1_rtx
4202 && GET_CODE (XEXP (x, 0)) != REG
4203 && ! (GET_CODE (XEXP (x,0)) == SUBREG
4204 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
4205 && nonzero_bits (XEXP (x, 0), mode) == 1)
4206 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4207 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4208 gen_rtx_combine (XOR, mode,
4209 XEXP (x, 0), const1_rtx),
4210 GET_MODE_BITSIZE (mode) - 1),
4211 GET_MODE_BITSIZE (mode) - 1);
4213 /* If we are adding two things that have no bits in common, convert
4214 the addition into an IOR. This will often be further simplified,
4215 for example in cases like ((a & 1) + (a & 2)), which can
4218 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4219 && (nonzero_bits (XEXP (x, 0), mode)
4220 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4221 return gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4225 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4226 by reversing the comparison code if valid. */
4227 if (STORE_FLAG_VALUE == 1
4228 && XEXP (x, 0) == const1_rtx
4229 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
4230 && reversible_comparison_p (XEXP (x, 1)))
4231 return gen_binary (reverse_condition (GET_CODE (XEXP (x, 1))),
4232 mode, XEXP (XEXP (x, 1), 0),
4233 XEXP (XEXP (x, 1), 1));
4235 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4236 (and <foo> (const_int pow2-1)) */
4237 if (GET_CODE (XEXP (x, 1)) == AND
4238 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4239 && exact_log2 (- INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4240 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4241 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4242 - INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4244 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4246 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
4247 return gen_binary (MINUS, mode,
4248 gen_binary (MINUS, mode, XEXP (x, 0),
4249 XEXP (XEXP (x, 1), 0)),
4250 XEXP (XEXP (x, 1), 1));
4254 /* If we have (mult (plus A B) C), apply the distributive law and then
4255 the inverse distributive law to see if things simplify. This
4256 occurs mostly in addresses, often when unrolling loops. */
4258 if (GET_CODE (XEXP (x, 0)) == PLUS)
4260 x = apply_distributive_law
4261 (gen_binary (PLUS, mode,
4262 gen_binary (MULT, mode,
4263 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4264 gen_binary (MULT, mode,
4265 XEXP (XEXP (x, 0), 1),
4266 copy_rtx (XEXP (x, 1)))));
4268 if (GET_CODE (x) != MULT)
4274 /* If this is a divide by a power of two, treat it as a shift if
4275 its first operand is a shift. */
4276 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4277 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4278 && (GET_CODE (XEXP (x, 0)) == ASHIFT
4279 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4280 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4281 || GET_CODE (XEXP (x, 0)) == ROTATE
4282 || GET_CODE (XEXP (x, 0)) == ROTATERT))
4283 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4287 case GT: case GTU: case GE: case GEU:
4288 case LT: case LTU: case LE: case LEU:
4289 /* If the first operand is a condition code, we can't do anything
4291 if (GET_CODE (XEXP (x, 0)) == COMPARE
4292 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4294 && XEXP (x, 0) != cc0_rtx
4298 rtx op0 = XEXP (x, 0);
4299 rtx op1 = XEXP (x, 1);
4300 enum rtx_code new_code;
4302 if (GET_CODE (op0) == COMPARE)
4303 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4305 /* Simplify our comparison, if possible. */
4306 new_code = simplify_comparison (code, &op0, &op1);
4308 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4309 if only the low-order bit is possibly nonzero in X (such as when
4310 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4311 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4312 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4315 Remove any ZERO_EXTRACT we made when thinking this was a
4316 comparison. It may now be simpler to use, e.g., an AND. If a
4317 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4318 the call to make_compound_operation in the SET case. */
4320 if (STORE_FLAG_VALUE == 1
4321 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4322 && op1 == const0_rtx && nonzero_bits (op0, mode) == 1)
4323 return gen_lowpart_for_combine (mode,
4324 expand_compound_operation (op0));
4326 else if (STORE_FLAG_VALUE == 1
4327 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4328 && op1 == const0_rtx
4329 && (num_sign_bit_copies (op0, mode)
4330 == GET_MODE_BITSIZE (mode)))
4332 op0 = expand_compound_operation (op0);
4333 return gen_unary (NEG, mode, mode,
4334 gen_lowpart_for_combine (mode, op0));
4337 else if (STORE_FLAG_VALUE == 1
4338 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4339 && op1 == const0_rtx
4340 && nonzero_bits (op0, mode) == 1)
4342 op0 = expand_compound_operation (op0);
4343 return gen_binary (XOR, mode,
4344 gen_lowpart_for_combine (mode, op0),
4348 else if (STORE_FLAG_VALUE == 1
4349 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4350 && op1 == const0_rtx
4351 && (num_sign_bit_copies (op0, mode)
4352 == GET_MODE_BITSIZE (mode)))
4354 op0 = expand_compound_operation (op0);
4355 return plus_constant (gen_lowpart_for_combine (mode, op0), 1);
4358 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4360 if (STORE_FLAG_VALUE == -1
4361 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4362 && op1 == const0_rtx
4363 && (num_sign_bit_copies (op0, mode)
4364 == GET_MODE_BITSIZE (mode)))
4365 return gen_lowpart_for_combine (mode,
4366 expand_compound_operation (op0));
4368 else if (STORE_FLAG_VALUE == -1
4369 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4370 && op1 == const0_rtx
4371 && nonzero_bits (op0, mode) == 1)
4373 op0 = expand_compound_operation (op0);
4374 return gen_unary (NEG, mode, mode,
4375 gen_lowpart_for_combine (mode, op0));
4378 else if (STORE_FLAG_VALUE == -1
4379 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4380 && op1 == const0_rtx
4381 && (num_sign_bit_copies (op0, mode)
4382 == GET_MODE_BITSIZE (mode)))
4384 op0 = expand_compound_operation (op0);
4385 return gen_unary (NOT, mode, mode,
4386 gen_lowpart_for_combine (mode, op0));
4389 /* If X is 0/1, (eq X 0) is X-1. */
4390 else if (STORE_FLAG_VALUE == -1
4391 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4392 && op1 == const0_rtx
4393 && nonzero_bits (op0, mode) == 1)
4395 op0 = expand_compound_operation (op0);
4396 return plus_constant (gen_lowpart_for_combine (mode, op0), -1);
4399 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4400 one bit that might be nonzero, we can convert (ne x 0) to
4401 (ashift x c) where C puts the bit in the sign bit. Remove any
4402 AND with STORE_FLAG_VALUE when we are done, since we are only
4403 going to test the sign bit. */
4404 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4405 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4406 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4407 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE(mode)-1))
4408 && op1 == const0_rtx
4409 && mode == GET_MODE (op0)
4410 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4412 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4413 expand_compound_operation (op0),
4414 GET_MODE_BITSIZE (mode) - 1 - i);
4415 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4421 /* If the code changed, return a whole new comparison. */
4422 if (new_code != code)
4423 return gen_rtx_combine (new_code, mode, op0, op1);
4425 /* Otherwise, keep this operation, but maybe change its operands.
4426 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4427 SUBST (XEXP (x, 0), op0);
4428 SUBST (XEXP (x, 1), op1);
4433 return simplify_if_then_else (x);
4439 /* If we are processing SET_DEST, we are done. */
4443 return expand_compound_operation (x);
4446 return simplify_set (x);
4451 return simplify_logical (x, last);
4454 /* (abs (neg <foo>)) -> (abs <foo>) */
4455 if (GET_CODE (XEXP (x, 0)) == NEG)
4456 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4458 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4460 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
4463 /* If operand is something known to be positive, ignore the ABS. */
4464 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4465 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4466 <= HOST_BITS_PER_WIDE_INT)
4467 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4468 & ((HOST_WIDE_INT) 1
4469 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4474 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4475 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4476 return gen_rtx_combine (NEG, mode, XEXP (x, 0));
4481 /* (ffs (*_extend <X>)) = (ffs <X>) */
4482 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4483 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4484 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4488 /* (float (sign_extend <X>)) = (float <X>). */
4489 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4490 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4498 /* If this is a shift by a constant amount, simplify it. */
4499 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4500 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4501 INTVAL (XEXP (x, 1)));
4503 #ifdef SHIFT_COUNT_TRUNCATED
4504 else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG)
4506 force_to_mode (XEXP (x, 1), GET_MODE (x),
4508 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4522 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4525 simplify_if_then_else (x)
4528 enum machine_mode mode = GET_MODE (x);
4529 rtx cond = XEXP (x, 0);
4530 rtx true = XEXP (x, 1);
4531 rtx false = XEXP (x, 2);
4532 enum rtx_code true_code = GET_CODE (cond);
4533 int comparison_p = GET_RTX_CLASS (true_code) == '<';
4537 /* Simplify storing of the truth value. */
4538 if (comparison_p && true == const_true_rtx && false == const0_rtx)
4539 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
4541 /* Also when the truth value has to be reversed. */
4542 if (comparison_p && reversible_comparison_p (cond)
4543 && true == const0_rtx && false == const_true_rtx)
4544 return gen_binary (reverse_condition (true_code),
4545 mode, XEXP (cond, 0), XEXP (cond, 1));
4547 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4548 in it is being compared against certain values. Get the true and false
4549 comparisons and see if that says anything about the value of each arm. */
4551 if (comparison_p && reversible_comparison_p (cond)
4552 && GET_CODE (XEXP (cond, 0)) == REG)
4555 rtx from = XEXP (cond, 0);
4556 enum rtx_code false_code = reverse_condition (true_code);
4557 rtx true_val = XEXP (cond, 1);
4558 rtx false_val = true_val;
4561 /* If FALSE_CODE is EQ, swap the codes and arms. */
4563 if (false_code == EQ)
4565 swapped = 1, true_code = EQ, false_code = NE;
4566 temp = true, true = false, false = temp;
4569 /* If we are comparing against zero and the expression being tested has
4570 only a single bit that might be nonzero, that is its value when it is
4571 not equal to zero. Similarly if it is known to be -1 or 0. */
4573 if (true_code == EQ && true_val == const0_rtx
4574 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4575 false_code = EQ, false_val = GEN_INT (nzb);
4576 else if (true_code == EQ && true_val == const0_rtx
4577 && (num_sign_bit_copies (from, GET_MODE (from))
4578 == GET_MODE_BITSIZE (GET_MODE (from))))
4579 false_code = EQ, false_val = constm1_rtx;
4581 /* Now simplify an arm if we know the value of the register in the
4582 branch and it is used in the arm. Be careful due to the potential
4583 of locally-shared RTL. */
4585 if (reg_mentioned_p (from, true))
4586 true = subst (known_cond (copy_rtx (true), true_code, from, true_val),
4587 pc_rtx, pc_rtx, 0, 0);
4588 if (reg_mentioned_p (from, false))
4589 false = subst (known_cond (copy_rtx (false), false_code,
4591 pc_rtx, pc_rtx, 0, 0);
4593 SUBST (XEXP (x, 1), swapped ? false : true);
4594 SUBST (XEXP (x, 2), swapped ? true : false);
4596 true = XEXP (x, 1), false = XEXP (x, 2), true_code = GET_CODE (cond);
4599 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4600 reversed, do so to avoid needing two sets of patterns for
4601 subtract-and-branch insns. Similarly if we have a constant in the true
4602 arm, the false arm is the same as the first operand of the comparison, or
4603 the false arm is more complicated than the true arm. */
4605 if (comparison_p && reversible_comparison_p (cond)
4607 || (CONSTANT_P (true)
4608 && GET_CODE (false) != CONST_INT && false != pc_rtx)
4609 || true == const0_rtx
4610 || (GET_RTX_CLASS (GET_CODE (true)) == 'o'
4611 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4612 || (GET_CODE (true) == SUBREG
4613 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true))) == 'o'
4614 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4615 || reg_mentioned_p (true, false)
4616 || rtx_equal_p (false, XEXP (cond, 0))))
4618 true_code = reverse_condition (true_code);
4620 gen_binary (true_code, GET_MODE (cond), XEXP (cond, 0),
4623 SUBST (XEXP (x, 1), false);
4624 SUBST (XEXP (x, 2), true);
4626 temp = true, true = false, false = temp, cond = XEXP (x, 0);
4628 /* It is possible that the conditional has been simplified out. */
4629 true_code = GET_CODE (cond);
4630 comparison_p = GET_RTX_CLASS (true_code) == '<';
4633 /* If the two arms are identical, we don't need the comparison. */
4635 if (rtx_equal_p (true, false) && ! side_effects_p (cond))
4638 /* Convert a == b ? b : a to "a". */
4639 if (true_code == EQ && ! side_effects_p (cond)
4640 && rtx_equal_p (XEXP (cond, 0), false)
4641 && rtx_equal_p (XEXP (cond, 1), true))
4643 else if (true_code == NE && ! side_effects_p (cond)
4644 && rtx_equal_p (XEXP (cond, 0), true)
4645 && rtx_equal_p (XEXP (cond, 1), false))
4648 /* Look for cases where we have (abs x) or (neg (abs X)). */
4650 if (GET_MODE_CLASS (mode) == MODE_INT
4651 && GET_CODE (false) == NEG
4652 && rtx_equal_p (true, XEXP (false, 0))
4654 && rtx_equal_p (true, XEXP (cond, 0))
4655 && ! side_effects_p (true))
4660 return gen_unary (ABS, mode, mode, true);
4663 return gen_unary (NEG, mode, mode, gen_unary (ABS, mode, mode, true));
4668 /* Look for MIN or MAX. */
4670 if ((! FLOAT_MODE_P (mode) || flag_fast_math)
4672 && rtx_equal_p (XEXP (cond, 0), true)
4673 && rtx_equal_p (XEXP (cond, 1), false)
4674 && ! side_effects_p (cond))
4679 return gen_binary (SMAX, mode, true, false);
4682 return gen_binary (SMIN, mode, true, false);
4685 return gen_binary (UMAX, mode, true, false);
4688 return gen_binary (UMIN, mode, true, false);
4693 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4694 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4695 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4696 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4697 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4698 neither 1 or -1, but it isn't worth checking for. */
4700 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4701 && comparison_p && mode != VOIDmode && ! side_effects_p (x))
4703 rtx t = make_compound_operation (true, SET);
4704 rtx f = make_compound_operation (false, SET);
4705 rtx cond_op0 = XEXP (cond, 0);
4706 rtx cond_op1 = XEXP (cond, 1);
4707 enum rtx_code op = NIL, extend_op = NIL;
4708 enum machine_mode m = mode;
4709 rtx z = 0, c1 = NULL_RTX;
4711 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4712 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4713 || GET_CODE (t) == ASHIFT
4714 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4715 && rtx_equal_p (XEXP (t, 0), f))
4716 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4718 /* If an identity-zero op is commutative, check whether there
4719 would be a match if we swapped the operands. */
4720 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4721 || GET_CODE (t) == XOR)
4722 && rtx_equal_p (XEXP (t, 1), f))
4723 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4724 else if (GET_CODE (t) == SIGN_EXTEND
4725 && (GET_CODE (XEXP (t, 0)) == PLUS
4726 || GET_CODE (XEXP (t, 0)) == MINUS
4727 || GET_CODE (XEXP (t, 0)) == IOR
4728 || GET_CODE (XEXP (t, 0)) == XOR
4729 || GET_CODE (XEXP (t, 0)) == ASHIFT
4730 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4731 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4732 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4733 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4734 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4735 && (num_sign_bit_copies (f, GET_MODE (f))
4736 > (GET_MODE_BITSIZE (mode)
4737 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4739 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4740 extend_op = SIGN_EXTEND;
4741 m = GET_MODE (XEXP (t, 0));
4743 else if (GET_CODE (t) == SIGN_EXTEND
4744 && (GET_CODE (XEXP (t, 0)) == PLUS
4745 || GET_CODE (XEXP (t, 0)) == IOR
4746 || GET_CODE (XEXP (t, 0)) == XOR)
4747 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4748 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4749 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4750 && (num_sign_bit_copies (f, GET_MODE (f))
4751 > (GET_MODE_BITSIZE (mode)
4752 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4754 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4755 extend_op = SIGN_EXTEND;
4756 m = GET_MODE (XEXP (t, 0));
4758 else if (GET_CODE (t) == ZERO_EXTEND
4759 && (GET_CODE (XEXP (t, 0)) == PLUS
4760 || GET_CODE (XEXP (t, 0)) == MINUS
4761 || GET_CODE (XEXP (t, 0)) == IOR
4762 || GET_CODE (XEXP (t, 0)) == XOR
4763 || GET_CODE (XEXP (t, 0)) == ASHIFT
4764 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4765 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4766 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4767 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4768 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4769 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4770 && ((nonzero_bits (f, GET_MODE (f))
4771 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
4774 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4775 extend_op = ZERO_EXTEND;
4776 m = GET_MODE (XEXP (t, 0));
4778 else if (GET_CODE (t) == ZERO_EXTEND
4779 && (GET_CODE (XEXP (t, 0)) == PLUS
4780 || GET_CODE (XEXP (t, 0)) == IOR
4781 || GET_CODE (XEXP (t, 0)) == XOR)
4782 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4783 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4784 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4785 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4786 && ((nonzero_bits (f, GET_MODE (f))
4787 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
4790 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4791 extend_op = ZERO_EXTEND;
4792 m = GET_MODE (XEXP (t, 0));
4797 temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
4798 pc_rtx, pc_rtx, 0, 0);
4799 temp = gen_binary (MULT, m, temp,
4800 gen_binary (MULT, m, c1, const_true_rtx));
4801 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
4802 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
4804 if (extend_op != NIL)
4805 temp = gen_unary (extend_op, mode, m, temp);
4811 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4812 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4813 negation of a single bit, we can convert this operation to a shift. We
4814 can actually do this more generally, but it doesn't seem worth it. */
4816 if (true_code == NE && XEXP (cond, 1) == const0_rtx
4817 && false == const0_rtx && GET_CODE (true) == CONST_INT
4818 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
4819 && (i = exact_log2 (INTVAL (true))) >= 0)
4820 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
4821 == GET_MODE_BITSIZE (mode))
4822 && (i = exact_log2 (- INTVAL (true))) >= 0)))
4824 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4825 gen_lowpart_for_combine (mode, XEXP (cond, 0)), i);
4830 /* Simplify X, a SET expression. Return the new expression. */
4836 rtx src = SET_SRC (x);
4837 rtx dest = SET_DEST (x);
4838 enum machine_mode mode
4839 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
4843 /* (set (pc) (return)) gets written as (return). */
4844 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
4847 /* Now that we know for sure which bits of SRC we are using, see if we can
4848 simplify the expression for the object knowing that we only need the
4851 if (GET_MODE_CLASS (mode) == MODE_INT)
4853 src = force_to_mode (src, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
4854 SUBST (SET_SRC (x), src);
4857 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4858 the comparison result and try to simplify it unless we already have used
4859 undobuf.other_insn. */
4860 if ((GET_CODE (src) == COMPARE
4865 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
4866 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
4867 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
4868 && rtx_equal_p (XEXP (*cc_use, 0), dest))
4870 enum rtx_code old_code = GET_CODE (*cc_use);
4871 enum rtx_code new_code;
4873 int other_changed = 0;
4874 enum machine_mode compare_mode = GET_MODE (dest);
4876 if (GET_CODE (src) == COMPARE)
4877 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
4879 op0 = src, op1 = const0_rtx;
4881 /* Simplify our comparison, if possible. */
4882 new_code = simplify_comparison (old_code, &op0, &op1);
4884 #ifdef EXTRA_CC_MODES
4885 /* If this machine has CC modes other than CCmode, check to see if we
4886 need to use a different CC mode here. */
4887 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
4888 #endif /* EXTRA_CC_MODES */
4890 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
4891 /* If the mode changed, we have to change SET_DEST, the mode in the
4892 compare, and the mode in the place SET_DEST is used. If SET_DEST is
4893 a hard register, just build new versions with the proper mode. If it
4894 is a pseudo, we lose unless it is only time we set the pseudo, in
4895 which case we can safely change its mode. */
4896 if (compare_mode != GET_MODE (dest))
4898 unsigned int regno = REGNO (dest);
4899 rtx new_dest = gen_rtx_REG (compare_mode, regno);
4901 if (regno < FIRST_PSEUDO_REGISTER
4902 || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
4904 if (regno >= FIRST_PSEUDO_REGISTER)
4905 SUBST (regno_reg_rtx[regno], new_dest);
4907 SUBST (SET_DEST (x), new_dest);
4908 SUBST (XEXP (*cc_use, 0), new_dest);
4916 /* If the code changed, we have to build a new comparison in
4917 undobuf.other_insn. */
4918 if (new_code != old_code)
4920 unsigned HOST_WIDE_INT mask;
4922 SUBST (*cc_use, gen_rtx_combine (new_code, GET_MODE (*cc_use),
4925 /* If the only change we made was to change an EQ into an NE or
4926 vice versa, OP0 has only one bit that might be nonzero, and OP1
4927 is zero, check if changing the user of the condition code will
4928 produce a valid insn. If it won't, we can keep the original code
4929 in that insn by surrounding our operation with an XOR. */
4931 if (((old_code == NE && new_code == EQ)
4932 || (old_code == EQ && new_code == NE))
4933 && ! other_changed && op1 == const0_rtx
4934 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
4935 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
4937 rtx pat = PATTERN (other_insn), note = 0;
4939 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
4940 && ! check_asm_operands (pat)))
4942 PUT_CODE (*cc_use, old_code);
4945 op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
4953 undobuf.other_insn = other_insn;
4956 /* If we are now comparing against zero, change our source if
4957 needed. If we do not use cc0, we always have a COMPARE. */
4958 if (op1 == const0_rtx && dest == cc0_rtx)
4960 SUBST (SET_SRC (x), op0);
4966 /* Otherwise, if we didn't previously have a COMPARE in the
4967 correct mode, we need one. */
4968 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
4971 gen_rtx_combine (COMPARE, compare_mode, op0, op1));
4976 /* Otherwise, update the COMPARE if needed. */
4977 SUBST (XEXP (src, 0), op0);
4978 SUBST (XEXP (src, 1), op1);
4983 /* Get SET_SRC in a form where we have placed back any
4984 compound expressions. Then do the checks below. */
4985 src = make_compound_operation (src, SET);
4986 SUBST (SET_SRC (x), src);
4989 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
4990 and X being a REG or (subreg (reg)), we may be able to convert this to
4991 (set (subreg:m2 x) (op)).
4993 We can always do this if M1 is narrower than M2 because that means that
4994 we only care about the low bits of the result.
4996 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
4997 perform a narrower operation than requested since the high-order bits will
4998 be undefined. On machine where it is defined, this transformation is safe
4999 as long as M1 and M2 have the same number of words. */
5001 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5002 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o'
5003 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5005 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5006 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5007 #ifndef WORD_REGISTER_OPERATIONS
5008 && (GET_MODE_SIZE (GET_MODE (src))
5009 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5011 #ifdef CLASS_CANNOT_CHANGE_SIZE
5012 && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER
5013 && (TEST_HARD_REG_BIT
5014 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE],
5016 && (GET_MODE_SIZE (GET_MODE (src))
5017 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))))
5019 && (GET_CODE (dest) == REG
5020 || (GET_CODE (dest) == SUBREG
5021 && GET_CODE (SUBREG_REG (dest)) == REG)))
5023 SUBST (SET_DEST (x),
5024 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)),
5026 SUBST (SET_SRC (x), SUBREG_REG (src));
5028 src = SET_SRC (x), dest = SET_DEST (x);
5031 #ifdef LOAD_EXTEND_OP
5032 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5033 would require a paradoxical subreg. Replace the subreg with a
5034 zero_extend to avoid the reload that would otherwise be required. */
5036 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5037 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
5038 && SUBREG_WORD (src) == 0
5039 && (GET_MODE_SIZE (GET_MODE (src))
5040 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5041 && GET_CODE (SUBREG_REG (src)) == MEM)
5044 gen_rtx_combine (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5045 GET_MODE (src), XEXP (src, 0)));
5051 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5052 are comparing an item known to be 0 or -1 against 0, use a logical
5053 operation instead. Check for one of the arms being an IOR of the other
5054 arm with some value. We compute three terms to be IOR'ed together. In
5055 practice, at most two will be nonzero. Then we do the IOR's. */
5057 if (GET_CODE (dest) != PC
5058 && GET_CODE (src) == IF_THEN_ELSE
5059 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5060 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5061 && XEXP (XEXP (src, 0), 1) == const0_rtx
5062 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5063 #ifdef HAVE_conditional_move
5064 && ! can_conditionally_move_p (GET_MODE (src))
5066 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5067 GET_MODE (XEXP (XEXP (src, 0), 0)))
5068 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5069 && ! side_effects_p (src))
5071 rtx true = (GET_CODE (XEXP (src, 0)) == NE
5072 ? XEXP (src, 1) : XEXP (src, 2));
5073 rtx false = (GET_CODE (XEXP (src, 0)) == NE
5074 ? XEXP (src, 2) : XEXP (src, 1));
5075 rtx term1 = const0_rtx, term2, term3;
5077 if (GET_CODE (true) == IOR && rtx_equal_p (XEXP (true, 0), false))
5078 term1 = false, true = XEXP (true, 1), false = const0_rtx;
5079 else if (GET_CODE (true) == IOR
5080 && rtx_equal_p (XEXP (true, 1), false))
5081 term1 = false, true = XEXP (true, 0), false = const0_rtx;
5082 else if (GET_CODE (false) == IOR
5083 && rtx_equal_p (XEXP (false, 0), true))
5084 term1 = true, false = XEXP (false, 1), true = const0_rtx;
5085 else if (GET_CODE (false) == IOR
5086 && rtx_equal_p (XEXP (false, 1), true))
5087 term1 = true, false = XEXP (false, 0), true = const0_rtx;
5089 term2 = gen_binary (AND, GET_MODE (src), XEXP (XEXP (src, 0), 0), true);
5090 term3 = gen_binary (AND, GET_MODE (src),
5091 gen_unary (NOT, GET_MODE (src), GET_MODE (src),
5092 XEXP (XEXP (src, 0), 0)),
5096 gen_binary (IOR, GET_MODE (src),
5097 gen_binary (IOR, GET_MODE (src), term1, term2),
5103 #ifdef HAVE_conditional_arithmetic
5104 /* If we have conditional arithmetic and the operand of a SET is
5105 a conditional expression, replace this with an IF_THEN_ELSE.
5106 We can either have a conditional expression or a MULT of that expression
5108 if ((GET_RTX_CLASS (GET_CODE (src)) == '1'
5109 || GET_RTX_CLASS (GET_CODE (src)) == '2'
5110 || GET_RTX_CLASS (GET_CODE (src)) == 'c')
5111 && (GET_RTX_CLASS (GET_CODE (XEXP (src, 0))) == '<'
5112 || (GET_CODE (XEXP (src, 0)) == MULT
5113 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (src, 0), 0))) == '<'
5114 && GET_CODE (XEXP (XEXP (src, 0), 1)) == CONST_INT)))
5116 rtx cond = XEXP (src, 0);
5117 rtx true_val = const1_rtx;
5118 rtx false_arm, true_arm;
5120 if (GET_CODE (cond) == MULT)
5122 true_val = XEXP (cond, 1);
5123 cond = XEXP (cond, 0);
5126 if (GET_RTX_CLASS (GET_CODE (src)) == '1')
5128 true_arm = gen_unary (GET_CODE (src), GET_MODE (src),
5129 GET_MODE (XEXP (src, 0)), true_val);
5130 false_arm = gen_unary (GET_CODE (src), GET_MODE (src),
5131 GET_MODE (XEXP (src, 0)), const0_rtx);
5135 true_arm = gen_binary (GET_CODE (src), GET_MODE (src),
5136 true_val, XEXP (src, 1));
5137 false_arm = gen_binary (GET_CODE (src), GET_MODE (src),
5138 const0_rtx, XEXP (src, 1));
5141 /* Canonicalize if true_arm is the simpler one. */
5142 if (GET_RTX_CLASS (GET_CODE (true_arm)) == 'o'
5143 && GET_RTX_CLASS (GET_CODE (false_arm)) != 'o'
5144 && reversible_comparison_p (cond))
5146 rtx temp = true_arm;
5148 true_arm = false_arm;
5151 cond = gen_rtx_combine (reverse_condition (GET_CODE (cond)),
5152 GET_MODE (cond), XEXP (cond, 0),
5156 src = gen_rtx_combine (IF_THEN_ELSE, GET_MODE (src),
5157 gen_rtx_combine (GET_CODE (cond), VOIDmode,
5160 true_arm, false_arm);
5161 SUBST (SET_SRC (x), src);
5165 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5166 whole thing fail. */
5167 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5169 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5172 /* Convert this into a field assignment operation, if possible. */
5173 return make_field_assignment (x);
5176 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5177 result. LAST is nonzero if this is the last retry. */
5180 simplify_logical (x, last)
5184 enum machine_mode mode = GET_MODE (x);
5185 rtx op0 = XEXP (x, 0);
5186 rtx op1 = XEXP (x, 1);
5188 switch (GET_CODE (x))
5191 /* Convert (A ^ B) & A to A & (~ B) since the latter is often a single
5192 insn (and may simplify more). */
5193 if (GET_CODE (op0) == XOR
5194 && rtx_equal_p (XEXP (op0, 0), op1)
5195 && ! side_effects_p (op1))
5196 x = gen_binary (AND, mode,
5197 gen_unary (NOT, mode, mode, XEXP (op0, 1)), op1);
5199 if (GET_CODE (op0) == XOR
5200 && rtx_equal_p (XEXP (op0, 1), op1)
5201 && ! side_effects_p (op1))
5202 x = gen_binary (AND, mode,
5203 gen_unary (NOT, mode, mode, XEXP (op0, 0)), op1);
5205 /* Similarly for (~ (A ^ B)) & A. */
5206 if (GET_CODE (op0) == NOT
5207 && GET_CODE (XEXP (op0, 0)) == XOR
5208 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
5209 && ! side_effects_p (op1))
5210 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
5212 if (GET_CODE (op0) == NOT
5213 && GET_CODE (XEXP (op0, 0)) == XOR
5214 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
5215 && ! side_effects_p (op1))
5216 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
5218 /* We can call simplify_and_const_int only if we don't lose
5219 any (sign) bits when converting INTVAL (op1) to
5220 "unsigned HOST_WIDE_INT". */
5221 if (GET_CODE (op1) == CONST_INT
5222 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5223 || INTVAL (op1) > 0))
5225 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5227 /* If we have (ior (and (X C1) C2)) and the next restart would be
5228 the last, simplify this by making C1 as small as possible
5231 && GET_CODE (x) == IOR && GET_CODE (op0) == AND
5232 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5233 && GET_CODE (op1) == CONST_INT)
5234 return gen_binary (IOR, mode,
5235 gen_binary (AND, mode, XEXP (op0, 0),
5236 GEN_INT (INTVAL (XEXP (op0, 1))
5237 & ~ INTVAL (op1))), op1);
5239 if (GET_CODE (x) != AND)
5242 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
5243 || GET_RTX_CLASS (GET_CODE (x)) == '2')
5244 op0 = XEXP (x, 0), op1 = XEXP (x, 1);
5247 /* Convert (A | B) & A to A. */
5248 if (GET_CODE (op0) == IOR
5249 && (rtx_equal_p (XEXP (op0, 0), op1)
5250 || rtx_equal_p (XEXP (op0, 1), op1))
5251 && ! side_effects_p (XEXP (op0, 0))
5252 && ! side_effects_p (XEXP (op0, 1)))
5255 /* In the following group of tests (and those in case IOR below),
5256 we start with some combination of logical operations and apply
5257 the distributive law followed by the inverse distributive law.
5258 Most of the time, this results in no change. However, if some of
5259 the operands are the same or inverses of each other, simplifications
5262 For example, (and (ior A B) (not B)) can occur as the result of
5263 expanding a bit field assignment. When we apply the distributive
5264 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5265 which then simplifies to (and (A (not B))).
5267 If we have (and (ior A B) C), apply the distributive law and then
5268 the inverse distributive law to see if things simplify. */
5270 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5272 x = apply_distributive_law
5273 (gen_binary (GET_CODE (op0), mode,
5274 gen_binary (AND, mode, XEXP (op0, 0), op1),
5275 gen_binary (AND, mode, XEXP (op0, 1),
5277 if (GET_CODE (x) != AND)
5281 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5282 return apply_distributive_law
5283 (gen_binary (GET_CODE (op1), mode,
5284 gen_binary (AND, mode, XEXP (op1, 0), op0),
5285 gen_binary (AND, mode, XEXP (op1, 1),
5288 /* Similarly, taking advantage of the fact that
5289 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5291 if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
5292 return apply_distributive_law
5293 (gen_binary (XOR, mode,
5294 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
5295 gen_binary (IOR, mode, copy_rtx (XEXP (op0, 0)),
5298 else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
5299 return apply_distributive_law
5300 (gen_binary (XOR, mode,
5301 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
5302 gen_binary (IOR, mode, copy_rtx (XEXP (op1, 0)), XEXP (op0, 1))));
5306 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5307 if (GET_CODE (op1) == CONST_INT
5308 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5309 && (nonzero_bits (op0, mode) & ~ INTVAL (op1)) == 0)
5312 /* Convert (A & B) | A to A. */
5313 if (GET_CODE (op0) == AND
5314 && (rtx_equal_p (XEXP (op0, 0), op1)
5315 || rtx_equal_p (XEXP (op0, 1), op1))
5316 && ! side_effects_p (XEXP (op0, 0))
5317 && ! side_effects_p (XEXP (op0, 1)))
5320 /* If we have (ior (and A B) C), apply the distributive law and then
5321 the inverse distributive law to see if things simplify. */
5323 if (GET_CODE (op0) == AND)
5325 x = apply_distributive_law
5326 (gen_binary (AND, mode,
5327 gen_binary (IOR, mode, XEXP (op0, 0), op1),
5328 gen_binary (IOR, mode, XEXP (op0, 1),
5331 if (GET_CODE (x) != IOR)
5335 if (GET_CODE (op1) == AND)
5337 x = apply_distributive_law
5338 (gen_binary (AND, mode,
5339 gen_binary (IOR, mode, XEXP (op1, 0), op0),
5340 gen_binary (IOR, mode, XEXP (op1, 1),
5343 if (GET_CODE (x) != IOR)
5347 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5348 mode size to (rotate A CX). */
5350 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
5351 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
5352 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
5353 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5354 && GET_CODE (XEXP (op1, 1)) == CONST_INT
5355 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
5356 == GET_MODE_BITSIZE (mode)))
5357 return gen_rtx_ROTATE (mode, XEXP (op0, 0),
5358 (GET_CODE (op0) == ASHIFT
5359 ? XEXP (op0, 1) : XEXP (op1, 1)));
5361 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5362 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5363 does not affect any of the bits in OP1, it can really be done
5364 as a PLUS and we can associate. We do this by seeing if OP1
5365 can be safely shifted left C bits. */
5366 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
5367 && GET_CODE (XEXP (op0, 0)) == PLUS
5368 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
5369 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5370 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
5372 int count = INTVAL (XEXP (op0, 1));
5373 HOST_WIDE_INT mask = INTVAL (op1) << count;
5375 if (mask >> count == INTVAL (op1)
5376 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
5378 SUBST (XEXP (XEXP (op0, 0), 1),
5379 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
5386 /* If we are XORing two things that have no bits in common,
5387 convert them into an IOR. This helps to detect rotation encoded
5388 using those methods and possibly other simplifications. */
5390 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5391 && (nonzero_bits (op0, mode)
5392 & nonzero_bits (op1, mode)) == 0)
5393 return (gen_binary (IOR, mode, op0, op1));
5395 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5396 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5399 int num_negated = 0;
5401 if (GET_CODE (op0) == NOT)
5402 num_negated++, op0 = XEXP (op0, 0);
5403 if (GET_CODE (op1) == NOT)
5404 num_negated++, op1 = XEXP (op1, 0);
5406 if (num_negated == 2)
5408 SUBST (XEXP (x, 0), op0);
5409 SUBST (XEXP (x, 1), op1);
5411 else if (num_negated == 1)
5412 return gen_unary (NOT, mode, mode, gen_binary (XOR, mode, op0, op1));
5415 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5416 correspond to a machine insn or result in further simplifications
5417 if B is a constant. */
5419 if (GET_CODE (op0) == AND
5420 && rtx_equal_p (XEXP (op0, 1), op1)
5421 && ! side_effects_p (op1))
5422 return gen_binary (AND, mode,
5423 gen_unary (NOT, mode, mode, XEXP (op0, 0)),
5426 else if (GET_CODE (op0) == AND
5427 && rtx_equal_p (XEXP (op0, 0), op1)
5428 && ! side_effects_p (op1))
5429 return gen_binary (AND, mode,
5430 gen_unary (NOT, mode, mode, XEXP (op0, 1)),
5433 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5434 comparison if STORE_FLAG_VALUE is 1. */
5435 if (STORE_FLAG_VALUE == 1
5436 && op1 == const1_rtx
5437 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5438 && reversible_comparison_p (op0))
5439 return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
5440 mode, XEXP (op0, 0), XEXP (op0, 1));
5442 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5443 is (lt foo (const_int 0)), so we can perform the above
5444 simplification if STORE_FLAG_VALUE is 1. */
5446 if (STORE_FLAG_VALUE == 1
5447 && op1 == const1_rtx
5448 && GET_CODE (op0) == LSHIFTRT
5449 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5450 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
5451 return gen_rtx_combine (GE, mode, XEXP (op0, 0), const0_rtx);
5453 /* (xor (comparison foo bar) (const_int sign-bit))
5454 when STORE_FLAG_VALUE is the sign bit. */
5455 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5456 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5457 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5458 && op1 == const_true_rtx
5459 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5460 && reversible_comparison_p (op0))
5461 return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
5462 mode, XEXP (op0, 0), XEXP (op0, 1));
5473 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5474 operations" because they can be replaced with two more basic operations.
5475 ZERO_EXTEND is also considered "compound" because it can be replaced with
5476 an AND operation, which is simpler, though only one operation.
5478 The function expand_compound_operation is called with an rtx expression
5479 and will convert it to the appropriate shifts and AND operations,
5480 simplifying at each stage.
5482 The function make_compound_operation is called to convert an expression
5483 consisting of shifts and ANDs into the equivalent compound expression.
5484 It is the inverse of this function, loosely speaking. */
5487 expand_compound_operation (x)
5490 unsigned HOST_WIDE_INT pos = 0, len;
5492 unsigned int modewidth;
5495 switch (GET_CODE (x))
5500 /* We can't necessarily use a const_int for a multiword mode;
5501 it depends on implicitly extending the value.
5502 Since we don't know the right way to extend it,
5503 we can't tell whether the implicit way is right.
5505 Even for a mode that is no wider than a const_int,
5506 we can't win, because we need to sign extend one of its bits through
5507 the rest of it, and we don't know which bit. */
5508 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5511 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5512 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5513 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5514 reloaded. If not for that, MEM's would very rarely be safe.
5516 Reject MODEs bigger than a word, because we might not be able
5517 to reference a two-register group starting with an arbitrary register
5518 (and currently gen_lowpart might crash for a SUBREG). */
5520 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5523 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5524 /* If the inner object has VOIDmode (the only way this can happen
5525 is if it is a ASM_OPERANDS), we can't do anything since we don't
5526 know how much masking to do. */
5535 /* If the operand is a CLOBBER, just return it. */
5536 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5539 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5540 || GET_CODE (XEXP (x, 2)) != CONST_INT
5541 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5544 len = INTVAL (XEXP (x, 1));
5545 pos = INTVAL (XEXP (x, 2));
5547 /* If this goes outside the object being extracted, replace the object
5548 with a (use (mem ...)) construct that only combine understands
5549 and is used only for this purpose. */
5550 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5551 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
5553 if (BITS_BIG_ENDIAN)
5554 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5561 /* Convert sign extension to zero extension, if we know that the high
5562 bit is not set, as this is easier to optimize. It will be converted
5563 back to cheaper alternative in make_extraction. */
5564 if (GET_CODE (x) == SIGN_EXTEND
5565 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5566 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5567 & ~ (((unsigned HOST_WIDE_INT)
5568 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5572 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5573 return expand_compound_operation (temp);
5576 /* We can optimize some special cases of ZERO_EXTEND. */
5577 if (GET_CODE (x) == ZERO_EXTEND)
5579 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5580 know that the last value didn't have any inappropriate bits
5582 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5583 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5584 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5585 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5586 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5587 return XEXP (XEXP (x, 0), 0);
5589 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5590 if (GET_CODE (XEXP (x, 0)) == SUBREG
5591 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5592 && subreg_lowpart_p (XEXP (x, 0))
5593 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5594 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5595 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5596 return SUBREG_REG (XEXP (x, 0));
5598 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5599 is a comparison and STORE_FLAG_VALUE permits. This is like
5600 the first case, but it works even when GET_MODE (x) is larger
5601 than HOST_WIDE_INT. */
5602 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5603 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5604 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<'
5605 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5606 <= HOST_BITS_PER_WIDE_INT)
5607 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5608 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5609 return XEXP (XEXP (x, 0), 0);
5611 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5612 if (GET_CODE (XEXP (x, 0)) == SUBREG
5613 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5614 && subreg_lowpart_p (XEXP (x, 0))
5615 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<'
5616 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5617 <= HOST_BITS_PER_WIDE_INT)
5618 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5619 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5620 return SUBREG_REG (XEXP (x, 0));
5624 /* If we reach here, we want to return a pair of shifts. The inner
5625 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5626 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5627 logical depending on the value of UNSIGNEDP.
5629 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5630 converted into an AND of a shift.
5632 We must check for the case where the left shift would have a negative
5633 count. This can happen in a case like (x >> 31) & 255 on machines
5634 that can't shift by a constant. On those machines, we would first
5635 combine the shift with the AND to produce a variable-position
5636 extraction. Then the constant of 31 would be substituted in to produce
5637 a such a position. */
5639 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5640 if (modewidth + len >= pos)
5641 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5643 simplify_shift_const (NULL_RTX, ASHIFT,
5646 modewidth - pos - len),
5649 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5650 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5651 simplify_shift_const (NULL_RTX, LSHIFTRT,
5654 ((HOST_WIDE_INT) 1 << len) - 1);
5656 /* Any other cases we can't handle. */
5660 /* If we couldn't do this for some reason, return the original
5662 if (GET_CODE (tem) == CLOBBER)
5668 /* X is a SET which contains an assignment of one object into
5669 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5670 or certain SUBREGS). If possible, convert it into a series of
5673 We half-heartedly support variable positions, but do not at all
5674 support variable lengths. */
5677 expand_field_assignment (x)
5681 rtx pos; /* Always counts from low bit. */
5684 enum machine_mode compute_mode;
5686 /* Loop until we find something we can't simplify. */
5689 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5690 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5692 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5693 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5694 pos = GEN_INT (BITS_PER_WORD * SUBREG_WORD (XEXP (SET_DEST (x), 0)));
5696 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5697 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5699 inner = XEXP (SET_DEST (x), 0);
5700 len = INTVAL (XEXP (SET_DEST (x), 1));
5701 pos = XEXP (SET_DEST (x), 2);
5703 /* If the position is constant and spans the width of INNER,
5704 surround INNER with a USE to indicate this. */
5705 if (GET_CODE (pos) == CONST_INT
5706 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5707 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
5709 if (BITS_BIG_ENDIAN)
5711 if (GET_CODE (pos) == CONST_INT)
5712 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5714 else if (GET_CODE (pos) == MINUS
5715 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5716 && (INTVAL (XEXP (pos, 1))
5717 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5718 /* If position is ADJUST - X, new position is X. */
5719 pos = XEXP (pos, 0);
5721 pos = gen_binary (MINUS, GET_MODE (pos),
5722 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
5728 /* A SUBREG between two modes that occupy the same numbers of words
5729 can be done by moving the SUBREG to the source. */
5730 else if (GET_CODE (SET_DEST (x)) == SUBREG
5731 /* We need SUBREGs to compute nonzero_bits properly. */
5732 && nonzero_sign_valid
5733 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5734 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5735 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5736 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5738 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5739 gen_lowpart_for_combine
5740 (GET_MODE (SUBREG_REG (SET_DEST (x))),
5747 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5748 inner = SUBREG_REG (inner);
5750 compute_mode = GET_MODE (inner);
5752 /* Don't attempt bitwise arithmetic on non-integral modes. */
5753 if (! INTEGRAL_MODE_P (compute_mode))
5755 enum machine_mode imode;
5757 /* Something is probably seriously wrong if this matches. */
5758 if (! FLOAT_MODE_P (compute_mode))
5761 /* Try to find an integral mode to pun with. */
5762 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
5763 if (imode == BLKmode)
5766 compute_mode = imode;
5767 inner = gen_lowpart_for_combine (imode, inner);
5770 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5771 if (len < HOST_BITS_PER_WIDE_INT)
5772 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5776 /* Now compute the equivalent expression. Make a copy of INNER
5777 for the SET_DEST in case it is a MEM into which we will substitute;
5778 we don't want shared RTL in that case. */
5780 (VOIDmode, copy_rtx (inner),
5781 gen_binary (IOR, compute_mode,
5782 gen_binary (AND, compute_mode,
5783 gen_unary (NOT, compute_mode,
5789 gen_binary (ASHIFT, compute_mode,
5790 gen_binary (AND, compute_mode,
5791 gen_lowpart_for_combine
5792 (compute_mode, SET_SRC (x)),
5800 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5801 it is an RTX that represents a variable starting position; otherwise,
5802 POS is the (constant) starting bit position (counted from the LSB).
5804 INNER may be a USE. This will occur when we started with a bitfield
5805 that went outside the boundary of the object in memory, which is
5806 allowed on most machines. To isolate this case, we produce a USE
5807 whose mode is wide enough and surround the MEM with it. The only
5808 code that understands the USE is this routine. If it is not removed,
5809 it will cause the resulting insn not to match.
5811 UNSIGNEDP is non-zero for an unsigned reference and zero for a
5814 IN_DEST is non-zero if this is a reference in the destination of a
5815 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
5816 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5819 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
5820 ZERO_EXTRACT should be built even for bits starting at bit 0.
5822 MODE is the desired mode of the result (if IN_DEST == 0).
5824 The result is an RTX for the extraction or NULL_RTX if the target
5828 make_extraction (mode, inner, pos, pos_rtx, len,
5829 unsignedp, in_dest, in_compare)
5830 enum machine_mode mode;
5834 unsigned HOST_WIDE_INT len;
5836 int in_dest, in_compare;
5838 /* This mode describes the size of the storage area
5839 to fetch the overall value from. Within that, we
5840 ignore the POS lowest bits, etc. */
5841 enum machine_mode is_mode = GET_MODE (inner);
5842 enum machine_mode inner_mode;
5843 enum machine_mode wanted_inner_mode = byte_mode;
5844 enum machine_mode wanted_inner_reg_mode = word_mode;
5845 enum machine_mode pos_mode = word_mode;
5846 enum machine_mode extraction_mode = word_mode;
5847 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5850 rtx orig_pos_rtx = pos_rtx;
5851 HOST_WIDE_INT orig_pos;
5853 /* Get some information about INNER and get the innermost object. */
5854 if (GET_CODE (inner) == USE)
5855 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5856 /* We don't need to adjust the position because we set up the USE
5857 to pretend that it was a full-word object. */
5858 spans_byte = 1, inner = XEXP (inner, 0);
5859 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5861 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5862 consider just the QI as the memory to extract from.
5863 The subreg adds or removes high bits; its mode is
5864 irrelevant to the meaning of this extraction,
5865 since POS and LEN count from the lsb. */
5866 if (GET_CODE (SUBREG_REG (inner)) == MEM)
5867 is_mode = GET_MODE (SUBREG_REG (inner));
5868 inner = SUBREG_REG (inner);
5871 inner_mode = GET_MODE (inner);
5873 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
5874 pos = INTVAL (pos_rtx), pos_rtx = 0;
5876 /* See if this can be done without an extraction. We never can if the
5877 width of the field is not the same as that of some integer mode. For
5878 registers, we can only avoid the extraction if the position is at the
5879 low-order bit and this is either not in the destination or we have the
5880 appropriate STRICT_LOW_PART operation available.
5882 For MEM, we can avoid an extract if the field starts on an appropriate
5883 boundary and we can change the mode of the memory reference. However,
5884 we cannot directly access the MEM if we have a USE and the underlying
5885 MEM is not TMODE. This combination means that MEM was being used in a
5886 context where bits outside its mode were being referenced; that is only
5887 valid in bit-field insns. */
5889 if (tmode != BLKmode
5890 && ! (spans_byte && inner_mode != tmode)
5891 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
5892 && GET_CODE (inner) != MEM
5894 || (GET_CODE (inner) == REG
5895 && (movstrict_optab->handlers[(int) tmode].insn_code
5896 != CODE_FOR_nothing))))
5897 || (GET_CODE (inner) == MEM && pos_rtx == 0
5899 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
5900 : BITS_PER_UNIT)) == 0
5901 /* We can't do this if we are widening INNER_MODE (it
5902 may not be aligned, for one thing). */
5903 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
5904 && (inner_mode == tmode
5905 || (! mode_dependent_address_p (XEXP (inner, 0))
5906 && ! MEM_VOLATILE_P (inner))))))
5908 /* If INNER is a MEM, make a new MEM that encompasses just the desired
5909 field. If the original and current mode are the same, we need not
5910 adjust the offset. Otherwise, we do if bytes big endian.
5912 If INNER is not a MEM, get a piece consisting of just the field
5913 of interest (in this case POS % BITS_PER_WORD must be 0). */
5915 if (GET_CODE (inner) == MEM)
5918 /* POS counts from lsb, but make OFFSET count in memory order. */
5919 if (BYTES_BIG_ENDIAN)
5920 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
5922 offset = pos / BITS_PER_UNIT;
5924 new = gen_rtx_MEM (tmode, plus_constant (XEXP (inner, 0), offset));
5925 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (inner);
5926 MEM_COPY_ATTRIBUTES (new, inner);
5928 else if (GET_CODE (inner) == REG)
5930 /* We can't call gen_lowpart_for_combine here since we always want
5931 a SUBREG and it would sometimes return a new hard register. */
5932 if (tmode != inner_mode)
5933 new = gen_rtx_SUBREG (tmode, inner,
5935 && (GET_MODE_SIZE (inner_mode)
5937 ? (((GET_MODE_SIZE (inner_mode)
5938 - GET_MODE_SIZE (tmode))
5940 - pos / BITS_PER_WORD)
5941 : pos / BITS_PER_WORD));
5946 new = force_to_mode (inner, tmode,
5947 len >= HOST_BITS_PER_WIDE_INT
5948 ? GET_MODE_MASK (tmode)
5949 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
5952 /* If this extraction is going into the destination of a SET,
5953 make a STRICT_LOW_PART unless we made a MEM. */
5956 return (GET_CODE (new) == MEM ? new
5957 : (GET_CODE (new) != SUBREG
5958 ? gen_rtx_CLOBBER (tmode, const0_rtx)
5959 : gen_rtx_combine (STRICT_LOW_PART, VOIDmode, new)));
5964 /* If we know that no extraneous bits are set, and that the high
5965 bit is not set, convert the extraction to the cheaper of
5966 sign and zero extension, that are equivalent in these cases. */
5967 if (flag_expensive_optimizations
5968 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
5969 && ((nonzero_bits (new, tmode)
5970 & ~ (((unsigned HOST_WIDE_INT)
5971 GET_MODE_MASK (tmode))
5975 rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
5976 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
5978 /* Prefer ZERO_EXTENSION, since it gives more information to
5980 if (rtx_cost (temp, SET) < rtx_cost (temp1, SET))
5985 /* Otherwise, sign- or zero-extend unless we already are in the
5988 return (gen_rtx_combine (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
5992 /* Unless this is a COMPARE or we have a funny memory reference,
5993 don't do anything with zero-extending field extracts starting at
5994 the low-order bit since they are simple AND operations. */
5995 if (pos_rtx == 0 && pos == 0 && ! in_dest
5996 && ! in_compare && ! spans_byte && unsignedp)
5999 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6000 we would be spanning bytes or if the position is not a constant and the
6001 length is not 1. In all other cases, we would only be going outside
6002 our object in cases when an original shift would have been
6004 if (! spans_byte && GET_CODE (inner) == MEM
6005 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6006 || (pos_rtx != 0 && len != 1)))
6009 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6010 and the mode for the result. */
6014 wanted_inner_reg_mode
6015 = insn_data[(int) CODE_FOR_insv].operand[0].mode;
6016 if (wanted_inner_reg_mode == VOIDmode)
6017 wanted_inner_reg_mode = word_mode;
6019 pos_mode = insn_data[(int) CODE_FOR_insv].operand[2].mode;
6020 if (pos_mode == VOIDmode)
6021 pos_mode = word_mode;
6023 extraction_mode = insn_data[(int) CODE_FOR_insv].operand[3].mode;
6024 if (extraction_mode == VOIDmode)
6025 extraction_mode = word_mode;
6030 if (! in_dest && unsignedp)
6032 wanted_inner_reg_mode
6033 = insn_data[(int) CODE_FOR_extzv].operand[1].mode;
6034 if (wanted_inner_reg_mode == VOIDmode)
6035 wanted_inner_reg_mode = word_mode;
6037 pos_mode = insn_data[(int) CODE_FOR_extzv].operand[3].mode;
6038 if (pos_mode == VOIDmode)
6039 pos_mode = word_mode;
6041 extraction_mode = insn_data[(int) CODE_FOR_extzv].operand[0].mode;
6042 if (extraction_mode == VOIDmode)
6043 extraction_mode = word_mode;
6048 if (! in_dest && ! unsignedp)
6050 wanted_inner_reg_mode
6051 = insn_data[(int) CODE_FOR_extv].operand[1].mode;
6052 if (wanted_inner_reg_mode == VOIDmode)
6053 wanted_inner_reg_mode = word_mode;
6055 pos_mode = insn_data[(int) CODE_FOR_extv].operand[3].mode;
6056 if (pos_mode == VOIDmode)
6057 pos_mode = word_mode;
6059 extraction_mode = insn_data[(int) CODE_FOR_extv].operand[0].mode;
6060 if (extraction_mode == VOIDmode)
6061 extraction_mode = word_mode;
6065 /* Never narrow an object, since that might not be safe. */
6067 if (mode != VOIDmode
6068 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6069 extraction_mode = mode;
6071 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6072 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6073 pos_mode = GET_MODE (pos_rtx);
6075 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6076 if we have to change the mode of memory and cannot, the desired mode is
6078 if (GET_CODE (inner) != MEM)
6079 wanted_inner_mode = wanted_inner_reg_mode;
6080 else if (inner_mode != wanted_inner_mode
6081 && (mode_dependent_address_p (XEXP (inner, 0))
6082 || MEM_VOLATILE_P (inner)))
6083 wanted_inner_mode = extraction_mode;
6087 if (BITS_BIG_ENDIAN)
6089 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6090 BITS_BIG_ENDIAN style. If position is constant, compute new
6091 position. Otherwise, build subtraction.
6092 Note that POS is relative to the mode of the original argument.
6093 If it's a MEM we need to recompute POS relative to that.
6094 However, if we're extracting from (or inserting into) a register,
6095 we want to recompute POS relative to wanted_inner_mode. */
6096 int width = (GET_CODE (inner) == MEM
6097 ? GET_MODE_BITSIZE (is_mode)
6098 : GET_MODE_BITSIZE (wanted_inner_mode));
6101 pos = width - len - pos;
6104 = gen_rtx_combine (MINUS, GET_MODE (pos_rtx),
6105 GEN_INT (width - len), pos_rtx);
6106 /* POS may be less than 0 now, but we check for that below.
6107 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6110 /* If INNER has a wider mode, make it smaller. If this is a constant
6111 extract, try to adjust the byte to point to the byte containing
6113 if (wanted_inner_mode != VOIDmode
6114 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6115 && ((GET_CODE (inner) == MEM
6116 && (inner_mode == wanted_inner_mode
6117 || (! mode_dependent_address_p (XEXP (inner, 0))
6118 && ! MEM_VOLATILE_P (inner))))))
6122 /* The computations below will be correct if the machine is big
6123 endian in both bits and bytes or little endian in bits and bytes.
6124 If it is mixed, we must adjust. */
6126 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6127 adjust OFFSET to compensate. */
6128 if (BYTES_BIG_ENDIAN
6130 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6131 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6133 /* If this is a constant position, we can move to the desired byte. */
6136 offset += pos / BITS_PER_UNIT;
6137 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6140 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6142 && is_mode != wanted_inner_mode)
6143 offset = (GET_MODE_SIZE (is_mode)
6144 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6146 if (offset != 0 || inner_mode != wanted_inner_mode)
6148 rtx newmem = gen_rtx_MEM (wanted_inner_mode,
6149 plus_constant (XEXP (inner, 0), offset));
6150 RTX_UNCHANGING_P (newmem) = RTX_UNCHANGING_P (inner);
6151 MEM_COPY_ATTRIBUTES (newmem, inner);
6156 /* If INNER is not memory, we can always get it into the proper mode. If we
6157 are changing its mode, POS must be a constant and smaller than the size
6159 else if (GET_CODE (inner) != MEM)
6161 if (GET_MODE (inner) != wanted_inner_mode
6163 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6166 inner = force_to_mode (inner, wanted_inner_mode,
6168 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6169 ? GET_MODE_MASK (wanted_inner_mode)
6170 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6175 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6176 have to zero extend. Otherwise, we can just use a SUBREG. */
6178 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6180 rtx temp = gen_rtx_combine (ZERO_EXTEND, pos_mode, pos_rtx);
6182 /* If we know that no extraneous bits are set, and that the high
6183 bit is not set, convert extraction to cheaper one - eighter
6184 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6186 if (flag_expensive_optimizations
6187 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6188 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6189 & ~ (((unsigned HOST_WIDE_INT)
6190 GET_MODE_MASK (GET_MODE (pos_rtx)))
6194 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6196 /* Preffer ZERO_EXTENSION, since it gives more information to
6198 if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6203 else if (pos_rtx != 0
6204 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6205 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
6207 /* Make POS_RTX unless we already have it and it is correct. If we don't
6208 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6210 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6211 pos_rtx = orig_pos_rtx;
6213 else if (pos_rtx == 0)
6214 pos_rtx = GEN_INT (pos);
6216 /* Make the required operation. See if we can use existing rtx. */
6217 new = gen_rtx_combine (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6218 extraction_mode, inner, GEN_INT (len), pos_rtx);
6220 new = gen_lowpart_for_combine (mode, new);
6225 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6226 with any other operations in X. Return X without that shift if so. */
6229 extract_left_shift (x, count)
6233 enum rtx_code code = GET_CODE (x);
6234 enum machine_mode mode = GET_MODE (x);
6240 /* This is the shift itself. If it is wide enough, we will return
6241 either the value being shifted if the shift count is equal to
6242 COUNT or a shift for the difference. */
6243 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6244 && INTVAL (XEXP (x, 1)) >= count)
6245 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6246 INTVAL (XEXP (x, 1)) - count);
6250 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6251 return gen_unary (code, mode, mode, tem);
6255 case PLUS: case IOR: case XOR: case AND:
6256 /* If we can safely shift this constant and we find the inner shift,
6257 make a new operation. */
6258 if (GET_CODE (XEXP (x,1)) == CONST_INT
6259 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6260 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6261 return gen_binary (code, mode, tem,
6262 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6273 /* Look at the expression rooted at X. Look for expressions
6274 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6275 Form these expressions.
6277 Return the new rtx, usually just X.
6279 Also, for machines like the Vax that don't have logical shift insns,
6280 try to convert logical to arithmetic shift operations in cases where
6281 they are equivalent. This undoes the canonicalizations to logical
6282 shifts done elsewhere.
6284 We try, as much as possible, to re-use rtl expressions to save memory.
6286 IN_CODE says what kind of expression we are processing. Normally, it is
6287 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6288 being kludges), it is MEM. When processing the arguments of a comparison
6289 or a COMPARE against zero, it is COMPARE. */
6292 make_compound_operation (x, in_code)
6294 enum rtx_code in_code;
6296 enum rtx_code code = GET_CODE (x);
6297 enum machine_mode mode = GET_MODE (x);
6298 int mode_width = GET_MODE_BITSIZE (mode);
6300 enum rtx_code next_code;
6306 /* Select the code to be used in recursive calls. Once we are inside an
6307 address, we stay there. If we have a comparison, set to COMPARE,
6308 but once inside, go back to our default of SET. */
6310 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6311 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
6312 && XEXP (x, 1) == const0_rtx) ? COMPARE
6313 : in_code == COMPARE ? SET : in_code);
6315 /* Process depending on the code of this operation. If NEW is set
6316 non-zero, it will be returned. */
6321 /* Convert shifts by constants into multiplications if inside
6323 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6324 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6325 && INTVAL (XEXP (x, 1)) >= 0)
6327 new = make_compound_operation (XEXP (x, 0), next_code);
6328 new = gen_rtx_combine (MULT, mode, new,
6329 GEN_INT ((HOST_WIDE_INT) 1
6330 << INTVAL (XEXP (x, 1))));
6335 /* If the second operand is not a constant, we can't do anything
6337 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6340 /* If the constant is a power of two minus one and the first operand
6341 is a logical right shift, make an extraction. */
6342 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6343 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6345 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6346 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6347 0, in_code == COMPARE);
6350 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6351 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6352 && subreg_lowpart_p (XEXP (x, 0))
6353 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6354 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6356 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6358 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6359 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6360 0, in_code == COMPARE);
6362 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6363 else if ((GET_CODE (XEXP (x, 0)) == XOR
6364 || GET_CODE (XEXP (x, 0)) == IOR)
6365 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6366 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6367 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6369 /* Apply the distributive law, and then try to make extractions. */
6370 new = gen_rtx_combine (GET_CODE (XEXP (x, 0)), mode,
6371 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6373 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6375 new = make_compound_operation (new, in_code);
6378 /* If we are have (and (rotate X C) M) and C is larger than the number
6379 of bits in M, this is an extraction. */
6381 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6382 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6383 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6384 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6386 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6387 new = make_extraction (mode, new,
6388 (GET_MODE_BITSIZE (mode)
6389 - INTVAL (XEXP (XEXP (x, 0), 1))),
6390 NULL_RTX, i, 1, 0, in_code == COMPARE);
6393 /* On machines without logical shifts, if the operand of the AND is
6394 a logical shift and our mask turns off all the propagated sign
6395 bits, we can replace the logical shift with an arithmetic shift. */
6396 else if (ashr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
6397 && (lshr_optab->handlers[(int) mode].insn_code
6398 == CODE_FOR_nothing)
6399 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
6400 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6401 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6402 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6403 && mode_width <= HOST_BITS_PER_WIDE_INT)
6405 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6407 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6408 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6410 gen_rtx_combine (ASHIFTRT, mode,
6411 make_compound_operation (XEXP (XEXP (x, 0), 0),
6413 XEXP (XEXP (x, 0), 1)));
6416 /* If the constant is one less than a power of two, this might be
6417 representable by an extraction even if no shift is present.
6418 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6419 we are in a COMPARE. */
6420 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6421 new = make_extraction (mode,
6422 make_compound_operation (XEXP (x, 0),
6424 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6426 /* If we are in a comparison and this is an AND with a power of two,
6427 convert this into the appropriate bit extract. */
6428 else if (in_code == COMPARE
6429 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6430 new = make_extraction (mode,
6431 make_compound_operation (XEXP (x, 0),
6433 i, NULL_RTX, 1, 1, 0, 1);
6438 /* If the sign bit is known to be zero, replace this with an
6439 arithmetic shift. */
6440 if (ashr_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing
6441 && lshr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
6442 && mode_width <= HOST_BITS_PER_WIDE_INT
6443 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6445 new = gen_rtx_combine (ASHIFTRT, mode,
6446 make_compound_operation (XEXP (x, 0),
6452 /* ... fall through ... */
6458 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6459 this is a SIGN_EXTRACT. */
6460 if (GET_CODE (rhs) == CONST_INT
6461 && GET_CODE (lhs) == ASHIFT
6462 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6463 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6465 new = make_compound_operation (XEXP (lhs, 0), next_code);
6466 new = make_extraction (mode, new,
6467 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6468 NULL_RTX, mode_width - INTVAL (rhs),
6469 code == LSHIFTRT, 0, in_code == COMPARE);
6472 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6473 If so, try to merge the shifts into a SIGN_EXTEND. We could
6474 also do this for some cases of SIGN_EXTRACT, but it doesn't
6475 seem worth the effort; the case checked for occurs on Alpha. */
6477 if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o'
6478 && ! (GET_CODE (lhs) == SUBREG
6479 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o'))
6480 && GET_CODE (rhs) == CONST_INT
6481 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6482 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6483 new = make_extraction (mode, make_compound_operation (new, next_code),
6484 0, NULL_RTX, mode_width - INTVAL (rhs),
6485 code == LSHIFTRT, 0, in_code == COMPARE);
6490 /* Call ourselves recursively on the inner expression. If we are
6491 narrowing the object and it has a different RTL code from
6492 what it originally did, do this SUBREG as a force_to_mode. */
6494 tem = make_compound_operation (SUBREG_REG (x), in_code);
6495 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6496 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6497 && subreg_lowpart_p (x))
6499 rtx newer = force_to_mode (tem, mode,
6500 GET_MODE_MASK (mode), NULL_RTX, 0);
6502 /* If we have something other than a SUBREG, we might have
6503 done an expansion, so rerun outselves. */
6504 if (GET_CODE (newer) != SUBREG)
6505 newer = make_compound_operation (newer, in_code);
6510 /* If this is a paradoxical subreg, and the new code is a sign or
6511 zero extension, omit the subreg and widen the extension. If it
6512 is a regular subreg, we can still get rid of the subreg by not
6513 widening so much, or in fact removing the extension entirely. */
6514 if ((GET_CODE (tem) == SIGN_EXTEND
6515 || GET_CODE (tem) == ZERO_EXTEND)
6516 && subreg_lowpart_p (x))
6518 if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (tem))
6519 || (GET_MODE_SIZE (mode) >
6520 GET_MODE_SIZE (GET_MODE (XEXP (tem, 0)))))
6521 tem = gen_rtx_combine (GET_CODE (tem), mode, XEXP (tem, 0));
6523 tem = gen_lowpart_for_combine (mode, XEXP (tem, 0));
6534 x = gen_lowpart_for_combine (mode, new);
6535 code = GET_CODE (x);
6538 /* Now recursively process each operand of this operation. */
6539 fmt = GET_RTX_FORMAT (code);
6540 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6543 new = make_compound_operation (XEXP (x, i), next_code);
6544 SUBST (XEXP (x, i), new);
6550 /* Given M see if it is a value that would select a field of bits
6551 within an item, but not the entire word. Return -1 if not.
6552 Otherwise, return the starting position of the field, where 0 is the
6555 *PLEN is set to the length of the field. */
6558 get_pos_from_mask (m, plen)
6559 unsigned HOST_WIDE_INT m;
6560 unsigned HOST_WIDE_INT *plen;
6562 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6563 int pos = exact_log2 (m & - m);
6568 /* Now shift off the low-order zero bits and see if we have a power of
6570 *plen = exact_log2 ((m >> pos) + 1);
6578 /* See if X can be simplified knowing that we will only refer to it in
6579 MODE and will only refer to those bits that are nonzero in MASK.
6580 If other bits are being computed or if masking operations are done
6581 that select a superset of the bits in MASK, they can sometimes be
6584 Return a possibly simplified expression, but always convert X to
6585 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6587 Also, if REG is non-zero and X is a register equal in value to REG,
6590 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6591 are all off in X. This is used when X will be complemented, by either
6592 NOT, NEG, or XOR. */
6595 force_to_mode (x, mode, mask, reg, just_select)
6597 enum machine_mode mode;
6598 unsigned HOST_WIDE_INT mask;
6602 enum rtx_code code = GET_CODE (x);
6603 int next_select = just_select || code == XOR || code == NOT || code == NEG;
6604 enum machine_mode op_mode;
6605 unsigned HOST_WIDE_INT fuller_mask, nonzero;
6608 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6609 code below will do the wrong thing since the mode of such an
6610 expression is VOIDmode.
6612 Also do nothing if X is a CLOBBER; this can happen if X was
6613 the return value from a call to gen_lowpart_for_combine. */
6614 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6617 /* We want to perform the operation is its present mode unless we know
6618 that the operation is valid in MODE, in which case we do the operation
6620 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6621 && code_to_optab[(int) code] != 0
6622 && (code_to_optab[(int) code]->handlers[(int) mode].insn_code
6623 != CODE_FOR_nothing))
6624 ? mode : GET_MODE (x));
6626 /* It is not valid to do a right-shift in a narrower mode
6627 than the one it came in with. */
6628 if ((code == LSHIFTRT || code == ASHIFTRT)
6629 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6630 op_mode = GET_MODE (x);
6632 /* Truncate MASK to fit OP_MODE. */
6634 mask &= GET_MODE_MASK (op_mode);
6636 /* When we have an arithmetic operation, or a shift whose count we
6637 do not know, we need to assume that all bit the up to the highest-order
6638 bit in MASK will be needed. This is how we form such a mask. */
6640 fuller_mask = (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT
6641 ? GET_MODE_MASK (op_mode)
6642 : (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
6645 fuller_mask = ~ (HOST_WIDE_INT) 0;
6647 /* Determine what bits of X are guaranteed to be (non)zero. */
6648 nonzero = nonzero_bits (x, mode);
6650 /* If none of the bits in X are needed, return a zero. */
6651 if (! just_select && (nonzero & mask) == 0)
6654 /* If X is a CONST_INT, return a new one. Do this here since the
6655 test below will fail. */
6656 if (GET_CODE (x) == CONST_INT)
6658 HOST_WIDE_INT cval = INTVAL (x) & mask;
6659 int width = GET_MODE_BITSIZE (mode);
6661 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6662 number, sign extend it. */
6663 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6664 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6665 cval |= (HOST_WIDE_INT) -1 << width;
6667 return GEN_INT (cval);
6670 /* If X is narrower than MODE and we want all the bits in X's mode, just
6671 get X in the proper mode. */
6672 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6673 && (GET_MODE_MASK (GET_MODE (x)) & ~ mask) == 0)
6674 return gen_lowpart_for_combine (mode, x);
6676 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6677 MASK are already known to be zero in X, we need not do anything. */
6678 if (GET_MODE (x) == mode && code != SUBREG && (~ mask & nonzero) == 0)
6684 /* If X is a (clobber (const_int)), return it since we know we are
6685 generating something that won't match. */
6689 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6690 spanned the boundary of the MEM. If we are now masking so it is
6691 within that boundary, we don't need the USE any more. */
6692 if (! BITS_BIG_ENDIAN
6693 && (mask & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6694 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6701 x = expand_compound_operation (x);
6702 if (GET_CODE (x) != code)
6703 return force_to_mode (x, mode, mask, reg, next_select);
6707 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6708 || rtx_equal_p (reg, get_last_value (x))))
6713 if (subreg_lowpart_p (x)
6714 /* We can ignore the effect of this SUBREG if it narrows the mode or
6715 if the constant masks to zero all the bits the mode doesn't
6717 && ((GET_MODE_SIZE (GET_MODE (x))
6718 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6720 & GET_MODE_MASK (GET_MODE (x))
6721 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6722 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
6726 /* If this is an AND with a constant, convert it into an AND
6727 whose constant is the AND of that constant with MASK. If it
6728 remains an AND of MASK, delete it since it is redundant. */
6730 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6732 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6733 mask & INTVAL (XEXP (x, 1)));
6735 /* If X is still an AND, see if it is an AND with a mask that
6736 is just some low-order bits. If so, and it is MASK, we don't
6739 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6740 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) == mask)
6743 /* If it remains an AND, try making another AND with the bits
6744 in the mode mask that aren't in MASK turned on. If the
6745 constant in the AND is wide enough, this might make a
6746 cheaper constant. */
6748 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6749 && GET_MODE_MASK (GET_MODE (x)) != mask
6750 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6752 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6753 | (GET_MODE_MASK (GET_MODE (x)) & ~ mask));
6754 int width = GET_MODE_BITSIZE (GET_MODE (x));
6757 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6758 number, sign extend it. */
6759 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6760 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6761 cval |= (HOST_WIDE_INT) -1 << width;
6763 y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
6764 if (rtx_cost (y, SET) < rtx_cost (x, SET))
6774 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6775 low-order bits (as in an alignment operation) and FOO is already
6776 aligned to that boundary, mask C1 to that boundary as well.
6777 This may eliminate that PLUS and, later, the AND. */
6780 unsigned int width = GET_MODE_BITSIZE (mode);
6781 unsigned HOST_WIDE_INT smask = mask;
6783 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6784 number, sign extend it. */
6786 if (width < HOST_BITS_PER_WIDE_INT
6787 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6788 smask |= (HOST_WIDE_INT) -1 << width;
6790 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6791 && exact_log2 (- smask) >= 0)
6795 && (XEXP (x, 0) == stack_pointer_rtx
6796 || XEXP (x, 0) == frame_pointer_rtx))
6798 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
6799 unsigned HOST_WIDE_INT sp_mask = GET_MODE_MASK (mode);
6801 sp_mask &= ~ (sp_alignment - 1);
6802 if ((sp_mask & ~ smask) == 0
6803 && ((INTVAL (XEXP (x, 1)) - STACK_BIAS) & ~ smask) != 0)
6804 return force_to_mode (plus_constant (XEXP (x, 0),
6805 ((INTVAL (XEXP (x, 1)) -
6806 STACK_BIAS) & smask)
6808 mode, smask, reg, next_select);
6811 if ((nonzero_bits (XEXP (x, 0), mode) & ~ smask) == 0
6812 && (INTVAL (XEXP (x, 1)) & ~ smask) != 0)
6813 return force_to_mode (plus_constant (XEXP (x, 0),
6814 (INTVAL (XEXP (x, 1))
6816 mode, smask, reg, next_select);
6820 /* ... fall through ... */
6824 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6825 most significant bit in MASK since carries from those bits will
6826 affect the bits we are interested in. */
6832 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6833 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6834 operation which may be a bitfield extraction. Ensure that the
6835 constant we form is not wider than the mode of X. */
6837 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6838 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6839 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6840 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6841 && GET_CODE (XEXP (x, 1)) == CONST_INT
6842 && ((INTVAL (XEXP (XEXP (x, 0), 1))
6843 + floor_log2 (INTVAL (XEXP (x, 1))))
6844 < GET_MODE_BITSIZE (GET_MODE (x)))
6845 && (INTVAL (XEXP (x, 1))
6846 & ~ nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
6848 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
6849 << INTVAL (XEXP (XEXP (x, 0), 1)));
6850 temp = gen_binary (GET_CODE (x), GET_MODE (x),
6851 XEXP (XEXP (x, 0), 0), temp);
6852 x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
6853 XEXP (XEXP (x, 0), 1));
6854 return force_to_mode (x, mode, mask, reg, next_select);
6858 /* For most binary operations, just propagate into the operation and
6859 change the mode if we have an operation of that mode. */
6861 op0 = gen_lowpart_for_combine (op_mode,
6862 force_to_mode (XEXP (x, 0), mode, mask,
6864 op1 = gen_lowpart_for_combine (op_mode,
6865 force_to_mode (XEXP (x, 1), mode, mask,
6868 /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside
6869 MASK since OP1 might have been sign-extended but we never want
6870 to turn on extra bits, since combine might have previously relied
6871 on them being off. */
6872 if (GET_CODE (op1) == CONST_INT && (code == IOR || code == XOR)
6873 && (INTVAL (op1) & mask) != 0)
6874 op1 = GEN_INT (INTVAL (op1) & mask);
6876 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6877 x = gen_binary (code, op_mode, op0, op1);
6881 /* For left shifts, do the same, but just for the first operand.
6882 However, we cannot do anything with shifts where we cannot
6883 guarantee that the counts are smaller than the size of the mode
6884 because such a count will have a different meaning in a
6887 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
6888 && INTVAL (XEXP (x, 1)) >= 0
6889 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
6890 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
6891 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
6892 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
6895 /* If the shift count is a constant and we can do arithmetic in
6896 the mode of the shift, refine which bits we need. Otherwise, use the
6897 conservative form of the mask. */
6898 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6899 && INTVAL (XEXP (x, 1)) >= 0
6900 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
6901 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6902 mask >>= INTVAL (XEXP (x, 1));
6906 op0 = gen_lowpart_for_combine (op_mode,
6907 force_to_mode (XEXP (x, 0), op_mode,
6908 mask, reg, next_select));
6910 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6911 x = gen_binary (code, op_mode, op0, XEXP (x, 1));
6915 /* Here we can only do something if the shift count is a constant,
6916 this shift constant is valid for the host, and we can do arithmetic
6919 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6920 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6921 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6923 rtx inner = XEXP (x, 0);
6924 unsigned HOST_WIDE_INT inner_mask;
6926 /* Select the mask of the bits we need for the shift operand. */
6927 inner_mask = mask << INTVAL (XEXP (x, 1));
6929 /* We can only change the mode of the shift if we can do arithmetic
6930 in the mode of the shift and INNER_MASK is no wider than the
6931 width of OP_MODE. */
6932 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT
6933 || (inner_mask & ~ GET_MODE_MASK (op_mode)) != 0)
6934 op_mode = GET_MODE (x);
6936 inner = force_to_mode (inner, op_mode, inner_mask, reg, next_select);
6938 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
6939 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
6942 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
6943 shift and AND produces only copies of the sign bit (C2 is one less
6944 than a power of two), we can do this with just a shift. */
6946 if (GET_CODE (x) == LSHIFTRT
6947 && GET_CODE (XEXP (x, 1)) == CONST_INT
6948 /* The shift puts one of the sign bit copies in the least significant
6950 && ((INTVAL (XEXP (x, 1))
6951 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
6952 >= GET_MODE_BITSIZE (GET_MODE (x)))
6953 && exact_log2 (mask + 1) >= 0
6954 /* Number of bits left after the shift must be more than the mask
6956 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
6957 <= GET_MODE_BITSIZE (GET_MODE (x)))
6958 /* Must be more sign bit copies than the mask needs. */
6959 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6960 >= exact_log2 (mask + 1)))
6961 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
6962 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
6963 - exact_log2 (mask + 1)));
6968 /* If we are just looking for the sign bit, we don't need this shift at
6969 all, even if it has a variable count. */
6970 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6971 && (mask == ((unsigned HOST_WIDE_INT) 1
6972 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
6973 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6975 /* If this is a shift by a constant, get a mask that contains those bits
6976 that are not copies of the sign bit. We then have two cases: If
6977 MASK only includes those bits, this can be a logical shift, which may
6978 allow simplifications. If MASK is a single-bit field not within
6979 those bits, we are requesting a copy of the sign bit and hence can
6980 shift the sign bit to the appropriate location. */
6982 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
6983 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
6987 /* If the considered data is wider then HOST_WIDE_INT, we can't
6988 represent a mask for all its bits in a single scalar.
6989 But we only care about the lower bits, so calculate these. */
6991 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
6993 nonzero = ~ (HOST_WIDE_INT) 0;
6995 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6996 is the number of bits a full-width mask would have set.
6997 We need only shift if these are fewer than nonzero can
6998 hold. If not, we must keep all bits set in nonzero. */
7000 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7001 < HOST_BITS_PER_WIDE_INT)
7002 nonzero >>= INTVAL (XEXP (x, 1))
7003 + HOST_BITS_PER_WIDE_INT
7004 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7008 nonzero = GET_MODE_MASK (GET_MODE (x));
7009 nonzero >>= INTVAL (XEXP (x, 1));
7012 if ((mask & ~ nonzero) == 0
7013 || (i = exact_log2 (mask)) >= 0)
7015 x = simplify_shift_const
7016 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7017 i < 0 ? INTVAL (XEXP (x, 1))
7018 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7020 if (GET_CODE (x) != ASHIFTRT)
7021 return force_to_mode (x, mode, mask, reg, next_select);
7025 /* If MASK is 1, convert this to a LSHIFTRT. This can be done
7026 even if the shift count isn't a constant. */
7028 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
7032 /* If this is a zero- or sign-extension operation that just affects bits
7033 we don't care about, remove it. Be sure the call above returned
7034 something that is still a shift. */
7036 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7037 && GET_CODE (XEXP (x, 1)) == CONST_INT
7038 && INTVAL (XEXP (x, 1)) >= 0
7039 && (INTVAL (XEXP (x, 1))
7040 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7041 && GET_CODE (XEXP (x, 0)) == ASHIFT
7042 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7043 && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1)))
7044 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7051 /* If the shift count is constant and we can do computations
7052 in the mode of X, compute where the bits we care about are.
7053 Otherwise, we can't do anything. Don't change the mode of
7054 the shift or propagate MODE into the shift, though. */
7055 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7056 && INTVAL (XEXP (x, 1)) >= 0)
7058 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7059 GET_MODE (x), GEN_INT (mask),
7061 if (temp && GET_CODE(temp) == CONST_INT)
7063 force_to_mode (XEXP (x, 0), GET_MODE (x),
7064 INTVAL (temp), reg, next_select));
7069 /* If we just want the low-order bit, the NEG isn't needed since it
7070 won't change the low-order bit. */
7072 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
7074 /* We need any bits less significant than the most significant bit in
7075 MASK since carries from those bits will affect the bits we are
7081 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7082 same as the XOR case above. Ensure that the constant we form is not
7083 wider than the mode of X. */
7085 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7086 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7087 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7088 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7089 < GET_MODE_BITSIZE (GET_MODE (x)))
7090 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7092 temp = GEN_INT (mask << INTVAL (XEXP (XEXP (x, 0), 1)));
7093 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
7094 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
7096 return force_to_mode (x, mode, mask, reg, next_select);
7099 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7100 use the full mask inside the NOT. */
7104 op0 = gen_lowpart_for_combine (op_mode,
7105 force_to_mode (XEXP (x, 0), mode, mask,
7107 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7108 x = gen_unary (code, op_mode, op_mode, op0);
7112 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7113 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7114 which is equal to STORE_FLAG_VALUE. */
7115 if ((mask & ~ STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7116 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7117 && nonzero_bits (XEXP (x, 0), mode) == STORE_FLAG_VALUE)
7118 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7123 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7124 written in a narrower mode. We play it safe and do not do so. */
7127 gen_lowpart_for_combine (GET_MODE (x),
7128 force_to_mode (XEXP (x, 1), mode,
7129 mask, reg, next_select)));
7131 gen_lowpart_for_combine (GET_MODE (x),
7132 force_to_mode (XEXP (x, 2), mode,
7133 mask, reg,next_select)));
7140 /* Ensure we return a value of the proper mode. */
7141 return gen_lowpart_for_combine (mode, x);
7144 /* Return nonzero if X is an expression that has one of two values depending on
7145 whether some other value is zero or nonzero. In that case, we return the
7146 value that is being tested, *PTRUE is set to the value if the rtx being
7147 returned has a nonzero value, and *PFALSE is set to the other alternative.
7149 If we return zero, we set *PTRUE and *PFALSE to X. */
7152 if_then_else_cond (x, ptrue, pfalse)
7154 rtx *ptrue, *pfalse;
7156 enum machine_mode mode = GET_MODE (x);
7157 enum rtx_code code = GET_CODE (x);
7158 unsigned int size = GET_MODE_BITSIZE (mode);
7159 rtx cond0, cond1, true0, true1, false0, false1;
7160 unsigned HOST_WIDE_INT nz;
7162 /* If we are comparing a value against zero, we are done. */
7163 if ((code == NE || code == EQ)
7164 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 0)
7166 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7167 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7171 /* If this is a unary operation whose operand has one of two values, apply
7172 our opcode to compute those values. */
7173 else if (GET_RTX_CLASS (code) == '1'
7174 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7176 *ptrue = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), true0);
7177 *pfalse = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), false0);
7181 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7182 make can't possibly match and would suppress other optimizations. */
7183 else if (code == COMPARE)
7186 /* If this is a binary operation, see if either side has only one of two
7187 values. If either one does or if both do and they are conditional on
7188 the same value, compute the new true and false values. */
7189 else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2'
7190 || GET_RTX_CLASS (code) == '<')
7192 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7193 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7195 if ((cond0 != 0 || cond1 != 0)
7196 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7198 /* If if_then_else_cond returned zero, then true/false are the
7199 same rtl. We must copy one of them to prevent invalid rtl
7202 true0 = copy_rtx (true0);
7203 else if (cond1 == 0)
7204 true1 = copy_rtx (true1);
7206 *ptrue = gen_binary (code, mode, true0, true1);
7207 *pfalse = gen_binary (code, mode, false0, false1);
7208 return cond0 ? cond0 : cond1;
7211 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7212 operands is zero when the other is non-zero, and vice-versa,
7213 and STORE_FLAG_VALUE is 1 or -1. */
7215 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7216 && (code == PLUS || code == IOR || code == XOR || code == MINUS
7218 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7220 rtx op0 = XEXP (XEXP (x, 0), 1);
7221 rtx op1 = XEXP (XEXP (x, 1), 1);
7223 cond0 = XEXP (XEXP (x, 0), 0);
7224 cond1 = XEXP (XEXP (x, 1), 0);
7226 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7227 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7228 && reversible_comparison_p (cond1)
7229 && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
7230 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7231 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7232 || ((swap_condition (GET_CODE (cond0))
7233 == reverse_condition (GET_CODE (cond1)))
7234 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7235 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7236 && ! side_effects_p (x))
7238 *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
7239 *pfalse = gen_binary (MULT, mode,
7241 ? gen_unary (NEG, mode, mode, op1) : op1),
7247 /* Similarly for MULT, AND and UMIN, execpt that for these the result
7249 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7250 && (code == MULT || code == AND || code == UMIN)
7251 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7253 cond0 = XEXP (XEXP (x, 0), 0);
7254 cond1 = XEXP (XEXP (x, 1), 0);
7256 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7257 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7258 && reversible_comparison_p (cond1)
7259 && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
7260 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7261 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7262 || ((swap_condition (GET_CODE (cond0))
7263 == reverse_condition (GET_CODE (cond1)))
7264 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7265 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7266 && ! side_effects_p (x))
7268 *ptrue = *pfalse = const0_rtx;
7274 else if (code == IF_THEN_ELSE)
7276 /* If we have IF_THEN_ELSE already, extract the condition and
7277 canonicalize it if it is NE or EQ. */
7278 cond0 = XEXP (x, 0);
7279 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7280 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7281 return XEXP (cond0, 0);
7282 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7284 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7285 return XEXP (cond0, 0);
7291 /* If X is a normal SUBREG with both inner and outer modes integral,
7292 we can narrow both the true and false values of the inner expression,
7293 if there is a condition. */
7294 else if (code == SUBREG && GET_MODE_CLASS (mode) == MODE_INT
7295 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_INT
7296 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))
7297 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7300 if ((GET_CODE (SUBREG_REG (x)) == REG
7301 || GET_CODE (SUBREG_REG (x)) == MEM
7302 || CONSTANT_P (SUBREG_REG (x)))
7303 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))) > UNITS_PER_WORD
7304 && (WORDS_BIG_ENDIAN || SUBREG_WORD (x) != 0))
7306 true0 = operand_subword (true0, SUBREG_WORD (x), 0, mode);
7307 false0 = operand_subword (false0, SUBREG_WORD (x), 0, mode);
7309 *ptrue = force_to_mode (true0, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
7311 = force_to_mode (false0, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
7316 /* If X is a constant, this isn't special and will cause confusions
7317 if we treat it as such. Likewise if it is equivalent to a constant. */
7318 else if (CONSTANT_P (x)
7319 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7322 /* If X is known to be either 0 or -1, those are the true and
7323 false values when testing X. */
7324 else if (num_sign_bit_copies (x, mode) == size)
7326 *ptrue = constm1_rtx, *pfalse = const0_rtx;
7330 /* Likewise for 0 or a single bit. */
7331 else if (exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7333 *ptrue = GEN_INT (nz), *pfalse = const0_rtx;
7337 /* Otherwise fail; show no condition with true and false values the same. */
7338 *ptrue = *pfalse = x;
7342 /* Return the value of expression X given the fact that condition COND
7343 is known to be true when applied to REG as its first operand and VAL
7344 as its second. X is known to not be shared and so can be modified in
7347 We only handle the simplest cases, and specifically those cases that
7348 arise with IF_THEN_ELSE expressions. */
7351 known_cond (x, cond, reg, val)
7356 enum rtx_code code = GET_CODE (x);
7361 if (side_effects_p (x))
7364 if (cond == EQ && rtx_equal_p (x, reg))
7367 /* If X is (abs REG) and we know something about REG's relationship
7368 with zero, we may be able to simplify this. */
7370 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7373 case GE: case GT: case EQ:
7376 return gen_unary (NEG, GET_MODE (XEXP (x, 0)), GET_MODE (XEXP (x, 0)),
7382 /* The only other cases we handle are MIN, MAX, and comparisons if the
7383 operands are the same as REG and VAL. */
7385 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
7387 if (rtx_equal_p (XEXP (x, 0), val))
7388 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7390 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7392 if (GET_RTX_CLASS (code) == '<')
7394 if (comparison_dominates_p (cond, code))
7395 return const_true_rtx;
7397 code = reverse_condition (code);
7399 && comparison_dominates_p (cond, code))
7404 else if (code == SMAX || code == SMIN
7405 || code == UMIN || code == UMAX)
7407 int unsignedp = (code == UMIN || code == UMAX);
7409 if (code == SMAX || code == UMAX)
7410 cond = reverse_condition (cond);
7415 return unsignedp ? x : XEXP (x, 1);
7417 return unsignedp ? x : XEXP (x, 0);
7419 return unsignedp ? XEXP (x, 1) : x;
7421 return unsignedp ? XEXP (x, 0) : x;
7429 fmt = GET_RTX_FORMAT (code);
7430 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7433 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7434 else if (fmt[i] == 'E')
7435 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7436 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7443 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7444 assignment as a field assignment. */
7447 rtx_equal_for_field_assignment_p (x, y)
7451 if (x == y || rtx_equal_p (x, y))
7454 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7457 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7458 Note that all SUBREGs of MEM are paradoxical; otherwise they
7459 would have been rewritten. */
7460 if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG
7461 && GET_CODE (SUBREG_REG (y)) == MEM
7462 && rtx_equal_p (SUBREG_REG (y),
7463 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x)))
7466 if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG
7467 && GET_CODE (SUBREG_REG (x)) == MEM
7468 && rtx_equal_p (SUBREG_REG (x),
7469 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y)))
7472 /* We used to see if get_last_value of X and Y were the same but that's
7473 not correct. In one direction, we'll cause the assignment to have
7474 the wrong destination and in the case, we'll import a register into this
7475 insn that might have already have been dead. So fail if none of the
7476 above cases are true. */
7480 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7481 Return that assignment if so.
7483 We only handle the most common cases. */
7486 make_field_assignment (x)
7489 rtx dest = SET_DEST (x);
7490 rtx src = SET_SRC (x);
7495 unsigned HOST_WIDE_INT len;
7497 enum machine_mode mode;
7499 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7500 a clear of a one-bit field. We will have changed it to
7501 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7504 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7505 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7506 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7507 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7509 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7512 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7516 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7517 && subreg_lowpart_p (XEXP (src, 0))
7518 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7519 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7520 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7521 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7522 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7524 assign = make_extraction (VOIDmode, dest, 0,
7525 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7528 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7532 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7534 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7535 && XEXP (XEXP (src, 0), 0) == const1_rtx
7536 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7538 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7541 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7545 /* The other case we handle is assignments into a constant-position
7546 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7547 a mask that has all one bits except for a group of zero bits and
7548 OTHER is known to have zeros where C1 has ones, this is such an
7549 assignment. Compute the position and length from C1. Shift OTHER
7550 to the appropriate position, force it to the required mode, and
7551 make the extraction. Check for the AND in both operands. */
7553 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7556 rhs = expand_compound_operation (XEXP (src, 0));
7557 lhs = expand_compound_operation (XEXP (src, 1));
7559 if (GET_CODE (rhs) == AND
7560 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7561 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7562 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7563 else if (GET_CODE (lhs) == AND
7564 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7565 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7566 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7570 pos = get_pos_from_mask ((~ c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7571 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7572 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7573 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7576 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7580 /* The mode to use for the source is the mode of the assignment, or of
7581 what is inside a possible STRICT_LOW_PART. */
7582 mode = (GET_CODE (assign) == STRICT_LOW_PART
7583 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7585 /* Shift OTHER right POS places and make it the source, restricting it
7586 to the proper length and mode. */
7588 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
7589 GET_MODE (src), other, pos),
7591 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7592 ? GET_MODE_MASK (mode)
7593 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7596 return gen_rtx_combine (SET, VOIDmode, assign, src);
7599 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7603 apply_distributive_law (x)
7606 enum rtx_code code = GET_CODE (x);
7607 rtx lhs, rhs, other;
7609 enum rtx_code inner_code;
7611 /* Distributivity is not true for floating point.
7612 It can change the value. So don't do it.
7613 -- rms and moshier@world.std.com. */
7614 if (FLOAT_MODE_P (GET_MODE (x)))
7617 /* The outer operation can only be one of the following: */
7618 if (code != IOR && code != AND && code != XOR
7619 && code != PLUS && code != MINUS)
7622 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
7624 /* If either operand is a primitive we can't do anything, so get out
7626 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
7627 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
7630 lhs = expand_compound_operation (lhs);
7631 rhs = expand_compound_operation (rhs);
7632 inner_code = GET_CODE (lhs);
7633 if (inner_code != GET_CODE (rhs))
7636 /* See if the inner and outer operations distribute. */
7643 /* These all distribute except over PLUS. */
7644 if (code == PLUS || code == MINUS)
7649 if (code != PLUS && code != MINUS)
7654 /* This is also a multiply, so it distributes over everything. */
7658 /* Non-paradoxical SUBREGs distributes over all operations, provided
7659 the inner modes and word numbers are the same, this is an extraction
7660 of a low-order part, we don't convert an fp operation to int or
7661 vice versa, and we would not be converting a single-word
7662 operation into a multi-word operation. The latter test is not
7663 required, but it prevents generating unneeded multi-word operations.
7664 Some of the previous tests are redundant given the latter test, but
7665 are retained because they are required for correctness.
7667 We produce the result slightly differently in this case. */
7669 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7670 || SUBREG_WORD (lhs) != SUBREG_WORD (rhs)
7671 || ! subreg_lowpart_p (lhs)
7672 || (GET_MODE_CLASS (GET_MODE (lhs))
7673 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7674 || (GET_MODE_SIZE (GET_MODE (lhs))
7675 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7676 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
7679 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7680 SUBREG_REG (lhs), SUBREG_REG (rhs));
7681 return gen_lowpart_for_combine (GET_MODE (x), tem);
7687 /* Set LHS and RHS to the inner operands (A and B in the example
7688 above) and set OTHER to the common operand (C in the example).
7689 These is only one way to do this unless the inner operation is
7691 if (GET_RTX_CLASS (inner_code) == 'c'
7692 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
7693 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
7694 else if (GET_RTX_CLASS (inner_code) == 'c'
7695 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7696 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7697 else if (GET_RTX_CLASS (inner_code) == 'c'
7698 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
7699 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
7700 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
7701 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
7705 /* Form the new inner operation, seeing if it simplifies first. */
7706 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
7708 /* There is one exception to the general way of distributing:
7709 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
7710 if (code == XOR && inner_code == IOR)
7713 other = gen_unary (NOT, GET_MODE (x), GET_MODE (x), other);
7716 /* We may be able to continuing distributing the result, so call
7717 ourselves recursively on the inner operation before forming the
7718 outer operation, which we return. */
7719 return gen_binary (inner_code, GET_MODE (x),
7720 apply_distributive_law (tem), other);
7723 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7726 Return an equivalent form, if different from X. Otherwise, return X. If
7727 X is zero, we are to always construct the equivalent form. */
7730 simplify_and_const_int (x, mode, varop, constop)
7732 enum machine_mode mode;
7734 unsigned HOST_WIDE_INT constop;
7736 unsigned HOST_WIDE_INT nonzero;
7739 /* Simplify VAROP knowing that we will be only looking at some of the
7741 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
7743 /* If VAROP is a CLOBBER, we will fail so return it; if it is a
7744 CONST_INT, we are done. */
7745 if (GET_CODE (varop) == CLOBBER || GET_CODE (varop) == CONST_INT)
7748 /* See what bits may be nonzero in VAROP. Unlike the general case of
7749 a call to nonzero_bits, here we don't care about bits outside
7752 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
7753 nonzero = trunc_int_for_mode (nonzero, mode);
7755 /* Turn off all bits in the constant that are known to already be zero.
7756 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7757 which is tested below. */
7761 /* If we don't have any bits left, return zero. */
7765 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7766 a power of two, we can replace this with a ASHIFT. */
7767 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
7768 && (i = exact_log2 (constop)) >= 0)
7769 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
7771 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7772 or XOR, then try to apply the distributive law. This may eliminate
7773 operations if either branch can be simplified because of the AND.
7774 It may also make some cases more complex, but those cases probably
7775 won't match a pattern either with or without this. */
7777 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
7779 gen_lowpart_for_combine
7781 apply_distributive_law
7782 (gen_binary (GET_CODE (varop), GET_MODE (varop),
7783 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7784 XEXP (varop, 0), constop),
7785 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7786 XEXP (varop, 1), constop))));
7788 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7789 if we already had one (just check for the simplest cases). */
7790 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
7791 && GET_MODE (XEXP (x, 0)) == mode
7792 && SUBREG_REG (XEXP (x, 0)) == varop)
7793 varop = XEXP (x, 0);
7795 varop = gen_lowpart_for_combine (mode, varop);
7797 /* If we can't make the SUBREG, try to return what we were given. */
7798 if (GET_CODE (varop) == CLOBBER)
7799 return x ? x : varop;
7801 /* If we are only masking insignificant bits, return VAROP. */
7802 if (constop == nonzero)
7805 /* Otherwise, return an AND. See how much, if any, of X we can use. */
7806 else if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
7807 x = gen_binary (AND, mode, varop, GEN_INT (constop));
7811 if (GET_CODE (XEXP (x, 1)) != CONST_INT
7812 || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop)
7813 SUBST (XEXP (x, 1), GEN_INT (constop));
7815 SUBST (XEXP (x, 0), varop);
7821 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
7822 We don't let nonzero_bits recur into num_sign_bit_copies, because that
7823 is less useful. We can't allow both, because that results in exponential
7824 run time recursion. There is a nullstone testcase that triggered
7825 this. This macro avoids accidental uses of num_sign_bit_copies. */
7826 #define num_sign_bit_copies()
7828 /* Given an expression, X, compute which bits in X can be non-zero.
7829 We don't care about bits outside of those defined in MODE.
7831 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
7832 a shift, AND, or zero_extract, we can do better. */
7834 static unsigned HOST_WIDE_INT
7835 nonzero_bits (x, mode)
7837 enum machine_mode mode;
7839 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
7840 unsigned HOST_WIDE_INT inner_nz;
7842 unsigned int mode_width = GET_MODE_BITSIZE (mode);
7845 /* For floating-point values, assume all bits are needed. */
7846 if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode))
7849 /* If X is wider than MODE, use its mode instead. */
7850 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
7852 mode = GET_MODE (x);
7853 nonzero = GET_MODE_MASK (mode);
7854 mode_width = GET_MODE_BITSIZE (mode);
7857 if (mode_width > HOST_BITS_PER_WIDE_INT)
7858 /* Our only callers in this case look for single bit values. So
7859 just return the mode mask. Those tests will then be false. */
7862 #ifndef WORD_REGISTER_OPERATIONS
7863 /* If MODE is wider than X, but both are a single word for both the host
7864 and target machines, we can compute this from which bits of the
7865 object might be nonzero in its own mode, taking into account the fact
7866 that on many CISC machines, accessing an object in a wider mode
7867 causes the high-order bits to become undefined. So they are
7868 not known to be zero. */
7870 if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
7871 && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD
7872 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7873 && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x)))
7875 nonzero &= nonzero_bits (x, GET_MODE (x));
7876 nonzero |= GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x));
7881 code = GET_CODE (x);
7885 #ifdef POINTERS_EXTEND_UNSIGNED
7886 /* If pointers extend unsigned and this is a pointer in Pmode, say that
7887 all the bits above ptr_mode are known to be zero. */
7888 if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
7889 && REGNO_POINTER_FLAG (REGNO (x)))
7890 nonzero &= GET_MODE_MASK (ptr_mode);
7893 #ifdef STACK_BOUNDARY
7894 /* If this is the stack pointer, we may know something about its
7895 alignment. If PUSH_ROUNDING is defined, it is possible for the
7896 stack to be momentarily aligned only to that amount, so we pick
7897 the least alignment. */
7899 /* We can't check for arg_pointer_rtx here, because it is not
7900 guaranteed to have as much alignment as the stack pointer.
7901 In particular, in the Irix6 n64 ABI, the stack has 128 bit
7902 alignment but the argument pointer has only 64 bit alignment. */
7904 if ((x == frame_pointer_rtx
7905 || x == stack_pointer_rtx
7906 || x == hard_frame_pointer_rtx
7907 || (REGNO (x) >= FIRST_VIRTUAL_REGISTER
7908 && REGNO (x) <= LAST_VIRTUAL_REGISTER))
7914 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
7916 #ifdef PUSH_ROUNDING
7917 if (REGNO (x) == STACK_POINTER_REGNUM && PUSH_ARGS)
7918 sp_alignment = MIN (PUSH_ROUNDING (1), sp_alignment);
7921 /* We must return here, otherwise we may get a worse result from
7922 one of the choices below. There is nothing useful below as
7923 far as the stack pointer is concerned. */
7924 return nonzero &= ~ (sp_alignment - 1);
7928 /* If X is a register whose nonzero bits value is current, use it.
7929 Otherwise, if X is a register whose value we can find, use that
7930 value. Otherwise, use the previously-computed global nonzero bits
7931 for this register. */
7933 if (reg_last_set_value[REGNO (x)] != 0
7934 && reg_last_set_mode[REGNO (x)] == mode
7935 && (reg_last_set_label[REGNO (x)] == label_tick
7936 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
7937 && REG_N_SETS (REGNO (x)) == 1
7938 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start,
7940 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
7941 return reg_last_set_nonzero_bits[REGNO (x)];
7943 tem = get_last_value (x);
7947 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7948 /* If X is narrower than MODE and TEM is a non-negative
7949 constant that would appear negative in the mode of X,
7950 sign-extend it for use in reg_nonzero_bits because some
7951 machines (maybe most) will actually do the sign-extension
7952 and this is the conservative approach.
7954 ??? For 2.5, try to tighten up the MD files in this regard
7955 instead of this kludge. */
7957 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width
7958 && GET_CODE (tem) == CONST_INT
7960 && 0 != (INTVAL (tem)
7961 & ((HOST_WIDE_INT) 1
7962 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7963 tem = GEN_INT (INTVAL (tem)
7964 | ((HOST_WIDE_INT) (-1)
7965 << GET_MODE_BITSIZE (GET_MODE (x))));
7967 return nonzero_bits (tem, mode);
7969 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
7970 return reg_nonzero_bits[REGNO (x)] & nonzero;
7975 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7976 /* If X is negative in MODE, sign-extend the value. */
7977 if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD
7978 && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1))))
7979 return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width));
7985 #ifdef LOAD_EXTEND_OP
7986 /* In many, if not most, RISC machines, reading a byte from memory
7987 zeros the rest of the register. Noticing that fact saves a lot
7988 of extra zero-extends. */
7989 if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND)
7990 nonzero &= GET_MODE_MASK (GET_MODE (x));
8000 /* If this produces an integer result, we know which bits are set.
8001 Code here used to clear bits outside the mode of X, but that is
8004 if (GET_MODE_CLASS (mode) == MODE_INT
8005 && mode_width <= HOST_BITS_PER_WIDE_INT)
8006 nonzero = STORE_FLAG_VALUE;
8011 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8012 and num_sign_bit_copies. */
8013 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8014 == GET_MODE_BITSIZE (GET_MODE (x)))
8018 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
8019 nonzero |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x)));
8024 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8025 and num_sign_bit_copies. */
8026 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8027 == GET_MODE_BITSIZE (GET_MODE (x)))
8033 nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode));
8037 nonzero &= nonzero_bits (XEXP (x, 0), mode);
8038 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8039 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8043 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
8044 Otherwise, show all the bits in the outer mode but not the inner
8046 inner_nz = nonzero_bits (XEXP (x, 0), mode);
8047 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8049 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8051 & (((HOST_WIDE_INT) 1
8052 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
8053 inner_nz |= (GET_MODE_MASK (mode)
8054 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
8057 nonzero &= inner_nz;
8061 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
8062 & nonzero_bits (XEXP (x, 1), mode));
8066 case UMIN: case UMAX: case SMIN: case SMAX:
8067 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
8068 | nonzero_bits (XEXP (x, 1), mode));
8071 case PLUS: case MINUS:
8073 case DIV: case UDIV:
8074 case MOD: case UMOD:
8075 /* We can apply the rules of arithmetic to compute the number of
8076 high- and low-order zero bits of these operations. We start by
8077 computing the width (position of the highest-order non-zero bit)
8078 and the number of low-order zero bits for each value. */
8080 unsigned HOST_WIDE_INT nz0 = nonzero_bits (XEXP (x, 0), mode);
8081 unsigned HOST_WIDE_INT nz1 = nonzero_bits (XEXP (x, 1), mode);
8082 int width0 = floor_log2 (nz0) + 1;
8083 int width1 = floor_log2 (nz1) + 1;
8084 int low0 = floor_log2 (nz0 & -nz0);
8085 int low1 = floor_log2 (nz1 & -nz1);
8086 HOST_WIDE_INT op0_maybe_minusp
8087 = (nz0 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
8088 HOST_WIDE_INT op1_maybe_minusp
8089 = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
8090 unsigned int result_width = mode_width;
8098 && (XEXP (x, 0) == stack_pointer_rtx
8099 || XEXP (x, 0) == frame_pointer_rtx)
8100 && GET_CODE (XEXP (x, 1)) == CONST_INT)
8102 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
8104 nz0 = (GET_MODE_MASK (mode) & ~ (sp_alignment - 1));
8105 nz1 = INTVAL (XEXP (x, 1)) - STACK_BIAS;
8106 width0 = floor_log2 (nz0) + 1;
8107 width1 = floor_log2 (nz1) + 1;
8108 low0 = floor_log2 (nz0 & -nz0);
8109 low1 = floor_log2 (nz1 & -nz1);
8112 result_width = MAX (width0, width1) + 1;
8113 result_low = MIN (low0, low1);
8116 result_low = MIN (low0, low1);
8119 result_width = width0 + width1;
8120 result_low = low0 + low1;
8123 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8124 result_width = width0;
8127 result_width = width0;
8130 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8131 result_width = MIN (width0, width1);
8132 result_low = MIN (low0, low1);
8135 result_width = MIN (width0, width1);
8136 result_low = MIN (low0, low1);
8142 if (result_width < mode_width)
8143 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
8146 nonzero &= ~ (((HOST_WIDE_INT) 1 << result_low) - 1);
8151 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8152 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8153 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
8157 /* If this is a SUBREG formed for a promoted variable that has
8158 been zero-extended, we know that at least the high-order bits
8159 are zero, though others might be too. */
8161 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x))
8162 nonzero = (GET_MODE_MASK (GET_MODE (x))
8163 & nonzero_bits (SUBREG_REG (x), GET_MODE (x)));
8165 /* If the inner mode is a single word for both the host and target
8166 machines, we can compute this from which bits of the inner
8167 object might be nonzero. */
8168 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
8169 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8170 <= HOST_BITS_PER_WIDE_INT))
8172 nonzero &= nonzero_bits (SUBREG_REG (x), mode);
8174 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8175 /* If this is a typical RISC machine, we only have to worry
8176 about the way loads are extended. */
8177 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
8179 & (((unsigned HOST_WIDE_INT) 1
8180 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) - 1))))
8182 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) != ZERO_EXTEND)
8185 /* On many CISC machines, accessing an object in a wider mode
8186 causes the high-order bits to become undefined. So they are
8187 not known to be zero. */
8188 if (GET_MODE_SIZE (GET_MODE (x))
8189 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8190 nonzero |= (GET_MODE_MASK (GET_MODE (x))
8191 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
8200 /* The nonzero bits are in two classes: any bits within MODE
8201 that aren't in GET_MODE (x) are always significant. The rest of the
8202 nonzero bits are those that are significant in the operand of
8203 the shift when shifted the appropriate number of bits. This
8204 shows that high-order bits are cleared by the right shift and
8205 low-order bits by left shifts. */
8206 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8207 && INTVAL (XEXP (x, 1)) >= 0
8208 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8210 enum machine_mode inner_mode = GET_MODE (x);
8211 unsigned int width = GET_MODE_BITSIZE (inner_mode);
8212 int count = INTVAL (XEXP (x, 1));
8213 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
8214 unsigned HOST_WIDE_INT op_nonzero = nonzero_bits (XEXP (x, 0), mode);
8215 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
8216 unsigned HOST_WIDE_INT outer = 0;
8218 if (mode_width > width)
8219 outer = (op_nonzero & nonzero & ~ mode_mask);
8221 if (code == LSHIFTRT)
8223 else if (code == ASHIFTRT)
8227 /* If the sign bit may have been nonzero before the shift, we
8228 need to mark all the places it could have been copied to
8229 by the shift as possibly nonzero. */
8230 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
8231 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
8233 else if (code == ASHIFT)
8236 inner = ((inner << (count % width)
8237 | (inner >> (width - (count % width)))) & mode_mask);
8239 nonzero &= (outer | inner);
8244 /* This is at most the number of bits in the mode. */
8245 nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1;
8249 nonzero &= (nonzero_bits (XEXP (x, 1), mode)
8250 | nonzero_bits (XEXP (x, 2), mode));
8260 /* See the macro definition above. */
8261 #undef num_sign_bit_copies
8263 /* Return the number of bits at the high-order end of X that are known to
8264 be equal to the sign bit. X will be used in mode MODE; if MODE is
8265 VOIDmode, X will be used in its own mode. The returned value will always
8266 be between 1 and the number of bits in MODE. */
8269 num_sign_bit_copies (x, mode)
8271 enum machine_mode mode;
8273 enum rtx_code code = GET_CODE (x);
8274 unsigned int bitwidth;
8275 int num0, num1, result;
8276 unsigned HOST_WIDE_INT nonzero;
8279 /* If we weren't given a mode, use the mode of X. If the mode is still
8280 VOIDmode, we don't know anything. Likewise if one of the modes is
8283 if (mode == VOIDmode)
8284 mode = GET_MODE (x);
8286 if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)))
8289 bitwidth = GET_MODE_BITSIZE (mode);
8291 /* For a smaller object, just ignore the high bits. */
8292 if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
8294 num0 = num_sign_bit_copies (x, GET_MODE (x));
8296 num0 - (int) (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth));
8299 if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x)))
8301 #ifndef WORD_REGISTER_OPERATIONS
8302 /* If this machine does not do all register operations on the entire
8303 register and MODE is wider than the mode of X, we can say nothing
8304 at all about the high-order bits. */
8307 /* Likewise on machines that do, if the mode of the object is smaller
8308 than a word and loads of that size don't sign extend, we can say
8309 nothing about the high order bits. */
8310 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
8311 #ifdef LOAD_EXTEND_OP
8312 && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND
8323 #ifdef POINTERS_EXTEND_UNSIGNED
8324 /* If pointers extend signed and this is a pointer in Pmode, say that
8325 all the bits above ptr_mode are known to be sign bit copies. */
8326 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
8327 && REGNO_POINTER_FLAG (REGNO (x)))
8328 return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1;
8331 if (reg_last_set_value[REGNO (x)] != 0
8332 && reg_last_set_mode[REGNO (x)] == mode
8333 && (reg_last_set_label[REGNO (x)] == label_tick
8334 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8335 && REG_N_SETS (REGNO (x)) == 1
8336 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start,
8338 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8339 return reg_last_set_sign_bit_copies[REGNO (x)];
8341 tem = get_last_value (x);
8343 return num_sign_bit_copies (tem, mode);
8345 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0)
8346 return reg_sign_bit_copies[REGNO (x)];
8350 #ifdef LOAD_EXTEND_OP
8351 /* Some RISC machines sign-extend all loads of smaller than a word. */
8352 if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
8353 return MAX (1, ((int) bitwidth
8354 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1));
8359 /* If the constant is negative, take its 1's complement and remask.
8360 Then see how many zero bits we have. */
8361 nonzero = INTVAL (x) & GET_MODE_MASK (mode);
8362 if (bitwidth <= HOST_BITS_PER_WIDE_INT
8363 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8364 nonzero = (~ nonzero) & GET_MODE_MASK (mode);
8366 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
8369 /* If this is a SUBREG for a promoted object that is sign-extended
8370 and we are looking at it in a wider mode, we know that at least the
8371 high-order bits are known to be sign bit copies. */
8373 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
8375 num0 = num_sign_bit_copies (SUBREG_REG (x), mode);
8376 return MAX ((int) bitwidth
8377 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1,
8381 /* For a smaller object, just ignore the high bits. */
8382 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
8384 num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode);
8385 return MAX (1, (num0
8386 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8390 #ifdef WORD_REGISTER_OPERATIONS
8391 #ifdef LOAD_EXTEND_OP
8392 /* For paradoxical SUBREGs on machines where all register operations
8393 affect the entire register, just look inside. Note that we are
8394 passing MODE to the recursive call, so the number of sign bit copies
8395 will remain relative to that mode, not the inner mode. */
8397 /* This works only if loads sign extend. Otherwise, if we get a
8398 reload for the inner part, it may be loaded from the stack, and
8399 then we lose all sign bit copies that existed before the store
8402 if ((GET_MODE_SIZE (GET_MODE (x))
8403 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8404 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND)
8405 return num_sign_bit_copies (SUBREG_REG (x), mode);
8411 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
8412 return MAX (1, (int) bitwidth - INTVAL (XEXP (x, 1)));
8416 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8417 + num_sign_bit_copies (XEXP (x, 0), VOIDmode));
8420 /* For a smaller object, just ignore the high bits. */
8421 num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode);
8422 return MAX (1, (num0 - (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8426 return num_sign_bit_copies (XEXP (x, 0), mode);
8428 case ROTATE: case ROTATERT:
8429 /* If we are rotating left by a number of bits less than the number
8430 of sign bit copies, we can just subtract that amount from the
8432 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8433 && INTVAL (XEXP (x, 1)) >= 0 && INTVAL (XEXP (x, 1)) < bitwidth)
8435 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8436 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
8437 : (int) bitwidth - INTVAL (XEXP (x, 1))));
8442 /* In general, this subtracts one sign bit copy. But if the value
8443 is known to be positive, the number of sign bit copies is the
8444 same as that of the input. Finally, if the input has just one bit
8445 that might be nonzero, all the bits are copies of the sign bit. */
8446 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8447 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8448 return num0 > 1 ? num0 - 1 : 1;
8450 nonzero = nonzero_bits (XEXP (x, 0), mode);
8455 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
8460 case IOR: case AND: case XOR:
8461 case SMIN: case SMAX: case UMIN: case UMAX:
8462 /* Logical operations will preserve the number of sign-bit copies.
8463 MIN and MAX operations always return one of the operands. */
8464 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8465 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8466 return MIN (num0, num1);
8468 case PLUS: case MINUS:
8469 /* For addition and subtraction, we can have a 1-bit carry. However,
8470 if we are subtracting 1 from a positive number, there will not
8471 be such a carry. Furthermore, if the positive number is known to
8472 be 0 or 1, we know the result is either -1 or 0. */
8474 if (code == PLUS && XEXP (x, 1) == constm1_rtx
8475 && bitwidth <= HOST_BITS_PER_WIDE_INT)
8477 nonzero = nonzero_bits (XEXP (x, 0), mode);
8478 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
8479 return (nonzero == 1 || nonzero == 0 ? bitwidth
8480 : bitwidth - floor_log2 (nonzero) - 1);
8483 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8484 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8485 return MAX (1, MIN (num0, num1) - 1);
8488 /* The number of bits of the product is the sum of the number of
8489 bits of both terms. However, unless one of the terms if known
8490 to be positive, we must allow for an additional bit since negating
8491 a negative number can remove one sign bit copy. */
8493 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8494 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8496 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
8498 && (bitwidth > HOST_BITS_PER_WIDE_INT
8499 || (((nonzero_bits (XEXP (x, 0), mode)
8500 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8501 && ((nonzero_bits (XEXP (x, 1), mode)
8502 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))))
8505 return MAX (1, result);
8508 /* The result must be <= the first operand. If the first operand
8509 has the high bit set, we know nothing about the number of sign
8511 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8513 else if ((nonzero_bits (XEXP (x, 0), mode)
8514 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8517 return num_sign_bit_copies (XEXP (x, 0), mode);
8520 /* The result must be <= the scond operand. */
8521 return num_sign_bit_copies (XEXP (x, 1), mode);
8524 /* Similar to unsigned division, except that we have to worry about
8525 the case where the divisor is negative, in which case we have
8527 result = num_sign_bit_copies (XEXP (x, 0), mode);
8529 && (bitwidth > HOST_BITS_PER_WIDE_INT
8530 || (nonzero_bits (XEXP (x, 1), mode)
8531 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8537 result = num_sign_bit_copies (XEXP (x, 1), mode);
8539 && (bitwidth > HOST_BITS_PER_WIDE_INT
8540 || (nonzero_bits (XEXP (x, 1), mode)
8541 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8547 /* Shifts by a constant add to the number of bits equal to the
8549 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8550 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8551 && INTVAL (XEXP (x, 1)) > 0)
8552 num0 = MIN (bitwidth, num0 + INTVAL (XEXP (x, 1)));
8557 /* Left shifts destroy copies. */
8558 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8559 || INTVAL (XEXP (x, 1)) < 0
8560 || INTVAL (XEXP (x, 1)) >= bitwidth)
8563 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8564 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
8567 num0 = num_sign_bit_copies (XEXP (x, 1), mode);
8568 num1 = num_sign_bit_copies (XEXP (x, 2), mode);
8569 return MIN (num0, num1);
8571 case EQ: case NE: case GE: case GT: case LE: case LT:
8572 case GEU: case GTU: case LEU: case LTU:
8573 if (STORE_FLAG_VALUE == -1)
8581 /* If we haven't been able to figure it out by one of the above rules,
8582 see if some of the high-order bits are known to be zero. If so,
8583 count those bits and return one less than that amount. If we can't
8584 safely compute the mask for this mode, always return BITWIDTH. */
8586 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8589 nonzero = nonzero_bits (x, mode);
8590 return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
8591 ? 1 : bitwidth - floor_log2 (nonzero) - 1);
8594 /* Return the number of "extended" bits there are in X, when interpreted
8595 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8596 unsigned quantities, this is the number of high-order zero bits.
8597 For signed quantities, this is the number of copies of the sign bit
8598 minus 1. In both case, this function returns the number of "spare"
8599 bits. For example, if two quantities for which this function returns
8600 at least 1 are added, the addition is known not to overflow.
8602 This function will always return 0 unless called during combine, which
8603 implies that it must be called from a define_split. */
8606 extended_count (x, mode, unsignedp)
8608 enum machine_mode mode;
8611 if (nonzero_sign_valid == 0)
8615 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8616 ? (GET_MODE_BITSIZE (mode) - 1
8617 - floor_log2 (nonzero_bits (x, mode)))
8619 : num_sign_bit_copies (x, mode) - 1);
8622 /* This function is called from `simplify_shift_const' to merge two
8623 outer operations. Specifically, we have already found that we need
8624 to perform operation *POP0 with constant *PCONST0 at the outermost
8625 position. We would now like to also perform OP1 with constant CONST1
8626 (with *POP0 being done last).
8628 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8629 the resulting operation. *PCOMP_P is set to 1 if we would need to
8630 complement the innermost operand, otherwise it is unchanged.
8632 MODE is the mode in which the operation will be done. No bits outside
8633 the width of this mode matter. It is assumed that the width of this mode
8634 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8636 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8637 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8638 result is simply *PCONST0.
8640 If the resulting operation cannot be expressed as one operation, we
8641 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8644 merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
8645 enum rtx_code *pop0;
8646 HOST_WIDE_INT *pconst0;
8648 HOST_WIDE_INT const1;
8649 enum machine_mode mode;
8652 enum rtx_code op0 = *pop0;
8653 HOST_WIDE_INT const0 = *pconst0;
8655 const0 &= GET_MODE_MASK (mode);
8656 const1 &= GET_MODE_MASK (mode);
8658 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8662 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
8665 if (op1 == NIL || op0 == SET)
8668 else if (op0 == NIL)
8669 op0 = op1, const0 = const1;
8671 else if (op0 == op1)
8695 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8696 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8699 /* If the two constants aren't the same, we can't do anything. The
8700 remaining six cases can all be done. */
8701 else if (const0 != const1)
8709 /* (a & b) | b == b */
8711 else /* op1 == XOR */
8712 /* (a ^ b) | b == a | b */
8718 /* (a & b) ^ b == (~a) & b */
8719 op0 = AND, *pcomp_p = 1;
8720 else /* op1 == IOR */
8721 /* (a | b) ^ b == a & ~b */
8722 op0 = AND, *pconst0 = ~ const0;
8727 /* (a | b) & b == b */
8729 else /* op1 == XOR */
8730 /* (a ^ b) & b) == (~a) & b */
8737 /* Check for NO-OP cases. */
8738 const0 &= GET_MODE_MASK (mode);
8740 && (op0 == IOR || op0 == XOR || op0 == PLUS))
8742 else if (const0 == 0 && op0 == AND)
8744 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8748 /* ??? Slightly redundant with the above mask, but not entirely.
8749 Moving this above means we'd have to sign-extend the mode mask
8750 for the final test. */
8751 const0 = trunc_int_for_mode (const0, mode);
8759 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8760 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
8761 that we started with.
8763 The shift is normally computed in the widest mode we find in VAROP, as
8764 long as it isn't a different number of words than RESULT_MODE. Exceptions
8765 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8768 simplify_shift_const (x, code, result_mode, varop, input_count)
8771 enum machine_mode result_mode;
8775 enum rtx_code orig_code = code;
8776 int orig_count = input_count;
8779 enum machine_mode mode = result_mode;
8780 enum machine_mode shift_mode, tmode;
8781 unsigned int mode_words
8782 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8783 /* We form (outer_op (code varop count) (outer_const)). */
8784 enum rtx_code outer_op = NIL;
8785 HOST_WIDE_INT outer_const = 0;
8787 int complement_p = 0;
8790 /* If we were given an invalid count, don't do anything except exactly
8791 what was requested. */
8793 if (input_count < 0 || input_count > (int) GET_MODE_BITSIZE (mode))
8798 return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (input_count));
8801 count = input_count;
8803 /* Unless one of the branches of the `if' in this loop does a `continue',
8804 we will `break' the loop after the `if'. */
8808 /* If we have an operand of (clobber (const_int 0)), just return that
8810 if (GET_CODE (varop) == CLOBBER)
8813 /* If we discovered we had to complement VAROP, leave. Making a NOT
8814 here would cause an infinite loop. */
8818 /* Convert ROTATERT to ROTATE. */
8819 if (code == ROTATERT)
8820 code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count;
8822 /* We need to determine what mode we will do the shift in. If the
8823 shift is a right shift or a ROTATE, we must always do it in the mode
8824 it was originally done in. Otherwise, we can do it in MODE, the
8825 widest mode encountered. */
8827 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8828 ? result_mode : mode);
8830 /* Handle cases where the count is greater than the size of the mode
8831 minus 1. For ASHIFT, use the size minus one as the count (this can
8832 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8833 take the count modulo the size. For other shifts, the result is
8836 Since these shifts are being produced by the compiler by combining
8837 multiple operations, each of which are defined, we know what the
8838 result is supposed to be. */
8840 if (count > GET_MODE_BITSIZE (shift_mode) - 1)
8842 if (code == ASHIFTRT)
8843 count = GET_MODE_BITSIZE (shift_mode) - 1;
8844 else if (code == ROTATE || code == ROTATERT)
8845 count %= GET_MODE_BITSIZE (shift_mode);
8848 /* We can't simply return zero because there may be an
8856 /* An arithmetic right shift of a quantity known to be -1 or 0
8858 if (code == ASHIFTRT
8859 && (num_sign_bit_copies (varop, shift_mode)
8860 == GET_MODE_BITSIZE (shift_mode)))
8866 /* If we are doing an arithmetic right shift and discarding all but
8867 the sign bit copies, this is equivalent to doing a shift by the
8868 bitsize minus one. Convert it into that shift because it will often
8869 allow other simplifications. */
8871 if (code == ASHIFTRT
8872 && (count + num_sign_bit_copies (varop, shift_mode)
8873 >= GET_MODE_BITSIZE (shift_mode)))
8874 count = GET_MODE_BITSIZE (shift_mode) - 1;
8876 /* We simplify the tests below and elsewhere by converting
8877 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8878 `make_compound_operation' will convert it to a ASHIFTRT for
8879 those machines (such as Vax) that don't have a LSHIFTRT. */
8880 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8882 && ((nonzero_bits (varop, shift_mode)
8883 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
8887 switch (GET_CODE (varop))
8893 new = expand_compound_operation (varop);
8902 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8903 minus the width of a smaller mode, we can do this with a
8904 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
8905 if ((code == ASHIFTRT || code == LSHIFTRT)
8906 && ! mode_dependent_address_p (XEXP (varop, 0))
8907 && ! MEM_VOLATILE_P (varop)
8908 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8909 MODE_INT, 1)) != BLKmode)
8911 if (BYTES_BIG_ENDIAN)
8912 new = gen_rtx_MEM (tmode, XEXP (varop, 0));
8914 new = gen_rtx_MEM (tmode,
8915 plus_constant (XEXP (varop, 0),
8916 count / BITS_PER_UNIT));
8917 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (varop);
8918 MEM_COPY_ATTRIBUTES (new, varop);
8919 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
8920 : ZERO_EXTEND, mode, new);
8927 /* Similar to the case above, except that we can only do this if
8928 the resulting mode is the same as that of the underlying
8929 MEM and adjust the address depending on the *bits* endianness
8930 because of the way that bit-field extract insns are defined. */
8931 if ((code == ASHIFTRT || code == LSHIFTRT)
8932 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8933 MODE_INT, 1)) != BLKmode
8934 && tmode == GET_MODE (XEXP (varop, 0)))
8936 if (BITS_BIG_ENDIAN)
8937 new = XEXP (varop, 0);
8940 new = copy_rtx (XEXP (varop, 0));
8941 SUBST (XEXP (new, 0),
8942 plus_constant (XEXP (new, 0),
8943 count / BITS_PER_UNIT));
8946 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
8947 : ZERO_EXTEND, mode, new);
8954 /* If VAROP is a SUBREG, strip it as long as the inner operand has
8955 the same number of words as what we've seen so far. Then store
8956 the widest mode in MODE. */
8957 if (subreg_lowpart_p (varop)
8958 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8959 > GET_MODE_SIZE (GET_MODE (varop)))
8960 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8961 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
8964 varop = SUBREG_REG (varop);
8965 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
8966 mode = GET_MODE (varop);
8972 /* Some machines use MULT instead of ASHIFT because MULT
8973 is cheaper. But it is still better on those machines to
8974 merge two shifts into one. */
8975 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8976 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8979 = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
8980 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
8986 /* Similar, for when divides are cheaper. */
8987 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8988 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8991 = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
8992 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
8998 /* If we are extracting just the sign bit of an arithmetic right
8999 shift, that shift is not needed. */
9000 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1)
9002 varop = XEXP (varop, 0);
9006 /* ... fall through ... */
9011 /* Here we have two nested shifts. The result is usually the
9012 AND of a new shift with a mask. We compute the result below. */
9013 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9014 && INTVAL (XEXP (varop, 1)) >= 0
9015 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
9016 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9017 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9019 enum rtx_code first_code = GET_CODE (varop);
9020 unsigned int first_count = INTVAL (XEXP (varop, 1));
9021 unsigned HOST_WIDE_INT mask;
9024 /* We have one common special case. We can't do any merging if
9025 the inner code is an ASHIFTRT of a smaller mode. However, if
9026 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9027 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9028 we can convert it to
9029 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9030 This simplifies certain SIGN_EXTEND operations. */
9031 if (code == ASHIFT && first_code == ASHIFTRT
9032 && (GET_MODE_BITSIZE (result_mode)
9033 - GET_MODE_BITSIZE (GET_MODE (varop))) == count)
9035 /* C3 has the low-order C1 bits zero. */
9037 mask = (GET_MODE_MASK (mode)
9038 & ~ (((HOST_WIDE_INT) 1 << first_count) - 1));
9040 varop = simplify_and_const_int (NULL_RTX, result_mode,
9041 XEXP (varop, 0), mask);
9042 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
9044 count = first_count;
9049 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9050 than C1 high-order bits equal to the sign bit, we can convert
9051 this to either an ASHIFT or a ASHIFTRT depending on the
9054 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9056 if (code == ASHIFTRT && first_code == ASHIFT
9057 && GET_MODE (varop) == shift_mode
9058 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
9061 varop = XEXP (varop, 0);
9063 signed_count = count - first_count;
9064 if (signed_count < 0)
9065 count = - signed_count, code = ASHIFT;
9067 count = signed_count;
9072 /* There are some cases we can't do. If CODE is ASHIFTRT,
9073 we can only do this if FIRST_CODE is also ASHIFTRT.
9075 We can't do the case when CODE is ROTATE and FIRST_CODE is
9078 If the mode of this shift is not the mode of the outer shift,
9079 we can't do this if either shift is a right shift or ROTATE.
9081 Finally, we can't do any of these if the mode is too wide
9082 unless the codes are the same.
9084 Handle the case where the shift codes are the same
9087 if (code == first_code)
9089 if (GET_MODE (varop) != result_mode
9090 && (code == ASHIFTRT || code == LSHIFTRT
9094 count += first_count;
9095 varop = XEXP (varop, 0);
9099 if (code == ASHIFTRT
9100 || (code == ROTATE && first_code == ASHIFTRT)
9101 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
9102 || (GET_MODE (varop) != result_mode
9103 && (first_code == ASHIFTRT || first_code == LSHIFTRT
9104 || first_code == ROTATE
9105 || code == ROTATE)))
9108 /* To compute the mask to apply after the shift, shift the
9109 nonzero bits of the inner shift the same way the
9110 outer shift will. */
9112 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
9115 = simplify_binary_operation (code, result_mode, mask_rtx,
9118 /* Give up if we can't compute an outer operation to use. */
9120 || GET_CODE (mask_rtx) != CONST_INT
9121 || ! merge_outer_ops (&outer_op, &outer_const, AND,
9123 result_mode, &complement_p))
9126 /* If the shifts are in the same direction, we add the
9127 counts. Otherwise, we subtract them. */
9128 signed_count = count;
9129 if ((code == ASHIFTRT || code == LSHIFTRT)
9130 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
9131 signed_count += first_count;
9133 signed_count -= first_count;
9135 /* If COUNT is positive, the new shift is usually CODE,
9136 except for the two exceptions below, in which case it is
9137 FIRST_CODE. If the count is negative, FIRST_CODE should
9139 if (signed_count > 0
9140 && ((first_code == ROTATE && code == ASHIFT)
9141 || (first_code == ASHIFTRT && code == LSHIFTRT)))
9142 code = first_code, count = signed_count;
9143 else if (signed_count < 0)
9144 code = first_code, count = - signed_count;
9146 count = signed_count;
9148 varop = XEXP (varop, 0);
9152 /* If we have (A << B << C) for any shift, we can convert this to
9153 (A << C << B). This wins if A is a constant. Only try this if
9154 B is not a constant. */
9156 else if (GET_CODE (varop) == code
9157 && GET_CODE (XEXP (varop, 1)) != CONST_INT
9159 = simplify_binary_operation (code, mode,
9163 varop = gen_rtx_combine (code, mode, new, XEXP (varop, 1));
9170 /* Make this fit the case below. */
9171 varop = gen_rtx_combine (XOR, mode, XEXP (varop, 0),
9172 GEN_INT (GET_MODE_MASK (mode)));
9178 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9179 with C the size of VAROP - 1 and the shift is logical if
9180 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9181 we have an (le X 0) operation. If we have an arithmetic shift
9182 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9183 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9185 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9186 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9187 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9188 && (code == LSHIFTRT || code == ASHIFTRT)
9189 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
9190 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9193 varop = gen_rtx_combine (LE, GET_MODE (varop), XEXP (varop, 1),
9196 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9197 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
9202 /* If we have (shift (logical)), move the logical to the outside
9203 to allow it to possibly combine with another logical and the
9204 shift to combine with another shift. This also canonicalizes to
9205 what a ZERO_EXTRACT looks like. Also, some machines have
9206 (and (shift)) insns. */
9208 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9209 && (new = simplify_binary_operation (code, result_mode,
9211 GEN_INT (count))) != 0
9212 && GET_CODE(new) == CONST_INT
9213 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9214 INTVAL (new), result_mode, &complement_p))
9216 varop = XEXP (varop, 0);
9220 /* If we can't do that, try to simplify the shift in each arm of the
9221 logical expression, make a new logical expression, and apply
9222 the inverse distributive law. */
9224 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9225 XEXP (varop, 0), count);
9226 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9227 XEXP (varop, 1), count);
9229 varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
9230 varop = apply_distributive_law (varop);
9237 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9238 says that the sign bit can be tested, FOO has mode MODE, C is
9239 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9240 that may be nonzero. */
9241 if (code == LSHIFTRT
9242 && XEXP (varop, 1) == const0_rtx
9243 && GET_MODE (XEXP (varop, 0)) == result_mode
9244 && count == GET_MODE_BITSIZE (result_mode) - 1
9245 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9246 && ((STORE_FLAG_VALUE
9247 & ((HOST_WIDE_INT) 1
9248 < (GET_MODE_BITSIZE (result_mode) - 1))))
9249 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9250 && merge_outer_ops (&outer_op, &outer_const, XOR,
9251 (HOST_WIDE_INT) 1, result_mode,
9254 varop = XEXP (varop, 0);
9261 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9262 than the number of bits in the mode is equivalent to A. */
9263 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
9264 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9266 varop = XEXP (varop, 0);
9271 /* NEG commutes with ASHIFT since it is multiplication. Move the
9272 NEG outside to allow shifts to combine. */
9274 && merge_outer_ops (&outer_op, &outer_const, NEG,
9275 (HOST_WIDE_INT) 0, result_mode,
9278 varop = XEXP (varop, 0);
9284 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9285 is one less than the number of bits in the mode is
9286 equivalent to (xor A 1). */
9287 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
9288 && XEXP (varop, 1) == constm1_rtx
9289 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9290 && merge_outer_ops (&outer_op, &outer_const, XOR,
9291 (HOST_WIDE_INT) 1, result_mode,
9295 varop = XEXP (varop, 0);
9299 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9300 that might be nonzero in BAR are those being shifted out and those
9301 bits are known zero in FOO, we can replace the PLUS with FOO.
9302 Similarly in the other operand order. This code occurs when
9303 we are computing the size of a variable-size array. */
9305 if ((code == ASHIFTRT || code == LSHIFTRT)
9306 && count < HOST_BITS_PER_WIDE_INT
9307 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9308 && (nonzero_bits (XEXP (varop, 1), result_mode)
9309 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9311 varop = XEXP (varop, 0);
9314 else if ((code == ASHIFTRT || code == LSHIFTRT)
9315 && count < HOST_BITS_PER_WIDE_INT
9316 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9317 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9319 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9320 & nonzero_bits (XEXP (varop, 1),
9323 varop = XEXP (varop, 1);
9327 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9329 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9330 && (new = simplify_binary_operation (ASHIFT, result_mode,
9332 GEN_INT (count))) != 0
9333 && GET_CODE (new) == CONST_INT
9334 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9335 INTVAL (new), result_mode, &complement_p))
9337 varop = XEXP (varop, 0);
9343 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9344 with C the size of VAROP - 1 and the shift is logical if
9345 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9346 we have a (gt X 0) operation. If the shift is arithmetic with
9347 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9348 we have a (neg (gt X 0)) operation. */
9350 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9351 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9352 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
9353 && (code == LSHIFTRT || code == ASHIFTRT)
9354 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9355 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
9356 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9359 varop = gen_rtx_combine (GT, GET_MODE (varop), XEXP (varop, 1),
9362 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9363 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
9370 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9371 if the truncate does not affect the value. */
9372 if (code == LSHIFTRT
9373 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9374 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9375 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9376 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9377 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9379 rtx varop_inner = XEXP (varop, 0);
9382 = gen_rtx_combine (LSHIFTRT, GET_MODE (varop_inner),
9383 XEXP (varop_inner, 0),
9385 + INTVAL (XEXP (varop_inner, 1))));
9386 varop = gen_rtx_combine (TRUNCATE, GET_MODE (varop),
9400 /* We need to determine what mode to do the shift in. If the shift is
9401 a right shift or ROTATE, we must always do it in the mode it was
9402 originally done in. Otherwise, we can do it in MODE, the widest mode
9403 encountered. The code we care about is that of the shift that will
9404 actually be done, not the shift that was originally requested. */
9406 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9407 ? result_mode : mode);
9409 /* We have now finished analyzing the shift. The result should be
9410 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9411 OUTER_OP is non-NIL, it is an operation that needs to be applied
9412 to the result of the shift. OUTER_CONST is the relevant constant,
9413 but we must turn off all bits turned off in the shift.
9415 If we were passed a value for X, see if we can use any pieces of
9416 it. If not, make new rtx. */
9418 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
9419 && GET_CODE (XEXP (x, 1)) == CONST_INT
9420 && INTVAL (XEXP (x, 1)) == count)
9421 const_rtx = XEXP (x, 1);
9423 const_rtx = GEN_INT (count);
9425 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
9426 && GET_MODE (XEXP (x, 0)) == shift_mode
9427 && SUBREG_REG (XEXP (x, 0)) == varop)
9428 varop = XEXP (x, 0);
9429 else if (GET_MODE (varop) != shift_mode)
9430 varop = gen_lowpart_for_combine (shift_mode, varop);
9432 /* If we can't make the SUBREG, try to return what we were given. */
9433 if (GET_CODE (varop) == CLOBBER)
9434 return x ? x : varop;
9436 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
9441 if (x == 0 || GET_CODE (x) != code || GET_MODE (x) != shift_mode)
9442 x = gen_rtx_combine (code, shift_mode, varop, const_rtx);
9444 SUBST (XEXP (x, 0), varop);
9445 SUBST (XEXP (x, 1), const_rtx);
9448 /* If we have an outer operation and we just made a shift, it is
9449 possible that we could have simplified the shift were it not
9450 for the outer operation. So try to do the simplification
9453 if (outer_op != NIL && GET_CODE (x) == code
9454 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9455 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
9456 INTVAL (XEXP (x, 1)));
9458 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
9459 turn off all the bits that the shift would have turned off. */
9460 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9461 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9462 GET_MODE_MASK (result_mode) >> orig_count);
9464 /* Do the remainder of the processing in RESULT_MODE. */
9465 x = gen_lowpart_for_combine (result_mode, x);
9467 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9470 x = gen_unary (NOT, result_mode, result_mode, x);
9472 if (outer_op != NIL)
9474 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9475 outer_const = trunc_int_for_mode (outer_const, result_mode);
9477 if (outer_op == AND)
9478 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9479 else if (outer_op == SET)
9480 /* This means that we have determined that the result is
9481 equivalent to a constant. This should be rare. */
9482 x = GEN_INT (outer_const);
9483 else if (GET_RTX_CLASS (outer_op) == '1')
9484 x = gen_unary (outer_op, result_mode, result_mode, x);
9486 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
9492 /* Like recog, but we receive the address of a pointer to a new pattern.
9493 We try to match the rtx that the pointer points to.
9494 If that fails, we may try to modify or replace the pattern,
9495 storing the replacement into the same pointer object.
9497 Modifications include deletion or addition of CLOBBERs.
9499 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9500 the CLOBBERs are placed.
9502 The value is the final insn code from the pattern ultimately matched,
9506 recog_for_combine (pnewpat, insn, pnotes)
9511 register rtx pat = *pnewpat;
9512 int insn_code_number;
9513 int num_clobbers_to_add = 0;
9517 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9518 we use to indicate that something didn't match. If we find such a
9519 thing, force rejection. */
9520 if (GET_CODE (pat) == PARALLEL)
9521 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9522 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9523 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9526 /* Is the result of combination a valid instruction? */
9527 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9529 /* If it isn't, there is the possibility that we previously had an insn
9530 that clobbered some register as a side effect, but the combined
9531 insn doesn't need to do that. So try once more without the clobbers
9532 unless this represents an ASM insn. */
9534 if (insn_code_number < 0 && ! check_asm_operands (pat)
9535 && GET_CODE (pat) == PARALLEL)
9539 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9540 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9543 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9547 SUBST_INT (XVECLEN (pat, 0), pos);
9550 pat = XVECEXP (pat, 0, 0);
9552 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9555 /* If we had any clobbers to add, make a new pattern than contains
9556 them. Then check to make sure that all of them are dead. */
9557 if (num_clobbers_to_add)
9559 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9560 gen_rtvec (GET_CODE (pat) == PARALLEL
9562 + num_clobbers_to_add)
9563 : num_clobbers_to_add + 1));
9565 if (GET_CODE (pat) == PARALLEL)
9566 for (i = 0; i < XVECLEN (pat, 0); i++)
9567 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9569 XVECEXP (newpat, 0, 0) = pat;
9571 add_clobbers (newpat, insn_code_number);
9573 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9574 i < XVECLEN (newpat, 0); i++)
9576 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
9577 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9579 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9580 XEXP (XVECEXP (newpat, 0, i), 0), notes);
9588 return insn_code_number;
9591 /* Like gen_lowpart but for use by combine. In combine it is not possible
9592 to create any new pseudoregs. However, it is safe to create
9593 invalid memory addresses, because combine will try to recognize
9594 them and all they will do is make the combine attempt fail.
9596 If for some reason this cannot do its job, an rtx
9597 (clobber (const_int 0)) is returned.
9598 An insn containing that will not be recognized. */
9603 gen_lowpart_for_combine (mode, x)
9604 enum machine_mode mode;
9609 if (GET_MODE (x) == mode)
9612 /* We can only support MODE being wider than a word if X is a
9613 constant integer or has a mode the same size. */
9615 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
9616 && ! ((GET_MODE (x) == VOIDmode
9617 && (GET_CODE (x) == CONST_INT
9618 || GET_CODE (x) == CONST_DOUBLE))
9619 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
9620 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9622 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9623 won't know what to do. So we will strip off the SUBREG here and
9624 process normally. */
9625 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
9628 if (GET_MODE (x) == mode)
9632 result = gen_lowpart_common (mode, x);
9634 && GET_CODE (result) == SUBREG
9635 && GET_CODE (SUBREG_REG (result)) == REG
9636 && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER
9637 && (GET_MODE_SIZE (GET_MODE (result))
9638 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (result)))))
9639 REG_CHANGES_SIZE (REGNO (SUBREG_REG (result))) = 1;
9644 if (GET_CODE (x) == MEM)
9646 register int offset = 0;
9649 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9651 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9652 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9654 /* If we want to refer to something bigger than the original memref,
9655 generate a perverse subreg instead. That will force a reload
9656 of the original memref X. */
9657 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
9658 return gen_rtx_SUBREG (mode, x, 0);
9660 if (WORDS_BIG_ENDIAN)
9661 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
9662 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
9664 if (BYTES_BIG_ENDIAN)
9666 /* Adjust the address so that the address-after-the-data is
9668 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
9669 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
9671 new = gen_rtx_MEM (mode, plus_constant (XEXP (x, 0), offset));
9672 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (x);
9673 MEM_COPY_ATTRIBUTES (new, x);
9677 /* If X is a comparison operator, rewrite it in a new mode. This
9678 probably won't match, but may allow further simplifications. */
9679 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
9680 return gen_rtx_combine (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
9682 /* If we couldn't simplify X any other way, just enclose it in a
9683 SUBREG. Normally, this SUBREG won't match, but some patterns may
9684 include an explicit SUBREG or we may simplify it further in combine. */
9689 if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
9690 word = ((GET_MODE_SIZE (GET_MODE (x))
9691 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
9693 return gen_rtx_SUBREG (mode, x, word);
9697 /* Make an rtx expression. This is a subset of gen_rtx and only supports
9698 expressions of 1, 2, or 3 operands, each of which are rtx expressions.
9700 If the identical expression was previously in the insn (in the undobuf),
9701 it will be returned. Only if it is not found will a new expression
9706 gen_rtx_combine VPARAMS ((enum rtx_code code, enum machine_mode mode, ...))
9708 #ifndef ANSI_PROTOTYPES
9710 enum machine_mode mode;
9722 #ifndef ANSI_PROTOTYPES
9723 code = va_arg (p, enum rtx_code);
9724 mode = va_arg (p, enum machine_mode);
9727 n_args = GET_RTX_LENGTH (code);
9728 fmt = GET_RTX_FORMAT (code);
9730 if (n_args == 0 || n_args > 3)
9733 /* Get each arg and verify that it is supposed to be an expression. */
9734 for (j = 0; j < n_args; j++)
9739 args[j] = va_arg (p, rtx);
9744 /* See if this is in undobuf. Be sure we don't use objects that came
9745 from another insn; this could produce circular rtl structures. */
9747 for (undo = undobuf.undos; undo != undobuf.previous_undos; undo = undo->next)
9749 && GET_CODE (undo->old_contents.r) == code
9750 && GET_MODE (undo->old_contents.r) == mode)
9752 for (j = 0; j < n_args; j++)
9753 if (XEXP (undo->old_contents.r, j) != args[j])
9757 return undo->old_contents.r;
9760 /* Otherwise make a new rtx. We know we have 1, 2, or 3 args.
9761 Use rtx_alloc instead of gen_rtx because it's faster on RISC. */
9762 rt = rtx_alloc (code);
9763 PUT_MODE (rt, mode);
9764 XEXP (rt, 0) = args[0];
9767 XEXP (rt, 1) = args[1];
9769 XEXP (rt, 2) = args[2];
9774 /* These routines make binary and unary operations by first seeing if they
9775 fold; if not, a new expression is allocated. */
9778 gen_binary (code, mode, op0, op1)
9780 enum machine_mode mode;
9786 if (GET_RTX_CLASS (code) == 'c'
9787 && (GET_CODE (op0) == CONST_INT
9788 || (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)))
9789 tem = op0, op0 = op1, op1 = tem;
9791 if (GET_RTX_CLASS (code) == '<')
9793 enum machine_mode op_mode = GET_MODE (op0);
9795 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
9796 just (REL_OP X Y). */
9797 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
9799 op1 = XEXP (op0, 1);
9800 op0 = XEXP (op0, 0);
9801 op_mode = GET_MODE (op0);
9804 if (op_mode == VOIDmode)
9805 op_mode = GET_MODE (op1);
9806 result = simplify_relational_operation (code, op_mode, op0, op1);
9809 result = simplify_binary_operation (code, mode, op0, op1);
9814 /* Put complex operands first and constants second. */
9815 if (GET_RTX_CLASS (code) == 'c'
9816 && ((CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
9817 || (GET_RTX_CLASS (GET_CODE (op0)) == 'o'
9818 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')
9819 || (GET_CODE (op0) == SUBREG
9820 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0))) == 'o'
9821 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')))
9822 return gen_rtx_combine (code, mode, op1, op0);
9824 /* If we are turning off bits already known off in OP0, we need not do
9826 else if (code == AND && GET_CODE (op1) == CONST_INT
9827 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9828 && (nonzero_bits (op0, mode) & ~ INTVAL (op1)) == 0)
9831 return gen_rtx_combine (code, mode, op0, op1);
9835 gen_unary (code, mode, op0_mode, op0)
9837 enum machine_mode mode, op0_mode;
9840 rtx result = simplify_unary_operation (code, mode, op0, op0_mode);
9845 return gen_rtx_combine (code, mode, op0);
9848 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9849 comparison code that will be tested.
9851 The result is a possibly different comparison code to use. *POP0 and
9852 *POP1 may be updated.
9854 It is possible that we might detect that a comparison is either always
9855 true or always false. However, we do not perform general constant
9856 folding in combine, so this knowledge isn't useful. Such tautologies
9857 should have been detected earlier. Hence we ignore all such cases. */
9859 static enum rtx_code
9860 simplify_comparison (code, pop0, pop1)
9869 enum machine_mode mode, tmode;
9871 /* Try a few ways of applying the same transformation to both operands. */
9874 #ifndef WORD_REGISTER_OPERATIONS
9875 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9876 so check specially. */
9877 if (code != GTU && code != GEU && code != LTU && code != LEU
9878 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9879 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9880 && GET_CODE (XEXP (op1, 0)) == ASHIFT
9881 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9882 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9883 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9884 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9885 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9886 && GET_CODE (XEXP (op1, 1)) == CONST_INT
9887 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9888 && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT
9889 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (op1, 1))
9890 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op0, 0), 1))
9891 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op1, 0), 1))
9892 && (INTVAL (XEXP (op0, 1))
9893 == (GET_MODE_BITSIZE (GET_MODE (op0))
9895 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9897 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9898 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9902 /* If both operands are the same constant shift, see if we can ignore the
9903 shift. We can if the shift is a rotate or if the bits shifted out of
9904 this shift are known to be zero for both inputs and if the type of
9905 comparison is compatible with the shift. */
9906 if (GET_CODE (op0) == GET_CODE (op1)
9907 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9908 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
9909 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
9910 && (code != GT && code != LT && code != GE && code != LE))
9911 || (GET_CODE (op0) == ASHIFTRT
9912 && (code != GTU && code != LTU
9913 && code != GEU && code != GEU)))
9914 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9915 && INTVAL (XEXP (op0, 1)) >= 0
9916 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9917 && XEXP (op0, 1) == XEXP (op1, 1))
9919 enum machine_mode mode = GET_MODE (op0);
9920 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9921 int shift_count = INTVAL (XEXP (op0, 1));
9923 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
9924 mask &= (mask >> shift_count) << shift_count;
9925 else if (GET_CODE (op0) == ASHIFT)
9926 mask = (mask & (mask << shift_count)) >> shift_count;
9928 if ((nonzero_bits (XEXP (op0, 0), mode) & ~ mask) == 0
9929 && (nonzero_bits (XEXP (op1, 0), mode) & ~ mask) == 0)
9930 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
9935 /* If both operands are AND's of a paradoxical SUBREG by constant, the
9936 SUBREGs are of the same mode, and, in both cases, the AND would
9937 be redundant if the comparison was done in the narrower mode,
9938 do the comparison in the narrower mode (e.g., we are AND'ing with 1
9939 and the operand's possibly nonzero bits are 0xffffff01; in that case
9940 if we only care about QImode, we don't need the AND). This case
9941 occurs if the output mode of an scc insn is not SImode and
9942 STORE_FLAG_VALUE == 1 (e.g., the 386).
9944 Similarly, check for a case where the AND's are ZERO_EXTEND
9945 operations from some narrower mode even though a SUBREG is not
9948 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
9949 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9950 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
9952 rtx inner_op0 = XEXP (op0, 0);
9953 rtx inner_op1 = XEXP (op1, 0);
9954 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
9955 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
9958 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
9959 && (GET_MODE_SIZE (GET_MODE (inner_op0))
9960 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
9961 && (GET_MODE (SUBREG_REG (inner_op0))
9962 == GET_MODE (SUBREG_REG (inner_op1)))
9963 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
9964 <= HOST_BITS_PER_WIDE_INT)
9965 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
9966 GET_MODE (SUBREG_REG (inner_op0)))))
9967 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
9968 GET_MODE (SUBREG_REG (inner_op1))))))
9970 op0 = SUBREG_REG (inner_op0);
9971 op1 = SUBREG_REG (inner_op1);
9973 /* The resulting comparison is always unsigned since we masked
9974 off the original sign bit. */
9975 code = unsigned_condition (code);
9981 for (tmode = GET_CLASS_NARROWEST_MODE
9982 (GET_MODE_CLASS (GET_MODE (op0)));
9983 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
9984 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
9986 op0 = gen_lowpart_for_combine (tmode, inner_op0);
9987 op1 = gen_lowpart_for_combine (tmode, inner_op1);
9988 code = unsigned_condition (code);
9997 /* If both operands are NOT, we can strip off the outer operation
9998 and adjust the comparison code for swapped operands; similarly for
9999 NEG, except that this must be an equality comparison. */
10000 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
10001 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
10002 && (code == EQ || code == NE)))
10003 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
10009 /* If the first operand is a constant, swap the operands and adjust the
10010 comparison code appropriately, but don't do this if the second operand
10011 is already a constant integer. */
10012 if (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
10014 tem = op0, op0 = op1, op1 = tem;
10015 code = swap_condition (code);
10018 /* We now enter a loop during which we will try to simplify the comparison.
10019 For the most part, we only are concerned with comparisons with zero,
10020 but some things may really be comparisons with zero but not start
10021 out looking that way. */
10023 while (GET_CODE (op1) == CONST_INT)
10025 enum machine_mode mode = GET_MODE (op0);
10026 unsigned int mode_width = GET_MODE_BITSIZE (mode);
10027 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10028 int equality_comparison_p;
10029 int sign_bit_comparison_p;
10030 int unsigned_comparison_p;
10031 HOST_WIDE_INT const_op;
10033 /* We only want to handle integral modes. This catches VOIDmode,
10034 CCmode, and the floating-point modes. An exception is that we
10035 can handle VOIDmode if OP0 is a COMPARE or a comparison
10038 if (GET_MODE_CLASS (mode) != MODE_INT
10039 && ! (mode == VOIDmode
10040 && (GET_CODE (op0) == COMPARE
10041 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
10044 /* Get the constant we are comparing against and turn off all bits
10045 not on in our mode. */
10046 const_op = INTVAL (op1);
10047 if (mode_width <= HOST_BITS_PER_WIDE_INT)
10050 /* If we are comparing against a constant power of two and the value
10051 being compared can only have that single bit nonzero (e.g., it was
10052 `and'ed with that bit), we can replace this with a comparison
10055 && (code == EQ || code == NE || code == GE || code == GEU
10056 || code == LT || code == LTU)
10057 && mode_width <= HOST_BITS_PER_WIDE_INT
10058 && exact_log2 (const_op) >= 0
10059 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10061 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10062 op1 = const0_rtx, const_op = 0;
10065 /* Similarly, if we are comparing a value known to be either -1 or
10066 0 with -1, change it to the opposite comparison against zero. */
10069 && (code == EQ || code == NE || code == GT || code == LE
10070 || code == GEU || code == LTU)
10071 && num_sign_bit_copies (op0, mode) == mode_width)
10073 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10074 op1 = const0_rtx, const_op = 0;
10077 /* Do some canonicalizations based on the comparison code. We prefer
10078 comparisons against zero and then prefer equality comparisons.
10079 If we can reduce the size of a constant, we will do that too. */
10084 /* < C is equivalent to <= (C - 1) */
10088 op1 = GEN_INT (const_op);
10090 /* ... fall through to LE case below. */
10096 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10100 op1 = GEN_INT (const_op);
10104 /* If we are doing a <= 0 comparison on a value known to have
10105 a zero sign bit, we can replace this with == 0. */
10106 else if (const_op == 0
10107 && mode_width <= HOST_BITS_PER_WIDE_INT
10108 && (nonzero_bits (op0, mode)
10109 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10114 /* >= C is equivalent to > (C - 1). */
10118 op1 = GEN_INT (const_op);
10120 /* ... fall through to GT below. */
10126 /* > C is equivalent to >= (C + 1); we do this for C < 0*/
10130 op1 = GEN_INT (const_op);
10134 /* If we are doing a > 0 comparison on a value known to have
10135 a zero sign bit, we can replace this with != 0. */
10136 else if (const_op == 0
10137 && mode_width <= HOST_BITS_PER_WIDE_INT
10138 && (nonzero_bits (op0, mode)
10139 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10144 /* < C is equivalent to <= (C - 1). */
10148 op1 = GEN_INT (const_op);
10150 /* ... fall through ... */
10153 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10154 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10155 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10157 const_op = 0, op1 = const0_rtx;
10165 /* unsigned <= 0 is equivalent to == 0 */
10169 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10170 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10171 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10173 const_op = 0, op1 = const0_rtx;
10179 /* >= C is equivalent to < (C - 1). */
10183 op1 = GEN_INT (const_op);
10185 /* ... fall through ... */
10188 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10189 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10190 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10192 const_op = 0, op1 = const0_rtx;
10200 /* unsigned > 0 is equivalent to != 0 */
10204 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10205 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10206 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10208 const_op = 0, op1 = const0_rtx;
10217 /* Compute some predicates to simplify code below. */
10219 equality_comparison_p = (code == EQ || code == NE);
10220 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
10221 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
10224 /* If this is a sign bit comparison and we can do arithmetic in
10225 MODE, say that we will only be needing the sign bit of OP0. */
10226 if (sign_bit_comparison_p
10227 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10228 op0 = force_to_mode (op0, mode,
10230 << (GET_MODE_BITSIZE (mode) - 1)),
10233 /* Now try cases based on the opcode of OP0. If none of the cases
10234 does a "continue", we exit this loop immediately after the
10237 switch (GET_CODE (op0))
10240 /* If we are extracting a single bit from a variable position in
10241 a constant that has only a single bit set and are comparing it
10242 with zero, we can convert this into an equality comparison
10243 between the position and the location of the single bit. */
10245 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
10246 && XEXP (op0, 1) == const1_rtx
10247 && equality_comparison_p && const_op == 0
10248 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
10250 if (BITS_BIG_ENDIAN)
10253 mode = insn_data[(int) CODE_FOR_extzv].operand[1].mode;
10254 if (mode == VOIDmode)
10256 i = (GET_MODE_BITSIZE (mode) - 1 - i);
10258 i = BITS_PER_WORD - 1 - i;
10262 op0 = XEXP (op0, 2);
10266 /* Result is nonzero iff shift count is equal to I. */
10267 code = reverse_condition (code);
10271 /* ... fall through ... */
10274 tem = expand_compound_operation (op0);
10283 /* If testing for equality, we can take the NOT of the constant. */
10284 if (equality_comparison_p
10285 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10287 op0 = XEXP (op0, 0);
10292 /* If just looking at the sign bit, reverse the sense of the
10294 if (sign_bit_comparison_p)
10296 op0 = XEXP (op0, 0);
10297 code = (code == GE ? LT : GE);
10303 /* If testing for equality, we can take the NEG of the constant. */
10304 if (equality_comparison_p
10305 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10307 op0 = XEXP (op0, 0);
10312 /* The remaining cases only apply to comparisons with zero. */
10316 /* When X is ABS or is known positive,
10317 (neg X) is < 0 if and only if X != 0. */
10319 if (sign_bit_comparison_p
10320 && (GET_CODE (XEXP (op0, 0)) == ABS
10321 || (mode_width <= HOST_BITS_PER_WIDE_INT
10322 && (nonzero_bits (XEXP (op0, 0), mode)
10323 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10325 op0 = XEXP (op0, 0);
10326 code = (code == LT ? NE : EQ);
10330 /* If we have NEG of something whose two high-order bits are the
10331 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10332 if (num_sign_bit_copies (op0, mode) >= 2)
10334 op0 = XEXP (op0, 0);
10335 code = swap_condition (code);
10341 /* If we are testing equality and our count is a constant, we
10342 can perform the inverse operation on our RHS. */
10343 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10344 && (tem = simplify_binary_operation (ROTATERT, mode,
10345 op1, XEXP (op0, 1))) != 0)
10347 op0 = XEXP (op0, 0);
10352 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10353 a particular bit. Convert it to an AND of a constant of that
10354 bit. This will be converted into a ZERO_EXTRACT. */
10355 if (const_op == 0 && sign_bit_comparison_p
10356 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10357 && mode_width <= HOST_BITS_PER_WIDE_INT)
10359 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10362 - INTVAL (XEXP (op0, 1)))));
10363 code = (code == LT ? NE : EQ);
10367 /* ... fall through ... */
10370 /* ABS is ignorable inside an equality comparison with zero. */
10371 if (const_op == 0 && equality_comparison_p)
10373 op0 = XEXP (op0, 0);
10380 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10381 to (compare FOO CONST) if CONST fits in FOO's mode and we
10382 are either testing inequality or have an unsigned comparison
10383 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10384 if (! unsigned_comparison_p
10385 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10386 <= HOST_BITS_PER_WIDE_INT)
10387 && ((unsigned HOST_WIDE_INT) const_op
10388 < (((unsigned HOST_WIDE_INT) 1
10389 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
10391 op0 = XEXP (op0, 0);
10397 /* Check for the case where we are comparing A - C1 with C2,
10398 both constants are smaller than 1/2 the maximum positive
10399 value in MODE, and the comparison is equality or unsigned.
10400 In that case, if A is either zero-extended to MODE or has
10401 sufficient sign bits so that the high-order bit in MODE
10402 is a copy of the sign in the inner mode, we can prove that it is
10403 safe to do the operation in the wider mode. This simplifies
10404 many range checks. */
10406 if (mode_width <= HOST_BITS_PER_WIDE_INT
10407 && subreg_lowpart_p (op0)
10408 && GET_CODE (SUBREG_REG (op0)) == PLUS
10409 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
10410 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
10411 && (- INTVAL (XEXP (SUBREG_REG (op0), 1))
10412 < (HOST_WIDE_INT)(GET_MODE_MASK (mode) / 2))
10413 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
10414 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
10415 GET_MODE (SUBREG_REG (op0)))
10416 & ~ GET_MODE_MASK (mode))
10417 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
10418 GET_MODE (SUBREG_REG (op0)))
10419 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10420 - GET_MODE_BITSIZE (mode)))))
10422 op0 = SUBREG_REG (op0);
10426 /* If the inner mode is narrower and we are extracting the low part,
10427 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10428 if (subreg_lowpart_p (op0)
10429 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10430 /* Fall through */ ;
10434 /* ... fall through ... */
10437 if ((unsigned_comparison_p || equality_comparison_p)
10438 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10439 <= HOST_BITS_PER_WIDE_INT)
10440 && ((unsigned HOST_WIDE_INT) const_op
10441 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
10443 op0 = XEXP (op0, 0);
10449 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10450 this for equality comparisons due to pathological cases involving
10452 if (equality_comparison_p
10453 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10454 op1, XEXP (op0, 1))))
10456 op0 = XEXP (op0, 0);
10461 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10462 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10463 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10465 op0 = XEXP (XEXP (op0, 0), 0);
10466 code = (code == LT ? EQ : NE);
10472 /* We used to optimize signed comparisons against zero, but that
10473 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10474 arrive here as equality comparisons, or (GEU, LTU) are
10475 optimized away. No need to special-case them. */
10477 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10478 (eq B (minus A C)), whichever simplifies. We can only do
10479 this for equality comparisons due to pathological cases involving
10481 if (equality_comparison_p
10482 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10483 XEXP (op0, 1), op1)))
10485 op0 = XEXP (op0, 0);
10490 if (equality_comparison_p
10491 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10492 XEXP (op0, 0), op1)))
10494 op0 = XEXP (op0, 1);
10499 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10500 of bits in X minus 1, is one iff X > 0. */
10501 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10502 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10503 && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
10504 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10506 op0 = XEXP (op0, 1);
10507 code = (code == GE ? LE : GT);
10513 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10514 if C is zero or B is a constant. */
10515 if (equality_comparison_p
10516 && 0 != (tem = simplify_binary_operation (XOR, mode,
10517 XEXP (op0, 1), op1)))
10519 op0 = XEXP (op0, 0);
10526 case LT: case LTU: case LE: case LEU:
10527 case GT: case GTU: case GE: case GEU:
10528 /* We can't do anything if OP0 is a condition code value, rather
10529 than an actual data value. */
10532 || XEXP (op0, 0) == cc0_rtx
10534 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10537 /* Get the two operands being compared. */
10538 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10539 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10541 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10543 /* Check for the cases where we simply want the result of the
10544 earlier test or the opposite of that result. */
10546 || (code == EQ && reversible_comparison_p (op0))
10547 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10548 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10549 && (STORE_FLAG_VALUE
10550 & (((HOST_WIDE_INT) 1
10551 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10553 || (code == GE && reversible_comparison_p (op0)))))
10555 code = (code == LT || code == NE
10556 ? GET_CODE (op0) : reverse_condition (GET_CODE (op0)));
10557 op0 = tem, op1 = tem1;
10563 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
10565 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10566 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10567 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10569 op0 = XEXP (op0, 1);
10570 code = (code == GE ? GT : LE);
10576 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10577 will be converted to a ZERO_EXTRACT later. */
10578 if (const_op == 0 && equality_comparison_p
10579 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10580 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10582 op0 = simplify_and_const_int
10583 (op0, mode, gen_rtx_combine (LSHIFTRT, mode,
10585 XEXP (XEXP (op0, 0), 1)),
10586 (HOST_WIDE_INT) 1);
10590 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10591 zero and X is a comparison and C1 and C2 describe only bits set
10592 in STORE_FLAG_VALUE, we can compare with X. */
10593 if (const_op == 0 && equality_comparison_p
10594 && mode_width <= HOST_BITS_PER_WIDE_INT
10595 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10596 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10597 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10598 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10599 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10601 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10602 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10603 if ((~ STORE_FLAG_VALUE & mask) == 0
10604 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
10605 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10606 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
10608 op0 = XEXP (XEXP (op0, 0), 0);
10613 /* If we are doing an equality comparison of an AND of a bit equal
10614 to the sign bit, replace this with a LT or GE comparison of
10615 the underlying value. */
10616 if (equality_comparison_p
10618 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10619 && mode_width <= HOST_BITS_PER_WIDE_INT
10620 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10621 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10623 op0 = XEXP (op0, 0);
10624 code = (code == EQ ? GE : LT);
10628 /* If this AND operation is really a ZERO_EXTEND from a narrower
10629 mode, the constant fits within that mode, and this is either an
10630 equality or unsigned comparison, try to do this comparison in
10631 the narrower mode. */
10632 if ((equality_comparison_p || unsigned_comparison_p)
10633 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10634 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10635 & GET_MODE_MASK (mode))
10637 && const_op >> i == 0
10638 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
10640 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
10644 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 fits
10645 in both M1 and M2 and the SUBREG is either paradoxical or
10646 represents the low part, permute the SUBREG and the AND and
10648 if (GET_CODE (XEXP (op0, 0)) == SUBREG
10650 #ifdef WORD_REGISTER_OPERATIONS
10652 > (GET_MODE_BITSIZE
10653 (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10654 && mode_width <= BITS_PER_WORD)
10657 <= (GET_MODE_BITSIZE
10658 (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10659 && subreg_lowpart_p (XEXP (op0, 0))))
10660 #ifndef WORD_REGISTER_OPERATIONS
10661 /* It is unsafe to commute the AND into the SUBREG if the SUBREG
10662 is paradoxical and WORD_REGISTER_OPERATIONS is not defined.
10663 As originally written the upper bits have a defined value
10664 due to the AND operation. However, if we commute the AND
10665 inside the SUBREG then they no longer have defined values
10666 and the meaning of the code has been changed. */
10667 && (GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)))
10668 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))
10670 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10671 && mode_width <= HOST_BITS_PER_WIDE_INT
10672 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10673 <= HOST_BITS_PER_WIDE_INT)
10674 && (INTVAL (XEXP (op0, 1)) & ~ mask) == 0
10675 && 0 == (~ GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10676 & INTVAL (XEXP (op0, 1)))
10677 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1)) != mask
10678 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10679 != GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10683 = gen_lowpart_for_combine
10685 gen_binary (AND, GET_MODE (SUBREG_REG (XEXP (op0, 0))),
10686 SUBREG_REG (XEXP (op0, 0)), XEXP (op0, 1)));
10693 /* If we have (compare (ashift FOO N) (const_int C)) and
10694 the high order N bits of FOO (N+1 if an inequality comparison)
10695 are known to be zero, we can do this by comparing FOO with C
10696 shifted right N bits so long as the low-order N bits of C are
10698 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10699 && INTVAL (XEXP (op0, 1)) >= 0
10700 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10701 < HOST_BITS_PER_WIDE_INT)
10703 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10704 && mode_width <= HOST_BITS_PER_WIDE_INT
10705 && (nonzero_bits (XEXP (op0, 0), mode)
10706 & ~ (mask >> (INTVAL (XEXP (op0, 1))
10707 + ! equality_comparison_p))) == 0)
10709 /* We must perform a logical shift, not an arithmetic one,
10710 as we want the top N bits of C to be zero. */
10711 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10713 temp >>= INTVAL (XEXP (op0, 1));
10714 op1 = GEN_INT (trunc_int_for_mode (temp, mode));
10715 op0 = XEXP (op0, 0);
10719 /* If we are doing a sign bit comparison, it means we are testing
10720 a particular bit. Convert it to the appropriate AND. */
10721 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10722 && mode_width <= HOST_BITS_PER_WIDE_INT)
10724 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10727 - INTVAL (XEXP (op0, 1)))));
10728 code = (code == LT ? NE : EQ);
10732 /* If this an equality comparison with zero and we are shifting
10733 the low bit to the sign bit, we can convert this to an AND of the
10735 if (const_op == 0 && equality_comparison_p
10736 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10737 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10739 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10740 (HOST_WIDE_INT) 1);
10746 /* If this is an equality comparison with zero, we can do this
10747 as a logical shift, which might be much simpler. */
10748 if (equality_comparison_p && const_op == 0
10749 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10751 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10753 INTVAL (XEXP (op0, 1)));
10757 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10758 do the comparison in a narrower mode. */
10759 if (! unsigned_comparison_p
10760 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10761 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10762 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10763 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10764 MODE_INT, 1)) != BLKmode
10765 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
10766 || ((unsigned HOST_WIDE_INT) - const_op
10767 <= GET_MODE_MASK (tmode))))
10769 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
10773 /* Likewise if OP0 is a PLUS of a sign extension with a
10774 constant, which is usually represented with the PLUS
10775 between the shifts. */
10776 if (! unsigned_comparison_p
10777 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10778 && GET_CODE (XEXP (op0, 0)) == PLUS
10779 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10780 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
10781 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
10782 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10783 MODE_INT, 1)) != BLKmode
10784 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
10785 || ((unsigned HOST_WIDE_INT) - const_op
10786 <= GET_MODE_MASK (tmode))))
10788 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
10789 rtx add_const = XEXP (XEXP (op0, 0), 1);
10790 rtx new_const = gen_binary (ASHIFTRT, GET_MODE (op0), add_const,
10793 op0 = gen_binary (PLUS, tmode,
10794 gen_lowpart_for_combine (tmode, inner),
10799 /* ... fall through ... */
10801 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10802 the low order N bits of FOO are known to be zero, we can do this
10803 by comparing FOO with C shifted left N bits so long as no
10804 overflow occurs. */
10805 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10806 && INTVAL (XEXP (op0, 1)) >= 0
10807 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10808 && mode_width <= HOST_BITS_PER_WIDE_INT
10809 && (nonzero_bits (XEXP (op0, 0), mode)
10810 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10812 || (floor_log2 (const_op) + INTVAL (XEXP (op0, 1))
10815 const_op <<= INTVAL (XEXP (op0, 1));
10816 op1 = GEN_INT (const_op);
10817 op0 = XEXP (op0, 0);
10821 /* If we are using this shift to extract just the sign bit, we
10822 can replace this with an LT or GE comparison. */
10824 && (equality_comparison_p || sign_bit_comparison_p)
10825 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10826 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10828 op0 = XEXP (op0, 0);
10829 code = (code == NE || code == GT ? LT : GE);
10841 /* Now make any compound operations involved in this comparison. Then,
10842 check for an outmost SUBREG on OP0 that is not doing anything or is
10843 paradoxical. The latter case can only occur when it is known that the
10844 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
10845 We can never remove a SUBREG for a non-equality comparison because the
10846 sign bit is in a different place in the underlying object. */
10848 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10849 op1 = make_compound_operation (op1, SET);
10851 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10852 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10853 && (code == NE || code == EQ)
10854 && ((GET_MODE_SIZE (GET_MODE (op0))
10855 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))))
10857 op0 = SUBREG_REG (op0);
10858 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
10861 else if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10862 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10863 && (code == NE || code == EQ)
10864 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10865 <= HOST_BITS_PER_WIDE_INT)
10866 && (nonzero_bits (SUBREG_REG (op0), GET_MODE (SUBREG_REG (op0)))
10867 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0
10868 && (tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)),
10870 (nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
10871 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0))
10872 op0 = SUBREG_REG (op0), op1 = tem;
10874 /* We now do the opposite procedure: Some machines don't have compare
10875 insns in all modes. If OP0's mode is an integer mode smaller than a
10876 word and we can't do a compare in that mode, see if there is a larger
10877 mode for which we can do the compare. There are a number of cases in
10878 which we can use the wider mode. */
10880 mode = GET_MODE (op0);
10881 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10882 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
10883 && cmp_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
10884 for (tmode = GET_MODE_WIDER_MODE (mode);
10886 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
10887 tmode = GET_MODE_WIDER_MODE (tmode))
10888 if (cmp_optab->handlers[(int) tmode].insn_code != CODE_FOR_nothing)
10890 /* If the only nonzero bits in OP0 and OP1 are those in the
10891 narrower mode and this is an equality or unsigned comparison,
10892 we can use the wider mode. Similarly for sign-extended
10893 values, in which case it is true for all comparisons. */
10894 if (((code == EQ || code == NE
10895 || code == GEU || code == GTU || code == LEU || code == LTU)
10896 && (nonzero_bits (op0, tmode) & ~ GET_MODE_MASK (mode)) == 0
10897 && (nonzero_bits (op1, tmode) & ~ GET_MODE_MASK (mode)) == 0)
10898 || ((num_sign_bit_copies (op0, tmode)
10899 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))
10900 && (num_sign_bit_copies (op1, tmode)
10901 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))))
10903 /* If OP0 is an AND and we don't have an AND in MODE either,
10904 make a new AND in the proper mode. */
10905 if (GET_CODE (op0) == AND
10906 && (add_optab->handlers[(int) mode].insn_code
10907 == CODE_FOR_nothing))
10908 op0 = gen_binary (AND, tmode,
10909 gen_lowpart_for_combine (tmode,
10911 gen_lowpart_for_combine (tmode,
10914 op0 = gen_lowpart_for_combine (tmode, op0);
10915 op1 = gen_lowpart_for_combine (tmode, op1);
10919 /* If this is a test for negative, we can make an explicit
10920 test of the sign bit. */
10922 if (op1 == const0_rtx && (code == LT || code == GE)
10923 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10925 op0 = gen_binary (AND, tmode,
10926 gen_lowpart_for_combine (tmode, op0),
10927 GEN_INT ((HOST_WIDE_INT) 1
10928 << (GET_MODE_BITSIZE (mode) - 1)));
10929 code = (code == LT) ? NE : EQ;
10934 #ifdef CANONICALIZE_COMPARISON
10935 /* If this machine only supports a subset of valid comparisons, see if we
10936 can convert an unsupported one into a supported one. */
10937 CANONICALIZE_COMPARISON (code, op0, op1);
10946 /* Return 1 if we know that X, a comparison operation, is not operating
10947 on a floating-point value or is EQ or NE, meaning that we can safely
10951 reversible_comparison_p (x)
10954 if (TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
10956 || GET_CODE (x) == NE || GET_CODE (x) == EQ
10957 || GET_CODE (x) == UNORDERED || GET_CODE (x) == ORDERED)
10960 switch (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))))
10963 case MODE_PARTIAL_INT:
10964 case MODE_COMPLEX_INT:
10968 /* If the mode of the condition codes tells us that this is safe,
10969 we need look no further. */
10970 if (REVERSIBLE_CC_MODE (GET_MODE (XEXP (x, 0))))
10973 /* Otherwise try and find where the condition codes were last set and
10975 x = get_last_value (XEXP (x, 0));
10976 return (x && GET_CODE (x) == COMPARE
10977 && ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0))));
10984 /* Utility function for following routine. Called when X is part of a value
10985 being stored into reg_last_set_value. Sets reg_last_set_table_tick
10986 for each register mentioned. Similar to mention_regs in cse.c */
10989 update_table_tick (x)
10992 register enum rtx_code code = GET_CODE (x);
10993 register const char *fmt = GET_RTX_FORMAT (code);
10998 unsigned int regno = REGNO (x);
10999 unsigned int endregno
11000 = regno + (regno < FIRST_PSEUDO_REGISTER
11001 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11004 for (r = regno; r < endregno; r++)
11005 reg_last_set_table_tick[r] = label_tick;
11010 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11011 /* Note that we can't have an "E" in values stored; see
11012 get_last_value_validate. */
11014 update_table_tick (XEXP (x, i));
11017 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11018 are saying that the register is clobbered and we no longer know its
11019 value. If INSN is zero, don't update reg_last_set; this is only permitted
11020 with VALUE also zero and is used to invalidate the register. */
11023 record_value_for_reg (reg, insn, value)
11028 unsigned int regno = REGNO (reg);
11029 unsigned int endregno
11030 = regno + (regno < FIRST_PSEUDO_REGISTER
11031 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
11034 /* If VALUE contains REG and we have a previous value for REG, substitute
11035 the previous value. */
11036 if (value && insn && reg_overlap_mentioned_p (reg, value))
11040 /* Set things up so get_last_value is allowed to see anything set up to
11042 subst_low_cuid = INSN_CUID (insn);
11043 tem = get_last_value (reg);
11045 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11046 it isn't going to be useful and will take a lot of time to process,
11047 so just use the CLOBBER. */
11051 if ((GET_RTX_CLASS (GET_CODE (tem)) == '2'
11052 || GET_RTX_CLASS (GET_CODE (tem)) == 'c')
11053 && GET_CODE (XEXP (tem, 0)) == CLOBBER
11054 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
11055 tem = XEXP (tem, 0);
11057 value = replace_rtx (copy_rtx (value), reg, tem);
11061 /* For each register modified, show we don't know its value, that
11062 we don't know about its bitwise content, that its value has been
11063 updated, and that we don't know the location of the death of the
11065 for (i = regno; i < endregno; i++)
11068 reg_last_set[i] = insn;
11070 reg_last_set_value[i] = 0;
11071 reg_last_set_mode[i] = 0;
11072 reg_last_set_nonzero_bits[i] = 0;
11073 reg_last_set_sign_bit_copies[i] = 0;
11074 reg_last_death[i] = 0;
11077 /* Mark registers that are being referenced in this value. */
11079 update_table_tick (value);
11081 /* Now update the status of each register being set.
11082 If someone is using this register in this block, set this register
11083 to invalid since we will get confused between the two lives in this
11084 basic block. This makes using this register always invalid. In cse, we
11085 scan the table to invalidate all entries using this register, but this
11086 is too much work for us. */
11088 for (i = regno; i < endregno; i++)
11090 reg_last_set_label[i] = label_tick;
11091 if (value && reg_last_set_table_tick[i] == label_tick)
11092 reg_last_set_invalid[i] = 1;
11094 reg_last_set_invalid[i] = 0;
11097 /* The value being assigned might refer to X (like in "x++;"). In that
11098 case, we must replace it with (clobber (const_int 0)) to prevent
11100 if (value && ! get_last_value_validate (&value, insn,
11101 reg_last_set_label[regno], 0))
11103 value = copy_rtx (value);
11104 if (! get_last_value_validate (&value, insn,
11105 reg_last_set_label[regno], 1))
11109 /* For the main register being modified, update the value, the mode, the
11110 nonzero bits, and the number of sign bit copies. */
11112 reg_last_set_value[regno] = value;
11116 subst_low_cuid = INSN_CUID (insn);
11117 reg_last_set_mode[regno] = GET_MODE (reg);
11118 reg_last_set_nonzero_bits[regno] = nonzero_bits (value, GET_MODE (reg));
11119 reg_last_set_sign_bit_copies[regno]
11120 = num_sign_bit_copies (value, GET_MODE (reg));
11124 /* Called via note_stores from record_dead_and_set_regs to handle one
11125 SET or CLOBBER in an insn. DATA is the instruction in which the
11126 set is occurring. */
11129 record_dead_and_set_regs_1 (dest, setter, data)
11133 rtx record_dead_insn = (rtx) data;
11135 if (GET_CODE (dest) == SUBREG)
11136 dest = SUBREG_REG (dest);
11138 if (GET_CODE (dest) == REG)
11140 /* If we are setting the whole register, we know its value. Otherwise
11141 show that we don't know the value. We can handle SUBREG in
11143 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11144 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11145 else if (GET_CODE (setter) == SET
11146 && GET_CODE (SET_DEST (setter)) == SUBREG
11147 && SUBREG_REG (SET_DEST (setter)) == dest
11148 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11149 && subreg_lowpart_p (SET_DEST (setter)))
11150 record_value_for_reg (dest, record_dead_insn,
11151 gen_lowpart_for_combine (GET_MODE (dest),
11152 SET_SRC (setter)));
11154 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11156 else if (GET_CODE (dest) == MEM
11157 /* Ignore pushes, they clobber nothing. */
11158 && ! push_operand (dest, GET_MODE (dest)))
11159 mem_last_set = INSN_CUID (record_dead_insn);
11162 /* Update the records of when each REG was most recently set or killed
11163 for the things done by INSN. This is the last thing done in processing
11164 INSN in the combiner loop.
11166 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
11167 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
11168 and also the similar information mem_last_set (which insn most recently
11169 modified memory) and last_call_cuid (which insn was the most recent
11170 subroutine call). */
11173 record_dead_and_set_regs (insn)
11179 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11181 if (REG_NOTE_KIND (link) == REG_DEAD
11182 && GET_CODE (XEXP (link, 0)) == REG)
11184 unsigned int regno = REGNO (XEXP (link, 0));
11185 unsigned int endregno
11186 = regno + (regno < FIRST_PSEUDO_REGISTER
11187 ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0)))
11190 for (i = regno; i < endregno; i++)
11191 reg_last_death[i] = insn;
11193 else if (REG_NOTE_KIND (link) == REG_INC)
11194 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11197 if (GET_CODE (insn) == CALL_INSN)
11199 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11200 if (call_used_regs[i])
11202 reg_last_set_value[i] = 0;
11203 reg_last_set_mode[i] = 0;
11204 reg_last_set_nonzero_bits[i] = 0;
11205 reg_last_set_sign_bit_copies[i] = 0;
11206 reg_last_death[i] = 0;
11209 last_call_cuid = mem_last_set = INSN_CUID (insn);
11212 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11215 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11216 register present in the SUBREG, so for each such SUBREG go back and
11217 adjust nonzero and sign bit information of the registers that are
11218 known to have some zero/sign bits set.
11220 This is needed because when combine blows the SUBREGs away, the
11221 information on zero/sign bits is lost and further combines can be
11222 missed because of that. */
11225 record_promoted_value (insn, subreg)
11230 unsigned int regno = REGNO (SUBREG_REG (subreg));
11231 enum machine_mode mode = GET_MODE (subreg);
11233 if (GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT)
11236 for (links = LOG_LINKS (insn); links; )
11238 insn = XEXP (links, 0);
11239 set = single_set (insn);
11241 if (! set || GET_CODE (SET_DEST (set)) != REG
11242 || REGNO (SET_DEST (set)) != regno
11243 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11245 links = XEXP (links, 1);
11249 if (reg_last_set [regno] == insn)
11251 if (SUBREG_PROMOTED_UNSIGNED_P (subreg))
11252 reg_last_set_nonzero_bits [regno] &= GET_MODE_MASK (mode);
11255 if (GET_CODE (SET_SRC (set)) == REG)
11257 regno = REGNO (SET_SRC (set));
11258 links = LOG_LINKS (insn);
11265 /* Scan X for promoted SUBREGs. For each one found,
11266 note what it implies to the registers used in it. */
11269 check_promoted_subreg (insn, x)
11273 if (GET_CODE (x) == SUBREG && SUBREG_PROMOTED_VAR_P (x)
11274 && GET_CODE (SUBREG_REG (x)) == REG)
11275 record_promoted_value (insn, x);
11278 const char *format = GET_RTX_FORMAT (GET_CODE (x));
11281 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11282 switch (format [i])
11285 check_promoted_subreg (insn, XEXP (x, i));
11289 if (XVEC (x, i) != 0)
11290 for (j = 0; j < XVECLEN (x, i); j++)
11291 check_promoted_subreg (insn, XVECEXP (x, i, j));
11297 /* Utility routine for the following function. Verify that all the registers
11298 mentioned in *LOC are valid when *LOC was part of a value set when
11299 label_tick == TICK. Return 0 if some are not.
11301 If REPLACE is non-zero, replace the invalid reference with
11302 (clobber (const_int 0)) and return 1. This replacement is useful because
11303 we often can get useful information about the form of a value (e.g., if
11304 it was produced by a shift that always produces -1 or 0) even though
11305 we don't know exactly what registers it was produced from. */
11308 get_last_value_validate (loc, insn, tick, replace)
11315 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11316 int len = GET_RTX_LENGTH (GET_CODE (x));
11319 if (GET_CODE (x) == REG)
11321 unsigned int regno = REGNO (x);
11322 unsigned int endregno
11323 = regno + (regno < FIRST_PSEUDO_REGISTER
11324 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11327 for (j = regno; j < endregno; j++)
11328 if (reg_last_set_invalid[j]
11329 /* If this is a pseudo-register that was only set once and not
11330 live at the beginning of the function, it is always valid. */
11331 || (! (regno >= FIRST_PSEUDO_REGISTER
11332 && REG_N_SETS (regno) == 1
11333 && (! REGNO_REG_SET_P
11334 (BASIC_BLOCK (0)->global_live_at_start, regno)))
11335 && reg_last_set_label[j] > tick))
11338 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11344 /* If this is a memory reference, make sure that there were
11345 no stores after it that might have clobbered the value. We don't
11346 have alias info, so we assume any store invalidates it. */
11347 else if (GET_CODE (x) == MEM && ! RTX_UNCHANGING_P (x)
11348 && INSN_CUID (insn) <= mem_last_set)
11351 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11355 for (i = 0; i < len; i++)
11357 && get_last_value_validate (&XEXP (x, i), insn, tick, replace) == 0)
11358 /* Don't bother with these. They shouldn't occur anyway. */
11362 /* If we haven't found a reason for it to be invalid, it is valid. */
11366 /* Get the last value assigned to X, if known. Some registers
11367 in the value may be replaced with (clobber (const_int 0)) if their value
11368 is known longer known reliably. */
11374 unsigned int regno;
11377 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11378 then convert it to the desired mode. If this is a paradoxical SUBREG,
11379 we cannot predict what values the "extra" bits might have. */
11380 if (GET_CODE (x) == SUBREG
11381 && subreg_lowpart_p (x)
11382 && (GET_MODE_SIZE (GET_MODE (x))
11383 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11384 && (value = get_last_value (SUBREG_REG (x))) != 0)
11385 return gen_lowpart_for_combine (GET_MODE (x), value);
11387 if (GET_CODE (x) != REG)
11391 value = reg_last_set_value[regno];
11393 /* If we don't have a value, or if it isn't for this basic block and
11394 it's either a hard register, set more than once, or it's a live
11395 at the beginning of the function, return 0.
11397 Because if it's not live at the beginnning of the function then the reg
11398 is always set before being used (is never used without being set).
11399 And, if it's set only once, and it's always set before use, then all
11400 uses must have the same last value, even if it's not from this basic
11404 || (reg_last_set_label[regno] != label_tick
11405 && (regno < FIRST_PSEUDO_REGISTER
11406 || REG_N_SETS (regno) != 1
11407 || (REGNO_REG_SET_P
11408 (BASIC_BLOCK (0)->global_live_at_start, regno)))))
11411 /* If the value was set in a later insn than the ones we are processing,
11412 we can't use it even if the register was only set once. */
11413 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
11416 /* If the value has all its registers valid, return it. */
11417 if (get_last_value_validate (&value, reg_last_set[regno],
11418 reg_last_set_label[regno], 0))
11421 /* Otherwise, make a copy and replace any invalid register with
11422 (clobber (const_int 0)). If that fails for some reason, return 0. */
11424 value = copy_rtx (value);
11425 if (get_last_value_validate (&value, reg_last_set[regno],
11426 reg_last_set_label[regno], 1))
11432 /* Return nonzero if expression X refers to a REG or to memory
11433 that is set in an instruction more recent than FROM_CUID. */
11436 use_crosses_set_p (x, from_cuid)
11440 register const char *fmt;
11442 register enum rtx_code code = GET_CODE (x);
11446 unsigned int regno = REGNO (x);
11447 unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER
11448 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11450 #ifdef PUSH_ROUNDING
11451 /* Don't allow uses of the stack pointer to be moved,
11452 because we don't know whether the move crosses a push insn. */
11453 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11456 for (; regno < endreg; regno++)
11457 if (reg_last_set[regno]
11458 && INSN_CUID (reg_last_set[regno]) > from_cuid)
11463 if (code == MEM && mem_last_set > from_cuid)
11466 fmt = GET_RTX_FORMAT (code);
11468 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11473 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11474 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11477 else if (fmt[i] == 'e'
11478 && use_crosses_set_p (XEXP (x, i), from_cuid))
11484 /* Define three variables used for communication between the following
11487 static unsigned int reg_dead_regno, reg_dead_endregno;
11488 static int reg_dead_flag;
11490 /* Function called via note_stores from reg_dead_at_p.
11492 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11493 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11496 reg_dead_at_p_1 (dest, x, data)
11499 void *data ATTRIBUTE_UNUSED;
11501 unsigned int regno, endregno;
11503 if (GET_CODE (dest) != REG)
11506 regno = REGNO (dest);
11507 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11508 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
11510 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11511 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11514 /* Return non-zero if REG is known to be dead at INSN.
11516 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11517 referencing REG, it is dead. If we hit a SET referencing REG, it is
11518 live. Otherwise, see if it is live or dead at the start of the basic
11519 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11520 must be assumed to be always live. */
11523 reg_dead_at_p (reg, insn)
11530 /* Set variables for reg_dead_at_p_1. */
11531 reg_dead_regno = REGNO (reg);
11532 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
11533 ? HARD_REGNO_NREGS (reg_dead_regno,
11539 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11540 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11542 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11543 if (TEST_HARD_REG_BIT (newpat_used_regs, i))
11547 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11548 beginning of function. */
11549 for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER;
11550 insn = prev_nonnote_insn (insn))
11552 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11554 return reg_dead_flag == 1 ? 1 : 0;
11556 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11560 /* Get the basic block number that we were in. */
11565 for (block = 0; block < n_basic_blocks; block++)
11566 if (insn == BLOCK_HEAD (block))
11569 if (block == n_basic_blocks)
11573 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11574 if (REGNO_REG_SET_P (BASIC_BLOCK (block)->global_live_at_start, i))
11580 /* Note hard registers in X that are used. This code is similar to
11581 that in flow.c, but much simpler since we don't care about pseudos. */
11584 mark_used_regs_combine (x)
11587 RTX_CODE code = GET_CODE (x);
11588 unsigned int regno;
11600 case ADDR_DIFF_VEC:
11603 /* CC0 must die in the insn after it is set, so we don't need to take
11604 special note of it here. */
11610 /* If we are clobbering a MEM, mark any hard registers inside the
11611 address as used. */
11612 if (GET_CODE (XEXP (x, 0)) == MEM)
11613 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11618 /* A hard reg in a wide mode may really be multiple registers.
11619 If so, mark all of them just like the first. */
11620 if (regno < FIRST_PSEUDO_REGISTER)
11622 unsigned int endregno, r;
11624 /* None of this applies to the stack, frame or arg pointers */
11625 if (regno == STACK_POINTER_REGNUM
11626 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11627 || regno == HARD_FRAME_POINTER_REGNUM
11629 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11630 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11632 || regno == FRAME_POINTER_REGNUM)
11635 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11636 for (r = regno; r < endregno; r++)
11637 SET_HARD_REG_BIT (newpat_used_regs, r);
11643 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11645 register rtx testreg = SET_DEST (x);
11647 while (GET_CODE (testreg) == SUBREG
11648 || GET_CODE (testreg) == ZERO_EXTRACT
11649 || GET_CODE (testreg) == SIGN_EXTRACT
11650 || GET_CODE (testreg) == STRICT_LOW_PART)
11651 testreg = XEXP (testreg, 0);
11653 if (GET_CODE (testreg) == MEM)
11654 mark_used_regs_combine (XEXP (testreg, 0));
11656 mark_used_regs_combine (SET_SRC (x));
11664 /* Recursively scan the operands of this expression. */
11667 register const char *fmt = GET_RTX_FORMAT (code);
11669 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11672 mark_used_regs_combine (XEXP (x, i));
11673 else if (fmt[i] == 'E')
11677 for (j = 0; j < XVECLEN (x, i); j++)
11678 mark_used_regs_combine (XVECEXP (x, i, j));
11685 /* Remove register number REGNO from the dead registers list of INSN.
11687 Return the note used to record the death, if there was one. */
11690 remove_death (regno, insn)
11691 unsigned int regno;
11694 register rtx note = find_regno_note (insn, REG_DEAD, regno);
11698 REG_N_DEATHS (regno)--;
11699 remove_note (insn, note);
11705 /* For each register (hardware or pseudo) used within expression X, if its
11706 death is in an instruction with cuid between FROM_CUID (inclusive) and
11707 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11708 list headed by PNOTES.
11710 That said, don't move registers killed by maybe_kill_insn.
11712 This is done when X is being merged by combination into TO_INSN. These
11713 notes will then be distributed as needed. */
11716 move_deaths (x, maybe_kill_insn, from_cuid, to_insn, pnotes)
11718 rtx maybe_kill_insn;
11723 register const char *fmt;
11724 register int len, i;
11725 register enum rtx_code code = GET_CODE (x);
11729 unsigned int regno = REGNO (x);
11730 register rtx where_dead = reg_last_death[regno];
11731 register rtx before_dead, after_dead;
11733 /* Don't move the register if it gets killed in between from and to */
11734 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11735 && ! reg_referenced_p (x, maybe_kill_insn))
11738 /* WHERE_DEAD could be a USE insn made by combine, so first we
11739 make sure that we have insns with valid INSN_CUID values. */
11740 before_dead = where_dead;
11741 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11742 before_dead = PREV_INSN (before_dead);
11744 after_dead = where_dead;
11745 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11746 after_dead = NEXT_INSN (after_dead);
11748 if (before_dead && after_dead
11749 && INSN_CUID (before_dead) >= from_cuid
11750 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
11751 || (where_dead != after_dead
11752 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
11754 rtx note = remove_death (regno, where_dead);
11756 /* It is possible for the call above to return 0. This can occur
11757 when reg_last_death points to I2 or I1 that we combined with.
11758 In that case make a new note.
11760 We must also check for the case where X is a hard register
11761 and NOTE is a death note for a range of hard registers
11762 including X. In that case, we must put REG_DEAD notes for
11763 the remaining registers in place of NOTE. */
11765 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11766 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11767 > GET_MODE_SIZE (GET_MODE (x))))
11769 unsigned int deadregno = REGNO (XEXP (note, 0));
11770 unsigned int deadend
11771 = (deadregno + HARD_REGNO_NREGS (deadregno,
11772 GET_MODE (XEXP (note, 0))));
11773 unsigned int ourend
11774 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11777 for (i = deadregno; i < deadend; i++)
11778 if (i < regno || i >= ourend)
11779 REG_NOTES (where_dead)
11780 = gen_rtx_EXPR_LIST (REG_DEAD,
11781 gen_rtx_REG (reg_raw_mode[i], i),
11782 REG_NOTES (where_dead));
11785 /* If we didn't find any note, or if we found a REG_DEAD note that
11786 covers only part of the given reg, and we have a multi-reg hard
11787 register, then to be safe we must check for REG_DEAD notes
11788 for each register other than the first. They could have
11789 their own REG_DEAD notes lying around. */
11790 else if ((note == 0
11792 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11793 < GET_MODE_SIZE (GET_MODE (x)))))
11794 && regno < FIRST_PSEUDO_REGISTER
11795 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
11797 unsigned int ourend
11798 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11799 unsigned int i, offset;
11803 offset = HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0)));
11807 for (i = regno + offset; i < ourend; i++)
11808 move_deaths (gen_rtx_REG (reg_raw_mode[i], i),
11809 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
11812 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
11814 XEXP (note, 1) = *pnotes;
11818 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
11820 REG_N_DEATHS (regno)++;
11826 else if (GET_CODE (x) == SET)
11828 rtx dest = SET_DEST (x);
11830 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
11832 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11833 that accesses one word of a multi-word item, some
11834 piece of everything register in the expression is used by
11835 this insn, so remove any old death. */
11837 if (GET_CODE (dest) == ZERO_EXTRACT
11838 || GET_CODE (dest) == STRICT_LOW_PART
11839 || (GET_CODE (dest) == SUBREG
11840 && (((GET_MODE_SIZE (GET_MODE (dest))
11841 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
11842 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
11843 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
11845 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
11849 /* If this is some other SUBREG, we know it replaces the entire
11850 value, so use that as the destination. */
11851 if (GET_CODE (dest) == SUBREG)
11852 dest = SUBREG_REG (dest);
11854 /* If this is a MEM, adjust deaths of anything used in the address.
11855 For a REG (the only other possibility), the entire value is
11856 being replaced so the old value is not used in this insn. */
11858 if (GET_CODE (dest) == MEM)
11859 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
11864 else if (GET_CODE (x) == CLOBBER)
11867 len = GET_RTX_LENGTH (code);
11868 fmt = GET_RTX_FORMAT (code);
11870 for (i = 0; i < len; i++)
11875 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11876 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
11879 else if (fmt[i] == 'e')
11880 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
11884 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11885 pattern of an insn. X must be a REG. */
11888 reg_bitfield_target_p (x, body)
11894 if (GET_CODE (body) == SET)
11896 rtx dest = SET_DEST (body);
11898 unsigned int regno, tregno, endregno, endtregno;
11900 if (GET_CODE (dest) == ZERO_EXTRACT)
11901 target = XEXP (dest, 0);
11902 else if (GET_CODE (dest) == STRICT_LOW_PART)
11903 target = SUBREG_REG (XEXP (dest, 0));
11907 if (GET_CODE (target) == SUBREG)
11908 target = SUBREG_REG (target);
11910 if (GET_CODE (target) != REG)
11913 tregno = REGNO (target), regno = REGNO (x);
11914 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
11915 return target == x;
11917 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
11918 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11920 return endregno > tregno && regno < endtregno;
11923 else if (GET_CODE (body) == PARALLEL)
11924 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
11925 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
11931 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11932 as appropriate. I3 and I2 are the insns resulting from the combination
11933 insns including FROM (I2 may be zero).
11935 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
11936 not need REG_DEAD notes because they are being substituted for. This
11937 saves searching in the most common cases.
11939 Each note in the list is either ignored or placed on some insns, depending
11940 on the type of note. */
11943 distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
11947 rtx elim_i2, elim_i1;
11949 rtx note, next_note;
11952 for (note = notes; note; note = next_note)
11954 rtx place = 0, place2 = 0;
11956 /* If this NOTE references a pseudo register, ensure it references
11957 the latest copy of that register. */
11958 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
11959 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
11960 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
11962 next_note = XEXP (note, 1);
11963 switch (REG_NOTE_KIND (note))
11966 case REG_EXEC_COUNT:
11967 /* Doesn't matter much where we put this, as long as it's somewhere.
11968 It is preferable to keep these notes on branches, which is most
11969 likely to be i3. */
11973 case REG_EH_REGION:
11974 case REG_EH_RETHROW:
11975 /* These notes must remain with the call. It should not be
11976 possible for both I2 and I3 to be a call. */
11977 if (GET_CODE (i3) == CALL_INSN)
11979 else if (i2 && GET_CODE (i2) == CALL_INSN)
11986 /* Any clobbers for i3 may still exist, and so we must process
11987 REG_UNUSED notes from that insn.
11989 Any clobbers from i2 or i1 can only exist if they were added by
11990 recog_for_combine. In that case, recog_for_combine created the
11991 necessary REG_UNUSED notes. Trying to keep any original
11992 REG_UNUSED notes from these insns can cause incorrect output
11993 if it is for the same register as the original i3 dest.
11994 In that case, we will notice that the register is set in i3,
11995 and then add a REG_UNUSED note for the destination of i3, which
11996 is wrong. However, it is possible to have REG_UNUSED notes from
11997 i2 or i1 for register which were both used and clobbered, so
11998 we keep notes from i2 or i1 if they will turn into REG_DEAD
12001 /* If this register is set or clobbered in I3, put the note there
12002 unless there is one already. */
12003 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
12005 if (from_insn != i3)
12008 if (! (GET_CODE (XEXP (note, 0)) == REG
12009 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
12010 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
12013 /* Otherwise, if this register is used by I3, then this register
12014 now dies here, so we must put a REG_DEAD note here unless there
12016 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
12017 && ! (GET_CODE (XEXP (note, 0)) == REG
12018 ? find_regno_note (i3, REG_DEAD,
12019 REGNO (XEXP (note, 0)))
12020 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
12022 PUT_REG_NOTE_KIND (note, REG_DEAD);
12031 /* These notes say something about results of an insn. We can
12032 only support them if they used to be on I3 in which case they
12033 remain on I3. Otherwise they are ignored.
12035 If the note refers to an expression that is not a constant, we
12036 must also ignore the note since we cannot tell whether the
12037 equivalence is still true. It might be possible to do
12038 slightly better than this (we only have a problem if I2DEST
12039 or I1DEST is present in the expression), but it doesn't
12040 seem worth the trouble. */
12042 if (from_insn == i3
12043 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
12048 case REG_NO_CONFLICT:
12049 /* These notes say something about how a register is used. They must
12050 be present on any use of the register in I2 or I3. */
12051 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12054 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12064 /* This can show up in several ways -- either directly in the
12065 pattern, or hidden off in the constant pool with (or without?)
12066 a REG_EQUAL note. */
12067 /* ??? Ignore the without-reg_equal-note problem for now. */
12068 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12069 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12070 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12071 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12075 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12076 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12077 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12078 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12088 /* It is too much trouble to try to see if this note is still
12089 correct in all situations. It is better to simply delete it. */
12093 /* If the insn previously containing this note still exists,
12094 put it back where it was. Otherwise move it to the previous
12095 insn. Adjust the corresponding REG_LIBCALL note. */
12096 if (GET_CODE (from_insn) != NOTE)
12100 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
12101 place = prev_real_insn (from_insn);
12103 XEXP (tem, 0) = place;
12108 /* This is handled similarly to REG_RETVAL. */
12109 if (GET_CODE (from_insn) != NOTE)
12113 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
12114 place = next_real_insn (from_insn);
12116 XEXP (tem, 0) = place;
12121 /* If the register is used as an input in I3, it dies there.
12122 Similarly for I2, if it is non-zero and adjacent to I3.
12124 If the register is not used as an input in either I3 or I2
12125 and it is not one of the registers we were supposed to eliminate,
12126 there are two possibilities. We might have a non-adjacent I2
12127 or we might have somehow eliminated an additional register
12128 from a computation. For example, we might have had A & B where
12129 we discover that B will always be zero. In this case we will
12130 eliminate the reference to A.
12132 In both cases, we must search to see if we can find a previous
12133 use of A and put the death note there. */
12136 && GET_CODE (from_insn) == CALL_INSN
12137 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12139 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12141 else if (i2 != 0 && next_nonnote_insn (i2) == i3
12142 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12145 if (XEXP (note, 0) == elim_i2 || XEXP (note, 0) == elim_i1)
12150 basic_block bb = BASIC_BLOCK (this_basic_block);
12152 for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem))
12154 if (GET_RTX_CLASS (GET_CODE (tem)) != 'i')
12156 if (tem == bb->head)
12161 /* If the register is being set at TEM, see if that is all
12162 TEM is doing. If so, delete TEM. Otherwise, make this
12163 into a REG_UNUSED note instead. */
12164 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
12166 rtx set = single_set (tem);
12167 rtx inner_dest = 0;
12169 rtx cc0_setter = NULL_RTX;
12173 for (inner_dest = SET_DEST (set);
12174 GET_CODE (inner_dest) == STRICT_LOW_PART
12175 || GET_CODE (inner_dest) == SUBREG
12176 || GET_CODE (inner_dest) == ZERO_EXTRACT;
12177 inner_dest = XEXP (inner_dest, 0))
12180 /* Verify that it was the set, and not a clobber that
12181 modified the register.
12183 CC0 targets must be careful to maintain setter/user
12184 pairs. If we cannot delete the setter due to side
12185 effects, mark the user with an UNUSED note instead
12188 if (set != 0 && ! side_effects_p (SET_SRC (set))
12189 && rtx_equal_p (XEXP (note, 0), inner_dest)
12191 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12192 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12193 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12197 /* Move the notes and links of TEM elsewhere.
12198 This might delete other dead insns recursively.
12199 First set the pattern to something that won't use
12202 PATTERN (tem) = pc_rtx;
12204 distribute_notes (REG_NOTES (tem), tem, tem,
12205 NULL_RTX, NULL_RTX, NULL_RTX);
12206 distribute_links (LOG_LINKS (tem));
12208 PUT_CODE (tem, NOTE);
12209 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
12210 NOTE_SOURCE_FILE (tem) = 0;
12213 /* Delete the setter too. */
12216 PATTERN (cc0_setter) = pc_rtx;
12218 distribute_notes (REG_NOTES (cc0_setter),
12219 cc0_setter, cc0_setter,
12220 NULL_RTX, NULL_RTX, NULL_RTX);
12221 distribute_links (LOG_LINKS (cc0_setter));
12223 PUT_CODE (cc0_setter, NOTE);
12224 NOTE_LINE_NUMBER (cc0_setter)
12225 = NOTE_INSN_DELETED;
12226 NOTE_SOURCE_FILE (cc0_setter) = 0;
12230 /* If the register is both set and used here, put the
12231 REG_DEAD note here, but place a REG_UNUSED note
12232 here too unless there already is one. */
12233 else if (reg_referenced_p (XEXP (note, 0),
12238 if (! find_regno_note (tem, REG_UNUSED,
12239 REGNO (XEXP (note, 0))))
12241 = gen_rtx_EXPR_LIST (REG_UNUSED, XEXP (note, 0),
12246 PUT_REG_NOTE_KIND (note, REG_UNUSED);
12248 /* If there isn't already a REG_UNUSED note, put one
12250 if (! find_regno_note (tem, REG_UNUSED,
12251 REGNO (XEXP (note, 0))))
12256 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12257 || (GET_CODE (tem) == CALL_INSN
12258 && find_reg_fusage (tem, USE, XEXP (note, 0))))
12262 /* If we are doing a 3->2 combination, and we have a
12263 register which formerly died in i3 and was not used
12264 by i2, which now no longer dies in i3 and is used in
12265 i2 but does not die in i2, and place is between i2
12266 and i3, then we may need to move a link from place to
12268 if (i2 && INSN_UID (place) <= max_uid_cuid
12269 && INSN_CUID (place) > INSN_CUID (i2)
12270 && from_insn && INSN_CUID (from_insn) > INSN_CUID (i2)
12271 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12273 rtx links = LOG_LINKS (place);
12274 LOG_LINKS (place) = 0;
12275 distribute_links (links);
12280 if (tem == bb->head)
12284 /* We haven't found an insn for the death note and it
12285 is still a REG_DEAD note, but we have hit the beginning
12286 of the block. If the existing life info says the reg
12287 was dead, there's nothing left to do. Otherwise, we'll
12288 need to do a global life update after combine. */
12289 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
12290 && REGNO_REG_SET_P (bb->global_live_at_start,
12291 REGNO (XEXP (note, 0))))
12293 SET_BIT (refresh_blocks, this_basic_block);
12298 /* If the register is set or already dead at PLACE, we needn't do
12299 anything with this note if it is still a REG_DEAD note.
12300 We can here if it is set at all, not if is it totally replace,
12301 which is what `dead_or_set_p' checks, so also check for it being
12304 if (place && REG_NOTE_KIND (note) == REG_DEAD)
12306 unsigned int regno = REGNO (XEXP (note, 0));
12308 if (dead_or_set_p (place, XEXP (note, 0))
12309 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12311 /* Unless the register previously died in PLACE, clear
12312 reg_last_death. [I no longer understand why this is
12314 if (reg_last_death[regno] != place)
12315 reg_last_death[regno] = 0;
12319 reg_last_death[regno] = place;
12321 /* If this is a death note for a hard reg that is occupying
12322 multiple registers, ensure that we are still using all
12323 parts of the object. If we find a piece of the object
12324 that is unused, we must add a USE for that piece before
12325 PLACE and put the appropriate REG_DEAD note on it.
12327 An alternative would be to put a REG_UNUSED for the pieces
12328 on the insn that set the register, but that can't be done if
12329 it is not in the same block. It is simpler, though less
12330 efficient, to add the USE insns. */
12332 if (place && regno < FIRST_PSEUDO_REGISTER
12333 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
12335 unsigned int endregno
12336 = regno + HARD_REGNO_NREGS (regno,
12337 GET_MODE (XEXP (note, 0)));
12341 for (i = regno; i < endregno; i++)
12342 if (! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12343 && ! find_regno_fusage (place, USE, i))
12345 rtx piece = gen_rtx_REG (reg_raw_mode[i], i);
12348 /* See if we already placed a USE note for this
12349 register in front of PLACE. */
12351 GET_CODE (PREV_INSN (p)) == INSN
12352 && GET_CODE (PATTERN (PREV_INSN (p))) == USE;
12354 if (rtx_equal_p (piece,
12355 XEXP (PATTERN (PREV_INSN (p)), 0)))
12364 = emit_insn_before (gen_rtx_USE (VOIDmode,
12367 REG_NOTES (use_insn)
12368 = gen_rtx_EXPR_LIST (REG_DEAD, piece,
12369 REG_NOTES (use_insn));
12375 /* Check for the case where the register dying partially
12376 overlaps the register set by this insn. */
12378 for (i = regno; i < endregno; i++)
12379 if (dead_or_set_regno_p (place, i))
12387 /* Put only REG_DEAD notes for pieces that are
12388 still used and that are not already dead or set. */
12390 for (i = regno; i < endregno; i++)
12392 rtx piece = gen_rtx_REG (reg_raw_mode[i], i);
12394 if ((reg_referenced_p (piece, PATTERN (place))
12395 || (GET_CODE (place) == CALL_INSN
12396 && find_reg_fusage (place, USE, piece)))
12397 && ! dead_or_set_p (place, piece)
12398 && ! reg_bitfield_target_p (piece,
12401 = gen_rtx_EXPR_LIST (REG_DEAD, piece,
12402 REG_NOTES (place));
12412 /* Any other notes should not be present at this point in the
12419 XEXP (note, 1) = REG_NOTES (place);
12420 REG_NOTES (place) = note;
12422 else if ((REG_NOTE_KIND (note) == REG_DEAD
12423 || REG_NOTE_KIND (note) == REG_UNUSED)
12424 && GET_CODE (XEXP (note, 0)) == REG)
12425 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
12429 if ((REG_NOTE_KIND (note) == REG_DEAD
12430 || REG_NOTE_KIND (note) == REG_UNUSED)
12431 && GET_CODE (XEXP (note, 0)) == REG)
12432 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
12434 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
12435 REG_NOTE_KIND (note),
12437 REG_NOTES (place2));
12442 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12443 I3, I2, and I1 to new locations. This is also called in one case to
12444 add a link pointing at I3 when I3's destination is changed. */
12447 distribute_links (links)
12450 rtx link, next_link;
12452 for (link = links; link; link = next_link)
12458 next_link = XEXP (link, 1);
12460 /* If the insn that this link points to is a NOTE or isn't a single
12461 set, ignore it. In the latter case, it isn't clear what we
12462 can do other than ignore the link, since we can't tell which
12463 register it was for. Such links wouldn't be used by combine
12466 It is not possible for the destination of the target of the link to
12467 have been changed by combine. The only potential of this is if we
12468 replace I3, I2, and I1 by I3 and I2. But in that case the
12469 destination of I2 also remains unchanged. */
12471 if (GET_CODE (XEXP (link, 0)) == NOTE
12472 || (set = single_set (XEXP (link, 0))) == 0)
12475 reg = SET_DEST (set);
12476 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12477 || GET_CODE (reg) == SIGN_EXTRACT
12478 || GET_CODE (reg) == STRICT_LOW_PART)
12479 reg = XEXP (reg, 0);
12481 /* A LOG_LINK is defined as being placed on the first insn that uses
12482 a register and points to the insn that sets the register. Start
12483 searching at the next insn after the target of the link and stop
12484 when we reach a set of the register or the end of the basic block.
12486 Note that this correctly handles the link that used to point from
12487 I3 to I2. Also note that not much searching is typically done here
12488 since most links don't point very far away. */
12490 for (insn = NEXT_INSN (XEXP (link, 0));
12491 (insn && (this_basic_block == n_basic_blocks - 1
12492 || BLOCK_HEAD (this_basic_block + 1) != insn));
12493 insn = NEXT_INSN (insn))
12494 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
12495 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12497 if (reg_referenced_p (reg, PATTERN (insn)))
12501 else if (GET_CODE (insn) == CALL_INSN
12502 && find_reg_fusage (insn, USE, reg))
12508 /* If we found a place to put the link, place it there unless there
12509 is already a link to the same insn as LINK at that point. */
12515 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12516 if (XEXP (link2, 0) == XEXP (link, 0))
12521 XEXP (link, 1) = LOG_LINKS (place);
12522 LOG_LINKS (place) = link;
12524 /* Set added_links_insn to the earliest insn we added a
12526 if (added_links_insn == 0
12527 || INSN_CUID (added_links_insn) > INSN_CUID (place))
12528 added_links_insn = place;
12534 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12540 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
12541 && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE)
12542 insn = NEXT_INSN (insn);
12544 if (INSN_UID (insn) > max_uid_cuid)
12547 return INSN_CUID (insn);
12551 dump_combine_stats (file)
12556 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12557 combine_attempts, combine_merges, combine_extras, combine_successes);
12561 dump_combine_total_stats (file)
12566 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12567 total_attempts, total_merges, total_extras, total_successes);