1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
87 #include "hard-reg-set.h"
88 #include "basic-block.h"
89 #include "insn-config.h"
91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
93 #include "insn-attr.h"
98 #include "insn-codes.h"
99 #include "rtlhooks-def.h"
100 /* Include output.h for dump_file. */
104 #include "tree-pass.h"
108 /* Number of attempts to combine instructions in this function. */
110 static int combine_attempts;
112 /* Number of attempts that got as far as substitution in this function. */
114 static int combine_merges;
116 /* Number of instructions combined with added SETs in this function. */
118 static int combine_extras;
120 /* Number of instructions combined in this function. */
122 static int combine_successes;
124 /* Totals over entire compilation. */
126 static int total_attempts, total_merges, total_extras, total_successes;
128 /* combine_instructions may try to replace the right hand side of the
129 second instruction with the value of an associated REG_EQUAL note
130 before throwing it at try_combine. That is problematic when there
131 is a REG_DEAD note for a register used in the old right hand side
132 and can cause distribute_notes to do wrong things. This is the
133 second instruction if it has been so modified, null otherwise. */
137 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
139 static rtx i2mod_old_rhs;
141 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
143 static rtx i2mod_new_rhs;
145 typedef struct reg_stat_struct {
146 /* Record last point of death of (hard or pseudo) register n. */
149 /* Record last point of modification of (hard or pseudo) register n. */
152 /* The next group of fields allows the recording of the last value assigned
153 to (hard or pseudo) register n. We use this information to see if an
154 operation being processed is redundant given a prior operation performed
155 on the register. For example, an `and' with a constant is redundant if
156 all the zero bits are already known to be turned off.
158 We use an approach similar to that used by cse, but change it in the
161 (1) We do not want to reinitialize at each label.
162 (2) It is useful, but not critical, to know the actual value assigned
163 to a register. Often just its form is helpful.
165 Therefore, we maintain the following fields:
167 last_set_value the last value assigned
168 last_set_label records the value of label_tick when the
169 register was assigned
170 last_set_table_tick records the value of label_tick when a
171 value using the register is assigned
172 last_set_invalid set to nonzero when it is not valid
173 to use the value of this register in some
176 To understand the usage of these tables, it is important to understand
177 the distinction between the value in last_set_value being valid and
178 the register being validly contained in some other expression in the
181 (The next two parameters are out of date).
183 reg_stat[i].last_set_value is valid if it is nonzero, and either
184 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
186 Register I may validly appear in any expression returned for the value
187 of another register if reg_n_sets[i] is 1. It may also appear in the
188 value for register J if reg_stat[j].last_set_invalid is zero, or
189 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
191 If an expression is found in the table containing a register which may
192 not validly appear in an expression, the register is replaced by
193 something that won't match, (clobber (const_int 0)). */
195 /* Record last value assigned to (hard or pseudo) register n. */
199 /* Record the value of label_tick when an expression involving register n
200 is placed in last_set_value. */
202 int last_set_table_tick;
204 /* Record the value of label_tick when the value for register n is placed in
209 /* These fields are maintained in parallel with last_set_value and are
210 used to store the mode in which the register was last set, the bits
211 that were known to be zero when it was last set, and the number of
212 sign bits copies it was known to have when it was last set. */
214 unsigned HOST_WIDE_INT last_set_nonzero_bits;
215 char last_set_sign_bit_copies;
216 ENUM_BITFIELD(machine_mode) last_set_mode : 8;
218 /* Set nonzero if references to register n in expressions should not be
219 used. last_set_invalid is set nonzero when this register is being
220 assigned to and last_set_table_tick == label_tick. */
222 char last_set_invalid;
224 /* Some registers that are set more than once and used in more than one
225 basic block are nevertheless always set in similar ways. For example,
226 a QImode register may be loaded from memory in two places on a machine
227 where byte loads zero extend.
229 We record in the following fields if a register has some leading bits
230 that are always equal to the sign bit, and what we know about the
231 nonzero bits of a register, specifically which bits are known to be
234 If an entry is zero, it means that we don't know anything special. */
236 unsigned char sign_bit_copies;
238 unsigned HOST_WIDE_INT nonzero_bits;
240 /* Record the value of the label_tick when the last truncation
241 happened. The field truncated_to_mode is only valid if
242 truncation_label == label_tick. */
244 int truncation_label;
246 /* Record the last truncation seen for this register. If truncation
247 is not a nop to this mode we might be able to save an explicit
248 truncation if we know that value already contains a truncated
251 ENUM_BITFIELD(machine_mode) truncated_to_mode : 8;
254 DEF_VEC_O(reg_stat_type);
255 DEF_VEC_ALLOC_O(reg_stat_type,heap);
257 static VEC(reg_stat_type,heap) *reg_stat;
259 /* Record the luid of the last insn that invalidated memory
260 (anything that writes memory, and subroutine calls, but not pushes). */
262 static int mem_last_set;
264 /* Record the luid of the last CALL_INSN
265 so we can tell whether a potential combination crosses any calls. */
267 static int last_call_luid;
269 /* When `subst' is called, this is the insn that is being modified
270 (by combining in a previous insn). The PATTERN of this insn
271 is still the old pattern partially modified and it should not be
272 looked at, but this may be used to examine the successors of the insn
273 to judge whether a simplification is valid. */
275 static rtx subst_insn;
277 /* This is the lowest LUID that `subst' is currently dealing with.
278 get_last_value will not return a value if the register was set at or
279 after this LUID. If not for this mechanism, we could get confused if
280 I2 or I1 in try_combine were an insn that used the old value of a register
281 to obtain a new value. In that case, we might erroneously get the
282 new value of the register when we wanted the old one. */
284 static int subst_low_luid;
286 /* This contains any hard registers that are used in newpat; reg_dead_at_p
287 must consider all these registers to be always live. */
289 static HARD_REG_SET newpat_used_regs;
291 /* This is an insn to which a LOG_LINKS entry has been added. If this
292 insn is the earlier than I2 or I3, combine should rescan starting at
295 static rtx added_links_insn;
297 /* Basic block in which we are performing combines. */
298 static basic_block this_basic_block;
299 static bool optimize_this_for_speed_p;
302 /* Length of the currently allocated uid_insn_cost array. */
304 static int max_uid_known;
306 /* The following array records the insn_rtx_cost for every insn
307 in the instruction stream. */
309 static int *uid_insn_cost;
311 /* The following array records the LOG_LINKS for every insn in the
312 instruction stream as an INSN_LIST rtx. */
314 static rtx *uid_log_links;
316 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
317 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
319 /* Incremented for each basic block. */
321 static int label_tick;
323 /* Reset to label_tick for each extended basic block in scanning order. */
325 static int label_tick_ebb_start;
327 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
328 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
330 static enum machine_mode nonzero_bits_mode;
332 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
333 be safely used. It is zero while computing them and after combine has
334 completed. This former test prevents propagating values based on
335 previously set values, which can be incorrect if a variable is modified
338 static int nonzero_sign_valid;
341 /* Record one modification to rtl structure
342 to be undone by storing old_contents into *where. */
344 enum undo_kind { UNDO_RTX, UNDO_INT, UNDO_MODE };
350 union { rtx r; int i; enum machine_mode m; } old_contents;
351 union { rtx *r; int *i; } where;
354 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
355 num_undo says how many are currently recorded.
357 other_insn is nonzero if we have modified some other insn in the process
358 of working on subst_insn. It must be verified too. */
367 static struct undobuf undobuf;
369 /* Number of times the pseudo being substituted for
370 was found and replaced. */
372 static int n_occurrences;
374 static rtx reg_nonzero_bits_for_combine (const_rtx, enum machine_mode, const_rtx,
376 unsigned HOST_WIDE_INT,
377 unsigned HOST_WIDE_INT *);
378 static rtx reg_num_sign_bit_copies_for_combine (const_rtx, enum machine_mode, const_rtx,
380 unsigned int, unsigned int *);
381 static void do_SUBST (rtx *, rtx);
382 static void do_SUBST_INT (int *, int);
383 static void init_reg_last (void);
384 static void setup_incoming_promotions (rtx);
385 static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *);
386 static int cant_combine_insn_p (rtx);
387 static int can_combine_p (rtx, rtx, rtx, rtx, rtx *, rtx *);
388 static int combinable_i3pat (rtx, rtx *, rtx, rtx, int, rtx *);
389 static int contains_muldiv (rtx);
390 static rtx try_combine (rtx, rtx, rtx, int *);
391 static void undo_all (void);
392 static void undo_commit (void);
393 static rtx *find_split_point (rtx *, rtx, bool);
394 static rtx subst (rtx, rtx, rtx, int, int);
395 static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
396 static rtx simplify_if_then_else (rtx);
397 static rtx simplify_set (rtx);
398 static rtx simplify_logical (rtx);
399 static rtx expand_compound_operation (rtx);
400 static const_rtx expand_field_assignment (const_rtx);
401 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
402 rtx, unsigned HOST_WIDE_INT, int, int, int);
403 static rtx extract_left_shift (rtx, int);
404 static rtx make_compound_operation (rtx, enum rtx_code);
405 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
406 unsigned HOST_WIDE_INT *);
407 static rtx canon_reg_for_combine (rtx, rtx);
408 static rtx force_to_mode (rtx, enum machine_mode,
409 unsigned HOST_WIDE_INT, int);
410 static rtx if_then_else_cond (rtx, rtx *, rtx *);
411 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
412 static int rtx_equal_for_field_assignment_p (rtx, rtx);
413 static rtx make_field_assignment (rtx);
414 static rtx apply_distributive_law (rtx);
415 static rtx distribute_and_simplify_rtx (rtx, int);
416 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
417 unsigned HOST_WIDE_INT);
418 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
419 unsigned HOST_WIDE_INT);
420 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
421 HOST_WIDE_INT, enum machine_mode, int *);
422 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
423 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
425 static int recog_for_combine (rtx *, rtx, rtx *);
426 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
427 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
428 static void update_table_tick (rtx);
429 static void record_value_for_reg (rtx, rtx, rtx);
430 static void check_promoted_subreg (rtx, rtx);
431 static void record_dead_and_set_regs_1 (rtx, const_rtx, void *);
432 static void record_dead_and_set_regs (rtx);
433 static int get_last_value_validate (rtx *, rtx, int, int);
434 static rtx get_last_value (const_rtx);
435 static int use_crosses_set_p (const_rtx, int);
436 static void reg_dead_at_p_1 (rtx, const_rtx, void *);
437 static int reg_dead_at_p (rtx, rtx);
438 static void move_deaths (rtx, rtx, int, rtx, rtx *);
439 static int reg_bitfield_target_p (rtx, rtx);
440 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx);
441 static void distribute_links (rtx);
442 static void mark_used_regs_combine (rtx);
443 static void record_promoted_value (rtx, rtx);
444 static int unmentioned_reg_p_1 (rtx *, void *);
445 static bool unmentioned_reg_p (rtx, rtx);
446 static int record_truncated_value (rtx *, void *);
447 static void record_truncated_values (rtx *, void *);
448 static bool reg_truncated_to_mode (enum machine_mode, const_rtx);
449 static rtx gen_lowpart_or_truncate (enum machine_mode, rtx);
452 /* It is not safe to use ordinary gen_lowpart in combine.
453 See comments in gen_lowpart_for_combine. */
454 #undef RTL_HOOKS_GEN_LOWPART
455 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
457 /* Our implementation of gen_lowpart never emits a new pseudo. */
458 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
459 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
461 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
462 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
464 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
465 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
467 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
468 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
470 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
473 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
474 PATTERN can not be split. Otherwise, it returns an insn sequence.
475 This is a wrapper around split_insns which ensures that the
476 reg_stat vector is made larger if the splitter creates a new
480 combine_split_insns (rtx pattern, rtx insn)
485 ret = split_insns (pattern, insn);
486 nregs = max_reg_num ();
487 if (nregs > VEC_length (reg_stat_type, reg_stat))
488 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
492 /* This is used by find_single_use to locate an rtx in LOC that
493 contains exactly one use of DEST, which is typically either a REG
494 or CC0. It returns a pointer to the innermost rtx expression
495 containing DEST. Appearances of DEST that are being used to
496 totally replace it are not counted. */
499 find_single_use_1 (rtx dest, rtx *loc)
502 enum rtx_code code = GET_CODE (x);
520 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
521 of a REG that occupies all of the REG, the insn uses DEST if
522 it is mentioned in the destination or the source. Otherwise, we
523 need just check the source. */
524 if (GET_CODE (SET_DEST (x)) != CC0
525 && GET_CODE (SET_DEST (x)) != PC
526 && !REG_P (SET_DEST (x))
527 && ! (GET_CODE (SET_DEST (x)) == SUBREG
528 && REG_P (SUBREG_REG (SET_DEST (x)))
529 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
530 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
531 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
532 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
535 return find_single_use_1 (dest, &SET_SRC (x));
539 return find_single_use_1 (dest, &XEXP (x, 0));
545 /* If it wasn't one of the common cases above, check each expression and
546 vector of this code. Look for a unique usage of DEST. */
548 fmt = GET_RTX_FORMAT (code);
549 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
553 if (dest == XEXP (x, i)
554 || (REG_P (dest) && REG_P (XEXP (x, i))
555 && REGNO (dest) == REGNO (XEXP (x, i))))
558 this_result = find_single_use_1 (dest, &XEXP (x, i));
561 result = this_result;
562 else if (this_result)
563 /* Duplicate usage. */
566 else if (fmt[i] == 'E')
570 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
572 if (XVECEXP (x, i, j) == dest
574 && REG_P (XVECEXP (x, i, j))
575 && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
578 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
581 result = this_result;
582 else if (this_result)
592 /* See if DEST, produced in INSN, is used only a single time in the
593 sequel. If so, return a pointer to the innermost rtx expression in which
596 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
598 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
599 care about REG_DEAD notes or LOG_LINKS.
601 Otherwise, we find the single use by finding an insn that has a
602 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
603 only referenced once in that insn, we know that it must be the first
604 and last insn referencing DEST. */
607 find_single_use (rtx dest, rtx insn, rtx *ploc)
617 next = NEXT_INSN (insn);
619 || (!NONJUMP_INSN_P (next) && !JUMP_P (next)))
622 result = find_single_use_1 (dest, &PATTERN (next));
632 bb = BLOCK_FOR_INSN (insn);
633 for (next = NEXT_INSN (insn);
634 next && BLOCK_FOR_INSN (next) == bb;
635 next = NEXT_INSN (next))
636 if (INSN_P (next) && dead_or_set_p (next, dest))
638 for (link = LOG_LINKS (next); link; link = XEXP (link, 1))
639 if (XEXP (link, 0) == insn)
644 result = find_single_use_1 (dest, &PATTERN (next));
654 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
655 insn. The substitution can be undone by undo_all. If INTO is already
656 set to NEWVAL, do not record this change. Because computing NEWVAL might
657 also call SUBST, we have to compute it before we put anything into
661 do_SUBST (rtx *into, rtx newval)
666 if (oldval == newval)
669 /* We'd like to catch as many invalid transformations here as
670 possible. Unfortunately, there are way too many mode changes
671 that are perfectly valid, so we'd waste too much effort for
672 little gain doing the checks here. Focus on catching invalid
673 transformations involving integer constants. */
674 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
675 && CONST_INT_P (newval))
677 /* Sanity check that we're replacing oldval with a CONST_INT
678 that is a valid sign-extension for the original mode. */
679 gcc_assert (INTVAL (newval)
680 == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
682 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
683 CONST_INT is not valid, because after the replacement, the
684 original mode would be gone. Unfortunately, we can't tell
685 when do_SUBST is called to replace the operand thereof, so we
686 perform this test on oldval instead, checking whether an
687 invalid replacement took place before we got here. */
688 gcc_assert (!(GET_CODE (oldval) == SUBREG
689 && CONST_INT_P (SUBREG_REG (oldval))));
690 gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
691 && CONST_INT_P (XEXP (oldval, 0))));
695 buf = undobuf.frees, undobuf.frees = buf->next;
697 buf = XNEW (struct undo);
699 buf->kind = UNDO_RTX;
701 buf->old_contents.r = oldval;
704 buf->next = undobuf.undos, undobuf.undos = buf;
707 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
709 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
710 for the value of a HOST_WIDE_INT value (including CONST_INT) is
714 do_SUBST_INT (int *into, int newval)
719 if (oldval == newval)
723 buf = undobuf.frees, undobuf.frees = buf->next;
725 buf = XNEW (struct undo);
727 buf->kind = UNDO_INT;
729 buf->old_contents.i = oldval;
732 buf->next = undobuf.undos, undobuf.undos = buf;
735 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
737 /* Similar to SUBST, but just substitute the mode. This is used when
738 changing the mode of a pseudo-register, so that any other
739 references to the entry in the regno_reg_rtx array will change as
743 do_SUBST_MODE (rtx *into, enum machine_mode newval)
746 enum machine_mode oldval = GET_MODE (*into);
748 if (oldval == newval)
752 buf = undobuf.frees, undobuf.frees = buf->next;
754 buf = XNEW (struct undo);
756 buf->kind = UNDO_MODE;
758 buf->old_contents.m = oldval;
759 adjust_reg_mode (*into, newval);
761 buf->next = undobuf.undos, undobuf.undos = buf;
764 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE(&(INTO), (NEWVAL))
766 /* Subroutine of try_combine. Determine whether the combine replacement
767 patterns NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to
768 insn_rtx_cost that the original instruction sequence I1, I2, I3 and
769 undobuf.other_insn. Note that I1 and/or NEWI2PAT may be NULL_RTX.
770 NEWOTHERPAT and undobuf.other_insn may also both be NULL_RTX. This
771 function returns false, if the costs of all instructions can be
772 estimated, and the replacements are more expensive than the original
776 combine_validate_cost (rtx i1, rtx i2, rtx i3, rtx newpat, rtx newi2pat,
779 int i1_cost, i2_cost, i3_cost;
780 int new_i2_cost, new_i3_cost;
781 int old_cost, new_cost;
783 /* Lookup the original insn_rtx_costs. */
784 i2_cost = INSN_COST (i2);
785 i3_cost = INSN_COST (i3);
789 i1_cost = INSN_COST (i1);
790 old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0)
791 ? i1_cost + i2_cost + i3_cost : 0;
795 old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
799 /* Calculate the replacement insn_rtx_costs. */
800 new_i3_cost = insn_rtx_cost (newpat, optimize_this_for_speed_p);
803 new_i2_cost = insn_rtx_cost (newi2pat, optimize_this_for_speed_p);
804 new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
805 ? new_i2_cost + new_i3_cost : 0;
809 new_cost = new_i3_cost;
813 if (undobuf.other_insn)
815 int old_other_cost, new_other_cost;
817 old_other_cost = INSN_COST (undobuf.other_insn);
818 new_other_cost = insn_rtx_cost (newotherpat, optimize_this_for_speed_p);
819 if (old_other_cost > 0 && new_other_cost > 0)
821 old_cost += old_other_cost;
822 new_cost += new_other_cost;
828 /* Disallow this recombination if both new_cost and old_cost are
829 greater than zero, and new_cost is greater than old cost. */
831 && new_cost > old_cost)
838 "rejecting combination of insns %d, %d and %d\n",
839 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
840 fprintf (dump_file, "original costs %d + %d + %d = %d\n",
841 i1_cost, i2_cost, i3_cost, old_cost);
846 "rejecting combination of insns %d and %d\n",
847 INSN_UID (i2), INSN_UID (i3));
848 fprintf (dump_file, "original costs %d + %d = %d\n",
849 i2_cost, i3_cost, old_cost);
854 fprintf (dump_file, "replacement costs %d + %d = %d\n",
855 new_i2_cost, new_i3_cost, new_cost);
858 fprintf (dump_file, "replacement cost %d\n", new_cost);
864 /* Update the uid_insn_cost array with the replacement costs. */
865 INSN_COST (i2) = new_i2_cost;
866 INSN_COST (i3) = new_i3_cost;
874 /* Delete any insns that copy a register to itself. */
877 delete_noop_moves (void)
884 for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
886 next = NEXT_INSN (insn);
887 if (INSN_P (insn) && noop_move_p (insn))
890 fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn));
892 delete_insn_and_edges (insn);
899 /* Fill in log links field for all insns. */
902 create_log_links (void)
906 df_ref *def_vec, *use_vec;
908 next_use = XCNEWVEC (rtx, max_reg_num ());
910 /* Pass through each block from the end, recording the uses of each
911 register and establishing log links when def is encountered.
912 Note that we do not clear next_use array in order to save time,
913 so we have to test whether the use is in the same basic block as def.
915 There are a few cases below when we do not consider the definition or
916 usage -- these are taken from original flow.c did. Don't ask me why it is
917 done this way; I don't know and if it works, I don't want to know. */
921 FOR_BB_INSNS_REVERSE (bb, insn)
923 if (!NONDEBUG_INSN_P (insn))
926 /* Log links are created only once. */
927 gcc_assert (!LOG_LINKS (insn));
929 for (def_vec = DF_INSN_DEFS (insn); *def_vec; def_vec++)
931 df_ref def = *def_vec;
932 int regno = DF_REF_REGNO (def);
935 if (!next_use[regno])
938 /* Do not consider if it is pre/post modification in MEM. */
939 if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY)
942 /* Do not make the log link for frame pointer. */
943 if ((regno == FRAME_POINTER_REGNUM
944 && (! reload_completed || frame_pointer_needed))
945 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
946 || (regno == HARD_FRAME_POINTER_REGNUM
947 && (! reload_completed || frame_pointer_needed))
949 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
950 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
955 use_insn = next_use[regno];
956 if (BLOCK_FOR_INSN (use_insn) == bb)
960 We don't build a LOG_LINK for hard registers contained
961 in ASM_OPERANDs. If these registers get replaced,
962 we might wind up changing the semantics of the insn,
963 even if reload can make what appear to be valid
964 assignments later. */
965 if (regno >= FIRST_PSEUDO_REGISTER
966 || asm_noperands (PATTERN (use_insn)) < 0)
968 /* Don't add duplicate links between instructions. */
970 for (links = LOG_LINKS (use_insn); links;
971 links = XEXP (links, 1))
972 if (insn == XEXP (links, 0))
976 LOG_LINKS (use_insn) =
977 alloc_INSN_LIST (insn, LOG_LINKS (use_insn));
980 next_use[regno] = NULL_RTX;
983 for (use_vec = DF_INSN_USES (insn); *use_vec; use_vec++)
985 df_ref use = *use_vec;
986 int regno = DF_REF_REGNO (use);
988 /* Do not consider the usage of the stack pointer
990 if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE)
993 next_use[regno] = insn;
1001 /* Clear LOG_LINKS fields of insns. */
1004 clear_log_links (void)
1008 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
1010 free_INSN_LIST_list (&LOG_LINKS (insn));
1013 /* Main entry point for combiner. F is the first insn of the function.
1014 NREGS is the first unused pseudo-reg number.
1016 Return nonzero if the combiner has turned an indirect jump
1017 instruction into a direct jump. */
1019 combine_instructions (rtx f, unsigned int nregs)
1025 rtx links, nextlinks;
1027 basic_block last_bb;
1029 int new_direct_jump_p = 0;
1031 for (first = f; first && !INSN_P (first); )
1032 first = NEXT_INSN (first);
1036 combine_attempts = 0;
1039 combine_successes = 0;
1041 rtl_hooks = combine_rtl_hooks;
1043 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
1045 init_recog_no_volatile ();
1047 /* Allocate array for insn info. */
1048 max_uid_known = get_max_uid ();
1049 uid_log_links = XCNEWVEC (rtx, max_uid_known + 1);
1050 uid_insn_cost = XCNEWVEC (int, max_uid_known + 1);
1052 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
1054 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1055 problems when, for example, we have j <<= 1 in a loop. */
1057 nonzero_sign_valid = 0;
1058 label_tick = label_tick_ebb_start = 1;
1060 /* Scan all SETs and see if we can deduce anything about what
1061 bits are known to be zero for some registers and how many copies
1062 of the sign bit are known to exist for those registers.
1064 Also set any known values so that we can use it while searching
1065 for what bits are known to be set. */
1067 setup_incoming_promotions (first);
1068 /* Allow the entry block and the first block to fall into the same EBB.
1069 Conceptually the incoming promotions are assigned to the entry block. */
1070 last_bb = ENTRY_BLOCK_PTR;
1072 create_log_links ();
1073 FOR_EACH_BB (this_basic_block)
1075 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1080 if (!single_pred_p (this_basic_block)
1081 || single_pred (this_basic_block) != last_bb)
1082 label_tick_ebb_start = label_tick;
1083 last_bb = this_basic_block;
1085 FOR_BB_INSNS (this_basic_block, insn)
1086 if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
1088 subst_low_luid = DF_INSN_LUID (insn);
1091 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
1093 record_dead_and_set_regs (insn);
1096 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
1097 if (REG_NOTE_KIND (links) == REG_INC)
1098 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
1102 /* Record the current insn_rtx_cost of this instruction. */
1103 if (NONJUMP_INSN_P (insn))
1104 INSN_COST (insn) = insn_rtx_cost (PATTERN (insn),
1105 optimize_this_for_speed_p);
1107 fprintf(dump_file, "insn_cost %d: %d\n",
1108 INSN_UID (insn), INSN_COST (insn));
1112 nonzero_sign_valid = 1;
1114 /* Now scan all the insns in forward order. */
1115 label_tick = label_tick_ebb_start = 1;
1117 setup_incoming_promotions (first);
1118 last_bb = ENTRY_BLOCK_PTR;
1120 FOR_EACH_BB (this_basic_block)
1122 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1127 if (!single_pred_p (this_basic_block)
1128 || single_pred (this_basic_block) != last_bb)
1129 label_tick_ebb_start = label_tick;
1130 last_bb = this_basic_block;
1132 rtl_profile_for_bb (this_basic_block);
1133 for (insn = BB_HEAD (this_basic_block);
1134 insn != NEXT_INSN (BB_END (this_basic_block));
1135 insn = next ? next : NEXT_INSN (insn))
1138 if (NONDEBUG_INSN_P (insn))
1140 /* See if we know about function return values before this
1141 insn based upon SUBREG flags. */
1142 check_promoted_subreg (insn, PATTERN (insn));
1144 /* See if we can find hardregs and subreg of pseudos in
1145 narrower modes. This could help turning TRUNCATEs
1147 note_uses (&PATTERN (insn), record_truncated_values, NULL);
1149 /* Try this insn with each insn it links back to. */
1151 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1152 if ((next = try_combine (insn, XEXP (links, 0),
1153 NULL_RTX, &new_direct_jump_p)) != 0)
1156 /* Try each sequence of three linked insns ending with this one. */
1158 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1160 rtx link = XEXP (links, 0);
1162 /* If the linked insn has been replaced by a note, then there
1163 is no point in pursuing this chain any further. */
1167 for (nextlinks = LOG_LINKS (link);
1169 nextlinks = XEXP (nextlinks, 1))
1170 if ((next = try_combine (insn, link,
1171 XEXP (nextlinks, 0),
1172 &new_direct_jump_p)) != 0)
1177 /* Try to combine a jump insn that uses CC0
1178 with a preceding insn that sets CC0, and maybe with its
1179 logical predecessor as well.
1180 This is how we make decrement-and-branch insns.
1181 We need this special code because data flow connections
1182 via CC0 do not get entered in LOG_LINKS. */
1185 && (prev = prev_nonnote_insn (insn)) != 0
1186 && NONJUMP_INSN_P (prev)
1187 && sets_cc0_p (PATTERN (prev)))
1189 if ((next = try_combine (insn, prev,
1190 NULL_RTX, &new_direct_jump_p)) != 0)
1193 for (nextlinks = LOG_LINKS (prev); nextlinks;
1194 nextlinks = XEXP (nextlinks, 1))
1195 if ((next = try_combine (insn, prev,
1196 XEXP (nextlinks, 0),
1197 &new_direct_jump_p)) != 0)
1201 /* Do the same for an insn that explicitly references CC0. */
1202 if (NONJUMP_INSN_P (insn)
1203 && (prev = prev_nonnote_insn (insn)) != 0
1204 && NONJUMP_INSN_P (prev)
1205 && sets_cc0_p (PATTERN (prev))
1206 && GET_CODE (PATTERN (insn)) == SET
1207 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
1209 if ((next = try_combine (insn, prev,
1210 NULL_RTX, &new_direct_jump_p)) != 0)
1213 for (nextlinks = LOG_LINKS (prev); nextlinks;
1214 nextlinks = XEXP (nextlinks, 1))
1215 if ((next = try_combine (insn, prev,
1216 XEXP (nextlinks, 0),
1217 &new_direct_jump_p)) != 0)
1221 /* Finally, see if any of the insns that this insn links to
1222 explicitly references CC0. If so, try this insn, that insn,
1223 and its predecessor if it sets CC0. */
1224 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1225 if (NONJUMP_INSN_P (XEXP (links, 0))
1226 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
1227 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
1228 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
1229 && NONJUMP_INSN_P (prev)
1230 && sets_cc0_p (PATTERN (prev))
1231 && (next = try_combine (insn, XEXP (links, 0),
1232 prev, &new_direct_jump_p)) != 0)
1236 /* Try combining an insn with two different insns whose results it
1238 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1239 for (nextlinks = XEXP (links, 1); nextlinks;
1240 nextlinks = XEXP (nextlinks, 1))
1241 if ((next = try_combine (insn, XEXP (links, 0),
1242 XEXP (nextlinks, 0),
1243 &new_direct_jump_p)) != 0)
1246 /* Try this insn with each REG_EQUAL note it links back to. */
1247 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1250 rtx temp = XEXP (links, 0);
1251 if ((set = single_set (temp)) != 0
1252 && (note = find_reg_equal_equiv_note (temp)) != 0
1253 && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
1254 /* Avoid using a register that may already been marked
1255 dead by an earlier instruction. */
1256 && ! unmentioned_reg_p (note, SET_SRC (set))
1257 && (GET_MODE (note) == VOIDmode
1258 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
1259 : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
1261 /* Temporarily replace the set's source with the
1262 contents of the REG_EQUAL note. The insn will
1263 be deleted or recognized by try_combine. */
1264 rtx orig = SET_SRC (set);
1265 SET_SRC (set) = note;
1267 i2mod_old_rhs = copy_rtx (orig);
1268 i2mod_new_rhs = copy_rtx (note);
1269 next = try_combine (insn, i2mod, NULL_RTX,
1270 &new_direct_jump_p);
1274 SET_SRC (set) = orig;
1279 record_dead_and_set_regs (insn);
1287 default_rtl_profile ();
1290 new_direct_jump_p |= purge_all_dead_edges ();
1291 delete_noop_moves ();
1294 free (uid_log_links);
1295 free (uid_insn_cost);
1296 VEC_free (reg_stat_type, heap, reg_stat);
1299 struct undo *undo, *next;
1300 for (undo = undobuf.frees; undo; undo = next)
1308 total_attempts += combine_attempts;
1309 total_merges += combine_merges;
1310 total_extras += combine_extras;
1311 total_successes += combine_successes;
1313 nonzero_sign_valid = 0;
1314 rtl_hooks = general_rtl_hooks;
1316 /* Make recognizer allow volatile MEMs again. */
1319 return new_direct_jump_p;
1322 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1325 init_reg_last (void)
1330 for (i = 0; VEC_iterate (reg_stat_type, reg_stat, i, p); ++i)
1331 memset (p, 0, offsetof (reg_stat_type, sign_bit_copies));
1334 /* Set up any promoted values for incoming argument registers. */
1337 setup_incoming_promotions (rtx first)
1340 bool strictly_local = false;
1342 for (arg = DECL_ARGUMENTS (current_function_decl); arg;
1343 arg = TREE_CHAIN (arg))
1345 rtx x, reg = DECL_INCOMING_RTL (arg);
1347 enum machine_mode mode1, mode2, mode3, mode4;
1349 /* Only continue if the incoming argument is in a register. */
1353 /* Determine, if possible, whether all call sites of the current
1354 function lie within the current compilation unit. (This does
1355 take into account the exporting of a function via taking its
1356 address, and so forth.) */
1357 strictly_local = cgraph_local_info (current_function_decl)->local;
1359 /* The mode and signedness of the argument before any promotions happen
1360 (equal to the mode of the pseudo holding it at that stage). */
1361 mode1 = TYPE_MODE (TREE_TYPE (arg));
1362 uns1 = TYPE_UNSIGNED (TREE_TYPE (arg));
1364 /* The mode and signedness of the argument after any source language and
1365 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1366 mode2 = TYPE_MODE (DECL_ARG_TYPE (arg));
1367 uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg));
1369 /* The mode and signedness of the argument as it is actually passed,
1370 after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */
1371 mode3 = promote_function_mode (DECL_ARG_TYPE (arg), mode2, &uns3,
1372 TREE_TYPE (cfun->decl), 0);
1374 /* The mode of the register in which the argument is being passed. */
1375 mode4 = GET_MODE (reg);
1377 /* Eliminate sign extensions in the callee when:
1378 (a) A mode promotion has occurred; */
1381 /* (b) The mode of the register is the same as the mode of
1382 the argument as it is passed; */
1385 /* (c) There's no language level extension; */
1388 /* (c.1) All callers are from the current compilation unit. If that's
1389 the case we don't have to rely on an ABI, we only have to know
1390 what we're generating right now, and we know that we will do the
1391 mode1 to mode2 promotion with the given sign. */
1392 else if (!strictly_local)
1394 /* (c.2) The combination of the two promotions is useful. This is
1395 true when the signs match, or if the first promotion is unsigned.
1396 In the later case, (sign_extend (zero_extend x)) is the same as
1397 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1403 /* Record that the value was promoted from mode1 to mode3,
1404 so that any sign extension at the head of the current
1405 function may be eliminated. */
1406 x = gen_rtx_CLOBBER (mode1, const0_rtx);
1407 x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x);
1408 record_value_for_reg (reg, first, x);
1412 /* Called via note_stores. If X is a pseudo that is narrower than
1413 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1415 If we are setting only a portion of X and we can't figure out what
1416 portion, assume all bits will be used since we don't know what will
1419 Similarly, set how many bits of X are known to be copies of the sign bit
1420 at all locations in the function. This is the smallest number implied
1424 set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data)
1426 rtx insn = (rtx) data;
1430 && REGNO (x) >= FIRST_PSEUDO_REGISTER
1431 /* If this register is undefined at the start of the file, we can't
1432 say what its contents were. */
1433 && ! REGNO_REG_SET_P
1434 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x))
1435 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
1437 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
1439 if (set == 0 || GET_CODE (set) == CLOBBER)
1441 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1442 rsp->sign_bit_copies = 1;
1446 /* If this register is being initialized using itself, and the
1447 register is uninitialized in this basic block, and there are
1448 no LOG_LINKS which set the register, then part of the
1449 register is uninitialized. In that case we can't assume
1450 anything about the number of nonzero bits.
1452 ??? We could do better if we checked this in
1453 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1454 could avoid making assumptions about the insn which initially
1455 sets the register, while still using the information in other
1456 insns. We would have to be careful to check every insn
1457 involved in the combination. */
1460 && reg_referenced_p (x, PATTERN (insn))
1461 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)),
1466 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
1468 if (dead_or_set_p (XEXP (link, 0), x))
1473 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1474 rsp->sign_bit_copies = 1;
1479 /* If this is a complex assignment, see if we can convert it into a
1480 simple assignment. */
1481 set = expand_field_assignment (set);
1483 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1484 set what we know about X. */
1486 if (SET_DEST (set) == x
1487 || (GET_CODE (SET_DEST (set)) == SUBREG
1488 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
1489 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
1490 && SUBREG_REG (SET_DEST (set)) == x))
1492 rtx src = SET_SRC (set);
1494 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1495 /* If X is narrower than a word and SRC is a non-negative
1496 constant that would appear negative in the mode of X,
1497 sign-extend it for use in reg_stat[].nonzero_bits because some
1498 machines (maybe most) will actually do the sign-extension
1499 and this is the conservative approach.
1501 ??? For 2.5, try to tighten up the MD files in this regard
1502 instead of this kludge. */
1504 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
1505 && CONST_INT_P (src)
1507 && 0 != (INTVAL (src)
1508 & ((HOST_WIDE_INT) 1
1509 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
1510 src = GEN_INT (INTVAL (src)
1511 | ((HOST_WIDE_INT) (-1)
1512 << GET_MODE_BITSIZE (GET_MODE (x))));
1515 /* Don't call nonzero_bits if it cannot change anything. */
1516 if (rsp->nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1517 rsp->nonzero_bits |= nonzero_bits (src, nonzero_bits_mode);
1518 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1519 if (rsp->sign_bit_copies == 0
1520 || rsp->sign_bit_copies > num)
1521 rsp->sign_bit_copies = num;
1525 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1526 rsp->sign_bit_copies = 1;
1531 /* See if INSN can be combined into I3. PRED and SUCC are optionally
1532 insns that were previously combined into I3 or that will be combined
1533 into the merger of INSN and I3.
1535 Return 0 if the combination is not allowed for any reason.
1537 If the combination is allowed, *PDEST will be set to the single
1538 destination of INSN and *PSRC to the single source, and this function
1542 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ,
1543 rtx *pdest, rtx *psrc)
1552 int all_adjacent = (succ ? (next_active_insn (insn) == succ
1553 && next_active_insn (succ) == i3)
1554 : next_active_insn (insn) == i3);
1556 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1557 or a PARALLEL consisting of such a SET and CLOBBERs.
1559 If INSN has CLOBBER parallel parts, ignore them for our processing.
1560 By definition, these happen during the execution of the insn. When it
1561 is merged with another insn, all bets are off. If they are, in fact,
1562 needed and aren't also supplied in I3, they may be added by
1563 recog_for_combine. Otherwise, it won't match.
1565 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1568 Get the source and destination of INSN. If more than one, can't
1571 if (GET_CODE (PATTERN (insn)) == SET)
1572 set = PATTERN (insn);
1573 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1574 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1576 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1578 rtx elt = XVECEXP (PATTERN (insn), 0, i);
1580 switch (GET_CODE (elt))
1582 /* This is important to combine floating point insns
1583 for the SH4 port. */
1585 /* Combining an isolated USE doesn't make sense.
1586 We depend here on combinable_i3pat to reject them. */
1587 /* The code below this loop only verifies that the inputs of
1588 the SET in INSN do not change. We call reg_set_between_p
1589 to verify that the REG in the USE does not change between
1591 If the USE in INSN was for a pseudo register, the matching
1592 insn pattern will likely match any register; combining this
1593 with any other USE would only be safe if we knew that the
1594 used registers have identical values, or if there was
1595 something to tell them apart, e.g. different modes. For
1596 now, we forgo such complicated tests and simply disallow
1597 combining of USES of pseudo registers with any other USE. */
1598 if (REG_P (XEXP (elt, 0))
1599 && GET_CODE (PATTERN (i3)) == PARALLEL)
1601 rtx i3pat = PATTERN (i3);
1602 int i = XVECLEN (i3pat, 0) - 1;
1603 unsigned int regno = REGNO (XEXP (elt, 0));
1607 rtx i3elt = XVECEXP (i3pat, 0, i);
1609 if (GET_CODE (i3elt) == USE
1610 && REG_P (XEXP (i3elt, 0))
1611 && (REGNO (XEXP (i3elt, 0)) == regno
1612 ? reg_set_between_p (XEXP (elt, 0),
1613 PREV_INSN (insn), i3)
1614 : regno >= FIRST_PSEUDO_REGISTER))
1621 /* We can ignore CLOBBERs. */
1626 /* Ignore SETs whose result isn't used but not those that
1627 have side-effects. */
1628 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1629 && insn_nothrow_p (insn)
1630 && !side_effects_p (elt))
1633 /* If we have already found a SET, this is a second one and
1634 so we cannot combine with this insn. */
1642 /* Anything else means we can't combine. */
1648 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1649 so don't do anything with it. */
1650 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1659 set = expand_field_assignment (set);
1660 src = SET_SRC (set), dest = SET_DEST (set);
1662 /* Don't eliminate a store in the stack pointer. */
1663 if (dest == stack_pointer_rtx
1664 /* Don't combine with an insn that sets a register to itself if it has
1665 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1666 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1667 /* Can't merge an ASM_OPERANDS. */
1668 || GET_CODE (src) == ASM_OPERANDS
1669 /* Can't merge a function call. */
1670 || GET_CODE (src) == CALL
1671 /* Don't eliminate a function call argument. */
1673 && (find_reg_fusage (i3, USE, dest)
1675 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1676 && global_regs[REGNO (dest)])))
1677 /* Don't substitute into an incremented register. */
1678 || FIND_REG_INC_NOTE (i3, dest)
1679 || (succ && FIND_REG_INC_NOTE (succ, dest))
1680 /* Don't substitute into a non-local goto, this confuses CFG. */
1681 || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1682 /* Make sure that DEST is not used after SUCC but before I3. */
1683 || (succ && ! all_adjacent
1684 && reg_used_between_p (dest, succ, i3))
1685 /* Make sure that the value that is to be substituted for the register
1686 does not use any registers whose values alter in between. However,
1687 If the insns are adjacent, a use can't cross a set even though we
1688 think it might (this can happen for a sequence of insns each setting
1689 the same destination; last_set of that register might point to
1690 a NOTE). If INSN has a REG_EQUIV note, the register is always
1691 equivalent to the memory so the substitution is valid even if there
1692 are intervening stores. Also, don't move a volatile asm or
1693 UNSPEC_VOLATILE across any other insns. */
1696 || ! find_reg_note (insn, REG_EQUIV, src))
1697 && use_crosses_set_p (src, DF_INSN_LUID (insn)))
1698 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1699 || GET_CODE (src) == UNSPEC_VOLATILE))
1700 /* Don't combine across a CALL_INSN, because that would possibly
1701 change whether the life span of some REGs crosses calls or not,
1702 and it is a pain to update that information.
1703 Exception: if source is a constant, moving it later can't hurt.
1704 Accept that as a special case. */
1705 || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src)))
1708 /* DEST must either be a REG or CC0. */
1711 /* If register alignment is being enforced for multi-word items in all
1712 cases except for parameters, it is possible to have a register copy
1713 insn referencing a hard register that is not allowed to contain the
1714 mode being copied and which would not be valid as an operand of most
1715 insns. Eliminate this problem by not combining with such an insn.
1717 Also, on some machines we don't want to extend the life of a hard
1721 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1722 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1723 /* Don't extend the life of a hard register unless it is
1724 user variable (if we have few registers) or it can't
1725 fit into the desired register (meaning something special
1727 Also avoid substituting a return register into I3, because
1728 reload can't handle a conflict with constraints of other
1730 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1731 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1734 else if (GET_CODE (dest) != CC0)
1738 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1739 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1740 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1742 /* Don't substitute for a register intended as a clobberable
1744 rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1745 if (rtx_equal_p (reg, dest))
1748 /* If the clobber represents an earlyclobber operand, we must not
1749 substitute an expression containing the clobbered register.
1750 As we do not analyze the constraint strings here, we have to
1751 make the conservative assumption. However, if the register is
1752 a fixed hard reg, the clobber cannot represent any operand;
1753 we leave it up to the machine description to either accept or
1754 reject use-and-clobber patterns. */
1756 || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1757 || !fixed_regs[REGNO (reg)])
1758 if (reg_overlap_mentioned_p (reg, src))
1762 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1763 or not), reject, unless nothing volatile comes between it and I3 */
1765 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1767 /* Make sure succ doesn't contain a volatile reference. */
1768 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1771 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1772 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1776 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1777 to be an explicit register variable, and was chosen for a reason. */
1779 if (GET_CODE (src) == ASM_OPERANDS
1780 && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1783 /* If there are any volatile insns between INSN and I3, reject, because
1784 they might affect machine state. */
1786 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1787 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1790 /* If INSN contains an autoincrement or autodecrement, make sure that
1791 register is not used between there and I3, and not already used in
1792 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1793 Also insist that I3 not be a jump; if it were one
1794 and the incremented register were spilled, we would lose. */
1797 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1798 if (REG_NOTE_KIND (link) == REG_INC
1800 || reg_used_between_p (XEXP (link, 0), insn, i3)
1801 || (pred != NULL_RTX
1802 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1803 || (succ != NULL_RTX
1804 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1805 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1810 /* Don't combine an insn that follows a CC0-setting insn.
1811 An insn that uses CC0 must not be separated from the one that sets it.
1812 We do, however, allow I2 to follow a CC0-setting insn if that insn
1813 is passed as I1; in that case it will be deleted also.
1814 We also allow combining in this case if all the insns are adjacent
1815 because that would leave the two CC0 insns adjacent as well.
1816 It would be more logical to test whether CC0 occurs inside I1 or I2,
1817 but that would be much slower, and this ought to be equivalent. */
1819 p = prev_nonnote_insn (insn);
1820 if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
1825 /* If we get here, we have passed all the tests and the combination is
1834 /* LOC is the location within I3 that contains its pattern or the component
1835 of a PARALLEL of the pattern. We validate that it is valid for combining.
1837 One problem is if I3 modifies its output, as opposed to replacing it
1838 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1839 so would produce an insn that is not equivalent to the original insns.
1843 (set (reg:DI 101) (reg:DI 100))
1844 (set (subreg:SI (reg:DI 101) 0) <foo>)
1846 This is NOT equivalent to:
1848 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1849 (set (reg:DI 101) (reg:DI 100))])
1851 Not only does this modify 100 (in which case it might still be valid
1852 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1854 We can also run into a problem if I2 sets a register that I1
1855 uses and I1 gets directly substituted into I3 (not via I2). In that
1856 case, we would be getting the wrong value of I2DEST into I3, so we
1857 must reject the combination. This case occurs when I2 and I1 both
1858 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1859 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1860 of a SET must prevent combination from occurring.
1862 Before doing the above check, we first try to expand a field assignment
1863 into a set of logical operations.
1865 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1866 we place a register that is both set and used within I3. If more than one
1867 such register is detected, we fail.
1869 Return 1 if the combination is valid, zero otherwise. */
1872 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest,
1873 int i1_not_in_src, rtx *pi3dest_killed)
1877 if (GET_CODE (x) == SET)
1880 rtx dest = SET_DEST (set);
1881 rtx src = SET_SRC (set);
1882 rtx inner_dest = dest;
1885 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1886 || GET_CODE (inner_dest) == SUBREG
1887 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1888 inner_dest = XEXP (inner_dest, 0);
1890 /* Check for the case where I3 modifies its output, as discussed
1891 above. We don't want to prevent pseudos from being combined
1892 into the address of a MEM, so only prevent the combination if
1893 i1 or i2 set the same MEM. */
1894 if ((inner_dest != dest &&
1895 (!MEM_P (inner_dest)
1896 || rtx_equal_p (i2dest, inner_dest)
1897 || (i1dest && rtx_equal_p (i1dest, inner_dest)))
1898 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1899 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1901 /* This is the same test done in can_combine_p except we can't test
1902 all_adjacent; we don't have to, since this instruction will stay
1903 in place, thus we are not considering increasing the lifetime of
1906 Also, if this insn sets a function argument, combining it with
1907 something that might need a spill could clobber a previous
1908 function argument; the all_adjacent test in can_combine_p also
1909 checks this; here, we do a more specific test for this case. */
1911 || (REG_P (inner_dest)
1912 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1913 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1914 GET_MODE (inner_dest))))
1915 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1918 /* If DEST is used in I3, it is being killed in this insn, so
1919 record that for later. We have to consider paradoxical
1920 subregs here, since they kill the whole register, but we
1921 ignore partial subregs, STRICT_LOW_PART, etc.
1922 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1923 STACK_POINTER_REGNUM, since these are always considered to be
1924 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1926 if (GET_CODE (subdest) == SUBREG
1927 && (GET_MODE_SIZE (GET_MODE (subdest))
1928 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
1929 subdest = SUBREG_REG (subdest);
1932 && reg_referenced_p (subdest, PATTERN (i3))
1933 && REGNO (subdest) != FRAME_POINTER_REGNUM
1934 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1935 && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
1937 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1938 && (REGNO (subdest) != ARG_POINTER_REGNUM
1939 || ! fixed_regs [REGNO (subdest)])
1941 && REGNO (subdest) != STACK_POINTER_REGNUM)
1943 if (*pi3dest_killed)
1946 *pi3dest_killed = subdest;
1950 else if (GET_CODE (x) == PARALLEL)
1954 for (i = 0; i < XVECLEN (x, 0); i++)
1955 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1956 i1_not_in_src, pi3dest_killed))
1963 /* Return 1 if X is an arithmetic expression that contains a multiplication
1964 and division. We don't count multiplications by powers of two here. */
1967 contains_muldiv (rtx x)
1969 switch (GET_CODE (x))
1971 case MOD: case DIV: case UMOD: case UDIV:
1975 return ! (CONST_INT_P (XEXP (x, 1))
1976 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1979 return contains_muldiv (XEXP (x, 0))
1980 || contains_muldiv (XEXP (x, 1));
1983 return contains_muldiv (XEXP (x, 0));
1989 /* Determine whether INSN can be used in a combination. Return nonzero if
1990 not. This is used in try_combine to detect early some cases where we
1991 can't perform combinations. */
1994 cant_combine_insn_p (rtx insn)
1999 /* If this isn't really an insn, we can't do anything.
2000 This can occur when flow deletes an insn that it has merged into an
2001 auto-increment address. */
2002 if (! INSN_P (insn))
2005 /* Never combine loads and stores involving hard regs that are likely
2006 to be spilled. The register allocator can usually handle such
2007 reg-reg moves by tying. If we allow the combiner to make
2008 substitutions of likely-spilled regs, reload might die.
2009 As an exception, we allow combinations involving fixed regs; these are
2010 not available to the register allocator so there's no risk involved. */
2012 set = single_set (insn);
2015 src = SET_SRC (set);
2016 dest = SET_DEST (set);
2017 if (GET_CODE (src) == SUBREG)
2018 src = SUBREG_REG (src);
2019 if (GET_CODE (dest) == SUBREG)
2020 dest = SUBREG_REG (dest);
2021 if (REG_P (src) && REG_P (dest)
2022 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
2023 && ! fixed_regs[REGNO (src)]
2024 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src))))
2025 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
2026 && ! fixed_regs[REGNO (dest)]
2027 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest))))))
2033 struct likely_spilled_retval_info
2035 unsigned regno, nregs;
2039 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2040 hard registers that are known to be written to / clobbered in full. */
2042 likely_spilled_retval_1 (rtx x, const_rtx set, void *data)
2044 struct likely_spilled_retval_info *const info =
2045 (struct likely_spilled_retval_info *) data;
2046 unsigned regno, nregs;
2049 if (!REG_P (XEXP (set, 0)))
2052 if (regno >= info->regno + info->nregs)
2054 nregs = hard_regno_nregs[regno][GET_MODE (x)];
2055 if (regno + nregs <= info->regno)
2057 new_mask = (2U << (nregs - 1)) - 1;
2058 if (regno < info->regno)
2059 new_mask >>= info->regno - regno;
2061 new_mask <<= regno - info->regno;
2062 info->mask &= ~new_mask;
2065 /* Return nonzero iff part of the return value is live during INSN, and
2066 it is likely spilled. This can happen when more than one insn is needed
2067 to copy the return value, e.g. when we consider to combine into the
2068 second copy insn for a complex value. */
2071 likely_spilled_retval_p (rtx insn)
2073 rtx use = BB_END (this_basic_block);
2075 unsigned regno, nregs;
2076 /* We assume here that no machine mode needs more than
2077 32 hard registers when the value overlaps with a register
2078 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2080 struct likely_spilled_retval_info info;
2082 if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
2084 reg = XEXP (PATTERN (use), 0);
2085 if (!REG_P (reg) || !targetm.calls.function_value_regno_p (REGNO (reg)))
2087 regno = REGNO (reg);
2088 nregs = hard_regno_nregs[regno][GET_MODE (reg)];
2091 mask = (2U << (nregs - 1)) - 1;
2093 /* Disregard parts of the return value that are set later. */
2097 for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
2099 note_stores (PATTERN (p), likely_spilled_retval_1, &info);
2102 /* Check if any of the (probably) live return value registers is
2107 if ((mask & 1 << nregs)
2108 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (regno + nregs)))
2114 /* Adjust INSN after we made a change to its destination.
2116 Changing the destination can invalidate notes that say something about
2117 the results of the insn and a LOG_LINK pointing to the insn. */
2120 adjust_for_new_dest (rtx insn)
2122 /* For notes, be conservative and simply remove them. */
2123 remove_reg_equal_equiv_notes (insn);
2125 /* The new insn will have a destination that was previously the destination
2126 of an insn just above it. Call distribute_links to make a LOG_LINK from
2127 the next use of that destination. */
2128 distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX));
2130 df_insn_rescan (insn);
2133 /* Return TRUE if combine can reuse reg X in mode MODE.
2134 ADDED_SETS is nonzero if the original set is still required. */
2136 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
2144 /* Allow hard registers if the new mode is legal, and occupies no more
2145 registers than the old mode. */
2146 if (regno < FIRST_PSEUDO_REGISTER)
2147 return (HARD_REGNO_MODE_OK (regno, mode)
2148 && (hard_regno_nregs[regno][GET_MODE (x)]
2149 >= hard_regno_nregs[regno][mode]));
2151 /* Or a pseudo that is only used once. */
2152 return (REG_N_SETS (regno) == 1 && !added_sets
2153 && !REG_USERVAR_P (x));
2157 /* Check whether X, the destination of a set, refers to part of
2158 the register specified by REG. */
2161 reg_subword_p (rtx x, rtx reg)
2163 /* Check that reg is an integer mode register. */
2164 if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
2167 if (GET_CODE (x) == STRICT_LOW_PART
2168 || GET_CODE (x) == ZERO_EXTRACT)
2171 return GET_CODE (x) == SUBREG
2172 && SUBREG_REG (x) == reg
2173 && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
2177 /* Replace auto-increment addressing modes with explicit operations to
2178 access the same addresses without modifying the corresponding
2179 registers. If AFTER holds, SRC is meant to be reused after the
2180 side effect, otherwise it is to be reused before that. */
2183 cleanup_auto_inc_dec (rtx src, bool after, enum machine_mode mem_mode)
2186 const RTX_CODE code = GET_CODE (x);
2202 /* SCRATCH must be shared because they represent distinct values. */
2205 if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
2210 if (shared_const_p (x))
2215 mem_mode = GET_MODE (x);
2222 gcc_assert (mem_mode != VOIDmode && mem_mode != BLKmode);
2223 if (after == (code == PRE_INC || code == PRE_DEC))
2224 x = cleanup_auto_inc_dec (XEXP (x, 0), after, mem_mode);
2226 x = gen_rtx_PLUS (GET_MODE (x),
2227 cleanup_auto_inc_dec (XEXP (x, 0), after, mem_mode),
2228 GEN_INT ((code == PRE_INC || code == POST_INC)
2229 ? GET_MODE_SIZE (mem_mode)
2230 : -GET_MODE_SIZE (mem_mode)));
2235 if (after == (code == PRE_MODIFY))
2239 return cleanup_auto_inc_dec (x, after, mem_mode);
2245 /* Copy the various flags, fields, and other information. We assume
2246 that all fields need copying, and then clear the fields that should
2247 not be copied. That is the sensible default behavior, and forces
2248 us to explicitly document why we are *not* copying a flag. */
2249 x = shallow_copy_rtx (x);
2251 /* We do not copy the USED flag, which is used as a mark bit during
2252 walks over the RTL. */
2253 RTX_FLAG (x, used) = 0;
2255 /* We do not copy FRAME_RELATED for INSNs. */
2257 RTX_FLAG (x, frame_related) = 0;
2259 fmt = GET_RTX_FORMAT (code);
2260 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2262 XEXP (x, i) = cleanup_auto_inc_dec (XEXP (x, i), after, mem_mode);
2263 else if (fmt[i] == 'E' || fmt[i] == 'V')
2266 XVEC (x, i) = rtvec_alloc (XVECLEN (x, i));
2267 for (j = 0; j < XVECLEN (x, i); j++)
2269 = cleanup_auto_inc_dec (XVECEXP (src, i, j), after, mem_mode);
2275 /* Auxiliary data structure for propagate_for_debug_stmt. */
2277 struct rtx_subst_pair
2284 /* DATA points to an rtx_subst_pair. Return the value that should be
2288 propagate_for_debug_subst (rtx from, const_rtx old_rtx, void *data)
2290 struct rtx_subst_pair *pair = (struct rtx_subst_pair *)data;
2292 if (!rtx_equal_p (from, old_rtx))
2294 if (!pair->adjusted)
2296 pair->adjusted = true;
2297 pair->to = cleanup_auto_inc_dec (pair->to, pair->after, VOIDmode);
2300 return copy_rtx (pair->to);
2304 /* Replace occurrences of DEST with SRC in DEBUG_INSNs between INSN
2305 and LAST. If MOVE holds, debug insns must also be moved past
2309 propagate_for_debug (rtx insn, rtx last, rtx dest, rtx src, bool move)
2311 rtx next, move_pos = move ? last : NULL_RTX, loc;
2315 struct rtx_subst_pair p;
2322 next = NEXT_INSN (insn);
2323 while (next != last)
2326 next = NEXT_INSN (insn);
2327 if (DEBUG_INSN_P (insn))
2331 src = make_compound_operation (src, SET);
2335 loc = simplify_replace_fn_rtx (INSN_VAR_LOCATION_LOC (insn),
2336 dest, propagate_for_debug_subst, &p);
2338 loc = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (insn), dest, src);
2340 if (loc == INSN_VAR_LOCATION_LOC (insn))
2342 INSN_VAR_LOCATION_LOC (insn) = loc;
2346 PREV_INSN (insn) = NEXT_INSN (insn) = NULL_RTX;
2347 move_pos = emit_debug_insn_after (insn, move_pos);
2350 df_insn_rescan (insn);
2355 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2356 Note that the INSN should be deleted *after* removing dead edges, so
2357 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2358 but not for a (set (pc) (label_ref FOO)). */
2361 update_cfg_for_uncondjump (rtx insn)
2363 basic_block bb = BLOCK_FOR_INSN (insn);
2364 bool at_end = (BB_END (bb) == insn);
2367 purge_dead_edges (bb);
2370 if (at_end && EDGE_COUNT (bb->succs) == 1)
2371 single_succ_edge (bb)->flags |= EDGE_FALLTHRU;
2375 /* Try to combine the insns I1 and I2 into I3.
2376 Here I1 and I2 appear earlier than I3.
2377 I1 can be zero; then we combine just I2 into I3.
2379 If we are combining three insns and the resulting insn is not recognized,
2380 try splitting it into two insns. If that happens, I2 and I3 are retained
2381 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
2384 Return 0 if the combination does not work. Then nothing is changed.
2385 If we did the combination, return the insn at which combine should
2388 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2389 new direct jump instruction. */
2392 try_combine (rtx i3, rtx i2, rtx i1, int *new_direct_jump_p)
2394 /* New patterns for I3 and I2, respectively. */
2395 rtx newpat, newi2pat = 0;
2396 rtvec newpat_vec_with_clobbers = 0;
2397 int substed_i2 = 0, substed_i1 = 0;
2398 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
2399 int added_sets_1, added_sets_2;
2400 /* Total number of SETs to put into I3. */
2402 /* Nonzero if I2's body now appears in I3. */
2404 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2405 int insn_code_number, i2_code_number = 0, other_code_number = 0;
2406 /* Contains I3 if the destination of I3 is used in its source, which means
2407 that the old life of I3 is being killed. If that usage is placed into
2408 I2 and not in I3, a REG_DEAD note must be made. */
2409 rtx i3dest_killed = 0;
2410 /* SET_DEST and SET_SRC of I2 and I1. */
2411 rtx i2dest = 0, i2src = 0, i1dest = 0, i1src = 0;
2412 /* Set if I2DEST was reused as a scratch register. */
2413 bool i2scratch = false;
2414 /* PATTERN (I1) and PATTERN (I2), or a copy of it in certain cases. */
2415 rtx i1pat = 0, i2pat = 0;
2416 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2417 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
2418 int i2dest_killed = 0, i1dest_killed = 0;
2419 int i1_feeds_i3 = 0;
2420 /* Notes that must be added to REG_NOTES in I3 and I2. */
2421 rtx new_i3_notes, new_i2_notes;
2422 /* Notes that we substituted I3 into I2 instead of the normal case. */
2423 int i3_subst_into_i2 = 0;
2424 /* Notes that I1, I2 or I3 is a MULT operation. */
2427 int changed_i3_dest = 0;
2433 rtx new_other_notes;
2436 /* Exit early if one of the insns involved can't be used for
2438 if (cant_combine_insn_p (i3)
2439 || cant_combine_insn_p (i2)
2440 || (i1 && cant_combine_insn_p (i1))
2441 || likely_spilled_retval_p (i3))
2445 undobuf.other_insn = 0;
2447 /* Reset the hard register usage information. */
2448 CLEAR_HARD_REG_SET (newpat_used_regs);
2450 if (dump_file && (dump_flags & TDF_DETAILS))
2453 fprintf (dump_file, "\nTrying %d, %d -> %d:\n",
2454 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2456 fprintf (dump_file, "\nTrying %d -> %d:\n",
2457 INSN_UID (i2), INSN_UID (i3));
2460 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
2461 code below, set I1 to be the earlier of the two insns. */
2462 if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2))
2463 temp = i1, i1 = i2, i2 = temp;
2465 added_links_insn = 0;
2467 /* First check for one important special-case that the code below will
2468 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2469 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2470 we may be able to replace that destination with the destination of I3.
2471 This occurs in the common code where we compute both a quotient and
2472 remainder into a structure, in which case we want to do the computation
2473 directly into the structure to avoid register-register copies.
2475 Note that this case handles both multiple sets in I2 and also
2476 cases where I2 has a number of CLOBBER or PARALLELs.
2478 We make very conservative checks below and only try to handle the
2479 most common cases of this. For example, we only handle the case
2480 where I2 and I3 are adjacent to avoid making difficult register
2483 if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
2484 && REG_P (SET_SRC (PATTERN (i3)))
2485 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
2486 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
2487 && GET_CODE (PATTERN (i2)) == PARALLEL
2488 && ! side_effects_p (SET_DEST (PATTERN (i3)))
2489 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2490 below would need to check what is inside (and reg_overlap_mentioned_p
2491 doesn't support those codes anyway). Don't allow those destinations;
2492 the resulting insn isn't likely to be recognized anyway. */
2493 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
2494 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
2495 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
2496 SET_DEST (PATTERN (i3)))
2497 && next_active_insn (i2) == i3)
2499 rtx p2 = PATTERN (i2);
2501 /* Make sure that the destination of I3,
2502 which we are going to substitute into one output of I2,
2503 is not used within another output of I2. We must avoid making this:
2504 (parallel [(set (mem (reg 69)) ...)
2505 (set (reg 69) ...)])
2506 which is not well-defined as to order of actions.
2507 (Besides, reload can't handle output reloads for this.)
2509 The problem can also happen if the dest of I3 is a memory ref,
2510 if another dest in I2 is an indirect memory ref. */
2511 for (i = 0; i < XVECLEN (p2, 0); i++)
2512 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2513 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2514 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
2515 SET_DEST (XVECEXP (p2, 0, i))))
2518 if (i == XVECLEN (p2, 0))
2519 for (i = 0; i < XVECLEN (p2, 0); i++)
2520 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2521 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2522 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
2527 subst_low_luid = DF_INSN_LUID (i2);
2529 added_sets_2 = added_sets_1 = 0;
2530 i2src = SET_DEST (PATTERN (i3));
2531 i2dest = SET_SRC (PATTERN (i3));
2532 i2dest_killed = dead_or_set_p (i2, i2dest);
2534 /* Replace the dest in I2 with our dest and make the resulting
2535 insn the new pattern for I3. Then skip to where we
2536 validate the pattern. Everything was set up above. */
2537 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
2538 SET_DEST (PATTERN (i3)));
2541 i3_subst_into_i2 = 1;
2542 goto validate_replacement;
2546 /* If I2 is setting a pseudo to a constant and I3 is setting some
2547 sub-part of it to another constant, merge them by making a new
2550 && (temp = single_set (i2)) != 0
2551 && (CONST_INT_P (SET_SRC (temp))
2552 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
2553 && GET_CODE (PATTERN (i3)) == SET
2554 && (CONST_INT_P (SET_SRC (PATTERN (i3)))
2555 || GET_CODE (SET_SRC (PATTERN (i3))) == CONST_DOUBLE)
2556 && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
2558 rtx dest = SET_DEST (PATTERN (i3));
2562 if (GET_CODE (dest) == ZERO_EXTRACT)
2564 if (CONST_INT_P (XEXP (dest, 1))
2565 && CONST_INT_P (XEXP (dest, 2)))
2567 width = INTVAL (XEXP (dest, 1));
2568 offset = INTVAL (XEXP (dest, 2));
2569 dest = XEXP (dest, 0);
2570 if (BITS_BIG_ENDIAN)
2571 offset = GET_MODE_BITSIZE (GET_MODE (dest)) - width - offset;
2576 if (GET_CODE (dest) == STRICT_LOW_PART)
2577 dest = XEXP (dest, 0);
2578 width = GET_MODE_BITSIZE (GET_MODE (dest));
2584 /* If this is the low part, we're done. */
2585 if (subreg_lowpart_p (dest))
2587 /* Handle the case where inner is twice the size of outer. */
2588 else if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2589 == 2 * GET_MODE_BITSIZE (GET_MODE (dest)))
2590 offset += GET_MODE_BITSIZE (GET_MODE (dest));
2591 /* Otherwise give up for now. */
2597 && (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2598 <= HOST_BITS_PER_WIDE_INT * 2))
2600 HOST_WIDE_INT mhi, ohi, ihi;
2601 HOST_WIDE_INT mlo, olo, ilo;
2602 rtx inner = SET_SRC (PATTERN (i3));
2603 rtx outer = SET_SRC (temp);
2605 if (CONST_INT_P (outer))
2607 olo = INTVAL (outer);
2608 ohi = olo < 0 ? -1 : 0;
2612 olo = CONST_DOUBLE_LOW (outer);
2613 ohi = CONST_DOUBLE_HIGH (outer);
2616 if (CONST_INT_P (inner))
2618 ilo = INTVAL (inner);
2619 ihi = ilo < 0 ? -1 : 0;
2623 ilo = CONST_DOUBLE_LOW (inner);
2624 ihi = CONST_DOUBLE_HIGH (inner);
2627 if (width < HOST_BITS_PER_WIDE_INT)
2629 mlo = ((unsigned HOST_WIDE_INT) 1 << width) - 1;
2632 else if (width < HOST_BITS_PER_WIDE_INT * 2)
2634 mhi = ((unsigned HOST_WIDE_INT) 1
2635 << (width - HOST_BITS_PER_WIDE_INT)) - 1;
2647 if (offset >= HOST_BITS_PER_WIDE_INT)
2649 mhi = mlo << (offset - HOST_BITS_PER_WIDE_INT);
2651 ihi = ilo << (offset - HOST_BITS_PER_WIDE_INT);
2654 else if (offset > 0)
2656 mhi = (mhi << offset) | ((unsigned HOST_WIDE_INT) mlo
2657 >> (HOST_BITS_PER_WIDE_INT - offset));
2658 mlo = mlo << offset;
2659 ihi = (ihi << offset) | ((unsigned HOST_WIDE_INT) ilo
2660 >> (HOST_BITS_PER_WIDE_INT - offset));
2661 ilo = ilo << offset;
2664 olo = (olo & ~mlo) | ilo;
2665 ohi = (ohi & ~mhi) | ihi;
2669 subst_low_luid = DF_INSN_LUID (i2);
2670 added_sets_2 = added_sets_1 = 0;
2671 i2dest = SET_DEST (temp);
2672 i2dest_killed = dead_or_set_p (i2, i2dest);
2674 /* Replace the source in I2 with the new constant and make the
2675 resulting insn the new pattern for I3. Then skip to where we
2676 validate the pattern. Everything was set up above. */
2677 SUBST (SET_SRC (temp),
2678 immed_double_const (olo, ohi, GET_MODE (SET_DEST (temp))));
2680 newpat = PATTERN (i2);
2682 /* The dest of I3 has been replaced with the dest of I2. */
2683 changed_i3_dest = 1;
2684 goto validate_replacement;
2689 /* If we have no I1 and I2 looks like:
2690 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2692 make up a dummy I1 that is
2695 (set (reg:CC X) (compare:CC Y (const_int 0)))
2697 (We can ignore any trailing CLOBBERs.)
2699 This undoes a previous combination and allows us to match a branch-and-
2702 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2703 && XVECLEN (PATTERN (i2), 0) >= 2
2704 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2705 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2707 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2708 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2709 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2710 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2711 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2712 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2714 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2715 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2720 /* We make I1 with the same INSN_UID as I2. This gives it
2721 the same DF_INSN_LUID for value tracking. Our fake I1 will
2722 never appear in the insn stream so giving it the same INSN_UID
2723 as I2 will not cause a problem. */
2725 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
2726 BLOCK_FOR_INSN (i2), INSN_LOCATOR (i2),
2727 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX);
2729 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2730 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2731 SET_DEST (PATTERN (i1)));
2736 /* Verify that I2 and I1 are valid for combining. */
2737 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
2738 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
2744 /* Record whether I2DEST is used in I2SRC and similarly for the other
2745 cases. Knowing this will help in register status updating below. */
2746 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2747 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2748 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2749 i2dest_killed = dead_or_set_p (i2, i2dest);
2750 i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2752 /* See if I1 directly feeds into I3. It does if I1DEST is not used
2754 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
2756 /* Ensure that I3's pattern can be the destination of combines. */
2757 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
2758 i1 && i2dest_in_i1src && i1_feeds_i3,
2765 /* See if any of the insns is a MULT operation. Unless one is, we will
2766 reject a combination that is, since it must be slower. Be conservative
2768 if (GET_CODE (i2src) == MULT
2769 || (i1 != 0 && GET_CODE (i1src) == MULT)
2770 || (GET_CODE (PATTERN (i3)) == SET
2771 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2774 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2775 We used to do this EXCEPT in one case: I3 has a post-inc in an
2776 output operand. However, that exception can give rise to insns like
2778 which is a famous insn on the PDP-11 where the value of r3 used as the
2779 source was model-dependent. Avoid this sort of thing. */
2782 if (!(GET_CODE (PATTERN (i3)) == SET
2783 && REG_P (SET_SRC (PATTERN (i3)))
2784 && MEM_P (SET_DEST (PATTERN (i3)))
2785 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2786 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2787 /* It's not the exception. */
2790 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2791 if (REG_NOTE_KIND (link) == REG_INC
2792 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2794 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2801 /* See if the SETs in I1 or I2 need to be kept around in the merged
2802 instruction: whenever the value set there is still needed past I3.
2803 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2805 For the SET in I1, we have two cases: If I1 and I2 independently
2806 feed into I3, the set in I1 needs to be kept around if I1DEST dies
2807 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2808 in I1 needs to be kept around unless I1DEST dies or is set in either
2809 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
2810 I1DEST. If so, we know I1 feeds into I2. */
2812 added_sets_2 = ! dead_or_set_p (i3, i2dest);
2815 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
2816 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
2818 /* If the set in I2 needs to be kept around, we must make a copy of
2819 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2820 PATTERN (I2), we are only substituting for the original I1DEST, not into
2821 an already-substituted copy. This also prevents making self-referential
2822 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2827 if (GET_CODE (PATTERN (i2)) == PARALLEL)
2828 i2pat = gen_rtx_SET (VOIDmode, i2dest, copy_rtx (i2src));
2830 i2pat = copy_rtx (PATTERN (i2));
2835 if (GET_CODE (PATTERN (i1)) == PARALLEL)
2836 i1pat = gen_rtx_SET (VOIDmode, i1dest, copy_rtx (i1src));
2838 i1pat = copy_rtx (PATTERN (i1));
2843 /* Substitute in the latest insn for the regs set by the earlier ones. */
2845 maxreg = max_reg_num ();
2850 /* Many machines that don't use CC0 have insns that can both perform an
2851 arithmetic operation and set the condition code. These operations will
2852 be represented as a PARALLEL with the first element of the vector
2853 being a COMPARE of an arithmetic operation with the constant zero.
2854 The second element of the vector will set some pseudo to the result
2855 of the same arithmetic operation. If we simplify the COMPARE, we won't
2856 match such a pattern and so will generate an extra insn. Here we test
2857 for this case, where both the comparison and the operation result are
2858 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2859 I2SRC. Later we will make the PARALLEL that contains I2. */
2861 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
2862 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
2863 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
2864 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2866 #ifdef SELECT_CC_MODE
2868 enum machine_mode compare_mode;
2871 newpat = PATTERN (i3);
2872 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
2876 #ifdef SELECT_CC_MODE
2877 /* See if a COMPARE with the operand we substituted in should be done
2878 with the mode that is currently being used. If not, do the same
2879 processing we do in `subst' for a SET; namely, if the destination
2880 is used only once, try to replace it with a register of the proper
2881 mode and also replace the COMPARE. */
2882 if (undobuf.other_insn == 0
2883 && (cc_use = find_single_use (SET_DEST (newpat), i3,
2884 &undobuf.other_insn))
2885 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
2887 != GET_MODE (SET_DEST (newpat))))
2889 if (can_change_dest_mode(SET_DEST (newpat), added_sets_2,
2892 unsigned int regno = REGNO (SET_DEST (newpat));
2895 if (regno < FIRST_PSEUDO_REGISTER)
2896 new_dest = gen_rtx_REG (compare_mode, regno);
2899 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
2900 new_dest = regno_reg_rtx[regno];
2903 SUBST (SET_DEST (newpat), new_dest);
2904 SUBST (XEXP (*cc_use, 0), new_dest);
2905 SUBST (SET_SRC (newpat),
2906 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
2909 undobuf.other_insn = 0;
2916 /* It is possible that the source of I2 or I1 may be performing
2917 an unneeded operation, such as a ZERO_EXTEND of something
2918 that is known to have the high part zero. Handle that case
2919 by letting subst look at the innermost one of them.
2921 Another way to do this would be to have a function that tries
2922 to simplify a single insn instead of merging two or more
2923 insns. We don't do this because of the potential of infinite
2924 loops and because of the potential extra memory required.
2925 However, doing it the way we are is a bit of a kludge and
2926 doesn't catch all cases.
2928 But only do this if -fexpensive-optimizations since it slows
2929 things down and doesn't usually win.
2931 This is not done in the COMPARE case above because the
2932 unmodified I2PAT is used in the PARALLEL and so a pattern
2933 with a modified I2SRC would not match. */
2935 if (flag_expensive_optimizations)
2937 /* Pass pc_rtx so no substitutions are done, just
2941 subst_low_luid = DF_INSN_LUID (i1);
2942 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
2946 subst_low_luid = DF_INSN_LUID (i2);
2947 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
2951 n_occurrences = 0; /* `subst' counts here */
2953 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2954 need to make a unique copy of I2SRC each time we substitute it
2955 to avoid self-referential rtl. */
2957 subst_low_luid = DF_INSN_LUID (i2);
2958 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
2959 ! i1_feeds_i3 && i1dest_in_i1src);
2962 /* Record whether i2's body now appears within i3's body. */
2963 i2_is_used = n_occurrences;
2966 /* If we already got a failure, don't try to do more. Otherwise,
2967 try to substitute in I1 if we have it. */
2969 if (i1 && GET_CODE (newpat) != CLOBBER)
2971 /* Check that an autoincrement side-effect on I1 has not been lost.
2972 This happens if I1DEST is mentioned in I2 and dies there, and
2973 has disappeared from the new pattern. */
2974 if ((FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2976 && dead_or_set_p (i2, i1dest)
2977 && !reg_overlap_mentioned_p (i1dest, newpat))
2978 /* Before we can do this substitution, we must redo the test done
2979 above (see detailed comments there) that ensures that I1DEST
2980 isn't mentioned in any SETs in NEWPAT that are field assignments. */
2981 || !combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX, 0, 0))
2988 subst_low_luid = DF_INSN_LUID (i1);
2989 newpat = subst (newpat, i1dest, i1src, 0, 0);
2993 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2994 to count all the ways that I2SRC and I1SRC can be used. */
2995 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
2996 && i2_is_used + added_sets_2 > 1)
2997 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2998 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
3000 /* Fail if we tried to make a new register. */
3001 || max_reg_num () != maxreg
3002 /* Fail if we couldn't do something and have a CLOBBER. */
3003 || GET_CODE (newpat) == CLOBBER
3004 /* Fail if this new pattern is a MULT and we didn't have one before
3005 at the outer level. */
3006 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
3013 /* If the actions of the earlier insns must be kept
3014 in addition to substituting them into the latest one,
3015 we must make a new PARALLEL for the latest insn
3016 to hold additional the SETs. */
3018 if (added_sets_1 || added_sets_2)
3022 if (GET_CODE (newpat) == PARALLEL)
3024 rtvec old = XVEC (newpat, 0);
3025 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
3026 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3027 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
3028 sizeof (old->elem[0]) * old->num_elem);
3033 total_sets = 1 + added_sets_1 + added_sets_2;
3034 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3035 XVECEXP (newpat, 0, 0) = old;
3039 XVECEXP (newpat, 0, --total_sets) = i1pat;
3043 /* If there is no I1, use I2's body as is. We used to also not do
3044 the subst call below if I2 was substituted into I3,
3045 but that could lose a simplification. */
3047 XVECEXP (newpat, 0, --total_sets) = i2pat;
3049 /* See comment where i2pat is assigned. */
3050 XVECEXP (newpat, 0, --total_sets)
3051 = subst (i2pat, i1dest, i1src, 0, 0);
3055 validate_replacement:
3057 /* Note which hard regs this insn has as inputs. */
3058 mark_used_regs_combine (newpat);
3060 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3061 consider splitting this pattern, we might need these clobbers. */
3062 if (i1 && GET_CODE (newpat) == PARALLEL
3063 && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
3065 int len = XVECLEN (newpat, 0);
3067 newpat_vec_with_clobbers = rtvec_alloc (len);
3068 for (i = 0; i < len; i++)
3069 RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
3072 /* Is the result of combination a valid instruction? */
3073 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3075 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
3076 the second SET's destination is a register that is unused and isn't
3077 marked as an instruction that might trap in an EH region. In that case,
3078 we just need the first SET. This can occur when simplifying a divmod
3079 insn. We *must* test for this case here because the code below that
3080 splits two independent SETs doesn't handle this case correctly when it
3081 updates the register status.
3083 It's pointless doing this if we originally had two sets, one from
3084 i3, and one from i2. Combining then splitting the parallel results
3085 in the original i2 again plus an invalid insn (which we delete).
3086 The net effect is only to move instructions around, which makes
3087 debug info less accurate.
3089 Also check the case where the first SET's destination is unused.
3090 That would not cause incorrect code, but does cause an unneeded
3093 if (insn_code_number < 0
3094 && !(added_sets_2 && i1 == 0)
3095 && GET_CODE (newpat) == PARALLEL
3096 && XVECLEN (newpat, 0) == 2
3097 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3098 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3099 && asm_noperands (newpat) < 0)
3101 rtx set0 = XVECEXP (newpat, 0, 0);
3102 rtx set1 = XVECEXP (newpat, 0, 1);
3104 if (((REG_P (SET_DEST (set1))
3105 && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
3106 || (GET_CODE (SET_DEST (set1)) == SUBREG
3107 && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
3108 && insn_nothrow_p (i3)
3109 && !side_effects_p (SET_SRC (set1)))
3112 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3115 else if (((REG_P (SET_DEST (set0))
3116 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
3117 || (GET_CODE (SET_DEST (set0)) == SUBREG
3118 && find_reg_note (i3, REG_UNUSED,
3119 SUBREG_REG (SET_DEST (set0)))))
3120 && insn_nothrow_p (i3)
3121 && !side_effects_p (SET_SRC (set0)))
3124 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3126 if (insn_code_number >= 0)
3127 changed_i3_dest = 1;
3131 /* If we were combining three insns and the result is a simple SET
3132 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3133 insns. There are two ways to do this. It can be split using a
3134 machine-specific method (like when you have an addition of a large
3135 constant) or by combine in the function find_split_point. */
3137 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
3138 && asm_noperands (newpat) < 0)
3140 rtx parallel, m_split, *split;
3142 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3143 use I2DEST as a scratch register will help. In the latter case,
3144 convert I2DEST to the mode of the source of NEWPAT if we can. */
3146 m_split = combine_split_insns (newpat, i3);
3148 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3149 inputs of NEWPAT. */
3151 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3152 possible to try that as a scratch reg. This would require adding
3153 more code to make it work though. */
3155 if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
3157 enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
3159 /* First try to split using the original register as a
3160 scratch register. */
3161 parallel = gen_rtx_PARALLEL (VOIDmode,
3162 gen_rtvec (2, newpat,
3163 gen_rtx_CLOBBER (VOIDmode,
3165 m_split = combine_split_insns (parallel, i3);
3167 /* If that didn't work, try changing the mode of I2DEST if
3170 && new_mode != GET_MODE (i2dest)
3171 && new_mode != VOIDmode
3172 && can_change_dest_mode (i2dest, added_sets_2, new_mode))
3174 enum machine_mode old_mode = GET_MODE (i2dest);
3177 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3178 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
3181 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
3182 ni2dest = regno_reg_rtx[REGNO (i2dest)];
3185 parallel = (gen_rtx_PARALLEL
3187 gen_rtvec (2, newpat,
3188 gen_rtx_CLOBBER (VOIDmode,
3190 m_split = combine_split_insns (parallel, i3);
3193 && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
3197 adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode);
3198 buf = undobuf.undos;
3199 undobuf.undos = buf->next;
3200 buf->next = undobuf.frees;
3201 undobuf.frees = buf;
3205 i2scratch = m_split != 0;
3208 /* If recog_for_combine has discarded clobbers, try to use them
3209 again for the split. */
3210 if (m_split == 0 && newpat_vec_with_clobbers)
3212 parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers);
3213 m_split = combine_split_insns (parallel, i3);
3216 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
3218 m_split = PATTERN (m_split);
3219 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
3220 if (insn_code_number >= 0)
3223 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
3224 && (next_real_insn (i2) == i3
3225 || ! use_crosses_set_p (PATTERN (m_split), DF_INSN_LUID (i2))))
3228 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
3229 newi2pat = PATTERN (m_split);
3231 i3set = single_set (NEXT_INSN (m_split));
3232 i2set = single_set (m_split);
3234 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3236 /* If I2 or I3 has multiple SETs, we won't know how to track
3237 register status, so don't use these insns. If I2's destination
3238 is used between I2 and I3, we also can't use these insns. */
3240 if (i2_code_number >= 0 && i2set && i3set
3241 && (next_real_insn (i2) == i3
3242 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
3243 insn_code_number = recog_for_combine (&newi3pat, i3,
3245 if (insn_code_number >= 0)
3248 /* It is possible that both insns now set the destination of I3.
3249 If so, we must show an extra use of it. */
3251 if (insn_code_number >= 0)
3253 rtx new_i3_dest = SET_DEST (i3set);
3254 rtx new_i2_dest = SET_DEST (i2set);
3256 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
3257 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
3258 || GET_CODE (new_i3_dest) == SUBREG)
3259 new_i3_dest = XEXP (new_i3_dest, 0);
3261 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
3262 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
3263 || GET_CODE (new_i2_dest) == SUBREG)
3264 new_i2_dest = XEXP (new_i2_dest, 0);
3266 if (REG_P (new_i3_dest)
3267 && REG_P (new_i2_dest)
3268 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
3269 INC_REG_N_SETS (REGNO (new_i2_dest), 1);
3273 /* If we can split it and use I2DEST, go ahead and see if that
3274 helps things be recognized. Verify that none of the registers
3275 are set between I2 and I3. */
3276 if (insn_code_number < 0
3277 && (split = find_split_point (&newpat, i3, false)) != 0
3281 /* We need I2DEST in the proper mode. If it is a hard register
3282 or the only use of a pseudo, we can change its mode.
3283 Make sure we don't change a hard register to have a mode that
3284 isn't valid for it, or change the number of registers. */
3285 && (GET_MODE (*split) == GET_MODE (i2dest)
3286 || GET_MODE (*split) == VOIDmode
3287 || can_change_dest_mode (i2dest, added_sets_2,
3289 && (next_real_insn (i2) == i3
3290 || ! use_crosses_set_p (*split, DF_INSN_LUID (i2)))
3291 /* We can't overwrite I2DEST if its value is still used by
3293 && ! reg_referenced_p (i2dest, newpat))
3295 rtx newdest = i2dest;
3296 enum rtx_code split_code = GET_CODE (*split);
3297 enum machine_mode split_mode = GET_MODE (*split);
3298 bool subst_done = false;
3299 newi2pat = NULL_RTX;
3303 /* *SPLIT may be part of I2SRC, so make sure we have the
3304 original expression around for later debug processing.
3305 We should not need I2SRC any more in other cases. */
3306 if (MAY_HAVE_DEBUG_INSNS)
3307 i2src = copy_rtx (i2src);
3311 /* Get NEWDEST as a register in the proper mode. We have already
3312 validated that we can do this. */
3313 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
3315 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3316 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
3319 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
3320 newdest = regno_reg_rtx[REGNO (i2dest)];
3324 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3325 an ASHIFT. This can occur if it was inside a PLUS and hence
3326 appeared to be a memory address. This is a kludge. */
3327 if (split_code == MULT
3328 && CONST_INT_P (XEXP (*split, 1))
3329 && INTVAL (XEXP (*split, 1)) > 0
3330 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
3332 SUBST (*split, gen_rtx_ASHIFT (split_mode,
3333 XEXP (*split, 0), GEN_INT (i)));
3334 /* Update split_code because we may not have a multiply
3336 split_code = GET_CODE (*split);
3339 #ifdef INSN_SCHEDULING
3340 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3341 be written as a ZERO_EXTEND. */
3342 if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
3344 #ifdef LOAD_EXTEND_OP
3345 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3346 what it really is. */
3347 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
3349 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
3350 SUBREG_REG (*split)));
3353 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
3354 SUBREG_REG (*split)));
3358 /* Attempt to split binary operators using arithmetic identities. */
3359 if (BINARY_P (SET_SRC (newpat))
3360 && split_mode == GET_MODE (SET_SRC (newpat))
3361 && ! side_effects_p (SET_SRC (newpat)))
3363 rtx setsrc = SET_SRC (newpat);
3364 enum machine_mode mode = GET_MODE (setsrc);
3365 enum rtx_code code = GET_CODE (setsrc);
3366 rtx src_op0 = XEXP (setsrc, 0);
3367 rtx src_op1 = XEXP (setsrc, 1);
3369 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3370 if (rtx_equal_p (src_op0, src_op1))
3372 newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
3373 SUBST (XEXP (setsrc, 0), newdest);
3374 SUBST (XEXP (setsrc, 1), newdest);
3377 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3378 else if ((code == PLUS || code == MULT)
3379 && GET_CODE (src_op0) == code
3380 && GET_CODE (XEXP (src_op0, 0)) == code
3381 && (INTEGRAL_MODE_P (mode)
3382 || (FLOAT_MODE_P (mode)
3383 && flag_unsafe_math_optimizations)))
3385 rtx p = XEXP (XEXP (src_op0, 0), 0);
3386 rtx q = XEXP (XEXP (src_op0, 0), 1);
3387 rtx r = XEXP (src_op0, 1);
3390 /* Split both "((X op Y) op X) op Y" and
3391 "((X op Y) op Y) op X" as "T op T" where T is
3393 if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
3394 || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
3396 newi2pat = gen_rtx_SET (VOIDmode, newdest,
3398 SUBST (XEXP (setsrc, 0), newdest);
3399 SUBST (XEXP (setsrc, 1), newdest);
3402 /* Split "((X op X) op Y) op Y)" as "T op T" where
3404 else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
3406 rtx tmp = simplify_gen_binary (code, mode, p, r);
3407 newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
3408 SUBST (XEXP (setsrc, 0), newdest);
3409 SUBST (XEXP (setsrc, 1), newdest);
3417 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
3418 SUBST (*split, newdest);
3421 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3423 /* recog_for_combine might have added CLOBBERs to newi2pat.
3424 Make sure NEWPAT does not depend on the clobbered regs. */
3425 if (GET_CODE (newi2pat) == PARALLEL)
3426 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3427 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3429 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3430 if (reg_overlap_mentioned_p (reg, newpat))
3437 /* If the split point was a MULT and we didn't have one before,
3438 don't use one now. */
3439 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
3440 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3444 /* Check for a case where we loaded from memory in a narrow mode and
3445 then sign extended it, but we need both registers. In that case,
3446 we have a PARALLEL with both loads from the same memory location.
3447 We can split this into a load from memory followed by a register-register
3448 copy. This saves at least one insn, more if register allocation can
3451 We cannot do this if the destination of the first assignment is a
3452 condition code register or cc0. We eliminate this case by making sure
3453 the SET_DEST and SET_SRC have the same mode.
3455 We cannot do this if the destination of the second assignment is
3456 a register that we have already assumed is zero-extended. Similarly
3457 for a SUBREG of such a register. */
3459 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3460 && GET_CODE (newpat) == PARALLEL
3461 && XVECLEN (newpat, 0) == 2
3462 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3463 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
3464 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
3465 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
3466 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3467 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3468 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
3469 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3471 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3472 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3473 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
3475 && VEC_index (reg_stat_type, reg_stat,
3476 REGNO (temp))->nonzero_bits != 0
3477 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3478 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3479 && (VEC_index (reg_stat_type, reg_stat,
3480 REGNO (temp))->nonzero_bits
3481 != GET_MODE_MASK (word_mode))))
3482 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
3483 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
3485 && VEC_index (reg_stat_type, reg_stat,
3486 REGNO (temp))->nonzero_bits != 0
3487 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3488 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3489 && (VEC_index (reg_stat_type, reg_stat,
3490 REGNO (temp))->nonzero_bits
3491 != GET_MODE_MASK (word_mode)))))
3492 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3493 SET_SRC (XVECEXP (newpat, 0, 1)))
3494 && ! find_reg_note (i3, REG_UNUSED,
3495 SET_DEST (XVECEXP (newpat, 0, 0))))
3499 newi2pat = XVECEXP (newpat, 0, 0);
3500 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
3501 newpat = XVECEXP (newpat, 0, 1);
3502 SUBST (SET_SRC (newpat),
3503 gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
3504 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3506 if (i2_code_number >= 0)
3507 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3509 if (insn_code_number >= 0)
3513 /* Similarly, check for a case where we have a PARALLEL of two independent
3514 SETs but we started with three insns. In this case, we can do the sets
3515 as two separate insns. This case occurs when some SET allows two
3516 other insns to combine, but the destination of that SET is still live. */
3518 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3519 && GET_CODE (newpat) == PARALLEL
3520 && XVECLEN (newpat, 0) == 2
3521 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3522 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
3523 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
3524 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3525 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3526 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3527 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3529 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3530 XVECEXP (newpat, 0, 0))
3531 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
3532 XVECEXP (newpat, 0, 1))
3533 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
3534 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1))))
3536 /* We cannot split the parallel into two sets if both sets
3538 && ! (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0))
3539 && reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 1)))
3543 /* Normally, it doesn't matter which of the two is done first,
3544 but it does if one references cc0. In that case, it has to
3547 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
3549 newi2pat = XVECEXP (newpat, 0, 0);
3550 newpat = XVECEXP (newpat, 0, 1);
3555 newi2pat = XVECEXP (newpat, 0, 1);
3556 newpat = XVECEXP (newpat, 0, 0);
3559 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3561 if (i2_code_number >= 0)
3562 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3565 /* If it still isn't recognized, fail and change things back the way they
3567 if ((insn_code_number < 0
3568 /* Is the result a reasonable ASM_OPERANDS? */
3569 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
3575 /* If we had to change another insn, make sure it is valid also. */
3576 if (undobuf.other_insn)
3578 CLEAR_HARD_REG_SET (newpat_used_regs);
3580 other_pat = PATTERN (undobuf.other_insn);
3581 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
3584 if (other_code_number < 0 && ! check_asm_operands (other_pat))
3592 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3593 they are adjacent to each other or not. */
3595 rtx p = prev_nonnote_insn (i3);
3596 if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
3597 && sets_cc0_p (newi2pat))
3605 /* Only allow this combination if insn_rtx_costs reports that the
3606 replacement instructions are cheaper than the originals. */
3607 if (!combine_validate_cost (i1, i2, i3, newpat, newi2pat, other_pat))
3613 if (MAY_HAVE_DEBUG_INSNS)
3617 for (undo = undobuf.undos; undo; undo = undo->next)
3618 if (undo->kind == UNDO_MODE)
3620 rtx reg = *undo->where.r;
3621 enum machine_mode new_mode = GET_MODE (reg);
3622 enum machine_mode old_mode = undo->old_contents.m;
3624 /* Temporarily revert mode back. */
3625 adjust_reg_mode (reg, old_mode);
3627 if (reg == i2dest && i2scratch)
3629 /* If we used i2dest as a scratch register with a
3630 different mode, substitute it for the original
3631 i2src while its original mode is temporarily
3632 restored, and then clear i2scratch so that we don't
3633 do it again later. */
3634 propagate_for_debug (i2, i3, reg, i2src, false);
3636 /* Put back the new mode. */
3637 adjust_reg_mode (reg, new_mode);
3641 rtx tempreg = gen_raw_REG (old_mode, REGNO (reg));
3652 last = undobuf.other_insn;
3656 /* We're dealing with a reg that changed mode but not
3657 meaning, so we want to turn it into a subreg for
3658 the new mode. However, because of REG sharing and
3659 because its mode had already changed, we have to do
3660 it in two steps. First, replace any debug uses of
3661 reg, with its original mode temporarily restored,
3662 with this copy we have created; then, replace the
3663 copy with the SUBREG of the original shared reg,
3664 once again changed to the new mode. */
3665 propagate_for_debug (first, last, reg, tempreg, false);
3666 adjust_reg_mode (reg, new_mode);
3667 propagate_for_debug (first, last, tempreg,
3668 lowpart_subreg (old_mode, reg, new_mode),
3674 /* If we will be able to accept this, we have made a
3675 change to the destination of I3. This requires us to
3676 do a few adjustments. */
3678 if (changed_i3_dest)
3680 PATTERN (i3) = newpat;
3681 adjust_for_new_dest (i3);
3684 /* We now know that we can do this combination. Merge the insns and
3685 update the status of registers and LOG_LINKS. */
3687 if (undobuf.other_insn)
3691 PATTERN (undobuf.other_insn) = other_pat;
3693 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
3694 are still valid. Then add any non-duplicate notes added by
3695 recog_for_combine. */
3696 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
3698 next = XEXP (note, 1);
3700 if (REG_NOTE_KIND (note) == REG_UNUSED
3701 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
3702 remove_note (undobuf.other_insn, note);
3705 distribute_notes (new_other_notes, undobuf.other_insn,
3706 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
3715 /* I3 now uses what used to be its destination and which is now
3716 I2's destination. This requires us to do a few adjustments. */
3717 PATTERN (i3) = newpat;
3718 adjust_for_new_dest (i3);
3720 /* We need a LOG_LINK from I3 to I2. But we used to have one,
3723 However, some later insn might be using I2's dest and have
3724 a LOG_LINK pointing at I3. We must remove this link.
3725 The simplest way to remove the link is to point it at I1,
3726 which we know will be a NOTE. */
3728 /* newi2pat is usually a SET here; however, recog_for_combine might
3729 have added some clobbers. */
3730 if (GET_CODE (newi2pat) == PARALLEL)
3731 ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
3733 ni2dest = SET_DEST (newi2pat);
3735 for (insn = NEXT_INSN (i3);
3736 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3737 || insn != BB_HEAD (this_basic_block->next_bb));
3738 insn = NEXT_INSN (insn))
3740 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
3742 for (link = LOG_LINKS (insn); link;
3743 link = XEXP (link, 1))
3744 if (XEXP (link, 0) == i3)
3745 XEXP (link, 0) = i1;
3753 rtx i3notes, i2notes, i1notes = 0;
3754 rtx i3links, i2links, i1links = 0;
3757 /* Compute which registers we expect to eliminate. newi2pat may be setting
3758 either i3dest or i2dest, so we must check it. Also, i1dest may be the
3759 same as i3dest, in which case newi2pat may be setting i1dest. */
3760 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
3761 || i2dest_in_i2src || i2dest_in_i1src
3764 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
3765 || (newi2pat && reg_set_p (i1dest, newi2pat))
3769 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3771 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
3772 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
3774 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
3776 /* Ensure that we do not have something that should not be shared but
3777 occurs multiple times in the new insns. Check this by first
3778 resetting all the `used' flags and then copying anything is shared. */
3780 reset_used_flags (i3notes);
3781 reset_used_flags (i2notes);
3782 reset_used_flags (i1notes);
3783 reset_used_flags (newpat);
3784 reset_used_flags (newi2pat);
3785 if (undobuf.other_insn)
3786 reset_used_flags (PATTERN (undobuf.other_insn));
3788 i3notes = copy_rtx_if_shared (i3notes);
3789 i2notes = copy_rtx_if_shared (i2notes);
3790 i1notes = copy_rtx_if_shared (i1notes);
3791 newpat = copy_rtx_if_shared (newpat);
3792 newi2pat = copy_rtx_if_shared (newi2pat);
3793 if (undobuf.other_insn)
3794 reset_used_flags (PATTERN (undobuf.other_insn));
3796 INSN_CODE (i3) = insn_code_number;
3797 PATTERN (i3) = newpat;
3799 if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
3801 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
3803 reset_used_flags (call_usage);
3804 call_usage = copy_rtx (call_usage);
3808 /* I2SRC must still be meaningful at this point. Some splitting
3809 operations can invalidate I2SRC, but those operations do not
3812 replace_rtx (call_usage, i2dest, i2src);
3816 replace_rtx (call_usage, i1dest, i1src);
3818 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
3821 if (undobuf.other_insn)
3822 INSN_CODE (undobuf.other_insn) = other_code_number;
3824 /* We had one special case above where I2 had more than one set and
3825 we replaced a destination of one of those sets with the destination
3826 of I3. In that case, we have to update LOG_LINKS of insns later
3827 in this basic block. Note that this (expensive) case is rare.
3829 Also, in this case, we must pretend that all REG_NOTEs for I2
3830 actually came from I3, so that REG_UNUSED notes from I2 will be
3831 properly handled. */
3833 if (i3_subst_into_i2)
3835 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
3836 if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
3837 || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
3838 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
3839 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
3840 && ! find_reg_note (i2, REG_UNUSED,
3841 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
3842 for (temp = NEXT_INSN (i2);
3843 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3844 || BB_HEAD (this_basic_block) != temp);
3845 temp = NEXT_INSN (temp))
3846 if (temp != i3 && INSN_P (temp))
3847 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
3848 if (XEXP (link, 0) == i2)
3849 XEXP (link, 0) = i3;
3854 while (XEXP (link, 1))
3855 link = XEXP (link, 1);
3856 XEXP (link, 1) = i2notes;
3870 if (MAY_HAVE_DEBUG_INSNS && i2scratch)
3871 propagate_for_debug (i2, i3, i2dest, i2src, false);
3872 INSN_CODE (i2) = i2_code_number;
3873 PATTERN (i2) = newi2pat;
3877 if (MAY_HAVE_DEBUG_INSNS && i2src)
3878 propagate_for_debug (i2, i3, i2dest, i2src, i3_subst_into_i2);
3879 SET_INSN_DELETED (i2);
3886 if (MAY_HAVE_DEBUG_INSNS)
3887 propagate_for_debug (i1, i3, i1dest, i1src, false);
3888 SET_INSN_DELETED (i1);
3891 /* Get death notes for everything that is now used in either I3 or
3892 I2 and used to die in a previous insn. If we built two new
3893 patterns, move from I1 to I2 then I2 to I3 so that we get the
3894 proper movement on registers that I2 modifies. */
3898 move_deaths (newi2pat, NULL_RTX, DF_INSN_LUID (i1), i2, &midnotes);
3899 move_deaths (newpat, newi2pat, DF_INSN_LUID (i1), i3, &midnotes);
3902 move_deaths (newpat, NULL_RTX, i1 ? DF_INSN_LUID (i1) : DF_INSN_LUID (i2),
3905 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
3907 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
3910 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
3913 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
3916 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3919 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
3920 know these are REG_UNUSED and want them to go to the desired insn,
3921 so we always pass it as i3. */
3923 if (newi2pat && new_i2_notes)
3924 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3927 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
3929 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
3930 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
3931 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
3932 in that case, it might delete I2. Similarly for I2 and I1.
3933 Show an additional death due to the REG_DEAD note we make here. If
3934 we discard it in distribute_notes, we will decrement it again. */
3938 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
3939 distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
3941 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
3943 distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
3945 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3949 if (i2dest_in_i2src)
3951 if (newi2pat && reg_set_p (i2dest, newi2pat))
3952 distribute_notes (alloc_reg_note (REG_DEAD, i2dest, NULL_RTX),
3953 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3955 distribute_notes (alloc_reg_note (REG_DEAD, i2dest, NULL_RTX),
3956 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3957 NULL_RTX, NULL_RTX);
3960 if (i1dest_in_i1src)
3962 if (newi2pat && reg_set_p (i1dest, newi2pat))
3963 distribute_notes (alloc_reg_note (REG_DEAD, i1dest, NULL_RTX),
3964 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3966 distribute_notes (alloc_reg_note (REG_DEAD, i1dest, NULL_RTX),
3967 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3968 NULL_RTX, NULL_RTX);
3971 distribute_links (i3links);
3972 distribute_links (i2links);
3973 distribute_links (i1links);
3978 rtx i2_insn = 0, i2_val = 0, set;
3980 /* The insn that used to set this register doesn't exist, and
3981 this life of the register may not exist either. See if one of
3982 I3's links points to an insn that sets I2DEST. If it does,
3983 that is now the last known value for I2DEST. If we don't update
3984 this and I2 set the register to a value that depended on its old
3985 contents, we will get confused. If this insn is used, thing
3986 will be set correctly in combine_instructions. */
3988 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3989 if ((set = single_set (XEXP (link, 0))) != 0
3990 && rtx_equal_p (i2dest, SET_DEST (set)))
3991 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
3993 record_value_for_reg (i2dest, i2_insn, i2_val);
3995 /* If the reg formerly set in I2 died only once and that was in I3,
3996 zero its use count so it won't make `reload' do any work. */
3998 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
3999 && ! i2dest_in_i2src)
4001 regno = REGNO (i2dest);
4002 INC_REG_N_SETS (regno, -1);
4006 if (i1 && REG_P (i1dest))
4009 rtx i1_insn = 0, i1_val = 0, set;
4011 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
4012 if ((set = single_set (XEXP (link, 0))) != 0
4013 && rtx_equal_p (i1dest, SET_DEST (set)))
4014 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
4016 record_value_for_reg (i1dest, i1_insn, i1_val);
4018 regno = REGNO (i1dest);
4019 if (! added_sets_1 && ! i1dest_in_i1src)
4020 INC_REG_N_SETS (regno, -1);
4023 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4024 been made to this insn. The order of
4025 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
4026 can affect nonzero_bits of newpat */
4028 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
4029 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
4032 if (undobuf.other_insn != NULL_RTX)
4036 fprintf (dump_file, "modifying other_insn ");
4037 dump_insn_slim (dump_file, undobuf.other_insn);
4039 df_insn_rescan (undobuf.other_insn);
4042 if (i1 && !(NOTE_P(i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED)))
4046 fprintf (dump_file, "modifying insn i1 ");
4047 dump_insn_slim (dump_file, i1);
4049 df_insn_rescan (i1);
4052 if (i2 && !(NOTE_P(i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED)))
4056 fprintf (dump_file, "modifying insn i2 ");
4057 dump_insn_slim (dump_file, i2);
4059 df_insn_rescan (i2);
4062 if (i3 && !(NOTE_P(i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED)))
4066 fprintf (dump_file, "modifying insn i3 ");
4067 dump_insn_slim (dump_file, i3);
4069 df_insn_rescan (i3);
4072 /* Set new_direct_jump_p if a new return or simple jump instruction
4073 has been created. Adjust the CFG accordingly. */
4075 if (returnjump_p (i3) || any_uncondjump_p (i3))
4077 *new_direct_jump_p = 1;
4078 mark_jump_label (PATTERN (i3), i3, 0);
4079 update_cfg_for_uncondjump (i3);
4082 if (undobuf.other_insn != NULL_RTX
4083 && (returnjump_p (undobuf.other_insn)
4084 || any_uncondjump_p (undobuf.other_insn)))
4086 *new_direct_jump_p = 1;
4087 update_cfg_for_uncondjump (undobuf.other_insn);
4090 /* A noop might also need cleaning up of CFG, if it comes from the
4091 simplification of a jump. */
4092 if (GET_CODE (newpat) == SET
4093 && SET_SRC (newpat) == pc_rtx
4094 && SET_DEST (newpat) == pc_rtx)
4096 *new_direct_jump_p = 1;
4097 update_cfg_for_uncondjump (i3);
4100 combine_successes++;
4103 if (added_links_insn
4104 && (newi2pat == 0 || DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i2))
4105 && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i3))
4106 return added_links_insn;
4108 return newi2pat ? i2 : i3;
4111 /* Undo all the modifications recorded in undobuf. */
4116 struct undo *undo, *next;
4118 for (undo = undobuf.undos; undo; undo = next)
4124 *undo->where.r = undo->old_contents.r;
4127 *undo->where.i = undo->old_contents.i;
4130 adjust_reg_mode (*undo->where.r, undo->old_contents.m);
4136 undo->next = undobuf.frees;
4137 undobuf.frees = undo;
4143 /* We've committed to accepting the changes we made. Move all
4144 of the undos to the free list. */
4149 struct undo *undo, *next;
4151 for (undo = undobuf.undos; undo; undo = next)
4154 undo->next = undobuf.frees;
4155 undobuf.frees = undo;
4160 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4161 where we have an arithmetic expression and return that point. LOC will
4164 try_combine will call this function to see if an insn can be split into
4168 find_split_point (rtx *loc, rtx insn, bool set_src)
4171 enum rtx_code code = GET_CODE (x);
4173 unsigned HOST_WIDE_INT len = 0;
4174 HOST_WIDE_INT pos = 0;
4176 rtx inner = NULL_RTX;
4178 /* First special-case some codes. */
4182 #ifdef INSN_SCHEDULING
4183 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4185 if (MEM_P (SUBREG_REG (x)))
4188 return find_split_point (&SUBREG_REG (x), insn, false);
4192 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4193 using LO_SUM and HIGH. */
4194 if (GET_CODE (XEXP (x, 0)) == CONST
4195 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
4197 enum machine_mode address_mode
4198 = targetm.addr_space.address_mode (MEM_ADDR_SPACE (x));
4201 gen_rtx_LO_SUM (address_mode,
4202 gen_rtx_HIGH (address_mode, XEXP (x, 0)),
4204 return &XEXP (XEXP (x, 0), 0);
4208 /* If we have a PLUS whose second operand is a constant and the
4209 address is not valid, perhaps will can split it up using
4210 the machine-specific way to split large constants. We use
4211 the first pseudo-reg (one of the virtual regs) as a placeholder;
4212 it will not remain in the result. */
4213 if (GET_CODE (XEXP (x, 0)) == PLUS
4214 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
4215 && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4216 MEM_ADDR_SPACE (x)))
4218 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
4219 rtx seq = combine_split_insns (gen_rtx_SET (VOIDmode, reg,
4223 /* This should have produced two insns, each of which sets our
4224 placeholder. If the source of the second is a valid address,
4225 we can make put both sources together and make a split point
4229 && NEXT_INSN (seq) != NULL_RTX
4230 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
4231 && NONJUMP_INSN_P (seq)
4232 && GET_CODE (PATTERN (seq)) == SET
4233 && SET_DEST (PATTERN (seq)) == reg
4234 && ! reg_mentioned_p (reg,
4235 SET_SRC (PATTERN (seq)))
4236 && NONJUMP_INSN_P (NEXT_INSN (seq))
4237 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
4238 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
4239 && memory_address_addr_space_p
4240 (GET_MODE (x), SET_SRC (PATTERN (NEXT_INSN (seq))),
4241 MEM_ADDR_SPACE (x)))
4243 rtx src1 = SET_SRC (PATTERN (seq));
4244 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
4246 /* Replace the placeholder in SRC2 with SRC1. If we can
4247 find where in SRC2 it was placed, that can become our
4248 split point and we can replace this address with SRC2.
4249 Just try two obvious places. */
4251 src2 = replace_rtx (src2, reg, src1);
4253 if (XEXP (src2, 0) == src1)
4254 split = &XEXP (src2, 0);
4255 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
4256 && XEXP (XEXP (src2, 0), 0) == src1)
4257 split = &XEXP (XEXP (src2, 0), 0);
4261 SUBST (XEXP (x, 0), src2);
4266 /* If that didn't work, perhaps the first operand is complex and
4267 needs to be computed separately, so make a split point there.
4268 This will occur on machines that just support REG + CONST
4269 and have a constant moved through some previous computation. */
4271 else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
4272 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4273 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4274 return &XEXP (XEXP (x, 0), 0);
4277 /* If we have a PLUS whose first operand is complex, try computing it
4278 separately by making a split there. */
4279 if (GET_CODE (XEXP (x, 0)) == PLUS
4280 && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4282 && ! OBJECT_P (XEXP (XEXP (x, 0), 0))
4283 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4284 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4285 return &XEXP (XEXP (x, 0), 0);
4290 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4291 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4292 we need to put the operand into a register. So split at that
4295 if (SET_DEST (x) == cc0_rtx
4296 && GET_CODE (SET_SRC (x)) != COMPARE
4297 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
4298 && !OBJECT_P (SET_SRC (x))
4299 && ! (GET_CODE (SET_SRC (x)) == SUBREG
4300 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
4301 return &SET_SRC (x);
4304 /* See if we can split SET_SRC as it stands. */
4305 split = find_split_point (&SET_SRC (x), insn, true);
4306 if (split && split != &SET_SRC (x))
4309 /* See if we can split SET_DEST as it stands. */
4310 split = find_split_point (&SET_DEST (x), insn, false);
4311 if (split && split != &SET_DEST (x))
4314 /* See if this is a bitfield assignment with everything constant. If
4315 so, this is an IOR of an AND, so split it into that. */
4316 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
4317 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
4318 <= HOST_BITS_PER_WIDE_INT)
4319 && CONST_INT_P (XEXP (SET_DEST (x), 1))
4320 && CONST_INT_P (XEXP (SET_DEST (x), 2))
4321 && CONST_INT_P (SET_SRC (x))
4322 && ((INTVAL (XEXP (SET_DEST (x), 1))
4323 + INTVAL (XEXP (SET_DEST (x), 2)))
4324 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
4325 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
4327 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
4328 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
4329 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
4330 rtx dest = XEXP (SET_DEST (x), 0);
4331 enum machine_mode mode = GET_MODE (dest);
4332 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
4335 if (BITS_BIG_ENDIAN)
4336 pos = GET_MODE_BITSIZE (mode) - len - pos;
4338 or_mask = gen_int_mode (src << pos, mode);
4341 simplify_gen_binary (IOR, mode, dest, or_mask));
4344 rtx negmask = gen_int_mode (~(mask << pos), mode);
4346 simplify_gen_binary (IOR, mode,
4347 simplify_gen_binary (AND, mode,
4352 SUBST (SET_DEST (x), dest);
4354 split = find_split_point (&SET_SRC (x), insn, true);
4355 if (split && split != &SET_SRC (x))
4359 /* Otherwise, see if this is an operation that we can split into two.
4360 If so, try to split that. */
4361 code = GET_CODE (SET_SRC (x));
4366 /* If we are AND'ing with a large constant that is only a single
4367 bit and the result is only being used in a context where we
4368 need to know if it is zero or nonzero, replace it with a bit
4369 extraction. This will avoid the large constant, which might
4370 have taken more than one insn to make. If the constant were
4371 not a valid argument to the AND but took only one insn to make,
4372 this is no worse, but if it took more than one insn, it will
4375 if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4376 && REG_P (XEXP (SET_SRC (x), 0))
4377 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
4378 && REG_P (SET_DEST (x))
4379 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
4380 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
4381 && XEXP (*split, 0) == SET_DEST (x)
4382 && XEXP (*split, 1) == const0_rtx)
4384 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
4385 XEXP (SET_SRC (x), 0),
4386 pos, NULL_RTX, 1, 1, 0, 0);
4387 if (extraction != 0)
4389 SUBST (SET_SRC (x), extraction);
4390 return find_split_point (loc, insn, false);
4396 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4397 is known to be on, this can be converted into a NEG of a shift. */
4398 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
4399 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
4400 && 1 <= (pos = exact_log2
4401 (nonzero_bits (XEXP (SET_SRC (x), 0),
4402 GET_MODE (XEXP (SET_SRC (x), 0))))))
4404 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
4408 gen_rtx_LSHIFTRT (mode,
4409 XEXP (SET_SRC (x), 0),
4412 split = find_split_point (&SET_SRC (x), insn, true);
4413 if (split && split != &SET_SRC (x))
4419 inner = XEXP (SET_SRC (x), 0);
4421 /* We can't optimize if either mode is a partial integer
4422 mode as we don't know how many bits are significant
4424 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
4425 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
4429 len = GET_MODE_BITSIZE (GET_MODE (inner));
4435 if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4436 && CONST_INT_P (XEXP (SET_SRC (x), 2)))
4438 inner = XEXP (SET_SRC (x), 0);
4439 len = INTVAL (XEXP (SET_SRC (x), 1));
4440 pos = INTVAL (XEXP (SET_SRC (x), 2));
4442 if (BITS_BIG_ENDIAN)
4443 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
4444 unsignedp = (code == ZERO_EXTRACT);
4452 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
4454 enum machine_mode mode = GET_MODE (SET_SRC (x));
4456 /* For unsigned, we have a choice of a shift followed by an
4457 AND or two shifts. Use two shifts for field sizes where the
4458 constant might be too large. We assume here that we can
4459 always at least get 8-bit constants in an AND insn, which is
4460 true for every current RISC. */
4462 if (unsignedp && len <= 8)
4467 (mode, gen_lowpart (mode, inner),
4469 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
4471 split = find_split_point (&SET_SRC (x), insn, true);
4472 if (split && split != &SET_SRC (x))
4479 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
4480 gen_rtx_ASHIFT (mode,
4481 gen_lowpart (mode, inner),
4482 GEN_INT (GET_MODE_BITSIZE (mode)
4484 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
4486 split = find_split_point (&SET_SRC (x), insn, true);
4487 if (split && split != &SET_SRC (x))
4492 /* See if this is a simple operation with a constant as the second
4493 operand. It might be that this constant is out of range and hence
4494 could be used as a split point. */
4495 if (BINARY_P (SET_SRC (x))
4496 && CONSTANT_P (XEXP (SET_SRC (x), 1))
4497 && (OBJECT_P (XEXP (SET_SRC (x), 0))
4498 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
4499 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
4500 return &XEXP (SET_SRC (x), 1);
4502 /* Finally, see if this is a simple operation with its first operand
4503 not in a register. The operation might require this operand in a
4504 register, so return it as a split point. We can always do this
4505 because if the first operand were another operation, we would have
4506 already found it as a split point. */
4507 if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
4508 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
4509 return &XEXP (SET_SRC (x), 0);
4515 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4516 it is better to write this as (not (ior A B)) so we can split it.
4517 Similarly for IOR. */
4518 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
4521 gen_rtx_NOT (GET_MODE (x),
4522 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
4524 XEXP (XEXP (x, 0), 0),
4525 XEXP (XEXP (x, 1), 0))));
4526 return find_split_point (loc, insn, set_src);
4529 /* Many RISC machines have a large set of logical insns. If the
4530 second operand is a NOT, put it first so we will try to split the
4531 other operand first. */
4532 if (GET_CODE (XEXP (x, 1)) == NOT)
4534 rtx tem = XEXP (x, 0);
4535 SUBST (XEXP (x, 0), XEXP (x, 1));
4536 SUBST (XEXP (x, 1), tem);
4542 /* Split at a multiply-accumulate instruction. However if this is
4543 the SET_SRC, we likely do not have such an instruction and it's
4544 worthless to try this split. */
4545 if (!set_src && GET_CODE (XEXP (x, 0)) == MULT)
4552 /* Otherwise, select our actions depending on our rtx class. */
4553 switch (GET_RTX_CLASS (code))
4555 case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
4557 split = find_split_point (&XEXP (x, 2), insn, false);
4560 /* ... fall through ... */
4562 case RTX_COMM_ARITH:
4564 case RTX_COMM_COMPARE:
4565 split = find_split_point (&XEXP (x, 1), insn, false);
4568 /* ... fall through ... */
4570 /* Some machines have (and (shift ...) ...) insns. If X is not
4571 an AND, but XEXP (X, 0) is, use it as our split point. */
4572 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
4573 return &XEXP (x, 0);
4575 split = find_split_point (&XEXP (x, 0), insn, false);
4581 /* Otherwise, we don't have a split point. */
4586 /* Throughout X, replace FROM with TO, and return the result.
4587 The result is TO if X is FROM;
4588 otherwise the result is X, but its contents may have been modified.
4589 If they were modified, a record was made in undobuf so that
4590 undo_all will (among other things) return X to its original state.
4592 If the number of changes necessary is too much to record to undo,
4593 the excess changes are not made, so the result is invalid.
4594 The changes already made can still be undone.
4595 undobuf.num_undo is incremented for such changes, so by testing that
4596 the caller can tell whether the result is valid.
4598 `n_occurrences' is incremented each time FROM is replaced.
4600 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4602 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
4603 by copying if `n_occurrences' is nonzero. */
4606 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
4608 enum rtx_code code = GET_CODE (x);
4609 enum machine_mode op0_mode = VOIDmode;
4614 /* Two expressions are equal if they are identical copies of a shared
4615 RTX or if they are both registers with the same register number
4618 #define COMBINE_RTX_EQUAL_P(X,Y) \
4620 || (REG_P (X) && REG_P (Y) \
4621 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4623 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
4626 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
4629 /* If X and FROM are the same register but different modes, they
4630 will not have been seen as equal above. However, the log links code
4631 will make a LOG_LINKS entry for that case. If we do nothing, we
4632 will try to rerecognize our original insn and, when it succeeds,
4633 we will delete the feeding insn, which is incorrect.
4635 So force this insn not to match in this (rare) case. */
4636 if (! in_dest && code == REG && REG_P (from)
4637 && reg_overlap_mentioned_p (x, from))
4638 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
4640 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4641 of which may contain things that can be combined. */
4642 if (code != MEM && code != LO_SUM && OBJECT_P (x))
4645 /* It is possible to have a subexpression appear twice in the insn.
4646 Suppose that FROM is a register that appears within TO.
4647 Then, after that subexpression has been scanned once by `subst',
4648 the second time it is scanned, TO may be found. If we were
4649 to scan TO here, we would find FROM within it and create a
4650 self-referent rtl structure which is completely wrong. */
4651 if (COMBINE_RTX_EQUAL_P (x, to))
4654 /* Parallel asm_operands need special attention because all of the
4655 inputs are shared across the arms. Furthermore, unsharing the
4656 rtl results in recognition failures. Failure to handle this case
4657 specially can result in circular rtl.
4659 Solve this by doing a normal pass across the first entry of the
4660 parallel, and only processing the SET_DESTs of the subsequent
4663 if (code == PARALLEL
4664 && GET_CODE (XVECEXP (x, 0, 0)) == SET
4665 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
4667 new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
4669 /* If this substitution failed, this whole thing fails. */
4670 if (GET_CODE (new_rtx) == CLOBBER
4671 && XEXP (new_rtx, 0) == const0_rtx)
4674 SUBST (XVECEXP (x, 0, 0), new_rtx);
4676 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
4678 rtx dest = SET_DEST (XVECEXP (x, 0, i));
4681 && GET_CODE (dest) != CC0
4682 && GET_CODE (dest) != PC)
4684 new_rtx = subst (dest, from, to, 0, unique_copy);
4686 /* If this substitution failed, this whole thing fails. */
4687 if (GET_CODE (new_rtx) == CLOBBER
4688 && XEXP (new_rtx, 0) == const0_rtx)
4691 SUBST (SET_DEST (XVECEXP (x, 0, i)), new_rtx);
4697 len = GET_RTX_LENGTH (code);
4698 fmt = GET_RTX_FORMAT (code);
4700 /* We don't need to process a SET_DEST that is a register, CC0,
4701 or PC, so set up to skip this common case. All other cases
4702 where we want to suppress replacing something inside a
4703 SET_SRC are handled via the IN_DEST operand. */
4705 && (REG_P (SET_DEST (x))
4706 || GET_CODE (SET_DEST (x)) == CC0
4707 || GET_CODE (SET_DEST (x)) == PC))
4710 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
4713 op0_mode = GET_MODE (XEXP (x, 0));
4715 for (i = 0; i < len; i++)
4720 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4722 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
4724 new_rtx = (unique_copy && n_occurrences
4725 ? copy_rtx (to) : to);
4730 new_rtx = subst (XVECEXP (x, i, j), from, to, 0,
4733 /* If this substitution failed, this whole thing
4735 if (GET_CODE (new_rtx) == CLOBBER
4736 && XEXP (new_rtx, 0) == const0_rtx)
4740 SUBST (XVECEXP (x, i, j), new_rtx);
4743 else if (fmt[i] == 'e')
4745 /* If this is a register being set, ignore it. */
4746 new_rtx = XEXP (x, i);
4749 && (((code == SUBREG || code == ZERO_EXTRACT)
4751 || code == STRICT_LOW_PART))
4754 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
4756 /* In general, don't install a subreg involving two
4757 modes not tieable. It can worsen register
4758 allocation, and can even make invalid reload
4759 insns, since the reg inside may need to be copied
4760 from in the outside mode, and that may be invalid
4761 if it is an fp reg copied in integer mode.
4763 We allow two exceptions to this: It is valid if
4764 it is inside another SUBREG and the mode of that
4765 SUBREG and the mode of the inside of TO is
4766 tieable and it is valid if X is a SET that copies
4769 if (GET_CODE (to) == SUBREG
4770 && ! MODES_TIEABLE_P (GET_MODE (to),
4771 GET_MODE (SUBREG_REG (to)))
4772 && ! (code == SUBREG
4773 && MODES_TIEABLE_P (GET_MODE (x),
4774 GET_MODE (SUBREG_REG (to))))
4776 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
4779 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4781 #ifdef CANNOT_CHANGE_MODE_CLASS
4784 && REGNO (to) < FIRST_PSEUDO_REGISTER
4785 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
4788 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4791 new_rtx = (unique_copy && n_occurrences ? copy_rtx (to) : to);
4795 /* If we are in a SET_DEST, suppress most cases unless we
4796 have gone inside a MEM, in which case we want to
4797 simplify the address. We assume here that things that
4798 are actually part of the destination have their inner
4799 parts in the first expression. This is true for SUBREG,
4800 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
4801 things aside from REG and MEM that should appear in a
4803 new_rtx = subst (XEXP (x, i), from, to,
4805 && (code == SUBREG || code == STRICT_LOW_PART
4806 || code == ZERO_EXTRACT))
4808 && i == 0), unique_copy);
4810 /* If we found that we will have to reject this combination,
4811 indicate that by returning the CLOBBER ourselves, rather than
4812 an expression containing it. This will speed things up as
4813 well as prevent accidents where two CLOBBERs are considered
4814 to be equal, thus producing an incorrect simplification. */
4816 if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx)
4819 if (GET_CODE (x) == SUBREG
4820 && (CONST_INT_P (new_rtx)
4821 || GET_CODE (new_rtx) == CONST_DOUBLE))
4823 enum machine_mode mode = GET_MODE (x);
4825 x = simplify_subreg (GET_MODE (x), new_rtx,
4826 GET_MODE (SUBREG_REG (x)),
4829 x = gen_rtx_CLOBBER (mode, const0_rtx);
4831 else if (CONST_INT_P (new_rtx)
4832 && GET_CODE (x) == ZERO_EXTEND)
4834 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
4835 new_rtx, GET_MODE (XEXP (x, 0)));
4839 SUBST (XEXP (x, i), new_rtx);
4844 /* Check if we are loading something from the constant pool via float
4845 extension; in this case we would undo compress_float_constant
4846 optimization and degenerate constant load to an immediate value. */
4847 if (GET_CODE (x) == FLOAT_EXTEND
4848 && MEM_P (XEXP (x, 0))
4849 && MEM_READONLY_P (XEXP (x, 0)))
4851 rtx tmp = avoid_constant_pool_reference (x);
4856 /* Try to simplify X. If the simplification changed the code, it is likely
4857 that further simplification will help, so loop, but limit the number
4858 of repetitions that will be performed. */
4860 for (i = 0; i < 4; i++)
4862 /* If X is sufficiently simple, don't bother trying to do anything
4864 if (code != CONST_INT && code != REG && code != CLOBBER)
4865 x = combine_simplify_rtx (x, op0_mode, in_dest);
4867 if (GET_CODE (x) == code)
4870 code = GET_CODE (x);
4872 /* We no longer know the original mode of operand 0 since we
4873 have changed the form of X) */
4874 op0_mode = VOIDmode;
4880 /* Simplify X, a piece of RTL. We just operate on the expression at the
4881 outer level; call `subst' to simplify recursively. Return the new
4884 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
4885 if we are inside a SET_DEST. */
4888 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
4890 enum rtx_code code = GET_CODE (x);
4891 enum machine_mode mode = GET_MODE (x);
4895 /* If this is a commutative operation, put a constant last and a complex
4896 expression first. We don't need to do this for comparisons here. */
4897 if (COMMUTATIVE_ARITH_P (x)
4898 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
4901 SUBST (XEXP (x, 0), XEXP (x, 1));
4902 SUBST (XEXP (x, 1), temp);
4905 /* If this is a simple operation applied to an IF_THEN_ELSE, try
4906 applying it to the arms of the IF_THEN_ELSE. This often simplifies
4907 things. Check for cases where both arms are testing the same
4910 Don't do anything if all operands are very simple. */
4913 && ((!OBJECT_P (XEXP (x, 0))
4914 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4915 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
4916 || (!OBJECT_P (XEXP (x, 1))
4917 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
4918 && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
4920 && (!OBJECT_P (XEXP (x, 0))
4921 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4922 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
4924 rtx cond, true_rtx, false_rtx;
4926 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
4928 /* If everything is a comparison, what we have is highly unlikely
4929 to be simpler, so don't use it. */
4930 && ! (COMPARISON_P (x)
4931 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
4933 rtx cop1 = const0_rtx;
4934 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
4936 if (cond_code == NE && COMPARISON_P (cond))
4939 /* Simplify the alternative arms; this may collapse the true and
4940 false arms to store-flag values. Be careful to use copy_rtx
4941 here since true_rtx or false_rtx might share RTL with x as a
4942 result of the if_then_else_cond call above. */
4943 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
4944 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
4946 /* If true_rtx and false_rtx are not general_operands, an if_then_else
4947 is unlikely to be simpler. */
4948 if (general_operand (true_rtx, VOIDmode)
4949 && general_operand (false_rtx, VOIDmode))
4951 enum rtx_code reversed;
4953 /* Restarting if we generate a store-flag expression will cause
4954 us to loop. Just drop through in this case. */
4956 /* If the result values are STORE_FLAG_VALUE and zero, we can
4957 just make the comparison operation. */
4958 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
4959 x = simplify_gen_relational (cond_code, mode, VOIDmode,
4961 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
4962 && ((reversed = reversed_comparison_code_parts
4963 (cond_code, cond, cop1, NULL))
4965 x = simplify_gen_relational (reversed, mode, VOIDmode,
4968 /* Likewise, we can make the negate of a comparison operation
4969 if the result values are - STORE_FLAG_VALUE and zero. */
4970 else if (CONST_INT_P (true_rtx)
4971 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
4972 && false_rtx == const0_rtx)
4973 x = simplify_gen_unary (NEG, mode,
4974 simplify_gen_relational (cond_code,
4978 else if (CONST_INT_P (false_rtx)
4979 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
4980 && true_rtx == const0_rtx
4981 && ((reversed = reversed_comparison_code_parts
4982 (cond_code, cond, cop1, NULL))
4984 x = simplify_gen_unary (NEG, mode,
4985 simplify_gen_relational (reversed,
4990 return gen_rtx_IF_THEN_ELSE (mode,
4991 simplify_gen_relational (cond_code,
4996 true_rtx, false_rtx);
4998 code = GET_CODE (x);
4999 op0_mode = VOIDmode;
5004 /* Try to fold this expression in case we have constants that weren't
5007 switch (GET_RTX_CLASS (code))
5010 if (op0_mode == VOIDmode)
5011 op0_mode = GET_MODE (XEXP (x, 0));
5012 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
5015 case RTX_COMM_COMPARE:
5017 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
5018 if (cmp_mode == VOIDmode)
5020 cmp_mode = GET_MODE (XEXP (x, 1));
5021 if (cmp_mode == VOIDmode)
5022 cmp_mode = op0_mode;
5024 temp = simplify_relational_operation (code, mode, cmp_mode,
5025 XEXP (x, 0), XEXP (x, 1));
5028 case RTX_COMM_ARITH:
5030 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
5032 case RTX_BITFIELD_OPS:
5034 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
5035 XEXP (x, 1), XEXP (x, 2));
5044 code = GET_CODE (temp);
5045 op0_mode = VOIDmode;
5046 mode = GET_MODE (temp);
5049 /* First see if we can apply the inverse distributive law. */
5050 if (code == PLUS || code == MINUS
5051 || code == AND || code == IOR || code == XOR)
5053 x = apply_distributive_law (x);
5054 code = GET_CODE (x);
5055 op0_mode = VOIDmode;
5058 /* If CODE is an associative operation not otherwise handled, see if we
5059 can associate some operands. This can win if they are constants or
5060 if they are logically related (i.e. (a & b) & a). */
5061 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
5062 || code == AND || code == IOR || code == XOR
5063 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
5064 && ((INTEGRAL_MODE_P (mode) && code != DIV)
5065 || (flag_associative_math && FLOAT_MODE_P (mode))))
5067 if (GET_CODE (XEXP (x, 0)) == code)
5069 rtx other = XEXP (XEXP (x, 0), 0);
5070 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
5071 rtx inner_op1 = XEXP (x, 1);
5074 /* Make sure we pass the constant operand if any as the second
5075 one if this is a commutative operation. */
5076 if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
5078 rtx tem = inner_op0;
5079 inner_op0 = inner_op1;
5082 inner = simplify_binary_operation (code == MINUS ? PLUS
5083 : code == DIV ? MULT
5085 mode, inner_op0, inner_op1);
5087 /* For commutative operations, try the other pair if that one
5089 if (inner == 0 && COMMUTATIVE_ARITH_P (x))
5091 other = XEXP (XEXP (x, 0), 1);
5092 inner = simplify_binary_operation (code, mode,
5093 XEXP (XEXP (x, 0), 0),
5098 return simplify_gen_binary (code, mode, other, inner);
5102 /* A little bit of algebraic simplification here. */
5106 /* Ensure that our address has any ASHIFTs converted to MULT in case
5107 address-recognizing predicates are called later. */
5108 temp = make_compound_operation (XEXP (x, 0), MEM);
5109 SUBST (XEXP (x, 0), temp);
5113 if (op0_mode == VOIDmode)
5114 op0_mode = GET_MODE (SUBREG_REG (x));
5116 /* See if this can be moved to simplify_subreg. */
5117 if (CONSTANT_P (SUBREG_REG (x))
5118 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
5119 /* Don't call gen_lowpart if the inner mode
5120 is VOIDmode and we cannot simplify it, as SUBREG without
5121 inner mode is invalid. */
5122 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
5123 || gen_lowpart_common (mode, SUBREG_REG (x))))
5124 return gen_lowpart (mode, SUBREG_REG (x));
5126 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
5130 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
5136 /* Don't change the mode of the MEM if that would change the meaning
5138 if (MEM_P (SUBREG_REG (x))
5139 && (MEM_VOLATILE_P (SUBREG_REG (x))
5140 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
5141 return gen_rtx_CLOBBER (mode, const0_rtx);
5143 /* Note that we cannot do any narrowing for non-constants since
5144 we might have been counting on using the fact that some bits were
5145 zero. We now do this in the SET. */
5150 temp = expand_compound_operation (XEXP (x, 0));
5152 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5153 replaced by (lshiftrt X C). This will convert
5154 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5156 if (GET_CODE (temp) == ASHIFTRT
5157 && CONST_INT_P (XEXP (temp, 1))
5158 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
5159 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
5160 INTVAL (XEXP (temp, 1)));
5162 /* If X has only a single bit that might be nonzero, say, bit I, convert
5163 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5164 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5165 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5166 or a SUBREG of one since we'd be making the expression more
5167 complex if it was just a register. */
5170 && ! (GET_CODE (temp) == SUBREG
5171 && REG_P (SUBREG_REG (temp)))
5172 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
5174 rtx temp1 = simplify_shift_const
5175 (NULL_RTX, ASHIFTRT, mode,
5176 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
5177 GET_MODE_BITSIZE (mode) - 1 - i),
5178 GET_MODE_BITSIZE (mode) - 1 - i);
5180 /* If all we did was surround TEMP with the two shifts, we
5181 haven't improved anything, so don't use it. Otherwise,
5182 we are better off with TEMP1. */
5183 if (GET_CODE (temp1) != ASHIFTRT
5184 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
5185 || XEXP (XEXP (temp1, 0), 0) != temp)
5191 /* We can't handle truncation to a partial integer mode here
5192 because we don't know the real bitsize of the partial
5194 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
5197 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5199 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
5200 GET_MODE_MASK (mode), 0));
5202 /* We can truncate a constant value and return it. */
5203 if (CONST_INT_P (XEXP (x, 0)))
5204 return gen_int_mode (INTVAL (XEXP (x, 0)), mode);
5206 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5207 whose value is a comparison can be replaced with a subreg if
5208 STORE_FLAG_VALUE permits. */
5209 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5210 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
5211 && (temp = get_last_value (XEXP (x, 0)))
5212 && COMPARISON_P (temp))
5213 return gen_lowpart (mode, XEXP (x, 0));
5217 /* (const (const X)) can become (const X). Do it this way rather than
5218 returning the inner CONST since CONST can be shared with a
5220 if (GET_CODE (XEXP (x, 0)) == CONST)
5221 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
5226 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5227 can add in an offset. find_split_point will split this address up
5228 again if it doesn't match. */
5229 if (GET_CODE (XEXP (x, 0)) == HIGH
5230 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
5236 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5237 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5238 bit-field and can be replaced by either a sign_extend or a
5239 sign_extract. The `and' may be a zero_extend and the two
5240 <c>, -<c> constants may be reversed. */
5241 if (GET_CODE (XEXP (x, 0)) == XOR
5242 && CONST_INT_P (XEXP (x, 1))
5243 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
5244 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
5245 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
5246 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
5247 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5248 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
5249 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
5250 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
5251 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
5252 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
5253 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
5254 == (unsigned int) i + 1))))
5255 return simplify_shift_const
5256 (NULL_RTX, ASHIFTRT, mode,
5257 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5258 XEXP (XEXP (XEXP (x, 0), 0), 0),
5259 GET_MODE_BITSIZE (mode) - (i + 1)),
5260 GET_MODE_BITSIZE (mode) - (i + 1));
5262 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5263 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5264 the bitsize of the mode - 1. This allows simplification of
5265 "a = (b & 8) == 0;" */
5266 if (XEXP (x, 1) == constm1_rtx
5267 && !REG_P (XEXP (x, 0))
5268 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5269 && REG_P (SUBREG_REG (XEXP (x, 0))))
5270 && nonzero_bits (XEXP (x, 0), mode) == 1)
5271 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
5272 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5273 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
5274 GET_MODE_BITSIZE (mode) - 1),
5275 GET_MODE_BITSIZE (mode) - 1);
5277 /* If we are adding two things that have no bits in common, convert
5278 the addition into an IOR. This will often be further simplified,
5279 for example in cases like ((a & 1) + (a & 2)), which can
5282 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5283 && (nonzero_bits (XEXP (x, 0), mode)
5284 & nonzero_bits (XEXP (x, 1), mode)) == 0)
5286 /* Try to simplify the expression further. */
5287 rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
5288 temp = combine_simplify_rtx (tor, mode, in_dest);
5290 /* If we could, great. If not, do not go ahead with the IOR
5291 replacement, since PLUS appears in many special purpose
5292 address arithmetic instructions. */
5293 if (GET_CODE (temp) != CLOBBER && temp != tor)
5299 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5300 (and <foo> (const_int pow2-1)) */
5301 if (GET_CODE (XEXP (x, 1)) == AND
5302 && CONST_INT_P (XEXP (XEXP (x, 1), 1))
5303 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
5304 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
5305 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
5306 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
5310 /* If we have (mult (plus A B) C), apply the distributive law and then
5311 the inverse distributive law to see if things simplify. This
5312 occurs mostly in addresses, often when unrolling loops. */
5314 if (GET_CODE (XEXP (x, 0)) == PLUS)
5316 rtx result = distribute_and_simplify_rtx (x, 0);
5321 /* Try simplify a*(b/c) as (a*b)/c. */
5322 if (FLOAT_MODE_P (mode) && flag_associative_math
5323 && GET_CODE (XEXP (x, 0)) == DIV)
5325 rtx tem = simplify_binary_operation (MULT, mode,
5326 XEXP (XEXP (x, 0), 0),
5329 return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
5334 /* If this is a divide by a power of two, treat it as a shift if
5335 its first operand is a shift. */
5336 if (CONST_INT_P (XEXP (x, 1))
5337 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
5338 && (GET_CODE (XEXP (x, 0)) == ASHIFT
5339 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
5340 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
5341 || GET_CODE (XEXP (x, 0)) == ROTATE
5342 || GET_CODE (XEXP (x, 0)) == ROTATERT))
5343 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
5347 case GT: case GTU: case GE: case GEU:
5348 case LT: case LTU: case LE: case LEU:
5349 case UNEQ: case LTGT:
5350 case UNGT: case UNGE:
5351 case UNLT: case UNLE:
5352 case UNORDERED: case ORDERED:
5353 /* If the first operand is a condition code, we can't do anything
5355 if (GET_CODE (XEXP (x, 0)) == COMPARE
5356 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
5357 && ! CC0_P (XEXP (x, 0))))
5359 rtx op0 = XEXP (x, 0);
5360 rtx op1 = XEXP (x, 1);
5361 enum rtx_code new_code;
5363 if (GET_CODE (op0) == COMPARE)
5364 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
5366 /* Simplify our comparison, if possible. */
5367 new_code = simplify_comparison (code, &op0, &op1);
5369 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5370 if only the low-order bit is possibly nonzero in X (such as when
5371 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5372 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5373 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5376 Remove any ZERO_EXTRACT we made when thinking this was a
5377 comparison. It may now be simpler to use, e.g., an AND. If a
5378 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5379 the call to make_compound_operation in the SET case. */
5381 if (STORE_FLAG_VALUE == 1
5382 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5383 && op1 == const0_rtx
5384 && mode == GET_MODE (op0)
5385 && nonzero_bits (op0, mode) == 1)
5386 return gen_lowpart (mode,
5387 expand_compound_operation (op0));
5389 else if (STORE_FLAG_VALUE == 1
5390 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5391 && op1 == const0_rtx
5392 && mode == GET_MODE (op0)
5393 && (num_sign_bit_copies (op0, mode)
5394 == GET_MODE_BITSIZE (mode)))
5396 op0 = expand_compound_operation (op0);
5397 return simplify_gen_unary (NEG, mode,
5398 gen_lowpart (mode, op0),
5402 else if (STORE_FLAG_VALUE == 1
5403 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5404 && op1 == const0_rtx
5405 && mode == GET_MODE (op0)
5406 && nonzero_bits (op0, mode) == 1)
5408 op0 = expand_compound_operation (op0);
5409 return simplify_gen_binary (XOR, mode,
5410 gen_lowpart (mode, op0),
5414 else if (STORE_FLAG_VALUE == 1
5415 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5416 && op1 == const0_rtx
5417 && mode == GET_MODE (op0)
5418 && (num_sign_bit_copies (op0, mode)
5419 == GET_MODE_BITSIZE (mode)))
5421 op0 = expand_compound_operation (op0);
5422 return plus_constant (gen_lowpart (mode, op0), 1);
5425 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5427 if (STORE_FLAG_VALUE == -1
5428 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5429 && op1 == const0_rtx
5430 && (num_sign_bit_copies (op0, mode)
5431 == GET_MODE_BITSIZE (mode)))
5432 return gen_lowpart (mode,
5433 expand_compound_operation (op0));
5435 else if (STORE_FLAG_VALUE == -1
5436 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5437 && op1 == const0_rtx
5438 && mode == GET_MODE (op0)
5439 && nonzero_bits (op0, mode) == 1)
5441 op0 = expand_compound_operation (op0);
5442 return simplify_gen_unary (NEG, mode,
5443 gen_lowpart (mode, op0),
5447 else if (STORE_FLAG_VALUE == -1
5448 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5449 && op1 == const0_rtx
5450 && mode == GET_MODE (op0)
5451 && (num_sign_bit_copies (op0, mode)
5452 == GET_MODE_BITSIZE (mode)))
5454 op0 = expand_compound_operation (op0);
5455 return simplify_gen_unary (NOT, mode,
5456 gen_lowpart (mode, op0),
5460 /* If X is 0/1, (eq X 0) is X-1. */
5461 else if (STORE_FLAG_VALUE == -1
5462 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5463 && op1 == const0_rtx
5464 && mode == GET_MODE (op0)
5465 && nonzero_bits (op0, mode) == 1)
5467 op0 = expand_compound_operation (op0);
5468 return plus_constant (gen_lowpart (mode, op0), -1);
5471 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5472 one bit that might be nonzero, we can convert (ne x 0) to
5473 (ashift x c) where C puts the bit in the sign bit. Remove any
5474 AND with STORE_FLAG_VALUE when we are done, since we are only
5475 going to test the sign bit. */
5476 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5477 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5478 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5479 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5480 && op1 == const0_rtx
5481 && mode == GET_MODE (op0)
5482 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
5484 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
5485 expand_compound_operation (op0),
5486 GET_MODE_BITSIZE (mode) - 1 - i);
5487 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
5493 /* If the code changed, return a whole new comparison. */
5494 if (new_code != code)
5495 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
5497 /* Otherwise, keep this operation, but maybe change its operands.
5498 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5499 SUBST (XEXP (x, 0), op0);
5500 SUBST (XEXP (x, 1), op1);
5505 return simplify_if_then_else (x);
5511 /* If we are processing SET_DEST, we are done. */
5515 return expand_compound_operation (x);
5518 return simplify_set (x);
5522 return simplify_logical (x);
5529 /* If this is a shift by a constant amount, simplify it. */
5530 if (CONST_INT_P (XEXP (x, 1)))
5531 return simplify_shift_const (x, code, mode, XEXP (x, 0),
5532 INTVAL (XEXP (x, 1)));
5534 else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
5536 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
5538 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
5550 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5553 simplify_if_then_else (rtx x)
5555 enum machine_mode mode = GET_MODE (x);
5556 rtx cond = XEXP (x, 0);
5557 rtx true_rtx = XEXP (x, 1);
5558 rtx false_rtx = XEXP (x, 2);
5559 enum rtx_code true_code = GET_CODE (cond);
5560 int comparison_p = COMPARISON_P (cond);
5563 enum rtx_code false_code;
5566 /* Simplify storing of the truth value. */
5567 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
5568 return simplify_gen_relational (true_code, mode, VOIDmode,
5569 XEXP (cond, 0), XEXP (cond, 1));
5571 /* Also when the truth value has to be reversed. */
5573 && true_rtx == const0_rtx && false_rtx == const_true_rtx
5574 && (reversed = reversed_comparison (cond, mode)))
5577 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5578 in it is being compared against certain values. Get the true and false
5579 comparisons and see if that says anything about the value of each arm. */
5582 && ((false_code = reversed_comparison_code (cond, NULL))
5584 && REG_P (XEXP (cond, 0)))
5587 rtx from = XEXP (cond, 0);
5588 rtx true_val = XEXP (cond, 1);
5589 rtx false_val = true_val;
5592 /* If FALSE_CODE is EQ, swap the codes and arms. */
5594 if (false_code == EQ)
5596 swapped = 1, true_code = EQ, false_code = NE;
5597 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5600 /* If we are comparing against zero and the expression being tested has
5601 only a single bit that might be nonzero, that is its value when it is
5602 not equal to zero. Similarly if it is known to be -1 or 0. */
5604 if (true_code == EQ && true_val == const0_rtx
5605 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
5608 false_val = GEN_INT (trunc_int_for_mode (nzb, GET_MODE (from)));
5610 else if (true_code == EQ && true_val == const0_rtx
5611 && (num_sign_bit_copies (from, GET_MODE (from))
5612 == GET_MODE_BITSIZE (GET_MODE (from))))
5615 false_val = constm1_rtx;
5618 /* Now simplify an arm if we know the value of the register in the
5619 branch and it is used in the arm. Be careful due to the potential
5620 of locally-shared RTL. */
5622 if (reg_mentioned_p (from, true_rtx))
5623 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
5625 pc_rtx, pc_rtx, 0, 0);
5626 if (reg_mentioned_p (from, false_rtx))
5627 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
5629 pc_rtx, pc_rtx, 0, 0);
5631 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
5632 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
5634 true_rtx = XEXP (x, 1);
5635 false_rtx = XEXP (x, 2);
5636 true_code = GET_CODE (cond);
5639 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
5640 reversed, do so to avoid needing two sets of patterns for
5641 subtract-and-branch insns. Similarly if we have a constant in the true
5642 arm, the false arm is the same as the first operand of the comparison, or
5643 the false arm is more complicated than the true arm. */
5646 && reversed_comparison_code (cond, NULL) != UNKNOWN
5647 && (true_rtx == pc_rtx
5648 || (CONSTANT_P (true_rtx)
5649 && !CONST_INT_P (false_rtx) && false_rtx != pc_rtx)
5650 || true_rtx == const0_rtx
5651 || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
5652 || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
5653 && !OBJECT_P (false_rtx))
5654 || reg_mentioned_p (true_rtx, false_rtx)
5655 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
5657 true_code = reversed_comparison_code (cond, NULL);
5658 SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
5659 SUBST (XEXP (x, 1), false_rtx);
5660 SUBST (XEXP (x, 2), true_rtx);
5662 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5665 /* It is possible that the conditional has been simplified out. */
5666 true_code = GET_CODE (cond);
5667 comparison_p = COMPARISON_P (cond);
5670 /* If the two arms are identical, we don't need the comparison. */
5672 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
5675 /* Convert a == b ? b : a to "a". */
5676 if (true_code == EQ && ! side_effects_p (cond)
5677 && !HONOR_NANS (mode)
5678 && rtx_equal_p (XEXP (cond, 0), false_rtx)
5679 && rtx_equal_p (XEXP (cond, 1), true_rtx))
5681 else if (true_code == NE && ! side_effects_p (cond)
5682 && !HONOR_NANS (mode)
5683 && rtx_equal_p (XEXP (cond, 0), true_rtx)
5684 && rtx_equal_p (XEXP (cond, 1), false_rtx))
5687 /* Look for cases where we have (abs x) or (neg (abs X)). */
5689 if (GET_MODE_CLASS (mode) == MODE_INT
5691 && XEXP (cond, 1) == const0_rtx
5692 && GET_CODE (false_rtx) == NEG
5693 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
5694 && rtx_equal_p (true_rtx, XEXP (cond, 0))
5695 && ! side_effects_p (true_rtx))
5700 return simplify_gen_unary (ABS, mode, true_rtx, mode);
5704 simplify_gen_unary (NEG, mode,
5705 simplify_gen_unary (ABS, mode, true_rtx, mode),
5711 /* Look for MIN or MAX. */
5713 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
5715 && rtx_equal_p (XEXP (cond, 0), true_rtx)
5716 && rtx_equal_p (XEXP (cond, 1), false_rtx)
5717 && ! side_effects_p (cond))
5722 return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
5725 return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
5728 return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
5731 return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
5736 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
5737 second operand is zero, this can be done as (OP Z (mult COND C2)) where
5738 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
5739 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
5740 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
5741 neither 1 or -1, but it isn't worth checking for. */
5743 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
5745 && GET_MODE_CLASS (mode) == MODE_INT
5746 && ! side_effects_p (x))
5748 rtx t = make_compound_operation (true_rtx, SET);
5749 rtx f = make_compound_operation (false_rtx, SET);
5750 rtx cond_op0 = XEXP (cond, 0);
5751 rtx cond_op1 = XEXP (cond, 1);
5752 enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
5753 enum machine_mode m = mode;
5754 rtx z = 0, c1 = NULL_RTX;
5756 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
5757 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
5758 || GET_CODE (t) == ASHIFT
5759 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
5760 && rtx_equal_p (XEXP (t, 0), f))
5761 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
5763 /* If an identity-zero op is commutative, check whether there
5764 would be a match if we swapped the operands. */
5765 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
5766 || GET_CODE (t) == XOR)
5767 && rtx_equal_p (XEXP (t, 1), f))
5768 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
5769 else if (GET_CODE (t) == SIGN_EXTEND
5770 && (GET_CODE (XEXP (t, 0)) == PLUS
5771 || GET_CODE (XEXP (t, 0)) == MINUS
5772 || GET_CODE (XEXP (t, 0)) == IOR
5773 || GET_CODE (XEXP (t, 0)) == XOR
5774 || GET_CODE (XEXP (t, 0)) == ASHIFT
5775 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5776 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5777 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5778 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5779 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5780 && (num_sign_bit_copies (f, GET_MODE (f))
5782 (GET_MODE_BITSIZE (mode)
5783 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
5785 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5786 extend_op = SIGN_EXTEND;
5787 m = GET_MODE (XEXP (t, 0));
5789 else if (GET_CODE (t) == SIGN_EXTEND
5790 && (GET_CODE (XEXP (t, 0)) == PLUS
5791 || GET_CODE (XEXP (t, 0)) == IOR
5792 || GET_CODE (XEXP (t, 0)) == XOR)
5793 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5794 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5795 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5796 && (num_sign_bit_copies (f, GET_MODE (f))
5798 (GET_MODE_BITSIZE (mode)
5799 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
5801 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5802 extend_op = SIGN_EXTEND;
5803 m = GET_MODE (XEXP (t, 0));
5805 else if (GET_CODE (t) == ZERO_EXTEND
5806 && (GET_CODE (XEXP (t, 0)) == PLUS
5807 || GET_CODE (XEXP (t, 0)) == MINUS
5808 || GET_CODE (XEXP (t, 0)) == IOR
5809 || GET_CODE (XEXP (t, 0)) == XOR
5810 || GET_CODE (XEXP (t, 0)) == ASHIFT
5811 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5812 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5813 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5814 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5815 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5816 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5817 && ((nonzero_bits (f, GET_MODE (f))
5818 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
5821 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5822 extend_op = ZERO_EXTEND;
5823 m = GET_MODE (XEXP (t, 0));
5825 else if (GET_CODE (t) == ZERO_EXTEND
5826 && (GET_CODE (XEXP (t, 0)) == PLUS
5827 || GET_CODE (XEXP (t, 0)) == IOR
5828 || GET_CODE (XEXP (t, 0)) == XOR)
5829 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5830 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5831 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5832 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5833 && ((nonzero_bits (f, GET_MODE (f))
5834 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
5837 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5838 extend_op = ZERO_EXTEND;
5839 m = GET_MODE (XEXP (t, 0));
5844 temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
5845 cond_op0, cond_op1),
5846 pc_rtx, pc_rtx, 0, 0);
5847 temp = simplify_gen_binary (MULT, m, temp,
5848 simplify_gen_binary (MULT, m, c1,
5850 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
5851 temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
5853 if (extend_op != UNKNOWN)
5854 temp = simplify_gen_unary (extend_op, mode, temp, m);
5860 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5861 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5862 negation of a single bit, we can convert this operation to a shift. We
5863 can actually do this more generally, but it doesn't seem worth it. */
5865 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5866 && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
5867 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
5868 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
5869 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
5870 == GET_MODE_BITSIZE (mode))
5871 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
5873 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5874 gen_lowpart (mode, XEXP (cond, 0)), i);
5876 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
5877 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5878 && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
5879 && GET_MODE (XEXP (cond, 0)) == mode
5880 && (INTVAL (true_rtx) & GET_MODE_MASK (mode))
5881 == nonzero_bits (XEXP (cond, 0), mode)
5882 && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
5883 return XEXP (cond, 0);
5888 /* Simplify X, a SET expression. Return the new expression. */
5891 simplify_set (rtx x)
5893 rtx src = SET_SRC (x);
5894 rtx dest = SET_DEST (x);
5895 enum machine_mode mode
5896 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
5900 /* (set (pc) (return)) gets written as (return). */
5901 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
5904 /* Now that we know for sure which bits of SRC we are using, see if we can
5905 simplify the expression for the object knowing that we only need the
5908 if (GET_MODE_CLASS (mode) == MODE_INT
5909 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5911 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, 0);
5912 SUBST (SET_SRC (x), src);
5915 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5916 the comparison result and try to simplify it unless we already have used
5917 undobuf.other_insn. */
5918 if ((GET_MODE_CLASS (mode) == MODE_CC
5919 || GET_CODE (src) == COMPARE
5921 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5922 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5923 && COMPARISON_P (*cc_use)
5924 && rtx_equal_p (XEXP (*cc_use, 0), dest))
5926 enum rtx_code old_code = GET_CODE (*cc_use);
5927 enum rtx_code new_code;
5929 int other_changed = 0;
5930 enum machine_mode compare_mode = GET_MODE (dest);
5932 if (GET_CODE (src) == COMPARE)
5933 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5935 op0 = src, op1 = CONST0_RTX (GET_MODE (src));
5937 tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
5940 new_code = old_code;
5941 else if (!CONSTANT_P (tmp))
5943 new_code = GET_CODE (tmp);
5944 op0 = XEXP (tmp, 0);
5945 op1 = XEXP (tmp, 1);
5949 rtx pat = PATTERN (other_insn);
5950 undobuf.other_insn = other_insn;
5951 SUBST (*cc_use, tmp);
5953 /* Attempt to simplify CC user. */
5954 if (GET_CODE (pat) == SET)
5956 rtx new_rtx = simplify_rtx (SET_SRC (pat));
5957 if (new_rtx != NULL_RTX)
5958 SUBST (SET_SRC (pat), new_rtx);
5961 /* Convert X into a no-op move. */
5962 SUBST (SET_DEST (x), pc_rtx);
5963 SUBST (SET_SRC (x), pc_rtx);
5967 /* Simplify our comparison, if possible. */
5968 new_code = simplify_comparison (new_code, &op0, &op1);
5970 #ifdef SELECT_CC_MODE
5971 /* If this machine has CC modes other than CCmode, check to see if we
5972 need to use a different CC mode here. */
5973 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
5974 compare_mode = GET_MODE (op0);
5976 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5979 /* If the mode changed, we have to change SET_DEST, the mode in the
5980 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5981 a hard register, just build new versions with the proper mode. If it
5982 is a pseudo, we lose unless it is only time we set the pseudo, in
5983 which case we can safely change its mode. */
5984 if (compare_mode != GET_MODE (dest))
5986 if (can_change_dest_mode (dest, 0, compare_mode))
5988 unsigned int regno = REGNO (dest);
5991 if (regno < FIRST_PSEUDO_REGISTER)
5992 new_dest = gen_rtx_REG (compare_mode, regno);
5995 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
5996 new_dest = regno_reg_rtx[regno];
5999 SUBST (SET_DEST (x), new_dest);
6000 SUBST (XEXP (*cc_use, 0), new_dest);
6007 #endif /* SELECT_CC_MODE */
6009 /* If the code changed, we have to build a new comparison in
6010 undobuf.other_insn. */
6011 if (new_code != old_code)
6013 int other_changed_previously = other_changed;
6014 unsigned HOST_WIDE_INT mask;
6015 rtx old_cc_use = *cc_use;
6017 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
6021 /* If the only change we made was to change an EQ into an NE or
6022 vice versa, OP0 has only one bit that might be nonzero, and OP1
6023 is zero, check if changing the user of the condition code will
6024 produce a valid insn. If it won't, we can keep the original code
6025 in that insn by surrounding our operation with an XOR. */
6027 if (((old_code == NE && new_code == EQ)
6028 || (old_code == EQ && new_code == NE))
6029 && ! other_changed_previously && op1 == const0_rtx
6030 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
6031 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
6033 rtx pat = PATTERN (other_insn), note = 0;
6035 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
6036 && ! check_asm_operands (pat)))
6038 *cc_use = old_cc_use;
6041 op0 = simplify_gen_binary (XOR, GET_MODE (op0),
6042 op0, GEN_INT (mask));
6048 undobuf.other_insn = other_insn;
6050 /* Otherwise, if we didn't previously have a COMPARE in the
6051 correct mode, we need one. */
6052 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
6054 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6057 else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
6059 SUBST (SET_SRC (x), op0);
6062 /* Otherwise, update the COMPARE if needed. */
6063 else if (XEXP (src, 0) != op0 || XEXP (src, 1) != op1)
6065 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6071 /* Get SET_SRC in a form where we have placed back any
6072 compound expressions. Then do the checks below. */
6073 src = make_compound_operation (src, SET);
6074 SUBST (SET_SRC (x), src);
6077 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6078 and X being a REG or (subreg (reg)), we may be able to convert this to
6079 (set (subreg:m2 x) (op)).
6081 We can always do this if M1 is narrower than M2 because that means that
6082 we only care about the low bits of the result.
6084 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6085 perform a narrower operation than requested since the high-order bits will
6086 be undefined. On machine where it is defined, this transformation is safe
6087 as long as M1 and M2 have the same number of words. */
6089 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6090 && !OBJECT_P (SUBREG_REG (src))
6091 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
6093 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
6094 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
6095 #ifndef WORD_REGISTER_OPERATIONS
6096 && (GET_MODE_SIZE (GET_MODE (src))
6097 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
6099 #ifdef CANNOT_CHANGE_MODE_CLASS
6100 && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
6101 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
6102 GET_MODE (SUBREG_REG (src)),
6106 || (GET_CODE (dest) == SUBREG
6107 && REG_P (SUBREG_REG (dest)))))
6109 SUBST (SET_DEST (x),
6110 gen_lowpart (GET_MODE (SUBREG_REG (src)),
6112 SUBST (SET_SRC (x), SUBREG_REG (src));
6114 src = SET_SRC (x), dest = SET_DEST (x);
6118 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6121 && GET_CODE (src) == SUBREG
6122 && subreg_lowpart_p (src)
6123 && (GET_MODE_BITSIZE (GET_MODE (src))
6124 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
6126 rtx inner = SUBREG_REG (src);
6127 enum machine_mode inner_mode = GET_MODE (inner);
6129 /* Here we make sure that we don't have a sign bit on. */
6130 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
6131 && (nonzero_bits (inner, inner_mode)
6132 < ((unsigned HOST_WIDE_INT) 1
6133 << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
6135 SUBST (SET_SRC (x), inner);
6141 #ifdef LOAD_EXTEND_OP
6142 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6143 would require a paradoxical subreg. Replace the subreg with a
6144 zero_extend to avoid the reload that would otherwise be required. */
6146 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6147 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src)))
6148 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
6149 && SUBREG_BYTE (src) == 0
6150 && (GET_MODE_SIZE (GET_MODE (src))
6151 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
6152 && MEM_P (SUBREG_REG (src)))
6155 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
6156 GET_MODE (src), SUBREG_REG (src)));
6162 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6163 are comparing an item known to be 0 or -1 against 0, use a logical
6164 operation instead. Check for one of the arms being an IOR of the other
6165 arm with some value. We compute three terms to be IOR'ed together. In
6166 practice, at most two will be nonzero. Then we do the IOR's. */
6168 if (GET_CODE (dest) != PC
6169 && GET_CODE (src) == IF_THEN_ELSE
6170 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
6171 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
6172 && XEXP (XEXP (src, 0), 1) == const0_rtx
6173 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
6174 #ifdef HAVE_conditional_move
6175 && ! can_conditionally_move_p (GET_MODE (src))
6177 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
6178 GET_MODE (XEXP (XEXP (src, 0), 0)))
6179 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
6180 && ! side_effects_p (src))
6182 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
6183 ? XEXP (src, 1) : XEXP (src, 2));
6184 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
6185 ? XEXP (src, 2) : XEXP (src, 1));
6186 rtx term1 = const0_rtx, term2, term3;
6188 if (GET_CODE (true_rtx) == IOR
6189 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
6190 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
6191 else if (GET_CODE (true_rtx) == IOR
6192 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
6193 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
6194 else if (GET_CODE (false_rtx) == IOR
6195 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
6196 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
6197 else if (GET_CODE (false_rtx) == IOR
6198 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
6199 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
6201 term2 = simplify_gen_binary (AND, GET_MODE (src),
6202 XEXP (XEXP (src, 0), 0), true_rtx);
6203 term3 = simplify_gen_binary (AND, GET_MODE (src),
6204 simplify_gen_unary (NOT, GET_MODE (src),
6205 XEXP (XEXP (src, 0), 0),
6210 simplify_gen_binary (IOR, GET_MODE (src),
6211 simplify_gen_binary (IOR, GET_MODE (src),
6218 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6219 whole thing fail. */
6220 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
6222 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
6225 /* Convert this into a field assignment operation, if possible. */
6226 return make_field_assignment (x);
6229 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6233 simplify_logical (rtx x)
6235 enum machine_mode mode = GET_MODE (x);
6236 rtx op0 = XEXP (x, 0);
6237 rtx op1 = XEXP (x, 1);
6239 switch (GET_CODE (x))
6242 /* We can call simplify_and_const_int only if we don't lose
6243 any (sign) bits when converting INTVAL (op1) to
6244 "unsigned HOST_WIDE_INT". */
6245 if (CONST_INT_P (op1)
6246 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
6247 || INTVAL (op1) > 0))
6249 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
6250 if (GET_CODE (x) != AND)
6257 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6258 apply the distributive law and then the inverse distributive
6259 law to see if things simplify. */
6260 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
6262 rtx result = distribute_and_simplify_rtx (x, 0);
6266 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
6268 rtx result = distribute_and_simplify_rtx (x, 1);
6275 /* If we have (ior (and A B) C), apply the distributive law and then
6276 the inverse distributive law to see if things simplify. */
6278 if (GET_CODE (op0) == AND)
6280 rtx result = distribute_and_simplify_rtx (x, 0);
6285 if (GET_CODE (op1) == AND)
6287 rtx result = distribute_and_simplify_rtx (x, 1);
6300 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6301 operations" because they can be replaced with two more basic operations.
6302 ZERO_EXTEND is also considered "compound" because it can be replaced with
6303 an AND operation, which is simpler, though only one operation.
6305 The function expand_compound_operation is called with an rtx expression
6306 and will convert it to the appropriate shifts and AND operations,
6307 simplifying at each stage.
6309 The function make_compound_operation is called to convert an expression
6310 consisting of shifts and ANDs into the equivalent compound expression.
6311 It is the inverse of this function, loosely speaking. */
6314 expand_compound_operation (rtx x)
6316 unsigned HOST_WIDE_INT pos = 0, len;
6318 unsigned int modewidth;
6321 switch (GET_CODE (x))
6326 /* We can't necessarily use a const_int for a multiword mode;
6327 it depends on implicitly extending the value.
6328 Since we don't know the right way to extend it,
6329 we can't tell whether the implicit way is right.
6331 Even for a mode that is no wider than a const_int,
6332 we can't win, because we need to sign extend one of its bits through
6333 the rest of it, and we don't know which bit. */
6334 if (CONST_INT_P (XEXP (x, 0)))
6337 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6338 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6339 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6340 reloaded. If not for that, MEM's would very rarely be safe.
6342 Reject MODEs bigger than a word, because we might not be able
6343 to reference a two-register group starting with an arbitrary register
6344 (and currently gen_lowpart might crash for a SUBREG). */
6346 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
6349 /* Reject MODEs that aren't scalar integers because turning vector
6350 or complex modes into shifts causes problems. */
6352 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6355 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
6356 /* If the inner object has VOIDmode (the only way this can happen
6357 is if it is an ASM_OPERANDS), we can't do anything since we don't
6358 know how much masking to do. */
6367 /* ... fall through ... */
6370 /* If the operand is a CLOBBER, just return it. */
6371 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
6374 if (!CONST_INT_P (XEXP (x, 1))
6375 || !CONST_INT_P (XEXP (x, 2))
6376 || GET_MODE (XEXP (x, 0)) == VOIDmode)
6379 /* Reject MODEs that aren't scalar integers because turning vector
6380 or complex modes into shifts causes problems. */
6382 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6385 len = INTVAL (XEXP (x, 1));
6386 pos = INTVAL (XEXP (x, 2));
6388 /* This should stay within the object being extracted, fail otherwise. */
6389 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
6392 if (BITS_BIG_ENDIAN)
6393 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
6400 /* Convert sign extension to zero extension, if we know that the high
6401 bit is not set, as this is easier to optimize. It will be converted
6402 back to cheaper alternative in make_extraction. */
6403 if (GET_CODE (x) == SIGN_EXTEND
6404 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6405 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6406 & ~(((unsigned HOST_WIDE_INT)
6407 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
6411 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
6412 rtx temp2 = expand_compound_operation (temp);
6414 /* Make sure this is a profitable operation. */
6415 if (rtx_cost (x, SET, optimize_this_for_speed_p)
6416 > rtx_cost (temp2, SET, optimize_this_for_speed_p))
6418 else if (rtx_cost (x, SET, optimize_this_for_speed_p)
6419 > rtx_cost (temp, SET, optimize_this_for_speed_p))
6425 /* We can optimize some special cases of ZERO_EXTEND. */
6426 if (GET_CODE (x) == ZERO_EXTEND)
6428 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6429 know that the last value didn't have any inappropriate bits
6431 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6432 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6433 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6434 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
6435 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6436 return XEXP (XEXP (x, 0), 0);
6438 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6439 if (GET_CODE (XEXP (x, 0)) == SUBREG
6440 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6441 && subreg_lowpart_p (XEXP (x, 0))
6442 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6443 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
6444 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6445 return SUBREG_REG (XEXP (x, 0));
6447 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6448 is a comparison and STORE_FLAG_VALUE permits. This is like
6449 the first case, but it works even when GET_MODE (x) is larger
6450 than HOST_WIDE_INT. */
6451 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6452 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6453 && COMPARISON_P (XEXP (XEXP (x, 0), 0))
6454 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6455 <= HOST_BITS_PER_WIDE_INT)
6456 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
6457 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6458 return XEXP (XEXP (x, 0), 0);
6460 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6461 if (GET_CODE (XEXP (x, 0)) == SUBREG
6462 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6463 && subreg_lowpart_p (XEXP (x, 0))
6464 && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
6465 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6466 <= HOST_BITS_PER_WIDE_INT)
6467 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
6468 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6469 return SUBREG_REG (XEXP (x, 0));
6473 /* If we reach here, we want to return a pair of shifts. The inner
6474 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6475 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6476 logical depending on the value of UNSIGNEDP.
6478 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6479 converted into an AND of a shift.
6481 We must check for the case where the left shift would have a negative
6482 count. This can happen in a case like (x >> 31) & 255 on machines
6483 that can't shift by a constant. On those machines, we would first
6484 combine the shift with the AND to produce a variable-position
6485 extraction. Then the constant of 31 would be substituted in to produce
6486 a such a position. */
6488 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
6489 if (modewidth + len >= pos)
6491 enum machine_mode mode = GET_MODE (x);
6492 tem = gen_lowpart (mode, XEXP (x, 0));
6493 if (!tem || GET_CODE (tem) == CLOBBER)
6495 tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
6496 tem, modewidth - pos - len);
6497 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
6498 mode, tem, modewidth - len);
6500 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
6501 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
6502 simplify_shift_const (NULL_RTX, LSHIFTRT,
6505 ((HOST_WIDE_INT) 1 << len) - 1);
6507 /* Any other cases we can't handle. */
6510 /* If we couldn't do this for some reason, return the original
6512 if (GET_CODE (tem) == CLOBBER)
6518 /* X is a SET which contains an assignment of one object into
6519 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6520 or certain SUBREGS). If possible, convert it into a series of
6523 We half-heartedly support variable positions, but do not at all
6524 support variable lengths. */
6527 expand_field_assignment (const_rtx x)
6530 rtx pos; /* Always counts from low bit. */
6532 rtx mask, cleared, masked;
6533 enum machine_mode compute_mode;
6535 /* Loop until we find something we can't simplify. */
6538 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
6539 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
6541 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
6542 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
6543 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
6545 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
6546 && CONST_INT_P (XEXP (SET_DEST (x), 1)))
6548 inner = XEXP (SET_DEST (x), 0);
6549 len = INTVAL (XEXP (SET_DEST (x), 1));
6550 pos = XEXP (SET_DEST (x), 2);
6552 /* A constant position should stay within the width of INNER. */
6553 if (CONST_INT_P (pos)
6554 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
6557 if (BITS_BIG_ENDIAN)
6559 if (CONST_INT_P (pos))
6560 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
6562 else if (GET_CODE (pos) == MINUS
6563 && CONST_INT_P (XEXP (pos, 1))
6564 && (INTVAL (XEXP (pos, 1))
6565 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
6566 /* If position is ADJUST - X, new position is X. */
6567 pos = XEXP (pos, 0);
6569 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
6570 GEN_INT (GET_MODE_BITSIZE (
6577 /* A SUBREG between two modes that occupy the same numbers of words
6578 can be done by moving the SUBREG to the source. */
6579 else if (GET_CODE (SET_DEST (x)) == SUBREG
6580 /* We need SUBREGs to compute nonzero_bits properly. */
6581 && nonzero_sign_valid
6582 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
6583 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
6584 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
6585 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
6587 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
6589 (GET_MODE (SUBREG_REG (SET_DEST (x))),
6596 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6597 inner = SUBREG_REG (inner);
6599 compute_mode = GET_MODE (inner);
6601 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6602 if (! SCALAR_INT_MODE_P (compute_mode))
6604 enum machine_mode imode;
6606 /* Don't do anything for vector or complex integral types. */
6607 if (! FLOAT_MODE_P (compute_mode))
6610 /* Try to find an integral mode to pun with. */
6611 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
6612 if (imode == BLKmode)
6615 compute_mode = imode;
6616 inner = gen_lowpart (imode, inner);
6619 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6620 if (len >= HOST_BITS_PER_WIDE_INT)
6623 /* Now compute the equivalent expression. Make a copy of INNER
6624 for the SET_DEST in case it is a MEM into which we will substitute;
6625 we don't want shared RTL in that case. */
6626 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
6627 cleared = simplify_gen_binary (AND, compute_mode,
6628 simplify_gen_unary (NOT, compute_mode,
6629 simplify_gen_binary (ASHIFT,
6634 masked = simplify_gen_binary (ASHIFT, compute_mode,
6635 simplify_gen_binary (
6637 gen_lowpart (compute_mode, SET_SRC (x)),
6641 x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
6642 simplify_gen_binary (IOR, compute_mode,
6649 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6650 it is an RTX that represents a variable starting position; otherwise,
6651 POS is the (constant) starting bit position (counted from the LSB).
6653 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6656 IN_DEST is nonzero if this is a reference in the destination of a
6657 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6658 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6661 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6662 ZERO_EXTRACT should be built even for bits starting at bit 0.
6664 MODE is the desired mode of the result (if IN_DEST == 0).
6666 The result is an RTX for the extraction or NULL_RTX if the target
6670 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
6671 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
6672 int in_dest, int in_compare)
6674 /* This mode describes the size of the storage area
6675 to fetch the overall value from. Within that, we
6676 ignore the POS lowest bits, etc. */
6677 enum machine_mode is_mode = GET_MODE (inner);
6678 enum machine_mode inner_mode;
6679 enum machine_mode wanted_inner_mode;
6680 enum machine_mode wanted_inner_reg_mode = word_mode;
6681 enum machine_mode pos_mode = word_mode;
6682 enum machine_mode extraction_mode = word_mode;
6683 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
6685 rtx orig_pos_rtx = pos_rtx;
6686 HOST_WIDE_INT orig_pos;
6688 if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6690 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6691 consider just the QI as the memory to extract from.
6692 The subreg adds or removes high bits; its mode is
6693 irrelevant to the meaning of this extraction,
6694 since POS and LEN count from the lsb. */
6695 if (MEM_P (SUBREG_REG (inner)))
6696 is_mode = GET_MODE (SUBREG_REG (inner));
6697 inner = SUBREG_REG (inner);
6699 else if (GET_CODE (inner) == ASHIFT
6700 && CONST_INT_P (XEXP (inner, 1))
6701 && pos_rtx == 0 && pos == 0
6702 && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
6704 /* We're extracting the least significant bits of an rtx
6705 (ashift X (const_int C)), where LEN > C. Extract the
6706 least significant (LEN - C) bits of X, giving an rtx
6707 whose mode is MODE, then shift it left C times. */
6708 new_rtx = make_extraction (mode, XEXP (inner, 0),
6709 0, 0, len - INTVAL (XEXP (inner, 1)),
6710 unsignedp, in_dest, in_compare);
6712 return gen_rtx_ASHIFT (mode, new_rtx, XEXP (inner, 1));
6715 inner_mode = GET_MODE (inner);
6717 if (pos_rtx && CONST_INT_P (pos_rtx))
6718 pos = INTVAL (pos_rtx), pos_rtx = 0;
6720 /* See if this can be done without an extraction. We never can if the
6721 width of the field is not the same as that of some integer mode. For
6722 registers, we can only avoid the extraction if the position is at the
6723 low-order bit and this is either not in the destination or we have the
6724 appropriate STRICT_LOW_PART operation available.
6726 For MEM, we can avoid an extract if the field starts on an appropriate
6727 boundary and we can change the mode of the memory reference. */
6729 if (tmode != BLKmode
6730 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
6732 && (inner_mode == tmode
6734 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
6735 GET_MODE_BITSIZE (inner_mode))
6736 || reg_truncated_to_mode (tmode, inner))
6739 && have_insn_for (STRICT_LOW_PART, tmode))))
6740 || (MEM_P (inner) && pos_rtx == 0
6742 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
6743 : BITS_PER_UNIT)) == 0
6744 /* We can't do this if we are widening INNER_MODE (it
6745 may not be aligned, for one thing). */
6746 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
6747 && (inner_mode == tmode
6748 || (! mode_dependent_address_p (XEXP (inner, 0))
6749 && ! MEM_VOLATILE_P (inner))))))
6751 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6752 field. If the original and current mode are the same, we need not
6753 adjust the offset. Otherwise, we do if bytes big endian.
6755 If INNER is not a MEM, get a piece consisting of just the field
6756 of interest (in this case POS % BITS_PER_WORD must be 0). */
6760 HOST_WIDE_INT offset;
6762 /* POS counts from lsb, but make OFFSET count in memory order. */
6763 if (BYTES_BIG_ENDIAN)
6764 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6766 offset = pos / BITS_PER_UNIT;
6768 new_rtx = adjust_address_nv (inner, tmode, offset);
6770 else if (REG_P (inner))
6772 if (tmode != inner_mode)
6774 /* We can't call gen_lowpart in a DEST since we
6775 always want a SUBREG (see below) and it would sometimes
6776 return a new hard register. */
6779 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6781 if (WORDS_BIG_ENDIAN
6782 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6783 final_word = ((GET_MODE_SIZE (inner_mode)
6784 - GET_MODE_SIZE (tmode))
6785 / UNITS_PER_WORD) - final_word;
6787 final_word *= UNITS_PER_WORD;
6788 if (BYTES_BIG_ENDIAN &&
6789 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6790 final_word += (GET_MODE_SIZE (inner_mode)
6791 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6793 /* Avoid creating invalid subregs, for example when
6794 simplifying (x>>32)&255. */
6795 if (!validate_subreg (tmode, inner_mode, inner, final_word))
6798 new_rtx = gen_rtx_SUBREG (tmode, inner, final_word);
6801 new_rtx = gen_lowpart (tmode, inner);
6807 new_rtx = force_to_mode (inner, tmode,
6808 len >= HOST_BITS_PER_WIDE_INT
6809 ? ~(unsigned HOST_WIDE_INT) 0
6810 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6813 /* If this extraction is going into the destination of a SET,
6814 make a STRICT_LOW_PART unless we made a MEM. */
6817 return (MEM_P (new_rtx) ? new_rtx
6818 : (GET_CODE (new_rtx) != SUBREG
6819 ? gen_rtx_CLOBBER (tmode, const0_rtx)
6820 : gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx)));
6825 if (CONST_INT_P (new_rtx)
6826 || GET_CODE (new_rtx) == CONST_DOUBLE)
6827 return simplify_unary_operation (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6828 mode, new_rtx, tmode);
6830 /* If we know that no extraneous bits are set, and that the high
6831 bit is not set, convert the extraction to the cheaper of
6832 sign and zero extension, that are equivalent in these cases. */
6833 if (flag_expensive_optimizations
6834 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6835 && ((nonzero_bits (new_rtx, tmode)
6836 & ~(((unsigned HOST_WIDE_INT)
6837 GET_MODE_MASK (tmode))
6841 rtx temp = gen_rtx_ZERO_EXTEND (mode, new_rtx);
6842 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new_rtx);
6844 /* Prefer ZERO_EXTENSION, since it gives more information to
6846 if (rtx_cost (temp, SET, optimize_this_for_speed_p)
6847 <= rtx_cost (temp1, SET, optimize_this_for_speed_p))
6852 /* Otherwise, sign- or zero-extend unless we already are in the
6855 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6859 /* Unless this is a COMPARE or we have a funny memory reference,
6860 don't do anything with zero-extending field extracts starting at
6861 the low-order bit since they are simple AND operations. */
6862 if (pos_rtx == 0 && pos == 0 && ! in_dest
6863 && ! in_compare && unsignedp)
6866 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
6867 if the position is not a constant and the length is not 1. In all
6868 other cases, we would only be going outside our object in cases when
6869 an original shift would have been undefined. */
6871 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6872 || (pos_rtx != 0 && len != 1)))
6875 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6876 and the mode for the result. */
6877 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6879 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6880 pos_mode = mode_for_extraction (EP_insv, 2);
6881 extraction_mode = mode_for_extraction (EP_insv, 3);
6884 if (! in_dest && unsignedp
6885 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6887 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6888 pos_mode = mode_for_extraction (EP_extzv, 3);
6889 extraction_mode = mode_for_extraction (EP_extzv, 0);
6892 if (! in_dest && ! unsignedp
6893 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6895 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6896 pos_mode = mode_for_extraction (EP_extv, 3);
6897 extraction_mode = mode_for_extraction (EP_extv, 0);
6900 /* Never narrow an object, since that might not be safe. */
6902 if (mode != VOIDmode
6903 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6904 extraction_mode = mode;
6906 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6907 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6908 pos_mode = GET_MODE (pos_rtx);
6910 /* If this is not from memory, the desired mode is the preferred mode
6911 for an extraction pattern's first input operand, or word_mode if there
6914 wanted_inner_mode = wanted_inner_reg_mode;
6917 /* Be careful not to go beyond the extracted object and maintain the
6918 natural alignment of the memory. */
6919 wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
6920 while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
6921 > GET_MODE_BITSIZE (wanted_inner_mode))
6923 wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
6924 gcc_assert (wanted_inner_mode != VOIDmode);
6927 /* If we have to change the mode of memory and cannot, the desired mode
6928 is EXTRACTION_MODE. */
6929 if (inner_mode != wanted_inner_mode
6930 && (mode_dependent_address_p (XEXP (inner, 0))
6931 || MEM_VOLATILE_P (inner)
6933 wanted_inner_mode = extraction_mode;
6938 if (BITS_BIG_ENDIAN)
6940 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6941 BITS_BIG_ENDIAN style. If position is constant, compute new
6942 position. Otherwise, build subtraction.
6943 Note that POS is relative to the mode of the original argument.
6944 If it's a MEM we need to recompute POS relative to that.
6945 However, if we're extracting from (or inserting into) a register,
6946 we want to recompute POS relative to wanted_inner_mode. */
6947 int width = (MEM_P (inner)
6948 ? GET_MODE_BITSIZE (is_mode)
6949 : GET_MODE_BITSIZE (wanted_inner_mode));
6952 pos = width - len - pos;
6955 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6956 /* POS may be less than 0 now, but we check for that below.
6957 Note that it can only be less than 0 if !MEM_P (inner). */
6960 /* If INNER has a wider mode, and this is a constant extraction, try to
6961 make it smaller and adjust the byte to point to the byte containing
6963 if (wanted_inner_mode != VOIDmode
6964 && inner_mode != wanted_inner_mode
6966 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6968 && ! mode_dependent_address_p (XEXP (inner, 0))
6969 && ! MEM_VOLATILE_P (inner))
6973 /* The computations below will be correct if the machine is big
6974 endian in both bits and bytes or little endian in bits and bytes.
6975 If it is mixed, we must adjust. */
6977 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6978 adjust OFFSET to compensate. */
6979 if (BYTES_BIG_ENDIAN
6980 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6981 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6983 /* We can now move to the desired byte. */
6984 offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
6985 * GET_MODE_SIZE (wanted_inner_mode);
6986 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6988 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6989 && is_mode != wanted_inner_mode)
6990 offset = (GET_MODE_SIZE (is_mode)
6991 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6993 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6996 /* If INNER is not memory, get it into the proper mode. If we are changing
6997 its mode, POS must be a constant and smaller than the size of the new
6999 else if (!MEM_P (inner))
7001 /* On the LHS, don't create paradoxical subregs implicitely truncating
7002 the register unless TRULY_NOOP_TRUNCATION. */
7004 && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE (inner)),
7005 GET_MODE_BITSIZE (wanted_inner_mode)))
7008 if (GET_MODE (inner) != wanted_inner_mode
7010 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
7016 inner = force_to_mode (inner, wanted_inner_mode,
7018 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
7019 ? ~(unsigned HOST_WIDE_INT) 0
7020 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
7025 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7026 have to zero extend. Otherwise, we can just use a SUBREG. */
7028 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
7030 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
7032 /* If we know that no extraneous bits are set, and that the high
7033 bit is not set, convert extraction to cheaper one - either
7034 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7036 if (flag_expensive_optimizations
7037 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
7038 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
7039 & ~(((unsigned HOST_WIDE_INT)
7040 GET_MODE_MASK (GET_MODE (pos_rtx)))
7044 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
7046 /* Prefer ZERO_EXTENSION, since it gives more information to
7048 if (rtx_cost (temp1, SET, optimize_this_for_speed_p)
7049 < rtx_cost (temp, SET, optimize_this_for_speed_p))
7054 else if (pos_rtx != 0
7055 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
7056 pos_rtx = gen_lowpart (pos_mode, pos_rtx);
7058 /* Make POS_RTX unless we already have it and it is correct. If we don't
7059 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7061 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
7062 pos_rtx = orig_pos_rtx;
7064 else if (pos_rtx == 0)
7065 pos_rtx = GEN_INT (pos);
7067 /* Make the required operation. See if we can use existing rtx. */
7068 new_rtx = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
7069 extraction_mode, inner, GEN_INT (len), pos_rtx);
7071 new_rtx = gen_lowpart (mode, new_rtx);
7076 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7077 with any other operations in X. Return X without that shift if so. */
7080 extract_left_shift (rtx x, int count)
7082 enum rtx_code code = GET_CODE (x);
7083 enum machine_mode mode = GET_MODE (x);
7089 /* This is the shift itself. If it is wide enough, we will return
7090 either the value being shifted if the shift count is equal to
7091 COUNT or a shift for the difference. */
7092 if (CONST_INT_P (XEXP (x, 1))
7093 && INTVAL (XEXP (x, 1)) >= count)
7094 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
7095 INTVAL (XEXP (x, 1)) - count);
7099 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7100 return simplify_gen_unary (code, mode, tem, mode);
7104 case PLUS: case IOR: case XOR: case AND:
7105 /* If we can safely shift this constant and we find the inner shift,
7106 make a new operation. */
7107 if (CONST_INT_P (XEXP (x, 1))
7108 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
7109 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7110 return simplify_gen_binary (code, mode, tem,
7111 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
7122 /* Look at the expression rooted at X. Look for expressions
7123 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7124 Form these expressions.
7126 Return the new rtx, usually just X.
7128 Also, for machines like the VAX that don't have logical shift insns,
7129 try to convert logical to arithmetic shift operations in cases where
7130 they are equivalent. This undoes the canonicalizations to logical
7131 shifts done elsewhere.
7133 We try, as much as possible, to re-use rtl expressions to save memory.
7135 IN_CODE says what kind of expression we are processing. Normally, it is
7136 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
7137 being kludges), it is MEM. When processing the arguments of a comparison
7138 or a COMPARE against zero, it is COMPARE. */
7141 make_compound_operation (rtx x, enum rtx_code in_code)
7143 enum rtx_code code = GET_CODE (x);
7144 enum machine_mode mode = GET_MODE (x);
7145 int mode_width = GET_MODE_BITSIZE (mode);
7147 enum rtx_code next_code;
7153 /* Select the code to be used in recursive calls. Once we are inside an
7154 address, we stay there. If we have a comparison, set to COMPARE,
7155 but once inside, go back to our default of SET. */
7157 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
7158 : ((code == COMPARE || COMPARISON_P (x))
7159 && XEXP (x, 1) == const0_rtx) ? COMPARE
7160 : in_code == COMPARE ? SET : in_code);
7162 /* Process depending on the code of this operation. If NEW is set
7163 nonzero, it will be returned. */
7168 /* Convert shifts by constants into multiplications if inside
7170 if (in_code == MEM && CONST_INT_P (XEXP (x, 1))
7171 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7172 && INTVAL (XEXP (x, 1)) >= 0)
7174 new_rtx = make_compound_operation (XEXP (x, 0), next_code);
7175 new_rtx = gen_rtx_MULT (mode, new_rtx,
7176 GEN_INT ((HOST_WIDE_INT) 1
7177 << INTVAL (XEXP (x, 1))));
7182 /* If the second operand is not a constant, we can't do anything
7184 if (!CONST_INT_P (XEXP (x, 1)))
7187 /* If the constant is a power of two minus one and the first operand
7188 is a logical right shift, make an extraction. */
7189 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7190 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
7192 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7193 new_rtx = make_extraction (mode, new_rtx, 0, XEXP (XEXP (x, 0), 1), i, 1,
7194 0, in_code == COMPARE);
7197 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7198 else if (GET_CODE (XEXP (x, 0)) == SUBREG
7199 && subreg_lowpart_p (XEXP (x, 0))
7200 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
7201 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
7203 new_rtx = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
7205 new_rtx = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new_rtx, 0,
7206 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
7207 0, in_code == COMPARE);
7209 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7210 else if ((GET_CODE (XEXP (x, 0)) == XOR
7211 || GET_CODE (XEXP (x, 0)) == IOR)
7212 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
7213 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
7214 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
7216 /* Apply the distributive law, and then try to make extractions. */
7217 new_rtx = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
7218 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
7220 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
7222 new_rtx = make_compound_operation (new_rtx, in_code);
7225 /* If we are have (and (rotate X C) M) and C is larger than the number
7226 of bits in M, this is an extraction. */
7228 else if (GET_CODE (XEXP (x, 0)) == ROTATE
7229 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7230 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
7231 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
7233 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7234 new_rtx = make_extraction (mode, new_rtx,
7235 (GET_MODE_BITSIZE (mode)
7236 - INTVAL (XEXP (XEXP (x, 0), 1))),
7237 NULL_RTX, i, 1, 0, in_code == COMPARE);
7240 /* On machines without logical shifts, if the operand of the AND is
7241 a logical shift and our mask turns off all the propagated sign
7242 bits, we can replace the logical shift with an arithmetic shift. */
7243 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7244 && !have_insn_for (LSHIFTRT, mode)
7245 && have_insn_for (ASHIFTRT, mode)
7246 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7247 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7248 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7249 && mode_width <= HOST_BITS_PER_WIDE_INT)
7251 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
7253 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
7254 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
7256 gen_rtx_ASHIFTRT (mode,
7257 make_compound_operation
7258 (XEXP (XEXP (x, 0), 0), next_code),
7259 XEXP (XEXP (x, 0), 1)));
7262 /* If the constant is one less than a power of two, this might be
7263 representable by an extraction even if no shift is present.
7264 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7265 we are in a COMPARE. */
7266 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
7267 new_rtx = make_extraction (mode,
7268 make_compound_operation (XEXP (x, 0),
7270 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
7272 /* If we are in a comparison and this is an AND with a power of two,
7273 convert this into the appropriate bit extract. */
7274 else if (in_code == COMPARE
7275 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
7276 new_rtx = make_extraction (mode,
7277 make_compound_operation (XEXP (x, 0),
7279 i, NULL_RTX, 1, 1, 0, 1);
7284 /* If the sign bit is known to be zero, replace this with an
7285 arithmetic shift. */
7286 if (have_insn_for (ASHIFTRT, mode)
7287 && ! have_insn_for (LSHIFTRT, mode)
7288 && mode_width <= HOST_BITS_PER_WIDE_INT
7289 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
7291 new_rtx = gen_rtx_ASHIFTRT (mode,
7292 make_compound_operation (XEXP (x, 0),
7298 /* ... fall through ... */
7304 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7305 this is a SIGN_EXTRACT. */
7306 if (CONST_INT_P (rhs)
7307 && GET_CODE (lhs) == ASHIFT
7308 && CONST_INT_P (XEXP (lhs, 1))
7309 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))
7310 && INTVAL (rhs) < mode_width)
7312 new_rtx = make_compound_operation (XEXP (lhs, 0), next_code);
7313 new_rtx = make_extraction (mode, new_rtx,
7314 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
7315 NULL_RTX, mode_width - INTVAL (rhs),
7316 code == LSHIFTRT, 0, in_code == COMPARE);
7320 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7321 If so, try to merge the shifts into a SIGN_EXTEND. We could
7322 also do this for some cases of SIGN_EXTRACT, but it doesn't
7323 seem worth the effort; the case checked for occurs on Alpha. */
7326 && ! (GET_CODE (lhs) == SUBREG
7327 && (OBJECT_P (SUBREG_REG (lhs))))
7328 && CONST_INT_P (rhs)
7329 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
7330 && INTVAL (rhs) < mode_width
7331 && (new_rtx = extract_left_shift (lhs, INTVAL (rhs))) != 0)
7332 new_rtx = make_extraction (mode, make_compound_operation (new_rtx, next_code),
7333 0, NULL_RTX, mode_width - INTVAL (rhs),
7334 code == LSHIFTRT, 0, in_code == COMPARE);
7339 /* Call ourselves recursively on the inner expression. If we are
7340 narrowing the object and it has a different RTL code from
7341 what it originally did, do this SUBREG as a force_to_mode. */
7343 tem = make_compound_operation (SUBREG_REG (x), in_code);
7346 rtx simplified = simplify_subreg (mode, tem, GET_MODE (SUBREG_REG (x)),
7352 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
7353 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))
7354 && subreg_lowpart_p (x))
7356 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
7359 /* If we have something other than a SUBREG, we might have
7360 done an expansion, so rerun ourselves. */
7361 if (GET_CODE (newer) != SUBREG)
7362 newer = make_compound_operation (newer, in_code);
7364 /* force_to_mode can expand compounds. If it just re-expanded the
7365 compound use gen_lowpart instead to convert to the desired
7367 if (rtx_equal_p (newer, x))
7368 return gen_lowpart (GET_MODE (x), tem);
7384 x = gen_lowpart (mode, new_rtx);
7385 code = GET_CODE (x);
7388 /* Now recursively process each operand of this operation. */
7389 fmt = GET_RTX_FORMAT (code);
7390 for (i = 0; i < GET_RTX_LENGTH (code); i++)
7393 new_rtx = make_compound_operation (XEXP (x, i), next_code);
7394 SUBST (XEXP (x, i), new_rtx);
7396 else if (fmt[i] == 'E')
7397 for (j = 0; j < XVECLEN (x, i); j++)
7399 new_rtx = make_compound_operation (XVECEXP (x, i, j), next_code);
7400 SUBST (XVECEXP (x, i, j), new_rtx);
7403 /* If this is a commutative operation, the changes to the operands
7404 may have made it noncanonical. */
7405 if (COMMUTATIVE_ARITH_P (x)
7406 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
7409 SUBST (XEXP (x, 0), XEXP (x, 1));
7410 SUBST (XEXP (x, 1), tem);
7416 /* Given M see if it is a value that would select a field of bits
7417 within an item, but not the entire word. Return -1 if not.
7418 Otherwise, return the starting position of the field, where 0 is the
7421 *PLEN is set to the length of the field. */
7424 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
7426 /* Get the bit number of the first 1 bit from the right, -1 if none. */
7427 int pos = exact_log2 (m & -m);
7431 /* Now shift off the low-order zero bits and see if we have a
7432 power of two minus 1. */
7433 len = exact_log2 ((m >> pos) + 1);
7442 /* If X refers to a register that equals REG in value, replace these
7443 references with REG. */
7445 canon_reg_for_combine (rtx x, rtx reg)
7452 enum rtx_code code = GET_CODE (x);
7453 switch (GET_RTX_CLASS (code))
7456 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7457 if (op0 != XEXP (x, 0))
7458 return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
7463 case RTX_COMM_ARITH:
7464 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7465 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7466 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7467 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
7471 case RTX_COMM_COMPARE:
7472 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7473 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7474 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7475 return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
7476 GET_MODE (op0), op0, op1);
7480 case RTX_BITFIELD_OPS:
7481 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7482 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7483 op2 = canon_reg_for_combine (XEXP (x, 2), reg);
7484 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
7485 return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
7486 GET_MODE (op0), op0, op1, op2);
7491 if (rtx_equal_p (get_last_value (reg), x)
7492 || rtx_equal_p (reg, get_last_value (x)))
7501 fmt = GET_RTX_FORMAT (code);
7503 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7506 rtx op = canon_reg_for_combine (XEXP (x, i), reg);
7507 if (op != XEXP (x, i))
7517 else if (fmt[i] == 'E')
7520 for (j = 0; j < XVECLEN (x, i); j++)
7522 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
7523 if (op != XVECEXP (x, i, j))
7530 XVECEXP (x, i, j) = op;
7541 /* Return X converted to MODE. If the value is already truncated to
7542 MODE we can just return a subreg even though in the general case we
7543 would need an explicit truncation. */
7546 gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
7548 if (!CONST_INT_P (x)
7549 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
7550 && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
7551 GET_MODE_BITSIZE (GET_MODE (x)))
7552 && !(REG_P (x) && reg_truncated_to_mode (mode, x)))
7554 /* Bit-cast X into an integer mode. */
7555 if (!SCALAR_INT_MODE_P (GET_MODE (x)))
7556 x = gen_lowpart (int_mode_for_mode (GET_MODE (x)), x);
7557 x = simplify_gen_unary (TRUNCATE, int_mode_for_mode (mode),
7561 return gen_lowpart (mode, x);
7564 /* See if X can be simplified knowing that we will only refer to it in
7565 MODE and will only refer to those bits that are nonzero in MASK.
7566 If other bits are being computed or if masking operations are done
7567 that select a superset of the bits in MASK, they can sometimes be
7570 Return a possibly simplified expression, but always convert X to
7571 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
7573 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
7574 are all off in X. This is used when X will be complemented, by either
7575 NOT, NEG, or XOR. */
7578 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
7581 enum rtx_code code = GET_CODE (x);
7582 int next_select = just_select || code == XOR || code == NOT || code == NEG;
7583 enum machine_mode op_mode;
7584 unsigned HOST_WIDE_INT fuller_mask, nonzero;
7587 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
7588 code below will do the wrong thing since the mode of such an
7589 expression is VOIDmode.
7591 Also do nothing if X is a CLOBBER; this can happen if X was
7592 the return value from a call to gen_lowpart. */
7593 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
7596 /* We want to perform the operation is its present mode unless we know
7597 that the operation is valid in MODE, in which case we do the operation
7599 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
7600 && have_insn_for (code, mode))
7601 ? mode : GET_MODE (x));
7603 /* It is not valid to do a right-shift in a narrower mode
7604 than the one it came in with. */
7605 if ((code == LSHIFTRT || code == ASHIFTRT)
7606 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
7607 op_mode = GET_MODE (x);
7609 /* Truncate MASK to fit OP_MODE. */
7611 mask &= GET_MODE_MASK (op_mode);
7613 /* When we have an arithmetic operation, or a shift whose count we
7614 do not know, we need to assume that all bits up to the highest-order
7615 bit in MASK will be needed. This is how we form such a mask. */
7616 if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
7617 fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
7619 fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
7622 /* Determine what bits of X are guaranteed to be (non)zero. */
7623 nonzero = nonzero_bits (x, mode);
7625 /* If none of the bits in X are needed, return a zero. */
7626 if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
7629 /* If X is a CONST_INT, return a new one. Do this here since the
7630 test below will fail. */
7631 if (CONST_INT_P (x))
7633 if (SCALAR_INT_MODE_P (mode))
7634 return gen_int_mode (INTVAL (x) & mask, mode);
7637 x = GEN_INT (INTVAL (x) & mask);
7638 return gen_lowpart_common (mode, x);
7642 /* If X is narrower than MODE and we want all the bits in X's mode, just
7643 get X in the proper mode. */
7644 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
7645 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
7646 return gen_lowpart (mode, x);
7648 /* We can ignore the effect of a SUBREG if it narrows the mode or
7649 if the constant masks to zero all the bits the mode doesn't have. */
7650 if (GET_CODE (x) == SUBREG
7651 && subreg_lowpart_p (x)
7652 && ((GET_MODE_SIZE (GET_MODE (x))
7653 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7655 & GET_MODE_MASK (GET_MODE (x))
7656 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
7657 return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
7659 /* The arithmetic simplifications here only work for scalar integer modes. */
7660 if (!SCALAR_INT_MODE_P (mode) || !SCALAR_INT_MODE_P (GET_MODE (x)))
7661 return gen_lowpart_or_truncate (mode, x);
7666 /* If X is a (clobber (const_int)), return it since we know we are
7667 generating something that won't match. */
7674 x = expand_compound_operation (x);
7675 if (GET_CODE (x) != code)
7676 return force_to_mode (x, mode, mask, next_select);
7680 /* Similarly for a truncate. */
7681 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7684 /* If this is an AND with a constant, convert it into an AND
7685 whose constant is the AND of that constant with MASK. If it
7686 remains an AND of MASK, delete it since it is redundant. */
7688 if (CONST_INT_P (XEXP (x, 1)))
7690 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
7691 mask & INTVAL (XEXP (x, 1)));
7693 /* If X is still an AND, see if it is an AND with a mask that
7694 is just some low-order bits. If so, and it is MASK, we don't
7697 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
7698 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
7702 /* If it remains an AND, try making another AND with the bits
7703 in the mode mask that aren't in MASK turned on. If the
7704 constant in the AND is wide enough, this might make a
7705 cheaper constant. */
7707 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
7708 && GET_MODE_MASK (GET_MODE (x)) != mask
7709 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
7711 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
7712 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
7713 int width = GET_MODE_BITSIZE (GET_MODE (x));
7716 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
7717 number, sign extend it. */
7718 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
7719 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7720 cval |= (HOST_WIDE_INT) -1 << width;
7722 y = simplify_gen_binary (AND, GET_MODE (x),
7723 XEXP (x, 0), GEN_INT (cval));
7724 if (rtx_cost (y, SET, optimize_this_for_speed_p)
7725 < rtx_cost (x, SET, optimize_this_for_speed_p))
7735 /* In (and (plus FOO C1) M), if M is a mask that just turns off
7736 low-order bits (as in an alignment operation) and FOO is already
7737 aligned to that boundary, mask C1 to that boundary as well.
7738 This may eliminate that PLUS and, later, the AND. */
7741 unsigned int width = GET_MODE_BITSIZE (mode);
7742 unsigned HOST_WIDE_INT smask = mask;
7744 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
7745 number, sign extend it. */
7747 if (width < HOST_BITS_PER_WIDE_INT
7748 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7749 smask |= (HOST_WIDE_INT) -1 << width;
7751 if (CONST_INT_P (XEXP (x, 1))
7752 && exact_log2 (- smask) >= 0
7753 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
7754 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
7755 return force_to_mode (plus_constant (XEXP (x, 0),
7756 (INTVAL (XEXP (x, 1)) & smask)),
7757 mode, smask, next_select);
7760 /* ... fall through ... */
7763 /* For PLUS, MINUS and MULT, we need any bits less significant than the
7764 most significant bit in MASK since carries from those bits will
7765 affect the bits we are interested in. */
7770 /* If X is (minus C Y) where C's least set bit is larger than any bit
7771 in the mask, then we may replace with (neg Y). */
7772 if (CONST_INT_P (XEXP (x, 0))
7773 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
7774 & -INTVAL (XEXP (x, 0))))
7777 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
7779 return force_to_mode (x, mode, mask, next_select);
7782 /* Similarly, if C contains every bit in the fuller_mask, then we may
7783 replace with (not Y). */
7784 if (CONST_INT_P (XEXP (x, 0))
7785 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
7786 == INTVAL (XEXP (x, 0))))
7788 x = simplify_gen_unary (NOT, GET_MODE (x),
7789 XEXP (x, 1), GET_MODE (x));
7790 return force_to_mode (x, mode, mask, next_select);
7798 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7799 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7800 operation which may be a bitfield extraction. Ensure that the
7801 constant we form is not wider than the mode of X. */
7803 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7804 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7805 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7806 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7807 && CONST_INT_P (XEXP (x, 1))
7808 && ((INTVAL (XEXP (XEXP (x, 0), 1))
7809 + floor_log2 (INTVAL (XEXP (x, 1))))
7810 < GET_MODE_BITSIZE (GET_MODE (x)))
7811 && (INTVAL (XEXP (x, 1))
7812 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
7814 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
7815 << INTVAL (XEXP (XEXP (x, 0), 1)));
7816 temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
7817 XEXP (XEXP (x, 0), 0), temp);
7818 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
7819 XEXP (XEXP (x, 0), 1));
7820 return force_to_mode (x, mode, mask, next_select);
7824 /* For most binary operations, just propagate into the operation and
7825 change the mode if we have an operation of that mode. */
7827 op0 = force_to_mode (XEXP (x, 0), mode, mask, next_select);
7828 op1 = force_to_mode (XEXP (x, 1), mode, mask, next_select);
7830 /* If we ended up truncating both operands, truncate the result of the
7831 operation instead. */
7832 if (GET_CODE (op0) == TRUNCATE
7833 && GET_CODE (op1) == TRUNCATE)
7835 op0 = XEXP (op0, 0);
7836 op1 = XEXP (op1, 0);
7839 op0 = gen_lowpart_or_truncate (op_mode, op0);
7840 op1 = gen_lowpart_or_truncate (op_mode, op1);
7842 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7843 x = simplify_gen_binary (code, op_mode, op0, op1);
7847 /* For left shifts, do the same, but just for the first operand.
7848 However, we cannot do anything with shifts where we cannot
7849 guarantee that the counts are smaller than the size of the mode
7850 because such a count will have a different meaning in a
7853 if (! (CONST_INT_P (XEXP (x, 1))
7854 && INTVAL (XEXP (x, 1)) >= 0
7855 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
7856 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
7857 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
7858 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
7861 /* If the shift count is a constant and we can do arithmetic in
7862 the mode of the shift, refine which bits we need. Otherwise, use the
7863 conservative form of the mask. */
7864 if (CONST_INT_P (XEXP (x, 1))
7865 && INTVAL (XEXP (x, 1)) >= 0
7866 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
7867 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7868 mask >>= INTVAL (XEXP (x, 1));
7872 op0 = gen_lowpart_or_truncate (op_mode,
7873 force_to_mode (XEXP (x, 0), op_mode,
7874 mask, next_select));
7876 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7877 x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
7881 /* Here we can only do something if the shift count is a constant,
7882 this shift constant is valid for the host, and we can do arithmetic
7885 if (CONST_INT_P (XEXP (x, 1))
7886 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7887 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7889 rtx inner = XEXP (x, 0);
7890 unsigned HOST_WIDE_INT inner_mask;
7892 /* Select the mask of the bits we need for the shift operand. */
7893 inner_mask = mask << INTVAL (XEXP (x, 1));
7895 /* We can only change the mode of the shift if we can do arithmetic
7896 in the mode of the shift and INNER_MASK is no wider than the
7897 width of X's mode. */
7898 if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
7899 op_mode = GET_MODE (x);
7901 inner = force_to_mode (inner, op_mode, inner_mask, next_select);
7903 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7904 x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7907 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7908 shift and AND produces only copies of the sign bit (C2 is one less
7909 than a power of two), we can do this with just a shift. */
7911 if (GET_CODE (x) == LSHIFTRT
7912 && CONST_INT_P (XEXP (x, 1))
7913 /* The shift puts one of the sign bit copies in the least significant
7915 && ((INTVAL (XEXP (x, 1))
7916 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7917 >= GET_MODE_BITSIZE (GET_MODE (x)))
7918 && exact_log2 (mask + 1) >= 0
7919 /* Number of bits left after the shift must be more than the mask
7921 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7922 <= GET_MODE_BITSIZE (GET_MODE (x)))
7923 /* Must be more sign bit copies than the mask needs. */
7924 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7925 >= exact_log2 (mask + 1)))
7926 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7927 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7928 - exact_log2 (mask + 1)));
7933 /* If we are just looking for the sign bit, we don't need this shift at
7934 all, even if it has a variable count. */
7935 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7936 && (mask == ((unsigned HOST_WIDE_INT) 1
7937 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7938 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7940 /* If this is a shift by a constant, get a mask that contains those bits
7941 that are not copies of the sign bit. We then have two cases: If
7942 MASK only includes those bits, this can be a logical shift, which may
7943 allow simplifications. If MASK is a single-bit field not within
7944 those bits, we are requesting a copy of the sign bit and hence can
7945 shift the sign bit to the appropriate location. */
7947 if (CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) >= 0
7948 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7952 /* If the considered data is wider than HOST_WIDE_INT, we can't
7953 represent a mask for all its bits in a single scalar.
7954 But we only care about the lower bits, so calculate these. */
7956 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7958 nonzero = ~(HOST_WIDE_INT) 0;
7960 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7961 is the number of bits a full-width mask would have set.
7962 We need only shift if these are fewer than nonzero can
7963 hold. If not, we must keep all bits set in nonzero. */
7965 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7966 < HOST_BITS_PER_WIDE_INT)
7967 nonzero >>= INTVAL (XEXP (x, 1))
7968 + HOST_BITS_PER_WIDE_INT
7969 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7973 nonzero = GET_MODE_MASK (GET_MODE (x));
7974 nonzero >>= INTVAL (XEXP (x, 1));
7977 if ((mask & ~nonzero) == 0)
7979 x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
7980 XEXP (x, 0), INTVAL (XEXP (x, 1)));
7981 if (GET_CODE (x) != ASHIFTRT)
7982 return force_to_mode (x, mode, mask, next_select);
7985 else if ((i = exact_log2 (mask)) >= 0)
7987 x = simplify_shift_const
7988 (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7989 GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7991 if (GET_CODE (x) != ASHIFTRT)
7992 return force_to_mode (x, mode, mask, next_select);
7996 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7997 even if the shift count isn't a constant. */
7999 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8000 XEXP (x, 0), XEXP (x, 1));
8004 /* If this is a zero- or sign-extension operation that just affects bits
8005 we don't care about, remove it. Be sure the call above returned
8006 something that is still a shift. */
8008 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
8009 && CONST_INT_P (XEXP (x, 1))
8010 && INTVAL (XEXP (x, 1)) >= 0
8011 && (INTVAL (XEXP (x, 1))
8012 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
8013 && GET_CODE (XEXP (x, 0)) == ASHIFT
8014 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
8015 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
8022 /* If the shift count is constant and we can do computations
8023 in the mode of X, compute where the bits we care about are.
8024 Otherwise, we can't do anything. Don't change the mode of
8025 the shift or propagate MODE into the shift, though. */
8026 if (CONST_INT_P (XEXP (x, 1))
8027 && INTVAL (XEXP (x, 1)) >= 0)
8029 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
8030 GET_MODE (x), GEN_INT (mask),
8032 if (temp && CONST_INT_P (temp))
8034 force_to_mode (XEXP (x, 0), GET_MODE (x),
8035 INTVAL (temp), next_select));
8040 /* If we just want the low-order bit, the NEG isn't needed since it
8041 won't change the low-order bit. */
8043 return force_to_mode (XEXP (x, 0), mode, mask, just_select);
8045 /* We need any bits less significant than the most significant bit in
8046 MASK since carries from those bits will affect the bits we are
8052 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8053 same as the XOR case above. Ensure that the constant we form is not
8054 wider than the mode of X. */
8056 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8057 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8058 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8059 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
8060 < GET_MODE_BITSIZE (GET_MODE (x)))
8061 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
8063 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
8065 temp = simplify_gen_binary (XOR, GET_MODE (x),
8066 XEXP (XEXP (x, 0), 0), temp);
8067 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8068 temp, XEXP (XEXP (x, 0), 1));
8070 return force_to_mode (x, mode, mask, next_select);
8073 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8074 use the full mask inside the NOT. */
8078 op0 = gen_lowpart_or_truncate (op_mode,
8079 force_to_mode (XEXP (x, 0), mode, mask,
8081 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8082 x = simplify_gen_unary (code, op_mode, op0, op_mode);
8086 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8087 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8088 which is equal to STORE_FLAG_VALUE. */
8089 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
8090 && GET_MODE (XEXP (x, 0)) == mode
8091 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
8092 && (nonzero_bits (XEXP (x, 0), mode)
8093 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
8094 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8099 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8100 written in a narrower mode. We play it safe and do not do so. */
8103 gen_lowpart_or_truncate (GET_MODE (x),
8104 force_to_mode (XEXP (x, 1), mode,
8105 mask, next_select)));
8107 gen_lowpart_or_truncate (GET_MODE (x),
8108 force_to_mode (XEXP (x, 2), mode,
8109 mask, next_select)));
8116 /* Ensure we return a value of the proper mode. */
8117 return gen_lowpart_or_truncate (mode, x);
8120 /* Return nonzero if X is an expression that has one of two values depending on
8121 whether some other value is zero or nonzero. In that case, we return the
8122 value that is being tested, *PTRUE is set to the value if the rtx being
8123 returned has a nonzero value, and *PFALSE is set to the other alternative.
8125 If we return zero, we set *PTRUE and *PFALSE to X. */
8128 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
8130 enum machine_mode mode = GET_MODE (x);
8131 enum rtx_code code = GET_CODE (x);
8132 rtx cond0, cond1, true0, true1, false0, false1;
8133 unsigned HOST_WIDE_INT nz;
8135 /* If we are comparing a value against zero, we are done. */
8136 if ((code == NE || code == EQ)
8137 && XEXP (x, 1) == const0_rtx)
8139 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
8140 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
8144 /* If this is a unary operation whose operand has one of two values, apply
8145 our opcode to compute those values. */
8146 else if (UNARY_P (x)
8147 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
8149 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
8150 *pfalse = simplify_gen_unary (code, mode, false0,
8151 GET_MODE (XEXP (x, 0)));
8155 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8156 make can't possibly match and would suppress other optimizations. */
8157 else if (code == COMPARE)
8160 /* If this is a binary operation, see if either side has only one of two
8161 values. If either one does or if both do and they are conditional on
8162 the same value, compute the new true and false values. */
8163 else if (BINARY_P (x))
8165 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
8166 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
8168 if ((cond0 != 0 || cond1 != 0)
8169 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
8171 /* If if_then_else_cond returned zero, then true/false are the
8172 same rtl. We must copy one of them to prevent invalid rtl
8175 true0 = copy_rtx (true0);
8176 else if (cond1 == 0)
8177 true1 = copy_rtx (true1);
8179 if (COMPARISON_P (x))
8181 *ptrue = simplify_gen_relational (code, mode, VOIDmode,
8183 *pfalse = simplify_gen_relational (code, mode, VOIDmode,
8188 *ptrue = simplify_gen_binary (code, mode, true0, true1);
8189 *pfalse = simplify_gen_binary (code, mode, false0, false1);
8192 return cond0 ? cond0 : cond1;
8195 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8196 operands is zero when the other is nonzero, and vice-versa,
8197 and STORE_FLAG_VALUE is 1 or -1. */
8199 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8200 && (code == PLUS || code == IOR || code == XOR || code == MINUS
8202 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8204 rtx op0 = XEXP (XEXP (x, 0), 1);
8205 rtx op1 = XEXP (XEXP (x, 1), 1);
8207 cond0 = XEXP (XEXP (x, 0), 0);
8208 cond1 = XEXP (XEXP (x, 1), 0);
8210 if (COMPARISON_P (cond0)
8211 && COMPARISON_P (cond1)
8212 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8213 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8214 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8215 || ((swap_condition (GET_CODE (cond0))
8216 == reversed_comparison_code (cond1, NULL))
8217 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8218 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8219 && ! side_effects_p (x))
8221 *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
8222 *pfalse = simplify_gen_binary (MULT, mode,
8224 ? simplify_gen_unary (NEG, mode,
8232 /* Similarly for MULT, AND and UMIN, except that for these the result
8234 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8235 && (code == MULT || code == AND || code == UMIN)
8236 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8238 cond0 = XEXP (XEXP (x, 0), 0);
8239 cond1 = XEXP (XEXP (x, 1), 0);
8241 if (COMPARISON_P (cond0)
8242 && COMPARISON_P (cond1)
8243 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8244 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8245 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8246 || ((swap_condition (GET_CODE (cond0))
8247 == reversed_comparison_code (cond1, NULL))
8248 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8249 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8250 && ! side_effects_p (x))
8252 *ptrue = *pfalse = const0_rtx;
8258 else if (code == IF_THEN_ELSE)
8260 /* If we have IF_THEN_ELSE already, extract the condition and
8261 canonicalize it if it is NE or EQ. */
8262 cond0 = XEXP (x, 0);
8263 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
8264 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
8265 return XEXP (cond0, 0);
8266 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
8268 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
8269 return XEXP (cond0, 0);
8275 /* If X is a SUBREG, we can narrow both the true and false values
8276 if the inner expression, if there is a condition. */
8277 else if (code == SUBREG
8278 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
8281 true0 = simplify_gen_subreg (mode, true0,
8282 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8283 false0 = simplify_gen_subreg (mode, false0,
8284 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8285 if (true0 && false0)
8293 /* If X is a constant, this isn't special and will cause confusions
8294 if we treat it as such. Likewise if it is equivalent to a constant. */
8295 else if (CONSTANT_P (x)
8296 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
8299 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8300 will be least confusing to the rest of the compiler. */
8301 else if (mode == BImode)
8303 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
8307 /* If X is known to be either 0 or -1, those are the true and
8308 false values when testing X. */
8309 else if (x == constm1_rtx || x == const0_rtx
8310 || (mode != VOIDmode
8311 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
8313 *ptrue = constm1_rtx, *pfalse = const0_rtx;
8317 /* Likewise for 0 or a single bit. */
8318 else if (SCALAR_INT_MODE_P (mode)
8319 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8320 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
8322 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
8326 /* Otherwise fail; show no condition with true and false values the same. */
8327 *ptrue = *pfalse = x;
8331 /* Return the value of expression X given the fact that condition COND
8332 is known to be true when applied to REG as its first operand and VAL
8333 as its second. X is known to not be shared and so can be modified in
8336 We only handle the simplest cases, and specifically those cases that
8337 arise with IF_THEN_ELSE expressions. */
8340 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
8342 enum rtx_code code = GET_CODE (x);
8347 if (side_effects_p (x))
8350 /* If either operand of the condition is a floating point value,
8351 then we have to avoid collapsing an EQ comparison. */
8353 && rtx_equal_p (x, reg)
8354 && ! FLOAT_MODE_P (GET_MODE (x))
8355 && ! FLOAT_MODE_P (GET_MODE (val)))
8358 if (cond == UNEQ && rtx_equal_p (x, reg))
8361 /* If X is (abs REG) and we know something about REG's relationship
8362 with zero, we may be able to simplify this. */
8364 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
8367 case GE: case GT: case EQ:
8370 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
8372 GET_MODE (XEXP (x, 0)));
8377 /* The only other cases we handle are MIN, MAX, and comparisons if the
8378 operands are the same as REG and VAL. */
8380 else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
8382 if (rtx_equal_p (XEXP (x, 0), val))
8383 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
8385 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
8387 if (COMPARISON_P (x))
8389 if (comparison_dominates_p (cond, code))
8390 return const_true_rtx;
8392 code = reversed_comparison_code (x, NULL);
8394 && comparison_dominates_p (cond, code))
8399 else if (code == SMAX || code == SMIN
8400 || code == UMIN || code == UMAX)
8402 int unsignedp = (code == UMIN || code == UMAX);
8404 /* Do not reverse the condition when it is NE or EQ.
8405 This is because we cannot conclude anything about
8406 the value of 'SMAX (x, y)' when x is not equal to y,
8407 but we can when x equals y. */
8408 if ((code == SMAX || code == UMAX)
8409 && ! (cond == EQ || cond == NE))
8410 cond = reverse_condition (cond);
8415 return unsignedp ? x : XEXP (x, 1);
8417 return unsignedp ? x : XEXP (x, 0);
8419 return unsignedp ? XEXP (x, 1) : x;
8421 return unsignedp ? XEXP (x, 0) : x;
8428 else if (code == SUBREG)
8430 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
8431 rtx new_rtx, r = known_cond (SUBREG_REG (x), cond, reg, val);
8433 if (SUBREG_REG (x) != r)
8435 /* We must simplify subreg here, before we lose track of the
8436 original inner_mode. */
8437 new_rtx = simplify_subreg (GET_MODE (x), r,
8438 inner_mode, SUBREG_BYTE (x));
8442 SUBST (SUBREG_REG (x), r);
8447 /* We don't have to handle SIGN_EXTEND here, because even in the
8448 case of replacing something with a modeless CONST_INT, a
8449 CONST_INT is already (supposed to be) a valid sign extension for
8450 its narrower mode, which implies it's already properly
8451 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
8452 story is different. */
8453 else if (code == ZERO_EXTEND)
8455 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
8456 rtx new_rtx, r = known_cond (XEXP (x, 0), cond, reg, val);
8458 if (XEXP (x, 0) != r)
8460 /* We must simplify the zero_extend here, before we lose
8461 track of the original inner_mode. */
8462 new_rtx = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
8467 SUBST (XEXP (x, 0), r);
8473 fmt = GET_RTX_FORMAT (code);
8474 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8477 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
8478 else if (fmt[i] == 'E')
8479 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8480 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
8487 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8488 assignment as a field assignment. */
8491 rtx_equal_for_field_assignment_p (rtx x, rtx y)
8493 if (x == y || rtx_equal_p (x, y))
8496 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
8499 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8500 Note that all SUBREGs of MEM are paradoxical; otherwise they
8501 would have been rewritten. */
8502 if (MEM_P (x) && GET_CODE (y) == SUBREG
8503 && MEM_P (SUBREG_REG (y))
8504 && rtx_equal_p (SUBREG_REG (y),
8505 gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
8508 if (MEM_P (y) && GET_CODE (x) == SUBREG
8509 && MEM_P (SUBREG_REG (x))
8510 && rtx_equal_p (SUBREG_REG (x),
8511 gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
8514 /* We used to see if get_last_value of X and Y were the same but that's
8515 not correct. In one direction, we'll cause the assignment to have
8516 the wrong destination and in the case, we'll import a register into this
8517 insn that might have already have been dead. So fail if none of the
8518 above cases are true. */
8522 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8523 Return that assignment if so.
8525 We only handle the most common cases. */
8528 make_field_assignment (rtx x)
8530 rtx dest = SET_DEST (x);
8531 rtx src = SET_SRC (x);
8536 unsigned HOST_WIDE_INT len;
8538 enum machine_mode mode;
8540 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
8541 a clear of a one-bit field. We will have changed it to
8542 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
8545 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
8546 && CONST_INT_P (XEXP (XEXP (src, 0), 0))
8547 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
8548 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8550 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8553 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8557 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
8558 && subreg_lowpart_p (XEXP (src, 0))
8559 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
8560 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
8561 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
8562 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src, 0)), 0))
8563 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
8564 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8566 assign = make_extraction (VOIDmode, dest, 0,
8567 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
8570 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8574 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
8576 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
8577 && XEXP (XEXP (src, 0), 0) == const1_rtx
8578 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8580 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8583 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
8587 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
8588 SRC is an AND with all bits of that field set, then we can discard
8590 if (GET_CODE (dest) == ZERO_EXTRACT
8591 && CONST_INT_P (XEXP (dest, 1))
8592 && GET_CODE (src) == AND
8593 && CONST_INT_P (XEXP (src, 1)))
8595 HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
8596 unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
8597 unsigned HOST_WIDE_INT ze_mask;
8599 if (width >= HOST_BITS_PER_WIDE_INT)
8602 ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
8604 /* Complete overlap. We can remove the source AND. */
8605 if ((and_mask & ze_mask) == ze_mask)
8606 return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
8608 /* Partial overlap. We can reduce the source AND. */
8609 if ((and_mask & ze_mask) != and_mask)
8611 mode = GET_MODE (src);
8612 src = gen_rtx_AND (mode, XEXP (src, 0),
8613 gen_int_mode (and_mask & ze_mask, mode));
8614 return gen_rtx_SET (VOIDmode, dest, src);
8618 /* The other case we handle is assignments into a constant-position
8619 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
8620 a mask that has all one bits except for a group of zero bits and
8621 OTHER is known to have zeros where C1 has ones, this is such an
8622 assignment. Compute the position and length from C1. Shift OTHER
8623 to the appropriate position, force it to the required mode, and
8624 make the extraction. Check for the AND in both operands. */
8626 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
8629 rhs = expand_compound_operation (XEXP (src, 0));
8630 lhs = expand_compound_operation (XEXP (src, 1));
8632 if (GET_CODE (rhs) == AND
8633 && CONST_INT_P (XEXP (rhs, 1))
8634 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
8635 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
8636 else if (GET_CODE (lhs) == AND
8637 && CONST_INT_P (XEXP (lhs, 1))
8638 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
8639 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
8643 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
8644 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
8645 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
8646 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
8649 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
8653 /* The mode to use for the source is the mode of the assignment, or of
8654 what is inside a possible STRICT_LOW_PART. */
8655 mode = (GET_CODE (assign) == STRICT_LOW_PART
8656 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
8658 /* Shift OTHER right POS places and make it the source, restricting it
8659 to the proper length and mode. */
8661 src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
8665 src = force_to_mode (src, mode,
8666 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
8667 ? ~(unsigned HOST_WIDE_INT) 0
8668 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
8671 /* If SRC is masked by an AND that does not make a difference in
8672 the value being stored, strip it. */
8673 if (GET_CODE (assign) == ZERO_EXTRACT
8674 && CONST_INT_P (XEXP (assign, 1))
8675 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
8676 && GET_CODE (src) == AND
8677 && CONST_INT_P (XEXP (src, 1))
8678 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
8679 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
8680 src = XEXP (src, 0);
8682 return gen_rtx_SET (VOIDmode, assign, src);
8685 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
8689 apply_distributive_law (rtx x)
8691 enum rtx_code code = GET_CODE (x);
8692 enum rtx_code inner_code;
8693 rtx lhs, rhs, other;
8696 /* Distributivity is not true for floating point as it can change the
8697 value. So we don't do it unless -funsafe-math-optimizations. */
8698 if (FLOAT_MODE_P (GET_MODE (x))
8699 && ! flag_unsafe_math_optimizations)
8702 /* The outer operation can only be one of the following: */
8703 if (code != IOR && code != AND && code != XOR
8704 && code != PLUS && code != MINUS)
8710 /* If either operand is a primitive we can't do anything, so get out
8712 if (OBJECT_P (lhs) || OBJECT_P (rhs))
8715 lhs = expand_compound_operation (lhs);
8716 rhs = expand_compound_operation (rhs);
8717 inner_code = GET_CODE (lhs);
8718 if (inner_code != GET_CODE (rhs))
8721 /* See if the inner and outer operations distribute. */
8728 /* These all distribute except over PLUS. */
8729 if (code == PLUS || code == MINUS)
8734 if (code != PLUS && code != MINUS)
8739 /* This is also a multiply, so it distributes over everything. */
8743 /* Non-paradoxical SUBREGs distributes over all operations,
8744 provided the inner modes and byte offsets are the same, this
8745 is an extraction of a low-order part, we don't convert an fp
8746 operation to int or vice versa, this is not a vector mode,
8747 and we would not be converting a single-word operation into a
8748 multi-word operation. The latter test is not required, but
8749 it prevents generating unneeded multi-word operations. Some
8750 of the previous tests are redundant given the latter test,
8751 but are retained because they are required for correctness.
8753 We produce the result slightly differently in this case. */
8755 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
8756 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
8757 || ! subreg_lowpart_p (lhs)
8758 || (GET_MODE_CLASS (GET_MODE (lhs))
8759 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
8760 || (GET_MODE_SIZE (GET_MODE (lhs))
8761 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
8762 || VECTOR_MODE_P (GET_MODE (lhs))
8763 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD
8764 /* Result might need to be truncated. Don't change mode if
8765 explicit truncation is needed. */
8766 || !TRULY_NOOP_TRUNCATION
8767 (GET_MODE_BITSIZE (GET_MODE (x)),
8768 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (lhs)))))
8771 tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
8772 SUBREG_REG (lhs), SUBREG_REG (rhs));
8773 return gen_lowpart (GET_MODE (x), tem);
8779 /* Set LHS and RHS to the inner operands (A and B in the example
8780 above) and set OTHER to the common operand (C in the example).
8781 There is only one way to do this unless the inner operation is
8783 if (COMMUTATIVE_ARITH_P (lhs)
8784 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
8785 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
8786 else if (COMMUTATIVE_ARITH_P (lhs)
8787 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
8788 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
8789 else if (COMMUTATIVE_ARITH_P (lhs)
8790 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
8791 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
8792 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
8793 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
8797 /* Form the new inner operation, seeing if it simplifies first. */
8798 tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
8800 /* There is one exception to the general way of distributing:
8801 (a | c) ^ (b | c) -> (a ^ b) & ~c */
8802 if (code == XOR && inner_code == IOR)
8805 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
8808 /* We may be able to continuing distributing the result, so call
8809 ourselves recursively on the inner operation before forming the
8810 outer operation, which we return. */
8811 return simplify_gen_binary (inner_code, GET_MODE (x),
8812 apply_distributive_law (tem), other);
8815 /* See if X is of the form (* (+ A B) C), and if so convert to
8816 (+ (* A C) (* B C)) and try to simplify.
8818 Most of the time, this results in no change. However, if some of
8819 the operands are the same or inverses of each other, simplifications
8822 For example, (and (ior A B) (not B)) can occur as the result of
8823 expanding a bit field assignment. When we apply the distributive
8824 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
8825 which then simplifies to (and (A (not B))).
8827 Note that no checks happen on the validity of applying the inverse
8828 distributive law. This is pointless since we can do it in the
8829 few places where this routine is called.
8831 N is the index of the term that is decomposed (the arithmetic operation,
8832 i.e. (+ A B) in the first example above). !N is the index of the term that
8833 is distributed, i.e. of C in the first example above. */
8835 distribute_and_simplify_rtx (rtx x, int n)
8837 enum machine_mode mode;
8838 enum rtx_code outer_code, inner_code;
8839 rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
8841 /* Distributivity is not true for floating point as it can change the
8842 value. So we don't do it unless -funsafe-math-optimizations. */
8843 if (FLOAT_MODE_P (GET_MODE (x))
8844 && ! flag_unsafe_math_optimizations)
8847 decomposed = XEXP (x, n);
8848 if (!ARITHMETIC_P (decomposed))
8851 mode = GET_MODE (x);
8852 outer_code = GET_CODE (x);
8853 distributed = XEXP (x, !n);
8855 inner_code = GET_CODE (decomposed);
8856 inner_op0 = XEXP (decomposed, 0);
8857 inner_op1 = XEXP (decomposed, 1);
8859 /* Special case (and (xor B C) (not A)), which is equivalent to
8860 (xor (ior A B) (ior A C)) */
8861 if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
8863 distributed = XEXP (distributed, 0);
8869 /* Distribute the second term. */
8870 new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
8871 new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
8875 /* Distribute the first term. */
8876 new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
8877 new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
8880 tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
8882 if (GET_CODE (tmp) != outer_code
8883 && rtx_cost (tmp, SET, optimize_this_for_speed_p)
8884 < rtx_cost (x, SET, optimize_this_for_speed_p))
8890 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
8891 in MODE. Return an equivalent form, if different from (and VAROP
8892 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
8895 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
8896 unsigned HOST_WIDE_INT constop)
8898 unsigned HOST_WIDE_INT nonzero;
8899 unsigned HOST_WIDE_INT orig_constop;
8904 orig_constop = constop;
8905 if (GET_CODE (varop) == CLOBBER)
8908 /* Simplify VAROP knowing that we will be only looking at some of the
8911 Note by passing in CONSTOP, we guarantee that the bits not set in
8912 CONSTOP are not significant and will never be examined. We must
8913 ensure that is the case by explicitly masking out those bits
8914 before returning. */
8915 varop = force_to_mode (varop, mode, constop, 0);
8917 /* If VAROP is a CLOBBER, we will fail so return it. */
8918 if (GET_CODE (varop) == CLOBBER)
8921 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8922 to VAROP and return the new constant. */
8923 if (CONST_INT_P (varop))
8924 return gen_int_mode (INTVAL (varop) & constop, mode);
8926 /* See what bits may be nonzero in VAROP. Unlike the general case of
8927 a call to nonzero_bits, here we don't care about bits outside
8930 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
8932 /* Turn off all bits in the constant that are known to already be zero.
8933 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8934 which is tested below. */
8938 /* If we don't have any bits left, return zero. */
8942 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8943 a power of two, we can replace this with an ASHIFT. */
8944 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
8945 && (i = exact_log2 (constop)) >= 0)
8946 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
8948 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8949 or XOR, then try to apply the distributive law. This may eliminate
8950 operations if either branch can be simplified because of the AND.
8951 It may also make some cases more complex, but those cases probably
8952 won't match a pattern either with or without this. */
8954 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
8958 apply_distributive_law
8959 (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
8960 simplify_and_const_int (NULL_RTX,
8964 simplify_and_const_int (NULL_RTX,
8969 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
8970 the AND and see if one of the operands simplifies to zero. If so, we
8971 may eliminate it. */
8973 if (GET_CODE (varop) == PLUS
8974 && exact_log2 (constop + 1) >= 0)
8978 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
8979 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
8980 if (o0 == const0_rtx)
8982 if (o1 == const0_rtx)
8986 /* Make a SUBREG if necessary. If we can't make it, fail. */
8987 varop = gen_lowpart (mode, varop);
8988 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
8991 /* If we are only masking insignificant bits, return VAROP. */
8992 if (constop == nonzero)
8995 if (varop == orig_varop && constop == orig_constop)
8998 /* Otherwise, return an AND. */
8999 return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
9003 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9006 Return an equivalent form, if different from X. Otherwise, return X. If
9007 X is zero, we are to always construct the equivalent form. */
9010 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
9011 unsigned HOST_WIDE_INT constop)
9013 rtx tem = simplify_and_const_int_1 (mode, varop, constop);
9018 x = simplify_gen_binary (AND, GET_MODE (varop), varop,
9019 gen_int_mode (constop, mode));
9020 if (GET_MODE (x) != mode)
9021 x = gen_lowpart (mode, x);
9025 /* Given a REG, X, compute which bits in X can be nonzero.
9026 We don't care about bits outside of those defined in MODE.
9028 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9029 a shift, AND, or zero_extract, we can do better. */
9032 reg_nonzero_bits_for_combine (const_rtx x, enum machine_mode mode,
9033 const_rtx known_x ATTRIBUTE_UNUSED,
9034 enum machine_mode known_mode ATTRIBUTE_UNUSED,
9035 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
9036 unsigned HOST_WIDE_INT *nonzero)
9041 /* If X is a register whose nonzero bits value is current, use it.
9042 Otherwise, if X is a register whose value we can find, use that
9043 value. Otherwise, use the previously-computed global nonzero bits
9044 for this register. */
9046 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
9047 if (rsp->last_set_value != 0
9048 && (rsp->last_set_mode == mode
9049 || (GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT
9050 && GET_MODE_CLASS (mode) == MODE_INT))
9051 && ((rsp->last_set_label >= label_tick_ebb_start
9052 && rsp->last_set_label < label_tick)
9053 || (rsp->last_set_label == label_tick
9054 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9055 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9056 && REG_N_SETS (REGNO (x)) == 1
9058 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9060 *nonzero &= rsp->last_set_nonzero_bits;
9064 tem = get_last_value (x);
9068 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9069 /* If X is narrower than MODE and TEM is a non-negative
9070 constant that would appear negative in the mode of X,
9071 sign-extend it for use in reg_nonzero_bits because some
9072 machines (maybe most) will actually do the sign-extension
9073 and this is the conservative approach.
9075 ??? For 2.5, try to tighten up the MD files in this regard
9076 instead of this kludge. */
9078 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)
9079 && CONST_INT_P (tem)
9081 && 0 != (INTVAL (tem)
9082 & ((HOST_WIDE_INT) 1
9083 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
9084 tem = GEN_INT (INTVAL (tem)
9085 | ((HOST_WIDE_INT) (-1)
9086 << GET_MODE_BITSIZE (GET_MODE (x))));
9090 else if (nonzero_sign_valid && rsp->nonzero_bits)
9092 unsigned HOST_WIDE_INT mask = rsp->nonzero_bits;
9094 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode))
9095 /* We don't know anything about the upper bits. */
9096 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
9103 /* Return the number of bits at the high-order end of X that are known to
9104 be equal to the sign bit. X will be used in mode MODE; if MODE is
9105 VOIDmode, X will be used in its own mode. The returned value will always
9106 be between 1 and the number of bits in MODE. */
9109 reg_num_sign_bit_copies_for_combine (const_rtx x, enum machine_mode mode,
9110 const_rtx known_x ATTRIBUTE_UNUSED,
9111 enum machine_mode known_mode
9113 unsigned int known_ret ATTRIBUTE_UNUSED,
9114 unsigned int *result)
9119 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
9120 if (rsp->last_set_value != 0
9121 && rsp->last_set_mode == mode
9122 && ((rsp->last_set_label >= label_tick_ebb_start
9123 && rsp->last_set_label < label_tick)
9124 || (rsp->last_set_label == label_tick
9125 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9126 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9127 && REG_N_SETS (REGNO (x)) == 1
9129 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9131 *result = rsp->last_set_sign_bit_copies;
9135 tem = get_last_value (x);
9139 if (nonzero_sign_valid && rsp->sign_bit_copies != 0
9140 && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode))
9141 *result = rsp->sign_bit_copies;
9146 /* Return the number of "extended" bits there are in X, when interpreted
9147 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9148 unsigned quantities, this is the number of high-order zero bits.
9149 For signed quantities, this is the number of copies of the sign bit
9150 minus 1. In both case, this function returns the number of "spare"
9151 bits. For example, if two quantities for which this function returns
9152 at least 1 are added, the addition is known not to overflow.
9154 This function will always return 0 unless called during combine, which
9155 implies that it must be called from a define_split. */
9158 extended_count (const_rtx x, enum machine_mode mode, int unsignedp)
9160 if (nonzero_sign_valid == 0)
9164 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9165 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
9166 - floor_log2 (nonzero_bits (x, mode)))
9168 : num_sign_bit_copies (x, mode) - 1);
9171 /* This function is called from `simplify_shift_const' to merge two
9172 outer operations. Specifically, we have already found that we need
9173 to perform operation *POP0 with constant *PCONST0 at the outermost
9174 position. We would now like to also perform OP1 with constant CONST1
9175 (with *POP0 being done last).
9177 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9178 the resulting operation. *PCOMP_P is set to 1 if we would need to
9179 complement the innermost operand, otherwise it is unchanged.
9181 MODE is the mode in which the operation will be done. No bits outside
9182 the width of this mode matter. It is assumed that the width of this mode
9183 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9185 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9186 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9187 result is simply *PCONST0.
9189 If the resulting operation cannot be expressed as one operation, we
9190 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9193 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
9195 enum rtx_code op0 = *pop0;
9196 HOST_WIDE_INT const0 = *pconst0;
9198 const0 &= GET_MODE_MASK (mode);
9199 const1 &= GET_MODE_MASK (mode);
9201 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9205 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9208 if (op1 == UNKNOWN || op0 == SET)
9211 else if (op0 == UNKNOWN)
9212 op0 = op1, const0 = const1;
9214 else if (op0 == op1)
9238 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9239 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
9242 /* If the two constants aren't the same, we can't do anything. The
9243 remaining six cases can all be done. */
9244 else if (const0 != const1)
9252 /* (a & b) | b == b */
9254 else /* op1 == XOR */
9255 /* (a ^ b) | b == a | b */
9261 /* (a & b) ^ b == (~a) & b */
9262 op0 = AND, *pcomp_p = 1;
9263 else /* op1 == IOR */
9264 /* (a | b) ^ b == a & ~b */
9265 op0 = AND, const0 = ~const0;
9270 /* (a | b) & b == b */
9272 else /* op1 == XOR */
9273 /* (a ^ b) & b) == (~a) & b */
9280 /* Check for NO-OP cases. */
9281 const0 &= GET_MODE_MASK (mode);
9283 && (op0 == IOR || op0 == XOR || op0 == PLUS))
9285 else if (const0 == 0 && op0 == AND)
9287 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
9293 /* ??? Slightly redundant with the above mask, but not entirely.
9294 Moving this above means we'd have to sign-extend the mode mask
9295 for the final test. */
9296 if (op0 != UNKNOWN && op0 != NEG)
9297 *pconst0 = trunc_int_for_mode (const0, mode);
9302 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9303 the shift in. The original shift operation CODE is performed on OP in
9304 ORIG_MODE. Return the wider mode MODE if we can perform the operation
9305 in that mode. Return ORIG_MODE otherwise. We can also assume that the
9306 result of the shift is subject to operation OUTER_CODE with operand
9309 static enum machine_mode
9310 try_widen_shift_mode (enum rtx_code code, rtx op, int count,
9311 enum machine_mode orig_mode, enum machine_mode mode,
9312 enum rtx_code outer_code, HOST_WIDE_INT outer_const)
9314 if (orig_mode == mode)
9316 gcc_assert (GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (orig_mode));
9318 /* In general we can't perform in wider mode for right shift and rotate. */
9322 /* We can still widen if the bits brought in from the left are identical
9323 to the sign bit of ORIG_MODE. */
9324 if (num_sign_bit_copies (op, mode)
9325 > (unsigned) (GET_MODE_BITSIZE (mode)
9326 - GET_MODE_BITSIZE (orig_mode)))
9331 /* Similarly here but with zero bits. */
9332 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9333 && (nonzero_bits (op, mode) & ~GET_MODE_MASK (orig_mode)) == 0)
9336 /* We can also widen if the bits brought in will be masked off. This
9337 operation is performed in ORIG_MODE. */
9338 if (outer_code == AND)
9340 int care_bits = low_bitmask_len (orig_mode, outer_const);
9343 && GET_MODE_BITSIZE (orig_mode) - care_bits >= count)
9359 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9360 The result of the shift is RESULT_MODE. Return NULL_RTX if we cannot
9361 simplify it. Otherwise, return a simplified value.
9363 The shift is normally computed in the widest mode we find in VAROP, as
9364 long as it isn't a different number of words than RESULT_MODE. Exceptions
9365 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9368 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
9369 rtx varop, int orig_count)
9371 enum rtx_code orig_code = code;
9372 rtx orig_varop = varop;
9374 enum machine_mode mode = result_mode;
9375 enum machine_mode shift_mode, tmode;
9376 unsigned int mode_words
9377 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
9378 /* We form (outer_op (code varop count) (outer_const)). */
9379 enum rtx_code outer_op = UNKNOWN;
9380 HOST_WIDE_INT outer_const = 0;
9381 int complement_p = 0;
9384 /* Make sure and truncate the "natural" shift on the way in. We don't
9385 want to do this inside the loop as it makes it more difficult to
9387 if (SHIFT_COUNT_TRUNCATED)
9388 orig_count &= GET_MODE_BITSIZE (mode) - 1;
9390 /* If we were given an invalid count, don't do anything except exactly
9391 what was requested. */
9393 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
9398 /* Unless one of the branches of the `if' in this loop does a `continue',
9399 we will `break' the loop after the `if'. */
9403 /* If we have an operand of (clobber (const_int 0)), fail. */
9404 if (GET_CODE (varop) == CLOBBER)
9407 /* Convert ROTATERT to ROTATE. */
9408 if (code == ROTATERT)
9410 unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
9412 if (VECTOR_MODE_P (result_mode))
9413 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
9415 count = bitsize - count;
9418 shift_mode = try_widen_shift_mode (code, varop, count, result_mode,
9419 mode, outer_op, outer_const);
9421 /* Handle cases where the count is greater than the size of the mode
9422 minus 1. For ASHIFT, use the size minus one as the count (this can
9423 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9424 take the count modulo the size. For other shifts, the result is
9427 Since these shifts are being produced by the compiler by combining
9428 multiple operations, each of which are defined, we know what the
9429 result is supposed to be. */
9431 if (count > (GET_MODE_BITSIZE (shift_mode) - 1))
9433 if (code == ASHIFTRT)
9434 count = GET_MODE_BITSIZE (shift_mode) - 1;
9435 else if (code == ROTATE || code == ROTATERT)
9436 count %= GET_MODE_BITSIZE (shift_mode);
9439 /* We can't simply return zero because there may be an
9447 /* If we discovered we had to complement VAROP, leave. Making a NOT
9448 here would cause an infinite loop. */
9452 /* An arithmetic right shift of a quantity known to be -1 or 0
9454 if (code == ASHIFTRT
9455 && (num_sign_bit_copies (varop, shift_mode)
9456 == GET_MODE_BITSIZE (shift_mode)))
9462 /* If we are doing an arithmetic right shift and discarding all but
9463 the sign bit copies, this is equivalent to doing a shift by the
9464 bitsize minus one. Convert it into that shift because it will often
9465 allow other simplifications. */
9467 if (code == ASHIFTRT
9468 && (count + num_sign_bit_copies (varop, shift_mode)
9469 >= GET_MODE_BITSIZE (shift_mode)))
9470 count = GET_MODE_BITSIZE (shift_mode) - 1;
9472 /* We simplify the tests below and elsewhere by converting
9473 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9474 `make_compound_operation' will convert it to an ASHIFTRT for
9475 those machines (such as VAX) that don't have an LSHIFTRT. */
9476 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9478 && ((nonzero_bits (varop, shift_mode)
9479 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
9483 if (((code == LSHIFTRT
9484 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9485 && !(nonzero_bits (varop, shift_mode) >> count))
9487 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9488 && !((nonzero_bits (varop, shift_mode) << count)
9489 & GET_MODE_MASK (shift_mode))))
9490 && !side_effects_p (varop))
9493 switch (GET_CODE (varop))
9499 new_rtx = expand_compound_operation (varop);
9500 if (new_rtx != varop)
9508 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9509 minus the width of a smaller mode, we can do this with a
9510 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9511 if ((code == ASHIFTRT || code == LSHIFTRT)
9512 && ! mode_dependent_address_p (XEXP (varop, 0))
9513 && ! MEM_VOLATILE_P (varop)
9514 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9515 MODE_INT, 1)) != BLKmode)
9517 new_rtx = adjust_address_nv (varop, tmode,
9518 BYTES_BIG_ENDIAN ? 0
9519 : count / BITS_PER_UNIT);
9521 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9522 : ZERO_EXTEND, mode, new_rtx);
9529 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9530 the same number of words as what we've seen so far. Then store
9531 the widest mode in MODE. */
9532 if (subreg_lowpart_p (varop)
9533 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9534 > GET_MODE_SIZE (GET_MODE (varop)))
9535 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9536 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9539 varop = SUBREG_REG (varop);
9540 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9541 mode = GET_MODE (varop);
9547 /* Some machines use MULT instead of ASHIFT because MULT
9548 is cheaper. But it is still better on those machines to
9549 merge two shifts into one. */
9550 if (CONST_INT_P (XEXP (varop, 1))
9551 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9554 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
9556 GEN_INT (exact_log2 (
9557 INTVAL (XEXP (varop, 1)))));
9563 /* Similar, for when divides are cheaper. */
9564 if (CONST_INT_P (XEXP (varop, 1))
9565 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9568 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
9570 GEN_INT (exact_log2 (
9571 INTVAL (XEXP (varop, 1)))));
9577 /* If we are extracting just the sign bit of an arithmetic
9578 right shift, that shift is not needed. However, the sign
9579 bit of a wider mode may be different from what would be
9580 interpreted as the sign bit in a narrower mode, so, if
9581 the result is narrower, don't discard the shift. */
9582 if (code == LSHIFTRT
9583 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9584 && (GET_MODE_BITSIZE (result_mode)
9585 >= GET_MODE_BITSIZE (GET_MODE (varop))))
9587 varop = XEXP (varop, 0);
9591 /* ... fall through ... */
9596 /* Here we have two nested shifts. The result is usually the
9597 AND of a new shift with a mask. We compute the result below. */
9598 if (CONST_INT_P (XEXP (varop, 1))
9599 && INTVAL (XEXP (varop, 1)) >= 0
9600 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
9601 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9602 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9603 && !VECTOR_MODE_P (result_mode))
9605 enum rtx_code first_code = GET_CODE (varop);
9606 unsigned int first_count = INTVAL (XEXP (varop, 1));
9607 unsigned HOST_WIDE_INT mask;
9610 /* We have one common special case. We can't do any merging if
9611 the inner code is an ASHIFTRT of a smaller mode. However, if
9612 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9613 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9614 we can convert it to
9615 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9616 This simplifies certain SIGN_EXTEND operations. */
9617 if (code == ASHIFT && first_code == ASHIFTRT
9618 && count == (GET_MODE_BITSIZE (result_mode)
9619 - GET_MODE_BITSIZE (GET_MODE (varop))))
9621 /* C3 has the low-order C1 bits zero. */
9623 mask = (GET_MODE_MASK (mode)
9624 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
9626 varop = simplify_and_const_int (NULL_RTX, result_mode,
9627 XEXP (varop, 0), mask);
9628 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
9630 count = first_count;
9635 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9636 than C1 high-order bits equal to the sign bit, we can convert
9637 this to either an ASHIFT or an ASHIFTRT depending on the
9640 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9642 if (code == ASHIFTRT && first_code == ASHIFT
9643 && GET_MODE (varop) == shift_mode
9644 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
9647 varop = XEXP (varop, 0);
9648 count -= first_count;
9658 /* There are some cases we can't do. If CODE is ASHIFTRT,
9659 we can only do this if FIRST_CODE is also ASHIFTRT.
9661 We can't do the case when CODE is ROTATE and FIRST_CODE is
9664 If the mode of this shift is not the mode of the outer shift,
9665 we can't do this if either shift is a right shift or ROTATE.
9667 Finally, we can't do any of these if the mode is too wide
9668 unless the codes are the same.
9670 Handle the case where the shift codes are the same
9673 if (code == first_code)
9675 if (GET_MODE (varop) != result_mode
9676 && (code == ASHIFTRT || code == LSHIFTRT
9680 count += first_count;
9681 varop = XEXP (varop, 0);
9685 if (code == ASHIFTRT
9686 || (code == ROTATE && first_code == ASHIFTRT)
9687 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
9688 || (GET_MODE (varop) != result_mode
9689 && (first_code == ASHIFTRT || first_code == LSHIFTRT
9690 || first_code == ROTATE
9691 || code == ROTATE)))
9694 /* To compute the mask to apply after the shift, shift the
9695 nonzero bits of the inner shift the same way the
9696 outer shift will. */
9698 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
9701 = simplify_const_binary_operation (code, result_mode, mask_rtx,
9704 /* Give up if we can't compute an outer operation to use. */
9706 || !CONST_INT_P (mask_rtx)
9707 || ! merge_outer_ops (&outer_op, &outer_const, AND,
9709 result_mode, &complement_p))
9712 /* If the shifts are in the same direction, we add the
9713 counts. Otherwise, we subtract them. */
9714 if ((code == ASHIFTRT || code == LSHIFTRT)
9715 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
9716 count += first_count;
9718 count -= first_count;
9720 /* If COUNT is positive, the new shift is usually CODE,
9721 except for the two exceptions below, in which case it is
9722 FIRST_CODE. If the count is negative, FIRST_CODE should
9725 && ((first_code == ROTATE && code == ASHIFT)
9726 || (first_code == ASHIFTRT && code == LSHIFTRT)))
9729 code = first_code, count = -count;
9731 varop = XEXP (varop, 0);
9735 /* If we have (A << B << C) for any shift, we can convert this to
9736 (A << C << B). This wins if A is a constant. Only try this if
9737 B is not a constant. */
9739 else if (GET_CODE (varop) == code
9740 && CONST_INT_P (XEXP (varop, 0))
9741 && !CONST_INT_P (XEXP (varop, 1)))
9743 rtx new_rtx = simplify_const_binary_operation (code, mode,
9746 varop = gen_rtx_fmt_ee (code, mode, new_rtx, XEXP (varop, 1));
9753 if (VECTOR_MODE_P (mode))
9756 /* Make this fit the case below. */
9757 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
9758 GEN_INT (GET_MODE_MASK (mode)));
9764 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9765 with C the size of VAROP - 1 and the shift is logical if
9766 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9767 we have an (le X 0) operation. If we have an arithmetic shift
9768 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9769 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9771 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9772 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9773 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9774 && (code == LSHIFTRT || code == ASHIFTRT)
9775 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9776 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9779 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
9782 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9783 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9788 /* If we have (shift (logical)), move the logical to the outside
9789 to allow it to possibly combine with another logical and the
9790 shift to combine with another shift. This also canonicalizes to
9791 what a ZERO_EXTRACT looks like. Also, some machines have
9792 (and (shift)) insns. */
9794 if (CONST_INT_P (XEXP (varop, 1))
9795 /* We can't do this if we have (ashiftrt (xor)) and the
9796 constant has its sign bit set in shift_mode. */
9797 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
9798 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
9800 && (new_rtx = simplify_const_binary_operation (code, result_mode,
9802 GEN_INT (count))) != 0
9803 && CONST_INT_P (new_rtx)
9804 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9805 INTVAL (new_rtx), result_mode, &complement_p))
9807 varop = XEXP (varop, 0);
9811 /* If we can't do that, try to simplify the shift in each arm of the
9812 logical expression, make a new logical expression, and apply
9813 the inverse distributive law. This also can't be done
9814 for some (ashiftrt (xor)). */
9815 if (CONST_INT_P (XEXP (varop, 1))
9816 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
9817 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
9820 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9821 XEXP (varop, 0), count);
9822 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9823 XEXP (varop, 1), count);
9825 varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
9827 varop = apply_distributive_law (varop);
9835 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9836 says that the sign bit can be tested, FOO has mode MODE, C is
9837 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9838 that may be nonzero. */
9839 if (code == LSHIFTRT
9840 && XEXP (varop, 1) == const0_rtx
9841 && GET_MODE (XEXP (varop, 0)) == result_mode
9842 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9843 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9844 && STORE_FLAG_VALUE == -1
9845 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9846 && merge_outer_ops (&outer_op, &outer_const, XOR,
9847 (HOST_WIDE_INT) 1, result_mode,
9850 varop = XEXP (varop, 0);
9857 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9858 than the number of bits in the mode is equivalent to A. */
9859 if (code == LSHIFTRT
9860 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9861 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9863 varop = XEXP (varop, 0);
9868 /* NEG commutes with ASHIFT since it is multiplication. Move the
9869 NEG outside to allow shifts to combine. */
9871 && merge_outer_ops (&outer_op, &outer_const, NEG,
9872 (HOST_WIDE_INT) 0, result_mode,
9875 varop = XEXP (varop, 0);
9881 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9882 is one less than the number of bits in the mode is
9883 equivalent to (xor A 1). */
9884 if (code == LSHIFTRT
9885 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9886 && XEXP (varop, 1) == constm1_rtx
9887 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9888 && merge_outer_ops (&outer_op, &outer_const, XOR,
9889 (HOST_WIDE_INT) 1, result_mode,
9893 varop = XEXP (varop, 0);
9897 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9898 that might be nonzero in BAR are those being shifted out and those
9899 bits are known zero in FOO, we can replace the PLUS with FOO.
9900 Similarly in the other operand order. This code occurs when
9901 we are computing the size of a variable-size array. */
9903 if ((code == ASHIFTRT || code == LSHIFTRT)
9904 && count < HOST_BITS_PER_WIDE_INT
9905 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9906 && (nonzero_bits (XEXP (varop, 1), result_mode)
9907 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9909 varop = XEXP (varop, 0);
9912 else if ((code == ASHIFTRT || code == LSHIFTRT)
9913 && count < HOST_BITS_PER_WIDE_INT
9914 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9915 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9917 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9918 & nonzero_bits (XEXP (varop, 1),
9921 varop = XEXP (varop, 1);
9925 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9927 && CONST_INT_P (XEXP (varop, 1))
9928 && (new_rtx = simplify_const_binary_operation (ASHIFT, result_mode,
9930 GEN_INT (count))) != 0
9931 && CONST_INT_P (new_rtx)
9932 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9933 INTVAL (new_rtx), result_mode, &complement_p))
9935 varop = XEXP (varop, 0);
9939 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
9940 signbit', and attempt to change the PLUS to an XOR and move it to
9941 the outer operation as is done above in the AND/IOR/XOR case
9942 leg for shift(logical). See details in logical handling above
9943 for reasoning in doing so. */
9944 if (code == LSHIFTRT
9945 && CONST_INT_P (XEXP (varop, 1))
9946 && mode_signbit_p (result_mode, XEXP (varop, 1))
9947 && (new_rtx = simplify_const_binary_operation (code, result_mode,
9949 GEN_INT (count))) != 0
9950 && CONST_INT_P (new_rtx)
9951 && merge_outer_ops (&outer_op, &outer_const, XOR,
9952 INTVAL (new_rtx), result_mode, &complement_p))
9954 varop = XEXP (varop, 0);
9961 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9962 with C the size of VAROP - 1 and the shift is logical if
9963 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9964 we have a (gt X 0) operation. If the shift is arithmetic with
9965 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9966 we have a (neg (gt X 0)) operation. */
9968 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9969 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9970 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9971 && (code == LSHIFTRT || code == ASHIFTRT)
9972 && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
9973 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
9974 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9977 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9980 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9981 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9988 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9989 if the truncate does not affect the value. */
9990 if (code == LSHIFTRT
9991 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9992 && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
9993 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9994 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9995 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9997 rtx varop_inner = XEXP (varop, 0);
10000 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
10001 XEXP (varop_inner, 0),
10003 (count + INTVAL (XEXP (varop_inner, 1))));
10004 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
10017 shift_mode = try_widen_shift_mode (code, varop, count, result_mode, mode,
10018 outer_op, outer_const);
10020 /* We have now finished analyzing the shift. The result should be
10021 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10022 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10023 to the result of the shift. OUTER_CONST is the relevant constant,
10024 but we must turn off all bits turned off in the shift. */
10026 if (outer_op == UNKNOWN
10027 && orig_code == code && orig_count == count
10028 && varop == orig_varop
10029 && shift_mode == GET_MODE (varop))
10032 /* Make a SUBREG if necessary. If we can't make it, fail. */
10033 varop = gen_lowpart (shift_mode, varop);
10034 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
10037 /* If we have an outer operation and we just made a shift, it is
10038 possible that we could have simplified the shift were it not
10039 for the outer operation. So try to do the simplification
10042 if (outer_op != UNKNOWN)
10043 x = simplify_shift_const_1 (code, shift_mode, varop, count);
10048 x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
10050 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10051 turn off all the bits that the shift would have turned off. */
10052 if (orig_code == LSHIFTRT && result_mode != shift_mode)
10053 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
10054 GET_MODE_MASK (result_mode) >> orig_count);
10056 /* Do the remainder of the processing in RESULT_MODE. */
10057 x = gen_lowpart_or_truncate (result_mode, x);
10059 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10062 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
10064 if (outer_op != UNKNOWN)
10066 if (GET_RTX_CLASS (outer_op) != RTX_UNARY
10067 && GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
10068 outer_const = trunc_int_for_mode (outer_const, result_mode);
10070 if (outer_op == AND)
10071 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
10072 else if (outer_op == SET)
10074 /* This means that we have determined that the result is
10075 equivalent to a constant. This should be rare. */
10076 if (!side_effects_p (x))
10077 x = GEN_INT (outer_const);
10079 else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
10080 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
10082 x = simplify_gen_binary (outer_op, result_mode, x,
10083 GEN_INT (outer_const));
10089 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10090 The result of the shift is RESULT_MODE. If we cannot simplify it,
10091 return X or, if it is NULL, synthesize the expression with
10092 simplify_gen_binary. Otherwise, return a simplified value.
10094 The shift is normally computed in the widest mode we find in VAROP, as
10095 long as it isn't a different number of words than RESULT_MODE. Exceptions
10096 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10099 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
10100 rtx varop, int count)
10102 rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
10107 x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
10108 if (GET_MODE (x) != result_mode)
10109 x = gen_lowpart (result_mode, x);
10114 /* Like recog, but we receive the address of a pointer to a new pattern.
10115 We try to match the rtx that the pointer points to.
10116 If that fails, we may try to modify or replace the pattern,
10117 storing the replacement into the same pointer object.
10119 Modifications include deletion or addition of CLOBBERs.
10121 PNOTES is a pointer to a location where any REG_UNUSED notes added for
10122 the CLOBBERs are placed.
10124 The value is the final insn code from the pattern ultimately matched,
10128 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
10130 rtx pat = *pnewpat;
10131 int insn_code_number;
10132 int num_clobbers_to_add = 0;
10135 rtx old_notes, old_pat;
10137 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10138 we use to indicate that something didn't match. If we find such a
10139 thing, force rejection. */
10140 if (GET_CODE (pat) == PARALLEL)
10141 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
10142 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
10143 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
10146 old_pat = PATTERN (insn);
10147 old_notes = REG_NOTES (insn);
10148 PATTERN (insn) = pat;
10149 REG_NOTES (insn) = 0;
10151 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10152 if (dump_file && (dump_flags & TDF_DETAILS))
10154 if (insn_code_number < 0)
10155 fputs ("Failed to match this instruction:\n", dump_file);
10157 fputs ("Successfully matched this instruction:\n", dump_file);
10158 print_rtl_single (dump_file, pat);
10161 /* If it isn't, there is the possibility that we previously had an insn
10162 that clobbered some register as a side effect, but the combined
10163 insn doesn't need to do that. So try once more without the clobbers
10164 unless this represents an ASM insn. */
10166 if (insn_code_number < 0 && ! check_asm_operands (pat)
10167 && GET_CODE (pat) == PARALLEL)
10171 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
10172 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
10175 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
10179 SUBST_INT (XVECLEN (pat, 0), pos);
10182 pat = XVECEXP (pat, 0, 0);
10184 PATTERN (insn) = pat;
10185 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10186 if (dump_file && (dump_flags & TDF_DETAILS))
10188 if (insn_code_number < 0)
10189 fputs ("Failed to match this instruction:\n", dump_file);
10191 fputs ("Successfully matched this instruction:\n", dump_file);
10192 print_rtl_single (dump_file, pat);
10195 PATTERN (insn) = old_pat;
10196 REG_NOTES (insn) = old_notes;
10198 /* Recognize all noop sets, these will be killed by followup pass. */
10199 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
10200 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
10202 /* If we had any clobbers to add, make a new pattern than contains
10203 them. Then check to make sure that all of them are dead. */
10204 if (num_clobbers_to_add)
10206 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
10207 rtvec_alloc (GET_CODE (pat) == PARALLEL
10208 ? (XVECLEN (pat, 0)
10209 + num_clobbers_to_add)
10210 : num_clobbers_to_add + 1));
10212 if (GET_CODE (pat) == PARALLEL)
10213 for (i = 0; i < XVECLEN (pat, 0); i++)
10214 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
10216 XVECEXP (newpat, 0, 0) = pat;
10218 add_clobbers (newpat, insn_code_number);
10220 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
10221 i < XVECLEN (newpat, 0); i++)
10223 if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
10224 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
10226 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH)
10228 gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)));
10229 notes = alloc_reg_note (REG_UNUSED,
10230 XEXP (XVECEXP (newpat, 0, i), 0), notes);
10239 return insn_code_number;
10242 /* Like gen_lowpart_general but for use by combine. In combine it
10243 is not possible to create any new pseudoregs. However, it is
10244 safe to create invalid memory addresses, because combine will
10245 try to recognize them and all they will do is make the combine
10248 If for some reason this cannot do its job, an rtx
10249 (clobber (const_int 0)) is returned.
10250 An insn containing that will not be recognized. */
10253 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
10255 enum machine_mode imode = GET_MODE (x);
10256 unsigned int osize = GET_MODE_SIZE (omode);
10257 unsigned int isize = GET_MODE_SIZE (imode);
10260 if (omode == imode)
10263 /* Return identity if this is a CONST or symbolic reference. */
10265 && (GET_CODE (x) == CONST
10266 || GET_CODE (x) == SYMBOL_REF
10267 || GET_CODE (x) == LABEL_REF))
10270 /* We can only support MODE being wider than a word if X is a
10271 constant integer or has a mode the same size. */
10272 if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
10273 && ! ((imode == VOIDmode
10274 && (CONST_INT_P (x)
10275 || GET_CODE (x) == CONST_DOUBLE))
10276 || isize == osize))
10279 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10280 won't know what to do. So we will strip off the SUBREG here and
10281 process normally. */
10282 if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
10284 x = SUBREG_REG (x);
10286 /* For use in case we fall down into the address adjustments
10287 further below, we need to adjust the known mode and size of
10288 x; imode and isize, since we just adjusted x. */
10289 imode = GET_MODE (x);
10291 if (imode == omode)
10294 isize = GET_MODE_SIZE (imode);
10297 result = gen_lowpart_common (omode, x);
10306 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10308 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
10311 /* If we want to refer to something bigger than the original memref,
10312 generate a paradoxical subreg instead. That will force a reload
10313 of the original memref X. */
10315 return gen_rtx_SUBREG (omode, x, 0);
10317 if (WORDS_BIG_ENDIAN)
10318 offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
10320 /* Adjust the address so that the address-after-the-data is
10322 if (BYTES_BIG_ENDIAN)
10323 offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
10325 return adjust_address_nv (x, omode, offset);
10328 /* If X is a comparison operator, rewrite it in a new mode. This
10329 probably won't match, but may allow further simplifications. */
10330 else if (COMPARISON_P (x))
10331 return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
10333 /* If we couldn't simplify X any other way, just enclose it in a
10334 SUBREG. Normally, this SUBREG won't match, but some patterns may
10335 include an explicit SUBREG or we may simplify it further in combine. */
10341 offset = subreg_lowpart_offset (omode, imode);
10342 if (imode == VOIDmode)
10344 imode = int_mode_for_mode (omode);
10345 x = gen_lowpart_common (imode, x);
10349 res = simplify_gen_subreg (omode, x, imode, offset);
10355 return gen_rtx_CLOBBER (omode, const0_rtx);
10358 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10359 comparison code that will be tested.
10361 The result is a possibly different comparison code to use. *POP0 and
10362 *POP1 may be updated.
10364 It is possible that we might detect that a comparison is either always
10365 true or always false. However, we do not perform general constant
10366 folding in combine, so this knowledge isn't useful. Such tautologies
10367 should have been detected earlier. Hence we ignore all such cases. */
10369 static enum rtx_code
10370 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
10376 enum machine_mode mode, tmode;
10378 /* Try a few ways of applying the same transformation to both operands. */
10381 #ifndef WORD_REGISTER_OPERATIONS
10382 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10383 so check specially. */
10384 if (code != GTU && code != GEU && code != LTU && code != LEU
10385 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
10386 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10387 && GET_CODE (XEXP (op1, 0)) == ASHIFT
10388 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
10389 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
10390 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
10391 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
10392 && CONST_INT_P (XEXP (op0, 1))
10393 && XEXP (op0, 1) == XEXP (op1, 1)
10394 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10395 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
10396 && (INTVAL (XEXP (op0, 1))
10397 == (GET_MODE_BITSIZE (GET_MODE (op0))
10398 - (GET_MODE_BITSIZE
10399 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
10401 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
10402 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
10406 /* If both operands are the same constant shift, see if we can ignore the
10407 shift. We can if the shift is a rotate or if the bits shifted out of
10408 this shift are known to be zero for both inputs and if the type of
10409 comparison is compatible with the shift. */
10410 if (GET_CODE (op0) == GET_CODE (op1)
10411 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10412 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
10413 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
10414 && (code != GT && code != LT && code != GE && code != LE))
10415 || (GET_CODE (op0) == ASHIFTRT
10416 && (code != GTU && code != LTU
10417 && code != GEU && code != LEU)))
10418 && CONST_INT_P (XEXP (op0, 1))
10419 && INTVAL (XEXP (op0, 1)) >= 0
10420 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10421 && XEXP (op0, 1) == XEXP (op1, 1))
10423 enum machine_mode mode = GET_MODE (op0);
10424 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10425 int shift_count = INTVAL (XEXP (op0, 1));
10427 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
10428 mask &= (mask >> shift_count) << shift_count;
10429 else if (GET_CODE (op0) == ASHIFT)
10430 mask = (mask & (mask << shift_count)) >> shift_count;
10432 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
10433 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
10434 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
10439 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10440 SUBREGs are of the same mode, and, in both cases, the AND would
10441 be redundant if the comparison was done in the narrower mode,
10442 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10443 and the operand's possibly nonzero bits are 0xffffff01; in that case
10444 if we only care about QImode, we don't need the AND). This case
10445 occurs if the output mode of an scc insn is not SImode and
10446 STORE_FLAG_VALUE == 1 (e.g., the 386).
10448 Similarly, check for a case where the AND's are ZERO_EXTEND
10449 operations from some narrower mode even though a SUBREG is not
10452 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
10453 && CONST_INT_P (XEXP (op0, 1))
10454 && CONST_INT_P (XEXP (op1, 1)))
10456 rtx inner_op0 = XEXP (op0, 0);
10457 rtx inner_op1 = XEXP (op1, 0);
10458 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
10459 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
10462 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
10463 && (GET_MODE_SIZE (GET_MODE (inner_op0))
10464 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
10465 && (GET_MODE (SUBREG_REG (inner_op0))
10466 == GET_MODE (SUBREG_REG (inner_op1)))
10467 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
10468 <= HOST_BITS_PER_WIDE_INT)
10469 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
10470 GET_MODE (SUBREG_REG (inner_op0)))))
10471 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
10472 GET_MODE (SUBREG_REG (inner_op1))))))
10474 op0 = SUBREG_REG (inner_op0);
10475 op1 = SUBREG_REG (inner_op1);
10477 /* The resulting comparison is always unsigned since we masked
10478 off the original sign bit. */
10479 code = unsigned_condition (code);
10485 for (tmode = GET_CLASS_NARROWEST_MODE
10486 (GET_MODE_CLASS (GET_MODE (op0)));
10487 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
10488 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
10490 op0 = gen_lowpart (tmode, inner_op0);
10491 op1 = gen_lowpart (tmode, inner_op1);
10492 code = unsigned_condition (code);
10501 /* If both operands are NOT, we can strip off the outer operation
10502 and adjust the comparison code for swapped operands; similarly for
10503 NEG, except that this must be an equality comparison. */
10504 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
10505 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
10506 && (code == EQ || code == NE)))
10507 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
10513 /* If the first operand is a constant, swap the operands and adjust the
10514 comparison code appropriately, but don't do this if the second operand
10515 is already a constant integer. */
10516 if (swap_commutative_operands_p (op0, op1))
10518 tem = op0, op0 = op1, op1 = tem;
10519 code = swap_condition (code);
10522 /* We now enter a loop during which we will try to simplify the comparison.
10523 For the most part, we only are concerned with comparisons with zero,
10524 but some things may really be comparisons with zero but not start
10525 out looking that way. */
10527 while (CONST_INT_P (op1))
10529 enum machine_mode mode = GET_MODE (op0);
10530 unsigned int mode_width = GET_MODE_BITSIZE (mode);
10531 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10532 int equality_comparison_p;
10533 int sign_bit_comparison_p;
10534 int unsigned_comparison_p;
10535 HOST_WIDE_INT const_op;
10537 /* We only want to handle integral modes. This catches VOIDmode,
10538 CCmode, and the floating-point modes. An exception is that we
10539 can handle VOIDmode if OP0 is a COMPARE or a comparison
10542 if (GET_MODE_CLASS (mode) != MODE_INT
10543 && ! (mode == VOIDmode
10544 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
10547 /* Get the constant we are comparing against and turn off all bits
10548 not on in our mode. */
10549 const_op = INTVAL (op1);
10550 if (mode != VOIDmode)
10551 const_op = trunc_int_for_mode (const_op, mode);
10552 op1 = GEN_INT (const_op);
10554 /* If we are comparing against a constant power of two and the value
10555 being compared can only have that single bit nonzero (e.g., it was
10556 `and'ed with that bit), we can replace this with a comparison
10559 && (code == EQ || code == NE || code == GE || code == GEU
10560 || code == LT || code == LTU)
10561 && mode_width <= HOST_BITS_PER_WIDE_INT
10562 && exact_log2 (const_op) >= 0
10563 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10565 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10566 op1 = const0_rtx, const_op = 0;
10569 /* Similarly, if we are comparing a value known to be either -1 or
10570 0 with -1, change it to the opposite comparison against zero. */
10573 && (code == EQ || code == NE || code == GT || code == LE
10574 || code == GEU || code == LTU)
10575 && num_sign_bit_copies (op0, mode) == mode_width)
10577 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10578 op1 = const0_rtx, const_op = 0;
10581 /* Do some canonicalizations based on the comparison code. We prefer
10582 comparisons against zero and then prefer equality comparisons.
10583 If we can reduce the size of a constant, we will do that too. */
10588 /* < C is equivalent to <= (C - 1) */
10592 op1 = GEN_INT (const_op);
10594 /* ... fall through to LE case below. */
10600 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10604 op1 = GEN_INT (const_op);
10608 /* If we are doing a <= 0 comparison on a value known to have
10609 a zero sign bit, we can replace this with == 0. */
10610 else if (const_op == 0
10611 && mode_width <= HOST_BITS_PER_WIDE_INT
10612 && (nonzero_bits (op0, mode)
10613 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10618 /* >= C is equivalent to > (C - 1). */
10622 op1 = GEN_INT (const_op);
10624 /* ... fall through to GT below. */
10630 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10634 op1 = GEN_INT (const_op);
10638 /* If we are doing a > 0 comparison on a value known to have
10639 a zero sign bit, we can replace this with != 0. */
10640 else if (const_op == 0
10641 && mode_width <= HOST_BITS_PER_WIDE_INT
10642 && (nonzero_bits (op0, mode)
10643 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10648 /* < C is equivalent to <= (C - 1). */
10652 op1 = GEN_INT (const_op);
10654 /* ... fall through ... */
10657 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10658 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10659 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10661 const_op = 0, op1 = const0_rtx;
10669 /* unsigned <= 0 is equivalent to == 0 */
10673 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10674 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10675 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10677 const_op = 0, op1 = const0_rtx;
10683 /* >= C is equivalent to > (C - 1). */
10687 op1 = GEN_INT (const_op);
10689 /* ... fall through ... */
10692 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10693 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10694 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10696 const_op = 0, op1 = const0_rtx;
10704 /* unsigned > 0 is equivalent to != 0 */
10708 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10709 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10710 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10712 const_op = 0, op1 = const0_rtx;
10721 /* Compute some predicates to simplify code below. */
10723 equality_comparison_p = (code == EQ || code == NE);
10724 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
10725 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
10728 /* If this is a sign bit comparison and we can do arithmetic in
10729 MODE, say that we will only be needing the sign bit of OP0. */
10730 if (sign_bit_comparison_p
10731 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10732 op0 = force_to_mode (op0, mode,
10734 << (GET_MODE_BITSIZE (mode) - 1)),
10737 /* Now try cases based on the opcode of OP0. If none of the cases
10738 does a "continue", we exit this loop immediately after the
10741 switch (GET_CODE (op0))
10744 /* If we are extracting a single bit from a variable position in
10745 a constant that has only a single bit set and are comparing it
10746 with zero, we can convert this into an equality comparison
10747 between the position and the location of the single bit. */
10748 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
10749 have already reduced the shift count modulo the word size. */
10750 if (!SHIFT_COUNT_TRUNCATED
10751 && CONST_INT_P (XEXP (op0, 0))
10752 && XEXP (op0, 1) == const1_rtx
10753 && equality_comparison_p && const_op == 0
10754 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
10756 if (BITS_BIG_ENDIAN)
10758 enum machine_mode new_mode
10759 = mode_for_extraction (EP_extzv, 1);
10760 if (new_mode == MAX_MACHINE_MODE)
10761 i = BITS_PER_WORD - 1 - i;
10765 i = (GET_MODE_BITSIZE (mode) - 1 - i);
10769 op0 = XEXP (op0, 2);
10773 /* Result is nonzero iff shift count is equal to I. */
10774 code = reverse_condition (code);
10778 /* ... fall through ... */
10781 tem = expand_compound_operation (op0);
10790 /* If testing for equality, we can take the NOT of the constant. */
10791 if (equality_comparison_p
10792 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10794 op0 = XEXP (op0, 0);
10799 /* If just looking at the sign bit, reverse the sense of the
10801 if (sign_bit_comparison_p)
10803 op0 = XEXP (op0, 0);
10804 code = (code == GE ? LT : GE);
10810 /* If testing for equality, we can take the NEG of the constant. */
10811 if (equality_comparison_p
10812 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10814 op0 = XEXP (op0, 0);
10819 /* The remaining cases only apply to comparisons with zero. */
10823 /* When X is ABS or is known positive,
10824 (neg X) is < 0 if and only if X != 0. */
10826 if (sign_bit_comparison_p
10827 && (GET_CODE (XEXP (op0, 0)) == ABS
10828 || (mode_width <= HOST_BITS_PER_WIDE_INT
10829 && (nonzero_bits (XEXP (op0, 0), mode)
10830 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10832 op0 = XEXP (op0, 0);
10833 code = (code == LT ? NE : EQ);
10837 /* If we have NEG of something whose two high-order bits are the
10838 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10839 if (num_sign_bit_copies (op0, mode) >= 2)
10841 op0 = XEXP (op0, 0);
10842 code = swap_condition (code);
10848 /* If we are testing equality and our count is a constant, we
10849 can perform the inverse operation on our RHS. */
10850 if (equality_comparison_p && CONST_INT_P (XEXP (op0, 1))
10851 && (tem = simplify_binary_operation (ROTATERT, mode,
10852 op1, XEXP (op0, 1))) != 0)
10854 op0 = XEXP (op0, 0);
10859 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10860 a particular bit. Convert it to an AND of a constant of that
10861 bit. This will be converted into a ZERO_EXTRACT. */
10862 if (const_op == 0 && sign_bit_comparison_p
10863 && CONST_INT_P (XEXP (op0, 1))
10864 && mode_width <= HOST_BITS_PER_WIDE_INT)
10866 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10869 - INTVAL (XEXP (op0, 1)))));
10870 code = (code == LT ? NE : EQ);
10874 /* Fall through. */
10877 /* ABS is ignorable inside an equality comparison with zero. */
10878 if (const_op == 0 && equality_comparison_p)
10880 op0 = XEXP (op0, 0);
10886 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
10887 (compare FOO CONST) if CONST fits in FOO's mode and we
10888 are either testing inequality or have an unsigned
10889 comparison with ZERO_EXTEND or a signed comparison with
10890 SIGN_EXTEND. But don't do it if we don't have a compare
10891 insn of the given mode, since we'd have to revert it
10892 later on, and then we wouldn't know whether to sign- or
10894 mode = GET_MODE (XEXP (op0, 0));
10895 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10896 && ! unsigned_comparison_p
10897 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10898 && ((unsigned HOST_WIDE_INT) const_op
10899 < (((unsigned HOST_WIDE_INT) 1
10900 << (GET_MODE_BITSIZE (mode) - 1))))
10901 && have_insn_for (COMPARE, mode))
10903 op0 = XEXP (op0, 0);
10909 /* Check for the case where we are comparing A - C1 with C2, that is
10911 (subreg:MODE (plus (A) (-C1))) op (C2)
10913 with C1 a constant, and try to lift the SUBREG, i.e. to do the
10914 comparison in the wider mode. One of the following two conditions
10915 must be true in order for this to be valid:
10917 1. The mode extension results in the same bit pattern being added
10918 on both sides and the comparison is equality or unsigned. As
10919 C2 has been truncated to fit in MODE, the pattern can only be
10922 2. The mode extension results in the sign bit being copied on
10925 The difficulty here is that we have predicates for A but not for
10926 (A - C1) so we need to check that C1 is within proper bounds so
10927 as to perturbate A as little as possible. */
10929 if (mode_width <= HOST_BITS_PER_WIDE_INT
10930 && subreg_lowpart_p (op0)
10931 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) > mode_width
10932 && GET_CODE (SUBREG_REG (op0)) == PLUS
10933 && CONST_INT_P (XEXP (SUBREG_REG (op0), 1)))
10935 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
10936 rtx a = XEXP (SUBREG_REG (op0), 0);
10937 HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
10940 && (unsigned HOST_WIDE_INT) c1
10941 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
10942 && (equality_comparison_p || unsigned_comparison_p)
10943 /* (A - C1) zero-extends if it is positive and sign-extends
10944 if it is negative, C2 both zero- and sign-extends. */
10945 && ((0 == (nonzero_bits (a, inner_mode)
10946 & ~GET_MODE_MASK (mode))
10948 /* (A - C1) sign-extends if it is positive and 1-extends
10949 if it is negative, C2 both sign- and 1-extends. */
10950 || (num_sign_bit_copies (a, inner_mode)
10951 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10954 || ((unsigned HOST_WIDE_INT) c1
10955 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
10956 /* (A - C1) always sign-extends, like C2. */
10957 && num_sign_bit_copies (a, inner_mode)
10958 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10959 - (mode_width - 1))))
10961 op0 = SUBREG_REG (op0);
10966 /* If the inner mode is narrower and we are extracting the low part,
10967 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10968 if (subreg_lowpart_p (op0)
10969 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10970 /* Fall through */ ;
10974 /* ... fall through ... */
10977 mode = GET_MODE (XEXP (op0, 0));
10978 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10979 && (unsigned_comparison_p || equality_comparison_p)
10980 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10981 && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode))
10982 && have_insn_for (COMPARE, mode))
10984 op0 = XEXP (op0, 0);
10990 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10991 this for equality comparisons due to pathological cases involving
10993 if (equality_comparison_p
10994 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10995 op1, XEXP (op0, 1))))
10997 op0 = XEXP (op0, 0);
11002 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
11003 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
11004 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
11006 op0 = XEXP (XEXP (op0, 0), 0);
11007 code = (code == LT ? EQ : NE);
11013 /* We used to optimize signed comparisons against zero, but that
11014 was incorrect. Unsigned comparisons against zero (GTU, LEU)
11015 arrive here as equality comparisons, or (GEU, LTU) are
11016 optimized away. No need to special-case them. */
11018 /* (eq (minus A B) C) -> (eq A (plus B C)) or
11019 (eq B (minus A C)), whichever simplifies. We can only do
11020 this for equality comparisons due to pathological cases involving
11022 if (equality_comparison_p
11023 && 0 != (tem = simplify_binary_operation (PLUS, mode,
11024 XEXP (op0, 1), op1)))
11026 op0 = XEXP (op0, 0);
11031 if (equality_comparison_p
11032 && 0 != (tem = simplify_binary_operation (MINUS, mode,
11033 XEXP (op0, 0), op1)))
11035 op0 = XEXP (op0, 1);
11040 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11041 of bits in X minus 1, is one iff X > 0. */
11042 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
11043 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11044 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
11046 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11048 op0 = XEXP (op0, 1);
11049 code = (code == GE ? LE : GT);
11055 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11056 if C is zero or B is a constant. */
11057 if (equality_comparison_p
11058 && 0 != (tem = simplify_binary_operation (XOR, mode,
11059 XEXP (op0, 1), op1)))
11061 op0 = XEXP (op0, 0);
11068 case UNEQ: case LTGT:
11069 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
11070 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
11071 case UNORDERED: case ORDERED:
11072 /* We can't do anything if OP0 is a condition code value, rather
11073 than an actual data value. */
11075 || CC0_P (XEXP (op0, 0))
11076 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
11079 /* Get the two operands being compared. */
11080 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
11081 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
11083 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
11085 /* Check for the cases where we simply want the result of the
11086 earlier test or the opposite of that result. */
11087 if (code == NE || code == EQ
11088 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
11089 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11090 && (STORE_FLAG_VALUE
11091 & (((HOST_WIDE_INT) 1
11092 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
11093 && (code == LT || code == GE)))
11095 enum rtx_code new_code;
11096 if (code == LT || code == NE)
11097 new_code = GET_CODE (op0);
11099 new_code = reversed_comparison_code (op0, NULL);
11101 if (new_code != UNKNOWN)
11112 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11114 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
11115 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
11116 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11118 op0 = XEXP (op0, 1);
11119 code = (code == GE ? GT : LE);
11125 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11126 will be converted to a ZERO_EXTRACT later. */
11127 if (const_op == 0 && equality_comparison_p
11128 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11129 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
11131 op0 = simplify_and_const_int
11132 (NULL_RTX, mode, gen_rtx_LSHIFTRT (mode,
11134 XEXP (XEXP (op0, 0), 1)),
11135 (HOST_WIDE_INT) 1);
11139 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11140 zero and X is a comparison and C1 and C2 describe only bits set
11141 in STORE_FLAG_VALUE, we can compare with X. */
11142 if (const_op == 0 && equality_comparison_p
11143 && mode_width <= HOST_BITS_PER_WIDE_INT
11144 && CONST_INT_P (XEXP (op0, 1))
11145 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
11146 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11147 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
11148 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
11150 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11151 << INTVAL (XEXP (XEXP (op0, 0), 1)));
11152 if ((~STORE_FLAG_VALUE & mask) == 0
11153 && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
11154 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
11155 && COMPARISON_P (tem))))
11157 op0 = XEXP (XEXP (op0, 0), 0);
11162 /* If we are doing an equality comparison of an AND of a bit equal
11163 to the sign bit, replace this with a LT or GE comparison of
11164 the underlying value. */
11165 if (equality_comparison_p
11167 && CONST_INT_P (XEXP (op0, 1))
11168 && mode_width <= HOST_BITS_PER_WIDE_INT
11169 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11170 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11172 op0 = XEXP (op0, 0);
11173 code = (code == EQ ? GE : LT);
11177 /* If this AND operation is really a ZERO_EXTEND from a narrower
11178 mode, the constant fits within that mode, and this is either an
11179 equality or unsigned comparison, try to do this comparison in
11184 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11185 -> (ne:DI (reg:SI 4) (const_int 0))
11187 unless TRULY_NOOP_TRUNCATION allows it or the register is
11188 known to hold a value of the required mode the
11189 transformation is invalid. */
11190 if ((equality_comparison_p || unsigned_comparison_p)
11191 && CONST_INT_P (XEXP (op0, 1))
11192 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
11193 & GET_MODE_MASK (mode))
11195 && const_op >> i == 0
11196 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode
11197 && (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
11198 GET_MODE_BITSIZE (GET_MODE (op0)))
11199 || (REG_P (XEXP (op0, 0))
11200 && reg_truncated_to_mode (tmode, XEXP (op0, 0)))))
11202 op0 = gen_lowpart (tmode, XEXP (op0, 0));
11206 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11207 fits in both M1 and M2 and the SUBREG is either paradoxical
11208 or represents the low part, permute the SUBREG and the AND
11210 if (GET_CODE (XEXP (op0, 0)) == SUBREG)
11212 unsigned HOST_WIDE_INT c1;
11213 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
11214 /* Require an integral mode, to avoid creating something like
11216 if (SCALAR_INT_MODE_P (tmode)
11217 /* It is unsafe to commute the AND into the SUBREG if the
11218 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11219 not defined. As originally written the upper bits
11220 have a defined value due to the AND operation.
11221 However, if we commute the AND inside the SUBREG then
11222 they no longer have defined values and the meaning of
11223 the code has been changed. */
11225 #ifdef WORD_REGISTER_OPERATIONS
11226 || (mode_width > GET_MODE_BITSIZE (tmode)
11227 && mode_width <= BITS_PER_WORD)
11229 || (mode_width <= GET_MODE_BITSIZE (tmode)
11230 && subreg_lowpart_p (XEXP (op0, 0))))
11231 && CONST_INT_P (XEXP (op0, 1))
11232 && mode_width <= HOST_BITS_PER_WIDE_INT
11233 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
11234 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
11235 && (c1 & ~GET_MODE_MASK (tmode)) == 0
11237 && c1 != GET_MODE_MASK (tmode))
11239 op0 = simplify_gen_binary (AND, tmode,
11240 SUBREG_REG (XEXP (op0, 0)),
11241 gen_int_mode (c1, tmode));
11242 op0 = gen_lowpart (mode, op0);
11247 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
11248 if (const_op == 0 && equality_comparison_p
11249 && XEXP (op0, 1) == const1_rtx
11250 && GET_CODE (XEXP (op0, 0)) == NOT)
11252 op0 = simplify_and_const_int
11253 (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1);
11254 code = (code == NE ? EQ : NE);
11258 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11259 (eq (and (lshiftrt X) 1) 0).
11260 Also handle the case where (not X) is expressed using xor. */
11261 if (const_op == 0 && equality_comparison_p
11262 && XEXP (op0, 1) == const1_rtx
11263 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
11265 rtx shift_op = XEXP (XEXP (op0, 0), 0);
11266 rtx shift_count = XEXP (XEXP (op0, 0), 1);
11268 if (GET_CODE (shift_op) == NOT
11269 || (GET_CODE (shift_op) == XOR
11270 && CONST_INT_P (XEXP (shift_op, 1))
11271 && CONST_INT_P (shift_count)
11272 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
11273 && (INTVAL (XEXP (shift_op, 1))
11274 == (HOST_WIDE_INT) 1 << INTVAL (shift_count))))
11276 op0 = simplify_and_const_int
11278 gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count),
11279 (HOST_WIDE_INT) 1);
11280 code = (code == NE ? EQ : NE);
11287 /* If we have (compare (ashift FOO N) (const_int C)) and
11288 the high order N bits of FOO (N+1 if an inequality comparison)
11289 are known to be zero, we can do this by comparing FOO with C
11290 shifted right N bits so long as the low-order N bits of C are
11292 if (CONST_INT_P (XEXP (op0, 1))
11293 && INTVAL (XEXP (op0, 1)) >= 0
11294 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
11295 < HOST_BITS_PER_WIDE_INT)
11297 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
11298 && mode_width <= HOST_BITS_PER_WIDE_INT
11299 && (nonzero_bits (XEXP (op0, 0), mode)
11300 & ~(mask >> (INTVAL (XEXP (op0, 1))
11301 + ! equality_comparison_p))) == 0)
11303 /* We must perform a logical shift, not an arithmetic one,
11304 as we want the top N bits of C to be zero. */
11305 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
11307 temp >>= INTVAL (XEXP (op0, 1));
11308 op1 = gen_int_mode (temp, mode);
11309 op0 = XEXP (op0, 0);
11313 /* If we are doing a sign bit comparison, it means we are testing
11314 a particular bit. Convert it to the appropriate AND. */
11315 if (sign_bit_comparison_p && CONST_INT_P (XEXP (op0, 1))
11316 && mode_width <= HOST_BITS_PER_WIDE_INT)
11318 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11321 - INTVAL (XEXP (op0, 1)))));
11322 code = (code == LT ? NE : EQ);
11326 /* If this an equality comparison with zero and we are shifting
11327 the low bit to the sign bit, we can convert this to an AND of the
11329 if (const_op == 0 && equality_comparison_p
11330 && CONST_INT_P (XEXP (op0, 1))
11331 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11334 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11335 (HOST_WIDE_INT) 1);
11341 /* If this is an equality comparison with zero, we can do this
11342 as a logical shift, which might be much simpler. */
11343 if (equality_comparison_p && const_op == 0
11344 && CONST_INT_P (XEXP (op0, 1)))
11346 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
11348 INTVAL (XEXP (op0, 1)));
11352 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11353 do the comparison in a narrower mode. */
11354 if (! unsigned_comparison_p
11355 && CONST_INT_P (XEXP (op0, 1))
11356 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11357 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11358 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11359 MODE_INT, 1)) != BLKmode
11360 && (((unsigned HOST_WIDE_INT) const_op
11361 + (GET_MODE_MASK (tmode) >> 1) + 1)
11362 <= GET_MODE_MASK (tmode)))
11364 op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
11368 /* Likewise if OP0 is a PLUS of a sign extension with a
11369 constant, which is usually represented with the PLUS
11370 between the shifts. */
11371 if (! unsigned_comparison_p
11372 && CONST_INT_P (XEXP (op0, 1))
11373 && GET_CODE (XEXP (op0, 0)) == PLUS
11374 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11375 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
11376 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
11377 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11378 MODE_INT, 1)) != BLKmode
11379 && (((unsigned HOST_WIDE_INT) const_op
11380 + (GET_MODE_MASK (tmode) >> 1) + 1)
11381 <= GET_MODE_MASK (tmode)))
11383 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
11384 rtx add_const = XEXP (XEXP (op0, 0), 1);
11385 rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
11386 add_const, XEXP (op0, 1));
11388 op0 = simplify_gen_binary (PLUS, tmode,
11389 gen_lowpart (tmode, inner),
11394 /* ... fall through ... */
11396 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11397 the low order N bits of FOO are known to be zero, we can do this
11398 by comparing FOO with C shifted left N bits so long as no
11399 overflow occurs. */
11400 if (CONST_INT_P (XEXP (op0, 1))
11401 && INTVAL (XEXP (op0, 1)) >= 0
11402 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11403 && mode_width <= HOST_BITS_PER_WIDE_INT
11404 && (nonzero_bits (XEXP (op0, 0), mode)
11405 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
11406 && (((unsigned HOST_WIDE_INT) const_op
11407 + (GET_CODE (op0) != LSHIFTRT
11408 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
11411 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
11413 /* If the shift was logical, then we must make the condition
11415 if (GET_CODE (op0) == LSHIFTRT)
11416 code = unsigned_condition (code);
11418 const_op <<= INTVAL (XEXP (op0, 1));
11419 op1 = GEN_INT (const_op);
11420 op0 = XEXP (op0, 0);
11424 /* If we are using this shift to extract just the sign bit, we
11425 can replace this with an LT or GE comparison. */
11427 && (equality_comparison_p || sign_bit_comparison_p)
11428 && CONST_INT_P (XEXP (op0, 1))
11429 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11432 op0 = XEXP (op0, 0);
11433 code = (code == NE || code == GT ? LT : GE);
11445 /* Now make any compound operations involved in this comparison. Then,
11446 check for an outmost SUBREG on OP0 that is not doing anything or is
11447 paradoxical. The latter transformation must only be performed when
11448 it is known that the "extra" bits will be the same in op0 and op1 or
11449 that they don't matter. There are three cases to consider:
11451 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11452 care bits and we can assume they have any convenient value. So
11453 making the transformation is safe.
11455 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11456 In this case the upper bits of op0 are undefined. We should not make
11457 the simplification in that case as we do not know the contents of
11460 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11461 UNKNOWN. In that case we know those bits are zeros or ones. We must
11462 also be sure that they are the same as the upper bits of op1.
11464 We can never remove a SUBREG for a non-equality comparison because
11465 the sign bit is in a different place in the underlying object. */
11467 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
11468 op1 = make_compound_operation (op1, SET);
11470 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11471 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11472 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
11473 && (code == NE || code == EQ))
11475 if (GET_MODE_SIZE (GET_MODE (op0))
11476 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
11478 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11480 if (REG_P (SUBREG_REG (op0)))
11482 op0 = SUBREG_REG (op0);
11483 op1 = gen_lowpart (GET_MODE (op0), op1);
11486 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
11487 <= HOST_BITS_PER_WIDE_INT)
11488 && (nonzero_bits (SUBREG_REG (op0),
11489 GET_MODE (SUBREG_REG (op0)))
11490 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11492 tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
11494 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11495 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11496 op0 = SUBREG_REG (op0), op1 = tem;
11500 /* We now do the opposite procedure: Some machines don't have compare
11501 insns in all modes. If OP0's mode is an integer mode smaller than a
11502 word and we can't do a compare in that mode, see if there is a larger
11503 mode for which we can do the compare. There are a number of cases in
11504 which we can use the wider mode. */
11506 mode = GET_MODE (op0);
11507 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11508 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11509 && ! have_insn_for (COMPARE, mode))
11510 for (tmode = GET_MODE_WIDER_MODE (mode);
11512 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
11513 tmode = GET_MODE_WIDER_MODE (tmode))
11514 if (have_insn_for (COMPARE, tmode))
11518 /* If this is a test for negative, we can make an explicit
11519 test of the sign bit. Test this first so we can use
11520 a paradoxical subreg to extend OP0. */
11522 if (op1 == const0_rtx && (code == LT || code == GE)
11523 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11525 op0 = simplify_gen_binary (AND, tmode,
11526 gen_lowpart (tmode, op0),
11527 GEN_INT ((HOST_WIDE_INT) 1
11528 << (GET_MODE_BITSIZE (mode)
11530 code = (code == LT) ? NE : EQ;
11534 /* If the only nonzero bits in OP0 and OP1 are those in the
11535 narrower mode and this is an equality or unsigned comparison,
11536 we can use the wider mode. Similarly for sign-extended
11537 values, in which case it is true for all comparisons. */
11538 zero_extended = ((code == EQ || code == NE
11539 || code == GEU || code == GTU
11540 || code == LEU || code == LTU)
11541 && (nonzero_bits (op0, tmode)
11542 & ~GET_MODE_MASK (mode)) == 0
11543 && ((CONST_INT_P (op1)
11544 || (nonzero_bits (op1, tmode)
11545 & ~GET_MODE_MASK (mode)) == 0)));
11548 || ((num_sign_bit_copies (op0, tmode)
11549 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11550 - GET_MODE_BITSIZE (mode)))
11551 && (num_sign_bit_copies (op1, tmode)
11552 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11553 - GET_MODE_BITSIZE (mode)))))
11555 /* If OP0 is an AND and we don't have an AND in MODE either,
11556 make a new AND in the proper mode. */
11557 if (GET_CODE (op0) == AND
11558 && !have_insn_for (AND, mode))
11559 op0 = simplify_gen_binary (AND, tmode,
11560 gen_lowpart (tmode,
11562 gen_lowpart (tmode,
11568 op0 = simplify_gen_unary (ZERO_EXTEND, tmode, op0, mode);
11569 op1 = simplify_gen_unary (ZERO_EXTEND, tmode, op1, mode);
11573 op0 = simplify_gen_unary (SIGN_EXTEND, tmode, op0, mode);
11574 op1 = simplify_gen_unary (SIGN_EXTEND, tmode, op1, mode);
11581 #ifdef CANONICALIZE_COMPARISON
11582 /* If this machine only supports a subset of valid comparisons, see if we
11583 can convert an unsupported one into a supported one. */
11584 CANONICALIZE_COMPARISON (code, op0, op1);
11593 /* Utility function for record_value_for_reg. Count number of
11598 enum rtx_code code = GET_CODE (x);
11602 if (GET_RTX_CLASS (code) == '2'
11603 || GET_RTX_CLASS (code) == 'c')
11605 rtx x0 = XEXP (x, 0);
11606 rtx x1 = XEXP (x, 1);
11609 return 1 + 2 * count_rtxs (x0);
11611 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
11612 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
11613 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11614 return 2 + 2 * count_rtxs (x0)
11615 + count_rtxs (x == XEXP (x1, 0)
11616 ? XEXP (x1, 1) : XEXP (x1, 0));
11618 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
11619 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
11620 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11621 return 2 + 2 * count_rtxs (x1)
11622 + count_rtxs (x == XEXP (x0, 0)
11623 ? XEXP (x0, 1) : XEXP (x0, 0));
11626 fmt = GET_RTX_FORMAT (code);
11627 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11629 ret += count_rtxs (XEXP (x, i));
11630 else if (fmt[i] == 'E')
11631 for (j = 0; j < XVECLEN (x, i); j++)
11632 ret += count_rtxs (XVECEXP (x, i, j));
11637 /* Utility function for following routine. Called when X is part of a value
11638 being stored into last_set_value. Sets last_set_table_tick
11639 for each register mentioned. Similar to mention_regs in cse.c */
11642 update_table_tick (rtx x)
11644 enum rtx_code code = GET_CODE (x);
11645 const char *fmt = GET_RTX_FORMAT (code);
11650 unsigned int regno = REGNO (x);
11651 unsigned int endregno = END_REGNO (x);
11654 for (r = regno; r < endregno; r++)
11656 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, r);
11657 rsp->last_set_table_tick = label_tick;
11663 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11666 /* Check for identical subexpressions. If x contains
11667 identical subexpression we only have to traverse one of
11669 if (i == 0 && ARITHMETIC_P (x))
11671 /* Note that at this point x1 has already been
11673 rtx x0 = XEXP (x, 0);
11674 rtx x1 = XEXP (x, 1);
11676 /* If x0 and x1 are identical then there is no need to
11681 /* If x0 is identical to a subexpression of x1 then while
11682 processing x1, x0 has already been processed. Thus we
11683 are done with x. */
11684 if (ARITHMETIC_P (x1)
11685 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11688 /* If x1 is identical to a subexpression of x0 then we
11689 still have to process the rest of x0. */
11690 if (ARITHMETIC_P (x0)
11691 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11693 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
11698 update_table_tick (XEXP (x, i));
11700 else if (fmt[i] == 'E')
11701 for (j = 0; j < XVECLEN (x, i); j++)
11702 update_table_tick (XVECEXP (x, i, j));
11705 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11706 are saying that the register is clobbered and we no longer know its
11707 value. If INSN is zero, don't update reg_stat[].last_set; this is
11708 only permitted with VALUE also zero and is used to invalidate the
11712 record_value_for_reg (rtx reg, rtx insn, rtx value)
11714 unsigned int regno = REGNO (reg);
11715 unsigned int endregno = END_REGNO (reg);
11717 reg_stat_type *rsp;
11719 /* If VALUE contains REG and we have a previous value for REG, substitute
11720 the previous value. */
11721 if (value && insn && reg_overlap_mentioned_p (reg, value))
11725 /* Set things up so get_last_value is allowed to see anything set up to
11727 subst_low_luid = DF_INSN_LUID (insn);
11728 tem = get_last_value (reg);
11730 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11731 it isn't going to be useful and will take a lot of time to process,
11732 so just use the CLOBBER. */
11736 if (ARITHMETIC_P (tem)
11737 && GET_CODE (XEXP (tem, 0)) == CLOBBER
11738 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
11739 tem = XEXP (tem, 0);
11740 else if (count_occurrences (value, reg, 1) >= 2)
11742 /* If there are two or more occurrences of REG in VALUE,
11743 prevent the value from growing too much. */
11744 if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
11745 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
11748 value = replace_rtx (copy_rtx (value), reg, tem);
11752 /* For each register modified, show we don't know its value, that
11753 we don't know about its bitwise content, that its value has been
11754 updated, and that we don't know the location of the death of the
11756 for (i = regno; i < endregno; i++)
11758 rsp = VEC_index (reg_stat_type, reg_stat, i);
11761 rsp->last_set = insn;
11763 rsp->last_set_value = 0;
11764 rsp->last_set_mode = VOIDmode;
11765 rsp->last_set_nonzero_bits = 0;
11766 rsp->last_set_sign_bit_copies = 0;
11767 rsp->last_death = 0;
11768 rsp->truncated_to_mode = VOIDmode;
11771 /* Mark registers that are being referenced in this value. */
11773 update_table_tick (value);
11775 /* Now update the status of each register being set.
11776 If someone is using this register in this block, set this register
11777 to invalid since we will get confused between the two lives in this
11778 basic block. This makes using this register always invalid. In cse, we
11779 scan the table to invalidate all entries using this register, but this
11780 is too much work for us. */
11782 for (i = regno; i < endregno; i++)
11784 rsp = VEC_index (reg_stat_type, reg_stat, i);
11785 rsp->last_set_label = label_tick;
11787 || (value && rsp->last_set_table_tick >= label_tick_ebb_start))
11788 rsp->last_set_invalid = 1;
11790 rsp->last_set_invalid = 0;
11793 /* The value being assigned might refer to X (like in "x++;"). In that
11794 case, we must replace it with (clobber (const_int 0)) to prevent
11796 rsp = VEC_index (reg_stat_type, reg_stat, regno);
11797 if (value && !get_last_value_validate (&value, insn, label_tick, 0))
11799 value = copy_rtx (value);
11800 if (!get_last_value_validate (&value, insn, label_tick, 1))
11804 /* For the main register being modified, update the value, the mode, the
11805 nonzero bits, and the number of sign bit copies. */
11807 rsp->last_set_value = value;
11811 enum machine_mode mode = GET_MODE (reg);
11812 subst_low_luid = DF_INSN_LUID (insn);
11813 rsp->last_set_mode = mode;
11814 if (GET_MODE_CLASS (mode) == MODE_INT
11815 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11816 mode = nonzero_bits_mode;
11817 rsp->last_set_nonzero_bits = nonzero_bits (value, mode);
11818 rsp->last_set_sign_bit_copies
11819 = num_sign_bit_copies (value, GET_MODE (reg));
11823 /* Called via note_stores from record_dead_and_set_regs to handle one
11824 SET or CLOBBER in an insn. DATA is the instruction in which the
11825 set is occurring. */
11828 record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
11830 rtx record_dead_insn = (rtx) data;
11832 if (GET_CODE (dest) == SUBREG)
11833 dest = SUBREG_REG (dest);
11835 if (!record_dead_insn)
11838 record_value_for_reg (dest, NULL_RTX, NULL_RTX);
11844 /* If we are setting the whole register, we know its value. Otherwise
11845 show that we don't know the value. We can handle SUBREG in
11847 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11848 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11849 else if (GET_CODE (setter) == SET
11850 && GET_CODE (SET_DEST (setter)) == SUBREG
11851 && SUBREG_REG (SET_DEST (setter)) == dest
11852 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11853 && subreg_lowpart_p (SET_DEST (setter)))
11854 record_value_for_reg (dest, record_dead_insn,
11855 gen_lowpart (GET_MODE (dest),
11856 SET_SRC (setter)));
11858 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11860 else if (MEM_P (dest)
11861 /* Ignore pushes, they clobber nothing. */
11862 && ! push_operand (dest, GET_MODE (dest)))
11863 mem_last_set = DF_INSN_LUID (record_dead_insn);
11866 /* Update the records of when each REG was most recently set or killed
11867 for the things done by INSN. This is the last thing done in processing
11868 INSN in the combiner loop.
11870 We update reg_stat[], in particular fields last_set, last_set_value,
11871 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
11872 last_death, and also the similar information mem_last_set (which insn
11873 most recently modified memory) and last_call_luid (which insn was the
11874 most recent subroutine call). */
11877 record_dead_and_set_regs (rtx insn)
11882 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11884 if (REG_NOTE_KIND (link) == REG_DEAD
11885 && REG_P (XEXP (link, 0)))
11887 unsigned int regno = REGNO (XEXP (link, 0));
11888 unsigned int endregno = END_REGNO (XEXP (link, 0));
11890 for (i = regno; i < endregno; i++)
11892 reg_stat_type *rsp;
11894 rsp = VEC_index (reg_stat_type, reg_stat, i);
11895 rsp->last_death = insn;
11898 else if (REG_NOTE_KIND (link) == REG_INC)
11899 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11904 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11905 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11907 reg_stat_type *rsp;
11909 rsp = VEC_index (reg_stat_type, reg_stat, i);
11910 rsp->last_set_invalid = 1;
11911 rsp->last_set = insn;
11912 rsp->last_set_value = 0;
11913 rsp->last_set_mode = VOIDmode;
11914 rsp->last_set_nonzero_bits = 0;
11915 rsp->last_set_sign_bit_copies = 0;
11916 rsp->last_death = 0;
11917 rsp->truncated_to_mode = VOIDmode;
11920 last_call_luid = mem_last_set = DF_INSN_LUID (insn);
11922 /* We can't combine into a call pattern. Remember, though, that
11923 the return value register is set at this LUID. We could
11924 still replace a register with the return value from the
11925 wrong subroutine call! */
11926 note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
11929 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11932 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11933 register present in the SUBREG, so for each such SUBREG go back and
11934 adjust nonzero and sign bit information of the registers that are
11935 known to have some zero/sign bits set.
11937 This is needed because when combine blows the SUBREGs away, the
11938 information on zero/sign bits is lost and further combines can be
11939 missed because of that. */
11942 record_promoted_value (rtx insn, rtx subreg)
11945 unsigned int regno = REGNO (SUBREG_REG (subreg));
11946 enum machine_mode mode = GET_MODE (subreg);
11948 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11951 for (links = LOG_LINKS (insn); links;)
11953 reg_stat_type *rsp;
11955 insn = XEXP (links, 0);
11956 set = single_set (insn);
11958 if (! set || !REG_P (SET_DEST (set))
11959 || REGNO (SET_DEST (set)) != regno
11960 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11962 links = XEXP (links, 1);
11966 rsp = VEC_index (reg_stat_type, reg_stat, regno);
11967 if (rsp->last_set == insn)
11969 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11970 rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode);
11973 if (REG_P (SET_SRC (set)))
11975 regno = REGNO (SET_SRC (set));
11976 links = LOG_LINKS (insn);
11983 /* Check if X, a register, is known to contain a value already
11984 truncated to MODE. In this case we can use a subreg to refer to
11985 the truncated value even though in the generic case we would need
11986 an explicit truncation. */
11989 reg_truncated_to_mode (enum machine_mode mode, const_rtx x)
11991 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
11992 enum machine_mode truncated = rsp->truncated_to_mode;
11995 || rsp->truncation_label < label_tick_ebb_start)
11997 if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
11999 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
12000 GET_MODE_BITSIZE (truncated)))
12005 /* Callback for for_each_rtx. If *P is a hard reg or a subreg record the mode
12006 that the register is accessed in. For non-TRULY_NOOP_TRUNCATION targets we
12007 might be able to turn a truncate into a subreg using this information.
12008 Return -1 if traversing *P is complete or 0 otherwise. */
12011 record_truncated_value (rtx *p, void *data ATTRIBUTE_UNUSED)
12014 enum machine_mode truncated_mode;
12015 reg_stat_type *rsp;
12017 if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
12019 enum machine_mode original_mode = GET_MODE (SUBREG_REG (x));
12020 truncated_mode = GET_MODE (x);
12022 if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
12025 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (truncated_mode),
12026 GET_MODE_BITSIZE (original_mode)))
12029 x = SUBREG_REG (x);
12031 /* ??? For hard-regs we now record everything. We might be able to
12032 optimize this using last_set_mode. */
12033 else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
12034 truncated_mode = GET_MODE (x);
12038 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
12039 if (rsp->truncated_to_mode == 0
12040 || rsp->truncation_label < label_tick_ebb_start
12041 || (GET_MODE_SIZE (truncated_mode)
12042 < GET_MODE_SIZE (rsp->truncated_to_mode)))
12044 rsp->truncated_to_mode = truncated_mode;
12045 rsp->truncation_label = label_tick;
12051 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12052 the modes they are used in. This can help truning TRUNCATEs into
12056 record_truncated_values (rtx *x, void *data ATTRIBUTE_UNUSED)
12058 for_each_rtx (x, record_truncated_value, NULL);
12061 /* Scan X for promoted SUBREGs. For each one found,
12062 note what it implies to the registers used in it. */
12065 check_promoted_subreg (rtx insn, rtx x)
12067 if (GET_CODE (x) == SUBREG
12068 && SUBREG_PROMOTED_VAR_P (x)
12069 && REG_P (SUBREG_REG (x)))
12070 record_promoted_value (insn, x);
12073 const char *format = GET_RTX_FORMAT (GET_CODE (x));
12076 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
12080 check_promoted_subreg (insn, XEXP (x, i));
12084 if (XVEC (x, i) != 0)
12085 for (j = 0; j < XVECLEN (x, i); j++)
12086 check_promoted_subreg (insn, XVECEXP (x, i, j));
12092 /* Verify that all the registers and memory references mentioned in *LOC are
12093 still valid. *LOC was part of a value set in INSN when label_tick was
12094 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12095 the invalid references with (clobber (const_int 0)) and return 1. This
12096 replacement is useful because we often can get useful information about
12097 the form of a value (e.g., if it was produced by a shift that always
12098 produces -1 or 0) even though we don't know exactly what registers it
12099 was produced from. */
12102 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
12105 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
12106 int len = GET_RTX_LENGTH (GET_CODE (x));
12111 unsigned int regno = REGNO (x);
12112 unsigned int endregno = END_REGNO (x);
12115 for (j = regno; j < endregno; j++)
12117 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, j);
12118 if (rsp->last_set_invalid
12119 /* If this is a pseudo-register that was only set once and not
12120 live at the beginning of the function, it is always valid. */
12121 || (! (regno >= FIRST_PSEUDO_REGISTER
12122 && REG_N_SETS (regno) == 1
12123 && (!REGNO_REG_SET_P
12124 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno)))
12125 && rsp->last_set_label > tick))
12128 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12135 /* If this is a memory reference, make sure that there were no stores after
12136 it that might have clobbered the value. We don't have alias info, so we
12137 assume any store invalidates it. Moreover, we only have local UIDs, so
12138 we also assume that there were stores in the intervening basic blocks. */
12139 else if (MEM_P (x) && !MEM_READONLY_P (x)
12140 && (tick != label_tick || DF_INSN_LUID (insn) <= mem_last_set))
12143 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12147 for (i = 0; i < len; i++)
12151 /* Check for identical subexpressions. If x contains
12152 identical subexpression we only have to traverse one of
12154 if (i == 1 && ARITHMETIC_P (x))
12156 /* Note that at this point x0 has already been checked
12157 and found valid. */
12158 rtx x0 = XEXP (x, 0);
12159 rtx x1 = XEXP (x, 1);
12161 /* If x0 and x1 are identical then x is also valid. */
12165 /* If x1 is identical to a subexpression of x0 then
12166 while checking x0, x1 has already been checked. Thus
12167 it is valid and so as x. */
12168 if (ARITHMETIC_P (x0)
12169 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12172 /* If x0 is identical to a subexpression of x1 then x is
12173 valid iff the rest of x1 is valid. */
12174 if (ARITHMETIC_P (x1)
12175 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12177 get_last_value_validate (&XEXP (x1,
12178 x0 == XEXP (x1, 0) ? 1 : 0),
12179 insn, tick, replace);
12182 if (get_last_value_validate (&XEXP (x, i), insn, tick,
12186 else if (fmt[i] == 'E')
12187 for (j = 0; j < XVECLEN (x, i); j++)
12188 if (get_last_value_validate (&XVECEXP (x, i, j),
12189 insn, tick, replace) == 0)
12193 /* If we haven't found a reason for it to be invalid, it is valid. */
12197 /* Get the last value assigned to X, if known. Some registers
12198 in the value may be replaced with (clobber (const_int 0)) if their value
12199 is known longer known reliably. */
12202 get_last_value (const_rtx x)
12204 unsigned int regno;
12206 reg_stat_type *rsp;
12208 /* If this is a non-paradoxical SUBREG, get the value of its operand and
12209 then convert it to the desired mode. If this is a paradoxical SUBREG,
12210 we cannot predict what values the "extra" bits might have. */
12211 if (GET_CODE (x) == SUBREG
12212 && subreg_lowpart_p (x)
12213 && (GET_MODE_SIZE (GET_MODE (x))
12214 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
12215 && (value = get_last_value (SUBREG_REG (x))) != 0)
12216 return gen_lowpart (GET_MODE (x), value);
12222 rsp = VEC_index (reg_stat_type, reg_stat, regno);
12223 value = rsp->last_set_value;
12225 /* If we don't have a value, or if it isn't for this basic block and
12226 it's either a hard register, set more than once, or it's a live
12227 at the beginning of the function, return 0.
12229 Because if it's not live at the beginning of the function then the reg
12230 is always set before being used (is never used without being set).
12231 And, if it's set only once, and it's always set before use, then all
12232 uses must have the same last value, even if it's not from this basic
12236 || (rsp->last_set_label < label_tick_ebb_start
12237 && (regno < FIRST_PSEUDO_REGISTER
12238 || REG_N_SETS (regno) != 1
12240 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno))))
12243 /* If the value was set in a later insn than the ones we are processing,
12244 we can't use it even if the register was only set once. */
12245 if (rsp->last_set_label == label_tick
12246 && DF_INSN_LUID (rsp->last_set) >= subst_low_luid)
12249 /* If the value has all its registers valid, return it. */
12250 if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 0))
12253 /* Otherwise, make a copy and replace any invalid register with
12254 (clobber (const_int 0)). If that fails for some reason, return 0. */
12256 value = copy_rtx (value);
12257 if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 1))
12263 /* Return nonzero if expression X refers to a REG or to memory
12264 that is set in an instruction more recent than FROM_LUID. */
12267 use_crosses_set_p (const_rtx x, int from_luid)
12271 enum rtx_code code = GET_CODE (x);
12275 unsigned int regno = REGNO (x);
12276 unsigned endreg = END_REGNO (x);
12278 #ifdef PUSH_ROUNDING
12279 /* Don't allow uses of the stack pointer to be moved,
12280 because we don't know whether the move crosses a push insn. */
12281 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
12284 for (; regno < endreg; regno++)
12286 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
12288 && rsp->last_set_label == label_tick
12289 && DF_INSN_LUID (rsp->last_set) > from_luid)
12295 if (code == MEM && mem_last_set > from_luid)
12298 fmt = GET_RTX_FORMAT (code);
12300 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12305 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12306 if (use_crosses_set_p (XVECEXP (x, i, j), from_luid))
12309 else if (fmt[i] == 'e'
12310 && use_crosses_set_p (XEXP (x, i), from_luid))
12316 /* Define three variables used for communication between the following
12319 static unsigned int reg_dead_regno, reg_dead_endregno;
12320 static int reg_dead_flag;
12322 /* Function called via note_stores from reg_dead_at_p.
12324 If DEST is within [reg_dead_regno, reg_dead_endregno), set
12325 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
12328 reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
12330 unsigned int regno, endregno;
12335 regno = REGNO (dest);
12336 endregno = END_REGNO (dest);
12337 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
12338 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
12341 /* Return nonzero if REG is known to be dead at INSN.
12343 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12344 referencing REG, it is dead. If we hit a SET referencing REG, it is
12345 live. Otherwise, see if it is live or dead at the start of the basic
12346 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12347 must be assumed to be always live. */
12350 reg_dead_at_p (rtx reg, rtx insn)
12355 /* Set variables for reg_dead_at_p_1. */
12356 reg_dead_regno = REGNO (reg);
12357 reg_dead_endregno = END_REGNO (reg);
12361 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
12362 we allow the machine description to decide whether use-and-clobber
12363 patterns are OK. */
12364 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
12366 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12367 if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
12371 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12372 beginning of basic block. */
12373 block = BLOCK_FOR_INSN (insn);
12378 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
12380 return reg_dead_flag == 1 ? 1 : 0;
12382 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
12386 if (insn == BB_HEAD (block))
12389 insn = PREV_INSN (insn);
12392 /* Look at live-in sets for the basic block that we were in. */
12393 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12394 if (REGNO_REG_SET_P (df_get_live_in (block), i))
12400 /* Note hard registers in X that are used. */
12403 mark_used_regs_combine (rtx x)
12405 RTX_CODE code = GET_CODE (x);
12406 unsigned int regno;
12419 case ADDR_DIFF_VEC:
12422 /* CC0 must die in the insn after it is set, so we don't need to take
12423 special note of it here. */
12429 /* If we are clobbering a MEM, mark any hard registers inside the
12430 address as used. */
12431 if (MEM_P (XEXP (x, 0)))
12432 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
12437 /* A hard reg in a wide mode may really be multiple registers.
12438 If so, mark all of them just like the first. */
12439 if (regno < FIRST_PSEUDO_REGISTER)
12441 /* None of this applies to the stack, frame or arg pointers. */
12442 if (regno == STACK_POINTER_REGNUM
12443 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
12444 || regno == HARD_FRAME_POINTER_REGNUM
12446 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12447 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
12449 || regno == FRAME_POINTER_REGNUM)
12452 add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno);
12458 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12460 rtx testreg = SET_DEST (x);
12462 while (GET_CODE (testreg) == SUBREG
12463 || GET_CODE (testreg) == ZERO_EXTRACT
12464 || GET_CODE (testreg) == STRICT_LOW_PART)
12465 testreg = XEXP (testreg, 0);
12467 if (MEM_P (testreg))
12468 mark_used_regs_combine (XEXP (testreg, 0));
12470 mark_used_regs_combine (SET_SRC (x));
12478 /* Recursively scan the operands of this expression. */
12481 const char *fmt = GET_RTX_FORMAT (code);
12483 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12486 mark_used_regs_combine (XEXP (x, i));
12487 else if (fmt[i] == 'E')
12491 for (j = 0; j < XVECLEN (x, i); j++)
12492 mark_used_regs_combine (XVECEXP (x, i, j));
12498 /* Remove register number REGNO from the dead registers list of INSN.
12500 Return the note used to record the death, if there was one. */
12503 remove_death (unsigned int regno, rtx insn)
12505 rtx note = find_regno_note (insn, REG_DEAD, regno);
12508 remove_note (insn, note);
12513 /* For each register (hardware or pseudo) used within expression X, if its
12514 death is in an instruction with luid between FROM_LUID (inclusive) and
12515 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12516 list headed by PNOTES.
12518 That said, don't move registers killed by maybe_kill_insn.
12520 This is done when X is being merged by combination into TO_INSN. These
12521 notes will then be distributed as needed. */
12524 move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx to_insn,
12529 enum rtx_code code = GET_CODE (x);
12533 unsigned int regno = REGNO (x);
12534 rtx where_dead = VEC_index (reg_stat_type, reg_stat, regno)->last_death;
12536 /* Don't move the register if it gets killed in between from and to. */
12537 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
12538 && ! reg_referenced_p (x, maybe_kill_insn))
12542 && BLOCK_FOR_INSN (where_dead) == BLOCK_FOR_INSN (to_insn)
12543 && DF_INSN_LUID (where_dead) >= from_luid
12544 && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn))
12546 rtx note = remove_death (regno, where_dead);
12548 /* It is possible for the call above to return 0. This can occur
12549 when last_death points to I2 or I1 that we combined with.
12550 In that case make a new note.
12552 We must also check for the case where X is a hard register
12553 and NOTE is a death note for a range of hard registers
12554 including X. In that case, we must put REG_DEAD notes for
12555 the remaining registers in place of NOTE. */
12557 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
12558 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12559 > GET_MODE_SIZE (GET_MODE (x))))
12561 unsigned int deadregno = REGNO (XEXP (note, 0));
12562 unsigned int deadend = END_HARD_REGNO (XEXP (note, 0));
12563 unsigned int ourend = END_HARD_REGNO (x);
12566 for (i = deadregno; i < deadend; i++)
12567 if (i < regno || i >= ourend)
12568 add_reg_note (where_dead, REG_DEAD, regno_reg_rtx[i]);
12571 /* If we didn't find any note, or if we found a REG_DEAD note that
12572 covers only part of the given reg, and we have a multi-reg hard
12573 register, then to be safe we must check for REG_DEAD notes
12574 for each register other than the first. They could have
12575 their own REG_DEAD notes lying around. */
12576 else if ((note == 0
12578 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12579 < GET_MODE_SIZE (GET_MODE (x)))))
12580 && regno < FIRST_PSEUDO_REGISTER
12581 && hard_regno_nregs[regno][GET_MODE (x)] > 1)
12583 unsigned int ourend = END_HARD_REGNO (x);
12584 unsigned int i, offset;
12588 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
12592 for (i = regno + offset; i < ourend; i++)
12593 move_deaths (regno_reg_rtx[i],
12594 maybe_kill_insn, from_luid, to_insn, &oldnotes);
12597 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
12599 XEXP (note, 1) = *pnotes;
12603 *pnotes = alloc_reg_note (REG_DEAD, x, *pnotes);
12609 else if (GET_CODE (x) == SET)
12611 rtx dest = SET_DEST (x);
12613 move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes);
12615 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12616 that accesses one word of a multi-word item, some
12617 piece of everything register in the expression is used by
12618 this insn, so remove any old death. */
12619 /* ??? So why do we test for equality of the sizes? */
12621 if (GET_CODE (dest) == ZERO_EXTRACT
12622 || GET_CODE (dest) == STRICT_LOW_PART
12623 || (GET_CODE (dest) == SUBREG
12624 && (((GET_MODE_SIZE (GET_MODE (dest))
12625 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
12626 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
12627 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
12629 move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes);
12633 /* If this is some other SUBREG, we know it replaces the entire
12634 value, so use that as the destination. */
12635 if (GET_CODE (dest) == SUBREG)
12636 dest = SUBREG_REG (dest);
12638 /* If this is a MEM, adjust deaths of anything used in the address.
12639 For a REG (the only other possibility), the entire value is
12640 being replaced so the old value is not used in this insn. */
12643 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid,
12648 else if (GET_CODE (x) == CLOBBER)
12651 len = GET_RTX_LENGTH (code);
12652 fmt = GET_RTX_FORMAT (code);
12654 for (i = 0; i < len; i++)
12659 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12660 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid,
12663 else if (fmt[i] == 'e')
12664 move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes);
12668 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12669 pattern of an insn. X must be a REG. */
12672 reg_bitfield_target_p (rtx x, rtx body)
12676 if (GET_CODE (body) == SET)
12678 rtx dest = SET_DEST (body);
12680 unsigned int regno, tregno, endregno, endtregno;
12682 if (GET_CODE (dest) == ZERO_EXTRACT)
12683 target = XEXP (dest, 0);
12684 else if (GET_CODE (dest) == STRICT_LOW_PART)
12685 target = SUBREG_REG (XEXP (dest, 0));
12689 if (GET_CODE (target) == SUBREG)
12690 target = SUBREG_REG (target);
12692 if (!REG_P (target))
12695 tregno = REGNO (target), regno = REGNO (x);
12696 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
12697 return target == x;
12699 endtregno = end_hard_regno (GET_MODE (target), tregno);
12700 endregno = end_hard_regno (GET_MODE (x), regno);
12702 return endregno > tregno && regno < endtregno;
12705 else if (GET_CODE (body) == PARALLEL)
12706 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
12707 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
12713 /* Return the next insn after INSN that is neither a NOTE nor a
12714 DEBUG_INSN. This routine does not look inside SEQUENCEs. */
12717 next_nonnote_nondebug_insn (rtx insn)
12721 insn = NEXT_INSN (insn);
12726 if (DEBUG_INSN_P (insn))
12736 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12737 as appropriate. I3 and I2 are the insns resulting from the combination
12738 insns including FROM (I2 may be zero).
12740 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
12741 not need REG_DEAD notes because they are being substituted for. This
12742 saves searching in the most common cases.
12744 Each note in the list is either ignored or placed on some insns, depending
12745 on the type of note. */
12748 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
12751 rtx note, next_note;
12754 for (note = notes; note; note = next_note)
12756 rtx place = 0, place2 = 0;
12758 next_note = XEXP (note, 1);
12759 switch (REG_NOTE_KIND (note))
12763 /* Doesn't matter much where we put this, as long as it's somewhere.
12764 It is preferable to keep these notes on branches, which is most
12765 likely to be i3. */
12769 case REG_VALUE_PROFILE:
12770 /* Just get rid of this note, as it is unused later anyway. */
12773 case REG_NON_LOCAL_GOTO:
12778 gcc_assert (i2 && JUMP_P (i2));
12783 case REG_EH_REGION:
12784 /* These notes must remain with the call or trapping instruction. */
12787 else if (i2 && CALL_P (i2))
12791 gcc_assert (flag_non_call_exceptions);
12792 if (may_trap_p (i3))
12794 else if (i2 && may_trap_p (i2))
12796 /* ??? Otherwise assume we've combined things such that we
12797 can now prove that the instructions can't trap. Drop the
12798 note in this case. */
12804 /* These notes must remain with the call. It should not be
12805 possible for both I2 and I3 to be a call. */
12810 gcc_assert (i2 && CALL_P (i2));
12816 /* Any clobbers for i3 may still exist, and so we must process
12817 REG_UNUSED notes from that insn.
12819 Any clobbers from i2 or i1 can only exist if they were added by
12820 recog_for_combine. In that case, recog_for_combine created the
12821 necessary REG_UNUSED notes. Trying to keep any original
12822 REG_UNUSED notes from these insns can cause incorrect output
12823 if it is for the same register as the original i3 dest.
12824 In that case, we will notice that the register is set in i3,
12825 and then add a REG_UNUSED note for the destination of i3, which
12826 is wrong. However, it is possible to have REG_UNUSED notes from
12827 i2 or i1 for register which were both used and clobbered, so
12828 we keep notes from i2 or i1 if they will turn into REG_DEAD
12831 /* If this register is set or clobbered in I3, put the note there
12832 unless there is one already. */
12833 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
12835 if (from_insn != i3)
12838 if (! (REG_P (XEXP (note, 0))
12839 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
12840 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
12843 /* Otherwise, if this register is used by I3, then this register
12844 now dies here, so we must put a REG_DEAD note here unless there
12846 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
12847 && ! (REG_P (XEXP (note, 0))
12848 ? find_regno_note (i3, REG_DEAD,
12849 REGNO (XEXP (note, 0)))
12850 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
12852 PUT_REG_NOTE_KIND (note, REG_DEAD);
12860 /* These notes say something about results of an insn. We can
12861 only support them if they used to be on I3 in which case they
12862 remain on I3. Otherwise they are ignored.
12864 If the note refers to an expression that is not a constant, we
12865 must also ignore the note since we cannot tell whether the
12866 equivalence is still true. It might be possible to do
12867 slightly better than this (we only have a problem if I2DEST
12868 or I1DEST is present in the expression), but it doesn't
12869 seem worth the trouble. */
12871 if (from_insn == i3
12872 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
12877 /* These notes say something about how a register is used. They must
12878 be present on any use of the register in I2 or I3. */
12879 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12882 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12891 case REG_LABEL_TARGET:
12892 case REG_LABEL_OPERAND:
12893 /* This can show up in several ways -- either directly in the
12894 pattern, or hidden off in the constant pool with (or without?)
12895 a REG_EQUAL note. */
12896 /* ??? Ignore the without-reg_equal-note problem for now. */
12897 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12898 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12899 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12900 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12904 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12905 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12906 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12907 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12915 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
12916 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
12918 if (place && JUMP_P (place)
12919 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
12920 && (JUMP_LABEL (place) == NULL
12921 || JUMP_LABEL (place) == XEXP (note, 0)))
12923 rtx label = JUMP_LABEL (place);
12926 JUMP_LABEL (place) = XEXP (note, 0);
12927 else if (LABEL_P (label))
12928 LABEL_NUSES (label)--;
12931 if (place2 && JUMP_P (place2)
12932 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
12933 && (JUMP_LABEL (place2) == NULL
12934 || JUMP_LABEL (place2) == XEXP (note, 0)))
12936 rtx label = JUMP_LABEL (place2);
12939 JUMP_LABEL (place2) = XEXP (note, 0);
12940 else if (LABEL_P (label))
12941 LABEL_NUSES (label)--;
12947 /* This note says something about the value of a register prior
12948 to the execution of an insn. It is too much trouble to see
12949 if the note is still correct in all situations. It is better
12950 to simply delete it. */
12954 /* If we replaced the right hand side of FROM_INSN with a
12955 REG_EQUAL note, the original use of the dying register
12956 will not have been combined into I3 and I2. In such cases,
12957 FROM_INSN is guaranteed to be the first of the combined
12958 instructions, so we simply need to search back before
12959 FROM_INSN for the previous use or set of this register,
12960 then alter the notes there appropriately.
12962 If the register is used as an input in I3, it dies there.
12963 Similarly for I2, if it is nonzero and adjacent to I3.
12965 If the register is not used as an input in either I3 or I2
12966 and it is not one of the registers we were supposed to eliminate,
12967 there are two possibilities. We might have a non-adjacent I2
12968 or we might have somehow eliminated an additional register
12969 from a computation. For example, we might have had A & B where
12970 we discover that B will always be zero. In this case we will
12971 eliminate the reference to A.
12973 In both cases, we must search to see if we can find a previous
12974 use of A and put the death note there. */
12977 && from_insn == i2mod
12978 && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
12983 && CALL_P (from_insn)
12984 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12986 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12988 else if (i2 != 0 && next_nonnote_nondebug_insn (i2) == i3
12989 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12991 else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
12993 && reg_overlap_mentioned_p (XEXP (note, 0),
12995 || rtx_equal_p (XEXP (note, 0), elim_i1))
13002 basic_block bb = this_basic_block;
13004 for (tem = PREV_INSN (tem); place == 0; tem = PREV_INSN (tem))
13006 if (!NONDEBUG_INSN_P (tem))
13008 if (tem == BB_HEAD (bb))
13013 /* If the register is being set at TEM, see if that is all
13014 TEM is doing. If so, delete TEM. Otherwise, make this
13015 into a REG_UNUSED note instead. Don't delete sets to
13016 global register vars. */
13017 if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
13018 || !global_regs[REGNO (XEXP (note, 0))])
13019 && reg_set_p (XEXP (note, 0), PATTERN (tem)))
13021 rtx set = single_set (tem);
13022 rtx inner_dest = 0;
13024 rtx cc0_setter = NULL_RTX;
13028 for (inner_dest = SET_DEST (set);
13029 (GET_CODE (inner_dest) == STRICT_LOW_PART
13030 || GET_CODE (inner_dest) == SUBREG
13031 || GET_CODE (inner_dest) == ZERO_EXTRACT);
13032 inner_dest = XEXP (inner_dest, 0))
13035 /* Verify that it was the set, and not a clobber that
13036 modified the register.
13038 CC0 targets must be careful to maintain setter/user
13039 pairs. If we cannot delete the setter due to side
13040 effects, mark the user with an UNUSED note instead
13043 if (set != 0 && ! side_effects_p (SET_SRC (set))
13044 && rtx_equal_p (XEXP (note, 0), inner_dest)
13046 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
13047 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
13048 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
13052 /* Move the notes and links of TEM elsewhere.
13053 This might delete other dead insns recursively.
13054 First set the pattern to something that won't use
13056 rtx old_notes = REG_NOTES (tem);
13058 PATTERN (tem) = pc_rtx;
13059 REG_NOTES (tem) = NULL;
13061 distribute_notes (old_notes, tem, tem, NULL_RTX,
13062 NULL_RTX, NULL_RTX);
13063 distribute_links (LOG_LINKS (tem));
13065 SET_INSN_DELETED (tem);
13070 /* Delete the setter too. */
13073 PATTERN (cc0_setter) = pc_rtx;
13074 old_notes = REG_NOTES (cc0_setter);
13075 REG_NOTES (cc0_setter) = NULL;
13077 distribute_notes (old_notes, cc0_setter,
13078 cc0_setter, NULL_RTX,
13079 NULL_RTX, NULL_RTX);
13080 distribute_links (LOG_LINKS (cc0_setter));
13082 SET_INSN_DELETED (cc0_setter);
13083 if (cc0_setter == i2)
13090 PUT_REG_NOTE_KIND (note, REG_UNUSED);
13092 /* If there isn't already a REG_UNUSED note, put one
13093 here. Do not place a REG_DEAD note, even if
13094 the register is also used here; that would not
13095 match the algorithm used in lifetime analysis
13096 and can cause the consistency check in the
13097 scheduler to fail. */
13098 if (! find_regno_note (tem, REG_UNUSED,
13099 REGNO (XEXP (note, 0))))
13104 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
13106 && find_reg_fusage (tem, USE, XEXP (note, 0))))
13110 /* If we are doing a 3->2 combination, and we have a
13111 register which formerly died in i3 and was not used
13112 by i2, which now no longer dies in i3 and is used in
13113 i2 but does not die in i2, and place is between i2
13114 and i3, then we may need to move a link from place to
13116 if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2)
13118 && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2)
13119 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13121 rtx links = LOG_LINKS (place);
13122 LOG_LINKS (place) = 0;
13123 distribute_links (links);
13128 if (tem == BB_HEAD (bb))
13134 /* If the register is set or already dead at PLACE, we needn't do
13135 anything with this note if it is still a REG_DEAD note.
13136 We check here if it is set at all, not if is it totally replaced,
13137 which is what `dead_or_set_p' checks, so also check for it being
13140 if (place && REG_NOTE_KIND (note) == REG_DEAD)
13142 unsigned int regno = REGNO (XEXP (note, 0));
13143 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
13145 if (dead_or_set_p (place, XEXP (note, 0))
13146 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
13148 /* Unless the register previously died in PLACE, clear
13149 last_death. [I no longer understand why this is
13151 if (rsp->last_death != place)
13152 rsp->last_death = 0;
13156 rsp->last_death = place;
13158 /* If this is a death note for a hard reg that is occupying
13159 multiple registers, ensure that we are still using all
13160 parts of the object. If we find a piece of the object
13161 that is unused, we must arrange for an appropriate REG_DEAD
13162 note to be added for it. However, we can't just emit a USE
13163 and tag the note to it, since the register might actually
13164 be dead; so we recourse, and the recursive call then finds
13165 the previous insn that used this register. */
13167 if (place && regno < FIRST_PSEUDO_REGISTER
13168 && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
13170 unsigned int endregno = END_HARD_REGNO (XEXP (note, 0));
13174 for (i = regno; i < endregno; i++)
13175 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
13176 && ! find_regno_fusage (place, USE, i))
13177 || dead_or_set_regno_p (place, i))
13182 /* Put only REG_DEAD notes for pieces that are
13183 not already dead or set. */
13185 for (i = regno; i < endregno;
13186 i += hard_regno_nregs[i][reg_raw_mode[i]])
13188 rtx piece = regno_reg_rtx[i];
13189 basic_block bb = this_basic_block;
13191 if (! dead_or_set_p (place, piece)
13192 && ! reg_bitfield_target_p (piece,
13195 rtx new_note = alloc_reg_note (REG_DEAD, piece,
13198 distribute_notes (new_note, place, place,
13199 NULL_RTX, NULL_RTX, NULL_RTX);
13201 else if (! refers_to_regno_p (i, i + 1,
13202 PATTERN (place), 0)
13203 && ! find_regno_fusage (place, USE, i))
13204 for (tem = PREV_INSN (place); ;
13205 tem = PREV_INSN (tem))
13207 if (!NONDEBUG_INSN_P (tem))
13209 if (tem == BB_HEAD (bb))
13213 if (dead_or_set_p (tem, piece)
13214 || reg_bitfield_target_p (piece,
13217 add_reg_note (tem, REG_UNUSED, piece);
13231 /* Any other notes should not be present at this point in the
13233 gcc_unreachable ();
13238 XEXP (note, 1) = REG_NOTES (place);
13239 REG_NOTES (place) = note;
13243 add_reg_note (place2, REG_NOTE_KIND (note), XEXP (note, 0));
13247 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13248 I3, I2, and I1 to new locations. This is also called to add a link
13249 pointing at I3 when I3's destination is changed. */
13252 distribute_links (rtx links)
13254 rtx link, next_link;
13256 for (link = links; link; link = next_link)
13262 next_link = XEXP (link, 1);
13264 /* If the insn that this link points to is a NOTE or isn't a single
13265 set, ignore it. In the latter case, it isn't clear what we
13266 can do other than ignore the link, since we can't tell which
13267 register it was for. Such links wouldn't be used by combine
13270 It is not possible for the destination of the target of the link to
13271 have been changed by combine. The only potential of this is if we
13272 replace I3, I2, and I1 by I3 and I2. But in that case the
13273 destination of I2 also remains unchanged. */
13275 if (NOTE_P (XEXP (link, 0))
13276 || (set = single_set (XEXP (link, 0))) == 0)
13279 reg = SET_DEST (set);
13280 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
13281 || GET_CODE (reg) == STRICT_LOW_PART)
13282 reg = XEXP (reg, 0);
13284 /* A LOG_LINK is defined as being placed on the first insn that uses
13285 a register and points to the insn that sets the register. Start
13286 searching at the next insn after the target of the link and stop
13287 when we reach a set of the register or the end of the basic block.
13289 Note that this correctly handles the link that used to point from
13290 I3 to I2. Also note that not much searching is typically done here
13291 since most links don't point very far away. */
13293 for (insn = NEXT_INSN (XEXP (link, 0));
13294 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
13295 || BB_HEAD (this_basic_block->next_bb) != insn));
13296 insn = NEXT_INSN (insn))
13297 if (DEBUG_INSN_P (insn))
13299 else if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
13301 if (reg_referenced_p (reg, PATTERN (insn)))
13305 else if (CALL_P (insn)
13306 && find_reg_fusage (insn, USE, reg))
13311 else if (INSN_P (insn) && reg_set_p (reg, insn))
13314 /* If we found a place to put the link, place it there unless there
13315 is already a link to the same insn as LINK at that point. */
13321 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
13322 if (XEXP (link2, 0) == XEXP (link, 0))
13327 XEXP (link, 1) = LOG_LINKS (place);
13328 LOG_LINKS (place) = link;
13330 /* Set added_links_insn to the earliest insn we added a
13332 if (added_links_insn == 0
13333 || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place))
13334 added_links_insn = place;
13340 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
13341 Check whether the expression pointer to by LOC is a register or
13342 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
13343 Otherwise return zero. */
13346 unmentioned_reg_p_1 (rtx *loc, void *expr)
13351 && (REG_P (x) || MEM_P (x))
13352 && ! reg_mentioned_p (x, (rtx) expr))
13357 /* Check for any register or memory mentioned in EQUIV that is not
13358 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
13359 of EXPR where some registers may have been replaced by constants. */
13362 unmentioned_reg_p (rtx equiv, rtx expr)
13364 return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
13368 dump_combine_stats (FILE *file)
13372 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13373 combine_attempts, combine_merges, combine_extras, combine_successes);
13377 dump_combine_total_stats (FILE *file)
13381 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13382 total_attempts, total_merges, total_extras, total_successes);
13386 gate_handle_combine (void)
13388 return (optimize > 0);
13391 /* Try combining insns through substitution. */
13392 static unsigned int
13393 rest_of_handle_combine (void)
13395 int rebuild_jump_labels_after_combine;
13397 df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN);
13398 df_note_add_problem ();
13401 regstat_init_n_sets_and_refs ();
13403 rebuild_jump_labels_after_combine
13404 = combine_instructions (get_insns (), max_reg_num ());
13406 /* Combining insns may have turned an indirect jump into a
13407 direct jump. Rebuild the JUMP_LABEL fields of jumping
13409 if (rebuild_jump_labels_after_combine)
13411 timevar_push (TV_JUMP);
13412 rebuild_jump_labels (get_insns ());
13414 timevar_pop (TV_JUMP);
13417 regstat_free_n_sets_and_refs ();
13421 struct rtl_opt_pass pass_combine =
13425 "combine", /* name */
13426 gate_handle_combine, /* gate */
13427 rest_of_handle_combine, /* execute */
13430 0, /* static_pass_number */
13431 TV_COMBINE, /* tv_id */
13432 PROP_cfglayout, /* properties_required */
13433 0, /* properties_provided */
13434 0, /* properties_destroyed */
13435 0, /* todo_flags_start */
13437 TODO_df_finish | TODO_verify_rtl_sharing |
13438 TODO_ggc_collect, /* todo_flags_finish */