1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
87 #include "hard-reg-set.h"
88 #include "basic-block.h"
89 #include "insn-config.h"
91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
93 #include "insn-attr.h"
99 #include "insn-codes.h"
100 #include "rtlhooks-def.h"
101 /* Include output.h for dump_file. */
105 #include "tree-pass.h"
109 /* Number of attempts to combine instructions in this function. */
111 static int combine_attempts;
113 /* Number of attempts that got as far as substitution in this function. */
115 static int combine_merges;
117 /* Number of instructions combined with added SETs in this function. */
119 static int combine_extras;
121 /* Number of instructions combined in this function. */
123 static int combine_successes;
125 /* Totals over entire compilation. */
127 static int total_attempts, total_merges, total_extras, total_successes;
129 /* combine_instructions may try to replace the right hand side of the
130 second instruction with the value of an associated REG_EQUAL note
131 before throwing it at try_combine. That is problematic when there
132 is a REG_DEAD note for a register used in the old right hand side
133 and can cause distribute_notes to do wrong things. This is the
134 second instruction if it has been so modified, null otherwise. */
138 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
140 static rtx i2mod_old_rhs;
142 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
144 static rtx i2mod_new_rhs;
146 typedef struct reg_stat_struct {
147 /* Record last point of death of (hard or pseudo) register n. */
150 /* Record last point of modification of (hard or pseudo) register n. */
153 /* The next group of fields allows the recording of the last value assigned
154 to (hard or pseudo) register n. We use this information to see if an
155 operation being processed is redundant given a prior operation performed
156 on the register. For example, an `and' with a constant is redundant if
157 all the zero bits are already known to be turned off.
159 We use an approach similar to that used by cse, but change it in the
162 (1) We do not want to reinitialize at each label.
163 (2) It is useful, but not critical, to know the actual value assigned
164 to a register. Often just its form is helpful.
166 Therefore, we maintain the following fields:
168 last_set_value the last value assigned
169 last_set_label records the value of label_tick when the
170 register was assigned
171 last_set_table_tick records the value of label_tick when a
172 value using the register is assigned
173 last_set_invalid set to nonzero when it is not valid
174 to use the value of this register in some
177 To understand the usage of these tables, it is important to understand
178 the distinction between the value in last_set_value being valid and
179 the register being validly contained in some other expression in the
182 (The next two parameters are out of date).
184 reg_stat[i].last_set_value is valid if it is nonzero, and either
185 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
187 Register I may validly appear in any expression returned for the value
188 of another register if reg_n_sets[i] is 1. It may also appear in the
189 value for register J if reg_stat[j].last_set_invalid is zero, or
190 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
192 If an expression is found in the table containing a register which may
193 not validly appear in an expression, the register is replaced by
194 something that won't match, (clobber (const_int 0)). */
196 /* Record last value assigned to (hard or pseudo) register n. */
200 /* Record the value of label_tick when an expression involving register n
201 is placed in last_set_value. */
203 int last_set_table_tick;
205 /* Record the value of label_tick when the value for register n is placed in
210 /* These fields are maintained in parallel with last_set_value and are
211 used to store the mode in which the register was last set, the bits
212 that were known to be zero when it was last set, and the number of
213 sign bits copies it was known to have when it was last set. */
215 unsigned HOST_WIDE_INT last_set_nonzero_bits;
216 char last_set_sign_bit_copies;
217 ENUM_BITFIELD(machine_mode) last_set_mode : 8;
219 /* Set nonzero if references to register n in expressions should not be
220 used. last_set_invalid is set nonzero when this register is being
221 assigned to and last_set_table_tick == label_tick. */
223 char last_set_invalid;
225 /* Some registers that are set more than once and used in more than one
226 basic block are nevertheless always set in similar ways. For example,
227 a QImode register may be loaded from memory in two places on a machine
228 where byte loads zero extend.
230 We record in the following fields if a register has some leading bits
231 that are always equal to the sign bit, and what we know about the
232 nonzero bits of a register, specifically which bits are known to be
235 If an entry is zero, it means that we don't know anything special. */
237 unsigned char sign_bit_copies;
239 unsigned HOST_WIDE_INT nonzero_bits;
241 /* Record the value of the label_tick when the last truncation
242 happened. The field truncated_to_mode is only valid if
243 truncation_label == label_tick. */
245 int truncation_label;
247 /* Record the last truncation seen for this register. If truncation
248 is not a nop to this mode we might be able to save an explicit
249 truncation if we know that value already contains a truncated
252 ENUM_BITFIELD(machine_mode) truncated_to_mode : 8;
255 DEF_VEC_O(reg_stat_type);
256 DEF_VEC_ALLOC_O(reg_stat_type,heap);
258 static VEC(reg_stat_type,heap) *reg_stat;
260 /* Record the luid of the last insn that invalidated memory
261 (anything that writes memory, and subroutine calls, but not pushes). */
263 static int mem_last_set;
265 /* Record the luid of the last CALL_INSN
266 so we can tell whether a potential combination crosses any calls. */
268 static int last_call_luid;
270 /* When `subst' is called, this is the insn that is being modified
271 (by combining in a previous insn). The PATTERN of this insn
272 is still the old pattern partially modified and it should not be
273 looked at, but this may be used to examine the successors of the insn
274 to judge whether a simplification is valid. */
276 static rtx subst_insn;
278 /* This is the lowest LUID that `subst' is currently dealing with.
279 get_last_value will not return a value if the register was set at or
280 after this LUID. If not for this mechanism, we could get confused if
281 I2 or I1 in try_combine were an insn that used the old value of a register
282 to obtain a new value. In that case, we might erroneously get the
283 new value of the register when we wanted the old one. */
285 static int subst_low_luid;
287 /* This contains any hard registers that are used in newpat; reg_dead_at_p
288 must consider all these registers to be always live. */
290 static HARD_REG_SET newpat_used_regs;
292 /* This is an insn to which a LOG_LINKS entry has been added. If this
293 insn is the earlier than I2 or I3, combine should rescan starting at
296 static rtx added_links_insn;
298 /* Basic block in which we are performing combines. */
299 static basic_block this_basic_block;
302 /* Length of the currently allocated uid_insn_cost array. */
304 static int max_uid_known;
306 /* The following array records the insn_rtx_cost for every insn
307 in the instruction stream. */
309 static int *uid_insn_cost;
311 /* The following array records the LOG_LINKS for every insn in the
312 instruction stream as an INSN_LIST rtx. */
314 static rtx *uid_log_links;
316 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
317 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
319 /* Incremented for each basic block. */
321 static int label_tick;
323 /* Reset to label_tick for each label. */
325 static int label_tick_ebb_start;
327 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
328 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
330 static enum machine_mode nonzero_bits_mode;
332 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
333 be safely used. It is zero while computing them and after combine has
334 completed. This former test prevents propagating values based on
335 previously set values, which can be incorrect if a variable is modified
338 static int nonzero_sign_valid;
341 /* Record one modification to rtl structure
342 to be undone by storing old_contents into *where. */
347 enum { UNDO_RTX, UNDO_INT, UNDO_MODE } kind;
348 union { rtx r; int i; enum machine_mode m; } old_contents;
349 union { rtx *r; int *i; } where;
352 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
353 num_undo says how many are currently recorded.
355 other_insn is nonzero if we have modified some other insn in the process
356 of working on subst_insn. It must be verified too. */
365 static struct undobuf undobuf;
367 /* Number of times the pseudo being substituted for
368 was found and replaced. */
370 static int n_occurrences;
372 static rtx reg_nonzero_bits_for_combine (const_rtx, enum machine_mode, const_rtx,
374 unsigned HOST_WIDE_INT,
375 unsigned HOST_WIDE_INT *);
376 static rtx reg_num_sign_bit_copies_for_combine (const_rtx, enum machine_mode, const_rtx,
378 unsigned int, unsigned int *);
379 static void do_SUBST (rtx *, rtx);
380 static void do_SUBST_INT (int *, int);
381 static void init_reg_last (void);
382 static void setup_incoming_promotions (rtx);
383 static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *);
384 static int cant_combine_insn_p (rtx);
385 static int can_combine_p (rtx, rtx, rtx, rtx, rtx *, rtx *);
386 static int combinable_i3pat (rtx, rtx *, rtx, rtx, int, rtx *);
387 static int contains_muldiv (rtx);
388 static rtx try_combine (rtx, rtx, rtx, int *);
389 static void undo_all (void);
390 static void undo_commit (void);
391 static rtx *find_split_point (rtx *, rtx);
392 static rtx subst (rtx, rtx, rtx, int, int);
393 static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
394 static rtx simplify_if_then_else (rtx);
395 static rtx simplify_set (rtx);
396 static rtx simplify_logical (rtx);
397 static rtx expand_compound_operation (rtx);
398 static const_rtx expand_field_assignment (const_rtx);
399 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
400 rtx, unsigned HOST_WIDE_INT, int, int, int);
401 static rtx extract_left_shift (rtx, int);
402 static rtx make_compound_operation (rtx, enum rtx_code);
403 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
404 unsigned HOST_WIDE_INT *);
405 static rtx canon_reg_for_combine (rtx, rtx);
406 static rtx force_to_mode (rtx, enum machine_mode,
407 unsigned HOST_WIDE_INT, int);
408 static rtx if_then_else_cond (rtx, rtx *, rtx *);
409 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
410 static int rtx_equal_for_field_assignment_p (rtx, rtx);
411 static rtx make_field_assignment (rtx);
412 static rtx apply_distributive_law (rtx);
413 static rtx distribute_and_simplify_rtx (rtx, int);
414 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
415 unsigned HOST_WIDE_INT);
416 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
417 unsigned HOST_WIDE_INT);
418 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
419 HOST_WIDE_INT, enum machine_mode, int *);
420 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
421 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
423 static int recog_for_combine (rtx *, rtx, rtx *);
424 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
425 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
426 static void update_table_tick (rtx);
427 static void record_value_for_reg (rtx, rtx, rtx);
428 static void check_promoted_subreg (rtx, rtx);
429 static void record_dead_and_set_regs_1 (rtx, const_rtx, void *);
430 static void record_dead_and_set_regs (rtx);
431 static int get_last_value_validate (rtx *, rtx, int, int);
432 static rtx get_last_value (const_rtx);
433 static int use_crosses_set_p (const_rtx, int);
434 static void reg_dead_at_p_1 (rtx, const_rtx, void *);
435 static int reg_dead_at_p (rtx, rtx);
436 static void move_deaths (rtx, rtx, int, rtx, rtx *);
437 static int reg_bitfield_target_p (rtx, rtx);
438 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx);
439 static void distribute_links (rtx);
440 static void mark_used_regs_combine (rtx);
441 static void record_promoted_value (rtx, rtx);
442 static int unmentioned_reg_p_1 (rtx *, void *);
443 static bool unmentioned_reg_p (rtx, rtx);
444 static int record_truncated_value (rtx *, void *);
445 static void record_truncated_values (rtx *, void *);
446 static bool reg_truncated_to_mode (enum machine_mode, const_rtx);
447 static rtx gen_lowpart_or_truncate (enum machine_mode, rtx);
450 /* It is not safe to use ordinary gen_lowpart in combine.
451 See comments in gen_lowpart_for_combine. */
452 #undef RTL_HOOKS_GEN_LOWPART
453 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
455 /* Our implementation of gen_lowpart never emits a new pseudo. */
456 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
457 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
459 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
460 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
462 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
463 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
465 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
466 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
468 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
471 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
472 PATTERN can not be split. Otherwise, it returns an insn sequence.
473 This is a wrapper around split_insns which ensures that the
474 reg_stat vector is made larger if the splitter creates a new
478 combine_split_insns (rtx pattern, rtx insn)
483 ret = split_insns (pattern, insn);
484 nregs = max_reg_num ();
485 if (nregs > VEC_length (reg_stat_type, reg_stat))
486 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
490 /* This is used by find_single_use to locate an rtx in LOC that
491 contains exactly one use of DEST, which is typically either a REG
492 or CC0. It returns a pointer to the innermost rtx expression
493 containing DEST. Appearances of DEST that are being used to
494 totally replace it are not counted. */
497 find_single_use_1 (rtx dest, rtx *loc)
500 enum rtx_code code = GET_CODE (x);
518 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
519 of a REG that occupies all of the REG, the insn uses DEST if
520 it is mentioned in the destination or the source. Otherwise, we
521 need just check the source. */
522 if (GET_CODE (SET_DEST (x)) != CC0
523 && GET_CODE (SET_DEST (x)) != PC
524 && !REG_P (SET_DEST (x))
525 && ! (GET_CODE (SET_DEST (x)) == SUBREG
526 && REG_P (SUBREG_REG (SET_DEST (x)))
527 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
528 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
529 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
530 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
533 return find_single_use_1 (dest, &SET_SRC (x));
537 return find_single_use_1 (dest, &XEXP (x, 0));
543 /* If it wasn't one of the common cases above, check each expression and
544 vector of this code. Look for a unique usage of DEST. */
546 fmt = GET_RTX_FORMAT (code);
547 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
551 if (dest == XEXP (x, i)
552 || (REG_P (dest) && REG_P (XEXP (x, i))
553 && REGNO (dest) == REGNO (XEXP (x, i))))
556 this_result = find_single_use_1 (dest, &XEXP (x, i));
559 result = this_result;
560 else if (this_result)
561 /* Duplicate usage. */
564 else if (fmt[i] == 'E')
568 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
570 if (XVECEXP (x, i, j) == dest
572 && REG_P (XVECEXP (x, i, j))
573 && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
576 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
579 result = this_result;
580 else if (this_result)
590 /* See if DEST, produced in INSN, is used only a single time in the
591 sequel. If so, return a pointer to the innermost rtx expression in which
594 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
596 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
597 care about REG_DEAD notes or LOG_LINKS.
599 Otherwise, we find the single use by finding an insn that has a
600 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
601 only referenced once in that insn, we know that it must be the first
602 and last insn referencing DEST. */
605 find_single_use (rtx dest, rtx insn, rtx *ploc)
614 next = NEXT_INSN (insn);
616 || (!NONJUMP_INSN_P (next) && !JUMP_P (next)))
619 result = find_single_use_1 (dest, &PATTERN (next));
629 for (next = next_nonnote_insn (insn);
630 next != 0 && !LABEL_P (next);
631 next = next_nonnote_insn (next))
632 if (INSN_P (next) && dead_or_set_p (next, dest))
634 for (link = LOG_LINKS (next); link; link = XEXP (link, 1))
635 if (XEXP (link, 0) == insn)
640 result = find_single_use_1 (dest, &PATTERN (next));
650 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
651 insn. The substitution can be undone by undo_all. If INTO is already
652 set to NEWVAL, do not record this change. Because computing NEWVAL might
653 also call SUBST, we have to compute it before we put anything into
657 do_SUBST (rtx *into, rtx newval)
662 if (oldval == newval)
665 /* We'd like to catch as many invalid transformations here as
666 possible. Unfortunately, there are way too many mode changes
667 that are perfectly valid, so we'd waste too much effort for
668 little gain doing the checks here. Focus on catching invalid
669 transformations involving integer constants. */
670 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
671 && GET_CODE (newval) == CONST_INT)
673 /* Sanity check that we're replacing oldval with a CONST_INT
674 that is a valid sign-extension for the original mode. */
675 gcc_assert (INTVAL (newval)
676 == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
678 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
679 CONST_INT is not valid, because after the replacement, the
680 original mode would be gone. Unfortunately, we can't tell
681 when do_SUBST is called to replace the operand thereof, so we
682 perform this test on oldval instead, checking whether an
683 invalid replacement took place before we got here. */
684 gcc_assert (!(GET_CODE (oldval) == SUBREG
685 && GET_CODE (SUBREG_REG (oldval)) == CONST_INT));
686 gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
687 && GET_CODE (XEXP (oldval, 0)) == CONST_INT));
691 buf = undobuf.frees, undobuf.frees = buf->next;
693 buf = XNEW (struct undo);
695 buf->kind = UNDO_RTX;
697 buf->old_contents.r = oldval;
700 buf->next = undobuf.undos, undobuf.undos = buf;
703 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
705 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
706 for the value of a HOST_WIDE_INT value (including CONST_INT) is
710 do_SUBST_INT (int *into, int newval)
715 if (oldval == newval)
719 buf = undobuf.frees, undobuf.frees = buf->next;
721 buf = XNEW (struct undo);
723 buf->kind = UNDO_INT;
725 buf->old_contents.i = oldval;
728 buf->next = undobuf.undos, undobuf.undos = buf;
731 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
733 /* Similar to SUBST, but just substitute the mode. This is used when
734 changing the mode of a pseudo-register, so that any other
735 references to the entry in the regno_reg_rtx array will change as
739 do_SUBST_MODE (rtx *into, enum machine_mode newval)
742 enum machine_mode oldval = GET_MODE (*into);
744 if (oldval == newval)
748 buf = undobuf.frees, undobuf.frees = buf->next;
750 buf = XNEW (struct undo);
752 buf->kind = UNDO_MODE;
754 buf->old_contents.m = oldval;
755 adjust_reg_mode (*into, newval);
757 buf->next = undobuf.undos, undobuf.undos = buf;
760 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE(&(INTO), (NEWVAL))
762 /* Subroutine of try_combine. Determine whether the combine replacement
763 patterns NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to
764 insn_rtx_cost that the original instruction sequence I1, I2, I3 and
765 undobuf.other_insn. Note that I1 and/or NEWI2PAT may be NULL_RTX.
766 NEWOTHERPAT and undobuf.other_insn may also both be NULL_RTX. This
767 function returns false, if the costs of all instructions can be
768 estimated, and the replacements are more expensive than the original
772 combine_validate_cost (rtx i1, rtx i2, rtx i3, rtx newpat, rtx newi2pat,
775 int i1_cost, i2_cost, i3_cost;
776 int new_i2_cost, new_i3_cost;
777 int old_cost, new_cost;
779 /* Lookup the original insn_rtx_costs. */
780 i2_cost = INSN_COST (i2);
781 i3_cost = INSN_COST (i3);
785 i1_cost = INSN_COST (i1);
786 old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0)
787 ? i1_cost + i2_cost + i3_cost : 0;
791 old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
795 /* Calculate the replacement insn_rtx_costs. */
796 new_i3_cost = insn_rtx_cost (newpat);
799 new_i2_cost = insn_rtx_cost (newi2pat);
800 new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
801 ? new_i2_cost + new_i3_cost : 0;
805 new_cost = new_i3_cost;
809 if (undobuf.other_insn)
811 int old_other_cost, new_other_cost;
813 old_other_cost = INSN_COST (undobuf.other_insn);
814 new_other_cost = insn_rtx_cost (newotherpat);
815 if (old_other_cost > 0 && new_other_cost > 0)
817 old_cost += old_other_cost;
818 new_cost += new_other_cost;
824 /* Disallow this recombination if both new_cost and old_cost are
825 greater than zero, and new_cost is greater than old cost. */
827 && new_cost > old_cost)
834 "rejecting combination of insns %d, %d and %d\n",
835 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
836 fprintf (dump_file, "original costs %d + %d + %d = %d\n",
837 i1_cost, i2_cost, i3_cost, old_cost);
842 "rejecting combination of insns %d and %d\n",
843 INSN_UID (i2), INSN_UID (i3));
844 fprintf (dump_file, "original costs %d + %d = %d\n",
845 i2_cost, i3_cost, old_cost);
850 fprintf (dump_file, "replacement costs %d + %d = %d\n",
851 new_i2_cost, new_i3_cost, new_cost);
854 fprintf (dump_file, "replacement cost %d\n", new_cost);
860 /* Update the uid_insn_cost array with the replacement costs. */
861 INSN_COST (i2) = new_i2_cost;
862 INSN_COST (i3) = new_i3_cost;
870 /* Delete any insns that copy a register to itself. */
873 delete_noop_moves (void)
880 for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
882 next = NEXT_INSN (insn);
883 if (INSN_P (insn) && noop_move_p (insn))
886 fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn));
888 delete_insn_and_edges (insn);
895 /* Fill in log links field for all insns. */
898 create_log_links (void)
902 struct df_ref **def_vec, **use_vec;
904 next_use = XCNEWVEC (rtx, max_reg_num ());
906 /* Pass through each block from the end, recording the uses of each
907 register and establishing log links when def is encountered.
908 Note that we do not clear next_use array in order to save time,
909 so we have to test whether the use is in the same basic block as def.
911 There are a few cases below when we do not consider the definition or
912 usage -- these are taken from original flow.c did. Don't ask me why it is
913 done this way; I don't know and if it works, I don't want to know. */
917 FOR_BB_INSNS_REVERSE (bb, insn)
922 /* Log links are created only once. */
923 gcc_assert (!LOG_LINKS (insn));
925 for (def_vec = DF_INSN_DEFS (insn); *def_vec; def_vec++)
927 struct df_ref *def = *def_vec;
928 int regno = DF_REF_REGNO (def);
931 if (!next_use[regno])
934 /* Do not consider if it is pre/post modification in MEM. */
935 if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY)
938 /* Do not make the log link for frame pointer. */
939 if ((regno == FRAME_POINTER_REGNUM
940 && (! reload_completed || frame_pointer_needed))
941 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
942 || (regno == HARD_FRAME_POINTER_REGNUM
943 && (! reload_completed || frame_pointer_needed))
945 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
946 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
951 use_insn = next_use[regno];
952 if (BLOCK_FOR_INSN (use_insn) == bb)
956 We don't build a LOG_LINK for hard registers contained
957 in ASM_OPERANDs. If these registers get replaced,
958 we might wind up changing the semantics of the insn,
959 even if reload can make what appear to be valid
960 assignments later. */
961 if (regno >= FIRST_PSEUDO_REGISTER
962 || asm_noperands (PATTERN (use_insn)) < 0)
964 /* Don't add duplicate links between instructions. */
966 for (links = LOG_LINKS (use_insn); links;
967 links = XEXP (links, 1))
968 if (insn == XEXP (links, 0))
972 LOG_LINKS (use_insn) =
973 alloc_INSN_LIST (insn, LOG_LINKS (use_insn));
976 next_use[regno] = NULL_RTX;
979 for (use_vec = DF_INSN_USES (insn); *use_vec; use_vec++)
981 struct df_ref *use = *use_vec;
982 int regno = DF_REF_REGNO (use);
984 /* Do not consider the usage of the stack pointer
986 if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE)
989 next_use[regno] = insn;
997 /* Clear LOG_LINKS fields of insns. */
1000 clear_log_links (void)
1004 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
1006 free_INSN_LIST_list (&LOG_LINKS (insn));
1012 /* Main entry point for combiner. F is the first insn of the function.
1013 NREGS is the first unused pseudo-reg number.
1015 Return nonzero if the combiner has turned an indirect jump
1016 instruction into a direct jump. */
1018 combine_instructions (rtx f, unsigned int nregs)
1024 rtx links, nextlinks;
1027 int new_direct_jump_p = 0;
1029 for (first = f; first && !INSN_P (first); )
1030 first = NEXT_INSN (first);
1034 combine_attempts = 0;
1037 combine_successes = 0;
1039 rtl_hooks = combine_rtl_hooks;
1041 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
1043 init_recog_no_volatile ();
1045 /* Allocate array for insn info. */
1046 max_uid_known = get_max_uid ();
1047 uid_log_links = XCNEWVEC (rtx, max_uid_known + 1);
1048 uid_insn_cost = XCNEWVEC (int, max_uid_known + 1);
1050 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
1052 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1053 problems when, for example, we have j <<= 1 in a loop. */
1055 nonzero_sign_valid = 0;
1057 /* Scan all SETs and see if we can deduce anything about what
1058 bits are known to be zero for some registers and how many copies
1059 of the sign bit are known to exist for those registers.
1061 Also set any known values so that we can use it while searching
1062 for what bits are known to be set. */
1064 label_tick = label_tick_ebb_start = 1;
1066 setup_incoming_promotions (first);
1068 create_log_links ();
1069 FOR_EACH_BB (this_basic_block)
1074 FOR_BB_INSNS (this_basic_block, insn)
1075 if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
1077 subst_low_luid = DF_INSN_LUID (insn);
1080 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
1082 record_dead_and_set_regs (insn);
1085 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
1086 if (REG_NOTE_KIND (links) == REG_INC)
1087 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
1091 /* Record the current insn_rtx_cost of this instruction. */
1092 if (NONJUMP_INSN_P (insn))
1093 INSN_COST (insn) = insn_rtx_cost (PATTERN (insn));
1095 fprintf(dump_file, "insn_cost %d: %d\n",
1096 INSN_UID (insn), INSN_COST (insn));
1098 else if (LABEL_P (insn))
1099 label_tick_ebb_start = label_tick;
1102 nonzero_sign_valid = 1;
1104 /* Now scan all the insns in forward order. */
1106 label_tick = label_tick_ebb_start = 1;
1108 setup_incoming_promotions (first);
1110 FOR_EACH_BB (this_basic_block)
1115 for (insn = BB_HEAD (this_basic_block);
1116 insn != NEXT_INSN (BB_END (this_basic_block));
1117 insn = next ? next : NEXT_INSN (insn))
1122 /* See if we know about function return values before this
1123 insn based upon SUBREG flags. */
1124 check_promoted_subreg (insn, PATTERN (insn));
1126 /* See if we can find hardregs and subreg of pseudos in
1127 narrower modes. This could help turning TRUNCATEs
1129 note_uses (&PATTERN (insn), record_truncated_values, NULL);
1131 /* Try this insn with each insn it links back to. */
1133 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1134 if ((next = try_combine (insn, XEXP (links, 0),
1135 NULL_RTX, &new_direct_jump_p)) != 0)
1138 /* Try each sequence of three linked insns ending with this one. */
1140 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1142 rtx link = XEXP (links, 0);
1144 /* If the linked insn has been replaced by a note, then there
1145 is no point in pursuing this chain any further. */
1149 for (nextlinks = LOG_LINKS (link);
1151 nextlinks = XEXP (nextlinks, 1))
1152 if ((next = try_combine (insn, link,
1153 XEXP (nextlinks, 0),
1154 &new_direct_jump_p)) != 0)
1159 /* Try to combine a jump insn that uses CC0
1160 with a preceding insn that sets CC0, and maybe with its
1161 logical predecessor as well.
1162 This is how we make decrement-and-branch insns.
1163 We need this special code because data flow connections
1164 via CC0 do not get entered in LOG_LINKS. */
1167 && (prev = prev_nonnote_insn (insn)) != 0
1168 && NONJUMP_INSN_P (prev)
1169 && sets_cc0_p (PATTERN (prev)))
1171 if ((next = try_combine (insn, prev,
1172 NULL_RTX, &new_direct_jump_p)) != 0)
1175 for (nextlinks = LOG_LINKS (prev); nextlinks;
1176 nextlinks = XEXP (nextlinks, 1))
1177 if ((next = try_combine (insn, prev,
1178 XEXP (nextlinks, 0),
1179 &new_direct_jump_p)) != 0)
1183 /* Do the same for an insn that explicitly references CC0. */
1184 if (NONJUMP_INSN_P (insn)
1185 && (prev = prev_nonnote_insn (insn)) != 0
1186 && NONJUMP_INSN_P (prev)
1187 && sets_cc0_p (PATTERN (prev))
1188 && GET_CODE (PATTERN (insn)) == SET
1189 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
1191 if ((next = try_combine (insn, prev,
1192 NULL_RTX, &new_direct_jump_p)) != 0)
1195 for (nextlinks = LOG_LINKS (prev); nextlinks;
1196 nextlinks = XEXP (nextlinks, 1))
1197 if ((next = try_combine (insn, prev,
1198 XEXP (nextlinks, 0),
1199 &new_direct_jump_p)) != 0)
1203 /* Finally, see if any of the insns that this insn links to
1204 explicitly references CC0. If so, try this insn, that insn,
1205 and its predecessor if it sets CC0. */
1206 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1207 if (NONJUMP_INSN_P (XEXP (links, 0))
1208 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
1209 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
1210 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
1211 && NONJUMP_INSN_P (prev)
1212 && sets_cc0_p (PATTERN (prev))
1213 && (next = try_combine (insn, XEXP (links, 0),
1214 prev, &new_direct_jump_p)) != 0)
1218 /* Try combining an insn with two different insns whose results it
1220 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1221 for (nextlinks = XEXP (links, 1); nextlinks;
1222 nextlinks = XEXP (nextlinks, 1))
1223 if ((next = try_combine (insn, XEXP (links, 0),
1224 XEXP (nextlinks, 0),
1225 &new_direct_jump_p)) != 0)
1228 /* Try this insn with each REG_EQUAL note it links back to. */
1229 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1232 rtx temp = XEXP (links, 0);
1233 if ((set = single_set (temp)) != 0
1234 && (note = find_reg_equal_equiv_note (temp)) != 0
1235 && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
1236 /* Avoid using a register that may already been marked
1237 dead by an earlier instruction. */
1238 && ! unmentioned_reg_p (note, SET_SRC (set))
1239 && (GET_MODE (note) == VOIDmode
1240 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
1241 : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
1243 /* Temporarily replace the set's source with the
1244 contents of the REG_EQUAL note. The insn will
1245 be deleted or recognized by try_combine. */
1246 rtx orig = SET_SRC (set);
1247 SET_SRC (set) = note;
1249 i2mod_old_rhs = copy_rtx (orig);
1250 i2mod_new_rhs = copy_rtx (note);
1251 next = try_combine (insn, i2mod, NULL_RTX,
1252 &new_direct_jump_p);
1256 SET_SRC (set) = orig;
1261 record_dead_and_set_regs (insn);
1266 else if (LABEL_P (insn))
1267 label_tick_ebb_start = label_tick;
1273 new_direct_jump_p |= purge_all_dead_edges ();
1274 delete_noop_moves ();
1277 free (uid_log_links);
1278 free (uid_insn_cost);
1279 VEC_free (reg_stat_type, heap, reg_stat);
1282 struct undo *undo, *next;
1283 for (undo = undobuf.frees; undo; undo = next)
1291 total_attempts += combine_attempts;
1292 total_merges += combine_merges;
1293 total_extras += combine_extras;
1294 total_successes += combine_successes;
1296 nonzero_sign_valid = 0;
1297 rtl_hooks = general_rtl_hooks;
1299 /* Make recognizer allow volatile MEMs again. */
1302 return new_direct_jump_p;
1305 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1308 init_reg_last (void)
1313 for (i = 0; VEC_iterate (reg_stat_type, reg_stat, i, p); ++i)
1314 memset (p, 0, offsetof (reg_stat_type, sign_bit_copies));
1317 /* Set up any promoted values for incoming argument registers. */
1320 setup_incoming_promotions (rtx first)
1323 bool strictly_local = false;
1325 if (!targetm.calls.promote_function_args (TREE_TYPE (cfun->decl)))
1328 for (arg = DECL_ARGUMENTS (current_function_decl); arg;
1329 arg = TREE_CHAIN (arg))
1331 rtx reg = DECL_INCOMING_RTL (arg);
1333 enum machine_mode mode1, mode2, mode3, mode4;
1335 /* Only continue if the incoming argument is in a register. */
1339 /* Determine, if possible, whether all call sites of the current
1340 function lie within the current compilation unit. (This does
1341 take into account the exporting of a function via taking its
1342 address, and so forth.) */
1343 strictly_local = cgraph_local_info (current_function_decl)->local;
1345 /* The mode and signedness of the argument before any promotions happen
1346 (equal to the mode of the pseudo holding it at that stage). */
1347 mode1 = TYPE_MODE (TREE_TYPE (arg));
1348 uns1 = TYPE_UNSIGNED (TREE_TYPE (arg));
1350 /* The mode and signedness of the argument after any source language and
1351 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1352 mode2 = TYPE_MODE (DECL_ARG_TYPE (arg));
1353 uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg));
1355 /* The mode and signedness of the argument as it is actually passed,
1356 after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */
1357 mode3 = promote_mode (DECL_ARG_TYPE (arg), mode2, &uns3, 1);
1359 /* The mode of the register in which the argument is being passed. */
1360 mode4 = GET_MODE (reg);
1362 /* Eliminate sign extensions in the callee when possible. Only
1364 (a) a mode promotion has occurred;
1365 (b) the mode of the register is the same as the mode of
1366 the argument as it is passed; and
1367 (c) the signedness does not change across any of the promotions; and
1368 (d) when no language-level promotions (which we cannot guarantee
1369 will have been done by an external caller) are necessary,
1370 unless we know that this function is only ever called from
1371 the current compilation unit -- all of whose call sites will
1372 do the mode1 --> mode2 promotion. */
1376 && (mode1 == mode2 || strictly_local))
1378 /* Record that the value was promoted from mode1 to mode3,
1379 so that any sign extension at the head of the current
1380 function may be eliminated. */
1382 x = gen_rtx_CLOBBER (mode1, const0_rtx);
1383 x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x);
1384 record_value_for_reg (reg, first, x);
1389 /* Called via note_stores. If X is a pseudo that is narrower than
1390 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1392 If we are setting only a portion of X and we can't figure out what
1393 portion, assume all bits will be used since we don't know what will
1396 Similarly, set how many bits of X are known to be copies of the sign bit
1397 at all locations in the function. This is the smallest number implied
1401 set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data)
1403 rtx insn = (rtx) data;
1407 && REGNO (x) >= FIRST_PSEUDO_REGISTER
1408 /* If this register is undefined at the start of the file, we can't
1409 say what its contents were. */
1410 && ! REGNO_REG_SET_P
1411 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x))
1412 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
1414 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
1416 if (set == 0 || GET_CODE (set) == CLOBBER)
1418 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1419 rsp->sign_bit_copies = 1;
1423 /* If this register is being initialized using itself, and the
1424 register is uninitialized in this basic block, and there are
1425 no LOG_LINKS which set the register, then part of the
1426 register is uninitialized. In that case we can't assume
1427 anything about the number of nonzero bits.
1429 ??? We could do better if we checked this in
1430 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1431 could avoid making assumptions about the insn which initially
1432 sets the register, while still using the information in other
1433 insns. We would have to be careful to check every insn
1434 involved in the combination. */
1437 && reg_referenced_p (x, PATTERN (insn))
1438 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)),
1443 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
1445 if (dead_or_set_p (XEXP (link, 0), x))
1450 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1451 rsp->sign_bit_copies = 1;
1456 /* If this is a complex assignment, see if we can convert it into a
1457 simple assignment. */
1458 set = expand_field_assignment (set);
1460 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1461 set what we know about X. */
1463 if (SET_DEST (set) == x
1464 || (GET_CODE (SET_DEST (set)) == SUBREG
1465 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
1466 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
1467 && SUBREG_REG (SET_DEST (set)) == x))
1469 rtx src = SET_SRC (set);
1471 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1472 /* If X is narrower than a word and SRC is a non-negative
1473 constant that would appear negative in the mode of X,
1474 sign-extend it for use in reg_stat[].nonzero_bits because some
1475 machines (maybe most) will actually do the sign-extension
1476 and this is the conservative approach.
1478 ??? For 2.5, try to tighten up the MD files in this regard
1479 instead of this kludge. */
1481 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
1482 && GET_CODE (src) == CONST_INT
1484 && 0 != (INTVAL (src)
1485 & ((HOST_WIDE_INT) 1
1486 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
1487 src = GEN_INT (INTVAL (src)
1488 | ((HOST_WIDE_INT) (-1)
1489 << GET_MODE_BITSIZE (GET_MODE (x))));
1492 /* Don't call nonzero_bits if it cannot change anything. */
1493 if (rsp->nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1494 rsp->nonzero_bits |= nonzero_bits (src, nonzero_bits_mode);
1495 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1496 if (rsp->sign_bit_copies == 0
1497 || rsp->sign_bit_copies > num)
1498 rsp->sign_bit_copies = num;
1502 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1503 rsp->sign_bit_copies = 1;
1508 /* See if INSN can be combined into I3. PRED and SUCC are optionally
1509 insns that were previously combined into I3 or that will be combined
1510 into the merger of INSN and I3.
1512 Return 0 if the combination is not allowed for any reason.
1514 If the combination is allowed, *PDEST will be set to the single
1515 destination of INSN and *PSRC to the single source, and this function
1519 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ,
1520 rtx *pdest, rtx *psrc)
1529 int all_adjacent = (succ ? (next_active_insn (insn) == succ
1530 && next_active_insn (succ) == i3)
1531 : next_active_insn (insn) == i3);
1533 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1534 or a PARALLEL consisting of such a SET and CLOBBERs.
1536 If INSN has CLOBBER parallel parts, ignore them for our processing.
1537 By definition, these happen during the execution of the insn. When it
1538 is merged with another insn, all bets are off. If they are, in fact,
1539 needed and aren't also supplied in I3, they may be added by
1540 recog_for_combine. Otherwise, it won't match.
1542 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1545 Get the source and destination of INSN. If more than one, can't
1548 if (GET_CODE (PATTERN (insn)) == SET)
1549 set = PATTERN (insn);
1550 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1551 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1553 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1555 rtx elt = XVECEXP (PATTERN (insn), 0, i);
1558 switch (GET_CODE (elt))
1560 /* This is important to combine floating point insns
1561 for the SH4 port. */
1563 /* Combining an isolated USE doesn't make sense.
1564 We depend here on combinable_i3pat to reject them. */
1565 /* The code below this loop only verifies that the inputs of
1566 the SET in INSN do not change. We call reg_set_between_p
1567 to verify that the REG in the USE does not change between
1569 If the USE in INSN was for a pseudo register, the matching
1570 insn pattern will likely match any register; combining this
1571 with any other USE would only be safe if we knew that the
1572 used registers have identical values, or if there was
1573 something to tell them apart, e.g. different modes. For
1574 now, we forgo such complicated tests and simply disallow
1575 combining of USES of pseudo registers with any other USE. */
1576 if (REG_P (XEXP (elt, 0))
1577 && GET_CODE (PATTERN (i3)) == PARALLEL)
1579 rtx i3pat = PATTERN (i3);
1580 int i = XVECLEN (i3pat, 0) - 1;
1581 unsigned int regno = REGNO (XEXP (elt, 0));
1585 rtx i3elt = XVECEXP (i3pat, 0, i);
1587 if (GET_CODE (i3elt) == USE
1588 && REG_P (XEXP (i3elt, 0))
1589 && (REGNO (XEXP (i3elt, 0)) == regno
1590 ? reg_set_between_p (XEXP (elt, 0),
1591 PREV_INSN (insn), i3)
1592 : regno >= FIRST_PSEUDO_REGISTER))
1599 /* We can ignore CLOBBERs. */
1604 /* Ignore SETs whose result isn't used but not those that
1605 have side-effects. */
1606 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1607 && (!(note = find_reg_note (insn, REG_EH_REGION, NULL_RTX))
1608 || INTVAL (XEXP (note, 0)) <= 0)
1609 && ! side_effects_p (elt))
1612 /* If we have already found a SET, this is a second one and
1613 so we cannot combine with this insn. */
1621 /* Anything else means we can't combine. */
1627 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1628 so don't do anything with it. */
1629 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1638 set = expand_field_assignment (set);
1639 src = SET_SRC (set), dest = SET_DEST (set);
1641 /* Don't eliminate a store in the stack pointer. */
1642 if (dest == stack_pointer_rtx
1643 /* Don't combine with an insn that sets a register to itself if it has
1644 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1645 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1646 /* Can't merge an ASM_OPERANDS. */
1647 || GET_CODE (src) == ASM_OPERANDS
1648 /* Can't merge a function call. */
1649 || GET_CODE (src) == CALL
1650 /* Don't eliminate a function call argument. */
1652 && (find_reg_fusage (i3, USE, dest)
1654 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1655 && global_regs[REGNO (dest)])))
1656 /* Don't substitute into an incremented register. */
1657 || FIND_REG_INC_NOTE (i3, dest)
1658 || (succ && FIND_REG_INC_NOTE (succ, dest))
1659 /* Don't substitute into a non-local goto, this confuses CFG. */
1660 || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1661 /* Make sure that DEST is not used after SUCC but before I3. */
1662 || (succ && ! all_adjacent
1663 && reg_used_between_p (dest, succ, i3))
1664 /* Make sure that the value that is to be substituted for the register
1665 does not use any registers whose values alter in between. However,
1666 If the insns are adjacent, a use can't cross a set even though we
1667 think it might (this can happen for a sequence of insns each setting
1668 the same destination; last_set of that register might point to
1669 a NOTE). If INSN has a REG_EQUIV note, the register is always
1670 equivalent to the memory so the substitution is valid even if there
1671 are intervening stores. Also, don't move a volatile asm or
1672 UNSPEC_VOLATILE across any other insns. */
1675 || ! find_reg_note (insn, REG_EQUIV, src))
1676 && use_crosses_set_p (src, DF_INSN_LUID (insn)))
1677 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1678 || GET_CODE (src) == UNSPEC_VOLATILE))
1679 /* Don't combine across a CALL_INSN, because that would possibly
1680 change whether the life span of some REGs crosses calls or not,
1681 and it is a pain to update that information.
1682 Exception: if source is a constant, moving it later can't hurt.
1683 Accept that as a special case. */
1684 || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src)))
1687 /* DEST must either be a REG or CC0. */
1690 /* If register alignment is being enforced for multi-word items in all
1691 cases except for parameters, it is possible to have a register copy
1692 insn referencing a hard register that is not allowed to contain the
1693 mode being copied and which would not be valid as an operand of most
1694 insns. Eliminate this problem by not combining with such an insn.
1696 Also, on some machines we don't want to extend the life of a hard
1700 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1701 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1702 /* Don't extend the life of a hard register unless it is
1703 user variable (if we have few registers) or it can't
1704 fit into the desired register (meaning something special
1706 Also avoid substituting a return register into I3, because
1707 reload can't handle a conflict with constraints of other
1709 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1710 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1713 else if (GET_CODE (dest) != CC0)
1717 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1718 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1719 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1721 /* Don't substitute for a register intended as a clobberable
1723 rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1724 if (rtx_equal_p (reg, dest))
1727 /* If the clobber represents an earlyclobber operand, we must not
1728 substitute an expression containing the clobbered register.
1729 As we do not analyze the constraint strings here, we have to
1730 make the conservative assumption. However, if the register is
1731 a fixed hard reg, the clobber cannot represent any operand;
1732 we leave it up to the machine description to either accept or
1733 reject use-and-clobber patterns. */
1735 || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1736 || !fixed_regs[REGNO (reg)])
1737 if (reg_overlap_mentioned_p (reg, src))
1741 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1742 or not), reject, unless nothing volatile comes between it and I3 */
1744 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1746 /* Make sure succ doesn't contain a volatile reference. */
1747 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1750 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1751 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1755 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1756 to be an explicit register variable, and was chosen for a reason. */
1758 if (GET_CODE (src) == ASM_OPERANDS
1759 && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1762 /* If there are any volatile insns between INSN and I3, reject, because
1763 they might affect machine state. */
1765 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1766 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1769 /* If INSN contains an autoincrement or autodecrement, make sure that
1770 register is not used between there and I3, and not already used in
1771 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1772 Also insist that I3 not be a jump; if it were one
1773 and the incremented register were spilled, we would lose. */
1776 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1777 if (REG_NOTE_KIND (link) == REG_INC
1779 || reg_used_between_p (XEXP (link, 0), insn, i3)
1780 || (pred != NULL_RTX
1781 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1782 || (succ != NULL_RTX
1783 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1784 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1789 /* Don't combine an insn that follows a CC0-setting insn.
1790 An insn that uses CC0 must not be separated from the one that sets it.
1791 We do, however, allow I2 to follow a CC0-setting insn if that insn
1792 is passed as I1; in that case it will be deleted also.
1793 We also allow combining in this case if all the insns are adjacent
1794 because that would leave the two CC0 insns adjacent as well.
1795 It would be more logical to test whether CC0 occurs inside I1 or I2,
1796 but that would be much slower, and this ought to be equivalent. */
1798 p = prev_nonnote_insn (insn);
1799 if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
1804 /* If we get here, we have passed all the tests and the combination is
1813 /* LOC is the location within I3 that contains its pattern or the component
1814 of a PARALLEL of the pattern. We validate that it is valid for combining.
1816 One problem is if I3 modifies its output, as opposed to replacing it
1817 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1818 so would produce an insn that is not equivalent to the original insns.
1822 (set (reg:DI 101) (reg:DI 100))
1823 (set (subreg:SI (reg:DI 101) 0) <foo>)
1825 This is NOT equivalent to:
1827 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1828 (set (reg:DI 101) (reg:DI 100))])
1830 Not only does this modify 100 (in which case it might still be valid
1831 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1833 We can also run into a problem if I2 sets a register that I1
1834 uses and I1 gets directly substituted into I3 (not via I2). In that
1835 case, we would be getting the wrong value of I2DEST into I3, so we
1836 must reject the combination. This case occurs when I2 and I1 both
1837 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1838 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1839 of a SET must prevent combination from occurring.
1841 Before doing the above check, we first try to expand a field assignment
1842 into a set of logical operations.
1844 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1845 we place a register that is both set and used within I3. If more than one
1846 such register is detected, we fail.
1848 Return 1 if the combination is valid, zero otherwise. */
1851 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest,
1852 int i1_not_in_src, rtx *pi3dest_killed)
1856 if (GET_CODE (x) == SET)
1859 rtx dest = SET_DEST (set);
1860 rtx src = SET_SRC (set);
1861 rtx inner_dest = dest;
1864 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1865 || GET_CODE (inner_dest) == SUBREG
1866 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1867 inner_dest = XEXP (inner_dest, 0);
1869 /* Check for the case where I3 modifies its output, as discussed
1870 above. We don't want to prevent pseudos from being combined
1871 into the address of a MEM, so only prevent the combination if
1872 i1 or i2 set the same MEM. */
1873 if ((inner_dest != dest &&
1874 (!MEM_P (inner_dest)
1875 || rtx_equal_p (i2dest, inner_dest)
1876 || (i1dest && rtx_equal_p (i1dest, inner_dest)))
1877 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1878 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1880 /* This is the same test done in can_combine_p except we can't test
1881 all_adjacent; we don't have to, since this instruction will stay
1882 in place, thus we are not considering increasing the lifetime of
1885 Also, if this insn sets a function argument, combining it with
1886 something that might need a spill could clobber a previous
1887 function argument; the all_adjacent test in can_combine_p also
1888 checks this; here, we do a more specific test for this case. */
1890 || (REG_P (inner_dest)
1891 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1892 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1893 GET_MODE (inner_dest))))
1894 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1897 /* If DEST is used in I3, it is being killed in this insn, so
1898 record that for later. We have to consider paradoxical
1899 subregs here, since they kill the whole register, but we
1900 ignore partial subregs, STRICT_LOW_PART, etc.
1901 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1902 STACK_POINTER_REGNUM, since these are always considered to be
1903 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1905 if (GET_CODE (subdest) == SUBREG
1906 && (GET_MODE_SIZE (GET_MODE (subdest))
1907 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
1908 subdest = SUBREG_REG (subdest);
1911 && reg_referenced_p (subdest, PATTERN (i3))
1912 && REGNO (subdest) != FRAME_POINTER_REGNUM
1913 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1914 && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
1916 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1917 && (REGNO (subdest) != ARG_POINTER_REGNUM
1918 || ! fixed_regs [REGNO (subdest)])
1920 && REGNO (subdest) != STACK_POINTER_REGNUM)
1922 if (*pi3dest_killed)
1925 *pi3dest_killed = subdest;
1929 else if (GET_CODE (x) == PARALLEL)
1933 for (i = 0; i < XVECLEN (x, 0); i++)
1934 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1935 i1_not_in_src, pi3dest_killed))
1942 /* Return 1 if X is an arithmetic expression that contains a multiplication
1943 and division. We don't count multiplications by powers of two here. */
1946 contains_muldiv (rtx x)
1948 switch (GET_CODE (x))
1950 case MOD: case DIV: case UMOD: case UDIV:
1954 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1955 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1958 return contains_muldiv (XEXP (x, 0))
1959 || contains_muldiv (XEXP (x, 1));
1962 return contains_muldiv (XEXP (x, 0));
1968 /* Determine whether INSN can be used in a combination. Return nonzero if
1969 not. This is used in try_combine to detect early some cases where we
1970 can't perform combinations. */
1973 cant_combine_insn_p (rtx insn)
1978 /* If this isn't really an insn, we can't do anything.
1979 This can occur when flow deletes an insn that it has merged into an
1980 auto-increment address. */
1981 if (! INSN_P (insn))
1984 /* Never combine loads and stores involving hard regs that are likely
1985 to be spilled. The register allocator can usually handle such
1986 reg-reg moves by tying. If we allow the combiner to make
1987 substitutions of likely-spilled regs, reload might die.
1988 As an exception, we allow combinations involving fixed regs; these are
1989 not available to the register allocator so there's no risk involved. */
1991 set = single_set (insn);
1994 src = SET_SRC (set);
1995 dest = SET_DEST (set);
1996 if (GET_CODE (src) == SUBREG)
1997 src = SUBREG_REG (src);
1998 if (GET_CODE (dest) == SUBREG)
1999 dest = SUBREG_REG (dest);
2000 if (REG_P (src) && REG_P (dest)
2001 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
2002 && ! fixed_regs[REGNO (src)]
2003 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src))))
2004 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
2005 && ! fixed_regs[REGNO (dest)]
2006 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest))))))
2012 struct likely_spilled_retval_info
2014 unsigned regno, nregs;
2018 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2019 hard registers that are known to be written to / clobbered in full. */
2021 likely_spilled_retval_1 (rtx x, const_rtx set, void *data)
2023 struct likely_spilled_retval_info *const info =
2024 (struct likely_spilled_retval_info *) data;
2025 unsigned regno, nregs;
2028 if (!REG_P (XEXP (set, 0)))
2031 if (regno >= info->regno + info->nregs)
2033 nregs = hard_regno_nregs[regno][GET_MODE (x)];
2034 if (regno + nregs <= info->regno)
2036 new_mask = (2U << (nregs - 1)) - 1;
2037 if (regno < info->regno)
2038 new_mask >>= info->regno - regno;
2040 new_mask <<= regno - info->regno;
2041 info->mask &= ~new_mask;
2044 /* Return nonzero iff part of the return value is live during INSN, and
2045 it is likely spilled. This can happen when more than one insn is needed
2046 to copy the return value, e.g. when we consider to combine into the
2047 second copy insn for a complex value. */
2050 likely_spilled_retval_p (rtx insn)
2052 rtx use = BB_END (this_basic_block);
2054 unsigned regno, nregs;
2055 /* We assume here that no machine mode needs more than
2056 32 hard registers when the value overlaps with a register
2057 for which FUNCTION_VALUE_REGNO_P is true. */
2059 struct likely_spilled_retval_info info;
2061 if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
2063 reg = XEXP (PATTERN (use), 0);
2064 if (!REG_P (reg) || !FUNCTION_VALUE_REGNO_P (REGNO (reg)))
2066 regno = REGNO (reg);
2067 nregs = hard_regno_nregs[regno][GET_MODE (reg)];
2070 mask = (2U << (nregs - 1)) - 1;
2072 /* Disregard parts of the return value that are set later. */
2076 for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
2078 note_stores (PATTERN (p), likely_spilled_retval_1, &info);
2081 /* Check if any of the (probably) live return value registers is
2086 if ((mask & 1 << nregs)
2087 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (regno + nregs)))
2093 /* Adjust INSN after we made a change to its destination.
2095 Changing the destination can invalidate notes that say something about
2096 the results of the insn and a LOG_LINK pointing to the insn. */
2099 adjust_for_new_dest (rtx insn)
2101 /* For notes, be conservative and simply remove them. */
2102 remove_reg_equal_equiv_notes (insn);
2104 /* The new insn will have a destination that was previously the destination
2105 of an insn just above it. Call distribute_links to make a LOG_LINK from
2106 the next use of that destination. */
2107 distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX));
2109 df_insn_rescan (insn);
2112 /* Return TRUE if combine can reuse reg X in mode MODE.
2113 ADDED_SETS is nonzero if the original set is still required. */
2115 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
2123 /* Allow hard registers if the new mode is legal, and occupies no more
2124 registers than the old mode. */
2125 if (regno < FIRST_PSEUDO_REGISTER)
2126 return (HARD_REGNO_MODE_OK (regno, mode)
2127 && (hard_regno_nregs[regno][GET_MODE (x)]
2128 >= hard_regno_nregs[regno][mode]));
2130 /* Or a pseudo that is only used once. */
2131 return (REG_N_SETS (regno) == 1 && !added_sets
2132 && !REG_USERVAR_P (x));
2136 /* Check whether X, the destination of a set, refers to part of
2137 the register specified by REG. */
2140 reg_subword_p (rtx x, rtx reg)
2142 /* Check that reg is an integer mode register. */
2143 if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
2146 if (GET_CODE (x) == STRICT_LOW_PART
2147 || GET_CODE (x) == ZERO_EXTRACT)
2150 return GET_CODE (x) == SUBREG
2151 && SUBREG_REG (x) == reg
2152 && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
2156 /* Try to combine the insns I1 and I2 into I3.
2157 Here I1 and I2 appear earlier than I3.
2158 I1 can be zero; then we combine just I2 into I3.
2160 If we are combining three insns and the resulting insn is not recognized,
2161 try splitting it into two insns. If that happens, I2 and I3 are retained
2162 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
2165 Return 0 if the combination does not work. Then nothing is changed.
2166 If we did the combination, return the insn at which combine should
2169 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2170 new direct jump instruction. */
2173 try_combine (rtx i3, rtx i2, rtx i1, int *new_direct_jump_p)
2175 /* New patterns for I3 and I2, respectively. */
2176 rtx newpat, newi2pat = 0;
2177 rtvec newpat_vec_with_clobbers = 0;
2178 int substed_i2 = 0, substed_i1 = 0;
2179 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
2180 int added_sets_1, added_sets_2;
2181 /* Total number of SETs to put into I3. */
2183 /* Nonzero if I2's body now appears in I3. */
2185 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2186 int insn_code_number, i2_code_number = 0, other_code_number = 0;
2187 /* Contains I3 if the destination of I3 is used in its source, which means
2188 that the old life of I3 is being killed. If that usage is placed into
2189 I2 and not in I3, a REG_DEAD note must be made. */
2190 rtx i3dest_killed = 0;
2191 /* SET_DEST and SET_SRC of I2 and I1. */
2192 rtx i2dest, i2src, i1dest = 0, i1src = 0;
2193 /* PATTERN (I1) and PATTERN (I2), or a copy of it in certain cases. */
2194 rtx i1pat = 0, i2pat = 0;
2195 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2196 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
2197 int i2dest_killed = 0, i1dest_killed = 0;
2198 int i1_feeds_i3 = 0;
2199 /* Notes that must be added to REG_NOTES in I3 and I2. */
2200 rtx new_i3_notes, new_i2_notes;
2201 /* Notes that we substituted I3 into I2 instead of the normal case. */
2202 int i3_subst_into_i2 = 0;
2203 /* Notes that I1, I2 or I3 is a MULT operation. */
2211 rtx new_other_notes;
2214 /* Exit early if one of the insns involved can't be used for
2216 if (cant_combine_insn_p (i3)
2217 || cant_combine_insn_p (i2)
2218 || (i1 && cant_combine_insn_p (i1))
2219 || likely_spilled_retval_p (i3))
2223 undobuf.other_insn = 0;
2225 /* Reset the hard register usage information. */
2226 CLEAR_HARD_REG_SET (newpat_used_regs);
2228 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
2229 code below, set I1 to be the earlier of the two insns. */
2230 if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2))
2231 temp = i1, i1 = i2, i2 = temp;
2233 added_links_insn = 0;
2235 /* First check for one important special-case that the code below will
2236 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2237 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2238 we may be able to replace that destination with the destination of I3.
2239 This occurs in the common code where we compute both a quotient and
2240 remainder into a structure, in which case we want to do the computation
2241 directly into the structure to avoid register-register copies.
2243 Note that this case handles both multiple sets in I2 and also
2244 cases where I2 has a number of CLOBBER or PARALLELs.
2246 We make very conservative checks below and only try to handle the
2247 most common cases of this. For example, we only handle the case
2248 where I2 and I3 are adjacent to avoid making difficult register
2251 if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
2252 && REG_P (SET_SRC (PATTERN (i3)))
2253 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
2254 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
2255 && GET_CODE (PATTERN (i2)) == PARALLEL
2256 && ! side_effects_p (SET_DEST (PATTERN (i3)))
2257 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2258 below would need to check what is inside (and reg_overlap_mentioned_p
2259 doesn't support those codes anyway). Don't allow those destinations;
2260 the resulting insn isn't likely to be recognized anyway. */
2261 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
2262 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
2263 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
2264 SET_DEST (PATTERN (i3)))
2265 && next_real_insn (i2) == i3)
2267 rtx p2 = PATTERN (i2);
2269 /* Make sure that the destination of I3,
2270 which we are going to substitute into one output of I2,
2271 is not used within another output of I2. We must avoid making this:
2272 (parallel [(set (mem (reg 69)) ...)
2273 (set (reg 69) ...)])
2274 which is not well-defined as to order of actions.
2275 (Besides, reload can't handle output reloads for this.)
2277 The problem can also happen if the dest of I3 is a memory ref,
2278 if another dest in I2 is an indirect memory ref. */
2279 for (i = 0; i < XVECLEN (p2, 0); i++)
2280 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2281 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2282 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
2283 SET_DEST (XVECEXP (p2, 0, i))))
2286 if (i == XVECLEN (p2, 0))
2287 for (i = 0; i < XVECLEN (p2, 0); i++)
2288 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2289 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2290 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
2295 subst_low_luid = DF_INSN_LUID (i2);
2297 added_sets_2 = added_sets_1 = 0;
2298 i2dest = SET_SRC (PATTERN (i3));
2299 i2dest_killed = dead_or_set_p (i2, i2dest);
2301 /* Replace the dest in I2 with our dest and make the resulting
2302 insn the new pattern for I3. Then skip to where we
2303 validate the pattern. Everything was set up above. */
2304 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
2305 SET_DEST (PATTERN (i3)));
2308 i3_subst_into_i2 = 1;
2309 goto validate_replacement;
2313 /* If I2 is setting a pseudo to a constant and I3 is setting some
2314 sub-part of it to another constant, merge them by making a new
2317 && (temp = single_set (i2)) != 0
2318 && (GET_CODE (SET_SRC (temp)) == CONST_INT
2319 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
2320 && GET_CODE (PATTERN (i3)) == SET
2321 && (GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT
2322 || GET_CODE (SET_SRC (PATTERN (i3))) == CONST_DOUBLE)
2323 && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
2325 rtx dest = SET_DEST (PATTERN (i3));
2329 if (GET_CODE (dest) == ZERO_EXTRACT)
2331 if (GET_CODE (XEXP (dest, 1)) == CONST_INT
2332 && GET_CODE (XEXP (dest, 2)) == CONST_INT)
2334 width = INTVAL (XEXP (dest, 1));
2335 offset = INTVAL (XEXP (dest, 2));
2336 dest = XEXP (dest, 0);
2337 if (BITS_BIG_ENDIAN)
2338 offset = GET_MODE_BITSIZE (GET_MODE (dest)) - width - offset;
2343 if (GET_CODE (dest) == STRICT_LOW_PART)
2344 dest = XEXP (dest, 0);
2345 width = GET_MODE_BITSIZE (GET_MODE (dest));
2351 /* If this is the low part, we're done. */
2352 if (subreg_lowpart_p (dest))
2354 /* Handle the case where inner is twice the size of outer. */
2355 else if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2356 == 2 * GET_MODE_BITSIZE (GET_MODE (dest)))
2357 offset += GET_MODE_BITSIZE (GET_MODE (dest));
2358 /* Otherwise give up for now. */
2364 && (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2365 <= HOST_BITS_PER_WIDE_INT * 2))
2367 HOST_WIDE_INT mhi, ohi, ihi;
2368 HOST_WIDE_INT mlo, olo, ilo;
2369 rtx inner = SET_SRC (PATTERN (i3));
2370 rtx outer = SET_SRC (temp);
2372 if (GET_CODE (outer) == CONST_INT)
2374 olo = INTVAL (outer);
2375 ohi = olo < 0 ? -1 : 0;
2379 olo = CONST_DOUBLE_LOW (outer);
2380 ohi = CONST_DOUBLE_HIGH (outer);
2383 if (GET_CODE (inner) == CONST_INT)
2385 ilo = INTVAL (inner);
2386 ihi = ilo < 0 ? -1 : 0;
2390 ilo = CONST_DOUBLE_LOW (inner);
2391 ihi = CONST_DOUBLE_HIGH (inner);
2394 if (width < HOST_BITS_PER_WIDE_INT)
2396 mlo = ((unsigned HOST_WIDE_INT) 1 << width) - 1;
2399 else if (width < HOST_BITS_PER_WIDE_INT * 2)
2401 mhi = ((unsigned HOST_WIDE_INT) 1
2402 << (width - HOST_BITS_PER_WIDE_INT)) - 1;
2414 if (offset >= HOST_BITS_PER_WIDE_INT)
2416 mhi = mlo << (offset - HOST_BITS_PER_WIDE_INT);
2418 ihi = ilo << (offset - HOST_BITS_PER_WIDE_INT);
2421 else if (offset > 0)
2423 mhi = (mhi << offset) | ((unsigned HOST_WIDE_INT) mlo
2424 >> (HOST_BITS_PER_WIDE_INT - offset));
2425 mlo = mlo << offset;
2426 ihi = (ihi << offset) | ((unsigned HOST_WIDE_INT) ilo
2427 >> (HOST_BITS_PER_WIDE_INT - offset));
2428 ilo = ilo << offset;
2431 olo = (olo & ~mlo) | ilo;
2432 ohi = (ohi & ~mhi) | ihi;
2436 subst_low_luid = DF_INSN_LUID (i2);
2437 added_sets_2 = added_sets_1 = 0;
2438 i2dest = SET_DEST (temp);
2439 i2dest_killed = dead_or_set_p (i2, i2dest);
2441 SUBST (SET_SRC (temp),
2442 immed_double_const (olo, ohi, GET_MODE (SET_DEST (temp))));
2444 newpat = PATTERN (i2);
2445 goto validate_replacement;
2450 /* If we have no I1 and I2 looks like:
2451 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2453 make up a dummy I1 that is
2456 (set (reg:CC X) (compare:CC Y (const_int 0)))
2458 (We can ignore any trailing CLOBBERs.)
2460 This undoes a previous combination and allows us to match a branch-and-
2463 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2464 && XVECLEN (PATTERN (i2), 0) >= 2
2465 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2466 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2468 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2469 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2470 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2471 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2472 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2473 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2475 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2476 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2481 /* We make I1 with the same INSN_UID as I2. This gives it
2482 the same DF_INSN_LUID for value tracking. Our fake I1 will
2483 never appear in the insn stream so giving it the same INSN_UID
2484 as I2 will not cause a problem. */
2486 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
2487 BLOCK_FOR_INSN (i2), INSN_LOCATOR (i2),
2488 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX);
2490 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2491 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2492 SET_DEST (PATTERN (i1)));
2497 /* Verify that I2 and I1 are valid for combining. */
2498 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
2499 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
2505 /* Record whether I2DEST is used in I2SRC and similarly for the other
2506 cases. Knowing this will help in register status updating below. */
2507 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2508 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2509 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2510 i2dest_killed = dead_or_set_p (i2, i2dest);
2511 i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2513 /* See if I1 directly feeds into I3. It does if I1DEST is not used
2515 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
2517 /* Ensure that I3's pattern can be the destination of combines. */
2518 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
2519 i1 && i2dest_in_i1src && i1_feeds_i3,
2526 /* See if any of the insns is a MULT operation. Unless one is, we will
2527 reject a combination that is, since it must be slower. Be conservative
2529 if (GET_CODE (i2src) == MULT
2530 || (i1 != 0 && GET_CODE (i1src) == MULT)
2531 || (GET_CODE (PATTERN (i3)) == SET
2532 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2535 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2536 We used to do this EXCEPT in one case: I3 has a post-inc in an
2537 output operand. However, that exception can give rise to insns like
2539 which is a famous insn on the PDP-11 where the value of r3 used as the
2540 source was model-dependent. Avoid this sort of thing. */
2543 if (!(GET_CODE (PATTERN (i3)) == SET
2544 && REG_P (SET_SRC (PATTERN (i3)))
2545 && MEM_P (SET_DEST (PATTERN (i3)))
2546 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2547 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2548 /* It's not the exception. */
2551 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2552 if (REG_NOTE_KIND (link) == REG_INC
2553 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2555 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2562 /* See if the SETs in I1 or I2 need to be kept around in the merged
2563 instruction: whenever the value set there is still needed past I3.
2564 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2566 For the SET in I1, we have two cases: If I1 and I2 independently
2567 feed into I3, the set in I1 needs to be kept around if I1DEST dies
2568 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2569 in I1 needs to be kept around unless I1DEST dies or is set in either
2570 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
2571 I1DEST. If so, we know I1 feeds into I2. */
2573 added_sets_2 = ! dead_or_set_p (i3, i2dest);
2576 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
2577 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
2579 /* If the set in I2 needs to be kept around, we must make a copy of
2580 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2581 PATTERN (I2), we are only substituting for the original I1DEST, not into
2582 an already-substituted copy. This also prevents making self-referential
2583 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2588 if (GET_CODE (PATTERN (i2)) == PARALLEL)
2589 i2pat = gen_rtx_SET (VOIDmode, i2dest, copy_rtx (i2src));
2591 i2pat = copy_rtx (PATTERN (i2));
2596 if (GET_CODE (PATTERN (i1)) == PARALLEL)
2597 i1pat = gen_rtx_SET (VOIDmode, i1dest, copy_rtx (i1src));
2599 i1pat = copy_rtx (PATTERN (i1));
2604 /* Substitute in the latest insn for the regs set by the earlier ones. */
2606 maxreg = max_reg_num ();
2611 /* Many machines that don't use CC0 have insns that can both perform an
2612 arithmetic operation and set the condition code. These operations will
2613 be represented as a PARALLEL with the first element of the vector
2614 being a COMPARE of an arithmetic operation with the constant zero.
2615 The second element of the vector will set some pseudo to the result
2616 of the same arithmetic operation. If we simplify the COMPARE, we won't
2617 match such a pattern and so will generate an extra insn. Here we test
2618 for this case, where both the comparison and the operation result are
2619 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2620 I2SRC. Later we will make the PARALLEL that contains I2. */
2622 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
2623 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
2624 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
2625 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2627 #ifdef SELECT_CC_MODE
2629 enum machine_mode compare_mode;
2632 newpat = PATTERN (i3);
2633 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
2637 #ifdef SELECT_CC_MODE
2638 /* See if a COMPARE with the operand we substituted in should be done
2639 with the mode that is currently being used. If not, do the same
2640 processing we do in `subst' for a SET; namely, if the destination
2641 is used only once, try to replace it with a register of the proper
2642 mode and also replace the COMPARE. */
2643 if (undobuf.other_insn == 0
2644 && (cc_use = find_single_use (SET_DEST (newpat), i3,
2645 &undobuf.other_insn))
2646 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
2648 != GET_MODE (SET_DEST (newpat))))
2650 if (can_change_dest_mode(SET_DEST (newpat), added_sets_2,
2653 unsigned int regno = REGNO (SET_DEST (newpat));
2656 if (regno < FIRST_PSEUDO_REGISTER)
2657 new_dest = gen_rtx_REG (compare_mode, regno);
2660 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
2661 new_dest = regno_reg_rtx[regno];
2664 SUBST (SET_DEST (newpat), new_dest);
2665 SUBST (XEXP (*cc_use, 0), new_dest);
2666 SUBST (SET_SRC (newpat),
2667 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
2670 undobuf.other_insn = 0;
2677 /* It is possible that the source of I2 or I1 may be performing
2678 an unneeded operation, such as a ZERO_EXTEND of something
2679 that is known to have the high part zero. Handle that case
2680 by letting subst look at the innermost one of them.
2682 Another way to do this would be to have a function that tries
2683 to simplify a single insn instead of merging two or more
2684 insns. We don't do this because of the potential of infinite
2685 loops and because of the potential extra memory required.
2686 However, doing it the way we are is a bit of a kludge and
2687 doesn't catch all cases.
2689 But only do this if -fexpensive-optimizations since it slows
2690 things down and doesn't usually win.
2692 This is not done in the COMPARE case above because the
2693 unmodified I2PAT is used in the PARALLEL and so a pattern
2694 with a modified I2SRC would not match. */
2696 if (flag_expensive_optimizations)
2698 /* Pass pc_rtx so no substitutions are done, just
2702 subst_low_luid = DF_INSN_LUID (i1);
2703 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
2707 subst_low_luid = DF_INSN_LUID (i2);
2708 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
2712 n_occurrences = 0; /* `subst' counts here */
2714 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2715 need to make a unique copy of I2SRC each time we substitute it
2716 to avoid self-referential rtl. */
2718 subst_low_luid = DF_INSN_LUID (i2);
2719 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
2720 ! i1_feeds_i3 && i1dest_in_i1src);
2723 /* Record whether i2's body now appears within i3's body. */
2724 i2_is_used = n_occurrences;
2727 /* If we already got a failure, don't try to do more. Otherwise,
2728 try to substitute in I1 if we have it. */
2730 if (i1 && GET_CODE (newpat) != CLOBBER)
2732 /* Check that an autoincrement side-effect on I1 has not been lost.
2733 This happens if I1DEST is mentioned in I2 and dies there, and
2734 has disappeared from the new pattern. */
2735 if ((FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2737 && dead_or_set_p (i2, i1dest)
2738 && !reg_overlap_mentioned_p (i1dest, newpat))
2739 /* Before we can do this substitution, we must redo the test done
2740 above (see detailed comments there) that ensures that I1DEST
2741 isn't mentioned in any SETs in NEWPAT that are field assignments. */
2742 || !combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX, 0, 0))
2749 subst_low_luid = DF_INSN_LUID (i1);
2750 newpat = subst (newpat, i1dest, i1src, 0, 0);
2754 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2755 to count all the ways that I2SRC and I1SRC can be used. */
2756 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
2757 && i2_is_used + added_sets_2 > 1)
2758 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2759 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
2761 /* Fail if we tried to make a new register. */
2762 || max_reg_num () != maxreg
2763 /* Fail if we couldn't do something and have a CLOBBER. */
2764 || GET_CODE (newpat) == CLOBBER
2765 /* Fail if this new pattern is a MULT and we didn't have one before
2766 at the outer level. */
2767 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
2774 /* If the actions of the earlier insns must be kept
2775 in addition to substituting them into the latest one,
2776 we must make a new PARALLEL for the latest insn
2777 to hold additional the SETs. */
2779 if (added_sets_1 || added_sets_2)
2783 if (GET_CODE (newpat) == PARALLEL)
2785 rtvec old = XVEC (newpat, 0);
2786 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2787 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2788 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
2789 sizeof (old->elem[0]) * old->num_elem);
2794 total_sets = 1 + added_sets_1 + added_sets_2;
2795 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2796 XVECEXP (newpat, 0, 0) = old;
2800 XVECEXP (newpat, 0, --total_sets) = i1pat;
2804 /* If there is no I1, use I2's body as is. We used to also not do
2805 the subst call below if I2 was substituted into I3,
2806 but that could lose a simplification. */
2808 XVECEXP (newpat, 0, --total_sets) = i2pat;
2810 /* See comment where i2pat is assigned. */
2811 XVECEXP (newpat, 0, --total_sets)
2812 = subst (i2pat, i1dest, i1src, 0, 0);
2816 /* We come here when we are replacing a destination in I2 with the
2817 destination of I3. */
2818 validate_replacement:
2820 /* Note which hard regs this insn has as inputs. */
2821 mark_used_regs_combine (newpat);
2823 /* If recog_for_combine fails, it strips existing clobbers. If we'll
2824 consider splitting this pattern, we might need these clobbers. */
2825 if (i1 && GET_CODE (newpat) == PARALLEL
2826 && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
2828 int len = XVECLEN (newpat, 0);
2830 newpat_vec_with_clobbers = rtvec_alloc (len);
2831 for (i = 0; i < len; i++)
2832 RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
2835 /* Is the result of combination a valid instruction? */
2836 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2838 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2839 the second SET's destination is a register that is unused and isn't
2840 marked as an instruction that might trap in an EH region. In that case,
2841 we just need the first SET. This can occur when simplifying a divmod
2842 insn. We *must* test for this case here because the code below that
2843 splits two independent SETs doesn't handle this case correctly when it
2844 updates the register status.
2846 It's pointless doing this if we originally had two sets, one from
2847 i3, and one from i2. Combining then splitting the parallel results
2848 in the original i2 again plus an invalid insn (which we delete).
2849 The net effect is only to move instructions around, which makes
2850 debug info less accurate.
2852 Also check the case where the first SET's destination is unused.
2853 That would not cause incorrect code, but does cause an unneeded
2856 if (insn_code_number < 0
2857 && !(added_sets_2 && i1 == 0)
2858 && GET_CODE (newpat) == PARALLEL
2859 && XVECLEN (newpat, 0) == 2
2860 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2861 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2862 && asm_noperands (newpat) < 0)
2864 rtx set0 = XVECEXP (newpat, 0, 0);
2865 rtx set1 = XVECEXP (newpat, 0, 1);
2868 if (((REG_P (SET_DEST (set1))
2869 && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
2870 || (GET_CODE (SET_DEST (set1)) == SUBREG
2871 && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
2872 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2873 || INTVAL (XEXP (note, 0)) <= 0)
2874 && ! side_effects_p (SET_SRC (set1)))
2877 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2880 else if (((REG_P (SET_DEST (set0))
2881 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
2882 || (GET_CODE (SET_DEST (set0)) == SUBREG
2883 && find_reg_note (i3, REG_UNUSED,
2884 SUBREG_REG (SET_DEST (set0)))))
2885 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2886 || INTVAL (XEXP (note, 0)) <= 0)
2887 && ! side_effects_p (SET_SRC (set0)))
2890 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2892 if (insn_code_number >= 0)
2894 /* If we will be able to accept this, we have made a
2895 change to the destination of I3. This requires us to
2896 do a few adjustments. */
2898 PATTERN (i3) = newpat;
2899 adjust_for_new_dest (i3);
2904 /* If we were combining three insns and the result is a simple SET
2905 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2906 insns. There are two ways to do this. It can be split using a
2907 machine-specific method (like when you have an addition of a large
2908 constant) or by combine in the function find_split_point. */
2910 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2911 && asm_noperands (newpat) < 0)
2913 rtx parallel, m_split, *split;
2915 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2916 use I2DEST as a scratch register will help. In the latter case,
2917 convert I2DEST to the mode of the source of NEWPAT if we can. */
2919 m_split = combine_split_insns (newpat, i3);
2921 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2922 inputs of NEWPAT. */
2924 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2925 possible to try that as a scratch reg. This would require adding
2926 more code to make it work though. */
2928 if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
2930 enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
2932 /* First try to split using the original register as a
2933 scratch register. */
2934 parallel = gen_rtx_PARALLEL (VOIDmode,
2935 gen_rtvec (2, newpat,
2936 gen_rtx_CLOBBER (VOIDmode,
2938 m_split = combine_split_insns (parallel, i3);
2940 /* If that didn't work, try changing the mode of I2DEST if
2943 && new_mode != GET_MODE (i2dest)
2944 && new_mode != VOIDmode
2945 && can_change_dest_mode (i2dest, added_sets_2, new_mode))
2947 enum machine_mode old_mode = GET_MODE (i2dest);
2950 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
2951 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
2954 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
2955 ni2dest = regno_reg_rtx[REGNO (i2dest)];
2958 parallel = (gen_rtx_PARALLEL
2960 gen_rtvec (2, newpat,
2961 gen_rtx_CLOBBER (VOIDmode,
2963 m_split = combine_split_insns (parallel, i3);
2966 && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2970 adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode);
2971 buf = undobuf.undos;
2972 undobuf.undos = buf->next;
2973 buf->next = undobuf.frees;
2974 undobuf.frees = buf;
2979 /* If recog_for_combine has discarded clobbers, try to use them
2980 again for the split. */
2981 if (m_split == 0 && newpat_vec_with_clobbers)
2983 parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers);
2984 m_split = combine_split_insns (parallel, i3);
2987 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
2989 m_split = PATTERN (m_split);
2990 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
2991 if (insn_code_number >= 0)
2994 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
2995 && (next_real_insn (i2) == i3
2996 || ! use_crosses_set_p (PATTERN (m_split), DF_INSN_LUID (i2))))
2999 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
3000 newi2pat = PATTERN (m_split);
3002 i3set = single_set (NEXT_INSN (m_split));
3003 i2set = single_set (m_split);
3005 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3007 /* If I2 or I3 has multiple SETs, we won't know how to track
3008 register status, so don't use these insns. If I2's destination
3009 is used between I2 and I3, we also can't use these insns. */
3011 if (i2_code_number >= 0 && i2set && i3set
3012 && (next_real_insn (i2) == i3
3013 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
3014 insn_code_number = recog_for_combine (&newi3pat, i3,
3016 if (insn_code_number >= 0)
3019 /* It is possible that both insns now set the destination of I3.
3020 If so, we must show an extra use of it. */
3022 if (insn_code_number >= 0)
3024 rtx new_i3_dest = SET_DEST (i3set);
3025 rtx new_i2_dest = SET_DEST (i2set);
3027 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
3028 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
3029 || GET_CODE (new_i3_dest) == SUBREG)
3030 new_i3_dest = XEXP (new_i3_dest, 0);
3032 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
3033 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
3034 || GET_CODE (new_i2_dest) == SUBREG)
3035 new_i2_dest = XEXP (new_i2_dest, 0);
3037 if (REG_P (new_i3_dest)
3038 && REG_P (new_i2_dest)
3039 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
3040 INC_REG_N_SETS (REGNO (new_i2_dest), 1);
3044 /* If we can split it and use I2DEST, go ahead and see if that
3045 helps things be recognized. Verify that none of the registers
3046 are set between I2 and I3. */
3047 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
3051 /* We need I2DEST in the proper mode. If it is a hard register
3052 or the only use of a pseudo, we can change its mode.
3053 Make sure we don't change a hard register to have a mode that
3054 isn't valid for it, or change the number of registers. */
3055 && (GET_MODE (*split) == GET_MODE (i2dest)
3056 || GET_MODE (*split) == VOIDmode
3057 || can_change_dest_mode (i2dest, added_sets_2,
3059 && (next_real_insn (i2) == i3
3060 || ! use_crosses_set_p (*split, DF_INSN_LUID (i2)))
3061 /* We can't overwrite I2DEST if its value is still used by
3063 && ! reg_referenced_p (i2dest, newpat))
3065 rtx newdest = i2dest;
3066 enum rtx_code split_code = GET_CODE (*split);
3067 enum machine_mode split_mode = GET_MODE (*split);
3068 bool subst_done = false;
3069 newi2pat = NULL_RTX;
3071 /* Get NEWDEST as a register in the proper mode. We have already
3072 validated that we can do this. */
3073 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
3075 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3076 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
3079 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
3080 newdest = regno_reg_rtx[REGNO (i2dest)];
3084 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3085 an ASHIFT. This can occur if it was inside a PLUS and hence
3086 appeared to be a memory address. This is a kludge. */
3087 if (split_code == MULT
3088 && GET_CODE (XEXP (*split, 1)) == CONST_INT
3089 && INTVAL (XEXP (*split, 1)) > 0
3090 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
3092 SUBST (*split, gen_rtx_ASHIFT (split_mode,
3093 XEXP (*split, 0), GEN_INT (i)));
3094 /* Update split_code because we may not have a multiply
3096 split_code = GET_CODE (*split);
3099 #ifdef INSN_SCHEDULING
3100 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3101 be written as a ZERO_EXTEND. */
3102 if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
3104 #ifdef LOAD_EXTEND_OP
3105 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3106 what it really is. */
3107 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
3109 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
3110 SUBREG_REG (*split)));
3113 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
3114 SUBREG_REG (*split)));
3118 /* Attempt to split binary operators using arithmetic identities. */
3119 if (BINARY_P (SET_SRC (newpat))
3120 && split_mode == GET_MODE (SET_SRC (newpat))
3121 && ! side_effects_p (SET_SRC (newpat)))
3123 rtx setsrc = SET_SRC (newpat);
3124 enum machine_mode mode = GET_MODE (setsrc);
3125 enum rtx_code code = GET_CODE (setsrc);
3126 rtx src_op0 = XEXP (setsrc, 0);
3127 rtx src_op1 = XEXP (setsrc, 1);
3129 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3130 if (rtx_equal_p (src_op0, src_op1))
3132 newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
3133 SUBST (XEXP (setsrc, 0), newdest);
3134 SUBST (XEXP (setsrc, 1), newdest);
3137 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3138 else if ((code == PLUS || code == MULT)
3139 && GET_CODE (src_op0) == code
3140 && GET_CODE (XEXP (src_op0, 0)) == code
3141 && (INTEGRAL_MODE_P (mode)
3142 || (FLOAT_MODE_P (mode)
3143 && flag_unsafe_math_optimizations)))
3145 rtx p = XEXP (XEXP (src_op0, 0), 0);
3146 rtx q = XEXP (XEXP (src_op0, 0), 1);
3147 rtx r = XEXP (src_op0, 1);
3150 /* Split both "((X op Y) op X) op Y" and
3151 "((X op Y) op Y) op X" as "T op T" where T is
3153 if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
3154 || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
3156 newi2pat = gen_rtx_SET (VOIDmode, newdest,
3158 SUBST (XEXP (setsrc, 0), newdest);
3159 SUBST (XEXP (setsrc, 1), newdest);
3162 /* Split "((X op X) op Y) op Y)" as "T op T" where
3164 else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
3166 rtx tmp = simplify_gen_binary (code, mode, p, r);
3167 newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
3168 SUBST (XEXP (setsrc, 0), newdest);
3169 SUBST (XEXP (setsrc, 1), newdest);
3177 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
3178 SUBST (*split, newdest);
3181 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3183 /* recog_for_combine might have added CLOBBERs to newi2pat.
3184 Make sure NEWPAT does not depend on the clobbered regs. */
3185 if (GET_CODE (newi2pat) == PARALLEL)
3186 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3187 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3189 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3190 if (reg_overlap_mentioned_p (reg, newpat))
3197 /* If the split point was a MULT and we didn't have one before,
3198 don't use one now. */
3199 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
3200 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3204 /* Check for a case where we loaded from memory in a narrow mode and
3205 then sign extended it, but we need both registers. In that case,
3206 we have a PARALLEL with both loads from the same memory location.
3207 We can split this into a load from memory followed by a register-register
3208 copy. This saves at least one insn, more if register allocation can
3211 We cannot do this if the destination of the first assignment is a
3212 condition code register or cc0. We eliminate this case by making sure
3213 the SET_DEST and SET_SRC have the same mode.
3215 We cannot do this if the destination of the second assignment is
3216 a register that we have already assumed is zero-extended. Similarly
3217 for a SUBREG of such a register. */
3219 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3220 && GET_CODE (newpat) == PARALLEL
3221 && XVECLEN (newpat, 0) == 2
3222 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3223 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
3224 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
3225 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
3226 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3227 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3228 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
3229 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3231 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3232 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3233 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
3235 && VEC_index (reg_stat_type, reg_stat,
3236 REGNO (temp))->nonzero_bits != 0
3237 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3238 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3239 && (VEC_index (reg_stat_type, reg_stat,
3240 REGNO (temp))->nonzero_bits
3241 != GET_MODE_MASK (word_mode))))
3242 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
3243 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
3245 && VEC_index (reg_stat_type, reg_stat,
3246 REGNO (temp))->nonzero_bits != 0
3247 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3248 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3249 && (VEC_index (reg_stat_type, reg_stat,
3250 REGNO (temp))->nonzero_bits
3251 != GET_MODE_MASK (word_mode)))))
3252 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3253 SET_SRC (XVECEXP (newpat, 0, 1)))
3254 && ! find_reg_note (i3, REG_UNUSED,
3255 SET_DEST (XVECEXP (newpat, 0, 0))))
3259 newi2pat = XVECEXP (newpat, 0, 0);
3260 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
3261 newpat = XVECEXP (newpat, 0, 1);
3262 SUBST (SET_SRC (newpat),
3263 gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
3264 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3266 if (i2_code_number >= 0)
3267 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3269 if (insn_code_number >= 0)
3273 /* Similarly, check for a case where we have a PARALLEL of two independent
3274 SETs but we started with three insns. In this case, we can do the sets
3275 as two separate insns. This case occurs when some SET allows two
3276 other insns to combine, but the destination of that SET is still live. */
3278 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3279 && GET_CODE (newpat) == PARALLEL
3280 && XVECLEN (newpat, 0) == 2
3281 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3282 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
3283 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
3284 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3285 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3286 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3287 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3289 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3290 XVECEXP (newpat, 0, 0))
3291 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
3292 XVECEXP (newpat, 0, 1))
3293 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
3294 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1))))
3296 /* We cannot split the parallel into two sets if both sets
3298 && ! (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0))
3299 && reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 1)))
3303 /* Normally, it doesn't matter which of the two is done first,
3304 but it does if one references cc0. In that case, it has to
3307 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
3309 newi2pat = XVECEXP (newpat, 0, 0);
3310 newpat = XVECEXP (newpat, 0, 1);
3315 newi2pat = XVECEXP (newpat, 0, 1);
3316 newpat = XVECEXP (newpat, 0, 0);
3319 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3321 if (i2_code_number >= 0)
3322 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3325 /* If it still isn't recognized, fail and change things back the way they
3327 if ((insn_code_number < 0
3328 /* Is the result a reasonable ASM_OPERANDS? */
3329 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
3335 /* If we had to change another insn, make sure it is valid also. */
3336 if (undobuf.other_insn)
3338 CLEAR_HARD_REG_SET (newpat_used_regs);
3340 other_pat = PATTERN (undobuf.other_insn);
3341 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
3344 if (other_code_number < 0 && ! check_asm_operands (other_pat))
3352 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3353 they are adjacent to each other or not. */
3355 rtx p = prev_nonnote_insn (i3);
3356 if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
3357 && sets_cc0_p (newi2pat))
3365 /* Only allow this combination if insn_rtx_costs reports that the
3366 replacement instructions are cheaper than the originals. */
3367 if (!combine_validate_cost (i1, i2, i3, newpat, newi2pat, other_pat))
3373 /* We now know that we can do this combination. Merge the insns and
3374 update the status of registers and LOG_LINKS. */
3376 if (undobuf.other_insn)
3380 PATTERN (undobuf.other_insn) = other_pat;
3382 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
3383 are still valid. Then add any non-duplicate notes added by
3384 recog_for_combine. */
3385 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
3387 next = XEXP (note, 1);
3389 if (REG_NOTE_KIND (note) == REG_UNUSED
3390 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
3391 remove_note (undobuf.other_insn, note);
3394 distribute_notes (new_other_notes, undobuf.other_insn,
3395 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
3404 /* I3 now uses what used to be its destination and which is now
3405 I2's destination. This requires us to do a few adjustments. */
3406 PATTERN (i3) = newpat;
3407 adjust_for_new_dest (i3);
3409 /* We need a LOG_LINK from I3 to I2. But we used to have one,
3412 However, some later insn might be using I2's dest and have
3413 a LOG_LINK pointing at I3. We must remove this link.
3414 The simplest way to remove the link is to point it at I1,
3415 which we know will be a NOTE. */
3417 /* newi2pat is usually a SET here; however, recog_for_combine might
3418 have added some clobbers. */
3419 if (GET_CODE (newi2pat) == PARALLEL)
3420 ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
3422 ni2dest = SET_DEST (newi2pat);
3424 for (insn = NEXT_INSN (i3);
3425 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3426 || insn != BB_HEAD (this_basic_block->next_bb));
3427 insn = NEXT_INSN (insn))
3429 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
3431 for (link = LOG_LINKS (insn); link;
3432 link = XEXP (link, 1))
3433 if (XEXP (link, 0) == i3)
3434 XEXP (link, 0) = i1;
3442 rtx i3notes, i2notes, i1notes = 0;
3443 rtx i3links, i2links, i1links = 0;
3446 /* Compute which registers we expect to eliminate. newi2pat may be setting
3447 either i3dest or i2dest, so we must check it. Also, i1dest may be the
3448 same as i3dest, in which case newi2pat may be setting i1dest. */
3449 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
3450 || i2dest_in_i2src || i2dest_in_i1src
3453 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
3454 || (newi2pat && reg_set_p (i1dest, newi2pat))
3458 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3460 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
3461 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
3463 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
3465 /* Ensure that we do not have something that should not be shared but
3466 occurs multiple times in the new insns. Check this by first
3467 resetting all the `used' flags and then copying anything is shared. */
3469 reset_used_flags (i3notes);
3470 reset_used_flags (i2notes);
3471 reset_used_flags (i1notes);
3472 reset_used_flags (newpat);
3473 reset_used_flags (newi2pat);
3474 if (undobuf.other_insn)
3475 reset_used_flags (PATTERN (undobuf.other_insn));
3477 i3notes = copy_rtx_if_shared (i3notes);
3478 i2notes = copy_rtx_if_shared (i2notes);
3479 i1notes = copy_rtx_if_shared (i1notes);
3480 newpat = copy_rtx_if_shared (newpat);
3481 newi2pat = copy_rtx_if_shared (newi2pat);
3482 if (undobuf.other_insn)
3483 reset_used_flags (PATTERN (undobuf.other_insn));
3485 INSN_CODE (i3) = insn_code_number;
3486 PATTERN (i3) = newpat;
3488 if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
3490 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
3492 reset_used_flags (call_usage);
3493 call_usage = copy_rtx (call_usage);
3496 replace_rtx (call_usage, i2dest, i2src);
3499 replace_rtx (call_usage, i1dest, i1src);
3501 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
3504 if (undobuf.other_insn)
3505 INSN_CODE (undobuf.other_insn) = other_code_number;
3507 /* We had one special case above where I2 had more than one set and
3508 we replaced a destination of one of those sets with the destination
3509 of I3. In that case, we have to update LOG_LINKS of insns later
3510 in this basic block. Note that this (expensive) case is rare.
3512 Also, in this case, we must pretend that all REG_NOTEs for I2
3513 actually came from I3, so that REG_UNUSED notes from I2 will be
3514 properly handled. */
3516 if (i3_subst_into_i2)
3518 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
3519 if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
3520 || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
3521 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
3522 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
3523 && ! find_reg_note (i2, REG_UNUSED,
3524 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
3525 for (temp = NEXT_INSN (i2);
3526 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3527 || BB_HEAD (this_basic_block) != temp);
3528 temp = NEXT_INSN (temp))
3529 if (temp != i3 && INSN_P (temp))
3530 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
3531 if (XEXP (link, 0) == i2)
3532 XEXP (link, 0) = i3;
3537 while (XEXP (link, 1))
3538 link = XEXP (link, 1);
3539 XEXP (link, 1) = i2notes;
3553 INSN_CODE (i2) = i2_code_number;
3554 PATTERN (i2) = newi2pat;
3557 SET_INSN_DELETED (i2);
3563 SET_INSN_DELETED (i1);
3566 /* Get death notes for everything that is now used in either I3 or
3567 I2 and used to die in a previous insn. If we built two new
3568 patterns, move from I1 to I2 then I2 to I3 so that we get the
3569 proper movement on registers that I2 modifies. */
3573 move_deaths (newi2pat, NULL_RTX, DF_INSN_LUID (i1), i2, &midnotes);
3574 move_deaths (newpat, newi2pat, DF_INSN_LUID (i1), i3, &midnotes);
3577 move_deaths (newpat, NULL_RTX, i1 ? DF_INSN_LUID (i1) : DF_INSN_LUID (i2),
3580 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
3582 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
3585 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
3588 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
3591 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3594 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
3595 know these are REG_UNUSED and want them to go to the desired insn,
3596 so we always pass it as i3. */
3598 if (newi2pat && new_i2_notes)
3599 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3602 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
3604 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
3605 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
3606 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
3607 in that case, it might delete I2. Similarly for I2 and I1.
3608 Show an additional death due to the REG_DEAD note we make here. If
3609 we discard it in distribute_notes, we will decrement it again. */
3613 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
3614 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
3616 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
3618 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
3620 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3624 if (i2dest_in_i2src)
3626 if (newi2pat && reg_set_p (i2dest, newi2pat))
3627 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
3628 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3630 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
3631 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3632 NULL_RTX, NULL_RTX);
3635 if (i1dest_in_i1src)
3637 if (newi2pat && reg_set_p (i1dest, newi2pat))
3638 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
3639 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3641 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
3642 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3643 NULL_RTX, NULL_RTX);
3646 distribute_links (i3links);
3647 distribute_links (i2links);
3648 distribute_links (i1links);
3653 rtx i2_insn = 0, i2_val = 0, set;
3655 /* The insn that used to set this register doesn't exist, and
3656 this life of the register may not exist either. See if one of
3657 I3's links points to an insn that sets I2DEST. If it does,
3658 that is now the last known value for I2DEST. If we don't update
3659 this and I2 set the register to a value that depended on its old
3660 contents, we will get confused. If this insn is used, thing
3661 will be set correctly in combine_instructions. */
3663 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3664 if ((set = single_set (XEXP (link, 0))) != 0
3665 && rtx_equal_p (i2dest, SET_DEST (set)))
3666 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
3668 record_value_for_reg (i2dest, i2_insn, i2_val);
3670 /* If the reg formerly set in I2 died only once and that was in I3,
3671 zero its use count so it won't make `reload' do any work. */
3673 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
3674 && ! i2dest_in_i2src)
3676 regno = REGNO (i2dest);
3677 INC_REG_N_SETS (regno, -1);
3681 if (i1 && REG_P (i1dest))
3684 rtx i1_insn = 0, i1_val = 0, set;
3686 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3687 if ((set = single_set (XEXP (link, 0))) != 0
3688 && rtx_equal_p (i1dest, SET_DEST (set)))
3689 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
3691 record_value_for_reg (i1dest, i1_insn, i1_val);
3693 regno = REGNO (i1dest);
3694 if (! added_sets_1 && ! i1dest_in_i1src)
3695 INC_REG_N_SETS (regno, -1);
3698 /* Update reg_stat[].nonzero_bits et al for any changes that may have
3699 been made to this insn. The order of
3700 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
3701 can affect nonzero_bits of newpat */
3703 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
3704 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
3706 /* Set new_direct_jump_p if a new return or simple jump instruction
3709 If I3 is now an unconditional jump, ensure that it has a
3710 BARRIER following it since it may have initially been a
3711 conditional jump. It may also be the last nonnote insn. */
3713 if (returnjump_p (i3) || any_uncondjump_p (i3))
3715 *new_direct_jump_p = 1;
3716 mark_jump_label (PATTERN (i3), i3, 0);
3718 if ((temp = next_nonnote_insn (i3)) == NULL_RTX
3719 || !BARRIER_P (temp))
3720 emit_barrier_after (i3);
3723 if (undobuf.other_insn != NULL_RTX
3724 && (returnjump_p (undobuf.other_insn)
3725 || any_uncondjump_p (undobuf.other_insn)))
3727 *new_direct_jump_p = 1;
3729 if ((temp = next_nonnote_insn (undobuf.other_insn)) == NULL_RTX
3730 || !BARRIER_P (temp))
3731 emit_barrier_after (undobuf.other_insn);
3734 /* An NOOP jump does not need barrier, but it does need cleaning up
3736 if (GET_CODE (newpat) == SET
3737 && SET_SRC (newpat) == pc_rtx
3738 && SET_DEST (newpat) == pc_rtx)
3739 *new_direct_jump_p = 1;
3742 if (undobuf.other_insn != NULL_RTX)
3746 fprintf (dump_file, "modifying other_insn ");
3747 dump_insn_slim (dump_file, undobuf.other_insn);
3749 df_insn_rescan (undobuf.other_insn);
3752 if (i1 && !(NOTE_P(i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED)))
3756 fprintf (dump_file, "modifying insn i1 ");
3757 dump_insn_slim (dump_file, i1);
3759 df_insn_rescan (i1);
3762 if (i2 && !(NOTE_P(i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED)))
3766 fprintf (dump_file, "modifying insn i2 ");
3767 dump_insn_slim (dump_file, i2);
3769 df_insn_rescan (i2);
3772 if (i3 && !(NOTE_P(i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED)))
3776 fprintf (dump_file, "modifying insn i3 ");
3777 dump_insn_slim (dump_file, i3);
3779 df_insn_rescan (i3);
3782 combine_successes++;
3785 if (added_links_insn
3786 && (newi2pat == 0 || DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i2))
3787 && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i3))
3788 return added_links_insn;
3790 return newi2pat ? i2 : i3;
3793 /* Undo all the modifications recorded in undobuf. */
3798 struct undo *undo, *next;
3800 for (undo = undobuf.undos; undo; undo = next)
3806 *undo->where.r = undo->old_contents.r;
3809 *undo->where.i = undo->old_contents.i;
3812 adjust_reg_mode (*undo->where.r, undo->old_contents.m);
3818 undo->next = undobuf.frees;
3819 undobuf.frees = undo;
3825 /* We've committed to accepting the changes we made. Move all
3826 of the undos to the free list. */
3831 struct undo *undo, *next;
3833 for (undo = undobuf.undos; undo; undo = next)
3836 undo->next = undobuf.frees;
3837 undobuf.frees = undo;
3842 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
3843 where we have an arithmetic expression and return that point. LOC will
3846 try_combine will call this function to see if an insn can be split into
3850 find_split_point (rtx *loc, rtx insn)
3853 enum rtx_code code = GET_CODE (x);
3855 unsigned HOST_WIDE_INT len = 0;
3856 HOST_WIDE_INT pos = 0;
3858 rtx inner = NULL_RTX;
3860 /* First special-case some codes. */
3864 #ifdef INSN_SCHEDULING
3865 /* If we are making a paradoxical SUBREG invalid, it becomes a split
3867 if (MEM_P (SUBREG_REG (x)))
3870 return find_split_point (&SUBREG_REG (x), insn);
3874 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
3875 using LO_SUM and HIGH. */
3876 if (GET_CODE (XEXP (x, 0)) == CONST
3877 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
3880 gen_rtx_LO_SUM (Pmode,
3881 gen_rtx_HIGH (Pmode, XEXP (x, 0)),
3883 return &XEXP (XEXP (x, 0), 0);
3887 /* If we have a PLUS whose second operand is a constant and the
3888 address is not valid, perhaps will can split it up using
3889 the machine-specific way to split large constants. We use
3890 the first pseudo-reg (one of the virtual regs) as a placeholder;
3891 it will not remain in the result. */
3892 if (GET_CODE (XEXP (x, 0)) == PLUS
3893 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3894 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
3896 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
3897 rtx seq = combine_split_insns (gen_rtx_SET (VOIDmode, reg,
3901 /* This should have produced two insns, each of which sets our
3902 placeholder. If the source of the second is a valid address,
3903 we can make put both sources together and make a split point
3907 && NEXT_INSN (seq) != NULL_RTX
3908 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
3909 && NONJUMP_INSN_P (seq)
3910 && GET_CODE (PATTERN (seq)) == SET
3911 && SET_DEST (PATTERN (seq)) == reg
3912 && ! reg_mentioned_p (reg,
3913 SET_SRC (PATTERN (seq)))
3914 && NONJUMP_INSN_P (NEXT_INSN (seq))
3915 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
3916 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
3917 && memory_address_p (GET_MODE (x),
3918 SET_SRC (PATTERN (NEXT_INSN (seq)))))
3920 rtx src1 = SET_SRC (PATTERN (seq));
3921 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
3923 /* Replace the placeholder in SRC2 with SRC1. If we can
3924 find where in SRC2 it was placed, that can become our
3925 split point and we can replace this address with SRC2.
3926 Just try two obvious places. */
3928 src2 = replace_rtx (src2, reg, src1);
3930 if (XEXP (src2, 0) == src1)
3931 split = &XEXP (src2, 0);
3932 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
3933 && XEXP (XEXP (src2, 0), 0) == src1)
3934 split = &XEXP (XEXP (src2, 0), 0);
3938 SUBST (XEXP (x, 0), src2);
3943 /* If that didn't work, perhaps the first operand is complex and
3944 needs to be computed separately, so make a split point there.
3945 This will occur on machines that just support REG + CONST
3946 and have a constant moved through some previous computation. */
3948 else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
3949 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
3950 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
3951 return &XEXP (XEXP (x, 0), 0);
3954 /* If we have a PLUS whose first operand is complex, try computing it
3955 separately by making a split there. */
3956 if (GET_CODE (XEXP (x, 0)) == PLUS
3957 && ! memory_address_p (GET_MODE (x), XEXP (x, 0))
3958 && ! OBJECT_P (XEXP (XEXP (x, 0), 0))
3959 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
3960 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
3961 return &XEXP (XEXP (x, 0), 0);
3966 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3967 ZERO_EXTRACT, the most likely reason why this doesn't match is that
3968 we need to put the operand into a register. So split at that
3971 if (SET_DEST (x) == cc0_rtx
3972 && GET_CODE (SET_SRC (x)) != COMPARE
3973 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
3974 && !OBJECT_P (SET_SRC (x))
3975 && ! (GET_CODE (SET_SRC (x)) == SUBREG
3976 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
3977 return &SET_SRC (x);
3980 /* See if we can split SET_SRC as it stands. */
3981 split = find_split_point (&SET_SRC (x), insn);
3982 if (split && split != &SET_SRC (x))
3985 /* See if we can split SET_DEST as it stands. */
3986 split = find_split_point (&SET_DEST (x), insn);
3987 if (split && split != &SET_DEST (x))
3990 /* See if this is a bitfield assignment with everything constant. If
3991 so, this is an IOR of an AND, so split it into that. */
3992 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
3993 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
3994 <= HOST_BITS_PER_WIDE_INT)
3995 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
3996 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
3997 && GET_CODE (SET_SRC (x)) == CONST_INT
3998 && ((INTVAL (XEXP (SET_DEST (x), 1))
3999 + INTVAL (XEXP (SET_DEST (x), 2)))
4000 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
4001 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
4003 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
4004 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
4005 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
4006 rtx dest = XEXP (SET_DEST (x), 0);
4007 enum machine_mode mode = GET_MODE (dest);
4008 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
4011 if (BITS_BIG_ENDIAN)
4012 pos = GET_MODE_BITSIZE (mode) - len - pos;
4014 or_mask = gen_int_mode (src << pos, mode);
4017 simplify_gen_binary (IOR, mode, dest, or_mask));
4020 rtx negmask = gen_int_mode (~(mask << pos), mode);
4022 simplify_gen_binary (IOR, mode,
4023 simplify_gen_binary (AND, mode,
4028 SUBST (SET_DEST (x), dest);
4030 split = find_split_point (&SET_SRC (x), insn);
4031 if (split && split != &SET_SRC (x))
4035 /* Otherwise, see if this is an operation that we can split into two.
4036 If so, try to split that. */
4037 code = GET_CODE (SET_SRC (x));
4042 /* If we are AND'ing with a large constant that is only a single
4043 bit and the result is only being used in a context where we
4044 need to know if it is zero or nonzero, replace it with a bit
4045 extraction. This will avoid the large constant, which might
4046 have taken more than one insn to make. If the constant were
4047 not a valid argument to the AND but took only one insn to make,
4048 this is no worse, but if it took more than one insn, it will
4051 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
4052 && REG_P (XEXP (SET_SRC (x), 0))
4053 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
4054 && REG_P (SET_DEST (x))
4055 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
4056 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
4057 && XEXP (*split, 0) == SET_DEST (x)
4058 && XEXP (*split, 1) == const0_rtx)
4060 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
4061 XEXP (SET_SRC (x), 0),
4062 pos, NULL_RTX, 1, 1, 0, 0);
4063 if (extraction != 0)
4065 SUBST (SET_SRC (x), extraction);
4066 return find_split_point (loc, insn);
4072 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4073 is known to be on, this can be converted into a NEG of a shift. */
4074 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
4075 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
4076 && 1 <= (pos = exact_log2
4077 (nonzero_bits (XEXP (SET_SRC (x), 0),
4078 GET_MODE (XEXP (SET_SRC (x), 0))))))
4080 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
4084 gen_rtx_LSHIFTRT (mode,
4085 XEXP (SET_SRC (x), 0),
4088 split = find_split_point (&SET_SRC (x), insn);
4089 if (split && split != &SET_SRC (x))
4095 inner = XEXP (SET_SRC (x), 0);
4097 /* We can't optimize if either mode is a partial integer
4098 mode as we don't know how many bits are significant
4100 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
4101 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
4105 len = GET_MODE_BITSIZE (GET_MODE (inner));
4111 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
4112 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
4114 inner = XEXP (SET_SRC (x), 0);
4115 len = INTVAL (XEXP (SET_SRC (x), 1));
4116 pos = INTVAL (XEXP (SET_SRC (x), 2));
4118 if (BITS_BIG_ENDIAN)
4119 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
4120 unsignedp = (code == ZERO_EXTRACT);
4128 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
4130 enum machine_mode mode = GET_MODE (SET_SRC (x));
4132 /* For unsigned, we have a choice of a shift followed by an
4133 AND or two shifts. Use two shifts for field sizes where the
4134 constant might be too large. We assume here that we can
4135 always at least get 8-bit constants in an AND insn, which is
4136 true for every current RISC. */
4138 if (unsignedp && len <= 8)
4143 (mode, gen_lowpart (mode, inner),
4145 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
4147 split = find_split_point (&SET_SRC (x), insn);
4148 if (split && split != &SET_SRC (x))
4155 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
4156 gen_rtx_ASHIFT (mode,
4157 gen_lowpart (mode, inner),
4158 GEN_INT (GET_MODE_BITSIZE (mode)
4160 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
4162 split = find_split_point (&SET_SRC (x), insn);
4163 if (split && split != &SET_SRC (x))
4168 /* See if this is a simple operation with a constant as the second
4169 operand. It might be that this constant is out of range and hence
4170 could be used as a split point. */
4171 if (BINARY_P (SET_SRC (x))
4172 && CONSTANT_P (XEXP (SET_SRC (x), 1))
4173 && (OBJECT_P (XEXP (SET_SRC (x), 0))
4174 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
4175 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
4176 return &XEXP (SET_SRC (x), 1);
4178 /* Finally, see if this is a simple operation with its first operand
4179 not in a register. The operation might require this operand in a
4180 register, so return it as a split point. We can always do this
4181 because if the first operand were another operation, we would have
4182 already found it as a split point. */
4183 if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
4184 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
4185 return &XEXP (SET_SRC (x), 0);
4191 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4192 it is better to write this as (not (ior A B)) so we can split it.
4193 Similarly for IOR. */
4194 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
4197 gen_rtx_NOT (GET_MODE (x),
4198 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
4200 XEXP (XEXP (x, 0), 0),
4201 XEXP (XEXP (x, 1), 0))));
4202 return find_split_point (loc, insn);
4205 /* Many RISC machines have a large set of logical insns. If the
4206 second operand is a NOT, put it first so we will try to split the
4207 other operand first. */
4208 if (GET_CODE (XEXP (x, 1)) == NOT)
4210 rtx tem = XEXP (x, 0);
4211 SUBST (XEXP (x, 0), XEXP (x, 1));
4212 SUBST (XEXP (x, 1), tem);
4220 /* Otherwise, select our actions depending on our rtx class. */
4221 switch (GET_RTX_CLASS (code))
4223 case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
4225 split = find_split_point (&XEXP (x, 2), insn);
4228 /* ... fall through ... */
4230 case RTX_COMM_ARITH:
4232 case RTX_COMM_COMPARE:
4233 split = find_split_point (&XEXP (x, 1), insn);
4236 /* ... fall through ... */
4238 /* Some machines have (and (shift ...) ...) insns. If X is not
4239 an AND, but XEXP (X, 0) is, use it as our split point. */
4240 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
4241 return &XEXP (x, 0);
4243 split = find_split_point (&XEXP (x, 0), insn);
4249 /* Otherwise, we don't have a split point. */
4254 /* Throughout X, replace FROM with TO, and return the result.
4255 The result is TO if X is FROM;
4256 otherwise the result is X, but its contents may have been modified.
4257 If they were modified, a record was made in undobuf so that
4258 undo_all will (among other things) return X to its original state.
4260 If the number of changes necessary is too much to record to undo,
4261 the excess changes are not made, so the result is invalid.
4262 The changes already made can still be undone.
4263 undobuf.num_undo is incremented for such changes, so by testing that
4264 the caller can tell whether the result is valid.
4266 `n_occurrences' is incremented each time FROM is replaced.
4268 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4270 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
4271 by copying if `n_occurrences' is nonzero. */
4274 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
4276 enum rtx_code code = GET_CODE (x);
4277 enum machine_mode op0_mode = VOIDmode;
4282 /* Two expressions are equal if they are identical copies of a shared
4283 RTX or if they are both registers with the same register number
4286 #define COMBINE_RTX_EQUAL_P(X,Y) \
4288 || (REG_P (X) && REG_P (Y) \
4289 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4291 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
4294 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
4297 /* If X and FROM are the same register but different modes, they
4298 will not have been seen as equal above. However, the log links code
4299 will make a LOG_LINKS entry for that case. If we do nothing, we
4300 will try to rerecognize our original insn and, when it succeeds,
4301 we will delete the feeding insn, which is incorrect.
4303 So force this insn not to match in this (rare) case. */
4304 if (! in_dest && code == REG && REG_P (from)
4305 && reg_overlap_mentioned_p (x, from))
4306 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
4308 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4309 of which may contain things that can be combined. */
4310 if (code != MEM && code != LO_SUM && OBJECT_P (x))
4313 /* It is possible to have a subexpression appear twice in the insn.
4314 Suppose that FROM is a register that appears within TO.
4315 Then, after that subexpression has been scanned once by `subst',
4316 the second time it is scanned, TO may be found. If we were
4317 to scan TO here, we would find FROM within it and create a
4318 self-referent rtl structure which is completely wrong. */
4319 if (COMBINE_RTX_EQUAL_P (x, to))
4322 /* Parallel asm_operands need special attention because all of the
4323 inputs are shared across the arms. Furthermore, unsharing the
4324 rtl results in recognition failures. Failure to handle this case
4325 specially can result in circular rtl.
4327 Solve this by doing a normal pass across the first entry of the
4328 parallel, and only processing the SET_DESTs of the subsequent
4331 if (code == PARALLEL
4332 && GET_CODE (XVECEXP (x, 0, 0)) == SET
4333 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
4335 new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
4337 /* If this substitution failed, this whole thing fails. */
4338 if (GET_CODE (new_rtx) == CLOBBER
4339 && XEXP (new_rtx, 0) == const0_rtx)
4342 SUBST (XVECEXP (x, 0, 0), new_rtx);
4344 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
4346 rtx dest = SET_DEST (XVECEXP (x, 0, i));
4349 && GET_CODE (dest) != CC0
4350 && GET_CODE (dest) != PC)
4352 new_rtx = subst (dest, from, to, 0, unique_copy);
4354 /* If this substitution failed, this whole thing fails. */
4355 if (GET_CODE (new_rtx) == CLOBBER
4356 && XEXP (new_rtx, 0) == const0_rtx)
4359 SUBST (SET_DEST (XVECEXP (x, 0, i)), new_rtx);
4365 len = GET_RTX_LENGTH (code);
4366 fmt = GET_RTX_FORMAT (code);
4368 /* We don't need to process a SET_DEST that is a register, CC0,
4369 or PC, so set up to skip this common case. All other cases
4370 where we want to suppress replacing something inside a
4371 SET_SRC are handled via the IN_DEST operand. */
4373 && (REG_P (SET_DEST (x))
4374 || GET_CODE (SET_DEST (x)) == CC0
4375 || GET_CODE (SET_DEST (x)) == PC))
4378 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
4381 op0_mode = GET_MODE (XEXP (x, 0));
4383 for (i = 0; i < len; i++)
4388 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4390 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
4392 new_rtx = (unique_copy && n_occurrences
4393 ? copy_rtx (to) : to);
4398 new_rtx = subst (XVECEXP (x, i, j), from, to, 0,
4401 /* If this substitution failed, this whole thing
4403 if (GET_CODE (new_rtx) == CLOBBER
4404 && XEXP (new_rtx, 0) == const0_rtx)
4408 SUBST (XVECEXP (x, i, j), new_rtx);
4411 else if (fmt[i] == 'e')
4413 /* If this is a register being set, ignore it. */
4414 new_rtx = XEXP (x, i);
4417 && (((code == SUBREG || code == ZERO_EXTRACT)
4419 || code == STRICT_LOW_PART))
4422 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
4424 /* In general, don't install a subreg involving two
4425 modes not tieable. It can worsen register
4426 allocation, and can even make invalid reload
4427 insns, since the reg inside may need to be copied
4428 from in the outside mode, and that may be invalid
4429 if it is an fp reg copied in integer mode.
4431 We allow two exceptions to this: It is valid if
4432 it is inside another SUBREG and the mode of that
4433 SUBREG and the mode of the inside of TO is
4434 tieable and it is valid if X is a SET that copies
4437 if (GET_CODE (to) == SUBREG
4438 && ! MODES_TIEABLE_P (GET_MODE (to),
4439 GET_MODE (SUBREG_REG (to)))
4440 && ! (code == SUBREG
4441 && MODES_TIEABLE_P (GET_MODE (x),
4442 GET_MODE (SUBREG_REG (to))))
4444 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
4447 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4449 #ifdef CANNOT_CHANGE_MODE_CLASS
4452 && REGNO (to) < FIRST_PSEUDO_REGISTER
4453 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
4456 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4459 new_rtx = (unique_copy && n_occurrences ? copy_rtx (to) : to);
4463 /* If we are in a SET_DEST, suppress most cases unless we
4464 have gone inside a MEM, in which case we want to
4465 simplify the address. We assume here that things that
4466 are actually part of the destination have their inner
4467 parts in the first expression. This is true for SUBREG,
4468 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
4469 things aside from REG and MEM that should appear in a
4471 new_rtx = subst (XEXP (x, i), from, to,
4473 && (code == SUBREG || code == STRICT_LOW_PART
4474 || code == ZERO_EXTRACT))
4476 && i == 0), unique_copy);
4478 /* If we found that we will have to reject this combination,
4479 indicate that by returning the CLOBBER ourselves, rather than
4480 an expression containing it. This will speed things up as
4481 well as prevent accidents where two CLOBBERs are considered
4482 to be equal, thus producing an incorrect simplification. */
4484 if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx)
4487 if (GET_CODE (x) == SUBREG
4488 && (GET_CODE (new_rtx) == CONST_INT
4489 || GET_CODE (new_rtx) == CONST_DOUBLE))
4491 enum machine_mode mode = GET_MODE (x);
4493 x = simplify_subreg (GET_MODE (x), new_rtx,
4494 GET_MODE (SUBREG_REG (x)),
4497 x = gen_rtx_CLOBBER (mode, const0_rtx);
4499 else if (GET_CODE (new_rtx) == CONST_INT
4500 && GET_CODE (x) == ZERO_EXTEND)
4502 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
4503 new_rtx, GET_MODE (XEXP (x, 0)));
4507 SUBST (XEXP (x, i), new_rtx);
4512 /* Check if we are loading something from the constant pool via float
4513 extension; in this case we would undo compress_float_constant
4514 optimization and degenerate constant load to an immediate value. */
4515 if (GET_CODE (x) == FLOAT_EXTEND
4516 && MEM_P (XEXP (x, 0))
4517 && MEM_READONLY_P (XEXP (x, 0)))
4519 rtx tmp = avoid_constant_pool_reference (x);
4524 /* Try to simplify X. If the simplification changed the code, it is likely
4525 that further simplification will help, so loop, but limit the number
4526 of repetitions that will be performed. */
4528 for (i = 0; i < 4; i++)
4530 /* If X is sufficiently simple, don't bother trying to do anything
4532 if (code != CONST_INT && code != REG && code != CLOBBER)
4533 x = combine_simplify_rtx (x, op0_mode, in_dest);
4535 if (GET_CODE (x) == code)
4538 code = GET_CODE (x);
4540 /* We no longer know the original mode of operand 0 since we
4541 have changed the form of X) */
4542 op0_mode = VOIDmode;
4548 /* Simplify X, a piece of RTL. We just operate on the expression at the
4549 outer level; call `subst' to simplify recursively. Return the new
4552 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
4553 if we are inside a SET_DEST. */
4556 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
4558 enum rtx_code code = GET_CODE (x);
4559 enum machine_mode mode = GET_MODE (x);
4563 /* If this is a commutative operation, put a constant last and a complex
4564 expression first. We don't need to do this for comparisons here. */
4565 if (COMMUTATIVE_ARITH_P (x)
4566 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
4569 SUBST (XEXP (x, 0), XEXP (x, 1));
4570 SUBST (XEXP (x, 1), temp);
4573 /* If this is a simple operation applied to an IF_THEN_ELSE, try
4574 applying it to the arms of the IF_THEN_ELSE. This often simplifies
4575 things. Check for cases where both arms are testing the same
4578 Don't do anything if all operands are very simple. */
4581 && ((!OBJECT_P (XEXP (x, 0))
4582 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4583 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
4584 || (!OBJECT_P (XEXP (x, 1))
4585 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
4586 && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
4588 && (!OBJECT_P (XEXP (x, 0))
4589 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4590 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
4592 rtx cond, true_rtx, false_rtx;
4594 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
4596 /* If everything is a comparison, what we have is highly unlikely
4597 to be simpler, so don't use it. */
4598 && ! (COMPARISON_P (x)
4599 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
4601 rtx cop1 = const0_rtx;
4602 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
4604 if (cond_code == NE && COMPARISON_P (cond))
4607 /* Simplify the alternative arms; this may collapse the true and
4608 false arms to store-flag values. Be careful to use copy_rtx
4609 here since true_rtx or false_rtx might share RTL with x as a
4610 result of the if_then_else_cond call above. */
4611 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
4612 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
4614 /* If true_rtx and false_rtx are not general_operands, an if_then_else
4615 is unlikely to be simpler. */
4616 if (general_operand (true_rtx, VOIDmode)
4617 && general_operand (false_rtx, VOIDmode))
4619 enum rtx_code reversed;
4621 /* Restarting if we generate a store-flag expression will cause
4622 us to loop. Just drop through in this case. */
4624 /* If the result values are STORE_FLAG_VALUE and zero, we can
4625 just make the comparison operation. */
4626 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
4627 x = simplify_gen_relational (cond_code, mode, VOIDmode,
4629 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
4630 && ((reversed = reversed_comparison_code_parts
4631 (cond_code, cond, cop1, NULL))
4633 x = simplify_gen_relational (reversed, mode, VOIDmode,
4636 /* Likewise, we can make the negate of a comparison operation
4637 if the result values are - STORE_FLAG_VALUE and zero. */
4638 else if (GET_CODE (true_rtx) == CONST_INT
4639 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
4640 && false_rtx == const0_rtx)
4641 x = simplify_gen_unary (NEG, mode,
4642 simplify_gen_relational (cond_code,
4646 else if (GET_CODE (false_rtx) == CONST_INT
4647 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
4648 && true_rtx == const0_rtx
4649 && ((reversed = reversed_comparison_code_parts
4650 (cond_code, cond, cop1, NULL))
4652 x = simplify_gen_unary (NEG, mode,
4653 simplify_gen_relational (reversed,
4658 return gen_rtx_IF_THEN_ELSE (mode,
4659 simplify_gen_relational (cond_code,
4664 true_rtx, false_rtx);
4666 code = GET_CODE (x);
4667 op0_mode = VOIDmode;
4672 /* Try to fold this expression in case we have constants that weren't
4675 switch (GET_RTX_CLASS (code))
4678 if (op0_mode == VOIDmode)
4679 op0_mode = GET_MODE (XEXP (x, 0));
4680 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
4683 case RTX_COMM_COMPARE:
4685 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
4686 if (cmp_mode == VOIDmode)
4688 cmp_mode = GET_MODE (XEXP (x, 1));
4689 if (cmp_mode == VOIDmode)
4690 cmp_mode = op0_mode;
4692 temp = simplify_relational_operation (code, mode, cmp_mode,
4693 XEXP (x, 0), XEXP (x, 1));
4696 case RTX_COMM_ARITH:
4698 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
4700 case RTX_BITFIELD_OPS:
4702 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
4703 XEXP (x, 1), XEXP (x, 2));
4712 code = GET_CODE (temp);
4713 op0_mode = VOIDmode;
4714 mode = GET_MODE (temp);
4717 /* First see if we can apply the inverse distributive law. */
4718 if (code == PLUS || code == MINUS
4719 || code == AND || code == IOR || code == XOR)
4721 x = apply_distributive_law (x);
4722 code = GET_CODE (x);
4723 op0_mode = VOIDmode;
4726 /* If CODE is an associative operation not otherwise handled, see if we
4727 can associate some operands. This can win if they are constants or
4728 if they are logically related (i.e. (a & b) & a). */
4729 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
4730 || code == AND || code == IOR || code == XOR
4731 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
4732 && ((INTEGRAL_MODE_P (mode) && code != DIV)
4733 || (flag_associative_math && FLOAT_MODE_P (mode))))
4735 if (GET_CODE (XEXP (x, 0)) == code)
4737 rtx other = XEXP (XEXP (x, 0), 0);
4738 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
4739 rtx inner_op1 = XEXP (x, 1);
4742 /* Make sure we pass the constant operand if any as the second
4743 one if this is a commutative operation. */
4744 if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
4746 rtx tem = inner_op0;
4747 inner_op0 = inner_op1;
4750 inner = simplify_binary_operation (code == MINUS ? PLUS
4751 : code == DIV ? MULT
4753 mode, inner_op0, inner_op1);
4755 /* For commutative operations, try the other pair if that one
4757 if (inner == 0 && COMMUTATIVE_ARITH_P (x))
4759 other = XEXP (XEXP (x, 0), 1);
4760 inner = simplify_binary_operation (code, mode,
4761 XEXP (XEXP (x, 0), 0),
4766 return simplify_gen_binary (code, mode, other, inner);
4770 /* A little bit of algebraic simplification here. */
4774 /* Ensure that our address has any ASHIFTs converted to MULT in case
4775 address-recognizing predicates are called later. */
4776 temp = make_compound_operation (XEXP (x, 0), MEM);
4777 SUBST (XEXP (x, 0), temp);
4781 if (op0_mode == VOIDmode)
4782 op0_mode = GET_MODE (SUBREG_REG (x));
4784 /* See if this can be moved to simplify_subreg. */
4785 if (CONSTANT_P (SUBREG_REG (x))
4786 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
4787 /* Don't call gen_lowpart if the inner mode
4788 is VOIDmode and we cannot simplify it, as SUBREG without
4789 inner mode is invalid. */
4790 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
4791 || gen_lowpart_common (mode, SUBREG_REG (x))))
4792 return gen_lowpart (mode, SUBREG_REG (x));
4794 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
4798 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
4804 /* Don't change the mode of the MEM if that would change the meaning
4806 if (MEM_P (SUBREG_REG (x))
4807 && (MEM_VOLATILE_P (SUBREG_REG (x))
4808 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
4809 return gen_rtx_CLOBBER (mode, const0_rtx);
4811 /* Note that we cannot do any narrowing for non-constants since
4812 we might have been counting on using the fact that some bits were
4813 zero. We now do this in the SET. */
4818 temp = expand_compound_operation (XEXP (x, 0));
4820 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4821 replaced by (lshiftrt X C). This will convert
4822 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4824 if (GET_CODE (temp) == ASHIFTRT
4825 && GET_CODE (XEXP (temp, 1)) == CONST_INT
4826 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4827 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
4828 INTVAL (XEXP (temp, 1)));
4830 /* If X has only a single bit that might be nonzero, say, bit I, convert
4831 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4832 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4833 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4834 or a SUBREG of one since we'd be making the expression more
4835 complex if it was just a register. */
4838 && ! (GET_CODE (temp) == SUBREG
4839 && REG_P (SUBREG_REG (temp)))
4840 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4842 rtx temp1 = simplify_shift_const
4843 (NULL_RTX, ASHIFTRT, mode,
4844 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4845 GET_MODE_BITSIZE (mode) - 1 - i),
4846 GET_MODE_BITSIZE (mode) - 1 - i);
4848 /* If all we did was surround TEMP with the two shifts, we
4849 haven't improved anything, so don't use it. Otherwise,
4850 we are better off with TEMP1. */
4851 if (GET_CODE (temp1) != ASHIFTRT
4852 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4853 || XEXP (XEXP (temp1, 0), 0) != temp)
4859 /* We can't handle truncation to a partial integer mode here
4860 because we don't know the real bitsize of the partial
4862 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4865 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4866 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4867 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4869 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4870 GET_MODE_MASK (mode), 0));
4872 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
4873 whose value is a comparison can be replaced with a subreg if
4874 STORE_FLAG_VALUE permits. */
4875 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4876 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4877 && (temp = get_last_value (XEXP (x, 0)))
4878 && COMPARISON_P (temp))
4879 return gen_lowpart (mode, XEXP (x, 0));
4884 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4885 using cc0, in which case we want to leave it as a COMPARE
4886 so we can distinguish it from a register-register-copy. */
4887 if (XEXP (x, 1) == const0_rtx)
4890 /* x - 0 is the same as x unless x's mode has signed zeros and
4891 allows rounding towards -infinity. Under those conditions,
4893 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0)))
4894 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0))))
4895 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4901 /* (const (const X)) can become (const X). Do it this way rather than
4902 returning the inner CONST since CONST can be shared with a
4904 if (GET_CODE (XEXP (x, 0)) == CONST)
4905 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4910 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4911 can add in an offset. find_split_point will split this address up
4912 again if it doesn't match. */
4913 if (GET_CODE (XEXP (x, 0)) == HIGH
4914 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4920 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4921 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4922 bit-field and can be replaced by either a sign_extend or a
4923 sign_extract. The `and' may be a zero_extend and the two
4924 <c>, -<c> constants may be reversed. */
4925 if (GET_CODE (XEXP (x, 0)) == XOR
4926 && GET_CODE (XEXP (x, 1)) == CONST_INT
4927 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4928 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4929 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4930 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4931 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4932 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4933 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4934 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4935 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4936 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4937 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4938 == (unsigned int) i + 1))))
4939 return simplify_shift_const
4940 (NULL_RTX, ASHIFTRT, mode,
4941 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4942 XEXP (XEXP (XEXP (x, 0), 0), 0),
4943 GET_MODE_BITSIZE (mode) - (i + 1)),
4944 GET_MODE_BITSIZE (mode) - (i + 1));
4946 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4947 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4948 the bitsize of the mode - 1. This allows simplification of
4949 "a = (b & 8) == 0;" */
4950 if (XEXP (x, 1) == constm1_rtx
4951 && !REG_P (XEXP (x, 0))
4952 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4953 && REG_P (SUBREG_REG (XEXP (x, 0))))
4954 && nonzero_bits (XEXP (x, 0), mode) == 1)
4955 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4956 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4957 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4958 GET_MODE_BITSIZE (mode) - 1),
4959 GET_MODE_BITSIZE (mode) - 1);
4961 /* If we are adding two things that have no bits in common, convert
4962 the addition into an IOR. This will often be further simplified,
4963 for example in cases like ((a & 1) + (a & 2)), which can
4966 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4967 && (nonzero_bits (XEXP (x, 0), mode)
4968 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4970 /* Try to simplify the expression further. */
4971 rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4972 temp = combine_simplify_rtx (tor, mode, in_dest);
4974 /* If we could, great. If not, do not go ahead with the IOR
4975 replacement, since PLUS appears in many special purpose
4976 address arithmetic instructions. */
4977 if (GET_CODE (temp) != CLOBBER && temp != tor)
4983 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4984 (and <foo> (const_int pow2-1)) */
4985 if (GET_CODE (XEXP (x, 1)) == AND
4986 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4987 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4988 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4989 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4990 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4994 /* If we have (mult (plus A B) C), apply the distributive law and then
4995 the inverse distributive law to see if things simplify. This
4996 occurs mostly in addresses, often when unrolling loops. */
4998 if (GET_CODE (XEXP (x, 0)) == PLUS)
5000 rtx result = distribute_and_simplify_rtx (x, 0);
5005 /* Try simplify a*(b/c) as (a*b)/c. */
5006 if (FLOAT_MODE_P (mode) && flag_associative_math
5007 && GET_CODE (XEXP (x, 0)) == DIV)
5009 rtx tem = simplify_binary_operation (MULT, mode,
5010 XEXP (XEXP (x, 0), 0),
5013 return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
5018 /* If this is a divide by a power of two, treat it as a shift if
5019 its first operand is a shift. */
5020 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5021 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
5022 && (GET_CODE (XEXP (x, 0)) == ASHIFT
5023 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
5024 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
5025 || GET_CODE (XEXP (x, 0)) == ROTATE
5026 || GET_CODE (XEXP (x, 0)) == ROTATERT))
5027 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
5031 case GT: case GTU: case GE: case GEU:
5032 case LT: case LTU: case LE: case LEU:
5033 case UNEQ: case LTGT:
5034 case UNGT: case UNGE:
5035 case UNLT: case UNLE:
5036 case UNORDERED: case ORDERED:
5037 /* If the first operand is a condition code, we can't do anything
5039 if (GET_CODE (XEXP (x, 0)) == COMPARE
5040 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
5041 && ! CC0_P (XEXP (x, 0))))
5043 rtx op0 = XEXP (x, 0);
5044 rtx op1 = XEXP (x, 1);
5045 enum rtx_code new_code;
5047 if (GET_CODE (op0) == COMPARE)
5048 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
5050 /* Simplify our comparison, if possible. */
5051 new_code = simplify_comparison (code, &op0, &op1);
5053 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5054 if only the low-order bit is possibly nonzero in X (such as when
5055 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5056 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5057 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5060 Remove any ZERO_EXTRACT we made when thinking this was a
5061 comparison. It may now be simpler to use, e.g., an AND. If a
5062 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5063 the call to make_compound_operation in the SET case. */
5065 if (STORE_FLAG_VALUE == 1
5066 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5067 && op1 == const0_rtx
5068 && mode == GET_MODE (op0)
5069 && nonzero_bits (op0, mode) == 1)
5070 return gen_lowpart (mode,
5071 expand_compound_operation (op0));
5073 else if (STORE_FLAG_VALUE == 1
5074 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5075 && op1 == const0_rtx
5076 && mode == GET_MODE (op0)
5077 && (num_sign_bit_copies (op0, mode)
5078 == GET_MODE_BITSIZE (mode)))
5080 op0 = expand_compound_operation (op0);
5081 return simplify_gen_unary (NEG, mode,
5082 gen_lowpart (mode, op0),
5086 else if (STORE_FLAG_VALUE == 1
5087 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5088 && op1 == const0_rtx
5089 && mode == GET_MODE (op0)
5090 && nonzero_bits (op0, mode) == 1)
5092 op0 = expand_compound_operation (op0);
5093 return simplify_gen_binary (XOR, mode,
5094 gen_lowpart (mode, op0),
5098 else if (STORE_FLAG_VALUE == 1
5099 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5100 && op1 == const0_rtx
5101 && mode == GET_MODE (op0)
5102 && (num_sign_bit_copies (op0, mode)
5103 == GET_MODE_BITSIZE (mode)))
5105 op0 = expand_compound_operation (op0);
5106 return plus_constant (gen_lowpart (mode, op0), 1);
5109 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5111 if (STORE_FLAG_VALUE == -1
5112 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5113 && op1 == const0_rtx
5114 && (num_sign_bit_copies (op0, mode)
5115 == GET_MODE_BITSIZE (mode)))
5116 return gen_lowpart (mode,
5117 expand_compound_operation (op0));
5119 else if (STORE_FLAG_VALUE == -1
5120 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5121 && op1 == const0_rtx
5122 && mode == GET_MODE (op0)
5123 && nonzero_bits (op0, mode) == 1)
5125 op0 = expand_compound_operation (op0);
5126 return simplify_gen_unary (NEG, mode,
5127 gen_lowpart (mode, op0),
5131 else if (STORE_FLAG_VALUE == -1
5132 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5133 && op1 == const0_rtx
5134 && mode == GET_MODE (op0)
5135 && (num_sign_bit_copies (op0, mode)
5136 == GET_MODE_BITSIZE (mode)))
5138 op0 = expand_compound_operation (op0);
5139 return simplify_gen_unary (NOT, mode,
5140 gen_lowpart (mode, op0),
5144 /* If X is 0/1, (eq X 0) is X-1. */
5145 else if (STORE_FLAG_VALUE == -1
5146 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5147 && op1 == const0_rtx
5148 && mode == GET_MODE (op0)
5149 && nonzero_bits (op0, mode) == 1)
5151 op0 = expand_compound_operation (op0);
5152 return plus_constant (gen_lowpart (mode, op0), -1);
5155 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5156 one bit that might be nonzero, we can convert (ne x 0) to
5157 (ashift x c) where C puts the bit in the sign bit. Remove any
5158 AND with STORE_FLAG_VALUE when we are done, since we are only
5159 going to test the sign bit. */
5160 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5161 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5162 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5163 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5164 && op1 == const0_rtx
5165 && mode == GET_MODE (op0)
5166 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
5168 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
5169 expand_compound_operation (op0),
5170 GET_MODE_BITSIZE (mode) - 1 - i);
5171 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
5177 /* If the code changed, return a whole new comparison. */
5178 if (new_code != code)
5179 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
5181 /* Otherwise, keep this operation, but maybe change its operands.
5182 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5183 SUBST (XEXP (x, 0), op0);
5184 SUBST (XEXP (x, 1), op1);
5189 return simplify_if_then_else (x);
5195 /* If we are processing SET_DEST, we are done. */
5199 return expand_compound_operation (x);
5202 return simplify_set (x);
5206 return simplify_logical (x);
5213 /* If this is a shift by a constant amount, simplify it. */
5214 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
5215 return simplify_shift_const (x, code, mode, XEXP (x, 0),
5216 INTVAL (XEXP (x, 1)));
5218 else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
5220 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
5222 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
5234 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5237 simplify_if_then_else (rtx x)
5239 enum machine_mode mode = GET_MODE (x);
5240 rtx cond = XEXP (x, 0);
5241 rtx true_rtx = XEXP (x, 1);
5242 rtx false_rtx = XEXP (x, 2);
5243 enum rtx_code true_code = GET_CODE (cond);
5244 int comparison_p = COMPARISON_P (cond);
5247 enum rtx_code false_code;
5250 /* Simplify storing of the truth value. */
5251 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
5252 return simplify_gen_relational (true_code, mode, VOIDmode,
5253 XEXP (cond, 0), XEXP (cond, 1));
5255 /* Also when the truth value has to be reversed. */
5257 && true_rtx == const0_rtx && false_rtx == const_true_rtx
5258 && (reversed = reversed_comparison (cond, mode)))
5261 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5262 in it is being compared against certain values. Get the true and false
5263 comparisons and see if that says anything about the value of each arm. */
5266 && ((false_code = reversed_comparison_code (cond, NULL))
5268 && REG_P (XEXP (cond, 0)))
5271 rtx from = XEXP (cond, 0);
5272 rtx true_val = XEXP (cond, 1);
5273 rtx false_val = true_val;
5276 /* If FALSE_CODE is EQ, swap the codes and arms. */
5278 if (false_code == EQ)
5280 swapped = 1, true_code = EQ, false_code = NE;
5281 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5284 /* If we are comparing against zero and the expression being tested has
5285 only a single bit that might be nonzero, that is its value when it is
5286 not equal to zero. Similarly if it is known to be -1 or 0. */
5288 if (true_code == EQ && true_val == const0_rtx
5289 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
5292 false_val = GEN_INT (trunc_int_for_mode (nzb, GET_MODE (from)));
5294 else if (true_code == EQ && true_val == const0_rtx
5295 && (num_sign_bit_copies (from, GET_MODE (from))
5296 == GET_MODE_BITSIZE (GET_MODE (from))))
5299 false_val = constm1_rtx;
5302 /* Now simplify an arm if we know the value of the register in the
5303 branch and it is used in the arm. Be careful due to the potential
5304 of locally-shared RTL. */
5306 if (reg_mentioned_p (from, true_rtx))
5307 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
5309 pc_rtx, pc_rtx, 0, 0);
5310 if (reg_mentioned_p (from, false_rtx))
5311 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
5313 pc_rtx, pc_rtx, 0, 0);
5315 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
5316 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
5318 true_rtx = XEXP (x, 1);
5319 false_rtx = XEXP (x, 2);
5320 true_code = GET_CODE (cond);
5323 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
5324 reversed, do so to avoid needing two sets of patterns for
5325 subtract-and-branch insns. Similarly if we have a constant in the true
5326 arm, the false arm is the same as the first operand of the comparison, or
5327 the false arm is more complicated than the true arm. */
5330 && reversed_comparison_code (cond, NULL) != UNKNOWN
5331 && (true_rtx == pc_rtx
5332 || (CONSTANT_P (true_rtx)
5333 && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
5334 || true_rtx == const0_rtx
5335 || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
5336 || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
5337 && !OBJECT_P (false_rtx))
5338 || reg_mentioned_p (true_rtx, false_rtx)
5339 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
5341 true_code = reversed_comparison_code (cond, NULL);
5342 SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
5343 SUBST (XEXP (x, 1), false_rtx);
5344 SUBST (XEXP (x, 2), true_rtx);
5346 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5349 /* It is possible that the conditional has been simplified out. */
5350 true_code = GET_CODE (cond);
5351 comparison_p = COMPARISON_P (cond);
5354 /* If the two arms are identical, we don't need the comparison. */
5356 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
5359 /* Convert a == b ? b : a to "a". */
5360 if (true_code == EQ && ! side_effects_p (cond)
5361 && !HONOR_NANS (mode)
5362 && rtx_equal_p (XEXP (cond, 0), false_rtx)
5363 && rtx_equal_p (XEXP (cond, 1), true_rtx))
5365 else if (true_code == NE && ! side_effects_p (cond)
5366 && !HONOR_NANS (mode)
5367 && rtx_equal_p (XEXP (cond, 0), true_rtx)
5368 && rtx_equal_p (XEXP (cond, 1), false_rtx))
5371 /* Look for cases where we have (abs x) or (neg (abs X)). */
5373 if (GET_MODE_CLASS (mode) == MODE_INT
5375 && XEXP (cond, 1) == const0_rtx
5376 && GET_CODE (false_rtx) == NEG
5377 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
5378 && rtx_equal_p (true_rtx, XEXP (cond, 0))
5379 && ! side_effects_p (true_rtx))
5384 return simplify_gen_unary (ABS, mode, true_rtx, mode);
5388 simplify_gen_unary (NEG, mode,
5389 simplify_gen_unary (ABS, mode, true_rtx, mode),
5395 /* Look for MIN or MAX. */
5397 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
5399 && rtx_equal_p (XEXP (cond, 0), true_rtx)
5400 && rtx_equal_p (XEXP (cond, 1), false_rtx)
5401 && ! side_effects_p (cond))
5406 return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
5409 return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
5412 return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
5415 return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
5420 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
5421 second operand is zero, this can be done as (OP Z (mult COND C2)) where
5422 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
5423 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
5424 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
5425 neither 1 or -1, but it isn't worth checking for. */
5427 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
5429 && GET_MODE_CLASS (mode) == MODE_INT
5430 && ! side_effects_p (x))
5432 rtx t = make_compound_operation (true_rtx, SET);
5433 rtx f = make_compound_operation (false_rtx, SET);
5434 rtx cond_op0 = XEXP (cond, 0);
5435 rtx cond_op1 = XEXP (cond, 1);
5436 enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
5437 enum machine_mode m = mode;
5438 rtx z = 0, c1 = NULL_RTX;
5440 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
5441 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
5442 || GET_CODE (t) == ASHIFT
5443 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
5444 && rtx_equal_p (XEXP (t, 0), f))
5445 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
5447 /* If an identity-zero op is commutative, check whether there
5448 would be a match if we swapped the operands. */
5449 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
5450 || GET_CODE (t) == XOR)
5451 && rtx_equal_p (XEXP (t, 1), f))
5452 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
5453 else if (GET_CODE (t) == SIGN_EXTEND
5454 && (GET_CODE (XEXP (t, 0)) == PLUS
5455 || GET_CODE (XEXP (t, 0)) == MINUS
5456 || GET_CODE (XEXP (t, 0)) == IOR
5457 || GET_CODE (XEXP (t, 0)) == XOR
5458 || GET_CODE (XEXP (t, 0)) == ASHIFT
5459 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5460 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5461 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5462 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5463 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5464 && (num_sign_bit_copies (f, GET_MODE (f))
5466 (GET_MODE_BITSIZE (mode)
5467 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
5469 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5470 extend_op = SIGN_EXTEND;
5471 m = GET_MODE (XEXP (t, 0));
5473 else if (GET_CODE (t) == SIGN_EXTEND
5474 && (GET_CODE (XEXP (t, 0)) == PLUS
5475 || GET_CODE (XEXP (t, 0)) == IOR
5476 || GET_CODE (XEXP (t, 0)) == XOR)
5477 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5478 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5479 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5480 && (num_sign_bit_copies (f, GET_MODE (f))
5482 (GET_MODE_BITSIZE (mode)
5483 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
5485 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5486 extend_op = SIGN_EXTEND;
5487 m = GET_MODE (XEXP (t, 0));
5489 else if (GET_CODE (t) == ZERO_EXTEND
5490 && (GET_CODE (XEXP (t, 0)) == PLUS
5491 || GET_CODE (XEXP (t, 0)) == MINUS
5492 || GET_CODE (XEXP (t, 0)) == IOR
5493 || GET_CODE (XEXP (t, 0)) == XOR
5494 || GET_CODE (XEXP (t, 0)) == ASHIFT
5495 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5496 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5497 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5498 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5499 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5500 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5501 && ((nonzero_bits (f, GET_MODE (f))
5502 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
5505 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5506 extend_op = ZERO_EXTEND;
5507 m = GET_MODE (XEXP (t, 0));
5509 else if (GET_CODE (t) == ZERO_EXTEND
5510 && (GET_CODE (XEXP (t, 0)) == PLUS
5511 || GET_CODE (XEXP (t, 0)) == IOR
5512 || GET_CODE (XEXP (t, 0)) == XOR)
5513 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5514 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5515 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5516 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5517 && ((nonzero_bits (f, GET_MODE (f))
5518 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
5521 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5522 extend_op = ZERO_EXTEND;
5523 m = GET_MODE (XEXP (t, 0));
5528 temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
5529 cond_op0, cond_op1),
5530 pc_rtx, pc_rtx, 0, 0);
5531 temp = simplify_gen_binary (MULT, m, temp,
5532 simplify_gen_binary (MULT, m, c1,
5534 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
5535 temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
5537 if (extend_op != UNKNOWN)
5538 temp = simplify_gen_unary (extend_op, mode, temp, m);
5544 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5545 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5546 negation of a single bit, we can convert this operation to a shift. We
5547 can actually do this more generally, but it doesn't seem worth it. */
5549 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5550 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5551 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
5552 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
5553 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
5554 == GET_MODE_BITSIZE (mode))
5555 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
5557 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5558 gen_lowpart (mode, XEXP (cond, 0)), i);
5560 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
5561 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5562 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5563 && GET_MODE (XEXP (cond, 0)) == mode
5564 && (INTVAL (true_rtx) & GET_MODE_MASK (mode))
5565 == nonzero_bits (XEXP (cond, 0), mode)
5566 && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
5567 return XEXP (cond, 0);
5572 /* Simplify X, a SET expression. Return the new expression. */
5575 simplify_set (rtx x)
5577 rtx src = SET_SRC (x);
5578 rtx dest = SET_DEST (x);
5579 enum machine_mode mode
5580 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
5584 /* (set (pc) (return)) gets written as (return). */
5585 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
5588 /* Now that we know for sure which bits of SRC we are using, see if we can
5589 simplify the expression for the object knowing that we only need the
5592 if (GET_MODE_CLASS (mode) == MODE_INT
5593 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5595 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, 0);
5596 SUBST (SET_SRC (x), src);
5599 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5600 the comparison result and try to simplify it unless we already have used
5601 undobuf.other_insn. */
5602 if ((GET_MODE_CLASS (mode) == MODE_CC
5603 || GET_CODE (src) == COMPARE
5605 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5606 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5607 && COMPARISON_P (*cc_use)
5608 && rtx_equal_p (XEXP (*cc_use, 0), dest))
5610 enum rtx_code old_code = GET_CODE (*cc_use);
5611 enum rtx_code new_code;
5613 int other_changed = 0;
5614 enum machine_mode compare_mode = GET_MODE (dest);
5616 if (GET_CODE (src) == COMPARE)
5617 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5619 op0 = src, op1 = CONST0_RTX (GET_MODE (src));
5621 tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
5624 new_code = old_code;
5625 else if (!CONSTANT_P (tmp))
5627 new_code = GET_CODE (tmp);
5628 op0 = XEXP (tmp, 0);
5629 op1 = XEXP (tmp, 1);
5633 rtx pat = PATTERN (other_insn);
5634 undobuf.other_insn = other_insn;
5635 SUBST (*cc_use, tmp);
5637 /* Attempt to simplify CC user. */
5638 if (GET_CODE (pat) == SET)
5640 rtx new_rtx = simplify_rtx (SET_SRC (pat));
5641 if (new_rtx != NULL_RTX)
5642 SUBST (SET_SRC (pat), new_rtx);
5645 /* Convert X into a no-op move. */
5646 SUBST (SET_DEST (x), pc_rtx);
5647 SUBST (SET_SRC (x), pc_rtx);
5651 /* Simplify our comparison, if possible. */
5652 new_code = simplify_comparison (new_code, &op0, &op1);
5654 #ifdef SELECT_CC_MODE
5655 /* If this machine has CC modes other than CCmode, check to see if we
5656 need to use a different CC mode here. */
5657 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
5658 compare_mode = GET_MODE (op0);
5660 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5663 /* If the mode changed, we have to change SET_DEST, the mode in the
5664 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5665 a hard register, just build new versions with the proper mode. If it
5666 is a pseudo, we lose unless it is only time we set the pseudo, in
5667 which case we can safely change its mode. */
5668 if (compare_mode != GET_MODE (dest))
5670 if (can_change_dest_mode (dest, 0, compare_mode))
5672 unsigned int regno = REGNO (dest);
5675 if (regno < FIRST_PSEUDO_REGISTER)
5676 new_dest = gen_rtx_REG (compare_mode, regno);
5679 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
5680 new_dest = regno_reg_rtx[regno];
5683 SUBST (SET_DEST (x), new_dest);
5684 SUBST (XEXP (*cc_use, 0), new_dest);
5691 #endif /* SELECT_CC_MODE */
5693 /* If the code changed, we have to build a new comparison in
5694 undobuf.other_insn. */
5695 if (new_code != old_code)
5697 int other_changed_previously = other_changed;
5698 unsigned HOST_WIDE_INT mask;
5700 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5704 /* If the only change we made was to change an EQ into an NE or
5705 vice versa, OP0 has only one bit that might be nonzero, and OP1
5706 is zero, check if changing the user of the condition code will
5707 produce a valid insn. If it won't, we can keep the original code
5708 in that insn by surrounding our operation with an XOR. */
5710 if (((old_code == NE && new_code == EQ)
5711 || (old_code == EQ && new_code == NE))
5712 && ! other_changed_previously && op1 == const0_rtx
5713 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5714 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5716 rtx pat = PATTERN (other_insn), note = 0;
5718 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
5719 && ! check_asm_operands (pat)))
5721 PUT_CODE (*cc_use, old_code);
5724 op0 = simplify_gen_binary (XOR, GET_MODE (op0),
5725 op0, GEN_INT (mask));
5731 undobuf.other_insn = other_insn;
5734 /* If we are now comparing against zero, change our source if
5735 needed. If we do not use cc0, we always have a COMPARE. */
5736 if (op1 == const0_rtx && dest == cc0_rtx)
5738 SUBST (SET_SRC (x), op0);
5744 /* Otherwise, if we didn't previously have a COMPARE in the
5745 correct mode, we need one. */
5746 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5748 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5751 else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
5753 SUBST (SET_SRC (x), op0);
5756 /* Otherwise, update the COMPARE if needed. */
5757 else if (XEXP (src, 0) != op0 || XEXP (src, 1) != op1)
5759 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5765 /* Get SET_SRC in a form where we have placed back any
5766 compound expressions. Then do the checks below. */
5767 src = make_compound_operation (src, SET);
5768 SUBST (SET_SRC (x), src);
5771 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5772 and X being a REG or (subreg (reg)), we may be able to convert this to
5773 (set (subreg:m2 x) (op)).
5775 We can always do this if M1 is narrower than M2 because that means that
5776 we only care about the low bits of the result.
5778 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5779 perform a narrower operation than requested since the high-order bits will
5780 be undefined. On machine where it is defined, this transformation is safe
5781 as long as M1 and M2 have the same number of words. */
5783 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5784 && !OBJECT_P (SUBREG_REG (src))
5785 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5787 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5788 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5789 #ifndef WORD_REGISTER_OPERATIONS
5790 && (GET_MODE_SIZE (GET_MODE (src))
5791 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5793 #ifdef CANNOT_CHANGE_MODE_CLASS
5794 && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
5795 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
5796 GET_MODE (SUBREG_REG (src)),
5800 || (GET_CODE (dest) == SUBREG
5801 && REG_P (SUBREG_REG (dest)))))
5803 SUBST (SET_DEST (x),
5804 gen_lowpart (GET_MODE (SUBREG_REG (src)),
5806 SUBST (SET_SRC (x), SUBREG_REG (src));
5808 src = SET_SRC (x), dest = SET_DEST (x);
5812 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5815 && GET_CODE (src) == SUBREG
5816 && subreg_lowpart_p (src)
5817 && (GET_MODE_BITSIZE (GET_MODE (src))
5818 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
5820 rtx inner = SUBREG_REG (src);
5821 enum machine_mode inner_mode = GET_MODE (inner);
5823 /* Here we make sure that we don't have a sign bit on. */
5824 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
5825 && (nonzero_bits (inner, inner_mode)
5826 < ((unsigned HOST_WIDE_INT) 1
5827 << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
5829 SUBST (SET_SRC (x), inner);
5835 #ifdef LOAD_EXTEND_OP
5836 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5837 would require a paradoxical subreg. Replace the subreg with a
5838 zero_extend to avoid the reload that would otherwise be required. */
5840 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5841 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
5842 && SUBREG_BYTE (src) == 0
5843 && (GET_MODE_SIZE (GET_MODE (src))
5844 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5845 && MEM_P (SUBREG_REG (src)))
5848 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5849 GET_MODE (src), SUBREG_REG (src)));
5855 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5856 are comparing an item known to be 0 or -1 against 0, use a logical
5857 operation instead. Check for one of the arms being an IOR of the other
5858 arm with some value. We compute three terms to be IOR'ed together. In
5859 practice, at most two will be nonzero. Then we do the IOR's. */
5861 if (GET_CODE (dest) != PC
5862 && GET_CODE (src) == IF_THEN_ELSE
5863 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5864 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5865 && XEXP (XEXP (src, 0), 1) == const0_rtx
5866 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5867 #ifdef HAVE_conditional_move
5868 && ! can_conditionally_move_p (GET_MODE (src))
5870 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5871 GET_MODE (XEXP (XEXP (src, 0), 0)))
5872 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5873 && ! side_effects_p (src))
5875 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5876 ? XEXP (src, 1) : XEXP (src, 2));
5877 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5878 ? XEXP (src, 2) : XEXP (src, 1));
5879 rtx term1 = const0_rtx, term2, term3;
5881 if (GET_CODE (true_rtx) == IOR
5882 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5883 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
5884 else if (GET_CODE (true_rtx) == IOR
5885 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5886 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
5887 else if (GET_CODE (false_rtx) == IOR
5888 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5889 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
5890 else if (GET_CODE (false_rtx) == IOR
5891 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5892 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
5894 term2 = simplify_gen_binary (AND, GET_MODE (src),
5895 XEXP (XEXP (src, 0), 0), true_rtx);
5896 term3 = simplify_gen_binary (AND, GET_MODE (src),
5897 simplify_gen_unary (NOT, GET_MODE (src),
5898 XEXP (XEXP (src, 0), 0),
5903 simplify_gen_binary (IOR, GET_MODE (src),
5904 simplify_gen_binary (IOR, GET_MODE (src),
5911 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5912 whole thing fail. */
5913 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5915 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5918 /* Convert this into a field assignment operation, if possible. */
5919 return make_field_assignment (x);
5922 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5926 simplify_logical (rtx x)
5928 enum machine_mode mode = GET_MODE (x);
5929 rtx op0 = XEXP (x, 0);
5930 rtx op1 = XEXP (x, 1);
5932 switch (GET_CODE (x))
5935 /* We can call simplify_and_const_int only if we don't lose
5936 any (sign) bits when converting INTVAL (op1) to
5937 "unsigned HOST_WIDE_INT". */
5938 if (GET_CODE (op1) == CONST_INT
5939 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5940 || INTVAL (op1) > 0))
5942 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5943 if (GET_CODE (x) != AND)
5950 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
5951 apply the distributive law and then the inverse distributive
5952 law to see if things simplify. */
5953 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5955 rtx result = distribute_and_simplify_rtx (x, 0);
5959 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5961 rtx result = distribute_and_simplify_rtx (x, 1);
5968 /* If we have (ior (and A B) C), apply the distributive law and then
5969 the inverse distributive law to see if things simplify. */
5971 if (GET_CODE (op0) == AND)
5973 rtx result = distribute_and_simplify_rtx (x, 0);
5978 if (GET_CODE (op1) == AND)
5980 rtx result = distribute_and_simplify_rtx (x, 1);
5993 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5994 operations" because they can be replaced with two more basic operations.
5995 ZERO_EXTEND is also considered "compound" because it can be replaced with
5996 an AND operation, which is simpler, though only one operation.
5998 The function expand_compound_operation is called with an rtx expression
5999 and will convert it to the appropriate shifts and AND operations,
6000 simplifying at each stage.
6002 The function make_compound_operation is called to convert an expression
6003 consisting of shifts and ANDs into the equivalent compound expression.
6004 It is the inverse of this function, loosely speaking. */
6007 expand_compound_operation (rtx x)
6009 unsigned HOST_WIDE_INT pos = 0, len;
6011 unsigned int modewidth;
6014 switch (GET_CODE (x))
6019 /* We can't necessarily use a const_int for a multiword mode;
6020 it depends on implicitly extending the value.
6021 Since we don't know the right way to extend it,
6022 we can't tell whether the implicit way is right.
6024 Even for a mode that is no wider than a const_int,
6025 we can't win, because we need to sign extend one of its bits through
6026 the rest of it, and we don't know which bit. */
6027 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
6030 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6031 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6032 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6033 reloaded. If not for that, MEM's would very rarely be safe.
6035 Reject MODEs bigger than a word, because we might not be able
6036 to reference a two-register group starting with an arbitrary register
6037 (and currently gen_lowpart might crash for a SUBREG). */
6039 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
6042 /* Reject MODEs that aren't scalar integers because turning vector
6043 or complex modes into shifts causes problems. */
6045 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6048 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
6049 /* If the inner object has VOIDmode (the only way this can happen
6050 is if it is an ASM_OPERANDS), we can't do anything since we don't
6051 know how much masking to do. */
6060 /* ... fall through ... */
6063 /* If the operand is a CLOBBER, just return it. */
6064 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
6067 if (GET_CODE (XEXP (x, 1)) != CONST_INT
6068 || GET_CODE (XEXP (x, 2)) != CONST_INT
6069 || GET_MODE (XEXP (x, 0)) == VOIDmode)
6072 /* Reject MODEs that aren't scalar integers because turning vector
6073 or complex modes into shifts causes problems. */
6075 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6078 len = INTVAL (XEXP (x, 1));
6079 pos = INTVAL (XEXP (x, 2));
6081 /* This should stay within the object being extracted, fail otherwise. */
6082 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
6085 if (BITS_BIG_ENDIAN)
6086 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
6093 /* Convert sign extension to zero extension, if we know that the high
6094 bit is not set, as this is easier to optimize. It will be converted
6095 back to cheaper alternative in make_extraction. */
6096 if (GET_CODE (x) == SIGN_EXTEND
6097 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6098 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6099 & ~(((unsigned HOST_WIDE_INT)
6100 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
6104 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
6105 rtx temp2 = expand_compound_operation (temp);
6107 /* Make sure this is a profitable operation. */
6108 if (rtx_cost (x, SET) > rtx_cost (temp2, SET))
6110 else if (rtx_cost (x, SET) > rtx_cost (temp, SET))
6116 /* We can optimize some special cases of ZERO_EXTEND. */
6117 if (GET_CODE (x) == ZERO_EXTEND)
6119 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6120 know that the last value didn't have any inappropriate bits
6122 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6123 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6124 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6125 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
6126 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6127 return XEXP (XEXP (x, 0), 0);
6129 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6130 if (GET_CODE (XEXP (x, 0)) == SUBREG
6131 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6132 && subreg_lowpart_p (XEXP (x, 0))
6133 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6134 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
6135 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6136 return SUBREG_REG (XEXP (x, 0));
6138 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6139 is a comparison and STORE_FLAG_VALUE permits. This is like
6140 the first case, but it works even when GET_MODE (x) is larger
6141 than HOST_WIDE_INT. */
6142 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6143 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6144 && COMPARISON_P (XEXP (XEXP (x, 0), 0))
6145 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6146 <= HOST_BITS_PER_WIDE_INT)
6147 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
6148 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6149 return XEXP (XEXP (x, 0), 0);
6151 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6152 if (GET_CODE (XEXP (x, 0)) == SUBREG
6153 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6154 && subreg_lowpart_p (XEXP (x, 0))
6155 && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
6156 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6157 <= HOST_BITS_PER_WIDE_INT)
6158 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
6159 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6160 return SUBREG_REG (XEXP (x, 0));
6164 /* If we reach here, we want to return a pair of shifts. The inner
6165 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6166 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6167 logical depending on the value of UNSIGNEDP.
6169 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6170 converted into an AND of a shift.
6172 We must check for the case where the left shift would have a negative
6173 count. This can happen in a case like (x >> 31) & 255 on machines
6174 that can't shift by a constant. On those machines, we would first
6175 combine the shift with the AND to produce a variable-position
6176 extraction. Then the constant of 31 would be substituted in to produce
6177 a such a position. */
6179 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
6180 if (modewidth + len >= pos)
6182 enum machine_mode mode = GET_MODE (x);
6183 tem = gen_lowpart (mode, XEXP (x, 0));
6184 if (!tem || GET_CODE (tem) == CLOBBER)
6186 tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
6187 tem, modewidth - pos - len);
6188 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
6189 mode, tem, modewidth - len);
6191 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
6192 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
6193 simplify_shift_const (NULL_RTX, LSHIFTRT,
6196 ((HOST_WIDE_INT) 1 << len) - 1);
6198 /* Any other cases we can't handle. */
6201 /* If we couldn't do this for some reason, return the original
6203 if (GET_CODE (tem) == CLOBBER)
6209 /* X is a SET which contains an assignment of one object into
6210 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6211 or certain SUBREGS). If possible, convert it into a series of
6214 We half-heartedly support variable positions, but do not at all
6215 support variable lengths. */
6218 expand_field_assignment (const_rtx x)
6221 rtx pos; /* Always counts from low bit. */
6223 rtx mask, cleared, masked;
6224 enum machine_mode compute_mode;
6226 /* Loop until we find something we can't simplify. */
6229 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
6230 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
6232 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
6233 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
6234 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
6236 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
6237 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
6239 inner = XEXP (SET_DEST (x), 0);
6240 len = INTVAL (XEXP (SET_DEST (x), 1));
6241 pos = XEXP (SET_DEST (x), 2);
6243 /* A constant position should stay within the width of INNER. */
6244 if (GET_CODE (pos) == CONST_INT
6245 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
6248 if (BITS_BIG_ENDIAN)
6250 if (GET_CODE (pos) == CONST_INT)
6251 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
6253 else if (GET_CODE (pos) == MINUS
6254 && GET_CODE (XEXP (pos, 1)) == CONST_INT
6255 && (INTVAL (XEXP (pos, 1))
6256 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
6257 /* If position is ADJUST - X, new position is X. */
6258 pos = XEXP (pos, 0);
6260 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
6261 GEN_INT (GET_MODE_BITSIZE (
6268 /* A SUBREG between two modes that occupy the same numbers of words
6269 can be done by moving the SUBREG to the source. */
6270 else if (GET_CODE (SET_DEST (x)) == SUBREG
6271 /* We need SUBREGs to compute nonzero_bits properly. */
6272 && nonzero_sign_valid
6273 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
6274 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
6275 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
6276 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
6278 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
6280 (GET_MODE (SUBREG_REG (SET_DEST (x))),
6287 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6288 inner = SUBREG_REG (inner);
6290 compute_mode = GET_MODE (inner);
6292 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6293 if (! SCALAR_INT_MODE_P (compute_mode))
6295 enum machine_mode imode;
6297 /* Don't do anything for vector or complex integral types. */
6298 if (! FLOAT_MODE_P (compute_mode))
6301 /* Try to find an integral mode to pun with. */
6302 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
6303 if (imode == BLKmode)
6306 compute_mode = imode;
6307 inner = gen_lowpart (imode, inner);
6310 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6311 if (len >= HOST_BITS_PER_WIDE_INT)
6314 /* Now compute the equivalent expression. Make a copy of INNER
6315 for the SET_DEST in case it is a MEM into which we will substitute;
6316 we don't want shared RTL in that case. */
6317 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
6318 cleared = simplify_gen_binary (AND, compute_mode,
6319 simplify_gen_unary (NOT, compute_mode,
6320 simplify_gen_binary (ASHIFT,
6325 masked = simplify_gen_binary (ASHIFT, compute_mode,
6326 simplify_gen_binary (
6328 gen_lowpart (compute_mode, SET_SRC (x)),
6332 x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
6333 simplify_gen_binary (IOR, compute_mode,
6340 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6341 it is an RTX that represents a variable starting position; otherwise,
6342 POS is the (constant) starting bit position (counted from the LSB).
6344 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6347 IN_DEST is nonzero if this is a reference in the destination of a
6348 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6349 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6352 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6353 ZERO_EXTRACT should be built even for bits starting at bit 0.
6355 MODE is the desired mode of the result (if IN_DEST == 0).
6357 The result is an RTX for the extraction or NULL_RTX if the target
6361 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
6362 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
6363 int in_dest, int in_compare)
6365 /* This mode describes the size of the storage area
6366 to fetch the overall value from. Within that, we
6367 ignore the POS lowest bits, etc. */
6368 enum machine_mode is_mode = GET_MODE (inner);
6369 enum machine_mode inner_mode;
6370 enum machine_mode wanted_inner_mode;
6371 enum machine_mode wanted_inner_reg_mode = word_mode;
6372 enum machine_mode pos_mode = word_mode;
6373 enum machine_mode extraction_mode = word_mode;
6374 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
6376 rtx orig_pos_rtx = pos_rtx;
6377 HOST_WIDE_INT orig_pos;
6379 if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6381 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6382 consider just the QI as the memory to extract from.
6383 The subreg adds or removes high bits; its mode is
6384 irrelevant to the meaning of this extraction,
6385 since POS and LEN count from the lsb. */
6386 if (MEM_P (SUBREG_REG (inner)))
6387 is_mode = GET_MODE (SUBREG_REG (inner));
6388 inner = SUBREG_REG (inner);
6390 else if (GET_CODE (inner) == ASHIFT
6391 && GET_CODE (XEXP (inner, 1)) == CONST_INT
6392 && pos_rtx == 0 && pos == 0
6393 && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
6395 /* We're extracting the least significant bits of an rtx
6396 (ashift X (const_int C)), where LEN > C. Extract the
6397 least significant (LEN - C) bits of X, giving an rtx
6398 whose mode is MODE, then shift it left C times. */
6399 new_rtx = make_extraction (mode, XEXP (inner, 0),
6400 0, 0, len - INTVAL (XEXP (inner, 1)),
6401 unsignedp, in_dest, in_compare);
6403 return gen_rtx_ASHIFT (mode, new_rtx, XEXP (inner, 1));
6406 inner_mode = GET_MODE (inner);
6408 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
6409 pos = INTVAL (pos_rtx), pos_rtx = 0;
6411 /* See if this can be done without an extraction. We never can if the
6412 width of the field is not the same as that of some integer mode. For
6413 registers, we can only avoid the extraction if the position is at the
6414 low-order bit and this is either not in the destination or we have the
6415 appropriate STRICT_LOW_PART operation available.
6417 For MEM, we can avoid an extract if the field starts on an appropriate
6418 boundary and we can change the mode of the memory reference. */
6420 if (tmode != BLKmode
6421 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
6423 && (inner_mode == tmode
6425 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
6426 GET_MODE_BITSIZE (inner_mode))
6427 || reg_truncated_to_mode (tmode, inner))
6430 && have_insn_for (STRICT_LOW_PART, tmode))))
6431 || (MEM_P (inner) && pos_rtx == 0
6433 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
6434 : BITS_PER_UNIT)) == 0
6435 /* We can't do this if we are widening INNER_MODE (it
6436 may not be aligned, for one thing). */
6437 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
6438 && (inner_mode == tmode
6439 || (! mode_dependent_address_p (XEXP (inner, 0))
6440 && ! MEM_VOLATILE_P (inner))))))
6442 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6443 field. If the original and current mode are the same, we need not
6444 adjust the offset. Otherwise, we do if bytes big endian.
6446 If INNER is not a MEM, get a piece consisting of just the field
6447 of interest (in this case POS % BITS_PER_WORD must be 0). */
6451 HOST_WIDE_INT offset;
6453 /* POS counts from lsb, but make OFFSET count in memory order. */
6454 if (BYTES_BIG_ENDIAN)
6455 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6457 offset = pos / BITS_PER_UNIT;
6459 new_rtx = adjust_address_nv (inner, tmode, offset);
6461 else if (REG_P (inner))
6463 if (tmode != inner_mode)
6465 /* We can't call gen_lowpart in a DEST since we
6466 always want a SUBREG (see below) and it would sometimes
6467 return a new hard register. */
6470 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6472 if (WORDS_BIG_ENDIAN
6473 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6474 final_word = ((GET_MODE_SIZE (inner_mode)
6475 - GET_MODE_SIZE (tmode))
6476 / UNITS_PER_WORD) - final_word;
6478 final_word *= UNITS_PER_WORD;
6479 if (BYTES_BIG_ENDIAN &&
6480 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6481 final_word += (GET_MODE_SIZE (inner_mode)
6482 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6484 /* Avoid creating invalid subregs, for example when
6485 simplifying (x>>32)&255. */
6486 if (!validate_subreg (tmode, inner_mode, inner, final_word))
6489 new_rtx = gen_rtx_SUBREG (tmode, inner, final_word);
6492 new_rtx = gen_lowpart (tmode, inner);
6498 new_rtx = force_to_mode (inner, tmode,
6499 len >= HOST_BITS_PER_WIDE_INT
6500 ? ~(unsigned HOST_WIDE_INT) 0
6501 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6504 /* If this extraction is going into the destination of a SET,
6505 make a STRICT_LOW_PART unless we made a MEM. */
6508 return (MEM_P (new_rtx) ? new_rtx
6509 : (GET_CODE (new_rtx) != SUBREG
6510 ? gen_rtx_CLOBBER (tmode, const0_rtx)
6511 : gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx)));
6516 if (GET_CODE (new_rtx) == CONST_INT)
6517 return gen_int_mode (INTVAL (new_rtx), mode);
6519 /* If we know that no extraneous bits are set, and that the high
6520 bit is not set, convert the extraction to the cheaper of
6521 sign and zero extension, that are equivalent in these cases. */
6522 if (flag_expensive_optimizations
6523 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6524 && ((nonzero_bits (new_rtx, tmode)
6525 & ~(((unsigned HOST_WIDE_INT)
6526 GET_MODE_MASK (tmode))
6530 rtx temp = gen_rtx_ZERO_EXTEND (mode, new_rtx);
6531 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new_rtx);
6533 /* Prefer ZERO_EXTENSION, since it gives more information to
6535 if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
6540 /* Otherwise, sign- or zero-extend unless we already are in the
6543 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6547 /* Unless this is a COMPARE or we have a funny memory reference,
6548 don't do anything with zero-extending field extracts starting at
6549 the low-order bit since they are simple AND operations. */
6550 if (pos_rtx == 0 && pos == 0 && ! in_dest
6551 && ! in_compare && unsignedp)
6554 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
6555 if the position is not a constant and the length is not 1. In all
6556 other cases, we would only be going outside our object in cases when
6557 an original shift would have been undefined. */
6559 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6560 || (pos_rtx != 0 && len != 1)))
6563 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6564 and the mode for the result. */
6565 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6567 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6568 pos_mode = mode_for_extraction (EP_insv, 2);
6569 extraction_mode = mode_for_extraction (EP_insv, 3);
6572 if (! in_dest && unsignedp
6573 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6575 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6576 pos_mode = mode_for_extraction (EP_extzv, 3);
6577 extraction_mode = mode_for_extraction (EP_extzv, 0);
6580 if (! in_dest && ! unsignedp
6581 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6583 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6584 pos_mode = mode_for_extraction (EP_extv, 3);
6585 extraction_mode = mode_for_extraction (EP_extv, 0);
6588 /* Never narrow an object, since that might not be safe. */
6590 if (mode != VOIDmode
6591 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6592 extraction_mode = mode;
6594 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6595 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6596 pos_mode = GET_MODE (pos_rtx);
6598 /* If this is not from memory, the desired mode is the preferred mode
6599 for an extraction pattern's first input operand, or word_mode if there
6602 wanted_inner_mode = wanted_inner_reg_mode;
6605 /* Be careful not to go beyond the extracted object and maintain the
6606 natural alignment of the memory. */
6607 wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
6608 while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
6609 > GET_MODE_BITSIZE (wanted_inner_mode))
6611 wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
6612 gcc_assert (wanted_inner_mode != VOIDmode);
6615 /* If we have to change the mode of memory and cannot, the desired mode
6616 is EXTRACTION_MODE. */
6617 if (inner_mode != wanted_inner_mode
6618 && (mode_dependent_address_p (XEXP (inner, 0))
6619 || MEM_VOLATILE_P (inner)
6621 wanted_inner_mode = extraction_mode;
6626 if (BITS_BIG_ENDIAN)
6628 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6629 BITS_BIG_ENDIAN style. If position is constant, compute new
6630 position. Otherwise, build subtraction.
6631 Note that POS is relative to the mode of the original argument.
6632 If it's a MEM we need to recompute POS relative to that.
6633 However, if we're extracting from (or inserting into) a register,
6634 we want to recompute POS relative to wanted_inner_mode. */
6635 int width = (MEM_P (inner)
6636 ? GET_MODE_BITSIZE (is_mode)
6637 : GET_MODE_BITSIZE (wanted_inner_mode));
6640 pos = width - len - pos;
6643 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6644 /* POS may be less than 0 now, but we check for that below.
6645 Note that it can only be less than 0 if !MEM_P (inner). */
6648 /* If INNER has a wider mode, and this is a constant extraction, try to
6649 make it smaller and adjust the byte to point to the byte containing
6651 if (wanted_inner_mode != VOIDmode
6652 && inner_mode != wanted_inner_mode
6654 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6656 && ! mode_dependent_address_p (XEXP (inner, 0))
6657 && ! MEM_VOLATILE_P (inner))
6661 /* The computations below will be correct if the machine is big
6662 endian in both bits and bytes or little endian in bits and bytes.
6663 If it is mixed, we must adjust. */
6665 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6666 adjust OFFSET to compensate. */
6667 if (BYTES_BIG_ENDIAN
6668 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6669 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6671 /* We can now move to the desired byte. */
6672 offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
6673 * GET_MODE_SIZE (wanted_inner_mode);
6674 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6676 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6677 && is_mode != wanted_inner_mode)
6678 offset = (GET_MODE_SIZE (is_mode)
6679 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6681 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6684 /* If INNER is not memory, we can always get it into the proper mode. If we
6685 are changing its mode, POS must be a constant and smaller than the size
6687 else if (!MEM_P (inner))
6689 if (GET_MODE (inner) != wanted_inner_mode
6691 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6697 inner = force_to_mode (inner, wanted_inner_mode,
6699 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6700 ? ~(unsigned HOST_WIDE_INT) 0
6701 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6706 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6707 have to zero extend. Otherwise, we can just use a SUBREG. */
6709 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6711 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6713 /* If we know that no extraneous bits are set, and that the high
6714 bit is not set, convert extraction to cheaper one - either
6715 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6717 if (flag_expensive_optimizations
6718 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6719 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6720 & ~(((unsigned HOST_WIDE_INT)
6721 GET_MODE_MASK (GET_MODE (pos_rtx)))
6725 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6727 /* Prefer ZERO_EXTENSION, since it gives more information to
6729 if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6734 else if (pos_rtx != 0
6735 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6736 pos_rtx = gen_lowpart (pos_mode, pos_rtx);
6738 /* Make POS_RTX unless we already have it and it is correct. If we don't
6739 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6741 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6742 pos_rtx = orig_pos_rtx;
6744 else if (pos_rtx == 0)
6745 pos_rtx = GEN_INT (pos);
6747 /* Make the required operation. See if we can use existing rtx. */
6748 new_rtx = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6749 extraction_mode, inner, GEN_INT (len), pos_rtx);
6751 new_rtx = gen_lowpart (mode, new_rtx);
6756 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6757 with any other operations in X. Return X without that shift if so. */
6760 extract_left_shift (rtx x, int count)
6762 enum rtx_code code = GET_CODE (x);
6763 enum machine_mode mode = GET_MODE (x);
6769 /* This is the shift itself. If it is wide enough, we will return
6770 either the value being shifted if the shift count is equal to
6771 COUNT or a shift for the difference. */
6772 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6773 && INTVAL (XEXP (x, 1)) >= count)
6774 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6775 INTVAL (XEXP (x, 1)) - count);
6779 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6780 return simplify_gen_unary (code, mode, tem, mode);
6784 case PLUS: case IOR: case XOR: case AND:
6785 /* If we can safely shift this constant and we find the inner shift,
6786 make a new operation. */
6787 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6788 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6789 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6790 return simplify_gen_binary (code, mode, tem,
6791 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6802 /* Look at the expression rooted at X. Look for expressions
6803 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6804 Form these expressions.
6806 Return the new rtx, usually just X.
6808 Also, for machines like the VAX that don't have logical shift insns,
6809 try to convert logical to arithmetic shift operations in cases where
6810 they are equivalent. This undoes the canonicalizations to logical
6811 shifts done elsewhere.
6813 We try, as much as possible, to re-use rtl expressions to save memory.
6815 IN_CODE says what kind of expression we are processing. Normally, it is
6816 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6817 being kludges), it is MEM. When processing the arguments of a comparison
6818 or a COMPARE against zero, it is COMPARE. */
6821 make_compound_operation (rtx x, enum rtx_code in_code)
6823 enum rtx_code code = GET_CODE (x);
6824 enum machine_mode mode = GET_MODE (x);
6825 int mode_width = GET_MODE_BITSIZE (mode);
6827 enum rtx_code next_code;
6833 /* Select the code to be used in recursive calls. Once we are inside an
6834 address, we stay there. If we have a comparison, set to COMPARE,
6835 but once inside, go back to our default of SET. */
6837 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6838 : ((code == COMPARE || COMPARISON_P (x))
6839 && XEXP (x, 1) == const0_rtx) ? COMPARE
6840 : in_code == COMPARE ? SET : in_code);
6842 /* Process depending on the code of this operation. If NEW is set
6843 nonzero, it will be returned. */
6848 /* Convert shifts by constants into multiplications if inside
6850 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6851 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6852 && INTVAL (XEXP (x, 1)) >= 0)
6854 new_rtx = make_compound_operation (XEXP (x, 0), next_code);
6855 new_rtx = gen_rtx_MULT (mode, new_rtx,
6856 GEN_INT ((HOST_WIDE_INT) 1
6857 << INTVAL (XEXP (x, 1))));
6862 /* If the second operand is not a constant, we can't do anything
6864 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6867 /* If the constant is a power of two minus one and the first operand
6868 is a logical right shift, make an extraction. */
6869 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6870 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6872 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6873 new_rtx = make_extraction (mode, new_rtx, 0, XEXP (XEXP (x, 0), 1), i, 1,
6874 0, in_code == COMPARE);
6877 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6878 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6879 && subreg_lowpart_p (XEXP (x, 0))
6880 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6881 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6883 new_rtx = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6885 new_rtx = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new_rtx, 0,
6886 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6887 0, in_code == COMPARE);
6889 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6890 else if ((GET_CODE (XEXP (x, 0)) == XOR
6891 || GET_CODE (XEXP (x, 0)) == IOR)
6892 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6893 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6894 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6896 /* Apply the distributive law, and then try to make extractions. */
6897 new_rtx = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6898 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6900 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6902 new_rtx = make_compound_operation (new_rtx, in_code);
6905 /* If we are have (and (rotate X C) M) and C is larger than the number
6906 of bits in M, this is an extraction. */
6908 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6909 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6910 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6911 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6913 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6914 new_rtx = make_extraction (mode, new_rtx,
6915 (GET_MODE_BITSIZE (mode)
6916 - INTVAL (XEXP (XEXP (x, 0), 1))),
6917 NULL_RTX, i, 1, 0, in_code == COMPARE);
6920 /* On machines without logical shifts, if the operand of the AND is
6921 a logical shift and our mask turns off all the propagated sign
6922 bits, we can replace the logical shift with an arithmetic shift. */
6923 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6924 && !have_insn_for (LSHIFTRT, mode)
6925 && have_insn_for (ASHIFTRT, mode)
6926 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6927 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6928 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6929 && mode_width <= HOST_BITS_PER_WIDE_INT)
6931 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6933 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6934 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6936 gen_rtx_ASHIFTRT (mode,
6937 make_compound_operation
6938 (XEXP (XEXP (x, 0), 0), next_code),
6939 XEXP (XEXP (x, 0), 1)));
6942 /* If the constant is one less than a power of two, this might be
6943 representable by an extraction even if no shift is present.
6944 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6945 we are in a COMPARE. */
6946 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6947 new_rtx = make_extraction (mode,
6948 make_compound_operation (XEXP (x, 0),
6950 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6952 /* If we are in a comparison and this is an AND with a power of two,
6953 convert this into the appropriate bit extract. */
6954 else if (in_code == COMPARE
6955 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6956 new_rtx = make_extraction (mode,
6957 make_compound_operation (XEXP (x, 0),
6959 i, NULL_RTX, 1, 1, 0, 1);
6964 /* If the sign bit is known to be zero, replace this with an
6965 arithmetic shift. */
6966 if (have_insn_for (ASHIFTRT, mode)
6967 && ! have_insn_for (LSHIFTRT, mode)
6968 && mode_width <= HOST_BITS_PER_WIDE_INT
6969 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6971 new_rtx = gen_rtx_ASHIFTRT (mode,
6972 make_compound_operation (XEXP (x, 0),
6978 /* ... fall through ... */
6984 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6985 this is a SIGN_EXTRACT. */
6986 if (GET_CODE (rhs) == CONST_INT
6987 && GET_CODE (lhs) == ASHIFT
6988 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6989 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6991 new_rtx = make_compound_operation (XEXP (lhs, 0), next_code);
6992 new_rtx = make_extraction (mode, new_rtx,
6993 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6994 NULL_RTX, mode_width - INTVAL (rhs),
6995 code == LSHIFTRT, 0, in_code == COMPARE);
6999 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7000 If so, try to merge the shifts into a SIGN_EXTEND. We could
7001 also do this for some cases of SIGN_EXTRACT, but it doesn't
7002 seem worth the effort; the case checked for occurs on Alpha. */
7005 && ! (GET_CODE (lhs) == SUBREG
7006 && (OBJECT_P (SUBREG_REG (lhs))))
7007 && GET_CODE (rhs) == CONST_INT
7008 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
7009 && (new_rtx = extract_left_shift (lhs, INTVAL (rhs))) != 0)
7010 new_rtx = make_extraction (mode, make_compound_operation (new_rtx, next_code),
7011 0, NULL_RTX, mode_width - INTVAL (rhs),
7012 code == LSHIFTRT, 0, in_code == COMPARE);
7017 /* Call ourselves recursively on the inner expression. If we are
7018 narrowing the object and it has a different RTL code from
7019 what it originally did, do this SUBREG as a force_to_mode. */
7021 tem = make_compound_operation (SUBREG_REG (x), in_code);
7025 simplified = simplify_subreg (GET_MODE (x), tem, GET_MODE (tem),
7031 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
7032 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
7033 && subreg_lowpart_p (x))
7035 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
7038 /* If we have something other than a SUBREG, we might have
7039 done an expansion, so rerun ourselves. */
7040 if (GET_CODE (newer) != SUBREG)
7041 newer = make_compound_operation (newer, in_code);
7057 x = gen_lowpart (mode, new_rtx);
7058 code = GET_CODE (x);
7061 /* Now recursively process each operand of this operation. */
7062 fmt = GET_RTX_FORMAT (code);
7063 for (i = 0; i < GET_RTX_LENGTH (code); i++)
7066 new_rtx = make_compound_operation (XEXP (x, i), next_code);
7067 SUBST (XEXP (x, i), new_rtx);
7070 /* If this is a commutative operation, the changes to the operands
7071 may have made it noncanonical. */
7072 if (COMMUTATIVE_ARITH_P (x)
7073 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
7076 SUBST (XEXP (x, 0), XEXP (x, 1));
7077 SUBST (XEXP (x, 1), tem);
7083 /* Given M see if it is a value that would select a field of bits
7084 within an item, but not the entire word. Return -1 if not.
7085 Otherwise, return the starting position of the field, where 0 is the
7088 *PLEN is set to the length of the field. */
7091 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
7093 /* Get the bit number of the first 1 bit from the right, -1 if none. */
7094 int pos = exact_log2 (m & -m);
7098 /* Now shift off the low-order zero bits and see if we have a
7099 power of two minus 1. */
7100 len = exact_log2 ((m >> pos) + 1);
7109 /* If X refers to a register that equals REG in value, replace these
7110 references with REG. */
7112 canon_reg_for_combine (rtx x, rtx reg)
7119 enum rtx_code code = GET_CODE (x);
7120 switch (GET_RTX_CLASS (code))
7123 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7124 if (op0 != XEXP (x, 0))
7125 return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
7130 case RTX_COMM_ARITH:
7131 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7132 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7133 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7134 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
7138 case RTX_COMM_COMPARE:
7139 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7140 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7141 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7142 return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
7143 GET_MODE (op0), op0, op1);
7147 case RTX_BITFIELD_OPS:
7148 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7149 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7150 op2 = canon_reg_for_combine (XEXP (x, 2), reg);
7151 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
7152 return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
7153 GET_MODE (op0), op0, op1, op2);
7158 if (rtx_equal_p (get_last_value (reg), x)
7159 || rtx_equal_p (reg, get_last_value (x)))
7168 fmt = GET_RTX_FORMAT (code);
7170 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7173 rtx op = canon_reg_for_combine (XEXP (x, i), reg);
7174 if (op != XEXP (x, i))
7184 else if (fmt[i] == 'E')
7187 for (j = 0; j < XVECLEN (x, i); j++)
7189 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
7190 if (op != XVECEXP (x, i, j))
7197 XVECEXP (x, i, j) = op;
7208 /* Return X converted to MODE. If the value is already truncated to
7209 MODE we can just return a subreg even though in the general case we
7210 would need an explicit truncation. */
7213 gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
7215 if (GET_MODE_SIZE (GET_MODE (x)) <= GET_MODE_SIZE (mode)
7216 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
7217 GET_MODE_BITSIZE (GET_MODE (x)))
7218 || (REG_P (x) && reg_truncated_to_mode (mode, x)))
7219 return gen_lowpart (mode, x);
7221 return simplify_gen_unary (TRUNCATE, mode, x, GET_MODE (x));
7224 /* See if X can be simplified knowing that we will only refer to it in
7225 MODE and will only refer to those bits that are nonzero in MASK.
7226 If other bits are being computed or if masking operations are done
7227 that select a superset of the bits in MASK, they can sometimes be
7230 Return a possibly simplified expression, but always convert X to
7231 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
7233 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
7234 are all off in X. This is used when X will be complemented, by either
7235 NOT, NEG, or XOR. */
7238 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
7241 enum rtx_code code = GET_CODE (x);
7242 int next_select = just_select || code == XOR || code == NOT || code == NEG;
7243 enum machine_mode op_mode;
7244 unsigned HOST_WIDE_INT fuller_mask, nonzero;
7247 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
7248 code below will do the wrong thing since the mode of such an
7249 expression is VOIDmode.
7251 Also do nothing if X is a CLOBBER; this can happen if X was
7252 the return value from a call to gen_lowpart. */
7253 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
7256 /* We want to perform the operation is its present mode unless we know
7257 that the operation is valid in MODE, in which case we do the operation
7259 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
7260 && have_insn_for (code, mode))
7261 ? mode : GET_MODE (x));
7263 /* It is not valid to do a right-shift in a narrower mode
7264 than the one it came in with. */
7265 if ((code == LSHIFTRT || code == ASHIFTRT)
7266 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
7267 op_mode = GET_MODE (x);
7269 /* Truncate MASK to fit OP_MODE. */
7271 mask &= GET_MODE_MASK (op_mode);
7273 /* When we have an arithmetic operation, or a shift whose count we
7274 do not know, we need to assume that all bits up to the highest-order
7275 bit in MASK will be needed. This is how we form such a mask. */
7276 if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
7277 fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
7279 fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
7282 /* Determine what bits of X are guaranteed to be (non)zero. */
7283 nonzero = nonzero_bits (x, mode);
7285 /* If none of the bits in X are needed, return a zero. */
7286 if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
7289 /* If X is a CONST_INT, return a new one. Do this here since the
7290 test below will fail. */
7291 if (GET_CODE (x) == CONST_INT)
7293 if (SCALAR_INT_MODE_P (mode))
7294 return gen_int_mode (INTVAL (x) & mask, mode);
7297 x = GEN_INT (INTVAL (x) & mask);
7298 return gen_lowpart_common (mode, x);
7302 /* If X is narrower than MODE and we want all the bits in X's mode, just
7303 get X in the proper mode. */
7304 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
7305 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
7306 return gen_lowpart (mode, x);
7311 /* If X is a (clobber (const_int)), return it since we know we are
7312 generating something that won't match. */
7319 x = expand_compound_operation (x);
7320 if (GET_CODE (x) != code)
7321 return force_to_mode (x, mode, mask, next_select);
7325 if (subreg_lowpart_p (x)
7326 /* We can ignore the effect of this SUBREG if it narrows the mode or
7327 if the constant masks to zero all the bits the mode doesn't
7329 && ((GET_MODE_SIZE (GET_MODE (x))
7330 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7332 & GET_MODE_MASK (GET_MODE (x))
7333 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
7334 return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
7338 /* If this is an AND with a constant, convert it into an AND
7339 whose constant is the AND of that constant with MASK. If it
7340 remains an AND of MASK, delete it since it is redundant. */
7342 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
7344 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
7345 mask & INTVAL (XEXP (x, 1)));
7347 /* If X is still an AND, see if it is an AND with a mask that
7348 is just some low-order bits. If so, and it is MASK, we don't
7351 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
7352 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
7356 /* If it remains an AND, try making another AND with the bits
7357 in the mode mask that aren't in MASK turned on. If the
7358 constant in the AND is wide enough, this might make a
7359 cheaper constant. */
7361 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
7362 && GET_MODE_MASK (GET_MODE (x)) != mask
7363 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
7365 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
7366 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
7367 int width = GET_MODE_BITSIZE (GET_MODE (x));
7370 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
7371 number, sign extend it. */
7372 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
7373 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7374 cval |= (HOST_WIDE_INT) -1 << width;
7376 y = simplify_gen_binary (AND, GET_MODE (x),
7377 XEXP (x, 0), GEN_INT (cval));
7378 if (rtx_cost (y, SET) < rtx_cost (x, SET))
7388 /* In (and (plus FOO C1) M), if M is a mask that just turns off
7389 low-order bits (as in an alignment operation) and FOO is already
7390 aligned to that boundary, mask C1 to that boundary as well.
7391 This may eliminate that PLUS and, later, the AND. */
7394 unsigned int width = GET_MODE_BITSIZE (mode);
7395 unsigned HOST_WIDE_INT smask = mask;
7397 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
7398 number, sign extend it. */
7400 if (width < HOST_BITS_PER_WIDE_INT
7401 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7402 smask |= (HOST_WIDE_INT) -1 << width;
7404 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7405 && exact_log2 (- smask) >= 0
7406 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
7407 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
7408 return force_to_mode (plus_constant (XEXP (x, 0),
7409 (INTVAL (XEXP (x, 1)) & smask)),
7410 mode, smask, next_select);
7413 /* ... fall through ... */
7416 /* For PLUS, MINUS and MULT, we need any bits less significant than the
7417 most significant bit in MASK since carries from those bits will
7418 affect the bits we are interested in. */
7423 /* If X is (minus C Y) where C's least set bit is larger than any bit
7424 in the mask, then we may replace with (neg Y). */
7425 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7426 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
7427 & -INTVAL (XEXP (x, 0))))
7430 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
7432 return force_to_mode (x, mode, mask, next_select);
7435 /* Similarly, if C contains every bit in the fuller_mask, then we may
7436 replace with (not Y). */
7437 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7438 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
7439 == INTVAL (XEXP (x, 0))))
7441 x = simplify_gen_unary (NOT, GET_MODE (x),
7442 XEXP (x, 1), GET_MODE (x));
7443 return force_to_mode (x, mode, mask, next_select);
7451 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7452 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7453 operation which may be a bitfield extraction. Ensure that the
7454 constant we form is not wider than the mode of X. */
7456 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7457 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7458 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7459 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7460 && GET_CODE (XEXP (x, 1)) == CONST_INT
7461 && ((INTVAL (XEXP (XEXP (x, 0), 1))
7462 + floor_log2 (INTVAL (XEXP (x, 1))))
7463 < GET_MODE_BITSIZE (GET_MODE (x)))
7464 && (INTVAL (XEXP (x, 1))
7465 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
7467 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
7468 << INTVAL (XEXP (XEXP (x, 0), 1)));
7469 temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
7470 XEXP (XEXP (x, 0), 0), temp);
7471 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
7472 XEXP (XEXP (x, 0), 1));
7473 return force_to_mode (x, mode, mask, next_select);
7477 /* For most binary operations, just propagate into the operation and
7478 change the mode if we have an operation of that mode. */
7480 op0 = gen_lowpart_or_truncate (op_mode,
7481 force_to_mode (XEXP (x, 0), mode, mask,
7483 op1 = gen_lowpart_or_truncate (op_mode,
7484 force_to_mode (XEXP (x, 1), mode, mask,
7487 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7488 x = simplify_gen_binary (code, op_mode, op0, op1);
7492 /* For left shifts, do the same, but just for the first operand.
7493 However, we cannot do anything with shifts where we cannot
7494 guarantee that the counts are smaller than the size of the mode
7495 because such a count will have a different meaning in a
7498 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
7499 && INTVAL (XEXP (x, 1)) >= 0
7500 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
7501 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
7502 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
7503 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
7506 /* If the shift count is a constant and we can do arithmetic in
7507 the mode of the shift, refine which bits we need. Otherwise, use the
7508 conservative form of the mask. */
7509 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7510 && INTVAL (XEXP (x, 1)) >= 0
7511 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
7512 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7513 mask >>= INTVAL (XEXP (x, 1));
7517 op0 = gen_lowpart_or_truncate (op_mode,
7518 force_to_mode (XEXP (x, 0), op_mode,
7519 mask, next_select));
7521 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7522 x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
7526 /* Here we can only do something if the shift count is a constant,
7527 this shift constant is valid for the host, and we can do arithmetic
7530 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7531 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7532 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7534 rtx inner = XEXP (x, 0);
7535 unsigned HOST_WIDE_INT inner_mask;
7537 /* Select the mask of the bits we need for the shift operand. */
7538 inner_mask = mask << INTVAL (XEXP (x, 1));
7540 /* We can only change the mode of the shift if we can do arithmetic
7541 in the mode of the shift and INNER_MASK is no wider than the
7542 width of X's mode. */
7543 if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
7544 op_mode = GET_MODE (x);
7546 inner = force_to_mode (inner, op_mode, inner_mask, next_select);
7548 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7549 x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7552 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7553 shift and AND produces only copies of the sign bit (C2 is one less
7554 than a power of two), we can do this with just a shift. */
7556 if (GET_CODE (x) == LSHIFTRT
7557 && GET_CODE (XEXP (x, 1)) == CONST_INT
7558 /* The shift puts one of the sign bit copies in the least significant
7560 && ((INTVAL (XEXP (x, 1))
7561 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7562 >= GET_MODE_BITSIZE (GET_MODE (x)))
7563 && exact_log2 (mask + 1) >= 0
7564 /* Number of bits left after the shift must be more than the mask
7566 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7567 <= GET_MODE_BITSIZE (GET_MODE (x)))
7568 /* Must be more sign bit copies than the mask needs. */
7569 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7570 >= exact_log2 (mask + 1)))
7571 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7572 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7573 - exact_log2 (mask + 1)));
7578 /* If we are just looking for the sign bit, we don't need this shift at
7579 all, even if it has a variable count. */
7580 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7581 && (mask == ((unsigned HOST_WIDE_INT) 1
7582 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7583 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7585 /* If this is a shift by a constant, get a mask that contains those bits
7586 that are not copies of the sign bit. We then have two cases: If
7587 MASK only includes those bits, this can be a logical shift, which may
7588 allow simplifications. If MASK is a single-bit field not within
7589 those bits, we are requesting a copy of the sign bit and hence can
7590 shift the sign bit to the appropriate location. */
7592 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7593 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7597 /* If the considered data is wider than HOST_WIDE_INT, we can't
7598 represent a mask for all its bits in a single scalar.
7599 But we only care about the lower bits, so calculate these. */
7601 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7603 nonzero = ~(HOST_WIDE_INT) 0;
7605 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7606 is the number of bits a full-width mask would have set.
7607 We need only shift if these are fewer than nonzero can
7608 hold. If not, we must keep all bits set in nonzero. */
7610 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7611 < HOST_BITS_PER_WIDE_INT)
7612 nonzero >>= INTVAL (XEXP (x, 1))
7613 + HOST_BITS_PER_WIDE_INT
7614 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7618 nonzero = GET_MODE_MASK (GET_MODE (x));
7619 nonzero >>= INTVAL (XEXP (x, 1));
7622 if ((mask & ~nonzero) == 0)
7624 x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
7625 XEXP (x, 0), INTVAL (XEXP (x, 1)));
7626 if (GET_CODE (x) != ASHIFTRT)
7627 return force_to_mode (x, mode, mask, next_select);
7630 else if ((i = exact_log2 (mask)) >= 0)
7632 x = simplify_shift_const
7633 (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7634 GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7636 if (GET_CODE (x) != ASHIFTRT)
7637 return force_to_mode (x, mode, mask, next_select);
7641 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7642 even if the shift count isn't a constant. */
7644 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7645 XEXP (x, 0), XEXP (x, 1));
7649 /* If this is a zero- or sign-extension operation that just affects bits
7650 we don't care about, remove it. Be sure the call above returned
7651 something that is still a shift. */
7653 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7654 && GET_CODE (XEXP (x, 1)) == CONST_INT
7655 && INTVAL (XEXP (x, 1)) >= 0
7656 && (INTVAL (XEXP (x, 1))
7657 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7658 && GET_CODE (XEXP (x, 0)) == ASHIFT
7659 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
7660 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7667 /* If the shift count is constant and we can do computations
7668 in the mode of X, compute where the bits we care about are.
7669 Otherwise, we can't do anything. Don't change the mode of
7670 the shift or propagate MODE into the shift, though. */
7671 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7672 && INTVAL (XEXP (x, 1)) >= 0)
7674 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7675 GET_MODE (x), GEN_INT (mask),
7677 if (temp && GET_CODE (temp) == CONST_INT)
7679 force_to_mode (XEXP (x, 0), GET_MODE (x),
7680 INTVAL (temp), next_select));
7685 /* If we just want the low-order bit, the NEG isn't needed since it
7686 won't change the low-order bit. */
7688 return force_to_mode (XEXP (x, 0), mode, mask, just_select);
7690 /* We need any bits less significant than the most significant bit in
7691 MASK since carries from those bits will affect the bits we are
7697 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7698 same as the XOR case above. Ensure that the constant we form is not
7699 wider than the mode of X. */
7701 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7702 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7703 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7704 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7705 < GET_MODE_BITSIZE (GET_MODE (x)))
7706 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7708 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
7710 temp = simplify_gen_binary (XOR, GET_MODE (x),
7711 XEXP (XEXP (x, 0), 0), temp);
7712 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7713 temp, XEXP (XEXP (x, 0), 1));
7715 return force_to_mode (x, mode, mask, next_select);
7718 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7719 use the full mask inside the NOT. */
7723 op0 = gen_lowpart_or_truncate (op_mode,
7724 force_to_mode (XEXP (x, 0), mode, mask,
7726 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7727 x = simplify_gen_unary (code, op_mode, op0, op_mode);
7731 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7732 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7733 which is equal to STORE_FLAG_VALUE. */
7734 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7735 && GET_MODE (XEXP (x, 0)) == mode
7736 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7737 && (nonzero_bits (XEXP (x, 0), mode)
7738 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
7739 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7744 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7745 written in a narrower mode. We play it safe and do not do so. */
7748 gen_lowpart_or_truncate (GET_MODE (x),
7749 force_to_mode (XEXP (x, 1), mode,
7750 mask, next_select)));
7752 gen_lowpart_or_truncate (GET_MODE (x),
7753 force_to_mode (XEXP (x, 2), mode,
7754 mask, next_select)));
7761 /* Ensure we return a value of the proper mode. */
7762 return gen_lowpart_or_truncate (mode, x);
7765 /* Return nonzero if X is an expression that has one of two values depending on
7766 whether some other value is zero or nonzero. In that case, we return the
7767 value that is being tested, *PTRUE is set to the value if the rtx being
7768 returned has a nonzero value, and *PFALSE is set to the other alternative.
7770 If we return zero, we set *PTRUE and *PFALSE to X. */
7773 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
7775 enum machine_mode mode = GET_MODE (x);
7776 enum rtx_code code = GET_CODE (x);
7777 rtx cond0, cond1, true0, true1, false0, false1;
7778 unsigned HOST_WIDE_INT nz;
7780 /* If we are comparing a value against zero, we are done. */
7781 if ((code == NE || code == EQ)
7782 && XEXP (x, 1) == const0_rtx)
7784 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7785 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7789 /* If this is a unary operation whose operand has one of two values, apply
7790 our opcode to compute those values. */
7791 else if (UNARY_P (x)
7792 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7794 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7795 *pfalse = simplify_gen_unary (code, mode, false0,
7796 GET_MODE (XEXP (x, 0)));
7800 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7801 make can't possibly match and would suppress other optimizations. */
7802 else if (code == COMPARE)
7805 /* If this is a binary operation, see if either side has only one of two
7806 values. If either one does or if both do and they are conditional on
7807 the same value, compute the new true and false values. */
7808 else if (BINARY_P (x))
7810 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7811 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7813 if ((cond0 != 0 || cond1 != 0)
7814 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7816 /* If if_then_else_cond returned zero, then true/false are the
7817 same rtl. We must copy one of them to prevent invalid rtl
7820 true0 = copy_rtx (true0);
7821 else if (cond1 == 0)
7822 true1 = copy_rtx (true1);
7824 if (COMPARISON_P (x))
7826 *ptrue = simplify_gen_relational (code, mode, VOIDmode,
7828 *pfalse = simplify_gen_relational (code, mode, VOIDmode,
7833 *ptrue = simplify_gen_binary (code, mode, true0, true1);
7834 *pfalse = simplify_gen_binary (code, mode, false0, false1);
7837 return cond0 ? cond0 : cond1;
7840 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7841 operands is zero when the other is nonzero, and vice-versa,
7842 and STORE_FLAG_VALUE is 1 or -1. */
7844 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7845 && (code == PLUS || code == IOR || code == XOR || code == MINUS
7847 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7849 rtx op0 = XEXP (XEXP (x, 0), 1);
7850 rtx op1 = XEXP (XEXP (x, 1), 1);
7852 cond0 = XEXP (XEXP (x, 0), 0);
7853 cond1 = XEXP (XEXP (x, 1), 0);
7855 if (COMPARISON_P (cond0)
7856 && COMPARISON_P (cond1)
7857 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7858 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7859 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7860 || ((swap_condition (GET_CODE (cond0))
7861 == reversed_comparison_code (cond1, NULL))
7862 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7863 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7864 && ! side_effects_p (x))
7866 *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
7867 *pfalse = simplify_gen_binary (MULT, mode,
7869 ? simplify_gen_unary (NEG, mode,
7877 /* Similarly for MULT, AND and UMIN, except that for these the result
7879 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7880 && (code == MULT || code == AND || code == UMIN)
7881 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7883 cond0 = XEXP (XEXP (x, 0), 0);
7884 cond1 = XEXP (XEXP (x, 1), 0);
7886 if (COMPARISON_P (cond0)
7887 && COMPARISON_P (cond1)
7888 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7889 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7890 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7891 || ((swap_condition (GET_CODE (cond0))
7892 == reversed_comparison_code (cond1, NULL))
7893 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7894 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7895 && ! side_effects_p (x))
7897 *ptrue = *pfalse = const0_rtx;
7903 else if (code == IF_THEN_ELSE)
7905 /* If we have IF_THEN_ELSE already, extract the condition and
7906 canonicalize it if it is NE or EQ. */
7907 cond0 = XEXP (x, 0);
7908 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7909 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7910 return XEXP (cond0, 0);
7911 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7913 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7914 return XEXP (cond0, 0);
7920 /* If X is a SUBREG, we can narrow both the true and false values
7921 if the inner expression, if there is a condition. */
7922 else if (code == SUBREG
7923 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7926 true0 = simplify_gen_subreg (mode, true0,
7927 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7928 false0 = simplify_gen_subreg (mode, false0,
7929 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7930 if (true0 && false0)
7938 /* If X is a constant, this isn't special and will cause confusions
7939 if we treat it as such. Likewise if it is equivalent to a constant. */
7940 else if (CONSTANT_P (x)
7941 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7944 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7945 will be least confusing to the rest of the compiler. */
7946 else if (mode == BImode)
7948 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7952 /* If X is known to be either 0 or -1, those are the true and
7953 false values when testing X. */
7954 else if (x == constm1_rtx || x == const0_rtx
7955 || (mode != VOIDmode
7956 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7958 *ptrue = constm1_rtx, *pfalse = const0_rtx;
7962 /* Likewise for 0 or a single bit. */
7963 else if (SCALAR_INT_MODE_P (mode)
7964 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7965 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7967 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
7971 /* Otherwise fail; show no condition with true and false values the same. */
7972 *ptrue = *pfalse = x;
7976 /* Return the value of expression X given the fact that condition COND
7977 is known to be true when applied to REG as its first operand and VAL
7978 as its second. X is known to not be shared and so can be modified in
7981 We only handle the simplest cases, and specifically those cases that
7982 arise with IF_THEN_ELSE expressions. */
7985 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
7987 enum rtx_code code = GET_CODE (x);
7992 if (side_effects_p (x))
7995 /* If either operand of the condition is a floating point value,
7996 then we have to avoid collapsing an EQ comparison. */
7998 && rtx_equal_p (x, reg)
7999 && ! FLOAT_MODE_P (GET_MODE (x))
8000 && ! FLOAT_MODE_P (GET_MODE (val)))
8003 if (cond == UNEQ && rtx_equal_p (x, reg))
8006 /* If X is (abs REG) and we know something about REG's relationship
8007 with zero, we may be able to simplify this. */
8009 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
8012 case GE: case GT: case EQ:
8015 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
8017 GET_MODE (XEXP (x, 0)));
8022 /* The only other cases we handle are MIN, MAX, and comparisons if the
8023 operands are the same as REG and VAL. */
8025 else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
8027 if (rtx_equal_p (XEXP (x, 0), val))
8028 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
8030 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
8032 if (COMPARISON_P (x))
8034 if (comparison_dominates_p (cond, code))
8035 return const_true_rtx;
8037 code = reversed_comparison_code (x, NULL);
8039 && comparison_dominates_p (cond, code))
8044 else if (code == SMAX || code == SMIN
8045 || code == UMIN || code == UMAX)
8047 int unsignedp = (code == UMIN || code == UMAX);
8049 /* Do not reverse the condition when it is NE or EQ.
8050 This is because we cannot conclude anything about
8051 the value of 'SMAX (x, y)' when x is not equal to y,
8052 but we can when x equals y. */
8053 if ((code == SMAX || code == UMAX)
8054 && ! (cond == EQ || cond == NE))
8055 cond = reverse_condition (cond);
8060 return unsignedp ? x : XEXP (x, 1);
8062 return unsignedp ? x : XEXP (x, 0);
8064 return unsignedp ? XEXP (x, 1) : x;
8066 return unsignedp ? XEXP (x, 0) : x;
8073 else if (code == SUBREG)
8075 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
8076 rtx new_rtx, r = known_cond (SUBREG_REG (x), cond, reg, val);
8078 if (SUBREG_REG (x) != r)
8080 /* We must simplify subreg here, before we lose track of the
8081 original inner_mode. */
8082 new_rtx = simplify_subreg (GET_MODE (x), r,
8083 inner_mode, SUBREG_BYTE (x));
8087 SUBST (SUBREG_REG (x), r);
8092 /* We don't have to handle SIGN_EXTEND here, because even in the
8093 case of replacing something with a modeless CONST_INT, a
8094 CONST_INT is already (supposed to be) a valid sign extension for
8095 its narrower mode, which implies it's already properly
8096 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
8097 story is different. */
8098 else if (code == ZERO_EXTEND)
8100 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
8101 rtx new_rtx, r = known_cond (XEXP (x, 0), cond, reg, val);
8103 if (XEXP (x, 0) != r)
8105 /* We must simplify the zero_extend here, before we lose
8106 track of the original inner_mode. */
8107 new_rtx = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
8112 SUBST (XEXP (x, 0), r);
8118 fmt = GET_RTX_FORMAT (code);
8119 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8122 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
8123 else if (fmt[i] == 'E')
8124 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8125 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
8132 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8133 assignment as a field assignment. */
8136 rtx_equal_for_field_assignment_p (rtx x, rtx y)
8138 if (x == y || rtx_equal_p (x, y))
8141 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
8144 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8145 Note that all SUBREGs of MEM are paradoxical; otherwise they
8146 would have been rewritten. */
8147 if (MEM_P (x) && GET_CODE (y) == SUBREG
8148 && MEM_P (SUBREG_REG (y))
8149 && rtx_equal_p (SUBREG_REG (y),
8150 gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
8153 if (MEM_P (y) && GET_CODE (x) == SUBREG
8154 && MEM_P (SUBREG_REG (x))
8155 && rtx_equal_p (SUBREG_REG (x),
8156 gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
8159 /* We used to see if get_last_value of X and Y were the same but that's
8160 not correct. In one direction, we'll cause the assignment to have
8161 the wrong destination and in the case, we'll import a register into this
8162 insn that might have already have been dead. So fail if none of the
8163 above cases are true. */
8167 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8168 Return that assignment if so.
8170 We only handle the most common cases. */
8173 make_field_assignment (rtx x)
8175 rtx dest = SET_DEST (x);
8176 rtx src = SET_SRC (x);
8181 unsigned HOST_WIDE_INT len;
8183 enum machine_mode mode;
8185 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
8186 a clear of a one-bit field. We will have changed it to
8187 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
8190 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
8191 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
8192 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
8193 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8195 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8198 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8202 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
8203 && subreg_lowpart_p (XEXP (src, 0))
8204 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
8205 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
8206 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
8207 && GET_CODE (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == CONST_INT
8208 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
8209 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8211 assign = make_extraction (VOIDmode, dest, 0,
8212 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
8215 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8219 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
8221 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
8222 && XEXP (XEXP (src, 0), 0) == const1_rtx
8223 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8225 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8228 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
8232 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
8233 SRC is an AND with all bits of that field set, then we can discard
8235 if (GET_CODE (dest) == ZERO_EXTRACT
8236 && GET_CODE (XEXP (dest, 1)) == CONST_INT
8237 && GET_CODE (src) == AND
8238 && GET_CODE (XEXP (src, 1)) == CONST_INT)
8240 HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
8241 unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
8242 unsigned HOST_WIDE_INT ze_mask;
8244 if (width >= HOST_BITS_PER_WIDE_INT)
8247 ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
8249 /* Complete overlap. We can remove the source AND. */
8250 if ((and_mask & ze_mask) == ze_mask)
8251 return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
8253 /* Partial overlap. We can reduce the source AND. */
8254 if ((and_mask & ze_mask) != and_mask)
8256 mode = GET_MODE (src);
8257 src = gen_rtx_AND (mode, XEXP (src, 0),
8258 gen_int_mode (and_mask & ze_mask, mode));
8259 return gen_rtx_SET (VOIDmode, dest, src);
8263 /* The other case we handle is assignments into a constant-position
8264 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
8265 a mask that has all one bits except for a group of zero bits and
8266 OTHER is known to have zeros where C1 has ones, this is such an
8267 assignment. Compute the position and length from C1. Shift OTHER
8268 to the appropriate position, force it to the required mode, and
8269 make the extraction. Check for the AND in both operands. */
8271 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
8274 rhs = expand_compound_operation (XEXP (src, 0));
8275 lhs = expand_compound_operation (XEXP (src, 1));
8277 if (GET_CODE (rhs) == AND
8278 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
8279 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
8280 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
8281 else if (GET_CODE (lhs) == AND
8282 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
8283 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
8284 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
8288 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
8289 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
8290 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
8291 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
8294 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
8298 /* The mode to use for the source is the mode of the assignment, or of
8299 what is inside a possible STRICT_LOW_PART. */
8300 mode = (GET_CODE (assign) == STRICT_LOW_PART
8301 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
8303 /* Shift OTHER right POS places and make it the source, restricting it
8304 to the proper length and mode. */
8306 src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
8310 src = force_to_mode (src, mode,
8311 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
8312 ? ~(unsigned HOST_WIDE_INT) 0
8313 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
8316 /* If SRC is masked by an AND that does not make a difference in
8317 the value being stored, strip it. */
8318 if (GET_CODE (assign) == ZERO_EXTRACT
8319 && GET_CODE (XEXP (assign, 1)) == CONST_INT
8320 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
8321 && GET_CODE (src) == AND
8322 && GET_CODE (XEXP (src, 1)) == CONST_INT
8323 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
8324 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
8325 src = XEXP (src, 0);
8327 return gen_rtx_SET (VOIDmode, assign, src);
8330 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
8334 apply_distributive_law (rtx x)
8336 enum rtx_code code = GET_CODE (x);
8337 enum rtx_code inner_code;
8338 rtx lhs, rhs, other;
8341 /* Distributivity is not true for floating point as it can change the
8342 value. So we don't do it unless -funsafe-math-optimizations. */
8343 if (FLOAT_MODE_P (GET_MODE (x))
8344 && ! flag_unsafe_math_optimizations)
8347 /* The outer operation can only be one of the following: */
8348 if (code != IOR && code != AND && code != XOR
8349 && code != PLUS && code != MINUS)
8355 /* If either operand is a primitive we can't do anything, so get out
8357 if (OBJECT_P (lhs) || OBJECT_P (rhs))
8360 lhs = expand_compound_operation (lhs);
8361 rhs = expand_compound_operation (rhs);
8362 inner_code = GET_CODE (lhs);
8363 if (inner_code != GET_CODE (rhs))
8366 /* See if the inner and outer operations distribute. */
8373 /* These all distribute except over PLUS. */
8374 if (code == PLUS || code == MINUS)
8379 if (code != PLUS && code != MINUS)
8384 /* This is also a multiply, so it distributes over everything. */
8388 /* Non-paradoxical SUBREGs distributes over all operations,
8389 provided the inner modes and byte offsets are the same, this
8390 is an extraction of a low-order part, we don't convert an fp
8391 operation to int or vice versa, this is not a vector mode,
8392 and we would not be converting a single-word operation into a
8393 multi-word operation. The latter test is not required, but
8394 it prevents generating unneeded multi-word operations. Some
8395 of the previous tests are redundant given the latter test,
8396 but are retained because they are required for correctness.
8398 We produce the result slightly differently in this case. */
8400 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
8401 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
8402 || ! subreg_lowpart_p (lhs)
8403 || (GET_MODE_CLASS (GET_MODE (lhs))
8404 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
8405 || (GET_MODE_SIZE (GET_MODE (lhs))
8406 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
8407 || VECTOR_MODE_P (GET_MODE (lhs))
8408 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD
8409 /* Result might need to be truncated. Don't change mode if
8410 explicit truncation is needed. */
8411 || !TRULY_NOOP_TRUNCATION
8412 (GET_MODE_BITSIZE (GET_MODE (x)),
8413 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (lhs)))))
8416 tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
8417 SUBREG_REG (lhs), SUBREG_REG (rhs));
8418 return gen_lowpart (GET_MODE (x), tem);
8424 /* Set LHS and RHS to the inner operands (A and B in the example
8425 above) and set OTHER to the common operand (C in the example).
8426 There is only one way to do this unless the inner operation is
8428 if (COMMUTATIVE_ARITH_P (lhs)
8429 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
8430 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
8431 else if (COMMUTATIVE_ARITH_P (lhs)
8432 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
8433 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
8434 else if (COMMUTATIVE_ARITH_P (lhs)
8435 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
8436 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
8437 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
8438 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
8442 /* Form the new inner operation, seeing if it simplifies first. */
8443 tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
8445 /* There is one exception to the general way of distributing:
8446 (a | c) ^ (b | c) -> (a ^ b) & ~c */
8447 if (code == XOR && inner_code == IOR)
8450 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
8453 /* We may be able to continuing distributing the result, so call
8454 ourselves recursively on the inner operation before forming the
8455 outer operation, which we return. */
8456 return simplify_gen_binary (inner_code, GET_MODE (x),
8457 apply_distributive_law (tem), other);
8460 /* See if X is of the form (* (+ A B) C), and if so convert to
8461 (+ (* A C) (* B C)) and try to simplify.
8463 Most of the time, this results in no change. However, if some of
8464 the operands are the same or inverses of each other, simplifications
8467 For example, (and (ior A B) (not B)) can occur as the result of
8468 expanding a bit field assignment. When we apply the distributive
8469 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
8470 which then simplifies to (and (A (not B))).
8472 Note that no checks happen on the validity of applying the inverse
8473 distributive law. This is pointless since we can do it in the
8474 few places where this routine is called.
8476 N is the index of the term that is decomposed (the arithmetic operation,
8477 i.e. (+ A B) in the first example above). !N is the index of the term that
8478 is distributed, i.e. of C in the first example above. */
8480 distribute_and_simplify_rtx (rtx x, int n)
8482 enum machine_mode mode;
8483 enum rtx_code outer_code, inner_code;
8484 rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
8486 decomposed = XEXP (x, n);
8487 if (!ARITHMETIC_P (decomposed))
8490 mode = GET_MODE (x);
8491 outer_code = GET_CODE (x);
8492 distributed = XEXP (x, !n);
8494 inner_code = GET_CODE (decomposed);
8495 inner_op0 = XEXP (decomposed, 0);
8496 inner_op1 = XEXP (decomposed, 1);
8498 /* Special case (and (xor B C) (not A)), which is equivalent to
8499 (xor (ior A B) (ior A C)) */
8500 if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
8502 distributed = XEXP (distributed, 0);
8508 /* Distribute the second term. */
8509 new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
8510 new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
8514 /* Distribute the first term. */
8515 new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
8516 new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
8519 tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
8521 if (GET_CODE (tmp) != outer_code
8522 && rtx_cost (tmp, SET) < rtx_cost (x, SET))
8528 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
8529 in MODE. Return an equivalent form, if different from (and VAROP
8530 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
8533 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
8534 unsigned HOST_WIDE_INT constop)
8536 unsigned HOST_WIDE_INT nonzero;
8537 unsigned HOST_WIDE_INT orig_constop;
8542 orig_constop = constop;
8543 if (GET_CODE (varop) == CLOBBER)
8546 /* Simplify VAROP knowing that we will be only looking at some of the
8549 Note by passing in CONSTOP, we guarantee that the bits not set in
8550 CONSTOP are not significant and will never be examined. We must
8551 ensure that is the case by explicitly masking out those bits
8552 before returning. */
8553 varop = force_to_mode (varop, mode, constop, 0);
8555 /* If VAROP is a CLOBBER, we will fail so return it. */
8556 if (GET_CODE (varop) == CLOBBER)
8559 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8560 to VAROP and return the new constant. */
8561 if (GET_CODE (varop) == CONST_INT)
8562 return gen_int_mode (INTVAL (varop) & constop, mode);
8564 /* See what bits may be nonzero in VAROP. Unlike the general case of
8565 a call to nonzero_bits, here we don't care about bits outside
8568 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
8570 /* Turn off all bits in the constant that are known to already be zero.
8571 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8572 which is tested below. */
8576 /* If we don't have any bits left, return zero. */
8580 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8581 a power of two, we can replace this with an ASHIFT. */
8582 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
8583 && (i = exact_log2 (constop)) >= 0)
8584 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
8586 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8587 or XOR, then try to apply the distributive law. This may eliminate
8588 operations if either branch can be simplified because of the AND.
8589 It may also make some cases more complex, but those cases probably
8590 won't match a pattern either with or without this. */
8592 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
8596 apply_distributive_law
8597 (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
8598 simplify_and_const_int (NULL_RTX,
8602 simplify_and_const_int (NULL_RTX,
8607 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
8608 the AND and see if one of the operands simplifies to zero. If so, we
8609 may eliminate it. */
8611 if (GET_CODE (varop) == PLUS
8612 && exact_log2 (constop + 1) >= 0)
8616 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
8617 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
8618 if (o0 == const0_rtx)
8620 if (o1 == const0_rtx)
8624 /* Make a SUBREG if necessary. If we can't make it, fail. */
8625 varop = gen_lowpart (mode, varop);
8626 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
8629 /* If we are only masking insignificant bits, return VAROP. */
8630 if (constop == nonzero)
8633 if (varop == orig_varop && constop == orig_constop)
8636 /* Otherwise, return an AND. */
8637 return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
8641 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8644 Return an equivalent form, if different from X. Otherwise, return X. If
8645 X is zero, we are to always construct the equivalent form. */
8648 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
8649 unsigned HOST_WIDE_INT constop)
8651 rtx tem = simplify_and_const_int_1 (mode, varop, constop);
8656 x = simplify_gen_binary (AND, GET_MODE (varop), varop,
8657 gen_int_mode (constop, mode));
8658 if (GET_MODE (x) != mode)
8659 x = gen_lowpart (mode, x);
8663 /* Given a REG, X, compute which bits in X can be nonzero.
8664 We don't care about bits outside of those defined in MODE.
8666 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8667 a shift, AND, or zero_extract, we can do better. */
8670 reg_nonzero_bits_for_combine (const_rtx x, enum machine_mode mode,
8671 const_rtx known_x ATTRIBUTE_UNUSED,
8672 enum machine_mode known_mode ATTRIBUTE_UNUSED,
8673 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
8674 unsigned HOST_WIDE_INT *nonzero)
8679 /* If X is a register whose nonzero bits value is current, use it.
8680 Otherwise, if X is a register whose value we can find, use that
8681 value. Otherwise, use the previously-computed global nonzero bits
8682 for this register. */
8684 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
8685 if (rsp->last_set_value != 0
8686 && (rsp->last_set_mode == mode
8687 || (GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT
8688 && GET_MODE_CLASS (mode) == MODE_INT))
8689 && ((rsp->last_set_label >= label_tick_ebb_start
8690 && rsp->last_set_label < label_tick)
8691 || (rsp->last_set_label == label_tick
8692 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
8693 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8694 && REG_N_SETS (REGNO (x)) == 1
8696 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
8698 *nonzero &= rsp->last_set_nonzero_bits;
8702 tem = get_last_value (x);
8706 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8707 /* If X is narrower than MODE and TEM is a non-negative
8708 constant that would appear negative in the mode of X,
8709 sign-extend it for use in reg_nonzero_bits because some
8710 machines (maybe most) will actually do the sign-extension
8711 and this is the conservative approach.
8713 ??? For 2.5, try to tighten up the MD files in this regard
8714 instead of this kludge. */
8716 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)
8717 && GET_CODE (tem) == CONST_INT
8719 && 0 != (INTVAL (tem)
8720 & ((HOST_WIDE_INT) 1
8721 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8722 tem = GEN_INT (INTVAL (tem)
8723 | ((HOST_WIDE_INT) (-1)
8724 << GET_MODE_BITSIZE (GET_MODE (x))));
8728 else if (nonzero_sign_valid && rsp->nonzero_bits)
8730 unsigned HOST_WIDE_INT mask = rsp->nonzero_bits;
8732 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode))
8733 /* We don't know anything about the upper bits. */
8734 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
8741 /* Return the number of bits at the high-order end of X that are known to
8742 be equal to the sign bit. X will be used in mode MODE; if MODE is
8743 VOIDmode, X will be used in its own mode. The returned value will always
8744 be between 1 and the number of bits in MODE. */
8747 reg_num_sign_bit_copies_for_combine (const_rtx x, enum machine_mode mode,
8748 const_rtx known_x ATTRIBUTE_UNUSED,
8749 enum machine_mode known_mode
8751 unsigned int known_ret ATTRIBUTE_UNUSED,
8752 unsigned int *result)
8757 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
8758 if (rsp->last_set_value != 0
8759 && rsp->last_set_mode == mode
8760 && ((rsp->last_set_label >= label_tick_ebb_start
8761 && rsp->last_set_label < label_tick)
8762 || (rsp->last_set_label == label_tick
8763 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
8764 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8765 && REG_N_SETS (REGNO (x)) == 1
8767 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
8769 *result = rsp->last_set_sign_bit_copies;
8773 tem = get_last_value (x);
8777 if (nonzero_sign_valid && rsp->sign_bit_copies != 0
8778 && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode))
8779 *result = rsp->sign_bit_copies;
8784 /* Return the number of "extended" bits there are in X, when interpreted
8785 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8786 unsigned quantities, this is the number of high-order zero bits.
8787 For signed quantities, this is the number of copies of the sign bit
8788 minus 1. In both case, this function returns the number of "spare"
8789 bits. For example, if two quantities for which this function returns
8790 at least 1 are added, the addition is known not to overflow.
8792 This function will always return 0 unless called during combine, which
8793 implies that it must be called from a define_split. */
8796 extended_count (const_rtx x, enum machine_mode mode, int unsignedp)
8798 if (nonzero_sign_valid == 0)
8802 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8803 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
8804 - floor_log2 (nonzero_bits (x, mode)))
8806 : num_sign_bit_copies (x, mode) - 1);
8809 /* This function is called from `simplify_shift_const' to merge two
8810 outer operations. Specifically, we have already found that we need
8811 to perform operation *POP0 with constant *PCONST0 at the outermost
8812 position. We would now like to also perform OP1 with constant CONST1
8813 (with *POP0 being done last).
8815 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8816 the resulting operation. *PCOMP_P is set to 1 if we would need to
8817 complement the innermost operand, otherwise it is unchanged.
8819 MODE is the mode in which the operation will be done. No bits outside
8820 the width of this mode matter. It is assumed that the width of this mode
8821 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8823 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
8824 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8825 result is simply *PCONST0.
8827 If the resulting operation cannot be expressed as one operation, we
8828 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8831 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
8833 enum rtx_code op0 = *pop0;
8834 HOST_WIDE_INT const0 = *pconst0;
8836 const0 &= GET_MODE_MASK (mode);
8837 const1 &= GET_MODE_MASK (mode);
8839 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8843 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
8846 if (op1 == UNKNOWN || op0 == SET)
8849 else if (op0 == UNKNOWN)
8850 op0 = op1, const0 = const1;
8852 else if (op0 == op1)
8876 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8877 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8880 /* If the two constants aren't the same, we can't do anything. The
8881 remaining six cases can all be done. */
8882 else if (const0 != const1)
8890 /* (a & b) | b == b */
8892 else /* op1 == XOR */
8893 /* (a ^ b) | b == a | b */
8899 /* (a & b) ^ b == (~a) & b */
8900 op0 = AND, *pcomp_p = 1;
8901 else /* op1 == IOR */
8902 /* (a | b) ^ b == a & ~b */
8903 op0 = AND, const0 = ~const0;
8908 /* (a | b) & b == b */
8910 else /* op1 == XOR */
8911 /* (a ^ b) & b) == (~a) & b */
8918 /* Check for NO-OP cases. */
8919 const0 &= GET_MODE_MASK (mode);
8921 && (op0 == IOR || op0 == XOR || op0 == PLUS))
8923 else if (const0 == 0 && op0 == AND)
8925 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8929 /* ??? Slightly redundant with the above mask, but not entirely.
8930 Moving this above means we'd have to sign-extend the mode mask
8931 for the final test. */
8932 const0 = trunc_int_for_mode (const0, mode);
8940 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8941 The result of the shift is RESULT_MODE. Return NULL_RTX if we cannot
8942 simplify it. Otherwise, return a simplified value.
8944 The shift is normally computed in the widest mode we find in VAROP, as
8945 long as it isn't a different number of words than RESULT_MODE. Exceptions
8946 are ASHIFTRT and ROTATE, which are always done in their original mode. */
8949 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
8950 rtx varop, int orig_count)
8952 enum rtx_code orig_code = code;
8953 rtx orig_varop = varop;
8955 enum machine_mode mode = result_mode;
8956 enum machine_mode shift_mode, tmode;
8957 unsigned int mode_words
8958 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8959 /* We form (outer_op (code varop count) (outer_const)). */
8960 enum rtx_code outer_op = UNKNOWN;
8961 HOST_WIDE_INT outer_const = 0;
8962 int complement_p = 0;
8965 /* Make sure and truncate the "natural" shift on the way in. We don't
8966 want to do this inside the loop as it makes it more difficult to
8968 if (SHIFT_COUNT_TRUNCATED)
8969 orig_count &= GET_MODE_BITSIZE (mode) - 1;
8971 /* If we were given an invalid count, don't do anything except exactly
8972 what was requested. */
8974 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
8979 /* Unless one of the branches of the `if' in this loop does a `continue',
8980 we will `break' the loop after the `if'. */
8984 /* If we have an operand of (clobber (const_int 0)), fail. */
8985 if (GET_CODE (varop) == CLOBBER)
8988 /* If we discovered we had to complement VAROP, leave. Making a NOT
8989 here would cause an infinite loop. */
8993 /* Convert ROTATERT to ROTATE. */
8994 if (code == ROTATERT)
8996 unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
8998 if (VECTOR_MODE_P (result_mode))
8999 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
9001 count = bitsize - count;
9004 /* We need to determine what mode we will do the shift in. If the
9005 shift is a right shift or a ROTATE, we must always do it in the mode
9006 it was originally done in. Otherwise, we can do it in MODE, the
9007 widest mode encountered. */
9009 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9010 ? result_mode : mode);
9012 /* Handle cases where the count is greater than the size of the mode
9013 minus 1. For ASHIFT, use the size minus one as the count (this can
9014 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9015 take the count modulo the size. For other shifts, the result is
9018 Since these shifts are being produced by the compiler by combining
9019 multiple operations, each of which are defined, we know what the
9020 result is supposed to be. */
9022 if (count > (GET_MODE_BITSIZE (shift_mode) - 1))
9024 if (code == ASHIFTRT)
9025 count = GET_MODE_BITSIZE (shift_mode) - 1;
9026 else if (code == ROTATE || code == ROTATERT)
9027 count %= GET_MODE_BITSIZE (shift_mode);
9030 /* We can't simply return zero because there may be an
9038 /* An arithmetic right shift of a quantity known to be -1 or 0
9040 if (code == ASHIFTRT
9041 && (num_sign_bit_copies (varop, shift_mode)
9042 == GET_MODE_BITSIZE (shift_mode)))
9048 /* If we are doing an arithmetic right shift and discarding all but
9049 the sign bit copies, this is equivalent to doing a shift by the
9050 bitsize minus one. Convert it into that shift because it will often
9051 allow other simplifications. */
9053 if (code == ASHIFTRT
9054 && (count + num_sign_bit_copies (varop, shift_mode)
9055 >= GET_MODE_BITSIZE (shift_mode)))
9056 count = GET_MODE_BITSIZE (shift_mode) - 1;
9058 /* We simplify the tests below and elsewhere by converting
9059 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9060 `make_compound_operation' will convert it to an ASHIFTRT for
9061 those machines (such as VAX) that don't have an LSHIFTRT. */
9062 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9064 && ((nonzero_bits (varop, shift_mode)
9065 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
9069 if (((code == LSHIFTRT
9070 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9071 && !(nonzero_bits (varop, shift_mode) >> count))
9073 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9074 && !((nonzero_bits (varop, shift_mode) << count)
9075 & GET_MODE_MASK (shift_mode))))
9076 && !side_effects_p (varop))
9079 switch (GET_CODE (varop))
9085 new_rtx = expand_compound_operation (varop);
9086 if (new_rtx != varop)
9094 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9095 minus the width of a smaller mode, we can do this with a
9096 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9097 if ((code == ASHIFTRT || code == LSHIFTRT)
9098 && ! mode_dependent_address_p (XEXP (varop, 0))
9099 && ! MEM_VOLATILE_P (varop)
9100 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9101 MODE_INT, 1)) != BLKmode)
9103 new_rtx = adjust_address_nv (varop, tmode,
9104 BYTES_BIG_ENDIAN ? 0
9105 : count / BITS_PER_UNIT);
9107 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9108 : ZERO_EXTEND, mode, new_rtx);
9115 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9116 the same number of words as what we've seen so far. Then store
9117 the widest mode in MODE. */
9118 if (subreg_lowpart_p (varop)
9119 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9120 > GET_MODE_SIZE (GET_MODE (varop)))
9121 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9122 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9125 varop = SUBREG_REG (varop);
9126 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9127 mode = GET_MODE (varop);
9133 /* Some machines use MULT instead of ASHIFT because MULT
9134 is cheaper. But it is still better on those machines to
9135 merge two shifts into one. */
9136 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9137 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9140 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
9142 GEN_INT (exact_log2 (
9143 INTVAL (XEXP (varop, 1)))));
9149 /* Similar, for when divides are cheaper. */
9150 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9151 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9154 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
9156 GEN_INT (exact_log2 (
9157 INTVAL (XEXP (varop, 1)))));
9163 /* If we are extracting just the sign bit of an arithmetic
9164 right shift, that shift is not needed. However, the sign
9165 bit of a wider mode may be different from what would be
9166 interpreted as the sign bit in a narrower mode, so, if
9167 the result is narrower, don't discard the shift. */
9168 if (code == LSHIFTRT
9169 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9170 && (GET_MODE_BITSIZE (result_mode)
9171 >= GET_MODE_BITSIZE (GET_MODE (varop))))
9173 varop = XEXP (varop, 0);
9177 /* ... fall through ... */
9182 /* Here we have two nested shifts. The result is usually the
9183 AND of a new shift with a mask. We compute the result below. */
9184 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9185 && INTVAL (XEXP (varop, 1)) >= 0
9186 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
9187 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9188 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9189 && !VECTOR_MODE_P (result_mode))
9191 enum rtx_code first_code = GET_CODE (varop);
9192 unsigned int first_count = INTVAL (XEXP (varop, 1));
9193 unsigned HOST_WIDE_INT mask;
9196 /* We have one common special case. We can't do any merging if
9197 the inner code is an ASHIFTRT of a smaller mode. However, if
9198 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9199 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9200 we can convert it to
9201 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9202 This simplifies certain SIGN_EXTEND operations. */
9203 if (code == ASHIFT && first_code == ASHIFTRT
9204 && count == (GET_MODE_BITSIZE (result_mode)
9205 - GET_MODE_BITSIZE (GET_MODE (varop))))
9207 /* C3 has the low-order C1 bits zero. */
9209 mask = (GET_MODE_MASK (mode)
9210 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
9212 varop = simplify_and_const_int (NULL_RTX, result_mode,
9213 XEXP (varop, 0), mask);
9214 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
9216 count = first_count;
9221 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9222 than C1 high-order bits equal to the sign bit, we can convert
9223 this to either an ASHIFT or an ASHIFTRT depending on the
9226 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9228 if (code == ASHIFTRT && first_code == ASHIFT
9229 && GET_MODE (varop) == shift_mode
9230 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
9233 varop = XEXP (varop, 0);
9234 count -= first_count;
9244 /* There are some cases we can't do. If CODE is ASHIFTRT,
9245 we can only do this if FIRST_CODE is also ASHIFTRT.
9247 We can't do the case when CODE is ROTATE and FIRST_CODE is
9250 If the mode of this shift is not the mode of the outer shift,
9251 we can't do this if either shift is a right shift or ROTATE.
9253 Finally, we can't do any of these if the mode is too wide
9254 unless the codes are the same.
9256 Handle the case where the shift codes are the same
9259 if (code == first_code)
9261 if (GET_MODE (varop) != result_mode
9262 && (code == ASHIFTRT || code == LSHIFTRT
9266 count += first_count;
9267 varop = XEXP (varop, 0);
9271 if (code == ASHIFTRT
9272 || (code == ROTATE && first_code == ASHIFTRT)
9273 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
9274 || (GET_MODE (varop) != result_mode
9275 && (first_code == ASHIFTRT || first_code == LSHIFTRT
9276 || first_code == ROTATE
9277 || code == ROTATE)))
9280 /* To compute the mask to apply after the shift, shift the
9281 nonzero bits of the inner shift the same way the
9282 outer shift will. */
9284 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
9287 = simplify_const_binary_operation (code, result_mode, mask_rtx,
9290 /* Give up if we can't compute an outer operation to use. */
9292 || GET_CODE (mask_rtx) != CONST_INT
9293 || ! merge_outer_ops (&outer_op, &outer_const, AND,
9295 result_mode, &complement_p))
9298 /* If the shifts are in the same direction, we add the
9299 counts. Otherwise, we subtract them. */
9300 if ((code == ASHIFTRT || code == LSHIFTRT)
9301 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
9302 count += first_count;
9304 count -= first_count;
9306 /* If COUNT is positive, the new shift is usually CODE,
9307 except for the two exceptions below, in which case it is
9308 FIRST_CODE. If the count is negative, FIRST_CODE should
9311 && ((first_code == ROTATE && code == ASHIFT)
9312 || (first_code == ASHIFTRT && code == LSHIFTRT)))
9315 code = first_code, count = -count;
9317 varop = XEXP (varop, 0);
9321 /* If we have (A << B << C) for any shift, we can convert this to
9322 (A << C << B). This wins if A is a constant. Only try this if
9323 B is not a constant. */
9325 else if (GET_CODE (varop) == code
9326 && GET_CODE (XEXP (varop, 0)) == CONST_INT
9327 && GET_CODE (XEXP (varop, 1)) != CONST_INT)
9329 rtx new_rtx = simplify_const_binary_operation (code, mode,
9332 varop = gen_rtx_fmt_ee (code, mode, new_rtx, XEXP (varop, 1));
9339 if (VECTOR_MODE_P (mode))
9342 /* Make this fit the case below. */
9343 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
9344 GEN_INT (GET_MODE_MASK (mode)));
9350 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9351 with C the size of VAROP - 1 and the shift is logical if
9352 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9353 we have an (le X 0) operation. If we have an arithmetic shift
9354 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9355 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9357 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9358 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9359 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9360 && (code == LSHIFTRT || code == ASHIFTRT)
9361 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9362 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9365 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
9368 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9369 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9374 /* If we have (shift (logical)), move the logical to the outside
9375 to allow it to possibly combine with another logical and the
9376 shift to combine with another shift. This also canonicalizes to
9377 what a ZERO_EXTRACT looks like. Also, some machines have
9378 (and (shift)) insns. */
9380 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9381 /* We can't do this if we have (ashiftrt (xor)) and the
9382 constant has its sign bit set in shift_mode. */
9383 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
9384 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
9386 && (new_rtx = simplify_const_binary_operation (code, result_mode,
9388 GEN_INT (count))) != 0
9389 && GET_CODE (new_rtx) == CONST_INT
9390 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9391 INTVAL (new_rtx), result_mode, &complement_p))
9393 varop = XEXP (varop, 0);
9397 /* If we can't do that, try to simplify the shift in each arm of the
9398 logical expression, make a new logical expression, and apply
9399 the inverse distributive law. This also can't be done
9400 for some (ashiftrt (xor)). */
9401 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9402 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
9403 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
9406 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9407 XEXP (varop, 0), count);
9408 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9409 XEXP (varop, 1), count);
9411 varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
9413 varop = apply_distributive_law (varop);
9421 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9422 says that the sign bit can be tested, FOO has mode MODE, C is
9423 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9424 that may be nonzero. */
9425 if (code == LSHIFTRT
9426 && XEXP (varop, 1) == const0_rtx
9427 && GET_MODE (XEXP (varop, 0)) == result_mode
9428 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9429 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9430 && STORE_FLAG_VALUE == -1
9431 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9432 && merge_outer_ops (&outer_op, &outer_const, XOR,
9433 (HOST_WIDE_INT) 1, result_mode,
9436 varop = XEXP (varop, 0);
9443 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9444 than the number of bits in the mode is equivalent to A. */
9445 if (code == LSHIFTRT
9446 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9447 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9449 varop = XEXP (varop, 0);
9454 /* NEG commutes with ASHIFT since it is multiplication. Move the
9455 NEG outside to allow shifts to combine. */
9457 && merge_outer_ops (&outer_op, &outer_const, NEG,
9458 (HOST_WIDE_INT) 0, result_mode,
9461 varop = XEXP (varop, 0);
9467 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9468 is one less than the number of bits in the mode is
9469 equivalent to (xor A 1). */
9470 if (code == LSHIFTRT
9471 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9472 && XEXP (varop, 1) == constm1_rtx
9473 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9474 && merge_outer_ops (&outer_op, &outer_const, XOR,
9475 (HOST_WIDE_INT) 1, result_mode,
9479 varop = XEXP (varop, 0);
9483 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9484 that might be nonzero in BAR are those being shifted out and those
9485 bits are known zero in FOO, we can replace the PLUS with FOO.
9486 Similarly in the other operand order. This code occurs when
9487 we are computing the size of a variable-size array. */
9489 if ((code == ASHIFTRT || code == LSHIFTRT)
9490 && count < HOST_BITS_PER_WIDE_INT
9491 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9492 && (nonzero_bits (XEXP (varop, 1), result_mode)
9493 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9495 varop = XEXP (varop, 0);
9498 else if ((code == ASHIFTRT || code == LSHIFTRT)
9499 && count < HOST_BITS_PER_WIDE_INT
9500 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9501 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9503 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9504 & nonzero_bits (XEXP (varop, 1),
9507 varop = XEXP (varop, 1);
9511 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9513 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9514 && (new_rtx = simplify_const_binary_operation (ASHIFT, result_mode,
9516 GEN_INT (count))) != 0
9517 && GET_CODE (new_rtx) == CONST_INT
9518 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9519 INTVAL (new_rtx), result_mode, &complement_p))
9521 varop = XEXP (varop, 0);
9525 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
9526 signbit', and attempt to change the PLUS to an XOR and move it to
9527 the outer operation as is done above in the AND/IOR/XOR case
9528 leg for shift(logical). See details in logical handling above
9529 for reasoning in doing so. */
9530 if (code == LSHIFTRT
9531 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9532 && mode_signbit_p (result_mode, XEXP (varop, 1))
9533 && (new_rtx = simplify_const_binary_operation (code, result_mode,
9535 GEN_INT (count))) != 0
9536 && GET_CODE (new_rtx) == CONST_INT
9537 && merge_outer_ops (&outer_op, &outer_const, XOR,
9538 INTVAL (new_rtx), result_mode, &complement_p))
9540 varop = XEXP (varop, 0);
9547 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9548 with C the size of VAROP - 1 and the shift is logical if
9549 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9550 we have a (gt X 0) operation. If the shift is arithmetic with
9551 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9552 we have a (neg (gt X 0)) operation. */
9554 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9555 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9556 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9557 && (code == LSHIFTRT || code == ASHIFTRT)
9558 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9559 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
9560 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9563 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9566 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9567 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9574 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9575 if the truncate does not affect the value. */
9576 if (code == LSHIFTRT
9577 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9578 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9579 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9580 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9581 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9583 rtx varop_inner = XEXP (varop, 0);
9586 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9587 XEXP (varop_inner, 0),
9589 (count + INTVAL (XEXP (varop_inner, 1))));
9590 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9603 /* We need to determine what mode to do the shift in. If the shift is
9604 a right shift or ROTATE, we must always do it in the mode it was
9605 originally done in. Otherwise, we can do it in MODE, the widest mode
9606 encountered. The code we care about is that of the shift that will
9607 actually be done, not the shift that was originally requested. */
9609 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9610 ? result_mode : mode);
9612 /* We have now finished analyzing the shift. The result should be
9613 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9614 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
9615 to the result of the shift. OUTER_CONST is the relevant constant,
9616 but we must turn off all bits turned off in the shift. */
9618 if (outer_op == UNKNOWN
9619 && orig_code == code && orig_count == count
9620 && varop == orig_varop
9621 && shift_mode == GET_MODE (varop))
9624 /* Make a SUBREG if necessary. If we can't make it, fail. */
9625 varop = gen_lowpart (shift_mode, varop);
9626 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
9629 /* If we have an outer operation and we just made a shift, it is
9630 possible that we could have simplified the shift were it not
9631 for the outer operation. So try to do the simplification
9634 if (outer_op != UNKNOWN)
9635 x = simplify_shift_const_1 (code, shift_mode, varop, count);
9640 x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
9642 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9643 turn off all the bits that the shift would have turned off. */
9644 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9645 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9646 GET_MODE_MASK (result_mode) >> orig_count);
9648 /* Do the remainder of the processing in RESULT_MODE. */
9649 x = gen_lowpart_or_truncate (result_mode, x);
9651 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9654 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
9656 if (outer_op != UNKNOWN)
9658 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9659 outer_const = trunc_int_for_mode (outer_const, result_mode);
9661 if (outer_op == AND)
9662 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9663 else if (outer_op == SET)
9665 /* This means that we have determined that the result is
9666 equivalent to a constant. This should be rare. */
9667 if (!side_effects_p (x))
9668 x = GEN_INT (outer_const);
9670 else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
9671 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
9673 x = simplify_gen_binary (outer_op, result_mode, x,
9674 GEN_INT (outer_const));
9680 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9681 The result of the shift is RESULT_MODE. If we cannot simplify it,
9682 return X or, if it is NULL, synthesize the expression with
9683 simplify_gen_binary. Otherwise, return a simplified value.
9685 The shift is normally computed in the widest mode we find in VAROP, as
9686 long as it isn't a different number of words than RESULT_MODE. Exceptions
9687 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9690 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
9691 rtx varop, int count)
9693 rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
9698 x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
9699 if (GET_MODE (x) != result_mode)
9700 x = gen_lowpart (result_mode, x);
9705 /* Like recog, but we receive the address of a pointer to a new pattern.
9706 We try to match the rtx that the pointer points to.
9707 If that fails, we may try to modify or replace the pattern,
9708 storing the replacement into the same pointer object.
9710 Modifications include deletion or addition of CLOBBERs.
9712 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9713 the CLOBBERs are placed.
9715 The value is the final insn code from the pattern ultimately matched,
9719 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
9722 int insn_code_number;
9723 int num_clobbers_to_add = 0;
9726 rtx old_notes, old_pat;
9728 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9729 we use to indicate that something didn't match. If we find such a
9730 thing, force rejection. */
9731 if (GET_CODE (pat) == PARALLEL)
9732 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9733 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9734 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9737 old_pat = PATTERN (insn);
9738 old_notes = REG_NOTES (insn);
9739 PATTERN (insn) = pat;
9740 REG_NOTES (insn) = 0;
9742 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9743 if (dump_file && (dump_flags & TDF_DETAILS))
9745 if (insn_code_number < 0)
9746 fputs ("Failed to match this instruction:\n", dump_file);
9748 fputs ("Successfully matched this instruction:\n", dump_file);
9749 print_rtl_single (dump_file, pat);
9752 /* If it isn't, there is the possibility that we previously had an insn
9753 that clobbered some register as a side effect, but the combined
9754 insn doesn't need to do that. So try once more without the clobbers
9755 unless this represents an ASM insn. */
9757 if (insn_code_number < 0 && ! check_asm_operands (pat)
9758 && GET_CODE (pat) == PARALLEL)
9762 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9763 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9766 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9770 SUBST_INT (XVECLEN (pat, 0), pos);
9773 pat = XVECEXP (pat, 0, 0);
9775 PATTERN (insn) = pat;
9776 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9777 if (dump_file && (dump_flags & TDF_DETAILS))
9779 if (insn_code_number < 0)
9780 fputs ("Failed to match this instruction:\n", dump_file);
9782 fputs ("Successfully matched this instruction:\n", dump_file);
9783 print_rtl_single (dump_file, pat);
9786 PATTERN (insn) = old_pat;
9787 REG_NOTES (insn) = old_notes;
9789 /* Recognize all noop sets, these will be killed by followup pass. */
9790 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
9791 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
9793 /* If we had any clobbers to add, make a new pattern than contains
9794 them. Then check to make sure that all of them are dead. */
9795 if (num_clobbers_to_add)
9797 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9798 rtvec_alloc (GET_CODE (pat) == PARALLEL
9800 + num_clobbers_to_add)
9801 : num_clobbers_to_add + 1));
9803 if (GET_CODE (pat) == PARALLEL)
9804 for (i = 0; i < XVECLEN (pat, 0); i++)
9805 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9807 XVECEXP (newpat, 0, 0) = pat;
9809 add_clobbers (newpat, insn_code_number);
9811 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9812 i < XVECLEN (newpat, 0); i++)
9814 if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
9815 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9817 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH)
9819 gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)));
9820 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9821 XEXP (XVECEXP (newpat, 0, i), 0), notes);
9830 return insn_code_number;
9833 /* Like gen_lowpart_general but for use by combine. In combine it
9834 is not possible to create any new pseudoregs. However, it is
9835 safe to create invalid memory addresses, because combine will
9836 try to recognize them and all they will do is make the combine
9839 If for some reason this cannot do its job, an rtx
9840 (clobber (const_int 0)) is returned.
9841 An insn containing that will not be recognized. */
9844 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
9846 enum machine_mode imode = GET_MODE (x);
9847 unsigned int osize = GET_MODE_SIZE (omode);
9848 unsigned int isize = GET_MODE_SIZE (imode);
9854 /* Return identity if this is a CONST or symbolic reference. */
9856 && (GET_CODE (x) == CONST
9857 || GET_CODE (x) == SYMBOL_REF
9858 || GET_CODE (x) == LABEL_REF))
9861 /* We can only support MODE being wider than a word if X is a
9862 constant integer or has a mode the same size. */
9863 if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
9864 && ! ((imode == VOIDmode
9865 && (GET_CODE (x) == CONST_INT
9866 || GET_CODE (x) == CONST_DOUBLE))
9870 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9871 won't know what to do. So we will strip off the SUBREG here and
9872 process normally. */
9873 if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
9877 /* For use in case we fall down into the address adjustments
9878 further below, we need to adjust the known mode and size of
9879 x; imode and isize, since we just adjusted x. */
9880 imode = GET_MODE (x);
9885 isize = GET_MODE_SIZE (imode);
9888 result = gen_lowpart_common (omode, x);
9897 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9899 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9902 /* If we want to refer to something bigger than the original memref,
9903 generate a paradoxical subreg instead. That will force a reload
9904 of the original memref X. */
9906 return gen_rtx_SUBREG (omode, x, 0);
9908 if (WORDS_BIG_ENDIAN)
9909 offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
9911 /* Adjust the address so that the address-after-the-data is
9913 if (BYTES_BIG_ENDIAN)
9914 offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
9916 return adjust_address_nv (x, omode, offset);
9919 /* If X is a comparison operator, rewrite it in a new mode. This
9920 probably won't match, but may allow further simplifications. */
9921 else if (COMPARISON_P (x))
9922 return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
9924 /* If we couldn't simplify X any other way, just enclose it in a
9925 SUBREG. Normally, this SUBREG won't match, but some patterns may
9926 include an explicit SUBREG or we may simplify it further in combine. */
9932 offset = subreg_lowpart_offset (omode, imode);
9933 if (imode == VOIDmode)
9935 imode = int_mode_for_mode (omode);
9936 x = gen_lowpart_common (imode, x);
9940 res = simplify_gen_subreg (omode, x, imode, offset);
9946 return gen_rtx_CLOBBER (imode, const0_rtx);
9949 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9950 comparison code that will be tested.
9952 The result is a possibly different comparison code to use. *POP0 and
9953 *POP1 may be updated.
9955 It is possible that we might detect that a comparison is either always
9956 true or always false. However, we do not perform general constant
9957 folding in combine, so this knowledge isn't useful. Such tautologies
9958 should have been detected earlier. Hence we ignore all such cases. */
9960 static enum rtx_code
9961 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
9967 enum machine_mode mode, tmode;
9969 /* Try a few ways of applying the same transformation to both operands. */
9972 #ifndef WORD_REGISTER_OPERATIONS
9973 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9974 so check specially. */
9975 if (code != GTU && code != GEU && code != LTU && code != LEU
9976 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9977 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9978 && GET_CODE (XEXP (op1, 0)) == ASHIFT
9979 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9980 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9981 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9982 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9983 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9984 && XEXP (op0, 1) == XEXP (op1, 1)
9985 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
9986 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
9987 && (INTVAL (XEXP (op0, 1))
9988 == (GET_MODE_BITSIZE (GET_MODE (op0))
9990 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9992 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9993 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9997 /* If both operands are the same constant shift, see if we can ignore the
9998 shift. We can if the shift is a rotate or if the bits shifted out of
9999 this shift are known to be zero for both inputs and if the type of
10000 comparison is compatible with the shift. */
10001 if (GET_CODE (op0) == GET_CODE (op1)
10002 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10003 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
10004 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
10005 && (code != GT && code != LT && code != GE && code != LE))
10006 || (GET_CODE (op0) == ASHIFTRT
10007 && (code != GTU && code != LTU
10008 && code != GEU && code != LEU)))
10009 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10010 && INTVAL (XEXP (op0, 1)) >= 0
10011 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10012 && XEXP (op0, 1) == XEXP (op1, 1))
10014 enum machine_mode mode = GET_MODE (op0);
10015 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10016 int shift_count = INTVAL (XEXP (op0, 1));
10018 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
10019 mask &= (mask >> shift_count) << shift_count;
10020 else if (GET_CODE (op0) == ASHIFT)
10021 mask = (mask & (mask << shift_count)) >> shift_count;
10023 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
10024 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
10025 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
10030 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10031 SUBREGs are of the same mode, and, in both cases, the AND would
10032 be redundant if the comparison was done in the narrower mode,
10033 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10034 and the operand's possibly nonzero bits are 0xffffff01; in that case
10035 if we only care about QImode, we don't need the AND). This case
10036 occurs if the output mode of an scc insn is not SImode and
10037 STORE_FLAG_VALUE == 1 (e.g., the 386).
10039 Similarly, check for a case where the AND's are ZERO_EXTEND
10040 operations from some narrower mode even though a SUBREG is not
10043 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
10044 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10045 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
10047 rtx inner_op0 = XEXP (op0, 0);
10048 rtx inner_op1 = XEXP (op1, 0);
10049 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
10050 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
10053 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
10054 && (GET_MODE_SIZE (GET_MODE (inner_op0))
10055 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
10056 && (GET_MODE (SUBREG_REG (inner_op0))
10057 == GET_MODE (SUBREG_REG (inner_op1)))
10058 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
10059 <= HOST_BITS_PER_WIDE_INT)
10060 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
10061 GET_MODE (SUBREG_REG (inner_op0)))))
10062 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
10063 GET_MODE (SUBREG_REG (inner_op1))))))
10065 op0 = SUBREG_REG (inner_op0);
10066 op1 = SUBREG_REG (inner_op1);
10068 /* The resulting comparison is always unsigned since we masked
10069 off the original sign bit. */
10070 code = unsigned_condition (code);
10076 for (tmode = GET_CLASS_NARROWEST_MODE
10077 (GET_MODE_CLASS (GET_MODE (op0)));
10078 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
10079 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
10081 op0 = gen_lowpart (tmode, inner_op0);
10082 op1 = gen_lowpart (tmode, inner_op1);
10083 code = unsigned_condition (code);
10092 /* If both operands are NOT, we can strip off the outer operation
10093 and adjust the comparison code for swapped operands; similarly for
10094 NEG, except that this must be an equality comparison. */
10095 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
10096 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
10097 && (code == EQ || code == NE)))
10098 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
10104 /* If the first operand is a constant, swap the operands and adjust the
10105 comparison code appropriately, but don't do this if the second operand
10106 is already a constant integer. */
10107 if (swap_commutative_operands_p (op0, op1))
10109 tem = op0, op0 = op1, op1 = tem;
10110 code = swap_condition (code);
10113 /* We now enter a loop during which we will try to simplify the comparison.
10114 For the most part, we only are concerned with comparisons with zero,
10115 but some things may really be comparisons with zero but not start
10116 out looking that way. */
10118 while (GET_CODE (op1) == CONST_INT)
10120 enum machine_mode mode = GET_MODE (op0);
10121 unsigned int mode_width = GET_MODE_BITSIZE (mode);
10122 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10123 int equality_comparison_p;
10124 int sign_bit_comparison_p;
10125 int unsigned_comparison_p;
10126 HOST_WIDE_INT const_op;
10128 /* We only want to handle integral modes. This catches VOIDmode,
10129 CCmode, and the floating-point modes. An exception is that we
10130 can handle VOIDmode if OP0 is a COMPARE or a comparison
10133 if (GET_MODE_CLASS (mode) != MODE_INT
10134 && ! (mode == VOIDmode
10135 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
10138 /* Get the constant we are comparing against and turn off all bits
10139 not on in our mode. */
10140 const_op = INTVAL (op1);
10141 if (mode != VOIDmode)
10142 const_op = trunc_int_for_mode (const_op, mode);
10143 op1 = GEN_INT (const_op);
10145 /* If we are comparing against a constant power of two and the value
10146 being compared can only have that single bit nonzero (e.g., it was
10147 `and'ed with that bit), we can replace this with a comparison
10150 && (code == EQ || code == NE || code == GE || code == GEU
10151 || code == LT || code == LTU)
10152 && mode_width <= HOST_BITS_PER_WIDE_INT
10153 && exact_log2 (const_op) >= 0
10154 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10156 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10157 op1 = const0_rtx, const_op = 0;
10160 /* Similarly, if we are comparing a value known to be either -1 or
10161 0 with -1, change it to the opposite comparison against zero. */
10164 && (code == EQ || code == NE || code == GT || code == LE
10165 || code == GEU || code == LTU)
10166 && num_sign_bit_copies (op0, mode) == mode_width)
10168 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10169 op1 = const0_rtx, const_op = 0;
10172 /* Do some canonicalizations based on the comparison code. We prefer
10173 comparisons against zero and then prefer equality comparisons.
10174 If we can reduce the size of a constant, we will do that too. */
10179 /* < C is equivalent to <= (C - 1) */
10183 op1 = GEN_INT (const_op);
10185 /* ... fall through to LE case below. */
10191 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10195 op1 = GEN_INT (const_op);
10199 /* If we are doing a <= 0 comparison on a value known to have
10200 a zero sign bit, we can replace this with == 0. */
10201 else if (const_op == 0
10202 && mode_width <= HOST_BITS_PER_WIDE_INT
10203 && (nonzero_bits (op0, mode)
10204 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10209 /* >= C is equivalent to > (C - 1). */
10213 op1 = GEN_INT (const_op);
10215 /* ... fall through to GT below. */
10221 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10225 op1 = GEN_INT (const_op);
10229 /* If we are doing a > 0 comparison on a value known to have
10230 a zero sign bit, we can replace this with != 0. */
10231 else if (const_op == 0
10232 && mode_width <= HOST_BITS_PER_WIDE_INT
10233 && (nonzero_bits (op0, mode)
10234 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10239 /* < C is equivalent to <= (C - 1). */
10243 op1 = GEN_INT (const_op);
10245 /* ... fall through ... */
10248 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10249 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10250 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10252 const_op = 0, op1 = const0_rtx;
10260 /* unsigned <= 0 is equivalent to == 0 */
10264 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10265 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10266 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10268 const_op = 0, op1 = const0_rtx;
10274 /* >= C is equivalent to > (C - 1). */
10278 op1 = GEN_INT (const_op);
10280 /* ... fall through ... */
10283 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10284 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10285 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10287 const_op = 0, op1 = const0_rtx;
10295 /* unsigned > 0 is equivalent to != 0 */
10299 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10300 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10301 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10303 const_op = 0, op1 = const0_rtx;
10312 /* Compute some predicates to simplify code below. */
10314 equality_comparison_p = (code == EQ || code == NE);
10315 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
10316 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
10319 /* If this is a sign bit comparison and we can do arithmetic in
10320 MODE, say that we will only be needing the sign bit of OP0. */
10321 if (sign_bit_comparison_p
10322 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10323 op0 = force_to_mode (op0, mode,
10325 << (GET_MODE_BITSIZE (mode) - 1)),
10328 /* Now try cases based on the opcode of OP0. If none of the cases
10329 does a "continue", we exit this loop immediately after the
10332 switch (GET_CODE (op0))
10335 /* If we are extracting a single bit from a variable position in
10336 a constant that has only a single bit set and are comparing it
10337 with zero, we can convert this into an equality comparison
10338 between the position and the location of the single bit. */
10339 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
10340 have already reduced the shift count modulo the word size. */
10341 if (!SHIFT_COUNT_TRUNCATED
10342 && GET_CODE (XEXP (op0, 0)) == CONST_INT
10343 && XEXP (op0, 1) == const1_rtx
10344 && equality_comparison_p && const_op == 0
10345 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
10347 if (BITS_BIG_ENDIAN)
10349 enum machine_mode new_mode
10350 = mode_for_extraction (EP_extzv, 1);
10351 if (new_mode == MAX_MACHINE_MODE)
10352 i = BITS_PER_WORD - 1 - i;
10356 i = (GET_MODE_BITSIZE (mode) - 1 - i);
10360 op0 = XEXP (op0, 2);
10364 /* Result is nonzero iff shift count is equal to I. */
10365 code = reverse_condition (code);
10369 /* ... fall through ... */
10372 tem = expand_compound_operation (op0);
10381 /* If testing for equality, we can take the NOT of the constant. */
10382 if (equality_comparison_p
10383 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10385 op0 = XEXP (op0, 0);
10390 /* If just looking at the sign bit, reverse the sense of the
10392 if (sign_bit_comparison_p)
10394 op0 = XEXP (op0, 0);
10395 code = (code == GE ? LT : GE);
10401 /* If testing for equality, we can take the NEG of the constant. */
10402 if (equality_comparison_p
10403 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10405 op0 = XEXP (op0, 0);
10410 /* The remaining cases only apply to comparisons with zero. */
10414 /* When X is ABS or is known positive,
10415 (neg X) is < 0 if and only if X != 0. */
10417 if (sign_bit_comparison_p
10418 && (GET_CODE (XEXP (op0, 0)) == ABS
10419 || (mode_width <= HOST_BITS_PER_WIDE_INT
10420 && (nonzero_bits (XEXP (op0, 0), mode)
10421 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10423 op0 = XEXP (op0, 0);
10424 code = (code == LT ? NE : EQ);
10428 /* If we have NEG of something whose two high-order bits are the
10429 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10430 if (num_sign_bit_copies (op0, mode) >= 2)
10432 op0 = XEXP (op0, 0);
10433 code = swap_condition (code);
10439 /* If we are testing equality and our count is a constant, we
10440 can perform the inverse operation on our RHS. */
10441 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10442 && (tem = simplify_binary_operation (ROTATERT, mode,
10443 op1, XEXP (op0, 1))) != 0)
10445 op0 = XEXP (op0, 0);
10450 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10451 a particular bit. Convert it to an AND of a constant of that
10452 bit. This will be converted into a ZERO_EXTRACT. */
10453 if (const_op == 0 && sign_bit_comparison_p
10454 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10455 && mode_width <= HOST_BITS_PER_WIDE_INT)
10457 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10460 - INTVAL (XEXP (op0, 1)))));
10461 code = (code == LT ? NE : EQ);
10465 /* Fall through. */
10468 /* ABS is ignorable inside an equality comparison with zero. */
10469 if (const_op == 0 && equality_comparison_p)
10471 op0 = XEXP (op0, 0);
10477 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
10478 (compare FOO CONST) if CONST fits in FOO's mode and we
10479 are either testing inequality or have an unsigned
10480 comparison with ZERO_EXTEND or a signed comparison with
10481 SIGN_EXTEND. But don't do it if we don't have a compare
10482 insn of the given mode, since we'd have to revert it
10483 later on, and then we wouldn't know whether to sign- or
10485 mode = GET_MODE (XEXP (op0, 0));
10486 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10487 && ! unsigned_comparison_p
10488 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10489 && ((unsigned HOST_WIDE_INT) const_op
10490 < (((unsigned HOST_WIDE_INT) 1
10491 << (GET_MODE_BITSIZE (mode) - 1))))
10492 && optab_handler (cmp_optab, mode)->insn_code != CODE_FOR_nothing)
10494 op0 = XEXP (op0, 0);
10500 /* Check for the case where we are comparing A - C1 with C2, that is
10502 (subreg:MODE (plus (A) (-C1))) op (C2)
10504 with C1 a constant, and try to lift the SUBREG, i.e. to do the
10505 comparison in the wider mode. One of the following two conditions
10506 must be true in order for this to be valid:
10508 1. The mode extension results in the same bit pattern being added
10509 on both sides and the comparison is equality or unsigned. As
10510 C2 has been truncated to fit in MODE, the pattern can only be
10513 2. The mode extension results in the sign bit being copied on
10516 The difficulty here is that we have predicates for A but not for
10517 (A - C1) so we need to check that C1 is within proper bounds so
10518 as to perturbate A as little as possible. */
10520 if (mode_width <= HOST_BITS_PER_WIDE_INT
10521 && subreg_lowpart_p (op0)
10522 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) > mode_width
10523 && GET_CODE (SUBREG_REG (op0)) == PLUS
10524 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT)
10526 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
10527 rtx a = XEXP (SUBREG_REG (op0), 0);
10528 HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
10531 && (unsigned HOST_WIDE_INT) c1
10532 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
10533 && (equality_comparison_p || unsigned_comparison_p)
10534 /* (A - C1) zero-extends if it is positive and sign-extends
10535 if it is negative, C2 both zero- and sign-extends. */
10536 && ((0 == (nonzero_bits (a, inner_mode)
10537 & ~GET_MODE_MASK (mode))
10539 /* (A - C1) sign-extends if it is positive and 1-extends
10540 if it is negative, C2 both sign- and 1-extends. */
10541 || (num_sign_bit_copies (a, inner_mode)
10542 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10545 || ((unsigned HOST_WIDE_INT) c1
10546 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
10547 /* (A - C1) always sign-extends, like C2. */
10548 && num_sign_bit_copies (a, inner_mode)
10549 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10550 - (mode_width - 1))))
10552 op0 = SUBREG_REG (op0);
10557 /* If the inner mode is narrower and we are extracting the low part,
10558 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10559 if (subreg_lowpart_p (op0)
10560 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10561 /* Fall through */ ;
10565 /* ... fall through ... */
10568 mode = GET_MODE (XEXP (op0, 0));
10569 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10570 && (unsigned_comparison_p || equality_comparison_p)
10571 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10572 && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode))
10573 && optab_handler (cmp_optab, mode)->insn_code != CODE_FOR_nothing)
10575 op0 = XEXP (op0, 0);
10581 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10582 this for equality comparisons due to pathological cases involving
10584 if (equality_comparison_p
10585 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10586 op1, XEXP (op0, 1))))
10588 op0 = XEXP (op0, 0);
10593 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10594 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10595 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10597 op0 = XEXP (XEXP (op0, 0), 0);
10598 code = (code == LT ? EQ : NE);
10604 /* We used to optimize signed comparisons against zero, but that
10605 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10606 arrive here as equality comparisons, or (GEU, LTU) are
10607 optimized away. No need to special-case them. */
10609 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10610 (eq B (minus A C)), whichever simplifies. We can only do
10611 this for equality comparisons due to pathological cases involving
10613 if (equality_comparison_p
10614 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10615 XEXP (op0, 1), op1)))
10617 op0 = XEXP (op0, 0);
10622 if (equality_comparison_p
10623 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10624 XEXP (op0, 0), op1)))
10626 op0 = XEXP (op0, 1);
10631 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10632 of bits in X minus 1, is one iff X > 0. */
10633 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10634 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10635 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
10637 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10639 op0 = XEXP (op0, 1);
10640 code = (code == GE ? LE : GT);
10646 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10647 if C is zero or B is a constant. */
10648 if (equality_comparison_p
10649 && 0 != (tem = simplify_binary_operation (XOR, mode,
10650 XEXP (op0, 1), op1)))
10652 op0 = XEXP (op0, 0);
10659 case UNEQ: case LTGT:
10660 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
10661 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
10662 case UNORDERED: case ORDERED:
10663 /* We can't do anything if OP0 is a condition code value, rather
10664 than an actual data value. */
10666 || CC0_P (XEXP (op0, 0))
10667 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10670 /* Get the two operands being compared. */
10671 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10672 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10674 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10676 /* Check for the cases where we simply want the result of the
10677 earlier test or the opposite of that result. */
10678 if (code == NE || code == EQ
10679 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10680 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10681 && (STORE_FLAG_VALUE
10682 & (((HOST_WIDE_INT) 1
10683 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10684 && (code == LT || code == GE)))
10686 enum rtx_code new_code;
10687 if (code == LT || code == NE)
10688 new_code = GET_CODE (op0);
10690 new_code = reversed_comparison_code (op0, NULL);
10692 if (new_code != UNKNOWN)
10703 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10705 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10706 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10707 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10709 op0 = XEXP (op0, 1);
10710 code = (code == GE ? GT : LE);
10716 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10717 will be converted to a ZERO_EXTRACT later. */
10718 if (const_op == 0 && equality_comparison_p
10719 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10720 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10722 op0 = simplify_and_const_int
10723 (NULL_RTX, mode, gen_rtx_LSHIFTRT (mode,
10725 XEXP (XEXP (op0, 0), 1)),
10726 (HOST_WIDE_INT) 1);
10730 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10731 zero and X is a comparison and C1 and C2 describe only bits set
10732 in STORE_FLAG_VALUE, we can compare with X. */
10733 if (const_op == 0 && equality_comparison_p
10734 && mode_width <= HOST_BITS_PER_WIDE_INT
10735 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10736 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10737 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10738 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10739 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10741 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10742 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10743 if ((~STORE_FLAG_VALUE & mask) == 0
10744 && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
10745 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10746 && COMPARISON_P (tem))))
10748 op0 = XEXP (XEXP (op0, 0), 0);
10753 /* If we are doing an equality comparison of an AND of a bit equal
10754 to the sign bit, replace this with a LT or GE comparison of
10755 the underlying value. */
10756 if (equality_comparison_p
10758 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10759 && mode_width <= HOST_BITS_PER_WIDE_INT
10760 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10761 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10763 op0 = XEXP (op0, 0);
10764 code = (code == EQ ? GE : LT);
10768 /* If this AND operation is really a ZERO_EXTEND from a narrower
10769 mode, the constant fits within that mode, and this is either an
10770 equality or unsigned comparison, try to do this comparison in
10775 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
10776 -> (ne:DI (reg:SI 4) (const_int 0))
10778 unless TRULY_NOOP_TRUNCATION allows it or the register is
10779 known to hold a value of the required mode the
10780 transformation is invalid. */
10781 if ((equality_comparison_p || unsigned_comparison_p)
10782 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10783 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10784 & GET_MODE_MASK (mode))
10786 && const_op >> i == 0
10787 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode
10788 && (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
10789 GET_MODE_BITSIZE (GET_MODE (op0)))
10790 || (REG_P (XEXP (op0, 0))
10791 && reg_truncated_to_mode (tmode, XEXP (op0, 0)))))
10793 op0 = gen_lowpart (tmode, XEXP (op0, 0));
10797 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10798 fits in both M1 and M2 and the SUBREG is either paradoxical
10799 or represents the low part, permute the SUBREG and the AND
10801 if (GET_CODE (XEXP (op0, 0)) == SUBREG)
10803 unsigned HOST_WIDE_INT c1;
10804 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
10805 /* Require an integral mode, to avoid creating something like
10807 if (SCALAR_INT_MODE_P (tmode)
10808 /* It is unsafe to commute the AND into the SUBREG if the
10809 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10810 not defined. As originally written the upper bits
10811 have a defined value due to the AND operation.
10812 However, if we commute the AND inside the SUBREG then
10813 they no longer have defined values and the meaning of
10814 the code has been changed. */
10816 #ifdef WORD_REGISTER_OPERATIONS
10817 || (mode_width > GET_MODE_BITSIZE (tmode)
10818 && mode_width <= BITS_PER_WORD)
10820 || (mode_width <= GET_MODE_BITSIZE (tmode)
10821 && subreg_lowpart_p (XEXP (op0, 0))))
10822 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10823 && mode_width <= HOST_BITS_PER_WIDE_INT
10824 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
10825 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
10826 && (c1 & ~GET_MODE_MASK (tmode)) == 0
10828 && c1 != GET_MODE_MASK (tmode))
10830 op0 = simplify_gen_binary (AND, tmode,
10831 SUBREG_REG (XEXP (op0, 0)),
10832 gen_int_mode (c1, tmode));
10833 op0 = gen_lowpart (mode, op0);
10838 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
10839 if (const_op == 0 && equality_comparison_p
10840 && XEXP (op0, 1) == const1_rtx
10841 && GET_CODE (XEXP (op0, 0)) == NOT)
10843 op0 = simplify_and_const_int
10844 (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1);
10845 code = (code == NE ? EQ : NE);
10849 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10850 (eq (and (lshiftrt X) 1) 0).
10851 Also handle the case where (not X) is expressed using xor. */
10852 if (const_op == 0 && equality_comparison_p
10853 && XEXP (op0, 1) == const1_rtx
10854 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
10856 rtx shift_op = XEXP (XEXP (op0, 0), 0);
10857 rtx shift_count = XEXP (XEXP (op0, 0), 1);
10859 if (GET_CODE (shift_op) == NOT
10860 || (GET_CODE (shift_op) == XOR
10861 && GET_CODE (XEXP (shift_op, 1)) == CONST_INT
10862 && GET_CODE (shift_count) == CONST_INT
10863 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
10864 && (INTVAL (XEXP (shift_op, 1))
10865 == (HOST_WIDE_INT) 1 << INTVAL (shift_count))))
10867 op0 = simplify_and_const_int
10869 gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count),
10870 (HOST_WIDE_INT) 1);
10871 code = (code == NE ? EQ : NE);
10878 /* If we have (compare (ashift FOO N) (const_int C)) and
10879 the high order N bits of FOO (N+1 if an inequality comparison)
10880 are known to be zero, we can do this by comparing FOO with C
10881 shifted right N bits so long as the low-order N bits of C are
10883 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10884 && INTVAL (XEXP (op0, 1)) >= 0
10885 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10886 < HOST_BITS_PER_WIDE_INT)
10888 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10889 && mode_width <= HOST_BITS_PER_WIDE_INT
10890 && (nonzero_bits (XEXP (op0, 0), mode)
10891 & ~(mask >> (INTVAL (XEXP (op0, 1))
10892 + ! equality_comparison_p))) == 0)
10894 /* We must perform a logical shift, not an arithmetic one,
10895 as we want the top N bits of C to be zero. */
10896 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10898 temp >>= INTVAL (XEXP (op0, 1));
10899 op1 = gen_int_mode (temp, mode);
10900 op0 = XEXP (op0, 0);
10904 /* If we are doing a sign bit comparison, it means we are testing
10905 a particular bit. Convert it to the appropriate AND. */
10906 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10907 && mode_width <= HOST_BITS_PER_WIDE_INT)
10909 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10912 - INTVAL (XEXP (op0, 1)))));
10913 code = (code == LT ? NE : EQ);
10917 /* If this an equality comparison with zero and we are shifting
10918 the low bit to the sign bit, we can convert this to an AND of the
10920 if (const_op == 0 && equality_comparison_p
10921 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10922 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10925 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10926 (HOST_WIDE_INT) 1);
10932 /* If this is an equality comparison with zero, we can do this
10933 as a logical shift, which might be much simpler. */
10934 if (equality_comparison_p && const_op == 0
10935 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10937 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10939 INTVAL (XEXP (op0, 1)));
10943 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10944 do the comparison in a narrower mode. */
10945 if (! unsigned_comparison_p
10946 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10947 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10948 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10949 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10950 MODE_INT, 1)) != BLKmode
10951 && (((unsigned HOST_WIDE_INT) const_op
10952 + (GET_MODE_MASK (tmode) >> 1) + 1)
10953 <= GET_MODE_MASK (tmode)))
10955 op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
10959 /* Likewise if OP0 is a PLUS of a sign extension with a
10960 constant, which is usually represented with the PLUS
10961 between the shifts. */
10962 if (! unsigned_comparison_p
10963 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10964 && GET_CODE (XEXP (op0, 0)) == PLUS
10965 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10966 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
10967 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
10968 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10969 MODE_INT, 1)) != BLKmode
10970 && (((unsigned HOST_WIDE_INT) const_op
10971 + (GET_MODE_MASK (tmode) >> 1) + 1)
10972 <= GET_MODE_MASK (tmode)))
10974 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
10975 rtx add_const = XEXP (XEXP (op0, 0), 1);
10976 rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
10977 add_const, XEXP (op0, 1));
10979 op0 = simplify_gen_binary (PLUS, tmode,
10980 gen_lowpart (tmode, inner),
10985 /* ... fall through ... */
10987 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10988 the low order N bits of FOO are known to be zero, we can do this
10989 by comparing FOO with C shifted left N bits so long as no
10990 overflow occurs. */
10991 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10992 && INTVAL (XEXP (op0, 1)) >= 0
10993 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10994 && mode_width <= HOST_BITS_PER_WIDE_INT
10995 && (nonzero_bits (XEXP (op0, 0), mode)
10996 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10997 && (((unsigned HOST_WIDE_INT) const_op
10998 + (GET_CODE (op0) != LSHIFTRT
10999 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
11002 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
11004 /* If the shift was logical, then we must make the condition
11006 if (GET_CODE (op0) == LSHIFTRT)
11007 code = unsigned_condition (code);
11009 const_op <<= INTVAL (XEXP (op0, 1));
11010 op1 = GEN_INT (const_op);
11011 op0 = XEXP (op0, 0);
11015 /* If we are using this shift to extract just the sign bit, we
11016 can replace this with an LT or GE comparison. */
11018 && (equality_comparison_p || sign_bit_comparison_p)
11019 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11020 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11023 op0 = XEXP (op0, 0);
11024 code = (code == NE || code == GT ? LT : GE);
11036 /* Now make any compound operations involved in this comparison. Then,
11037 check for an outmost SUBREG on OP0 that is not doing anything or is
11038 paradoxical. The latter transformation must only be performed when
11039 it is known that the "extra" bits will be the same in op0 and op1 or
11040 that they don't matter. There are three cases to consider:
11042 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11043 care bits and we can assume they have any convenient value. So
11044 making the transformation is safe.
11046 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11047 In this case the upper bits of op0 are undefined. We should not make
11048 the simplification in that case as we do not know the contents of
11051 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11052 UNKNOWN. In that case we know those bits are zeros or ones. We must
11053 also be sure that they are the same as the upper bits of op1.
11055 We can never remove a SUBREG for a non-equality comparison because
11056 the sign bit is in a different place in the underlying object. */
11058 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
11059 op1 = make_compound_operation (op1, SET);
11061 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11062 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11063 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
11064 && (code == NE || code == EQ))
11066 if (GET_MODE_SIZE (GET_MODE (op0))
11067 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
11069 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11071 if (REG_P (SUBREG_REG (op0)))
11073 op0 = SUBREG_REG (op0);
11074 op1 = gen_lowpart (GET_MODE (op0), op1);
11077 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
11078 <= HOST_BITS_PER_WIDE_INT)
11079 && (nonzero_bits (SUBREG_REG (op0),
11080 GET_MODE (SUBREG_REG (op0)))
11081 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11083 tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
11085 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11086 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11087 op0 = SUBREG_REG (op0), op1 = tem;
11091 /* We now do the opposite procedure: Some machines don't have compare
11092 insns in all modes. If OP0's mode is an integer mode smaller than a
11093 word and we can't do a compare in that mode, see if there is a larger
11094 mode for which we can do the compare. There are a number of cases in
11095 which we can use the wider mode. */
11097 mode = GET_MODE (op0);
11098 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11099 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11100 && ! have_insn_for (COMPARE, mode))
11101 for (tmode = GET_MODE_WIDER_MODE (mode);
11103 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
11104 tmode = GET_MODE_WIDER_MODE (tmode))
11105 if (have_insn_for (COMPARE, tmode))
11109 /* If the only nonzero bits in OP0 and OP1 are those in the
11110 narrower mode and this is an equality or unsigned comparison,
11111 we can use the wider mode. Similarly for sign-extended
11112 values, in which case it is true for all comparisons. */
11113 zero_extended = ((code == EQ || code == NE
11114 || code == GEU || code == GTU
11115 || code == LEU || code == LTU)
11116 && (nonzero_bits (op0, tmode)
11117 & ~GET_MODE_MASK (mode)) == 0
11118 && ((GET_CODE (op1) == CONST_INT
11119 || (nonzero_bits (op1, tmode)
11120 & ~GET_MODE_MASK (mode)) == 0)));
11123 || ((num_sign_bit_copies (op0, tmode)
11124 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11125 - GET_MODE_BITSIZE (mode)))
11126 && (num_sign_bit_copies (op1, tmode)
11127 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11128 - GET_MODE_BITSIZE (mode)))))
11130 /* If OP0 is an AND and we don't have an AND in MODE either,
11131 make a new AND in the proper mode. */
11132 if (GET_CODE (op0) == AND
11133 && !have_insn_for (AND, mode))
11134 op0 = simplify_gen_binary (AND, tmode,
11135 gen_lowpart (tmode,
11137 gen_lowpart (tmode,
11140 op0 = gen_lowpart (tmode, op0);
11141 if (zero_extended && GET_CODE (op1) == CONST_INT)
11142 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
11143 op1 = gen_lowpart (tmode, op1);
11147 /* If this is a test for negative, we can make an explicit
11148 test of the sign bit. */
11150 if (op1 == const0_rtx && (code == LT || code == GE)
11151 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11153 op0 = simplify_gen_binary (AND, tmode,
11154 gen_lowpart (tmode, op0),
11155 GEN_INT ((HOST_WIDE_INT) 1
11156 << (GET_MODE_BITSIZE (mode)
11158 code = (code == LT) ? NE : EQ;
11163 #ifdef CANONICALIZE_COMPARISON
11164 /* If this machine only supports a subset of valid comparisons, see if we
11165 can convert an unsupported one into a supported one. */
11166 CANONICALIZE_COMPARISON (code, op0, op1);
11175 /* Utility function for record_value_for_reg. Count number of
11180 enum rtx_code code = GET_CODE (x);
11184 if (GET_RTX_CLASS (code) == '2'
11185 || GET_RTX_CLASS (code) == 'c')
11187 rtx x0 = XEXP (x, 0);
11188 rtx x1 = XEXP (x, 1);
11191 return 1 + 2 * count_rtxs (x0);
11193 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
11194 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
11195 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11196 return 2 + 2 * count_rtxs (x0)
11197 + count_rtxs (x == XEXP (x1, 0)
11198 ? XEXP (x1, 1) : XEXP (x1, 0));
11200 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
11201 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
11202 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11203 return 2 + 2 * count_rtxs (x1)
11204 + count_rtxs (x == XEXP (x0, 0)
11205 ? XEXP (x0, 1) : XEXP (x0, 0));
11208 fmt = GET_RTX_FORMAT (code);
11209 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11211 ret += count_rtxs (XEXP (x, i));
11216 /* Utility function for following routine. Called when X is part of a value
11217 being stored into last_set_value. Sets last_set_table_tick
11218 for each register mentioned. Similar to mention_regs in cse.c */
11221 update_table_tick (rtx x)
11223 enum rtx_code code = GET_CODE (x);
11224 const char *fmt = GET_RTX_FORMAT (code);
11229 unsigned int regno = REGNO (x);
11230 unsigned int endregno = END_REGNO (x);
11233 for (r = regno; r < endregno; r++)
11235 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, r);
11236 rsp->last_set_table_tick = label_tick;
11242 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11243 /* Note that we can't have an "E" in values stored; see
11244 get_last_value_validate. */
11247 /* Check for identical subexpressions. If x contains
11248 identical subexpression we only have to traverse one of
11250 if (i == 0 && ARITHMETIC_P (x))
11252 /* Note that at this point x1 has already been
11254 rtx x0 = XEXP (x, 0);
11255 rtx x1 = XEXP (x, 1);
11257 /* If x0 and x1 are identical then there is no need to
11262 /* If x0 is identical to a subexpression of x1 then while
11263 processing x1, x0 has already been processed. Thus we
11264 are done with x. */
11265 if (ARITHMETIC_P (x1)
11266 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11269 /* If x1 is identical to a subexpression of x0 then we
11270 still have to process the rest of x0. */
11271 if (ARITHMETIC_P (x0)
11272 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11274 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
11279 update_table_tick (XEXP (x, i));
11283 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11284 are saying that the register is clobbered and we no longer know its
11285 value. If INSN is zero, don't update reg_stat[].last_set; this is
11286 only permitted with VALUE also zero and is used to invalidate the
11290 record_value_for_reg (rtx reg, rtx insn, rtx value)
11292 unsigned int regno = REGNO (reg);
11293 unsigned int endregno = END_REGNO (reg);
11295 reg_stat_type *rsp;
11297 /* If VALUE contains REG and we have a previous value for REG, substitute
11298 the previous value. */
11299 if (value && insn && reg_overlap_mentioned_p (reg, value))
11303 /* Set things up so get_last_value is allowed to see anything set up to
11305 subst_low_luid = DF_INSN_LUID (insn);
11306 tem = get_last_value (reg);
11308 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11309 it isn't going to be useful and will take a lot of time to process,
11310 so just use the CLOBBER. */
11314 if (ARITHMETIC_P (tem)
11315 && GET_CODE (XEXP (tem, 0)) == CLOBBER
11316 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
11317 tem = XEXP (tem, 0);
11318 else if (count_occurrences (value, reg, 1) >= 2)
11320 /* If there are two or more occurrences of REG in VALUE,
11321 prevent the value from growing too much. */
11322 if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
11323 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
11326 value = replace_rtx (copy_rtx (value), reg, tem);
11330 /* For each register modified, show we don't know its value, that
11331 we don't know about its bitwise content, that its value has been
11332 updated, and that we don't know the location of the death of the
11334 for (i = regno; i < endregno; i++)
11336 rsp = VEC_index (reg_stat_type, reg_stat, i);
11339 rsp->last_set = insn;
11341 rsp->last_set_value = 0;
11342 rsp->last_set_mode = 0;
11343 rsp->last_set_nonzero_bits = 0;
11344 rsp->last_set_sign_bit_copies = 0;
11345 rsp->last_death = 0;
11346 rsp->truncated_to_mode = 0;
11349 /* Mark registers that are being referenced in this value. */
11351 update_table_tick (value);
11353 /* Now update the status of each register being set.
11354 If someone is using this register in this block, set this register
11355 to invalid since we will get confused between the two lives in this
11356 basic block. This makes using this register always invalid. In cse, we
11357 scan the table to invalidate all entries using this register, but this
11358 is too much work for us. */
11360 for (i = regno; i < endregno; i++)
11362 rsp = VEC_index (reg_stat_type, reg_stat, i);
11363 rsp->last_set_label = label_tick;
11365 || (value && rsp->last_set_table_tick >= label_tick_ebb_start))
11366 rsp->last_set_invalid = 1;
11368 rsp->last_set_invalid = 0;
11371 /* The value being assigned might refer to X (like in "x++;"). In that
11372 case, we must replace it with (clobber (const_int 0)) to prevent
11374 rsp = VEC_index (reg_stat_type, reg_stat, regno);
11375 if (value && ! get_last_value_validate (&value, insn,
11376 rsp->last_set_label, 0))
11378 value = copy_rtx (value);
11379 if (! get_last_value_validate (&value, insn,
11380 rsp->last_set_label, 1))
11384 /* For the main register being modified, update the value, the mode, the
11385 nonzero bits, and the number of sign bit copies. */
11387 rsp->last_set_value = value;
11391 enum machine_mode mode = GET_MODE (reg);
11392 subst_low_luid = DF_INSN_LUID (insn);
11393 rsp->last_set_mode = mode;
11394 if (GET_MODE_CLASS (mode) == MODE_INT
11395 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11396 mode = nonzero_bits_mode;
11397 rsp->last_set_nonzero_bits = nonzero_bits (value, mode);
11398 rsp->last_set_sign_bit_copies
11399 = num_sign_bit_copies (value, GET_MODE (reg));
11403 /* Called via note_stores from record_dead_and_set_regs to handle one
11404 SET or CLOBBER in an insn. DATA is the instruction in which the
11405 set is occurring. */
11408 record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
11410 rtx record_dead_insn = (rtx) data;
11412 if (GET_CODE (dest) == SUBREG)
11413 dest = SUBREG_REG (dest);
11415 if (!record_dead_insn)
11418 record_value_for_reg (dest, NULL_RTX, NULL_RTX);
11424 /* If we are setting the whole register, we know its value. Otherwise
11425 show that we don't know the value. We can handle SUBREG in
11427 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11428 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11429 else if (GET_CODE (setter) == SET
11430 && GET_CODE (SET_DEST (setter)) == SUBREG
11431 && SUBREG_REG (SET_DEST (setter)) == dest
11432 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11433 && subreg_lowpart_p (SET_DEST (setter)))
11434 record_value_for_reg (dest, record_dead_insn,
11435 gen_lowpart (GET_MODE (dest),
11436 SET_SRC (setter)));
11438 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11440 else if (MEM_P (dest)
11441 /* Ignore pushes, they clobber nothing. */
11442 && ! push_operand (dest, GET_MODE (dest)))
11443 mem_last_set = DF_INSN_LUID (record_dead_insn);
11446 /* Update the records of when each REG was most recently set or killed
11447 for the things done by INSN. This is the last thing done in processing
11448 INSN in the combiner loop.
11450 We update reg_stat[], in particular fields last_set, last_set_value,
11451 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
11452 last_death, and also the similar information mem_last_set (which insn
11453 most recently modified memory) and last_call_luid (which insn was the
11454 most recent subroutine call). */
11457 record_dead_and_set_regs (rtx insn)
11462 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11464 if (REG_NOTE_KIND (link) == REG_DEAD
11465 && REG_P (XEXP (link, 0)))
11467 unsigned int regno = REGNO (XEXP (link, 0));
11468 unsigned int endregno = END_REGNO (XEXP (link, 0));
11470 for (i = regno; i < endregno; i++)
11472 reg_stat_type *rsp;
11474 rsp = VEC_index (reg_stat_type, reg_stat, i);
11475 rsp->last_death = insn;
11478 else if (REG_NOTE_KIND (link) == REG_INC)
11479 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11484 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11485 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11487 reg_stat_type *rsp;
11489 rsp = VEC_index (reg_stat_type, reg_stat, i);
11490 rsp->last_set_invalid = 1;
11491 rsp->last_set = insn;
11492 rsp->last_set_value = 0;
11493 rsp->last_set_mode = 0;
11494 rsp->last_set_nonzero_bits = 0;
11495 rsp->last_set_sign_bit_copies = 0;
11496 rsp->last_death = 0;
11497 rsp->truncated_to_mode = 0;
11500 last_call_luid = mem_last_set = DF_INSN_LUID (insn);
11502 /* We can't combine into a call pattern. Remember, though, that
11503 the return value register is set at this LUID. We could
11504 still replace a register with the return value from the
11505 wrong subroutine call! */
11506 note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
11509 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11512 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11513 register present in the SUBREG, so for each such SUBREG go back and
11514 adjust nonzero and sign bit information of the registers that are
11515 known to have some zero/sign bits set.
11517 This is needed because when combine blows the SUBREGs away, the
11518 information on zero/sign bits is lost and further combines can be
11519 missed because of that. */
11522 record_promoted_value (rtx insn, rtx subreg)
11525 unsigned int regno = REGNO (SUBREG_REG (subreg));
11526 enum machine_mode mode = GET_MODE (subreg);
11528 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11531 for (links = LOG_LINKS (insn); links;)
11533 reg_stat_type *rsp;
11535 insn = XEXP (links, 0);
11536 set = single_set (insn);
11538 if (! set || !REG_P (SET_DEST (set))
11539 || REGNO (SET_DEST (set)) != regno
11540 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11542 links = XEXP (links, 1);
11546 rsp = VEC_index (reg_stat_type, reg_stat, regno);
11547 if (rsp->last_set == insn)
11549 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11550 rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode);
11553 if (REG_P (SET_SRC (set)))
11555 regno = REGNO (SET_SRC (set));
11556 links = LOG_LINKS (insn);
11563 /* Check if X, a register, is known to contain a value already
11564 truncated to MODE. In this case we can use a subreg to refer to
11565 the truncated value even though in the generic case we would need
11566 an explicit truncation. */
11569 reg_truncated_to_mode (enum machine_mode mode, const_rtx x)
11571 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
11572 enum machine_mode truncated = rsp->truncated_to_mode;
11575 || rsp->truncation_label < label_tick_ebb_start)
11577 if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
11579 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
11580 GET_MODE_BITSIZE (truncated)))
11585 /* Callback for for_each_rtx. If *P is a hard reg or a subreg record the mode
11586 that the register is accessed in. For non-TRULY_NOOP_TRUNCATION targets we
11587 might be able to turn a truncate into a subreg using this information.
11588 Return -1 if traversing *P is complete or 0 otherwise. */
11591 record_truncated_value (rtx *p, void *data ATTRIBUTE_UNUSED)
11594 enum machine_mode truncated_mode;
11595 reg_stat_type *rsp;
11597 if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
11599 enum machine_mode original_mode = GET_MODE (SUBREG_REG (x));
11600 truncated_mode = GET_MODE (x);
11602 if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
11605 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (truncated_mode),
11606 GET_MODE_BITSIZE (original_mode)))
11609 x = SUBREG_REG (x);
11611 /* ??? For hard-regs we now record everything. We might be able to
11612 optimize this using last_set_mode. */
11613 else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
11614 truncated_mode = GET_MODE (x);
11618 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
11619 if (rsp->truncated_to_mode == 0
11620 || rsp->truncation_label < label_tick_ebb_start
11621 || (GET_MODE_SIZE (truncated_mode)
11622 < GET_MODE_SIZE (rsp->truncated_to_mode)))
11624 rsp->truncated_to_mode = truncated_mode;
11625 rsp->truncation_label = label_tick;
11631 /* Callback for note_uses. Find hardregs and subregs of pseudos and
11632 the modes they are used in. This can help truning TRUNCATEs into
11636 record_truncated_values (rtx *x, void *data ATTRIBUTE_UNUSED)
11638 for_each_rtx (x, record_truncated_value, NULL);
11641 /* Scan X for promoted SUBREGs. For each one found,
11642 note what it implies to the registers used in it. */
11645 check_promoted_subreg (rtx insn, rtx x)
11647 if (GET_CODE (x) == SUBREG
11648 && SUBREG_PROMOTED_VAR_P (x)
11649 && REG_P (SUBREG_REG (x)))
11650 record_promoted_value (insn, x);
11653 const char *format = GET_RTX_FORMAT (GET_CODE (x));
11656 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11660 check_promoted_subreg (insn, XEXP (x, i));
11664 if (XVEC (x, i) != 0)
11665 for (j = 0; j < XVECLEN (x, i); j++)
11666 check_promoted_subreg (insn, XVECEXP (x, i, j));
11672 /* Utility routine for the following function. Verify that all the registers
11673 mentioned in *LOC are valid when *LOC was part of a value set when
11674 label_tick == TICK. Return 0 if some are not.
11676 If REPLACE is nonzero, replace the invalid reference with
11677 (clobber (const_int 0)) and return 1. This replacement is useful because
11678 we often can get useful information about the form of a value (e.g., if
11679 it was produced by a shift that always produces -1 or 0) even though
11680 we don't know exactly what registers it was produced from. */
11683 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
11686 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11687 int len = GET_RTX_LENGTH (GET_CODE (x));
11692 unsigned int regno = REGNO (x);
11693 unsigned int endregno = END_REGNO (x);
11696 for (j = regno; j < endregno; j++)
11698 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, j);
11699 if (rsp->last_set_invalid
11700 /* If this is a pseudo-register that was only set once and not
11701 live at the beginning of the function, it is always valid. */
11702 || (! (regno >= FIRST_PSEUDO_REGISTER
11703 && REG_N_SETS (regno) == 1
11704 && (!REGNO_REG_SET_P
11705 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno)))
11706 && rsp->last_set_label > tick))
11709 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11716 /* If this is a memory reference, make sure that there were
11717 no stores after it that might have clobbered the value. We don't
11718 have alias info, so we assume any store invalidates it. */
11719 else if (MEM_P (x) && !MEM_READONLY_P (x)
11720 && DF_INSN_LUID (insn) <= mem_last_set)
11723 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11727 for (i = 0; i < len; i++)
11731 /* Check for identical subexpressions. If x contains
11732 identical subexpression we only have to traverse one of
11734 if (i == 1 && ARITHMETIC_P (x))
11736 /* Note that at this point x0 has already been checked
11737 and found valid. */
11738 rtx x0 = XEXP (x, 0);
11739 rtx x1 = XEXP (x, 1);
11741 /* If x0 and x1 are identical then x is also valid. */
11745 /* If x1 is identical to a subexpression of x0 then
11746 while checking x0, x1 has already been checked. Thus
11747 it is valid and so as x. */
11748 if (ARITHMETIC_P (x0)
11749 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11752 /* If x0 is identical to a subexpression of x1 then x is
11753 valid iff the rest of x1 is valid. */
11754 if (ARITHMETIC_P (x1)
11755 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11757 get_last_value_validate (&XEXP (x1,
11758 x0 == XEXP (x1, 0) ? 1 : 0),
11759 insn, tick, replace);
11762 if (get_last_value_validate (&XEXP (x, i), insn, tick,
11766 /* Don't bother with these. They shouldn't occur anyway. */
11767 else if (fmt[i] == 'E')
11771 /* If we haven't found a reason for it to be invalid, it is valid. */
11775 /* Get the last value assigned to X, if known. Some registers
11776 in the value may be replaced with (clobber (const_int 0)) if their value
11777 is known longer known reliably. */
11780 get_last_value (const_rtx x)
11782 unsigned int regno;
11784 reg_stat_type *rsp;
11786 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11787 then convert it to the desired mode. If this is a paradoxical SUBREG,
11788 we cannot predict what values the "extra" bits might have. */
11789 if (GET_CODE (x) == SUBREG
11790 && subreg_lowpart_p (x)
11791 && (GET_MODE_SIZE (GET_MODE (x))
11792 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11793 && (value = get_last_value (SUBREG_REG (x))) != 0)
11794 return gen_lowpart (GET_MODE (x), value);
11800 rsp = VEC_index (reg_stat_type, reg_stat, regno);
11801 value = rsp->last_set_value;
11803 /* If we don't have a value, or if it isn't for this basic block and
11804 it's either a hard register, set more than once, or it's a live
11805 at the beginning of the function, return 0.
11807 Because if it's not live at the beginning of the function then the reg
11808 is always set before being used (is never used without being set).
11809 And, if it's set only once, and it's always set before use, then all
11810 uses must have the same last value, even if it's not from this basic
11814 || (rsp->last_set_label < label_tick_ebb_start
11815 && (regno < FIRST_PSEUDO_REGISTER
11816 || REG_N_SETS (regno) != 1
11818 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno))))
11821 /* If the value was set in a later insn than the ones we are processing,
11822 we can't use it even if the register was only set once. */
11823 if (rsp->last_set_label == label_tick
11824 && DF_INSN_LUID (rsp->last_set) >= subst_low_luid)
11827 /* If the value has all its registers valid, return it. */
11828 if (get_last_value_validate (&value, rsp->last_set,
11829 rsp->last_set_label, 0))
11832 /* Otherwise, make a copy and replace any invalid register with
11833 (clobber (const_int 0)). If that fails for some reason, return 0. */
11835 value = copy_rtx (value);
11836 if (get_last_value_validate (&value, rsp->last_set,
11837 rsp->last_set_label, 1))
11843 /* Return nonzero if expression X refers to a REG or to memory
11844 that is set in an instruction more recent than FROM_LUID. */
11847 use_crosses_set_p (const_rtx x, int from_luid)
11851 enum rtx_code code = GET_CODE (x);
11855 unsigned int regno = REGNO (x);
11856 unsigned endreg = END_REGNO (x);
11858 #ifdef PUSH_ROUNDING
11859 /* Don't allow uses of the stack pointer to be moved,
11860 because we don't know whether the move crosses a push insn. */
11861 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11864 for (; regno < endreg; regno++)
11866 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
11868 && rsp->last_set_label == label_tick
11869 && DF_INSN_LUID (rsp->last_set) > from_luid)
11875 if (code == MEM && mem_last_set > from_luid)
11878 fmt = GET_RTX_FORMAT (code);
11880 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11885 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11886 if (use_crosses_set_p (XVECEXP (x, i, j), from_luid))
11889 else if (fmt[i] == 'e'
11890 && use_crosses_set_p (XEXP (x, i), from_luid))
11896 /* Define three variables used for communication between the following
11899 static unsigned int reg_dead_regno, reg_dead_endregno;
11900 static int reg_dead_flag;
11902 /* Function called via note_stores from reg_dead_at_p.
11904 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11905 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11908 reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
11910 unsigned int regno, endregno;
11915 regno = REGNO (dest);
11916 endregno = END_REGNO (dest);
11917 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11918 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11921 /* Return nonzero if REG is known to be dead at INSN.
11923 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11924 referencing REG, it is dead. If we hit a SET referencing REG, it is
11925 live. Otherwise, see if it is live or dead at the start of the basic
11926 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11927 must be assumed to be always live. */
11930 reg_dead_at_p (rtx reg, rtx insn)
11935 /* Set variables for reg_dead_at_p_1. */
11936 reg_dead_regno = REGNO (reg);
11937 reg_dead_endregno = END_REGNO (reg);
11941 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
11942 we allow the machine description to decide whether use-and-clobber
11943 patterns are OK. */
11944 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11946 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11947 if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
11951 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11952 beginning of function. */
11953 for (; insn && !LABEL_P (insn) && !BARRIER_P (insn);
11954 insn = prev_nonnote_insn (insn))
11956 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11958 return reg_dead_flag == 1 ? 1 : 0;
11960 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11964 /* Get the basic block that we were in. */
11966 block = ENTRY_BLOCK_PTR->next_bb;
11969 FOR_EACH_BB (block)
11970 if (insn == BB_HEAD (block))
11973 if (block == EXIT_BLOCK_PTR)
11977 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11978 if (REGNO_REG_SET_P (df_get_live_in (block), i))
11984 /* Note hard registers in X that are used. */
11987 mark_used_regs_combine (rtx x)
11989 RTX_CODE code = GET_CODE (x);
11990 unsigned int regno;
12003 case ADDR_DIFF_VEC:
12006 /* CC0 must die in the insn after it is set, so we don't need to take
12007 special note of it here. */
12013 /* If we are clobbering a MEM, mark any hard registers inside the
12014 address as used. */
12015 if (MEM_P (XEXP (x, 0)))
12016 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
12021 /* A hard reg in a wide mode may really be multiple registers.
12022 If so, mark all of them just like the first. */
12023 if (regno < FIRST_PSEUDO_REGISTER)
12025 /* None of this applies to the stack, frame or arg pointers. */
12026 if (regno == STACK_POINTER_REGNUM
12027 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
12028 || regno == HARD_FRAME_POINTER_REGNUM
12030 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12031 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
12033 || regno == FRAME_POINTER_REGNUM)
12036 add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno);
12042 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12044 rtx testreg = SET_DEST (x);
12046 while (GET_CODE (testreg) == SUBREG
12047 || GET_CODE (testreg) == ZERO_EXTRACT
12048 || GET_CODE (testreg) == STRICT_LOW_PART)
12049 testreg = XEXP (testreg, 0);
12051 if (MEM_P (testreg))
12052 mark_used_regs_combine (XEXP (testreg, 0));
12054 mark_used_regs_combine (SET_SRC (x));
12062 /* Recursively scan the operands of this expression. */
12065 const char *fmt = GET_RTX_FORMAT (code);
12067 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12070 mark_used_regs_combine (XEXP (x, i));
12071 else if (fmt[i] == 'E')
12075 for (j = 0; j < XVECLEN (x, i); j++)
12076 mark_used_regs_combine (XVECEXP (x, i, j));
12082 /* Remove register number REGNO from the dead registers list of INSN.
12084 Return the note used to record the death, if there was one. */
12087 remove_death (unsigned int regno, rtx insn)
12089 rtx note = find_regno_note (insn, REG_DEAD, regno);
12092 remove_note (insn, note);
12097 /* For each register (hardware or pseudo) used within expression X, if its
12098 death is in an instruction with luid between FROM_LUID (inclusive) and
12099 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12100 list headed by PNOTES.
12102 That said, don't move registers killed by maybe_kill_insn.
12104 This is done when X is being merged by combination into TO_INSN. These
12105 notes will then be distributed as needed. */
12108 move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx to_insn,
12113 enum rtx_code code = GET_CODE (x);
12117 unsigned int regno = REGNO (x);
12118 rtx where_dead = VEC_index (reg_stat_type, reg_stat, regno)->last_death;
12120 /* Don't move the register if it gets killed in between from and to. */
12121 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
12122 && ! reg_referenced_p (x, maybe_kill_insn))
12126 && DF_INSN_LUID (where_dead) >= from_luid
12127 && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn))
12129 rtx note = remove_death (regno, where_dead);
12131 /* It is possible for the call above to return 0. This can occur
12132 when last_death points to I2 or I1 that we combined with.
12133 In that case make a new note.
12135 We must also check for the case where X is a hard register
12136 and NOTE is a death note for a range of hard registers
12137 including X. In that case, we must put REG_DEAD notes for
12138 the remaining registers in place of NOTE. */
12140 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
12141 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12142 > GET_MODE_SIZE (GET_MODE (x))))
12144 unsigned int deadregno = REGNO (XEXP (note, 0));
12145 unsigned int deadend = END_HARD_REGNO (XEXP (note, 0));
12146 unsigned int ourend = END_HARD_REGNO (x);
12149 for (i = deadregno; i < deadend; i++)
12150 if (i < regno || i >= ourend)
12151 add_reg_note (where_dead, REG_DEAD, regno_reg_rtx[i]);
12154 /* If we didn't find any note, or if we found a REG_DEAD note that
12155 covers only part of the given reg, and we have a multi-reg hard
12156 register, then to be safe we must check for REG_DEAD notes
12157 for each register other than the first. They could have
12158 their own REG_DEAD notes lying around. */
12159 else if ((note == 0
12161 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12162 < GET_MODE_SIZE (GET_MODE (x)))))
12163 && regno < FIRST_PSEUDO_REGISTER
12164 && hard_regno_nregs[regno][GET_MODE (x)] > 1)
12166 unsigned int ourend = END_HARD_REGNO (x);
12167 unsigned int i, offset;
12171 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
12175 for (i = regno + offset; i < ourend; i++)
12176 move_deaths (regno_reg_rtx[i],
12177 maybe_kill_insn, from_luid, to_insn, &oldnotes);
12180 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
12182 XEXP (note, 1) = *pnotes;
12186 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
12192 else if (GET_CODE (x) == SET)
12194 rtx dest = SET_DEST (x);
12196 move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes);
12198 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12199 that accesses one word of a multi-word item, some
12200 piece of everything register in the expression is used by
12201 this insn, so remove any old death. */
12202 /* ??? So why do we test for equality of the sizes? */
12204 if (GET_CODE (dest) == ZERO_EXTRACT
12205 || GET_CODE (dest) == STRICT_LOW_PART
12206 || (GET_CODE (dest) == SUBREG
12207 && (((GET_MODE_SIZE (GET_MODE (dest))
12208 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
12209 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
12210 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
12212 move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes);
12216 /* If this is some other SUBREG, we know it replaces the entire
12217 value, so use that as the destination. */
12218 if (GET_CODE (dest) == SUBREG)
12219 dest = SUBREG_REG (dest);
12221 /* If this is a MEM, adjust deaths of anything used in the address.
12222 For a REG (the only other possibility), the entire value is
12223 being replaced so the old value is not used in this insn. */
12226 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid,
12231 else if (GET_CODE (x) == CLOBBER)
12234 len = GET_RTX_LENGTH (code);
12235 fmt = GET_RTX_FORMAT (code);
12237 for (i = 0; i < len; i++)
12242 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12243 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid,
12246 else if (fmt[i] == 'e')
12247 move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes);
12251 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12252 pattern of an insn. X must be a REG. */
12255 reg_bitfield_target_p (rtx x, rtx body)
12259 if (GET_CODE (body) == SET)
12261 rtx dest = SET_DEST (body);
12263 unsigned int regno, tregno, endregno, endtregno;
12265 if (GET_CODE (dest) == ZERO_EXTRACT)
12266 target = XEXP (dest, 0);
12267 else if (GET_CODE (dest) == STRICT_LOW_PART)
12268 target = SUBREG_REG (XEXP (dest, 0));
12272 if (GET_CODE (target) == SUBREG)
12273 target = SUBREG_REG (target);
12275 if (!REG_P (target))
12278 tregno = REGNO (target), regno = REGNO (x);
12279 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
12280 return target == x;
12282 endtregno = end_hard_regno (GET_MODE (target), tregno);
12283 endregno = end_hard_regno (GET_MODE (x), regno);
12285 return endregno > tregno && regno < endtregno;
12288 else if (GET_CODE (body) == PARALLEL)
12289 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
12290 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
12296 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12297 as appropriate. I3 and I2 are the insns resulting from the combination
12298 insns including FROM (I2 may be zero).
12300 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
12301 not need REG_DEAD notes because they are being substituted for. This
12302 saves searching in the most common cases.
12304 Each note in the list is either ignored or placed on some insns, depending
12305 on the type of note. */
12308 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
12311 rtx note, next_note;
12314 for (note = notes; note; note = next_note)
12316 rtx place = 0, place2 = 0;
12318 next_note = XEXP (note, 1);
12319 switch (REG_NOTE_KIND (note))
12323 /* Doesn't matter much where we put this, as long as it's somewhere.
12324 It is preferable to keep these notes on branches, which is most
12325 likely to be i3. */
12329 case REG_VALUE_PROFILE:
12330 /* Just get rid of this note, as it is unused later anyway. */
12333 case REG_NON_LOCAL_GOTO:
12338 gcc_assert (i2 && JUMP_P (i2));
12343 case REG_EH_REGION:
12344 /* These notes must remain with the call or trapping instruction. */
12347 else if (i2 && CALL_P (i2))
12351 gcc_assert (flag_non_call_exceptions);
12352 if (may_trap_p (i3))
12354 else if (i2 && may_trap_p (i2))
12356 /* ??? Otherwise assume we've combined things such that we
12357 can now prove that the instructions can't trap. Drop the
12358 note in this case. */
12364 /* These notes must remain with the call. It should not be
12365 possible for both I2 and I3 to be a call. */
12370 gcc_assert (i2 && CALL_P (i2));
12376 /* Any clobbers for i3 may still exist, and so we must process
12377 REG_UNUSED notes from that insn.
12379 Any clobbers from i2 or i1 can only exist if they were added by
12380 recog_for_combine. In that case, recog_for_combine created the
12381 necessary REG_UNUSED notes. Trying to keep any original
12382 REG_UNUSED notes from these insns can cause incorrect output
12383 if it is for the same register as the original i3 dest.
12384 In that case, we will notice that the register is set in i3,
12385 and then add a REG_UNUSED note for the destination of i3, which
12386 is wrong. However, it is possible to have REG_UNUSED notes from
12387 i2 or i1 for register which were both used and clobbered, so
12388 we keep notes from i2 or i1 if they will turn into REG_DEAD
12391 /* If this register is set or clobbered in I3, put the note there
12392 unless there is one already. */
12393 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
12395 if (from_insn != i3)
12398 if (! (REG_P (XEXP (note, 0))
12399 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
12400 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
12403 /* Otherwise, if this register is used by I3, then this register
12404 now dies here, so we must put a REG_DEAD note here unless there
12406 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
12407 && ! (REG_P (XEXP (note, 0))
12408 ? find_regno_note (i3, REG_DEAD,
12409 REGNO (XEXP (note, 0)))
12410 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
12412 PUT_REG_NOTE_KIND (note, REG_DEAD);
12420 /* These notes say something about results of an insn. We can
12421 only support them if they used to be on I3 in which case they
12422 remain on I3. Otherwise they are ignored.
12424 If the note refers to an expression that is not a constant, we
12425 must also ignore the note since we cannot tell whether the
12426 equivalence is still true. It might be possible to do
12427 slightly better than this (we only have a problem if I2DEST
12428 or I1DEST is present in the expression), but it doesn't
12429 seem worth the trouble. */
12431 if (from_insn == i3
12432 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
12437 /* These notes say something about how a register is used. They must
12438 be present on any use of the register in I2 or I3. */
12439 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12442 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12451 case REG_LABEL_TARGET:
12452 case REG_LABEL_OPERAND:
12453 /* This can show up in several ways -- either directly in the
12454 pattern, or hidden off in the constant pool with (or without?)
12455 a REG_EQUAL note. */
12456 /* ??? Ignore the without-reg_equal-note problem for now. */
12457 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12458 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12459 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12460 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12464 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12465 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12466 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12467 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12475 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
12476 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
12478 if (place && JUMP_P (place)
12479 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
12480 && (JUMP_LABEL (place) == NULL
12481 || JUMP_LABEL (place) == XEXP (note, 0)))
12483 rtx label = JUMP_LABEL (place);
12486 JUMP_LABEL (place) = XEXP (note, 0);
12487 else if (LABEL_P (label))
12488 LABEL_NUSES (label)--;
12491 if (place2 && JUMP_P (place2)
12492 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
12493 && (JUMP_LABEL (place2) == NULL
12494 || JUMP_LABEL (place2) == XEXP (note, 0)))
12496 rtx label = JUMP_LABEL (place2);
12499 JUMP_LABEL (place2) = XEXP (note, 0);
12500 else if (LABEL_P (label))
12501 LABEL_NUSES (label)--;
12507 /* This note says something about the value of a register prior
12508 to the execution of an insn. It is too much trouble to see
12509 if the note is still correct in all situations. It is better
12510 to simply delete it. */
12514 /* If we replaced the right hand side of FROM_INSN with a
12515 REG_EQUAL note, the original use of the dying register
12516 will not have been combined into I3 and I2. In such cases,
12517 FROM_INSN is guaranteed to be the first of the combined
12518 instructions, so we simply need to search back before
12519 FROM_INSN for the previous use or set of this register,
12520 then alter the notes there appropriately.
12522 If the register is used as an input in I3, it dies there.
12523 Similarly for I2, if it is nonzero and adjacent to I3.
12525 If the register is not used as an input in either I3 or I2
12526 and it is not one of the registers we were supposed to eliminate,
12527 there are two possibilities. We might have a non-adjacent I2
12528 or we might have somehow eliminated an additional register
12529 from a computation. For example, we might have had A & B where
12530 we discover that B will always be zero. In this case we will
12531 eliminate the reference to A.
12533 In both cases, we must search to see if we can find a previous
12534 use of A and put the death note there. */
12537 && from_insn == i2mod
12538 && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
12543 && CALL_P (from_insn)
12544 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12546 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12548 else if (i2 != 0 && next_nonnote_insn (i2) == i3
12549 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12551 else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
12553 && reg_overlap_mentioned_p (XEXP (note, 0),
12555 || rtx_equal_p (XEXP (note, 0), elim_i1))
12562 basic_block bb = this_basic_block;
12564 for (tem = PREV_INSN (tem); place == 0; tem = PREV_INSN (tem))
12566 if (! INSN_P (tem))
12568 if (tem == BB_HEAD (bb))
12573 /* If the register is being set at TEM, see if that is all
12574 TEM is doing. If so, delete TEM. Otherwise, make this
12575 into a REG_UNUSED note instead. Don't delete sets to
12576 global register vars. */
12577 if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
12578 || !global_regs[REGNO (XEXP (note, 0))])
12579 && reg_set_p (XEXP (note, 0), PATTERN (tem)))
12581 rtx set = single_set (tem);
12582 rtx inner_dest = 0;
12584 rtx cc0_setter = NULL_RTX;
12588 for (inner_dest = SET_DEST (set);
12589 (GET_CODE (inner_dest) == STRICT_LOW_PART
12590 || GET_CODE (inner_dest) == SUBREG
12591 || GET_CODE (inner_dest) == ZERO_EXTRACT);
12592 inner_dest = XEXP (inner_dest, 0))
12595 /* Verify that it was the set, and not a clobber that
12596 modified the register.
12598 CC0 targets must be careful to maintain setter/user
12599 pairs. If we cannot delete the setter due to side
12600 effects, mark the user with an UNUSED note instead
12603 if (set != 0 && ! side_effects_p (SET_SRC (set))
12604 && rtx_equal_p (XEXP (note, 0), inner_dest)
12606 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12607 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12608 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12612 /* Move the notes and links of TEM elsewhere.
12613 This might delete other dead insns recursively.
12614 First set the pattern to something that won't use
12616 rtx old_notes = REG_NOTES (tem);
12618 PATTERN (tem) = pc_rtx;
12619 REG_NOTES (tem) = NULL;
12621 distribute_notes (old_notes, tem, tem, NULL_RTX,
12622 NULL_RTX, NULL_RTX);
12623 distribute_links (LOG_LINKS (tem));
12625 SET_INSN_DELETED (tem);
12628 /* Delete the setter too. */
12631 PATTERN (cc0_setter) = pc_rtx;
12632 old_notes = REG_NOTES (cc0_setter);
12633 REG_NOTES (cc0_setter) = NULL;
12635 distribute_notes (old_notes, cc0_setter,
12636 cc0_setter, NULL_RTX,
12637 NULL_RTX, NULL_RTX);
12638 distribute_links (LOG_LINKS (cc0_setter));
12640 SET_INSN_DELETED (cc0_setter);
12646 PUT_REG_NOTE_KIND (note, REG_UNUSED);
12648 /* If there isn't already a REG_UNUSED note, put one
12649 here. Do not place a REG_DEAD note, even if
12650 the register is also used here; that would not
12651 match the algorithm used in lifetime analysis
12652 and can cause the consistency check in the
12653 scheduler to fail. */
12654 if (! find_regno_note (tem, REG_UNUSED,
12655 REGNO (XEXP (note, 0))))
12660 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12662 && find_reg_fusage (tem, USE, XEXP (note, 0))))
12666 /* If we are doing a 3->2 combination, and we have a
12667 register which formerly died in i3 and was not used
12668 by i2, which now no longer dies in i3 and is used in
12669 i2 but does not die in i2, and place is between i2
12670 and i3, then we may need to move a link from place to
12672 if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2)
12674 && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2)
12675 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12677 rtx links = LOG_LINKS (place);
12678 LOG_LINKS (place) = 0;
12679 distribute_links (links);
12684 if (tem == BB_HEAD (bb))
12690 /* If the register is set or already dead at PLACE, we needn't do
12691 anything with this note if it is still a REG_DEAD note.
12692 We check here if it is set at all, not if is it totally replaced,
12693 which is what `dead_or_set_p' checks, so also check for it being
12696 if (place && REG_NOTE_KIND (note) == REG_DEAD)
12698 unsigned int regno = REGNO (XEXP (note, 0));
12699 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
12701 if (dead_or_set_p (place, XEXP (note, 0))
12702 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12704 /* Unless the register previously died in PLACE, clear
12705 last_death. [I no longer understand why this is
12707 if (rsp->last_death != place)
12708 rsp->last_death = 0;
12712 rsp->last_death = place;
12714 /* If this is a death note for a hard reg that is occupying
12715 multiple registers, ensure that we are still using all
12716 parts of the object. If we find a piece of the object
12717 that is unused, we must arrange for an appropriate REG_DEAD
12718 note to be added for it. However, we can't just emit a USE
12719 and tag the note to it, since the register might actually
12720 be dead; so we recourse, and the recursive call then finds
12721 the previous insn that used this register. */
12723 if (place && regno < FIRST_PSEUDO_REGISTER
12724 && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
12726 unsigned int endregno = END_HARD_REGNO (XEXP (note, 0));
12730 for (i = regno; i < endregno; i++)
12731 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12732 && ! find_regno_fusage (place, USE, i))
12733 || dead_or_set_regno_p (place, i))
12738 /* Put only REG_DEAD notes for pieces that are
12739 not already dead or set. */
12741 for (i = regno; i < endregno;
12742 i += hard_regno_nregs[i][reg_raw_mode[i]])
12744 rtx piece = regno_reg_rtx[i];
12745 basic_block bb = this_basic_block;
12747 if (! dead_or_set_p (place, piece)
12748 && ! reg_bitfield_target_p (piece,
12752 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
12754 distribute_notes (new_note, place, place,
12755 NULL_RTX, NULL_RTX, NULL_RTX);
12757 else if (! refers_to_regno_p (i, i + 1,
12758 PATTERN (place), 0)
12759 && ! find_regno_fusage (place, USE, i))
12760 for (tem = PREV_INSN (place); ;
12761 tem = PREV_INSN (tem))
12763 if (! INSN_P (tem))
12765 if (tem == BB_HEAD (bb))
12769 if (dead_or_set_p (tem, piece)
12770 || reg_bitfield_target_p (piece,
12773 add_reg_note (tem, REG_UNUSED, piece);
12787 /* Any other notes should not be present at this point in the
12789 gcc_unreachable ();
12794 XEXP (note, 1) = REG_NOTES (place);
12795 REG_NOTES (place) = note;
12800 = gen_rtx_fmt_ee (GET_CODE (note), REG_NOTE_KIND (note),
12801 XEXP (note, 0), REG_NOTES (place2));
12805 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12806 I3, I2, and I1 to new locations. This is also called to add a link
12807 pointing at I3 when I3's destination is changed. */
12810 distribute_links (rtx links)
12812 rtx link, next_link;
12814 for (link = links; link; link = next_link)
12820 next_link = XEXP (link, 1);
12822 /* If the insn that this link points to is a NOTE or isn't a single
12823 set, ignore it. In the latter case, it isn't clear what we
12824 can do other than ignore the link, since we can't tell which
12825 register it was for. Such links wouldn't be used by combine
12828 It is not possible for the destination of the target of the link to
12829 have been changed by combine. The only potential of this is if we
12830 replace I3, I2, and I1 by I3 and I2. But in that case the
12831 destination of I2 also remains unchanged. */
12833 if (NOTE_P (XEXP (link, 0))
12834 || (set = single_set (XEXP (link, 0))) == 0)
12837 reg = SET_DEST (set);
12838 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12839 || GET_CODE (reg) == STRICT_LOW_PART)
12840 reg = XEXP (reg, 0);
12842 /* A LOG_LINK is defined as being placed on the first insn that uses
12843 a register and points to the insn that sets the register. Start
12844 searching at the next insn after the target of the link and stop
12845 when we reach a set of the register or the end of the basic block.
12847 Note that this correctly handles the link that used to point from
12848 I3 to I2. Also note that not much searching is typically done here
12849 since most links don't point very far away. */
12851 for (insn = NEXT_INSN (XEXP (link, 0));
12852 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
12853 || BB_HEAD (this_basic_block->next_bb) != insn));
12854 insn = NEXT_INSN (insn))
12855 if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12857 if (reg_referenced_p (reg, PATTERN (insn)))
12861 else if (CALL_P (insn)
12862 && find_reg_fusage (insn, USE, reg))
12867 else if (INSN_P (insn) && reg_set_p (reg, insn))
12870 /* If we found a place to put the link, place it there unless there
12871 is already a link to the same insn as LINK at that point. */
12877 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12878 if (XEXP (link2, 0) == XEXP (link, 0))
12883 XEXP (link, 1) = LOG_LINKS (place);
12884 LOG_LINKS (place) = link;
12886 /* Set added_links_insn to the earliest insn we added a
12888 if (added_links_insn == 0
12889 || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place))
12890 added_links_insn = place;
12896 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
12897 Check whether the expression pointer to by LOC is a register or
12898 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
12899 Otherwise return zero. */
12902 unmentioned_reg_p_1 (rtx *loc, void *expr)
12907 && (REG_P (x) || MEM_P (x))
12908 && ! reg_mentioned_p (x, (rtx) expr))
12913 /* Check for any register or memory mentioned in EQUIV that is not
12914 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
12915 of EXPR where some registers may have been replaced by constants. */
12918 unmentioned_reg_p (rtx equiv, rtx expr)
12920 return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
12924 dump_combine_stats (FILE *file)
12928 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12929 combine_attempts, combine_merges, combine_extras, combine_successes);
12933 dump_combine_total_stats (FILE *file)
12937 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12938 total_attempts, total_merges, total_extras, total_successes);
12942 gate_handle_combine (void)
12944 return (optimize > 0);
12947 /* Try combining insns through substitution. */
12948 static unsigned int
12949 rest_of_handle_combine (void)
12951 int rebuild_jump_labels_after_combine;
12953 df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN);
12954 df_note_add_problem ();
12957 regstat_init_n_sets_and_refs ();
12959 rebuild_jump_labels_after_combine
12960 = combine_instructions (get_insns (), max_reg_num ());
12962 /* Combining insns may have turned an indirect jump into a
12963 direct jump. Rebuild the JUMP_LABEL fields of jumping
12965 if (rebuild_jump_labels_after_combine)
12967 timevar_push (TV_JUMP);
12968 rebuild_jump_labels (get_insns ());
12970 timevar_pop (TV_JUMP);
12973 regstat_free_n_sets_and_refs ();
12977 struct rtl_opt_pass pass_combine =
12981 "combine", /* name */
12982 gate_handle_combine, /* gate */
12983 rest_of_handle_combine, /* execute */
12986 0, /* static_pass_number */
12987 TV_COMBINE, /* tv_id */
12988 0, /* properties_required */
12989 0, /* properties_provided */
12990 0, /* properties_destroyed */
12991 0, /* todo_flags_start */
12993 TODO_df_finish | TODO_verify_rtl_sharing |
12994 TODO_ggc_collect, /* todo_flags_finish */