1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
4 2011 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
87 #include "hard-reg-set.h"
88 #include "basic-block.h"
89 #include "insn-config.h"
91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
93 #include "insn-attr.h"
95 #include "diagnostic-core.h"
98 #include "insn-codes.h"
99 #include "rtlhooks-def.h"
100 /* Include output.h for dump_file. */
104 #include "tree-pass.h"
108 /* Number of attempts to combine instructions in this function. */
110 static int combine_attempts;
112 /* Number of attempts that got as far as substitution in this function. */
114 static int combine_merges;
116 /* Number of instructions combined with added SETs in this function. */
118 static int combine_extras;
120 /* Number of instructions combined in this function. */
122 static int combine_successes;
124 /* Totals over entire compilation. */
126 static int total_attempts, total_merges, total_extras, total_successes;
128 /* combine_instructions may try to replace the right hand side of the
129 second instruction with the value of an associated REG_EQUAL note
130 before throwing it at try_combine. That is problematic when there
131 is a REG_DEAD note for a register used in the old right hand side
132 and can cause distribute_notes to do wrong things. This is the
133 second instruction if it has been so modified, null otherwise. */
137 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
139 static rtx i2mod_old_rhs;
141 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
143 static rtx i2mod_new_rhs;
145 typedef struct reg_stat_struct {
146 /* Record last point of death of (hard or pseudo) register n. */
149 /* Record last point of modification of (hard or pseudo) register n. */
152 /* The next group of fields allows the recording of the last value assigned
153 to (hard or pseudo) register n. We use this information to see if an
154 operation being processed is redundant given a prior operation performed
155 on the register. For example, an `and' with a constant is redundant if
156 all the zero bits are already known to be turned off.
158 We use an approach similar to that used by cse, but change it in the
161 (1) We do not want to reinitialize at each label.
162 (2) It is useful, but not critical, to know the actual value assigned
163 to a register. Often just its form is helpful.
165 Therefore, we maintain the following fields:
167 last_set_value the last value assigned
168 last_set_label records the value of label_tick when the
169 register was assigned
170 last_set_table_tick records the value of label_tick when a
171 value using the register is assigned
172 last_set_invalid set to nonzero when it is not valid
173 to use the value of this register in some
176 To understand the usage of these tables, it is important to understand
177 the distinction between the value in last_set_value being valid and
178 the register being validly contained in some other expression in the
181 (The next two parameters are out of date).
183 reg_stat[i].last_set_value is valid if it is nonzero, and either
184 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
186 Register I may validly appear in any expression returned for the value
187 of another register if reg_n_sets[i] is 1. It may also appear in the
188 value for register J if reg_stat[j].last_set_invalid is zero, or
189 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
191 If an expression is found in the table containing a register which may
192 not validly appear in an expression, the register is replaced by
193 something that won't match, (clobber (const_int 0)). */
195 /* Record last value assigned to (hard or pseudo) register n. */
199 /* Record the value of label_tick when an expression involving register n
200 is placed in last_set_value. */
202 int last_set_table_tick;
204 /* Record the value of label_tick when the value for register n is placed in
209 /* These fields are maintained in parallel with last_set_value and are
210 used to store the mode in which the register was last set, the bits
211 that were known to be zero when it was last set, and the number of
212 sign bits copies it was known to have when it was last set. */
214 unsigned HOST_WIDE_INT last_set_nonzero_bits;
215 char last_set_sign_bit_copies;
216 ENUM_BITFIELD(machine_mode) last_set_mode : 8;
218 /* Set nonzero if references to register n in expressions should not be
219 used. last_set_invalid is set nonzero when this register is being
220 assigned to and last_set_table_tick == label_tick. */
222 char last_set_invalid;
224 /* Some registers that are set more than once and used in more than one
225 basic block are nevertheless always set in similar ways. For example,
226 a QImode register may be loaded from memory in two places on a machine
227 where byte loads zero extend.
229 We record in the following fields if a register has some leading bits
230 that are always equal to the sign bit, and what we know about the
231 nonzero bits of a register, specifically which bits are known to be
234 If an entry is zero, it means that we don't know anything special. */
236 unsigned char sign_bit_copies;
238 unsigned HOST_WIDE_INT nonzero_bits;
240 /* Record the value of the label_tick when the last truncation
241 happened. The field truncated_to_mode is only valid if
242 truncation_label == label_tick. */
244 int truncation_label;
246 /* Record the last truncation seen for this register. If truncation
247 is not a nop to this mode we might be able to save an explicit
248 truncation if we know that value already contains a truncated
251 ENUM_BITFIELD(machine_mode) truncated_to_mode : 8;
254 DEF_VEC_O(reg_stat_type);
255 DEF_VEC_ALLOC_O(reg_stat_type,heap);
257 static VEC(reg_stat_type,heap) *reg_stat;
259 /* Record the luid of the last insn that invalidated memory
260 (anything that writes memory, and subroutine calls, but not pushes). */
262 static int mem_last_set;
264 /* Record the luid of the last CALL_INSN
265 so we can tell whether a potential combination crosses any calls. */
267 static int last_call_luid;
269 /* When `subst' is called, this is the insn that is being modified
270 (by combining in a previous insn). The PATTERN of this insn
271 is still the old pattern partially modified and it should not be
272 looked at, but this may be used to examine the successors of the insn
273 to judge whether a simplification is valid. */
275 static rtx subst_insn;
277 /* This is the lowest LUID that `subst' is currently dealing with.
278 get_last_value will not return a value if the register was set at or
279 after this LUID. If not for this mechanism, we could get confused if
280 I2 or I1 in try_combine were an insn that used the old value of a register
281 to obtain a new value. In that case, we might erroneously get the
282 new value of the register when we wanted the old one. */
284 static int subst_low_luid;
286 /* This contains any hard registers that are used in newpat; reg_dead_at_p
287 must consider all these registers to be always live. */
289 static HARD_REG_SET newpat_used_regs;
291 /* This is an insn to which a LOG_LINKS entry has been added. If this
292 insn is the earlier than I2 or I3, combine should rescan starting at
295 static rtx added_links_insn;
297 /* Basic block in which we are performing combines. */
298 static basic_block this_basic_block;
299 static bool optimize_this_for_speed_p;
302 /* Length of the currently allocated uid_insn_cost array. */
304 static int max_uid_known;
306 /* The following array records the insn_rtx_cost for every insn
307 in the instruction stream. */
309 static int *uid_insn_cost;
311 /* The following array records the LOG_LINKS for every insn in the
312 instruction stream as an INSN_LIST rtx. */
314 static rtx *uid_log_links;
316 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
317 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
319 /* Incremented for each basic block. */
321 static int label_tick;
323 /* Reset to label_tick for each extended basic block in scanning order. */
325 static int label_tick_ebb_start;
327 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
328 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
330 static enum machine_mode nonzero_bits_mode;
332 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
333 be safely used. It is zero while computing them and after combine has
334 completed. This former test prevents propagating values based on
335 previously set values, which can be incorrect if a variable is modified
338 static int nonzero_sign_valid;
341 /* Record one modification to rtl structure
342 to be undone by storing old_contents into *where. */
344 enum undo_kind { UNDO_RTX, UNDO_INT, UNDO_MODE, UNDO_LINKS };
350 union { rtx r; int i; enum machine_mode m; } old_contents;
351 union { rtx *r; int *i; } where;
354 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
355 num_undo says how many are currently recorded.
357 other_insn is nonzero if we have modified some other insn in the process
358 of working on subst_insn. It must be verified too. */
367 static struct undobuf undobuf;
369 /* Number of times the pseudo being substituted for
370 was found and replaced. */
372 static int n_occurrences;
374 static rtx reg_nonzero_bits_for_combine (const_rtx, enum machine_mode, const_rtx,
376 unsigned HOST_WIDE_INT,
377 unsigned HOST_WIDE_INT *);
378 static rtx reg_num_sign_bit_copies_for_combine (const_rtx, enum machine_mode, const_rtx,
380 unsigned int, unsigned int *);
381 static void do_SUBST (rtx *, rtx);
382 static void do_SUBST_INT (int *, int);
383 static void init_reg_last (void);
384 static void setup_incoming_promotions (rtx);
385 static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *);
386 static int cant_combine_insn_p (rtx);
387 static int can_combine_p (rtx, rtx, rtx, rtx, rtx, rtx, rtx *, rtx *);
388 static int combinable_i3pat (rtx, rtx *, rtx, rtx, rtx, int, int, rtx *);
389 static int contains_muldiv (rtx);
390 static rtx try_combine (rtx, rtx, rtx, rtx, int *, rtx);
391 static void undo_all (void);
392 static void undo_commit (void);
393 static rtx *find_split_point (rtx *, rtx, bool);
394 static rtx subst (rtx, rtx, rtx, int, int);
395 static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
396 static rtx simplify_if_then_else (rtx);
397 static rtx simplify_set (rtx);
398 static rtx simplify_logical (rtx);
399 static rtx expand_compound_operation (rtx);
400 static const_rtx expand_field_assignment (const_rtx);
401 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
402 rtx, unsigned HOST_WIDE_INT, int, int, int);
403 static rtx extract_left_shift (rtx, int);
404 static rtx make_compound_operation (rtx, enum rtx_code);
405 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
406 unsigned HOST_WIDE_INT *);
407 static rtx canon_reg_for_combine (rtx, rtx);
408 static rtx force_to_mode (rtx, enum machine_mode,
409 unsigned HOST_WIDE_INT, int);
410 static rtx if_then_else_cond (rtx, rtx *, rtx *);
411 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
412 static int rtx_equal_for_field_assignment_p (rtx, rtx);
413 static rtx make_field_assignment (rtx);
414 static rtx apply_distributive_law (rtx);
415 static rtx distribute_and_simplify_rtx (rtx, int);
416 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
417 unsigned HOST_WIDE_INT);
418 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
419 unsigned HOST_WIDE_INT);
420 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
421 HOST_WIDE_INT, enum machine_mode, int *);
422 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
423 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
425 static int recog_for_combine (rtx *, rtx, rtx *);
426 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
427 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
428 static void update_table_tick (rtx);
429 static void record_value_for_reg (rtx, rtx, rtx);
430 static void check_promoted_subreg (rtx, rtx);
431 static void record_dead_and_set_regs_1 (rtx, const_rtx, void *);
432 static void record_dead_and_set_regs (rtx);
433 static int get_last_value_validate (rtx *, rtx, int, int);
434 static rtx get_last_value (const_rtx);
435 static int use_crosses_set_p (const_rtx, int);
436 static void reg_dead_at_p_1 (rtx, const_rtx, void *);
437 static int reg_dead_at_p (rtx, rtx);
438 static void move_deaths (rtx, rtx, int, rtx, rtx *);
439 static int reg_bitfield_target_p (rtx, rtx);
440 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx, rtx);
441 static void distribute_links (rtx);
442 static void mark_used_regs_combine (rtx);
443 static void record_promoted_value (rtx, rtx);
444 static int unmentioned_reg_p_1 (rtx *, void *);
445 static bool unmentioned_reg_p (rtx, rtx);
446 static int record_truncated_value (rtx *, void *);
447 static void record_truncated_values (rtx *, void *);
448 static bool reg_truncated_to_mode (enum machine_mode, const_rtx);
449 static rtx gen_lowpart_or_truncate (enum machine_mode, rtx);
452 /* It is not safe to use ordinary gen_lowpart in combine.
453 See comments in gen_lowpart_for_combine. */
454 #undef RTL_HOOKS_GEN_LOWPART
455 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
457 /* Our implementation of gen_lowpart never emits a new pseudo. */
458 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
459 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
461 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
462 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
464 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
465 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
467 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
468 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
470 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
473 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
474 PATTERN can not be split. Otherwise, it returns an insn sequence.
475 This is a wrapper around split_insns which ensures that the
476 reg_stat vector is made larger if the splitter creates a new
480 combine_split_insns (rtx pattern, rtx insn)
485 ret = split_insns (pattern, insn);
486 nregs = max_reg_num ();
487 if (nregs > VEC_length (reg_stat_type, reg_stat))
488 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
492 /* This is used by find_single_use to locate an rtx in LOC that
493 contains exactly one use of DEST, which is typically either a REG
494 or CC0. It returns a pointer to the innermost rtx expression
495 containing DEST. Appearances of DEST that are being used to
496 totally replace it are not counted. */
499 find_single_use_1 (rtx dest, rtx *loc)
502 enum rtx_code code = GET_CODE (x);
520 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
521 of a REG that occupies all of the REG, the insn uses DEST if
522 it is mentioned in the destination or the source. Otherwise, we
523 need just check the source. */
524 if (GET_CODE (SET_DEST (x)) != CC0
525 && GET_CODE (SET_DEST (x)) != PC
526 && !REG_P (SET_DEST (x))
527 && ! (GET_CODE (SET_DEST (x)) == SUBREG
528 && REG_P (SUBREG_REG (SET_DEST (x)))
529 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
530 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
531 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
532 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
535 return find_single_use_1 (dest, &SET_SRC (x));
539 return find_single_use_1 (dest, &XEXP (x, 0));
545 /* If it wasn't one of the common cases above, check each expression and
546 vector of this code. Look for a unique usage of DEST. */
548 fmt = GET_RTX_FORMAT (code);
549 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
553 if (dest == XEXP (x, i)
554 || (REG_P (dest) && REG_P (XEXP (x, i))
555 && REGNO (dest) == REGNO (XEXP (x, i))))
558 this_result = find_single_use_1 (dest, &XEXP (x, i));
561 result = this_result;
562 else if (this_result)
563 /* Duplicate usage. */
566 else if (fmt[i] == 'E')
570 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
572 if (XVECEXP (x, i, j) == dest
574 && REG_P (XVECEXP (x, i, j))
575 && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
578 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
581 result = this_result;
582 else if (this_result)
592 /* See if DEST, produced in INSN, is used only a single time in the
593 sequel. If so, return a pointer to the innermost rtx expression in which
596 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
598 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
599 care about REG_DEAD notes or LOG_LINKS.
601 Otherwise, we find the single use by finding an insn that has a
602 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
603 only referenced once in that insn, we know that it must be the first
604 and last insn referencing DEST. */
607 find_single_use (rtx dest, rtx insn, rtx *ploc)
617 next = NEXT_INSN (insn);
619 || (!NONJUMP_INSN_P (next) && !JUMP_P (next)))
622 result = find_single_use_1 (dest, &PATTERN (next));
632 bb = BLOCK_FOR_INSN (insn);
633 for (next = NEXT_INSN (insn);
634 next && BLOCK_FOR_INSN (next) == bb;
635 next = NEXT_INSN (next))
636 if (INSN_P (next) && dead_or_set_p (next, dest))
638 for (link = LOG_LINKS (next); link; link = XEXP (link, 1))
639 if (XEXP (link, 0) == insn)
644 result = find_single_use_1 (dest, &PATTERN (next));
654 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
655 insn. The substitution can be undone by undo_all. If INTO is already
656 set to NEWVAL, do not record this change. Because computing NEWVAL might
657 also call SUBST, we have to compute it before we put anything into
661 do_SUBST (rtx *into, rtx newval)
666 if (oldval == newval)
669 /* We'd like to catch as many invalid transformations here as
670 possible. Unfortunately, there are way too many mode changes
671 that are perfectly valid, so we'd waste too much effort for
672 little gain doing the checks here. Focus on catching invalid
673 transformations involving integer constants. */
675 && GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
676 && CONST_INT_P (newval))
678 /* Sanity check that we're replacing oldval with a CONST_INT
679 that is a valid sign-extension for the original mode. */
680 gcc_assert (INTVAL (newval)
681 == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
683 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
684 CONST_INT is not valid, because after the replacement, the
685 original mode would be gone. Unfortunately, we can't tell
686 when do_SUBST is called to replace the operand thereof, so we
687 perform this test on oldval instead, checking whether an
688 invalid replacement took place before we got here. */
689 gcc_assert (!(GET_CODE (oldval) == SUBREG
690 && CONST_INT_P (SUBREG_REG (oldval))));
691 gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
692 && CONST_INT_P (XEXP (oldval, 0))));
696 buf = undobuf.frees, undobuf.frees = buf->next;
698 buf = XNEW (struct undo);
700 buf->kind = UNDO_RTX;
702 buf->old_contents.r = oldval;
705 buf->next = undobuf.undos, undobuf.undos = buf;
708 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
710 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
711 for the value of a HOST_WIDE_INT value (including CONST_INT) is
715 do_SUBST_INT (int *into, int newval)
720 if (oldval == newval)
724 buf = undobuf.frees, undobuf.frees = buf->next;
726 buf = XNEW (struct undo);
728 buf->kind = UNDO_INT;
730 buf->old_contents.i = oldval;
733 buf->next = undobuf.undos, undobuf.undos = buf;
736 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
738 /* Similar to SUBST, but just substitute the mode. This is used when
739 changing the mode of a pseudo-register, so that any other
740 references to the entry in the regno_reg_rtx array will change as
744 do_SUBST_MODE (rtx *into, enum machine_mode newval)
747 enum machine_mode oldval = GET_MODE (*into);
749 if (oldval == newval)
753 buf = undobuf.frees, undobuf.frees = buf->next;
755 buf = XNEW (struct undo);
757 buf->kind = UNDO_MODE;
759 buf->old_contents.m = oldval;
760 adjust_reg_mode (*into, newval);
762 buf->next = undobuf.undos, undobuf.undos = buf;
765 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE(&(INTO), (NEWVAL))
769 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
772 do_SUBST_LINK (rtx *into, rtx newval)
776 if (oldval == newval)
780 buf = undobuf.frees, undobuf.frees = buf->next;
782 buf = XNEW (struct undo);
784 buf->kind = UNDO_LINKS;
786 buf->old_contents.r = oldval;
789 buf->next = undobuf.undos, undobuf.undos = buf;
792 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
795 /* Subroutine of try_combine. Determine whether the combine replacement
796 patterns NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to
797 insn_rtx_cost that the original instruction sequence I0, I1, I2, I3 and
798 undobuf.other_insn. Note that I1 and/or NEWI2PAT may be NULL_RTX.
799 NEWOTHERPAT and undobuf.other_insn may also both be NULL_RTX. This
800 function returns false, if the costs of all instructions can be
801 estimated, and the replacements are more expensive than the original
805 combine_validate_cost (rtx i0, rtx i1, rtx i2, rtx i3, rtx newpat,
806 rtx newi2pat, rtx newotherpat)
808 int i0_cost, i1_cost, i2_cost, i3_cost;
809 int new_i2_cost, new_i3_cost;
810 int old_cost, new_cost;
812 /* Lookup the original insn_rtx_costs. */
813 i2_cost = INSN_COST (i2);
814 i3_cost = INSN_COST (i3);
818 i1_cost = INSN_COST (i1);
821 i0_cost = INSN_COST (i0);
822 old_cost = (i0_cost > 0 && i1_cost > 0 && i2_cost > 0 && i3_cost > 0
823 ? i0_cost + i1_cost + i2_cost + i3_cost : 0);
827 old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0
828 ? i1_cost + i2_cost + i3_cost : 0);
834 old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
835 i1_cost = i0_cost = 0;
838 /* Calculate the replacement insn_rtx_costs. */
839 new_i3_cost = insn_rtx_cost (newpat, optimize_this_for_speed_p);
842 new_i2_cost = insn_rtx_cost (newi2pat, optimize_this_for_speed_p);
843 new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
844 ? new_i2_cost + new_i3_cost : 0;
848 new_cost = new_i3_cost;
852 if (undobuf.other_insn)
854 int old_other_cost, new_other_cost;
856 old_other_cost = INSN_COST (undobuf.other_insn);
857 new_other_cost = insn_rtx_cost (newotherpat, optimize_this_for_speed_p);
858 if (old_other_cost > 0 && new_other_cost > 0)
860 old_cost += old_other_cost;
861 new_cost += new_other_cost;
867 /* Disallow this recombination if both new_cost and old_cost are
868 greater than zero, and new_cost is greater than old cost. */
870 && new_cost > old_cost)
877 "rejecting combination of insns %d, %d, %d and %d\n",
878 INSN_UID (i0), INSN_UID (i1), INSN_UID (i2),
880 fprintf (dump_file, "original costs %d + %d + %d + %d = %d\n",
881 i0_cost, i1_cost, i2_cost, i3_cost, old_cost);
886 "rejecting combination of insns %d, %d and %d\n",
887 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
888 fprintf (dump_file, "original costs %d + %d + %d = %d\n",
889 i1_cost, i2_cost, i3_cost, old_cost);
894 "rejecting combination of insns %d and %d\n",
895 INSN_UID (i2), INSN_UID (i3));
896 fprintf (dump_file, "original costs %d + %d = %d\n",
897 i2_cost, i3_cost, old_cost);
902 fprintf (dump_file, "replacement costs %d + %d = %d\n",
903 new_i2_cost, new_i3_cost, new_cost);
906 fprintf (dump_file, "replacement cost %d\n", new_cost);
912 /* Update the uid_insn_cost array with the replacement costs. */
913 INSN_COST (i2) = new_i2_cost;
914 INSN_COST (i3) = new_i3_cost;
922 /* Delete any insns that copy a register to itself. */
925 delete_noop_moves (void)
932 for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
934 next = NEXT_INSN (insn);
935 if (INSN_P (insn) && noop_move_p (insn))
938 fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn));
940 delete_insn_and_edges (insn);
947 /* Fill in log links field for all insns. */
950 create_log_links (void)
954 df_ref *def_vec, *use_vec;
956 next_use = XCNEWVEC (rtx, max_reg_num ());
958 /* Pass through each block from the end, recording the uses of each
959 register and establishing log links when def is encountered.
960 Note that we do not clear next_use array in order to save time,
961 so we have to test whether the use is in the same basic block as def.
963 There are a few cases below when we do not consider the definition or
964 usage -- these are taken from original flow.c did. Don't ask me why it is
965 done this way; I don't know and if it works, I don't want to know. */
969 FOR_BB_INSNS_REVERSE (bb, insn)
971 if (!NONDEBUG_INSN_P (insn))
974 /* Log links are created only once. */
975 gcc_assert (!LOG_LINKS (insn));
977 for (def_vec = DF_INSN_DEFS (insn); *def_vec; def_vec++)
979 df_ref def = *def_vec;
980 int regno = DF_REF_REGNO (def);
983 if (!next_use[regno])
986 /* Do not consider if it is pre/post modification in MEM. */
987 if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY)
990 /* Do not make the log link for frame pointer. */
991 if ((regno == FRAME_POINTER_REGNUM
992 && (! reload_completed || frame_pointer_needed))
993 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
994 || (regno == HARD_FRAME_POINTER_REGNUM
995 && (! reload_completed || frame_pointer_needed))
997 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
998 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
1003 use_insn = next_use[regno];
1004 if (BLOCK_FOR_INSN (use_insn) == bb)
1008 We don't build a LOG_LINK for hard registers contained
1009 in ASM_OPERANDs. If these registers get replaced,
1010 we might wind up changing the semantics of the insn,
1011 even if reload can make what appear to be valid
1012 assignments later. */
1013 if (regno >= FIRST_PSEUDO_REGISTER
1014 || asm_noperands (PATTERN (use_insn)) < 0)
1016 /* Don't add duplicate links between instructions. */
1018 for (links = LOG_LINKS (use_insn); links;
1019 links = XEXP (links, 1))
1020 if (insn == XEXP (links, 0))
1024 LOG_LINKS (use_insn) =
1025 alloc_INSN_LIST (insn, LOG_LINKS (use_insn));
1028 next_use[regno] = NULL_RTX;
1031 for (use_vec = DF_INSN_USES (insn); *use_vec; use_vec++)
1033 df_ref use = *use_vec;
1034 int regno = DF_REF_REGNO (use);
1036 /* Do not consider the usage of the stack pointer
1037 by function call. */
1038 if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE)
1041 next_use[regno] = insn;
1049 /* Clear LOG_LINKS fields of insns. */
1052 clear_log_links (void)
1056 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
1058 free_INSN_LIST_list (&LOG_LINKS (insn));
1061 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1062 true if we found a LOG_LINK that proves that A feeds B. This only works
1063 if there are no instructions between A and B which could have a link
1064 depending on A, since in that case we would not record a link for B.
1065 We also check the implicit dependency created by a cc0 setter/user
1069 insn_a_feeds_b (rtx a, rtx b)
1072 for (links = LOG_LINKS (b); links; links = XEXP (links, 1))
1073 if (XEXP (links, 0) == a)
1082 /* Main entry point for combiner. F is the first insn of the function.
1083 NREGS is the first unused pseudo-reg number.
1085 Return nonzero if the combiner has turned an indirect jump
1086 instruction into a direct jump. */
1088 combine_instructions (rtx f, unsigned int nregs)
1094 rtx links, nextlinks;
1096 basic_block last_bb;
1098 int new_direct_jump_p = 0;
1100 for (first = f; first && !INSN_P (first); )
1101 first = NEXT_INSN (first);
1105 combine_attempts = 0;
1108 combine_successes = 0;
1110 rtl_hooks = combine_rtl_hooks;
1112 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
1114 init_recog_no_volatile ();
1116 /* Allocate array for insn info. */
1117 max_uid_known = get_max_uid ();
1118 uid_log_links = XCNEWVEC (rtx, max_uid_known + 1);
1119 uid_insn_cost = XCNEWVEC (int, max_uid_known + 1);
1121 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
1123 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1124 problems when, for example, we have j <<= 1 in a loop. */
1126 nonzero_sign_valid = 0;
1127 label_tick = label_tick_ebb_start = 1;
1129 /* Scan all SETs and see if we can deduce anything about what
1130 bits are known to be zero for some registers and how many copies
1131 of the sign bit are known to exist for those registers.
1133 Also set any known values so that we can use it while searching
1134 for what bits are known to be set. */
1136 setup_incoming_promotions (first);
1137 /* Allow the entry block and the first block to fall into the same EBB.
1138 Conceptually the incoming promotions are assigned to the entry block. */
1139 last_bb = ENTRY_BLOCK_PTR;
1141 create_log_links ();
1142 FOR_EACH_BB (this_basic_block)
1144 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1149 if (!single_pred_p (this_basic_block)
1150 || single_pred (this_basic_block) != last_bb)
1151 label_tick_ebb_start = label_tick;
1152 last_bb = this_basic_block;
1154 FOR_BB_INSNS (this_basic_block, insn)
1155 if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
1157 subst_low_luid = DF_INSN_LUID (insn);
1160 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
1162 record_dead_and_set_regs (insn);
1165 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
1166 if (REG_NOTE_KIND (links) == REG_INC)
1167 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
1171 /* Record the current insn_rtx_cost of this instruction. */
1172 if (NONJUMP_INSN_P (insn))
1173 INSN_COST (insn) = insn_rtx_cost (PATTERN (insn),
1174 optimize_this_for_speed_p);
1176 fprintf(dump_file, "insn_cost %d: %d\n",
1177 INSN_UID (insn), INSN_COST (insn));
1181 nonzero_sign_valid = 1;
1183 /* Now scan all the insns in forward order. */
1184 label_tick = label_tick_ebb_start = 1;
1186 setup_incoming_promotions (first);
1187 last_bb = ENTRY_BLOCK_PTR;
1189 FOR_EACH_BB (this_basic_block)
1191 rtx last_combined_insn = NULL_RTX;
1192 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1197 if (!single_pred_p (this_basic_block)
1198 || single_pred (this_basic_block) != last_bb)
1199 label_tick_ebb_start = label_tick;
1200 last_bb = this_basic_block;
1202 rtl_profile_for_bb (this_basic_block);
1203 for (insn = BB_HEAD (this_basic_block);
1204 insn != NEXT_INSN (BB_END (this_basic_block));
1205 insn = next ? next : NEXT_INSN (insn))
1208 if (NONDEBUG_INSN_P (insn))
1210 while (last_combined_insn
1211 && INSN_DELETED_P (last_combined_insn))
1212 last_combined_insn = PREV_INSN (last_combined_insn);
1213 if (last_combined_insn == NULL_RTX
1214 || BARRIER_P (last_combined_insn)
1215 || BLOCK_FOR_INSN (last_combined_insn) != this_basic_block
1216 || DF_INSN_LUID (last_combined_insn) <= DF_INSN_LUID (insn))
1217 last_combined_insn = insn;
1219 /* See if we know about function return values before this
1220 insn based upon SUBREG flags. */
1221 check_promoted_subreg (insn, PATTERN (insn));
1223 /* See if we can find hardregs and subreg of pseudos in
1224 narrower modes. This could help turning TRUNCATEs
1226 note_uses (&PATTERN (insn), record_truncated_values, NULL);
1228 /* Try this insn with each insn it links back to. */
1230 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1231 if ((next = try_combine (insn, XEXP (links, 0), NULL_RTX,
1232 NULL_RTX, &new_direct_jump_p,
1233 last_combined_insn)) != 0)
1236 /* Try each sequence of three linked insns ending with this one. */
1238 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1240 rtx link = XEXP (links, 0);
1242 /* If the linked insn has been replaced by a note, then there
1243 is no point in pursuing this chain any further. */
1247 for (nextlinks = LOG_LINKS (link);
1249 nextlinks = XEXP (nextlinks, 1))
1250 if ((next = try_combine (insn, link, XEXP (nextlinks, 0),
1251 NULL_RTX, &new_direct_jump_p,
1252 last_combined_insn)) != 0)
1257 /* Try to combine a jump insn that uses CC0
1258 with a preceding insn that sets CC0, and maybe with its
1259 logical predecessor as well.
1260 This is how we make decrement-and-branch insns.
1261 We need this special code because data flow connections
1262 via CC0 do not get entered in LOG_LINKS. */
1265 && (prev = prev_nonnote_insn (insn)) != 0
1266 && NONJUMP_INSN_P (prev)
1267 && sets_cc0_p (PATTERN (prev)))
1269 if ((next = try_combine (insn, prev, NULL_RTX, NULL_RTX,
1271 last_combined_insn)) != 0)
1274 for (nextlinks = LOG_LINKS (prev); nextlinks;
1275 nextlinks = XEXP (nextlinks, 1))
1276 if ((next = try_combine (insn, prev, XEXP (nextlinks, 0),
1277 NULL_RTX, &new_direct_jump_p,
1278 last_combined_insn)) != 0)
1282 /* Do the same for an insn that explicitly references CC0. */
1283 if (NONJUMP_INSN_P (insn)
1284 && (prev = prev_nonnote_insn (insn)) != 0
1285 && NONJUMP_INSN_P (prev)
1286 && sets_cc0_p (PATTERN (prev))
1287 && GET_CODE (PATTERN (insn)) == SET
1288 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
1290 if ((next = try_combine (insn, prev, NULL_RTX, NULL_RTX,
1292 last_combined_insn)) != 0)
1295 for (nextlinks = LOG_LINKS (prev); nextlinks;
1296 nextlinks = XEXP (nextlinks, 1))
1297 if ((next = try_combine (insn, prev, XEXP (nextlinks, 0),
1298 NULL_RTX, &new_direct_jump_p,
1299 last_combined_insn)) != 0)
1303 /* Finally, see if any of the insns that this insn links to
1304 explicitly references CC0. If so, try this insn, that insn,
1305 and its predecessor if it sets CC0. */
1306 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1307 if (NONJUMP_INSN_P (XEXP (links, 0))
1308 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
1309 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
1310 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
1311 && NONJUMP_INSN_P (prev)
1312 && sets_cc0_p (PATTERN (prev))
1313 && (next = try_combine (insn, XEXP (links, 0),
1314 prev, NULL_RTX, &new_direct_jump_p,
1315 last_combined_insn)) != 0)
1319 /* Try combining an insn with two different insns whose results it
1321 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1322 for (nextlinks = XEXP (links, 1); nextlinks;
1323 nextlinks = XEXP (nextlinks, 1))
1324 if ((next = try_combine (insn, XEXP (links, 0),
1325 XEXP (nextlinks, 0), NULL_RTX,
1327 last_combined_insn)) != 0)
1330 /* Try four-instruction combinations. */
1331 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1334 rtx link = XEXP (links, 0);
1336 /* If the linked insn has been replaced by a note, then there
1337 is no point in pursuing this chain any further. */
1341 for (next1 = LOG_LINKS (link); next1; next1 = XEXP (next1, 1))
1343 rtx link1 = XEXP (next1, 0);
1346 /* I0 -> I1 -> I2 -> I3. */
1347 for (nextlinks = LOG_LINKS (link1); nextlinks;
1348 nextlinks = XEXP (nextlinks, 1))
1349 if ((next = try_combine (insn, link, link1,
1350 XEXP (nextlinks, 0),
1352 last_combined_insn)) != 0)
1354 /* I0, I1 -> I2, I2 -> I3. */
1355 for (nextlinks = XEXP (next1, 1); nextlinks;
1356 nextlinks = XEXP (nextlinks, 1))
1357 if ((next = try_combine (insn, link, link1,
1358 XEXP (nextlinks, 0),
1360 last_combined_insn)) != 0)
1364 for (next1 = XEXP (links, 1); next1; next1 = XEXP (next1, 1))
1366 rtx link1 = XEXP (next1, 0);
1369 /* I0 -> I2; I1, I2 -> I3. */
1370 for (nextlinks = LOG_LINKS (link); nextlinks;
1371 nextlinks = XEXP (nextlinks, 1))
1372 if ((next = try_combine (insn, link, link1,
1373 XEXP (nextlinks, 0),
1375 last_combined_insn)) != 0)
1377 /* I0 -> I1; I1, I2 -> I3. */
1378 for (nextlinks = LOG_LINKS (link1); nextlinks;
1379 nextlinks = XEXP (nextlinks, 1))
1380 if ((next = try_combine (insn, link, link1,
1381 XEXP (nextlinks, 0),
1383 last_combined_insn)) != 0)
1388 /* Try this insn with each REG_EQUAL note it links back to. */
1389 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1392 rtx temp = XEXP (links, 0);
1393 if ((set = single_set (temp)) != 0
1394 && (note = find_reg_equal_equiv_note (temp)) != 0
1395 && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
1396 /* Avoid using a register that may already been marked
1397 dead by an earlier instruction. */
1398 && ! unmentioned_reg_p (note, SET_SRC (set))
1399 && (GET_MODE (note) == VOIDmode
1400 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
1401 : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
1403 /* Temporarily replace the set's source with the
1404 contents of the REG_EQUAL note. The insn will
1405 be deleted or recognized by try_combine. */
1406 rtx orig = SET_SRC (set);
1407 SET_SRC (set) = note;
1409 i2mod_old_rhs = copy_rtx (orig);
1410 i2mod_new_rhs = copy_rtx (note);
1411 next = try_combine (insn, i2mod, NULL_RTX, NULL_RTX,
1413 last_combined_insn);
1417 SET_SRC (set) = orig;
1422 record_dead_and_set_regs (insn);
1430 default_rtl_profile ();
1433 new_direct_jump_p |= purge_all_dead_edges ();
1434 delete_noop_moves ();
1437 free (uid_log_links);
1438 free (uid_insn_cost);
1439 VEC_free (reg_stat_type, heap, reg_stat);
1442 struct undo *undo, *next;
1443 for (undo = undobuf.frees; undo; undo = next)
1451 total_attempts += combine_attempts;
1452 total_merges += combine_merges;
1453 total_extras += combine_extras;
1454 total_successes += combine_successes;
1456 nonzero_sign_valid = 0;
1457 rtl_hooks = general_rtl_hooks;
1459 /* Make recognizer allow volatile MEMs again. */
1462 return new_direct_jump_p;
1465 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1468 init_reg_last (void)
1473 FOR_EACH_VEC_ELT (reg_stat_type, reg_stat, i, p)
1474 memset (p, 0, offsetof (reg_stat_type, sign_bit_copies));
1477 /* Set up any promoted values for incoming argument registers. */
1480 setup_incoming_promotions (rtx first)
1483 bool strictly_local = false;
1485 for (arg = DECL_ARGUMENTS (current_function_decl); arg;
1486 arg = DECL_CHAIN (arg))
1488 rtx x, reg = DECL_INCOMING_RTL (arg);
1490 enum machine_mode mode1, mode2, mode3, mode4;
1492 /* Only continue if the incoming argument is in a register. */
1496 /* Determine, if possible, whether all call sites of the current
1497 function lie within the current compilation unit. (This does
1498 take into account the exporting of a function via taking its
1499 address, and so forth.) */
1500 strictly_local = cgraph_local_info (current_function_decl)->local;
1502 /* The mode and signedness of the argument before any promotions happen
1503 (equal to the mode of the pseudo holding it at that stage). */
1504 mode1 = TYPE_MODE (TREE_TYPE (arg));
1505 uns1 = TYPE_UNSIGNED (TREE_TYPE (arg));
1507 /* The mode and signedness of the argument after any source language and
1508 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1509 mode2 = TYPE_MODE (DECL_ARG_TYPE (arg));
1510 uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg));
1512 /* The mode and signedness of the argument as it is actually passed,
1513 after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */
1514 mode3 = promote_function_mode (DECL_ARG_TYPE (arg), mode2, &uns3,
1515 TREE_TYPE (cfun->decl), 0);
1517 /* The mode of the register in which the argument is being passed. */
1518 mode4 = GET_MODE (reg);
1520 /* Eliminate sign extensions in the callee when:
1521 (a) A mode promotion has occurred; */
1524 /* (b) The mode of the register is the same as the mode of
1525 the argument as it is passed; */
1528 /* (c) There's no language level extension; */
1531 /* (c.1) All callers are from the current compilation unit. If that's
1532 the case we don't have to rely on an ABI, we only have to know
1533 what we're generating right now, and we know that we will do the
1534 mode1 to mode2 promotion with the given sign. */
1535 else if (!strictly_local)
1537 /* (c.2) The combination of the two promotions is useful. This is
1538 true when the signs match, or if the first promotion is unsigned.
1539 In the later case, (sign_extend (zero_extend x)) is the same as
1540 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1546 /* Record that the value was promoted from mode1 to mode3,
1547 so that any sign extension at the head of the current
1548 function may be eliminated. */
1549 x = gen_rtx_CLOBBER (mode1, const0_rtx);
1550 x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x);
1551 record_value_for_reg (reg, first, x);
1555 /* Called via note_stores. If X is a pseudo that is narrower than
1556 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1558 If we are setting only a portion of X and we can't figure out what
1559 portion, assume all bits will be used since we don't know what will
1562 Similarly, set how many bits of X are known to be copies of the sign bit
1563 at all locations in the function. This is the smallest number implied
1567 set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data)
1569 rtx insn = (rtx) data;
1573 && REGNO (x) >= FIRST_PSEUDO_REGISTER
1574 /* If this register is undefined at the start of the file, we can't
1575 say what its contents were. */
1576 && ! REGNO_REG_SET_P
1577 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x))
1578 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
1580 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
1582 if (set == 0 || GET_CODE (set) == CLOBBER)
1584 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1585 rsp->sign_bit_copies = 1;
1589 /* If this register is being initialized using itself, and the
1590 register is uninitialized in this basic block, and there are
1591 no LOG_LINKS which set the register, then part of the
1592 register is uninitialized. In that case we can't assume
1593 anything about the number of nonzero bits.
1595 ??? We could do better if we checked this in
1596 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1597 could avoid making assumptions about the insn which initially
1598 sets the register, while still using the information in other
1599 insns. We would have to be careful to check every insn
1600 involved in the combination. */
1603 && reg_referenced_p (x, PATTERN (insn))
1604 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)),
1609 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
1611 if (dead_or_set_p (XEXP (link, 0), x))
1616 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1617 rsp->sign_bit_copies = 1;
1622 /* If this is a complex assignment, see if we can convert it into a
1623 simple assignment. */
1624 set = expand_field_assignment (set);
1626 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1627 set what we know about X. */
1629 if (SET_DEST (set) == x
1630 || (GET_CODE (SET_DEST (set)) == SUBREG
1631 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
1632 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
1633 && SUBREG_REG (SET_DEST (set)) == x))
1635 rtx src = SET_SRC (set);
1637 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1638 /* If X is narrower than a word and SRC is a non-negative
1639 constant that would appear negative in the mode of X,
1640 sign-extend it for use in reg_stat[].nonzero_bits because some
1641 machines (maybe most) will actually do the sign-extension
1642 and this is the conservative approach.
1644 ??? For 2.5, try to tighten up the MD files in this regard
1645 instead of this kludge. */
1647 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
1648 && CONST_INT_P (src)
1650 && 0 != (UINTVAL (src)
1651 & ((unsigned HOST_WIDE_INT) 1
1652 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
1653 src = GEN_INT (UINTVAL (src)
1654 | ((unsigned HOST_WIDE_INT) (-1)
1655 << GET_MODE_BITSIZE (GET_MODE (x))));
1658 /* Don't call nonzero_bits if it cannot change anything. */
1659 if (rsp->nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1660 rsp->nonzero_bits |= nonzero_bits (src, nonzero_bits_mode);
1661 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1662 if (rsp->sign_bit_copies == 0
1663 || rsp->sign_bit_copies > num)
1664 rsp->sign_bit_copies = num;
1668 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1669 rsp->sign_bit_copies = 1;
1674 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1675 optionally insns that were previously combined into I3 or that will be
1676 combined into the merger of INSN and I3. The order is PRED, PRED2,
1677 INSN, SUCC, SUCC2, I3.
1679 Return 0 if the combination is not allowed for any reason.
1681 If the combination is allowed, *PDEST will be set to the single
1682 destination of INSN and *PSRC to the single source, and this function
1686 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED,
1687 rtx pred2 ATTRIBUTE_UNUSED, rtx succ, rtx succ2,
1688 rtx *pdest, rtx *psrc)
1697 bool all_adjacent = true;
1698 int (*is_volatile_p) (const_rtx);
1704 if (next_active_insn (succ2) != i3)
1705 all_adjacent = false;
1706 if (next_active_insn (succ) != succ2)
1707 all_adjacent = false;
1709 else if (next_active_insn (succ) != i3)
1710 all_adjacent = false;
1711 if (next_active_insn (insn) != succ)
1712 all_adjacent = false;
1714 else if (next_active_insn (insn) != i3)
1715 all_adjacent = false;
1717 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1718 or a PARALLEL consisting of such a SET and CLOBBERs.
1720 If INSN has CLOBBER parallel parts, ignore them for our processing.
1721 By definition, these happen during the execution of the insn. When it
1722 is merged with another insn, all bets are off. If they are, in fact,
1723 needed and aren't also supplied in I3, they may be added by
1724 recog_for_combine. Otherwise, it won't match.
1726 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1729 Get the source and destination of INSN. If more than one, can't
1732 if (GET_CODE (PATTERN (insn)) == SET)
1733 set = PATTERN (insn);
1734 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1735 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1737 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1739 rtx elt = XVECEXP (PATTERN (insn), 0, i);
1741 switch (GET_CODE (elt))
1743 /* This is important to combine floating point insns
1744 for the SH4 port. */
1746 /* Combining an isolated USE doesn't make sense.
1747 We depend here on combinable_i3pat to reject them. */
1748 /* The code below this loop only verifies that the inputs of
1749 the SET in INSN do not change. We call reg_set_between_p
1750 to verify that the REG in the USE does not change between
1752 If the USE in INSN was for a pseudo register, the matching
1753 insn pattern will likely match any register; combining this
1754 with any other USE would only be safe if we knew that the
1755 used registers have identical values, or if there was
1756 something to tell them apart, e.g. different modes. For
1757 now, we forgo such complicated tests and simply disallow
1758 combining of USES of pseudo registers with any other USE. */
1759 if (REG_P (XEXP (elt, 0))
1760 && GET_CODE (PATTERN (i3)) == PARALLEL)
1762 rtx i3pat = PATTERN (i3);
1763 int i = XVECLEN (i3pat, 0) - 1;
1764 unsigned int regno = REGNO (XEXP (elt, 0));
1768 rtx i3elt = XVECEXP (i3pat, 0, i);
1770 if (GET_CODE (i3elt) == USE
1771 && REG_P (XEXP (i3elt, 0))
1772 && (REGNO (XEXP (i3elt, 0)) == regno
1773 ? reg_set_between_p (XEXP (elt, 0),
1774 PREV_INSN (insn), i3)
1775 : regno >= FIRST_PSEUDO_REGISTER))
1782 /* We can ignore CLOBBERs. */
1787 /* Ignore SETs whose result isn't used but not those that
1788 have side-effects. */
1789 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1790 && insn_nothrow_p (insn)
1791 && !side_effects_p (elt))
1794 /* If we have already found a SET, this is a second one and
1795 so we cannot combine with this insn. */
1803 /* Anything else means we can't combine. */
1809 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1810 so don't do anything with it. */
1811 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1820 /* The simplification in expand_field_assignment may call back to
1821 get_last_value, so set safe guard here. */
1822 subst_low_luid = DF_INSN_LUID (insn);
1824 set = expand_field_assignment (set);
1825 src = SET_SRC (set), dest = SET_DEST (set);
1827 /* Don't eliminate a store in the stack pointer. */
1828 if (dest == stack_pointer_rtx
1829 /* Don't combine with an insn that sets a register to itself if it has
1830 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1831 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1832 /* Can't merge an ASM_OPERANDS. */
1833 || GET_CODE (src) == ASM_OPERANDS
1834 /* Can't merge a function call. */
1835 || GET_CODE (src) == CALL
1836 /* Don't eliminate a function call argument. */
1838 && (find_reg_fusage (i3, USE, dest)
1840 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1841 && global_regs[REGNO (dest)])))
1842 /* Don't substitute into an incremented register. */
1843 || FIND_REG_INC_NOTE (i3, dest)
1844 || (succ && FIND_REG_INC_NOTE (succ, dest))
1845 || (succ2 && FIND_REG_INC_NOTE (succ2, dest))
1846 /* Don't substitute into a non-local goto, this confuses CFG. */
1847 || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1848 /* Make sure that DEST is not used after SUCC but before I3. */
1851 && (reg_used_between_p (dest, succ2, i3)
1852 || reg_used_between_p (dest, succ, succ2)))
1853 || (!succ2 && succ && reg_used_between_p (dest, succ, i3))))
1854 /* Make sure that the value that is to be substituted for the register
1855 does not use any registers whose values alter in between. However,
1856 If the insns are adjacent, a use can't cross a set even though we
1857 think it might (this can happen for a sequence of insns each setting
1858 the same destination; last_set of that register might point to
1859 a NOTE). If INSN has a REG_EQUIV note, the register is always
1860 equivalent to the memory so the substitution is valid even if there
1861 are intervening stores. Also, don't move a volatile asm or
1862 UNSPEC_VOLATILE across any other insns. */
1865 || ! find_reg_note (insn, REG_EQUIV, src))
1866 && use_crosses_set_p (src, DF_INSN_LUID (insn)))
1867 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1868 || GET_CODE (src) == UNSPEC_VOLATILE))
1869 /* Don't combine across a CALL_INSN, because that would possibly
1870 change whether the life span of some REGs crosses calls or not,
1871 and it is a pain to update that information.
1872 Exception: if source is a constant, moving it later can't hurt.
1873 Accept that as a special case. */
1874 || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src)))
1877 /* DEST must either be a REG or CC0. */
1880 /* If register alignment is being enforced for multi-word items in all
1881 cases except for parameters, it is possible to have a register copy
1882 insn referencing a hard register that is not allowed to contain the
1883 mode being copied and which would not be valid as an operand of most
1884 insns. Eliminate this problem by not combining with such an insn.
1886 Also, on some machines we don't want to extend the life of a hard
1890 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1891 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1892 /* Don't extend the life of a hard register unless it is
1893 user variable (if we have few registers) or it can't
1894 fit into the desired register (meaning something special
1896 Also avoid substituting a return register into I3, because
1897 reload can't handle a conflict with constraints of other
1899 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1900 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1903 else if (GET_CODE (dest) != CC0)
1907 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1908 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1909 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1911 /* Don't substitute for a register intended as a clobberable
1913 rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1914 if (rtx_equal_p (reg, dest))
1917 /* If the clobber represents an earlyclobber operand, we must not
1918 substitute an expression containing the clobbered register.
1919 As we do not analyze the constraint strings here, we have to
1920 make the conservative assumption. However, if the register is
1921 a fixed hard reg, the clobber cannot represent any operand;
1922 we leave it up to the machine description to either accept or
1923 reject use-and-clobber patterns. */
1925 || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1926 || !fixed_regs[REGNO (reg)])
1927 if (reg_overlap_mentioned_p (reg, src))
1931 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1932 or not), reject, unless nothing volatile comes between it and I3 */
1934 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1936 /* Make sure neither succ nor succ2 contains a volatile reference. */
1937 if (succ2 != 0 && volatile_refs_p (PATTERN (succ2)))
1939 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1941 /* We'll check insns between INSN and I3 below. */
1944 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1945 to be an explicit register variable, and was chosen for a reason. */
1947 if (GET_CODE (src) == ASM_OPERANDS
1948 && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1951 /* If INSN contains volatile references (specifically volatile MEMs),
1952 we cannot combine across any other volatile references.
1953 Even if INSN doesn't contain volatile references, any intervening
1954 volatile insn might affect machine state. */
1956 is_volatile_p = volatile_refs_p (PATTERN (insn))
1960 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1961 if (INSN_P (p) && p != succ && p != succ2 && is_volatile_p (PATTERN (p)))
1964 /* If INSN contains an autoincrement or autodecrement, make sure that
1965 register is not used between there and I3, and not already used in
1966 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1967 Also insist that I3 not be a jump; if it were one
1968 and the incremented register were spilled, we would lose. */
1971 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1972 if (REG_NOTE_KIND (link) == REG_INC
1974 || reg_used_between_p (XEXP (link, 0), insn, i3)
1975 || (pred != NULL_RTX
1976 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1977 || (pred2 != NULL_RTX
1978 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred2)))
1979 || (succ != NULL_RTX
1980 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1981 || (succ2 != NULL_RTX
1982 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ2)))
1983 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1988 /* Don't combine an insn that follows a CC0-setting insn.
1989 An insn that uses CC0 must not be separated from the one that sets it.
1990 We do, however, allow I2 to follow a CC0-setting insn if that insn
1991 is passed as I1; in that case it will be deleted also.
1992 We also allow combining in this case if all the insns are adjacent
1993 because that would leave the two CC0 insns adjacent as well.
1994 It would be more logical to test whether CC0 occurs inside I1 or I2,
1995 but that would be much slower, and this ought to be equivalent. */
1997 p = prev_nonnote_insn (insn);
1998 if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
2003 /* If we get here, we have passed all the tests and the combination is
2012 /* LOC is the location within I3 that contains its pattern or the component
2013 of a PARALLEL of the pattern. We validate that it is valid for combining.
2015 One problem is if I3 modifies its output, as opposed to replacing it
2016 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2017 doing so would produce an insn that is not equivalent to the original insns.
2021 (set (reg:DI 101) (reg:DI 100))
2022 (set (subreg:SI (reg:DI 101) 0) <foo>)
2024 This is NOT equivalent to:
2026 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2027 (set (reg:DI 101) (reg:DI 100))])
2029 Not only does this modify 100 (in which case it might still be valid
2030 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2032 We can also run into a problem if I2 sets a register that I1
2033 uses and I1 gets directly substituted into I3 (not via I2). In that
2034 case, we would be getting the wrong value of I2DEST into I3, so we
2035 must reject the combination. This case occurs when I2 and I1 both
2036 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2037 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2038 of a SET must prevent combination from occurring. The same situation
2039 can occur for I0, in which case I0_NOT_IN_SRC is set.
2041 Before doing the above check, we first try to expand a field assignment
2042 into a set of logical operations.
2044 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2045 we place a register that is both set and used within I3. If more than one
2046 such register is detected, we fail.
2048 Return 1 if the combination is valid, zero otherwise. */
2051 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest, rtx i0dest,
2052 int i1_not_in_src, int i0_not_in_src, rtx *pi3dest_killed)
2056 if (GET_CODE (x) == SET)
2059 rtx dest = SET_DEST (set);
2060 rtx src = SET_SRC (set);
2061 rtx inner_dest = dest;
2064 while (GET_CODE (inner_dest) == STRICT_LOW_PART
2065 || GET_CODE (inner_dest) == SUBREG
2066 || GET_CODE (inner_dest) == ZERO_EXTRACT)
2067 inner_dest = XEXP (inner_dest, 0);
2069 /* Check for the case where I3 modifies its output, as discussed
2070 above. We don't want to prevent pseudos from being combined
2071 into the address of a MEM, so only prevent the combination if
2072 i1 or i2 set the same MEM. */
2073 if ((inner_dest != dest &&
2074 (!MEM_P (inner_dest)
2075 || rtx_equal_p (i2dest, inner_dest)
2076 || (i1dest && rtx_equal_p (i1dest, inner_dest))
2077 || (i0dest && rtx_equal_p (i0dest, inner_dest)))
2078 && (reg_overlap_mentioned_p (i2dest, inner_dest)
2079 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))
2080 || (i0dest && reg_overlap_mentioned_p (i0dest, inner_dest))))
2082 /* This is the same test done in can_combine_p except we can't test
2083 all_adjacent; we don't have to, since this instruction will stay
2084 in place, thus we are not considering increasing the lifetime of
2087 Also, if this insn sets a function argument, combining it with
2088 something that might need a spill could clobber a previous
2089 function argument; the all_adjacent test in can_combine_p also
2090 checks this; here, we do a more specific test for this case. */
2092 || (REG_P (inner_dest)
2093 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
2094 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
2095 GET_MODE (inner_dest))))
2096 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src))
2097 || (i0_not_in_src && reg_overlap_mentioned_p (i0dest, src)))
2100 /* If DEST is used in I3, it is being killed in this insn, so
2101 record that for later. We have to consider paradoxical
2102 subregs here, since they kill the whole register, but we
2103 ignore partial subregs, STRICT_LOW_PART, etc.
2104 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2105 STACK_POINTER_REGNUM, since these are always considered to be
2106 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2108 if (GET_CODE (subdest) == SUBREG
2109 && (GET_MODE_SIZE (GET_MODE (subdest))
2110 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
2111 subdest = SUBREG_REG (subdest);
2114 && reg_referenced_p (subdest, PATTERN (i3))
2115 && REGNO (subdest) != FRAME_POINTER_REGNUM
2116 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2117 && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
2119 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2120 && (REGNO (subdest) != ARG_POINTER_REGNUM
2121 || ! fixed_regs [REGNO (subdest)])
2123 && REGNO (subdest) != STACK_POINTER_REGNUM)
2125 if (*pi3dest_killed)
2128 *pi3dest_killed = subdest;
2132 else if (GET_CODE (x) == PARALLEL)
2136 for (i = 0; i < XVECLEN (x, 0); i++)
2137 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest, i0dest,
2138 i1_not_in_src, i0_not_in_src, pi3dest_killed))
2145 /* Return 1 if X is an arithmetic expression that contains a multiplication
2146 and division. We don't count multiplications by powers of two here. */
2149 contains_muldiv (rtx x)
2151 switch (GET_CODE (x))
2153 case MOD: case DIV: case UMOD: case UDIV:
2157 return ! (CONST_INT_P (XEXP (x, 1))
2158 && exact_log2 (UINTVAL (XEXP (x, 1))) >= 0);
2161 return contains_muldiv (XEXP (x, 0))
2162 || contains_muldiv (XEXP (x, 1));
2165 return contains_muldiv (XEXP (x, 0));
2171 /* Determine whether INSN can be used in a combination. Return nonzero if
2172 not. This is used in try_combine to detect early some cases where we
2173 can't perform combinations. */
2176 cant_combine_insn_p (rtx insn)
2181 /* If this isn't really an insn, we can't do anything.
2182 This can occur when flow deletes an insn that it has merged into an
2183 auto-increment address. */
2184 if (! INSN_P (insn))
2187 /* Never combine loads and stores involving hard regs that are likely
2188 to be spilled. The register allocator can usually handle such
2189 reg-reg moves by tying. If we allow the combiner to make
2190 substitutions of likely-spilled regs, reload might die.
2191 As an exception, we allow combinations involving fixed regs; these are
2192 not available to the register allocator so there's no risk involved. */
2194 set = single_set (insn);
2197 src = SET_SRC (set);
2198 dest = SET_DEST (set);
2199 if (GET_CODE (src) == SUBREG)
2200 src = SUBREG_REG (src);
2201 if (GET_CODE (dest) == SUBREG)
2202 dest = SUBREG_REG (dest);
2203 if (REG_P (src) && REG_P (dest)
2204 && ((HARD_REGISTER_P (src)
2205 && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (src))
2206 && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src))))
2207 || (HARD_REGISTER_P (dest)
2208 && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (dest))
2209 && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest))))))
2215 struct likely_spilled_retval_info
2217 unsigned regno, nregs;
2221 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2222 hard registers that are known to be written to / clobbered in full. */
2224 likely_spilled_retval_1 (rtx x, const_rtx set, void *data)
2226 struct likely_spilled_retval_info *const info =
2227 (struct likely_spilled_retval_info *) data;
2228 unsigned regno, nregs;
2231 if (!REG_P (XEXP (set, 0)))
2234 if (regno >= info->regno + info->nregs)
2236 nregs = hard_regno_nregs[regno][GET_MODE (x)];
2237 if (regno + nregs <= info->regno)
2239 new_mask = (2U << (nregs - 1)) - 1;
2240 if (regno < info->regno)
2241 new_mask >>= info->regno - regno;
2243 new_mask <<= regno - info->regno;
2244 info->mask &= ~new_mask;
2247 /* Return nonzero iff part of the return value is live during INSN, and
2248 it is likely spilled. This can happen when more than one insn is needed
2249 to copy the return value, e.g. when we consider to combine into the
2250 second copy insn for a complex value. */
2253 likely_spilled_retval_p (rtx insn)
2255 rtx use = BB_END (this_basic_block);
2257 unsigned regno, nregs;
2258 /* We assume here that no machine mode needs more than
2259 32 hard registers when the value overlaps with a register
2260 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2262 struct likely_spilled_retval_info info;
2264 if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
2266 reg = XEXP (PATTERN (use), 0);
2267 if (!REG_P (reg) || !targetm.calls.function_value_regno_p (REGNO (reg)))
2269 regno = REGNO (reg);
2270 nregs = hard_regno_nregs[regno][GET_MODE (reg)];
2273 mask = (2U << (nregs - 1)) - 1;
2275 /* Disregard parts of the return value that are set later. */
2279 for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
2281 note_stores (PATTERN (p), likely_spilled_retval_1, &info);
2284 /* Check if any of the (probably) live return value registers is
2289 if ((mask & 1 << nregs)
2290 && targetm.class_likely_spilled_p (REGNO_REG_CLASS (regno + nregs)))
2296 /* Adjust INSN after we made a change to its destination.
2298 Changing the destination can invalidate notes that say something about
2299 the results of the insn and a LOG_LINK pointing to the insn. */
2302 adjust_for_new_dest (rtx insn)
2304 /* For notes, be conservative and simply remove them. */
2305 remove_reg_equal_equiv_notes (insn);
2307 /* The new insn will have a destination that was previously the destination
2308 of an insn just above it. Call distribute_links to make a LOG_LINK from
2309 the next use of that destination. */
2310 distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX));
2312 df_insn_rescan (insn);
2315 /* Return TRUE if combine can reuse reg X in mode MODE.
2316 ADDED_SETS is nonzero if the original set is still required. */
2318 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
2326 /* Allow hard registers if the new mode is legal, and occupies no more
2327 registers than the old mode. */
2328 if (regno < FIRST_PSEUDO_REGISTER)
2329 return (HARD_REGNO_MODE_OK (regno, mode)
2330 && (hard_regno_nregs[regno][GET_MODE (x)]
2331 >= hard_regno_nregs[regno][mode]));
2333 /* Or a pseudo that is only used once. */
2334 return (REG_N_SETS (regno) == 1 && !added_sets
2335 && !REG_USERVAR_P (x));
2339 /* Check whether X, the destination of a set, refers to part of
2340 the register specified by REG. */
2343 reg_subword_p (rtx x, rtx reg)
2345 /* Check that reg is an integer mode register. */
2346 if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
2349 if (GET_CODE (x) == STRICT_LOW_PART
2350 || GET_CODE (x) == ZERO_EXTRACT)
2353 return GET_CODE (x) == SUBREG
2354 && SUBREG_REG (x) == reg
2355 && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
2359 /* Replace auto-increment addressing modes with explicit operations to access
2360 the same addresses without modifying the corresponding registers. */
2363 cleanup_auto_inc_dec (rtx src, enum machine_mode mem_mode)
2366 const RTX_CODE code = GET_CODE (x);
2382 /* SCRATCH must be shared because they represent distinct values. */
2385 if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
2390 if (shared_const_p (x))
2395 mem_mode = GET_MODE (x);
2400 gcc_assert (mem_mode != VOIDmode && mem_mode != BLKmode);
2401 return gen_rtx_PLUS (GET_MODE (x),
2402 cleanup_auto_inc_dec (XEXP (x, 0), mem_mode),
2403 GEN_INT (code == PRE_INC
2404 ? GET_MODE_SIZE (mem_mode)
2405 : -GET_MODE_SIZE (mem_mode)));
2411 return cleanup_auto_inc_dec (code == PRE_MODIFY
2412 ? XEXP (x, 1) : XEXP (x, 0),
2419 /* Copy the various flags, fields, and other information. We assume
2420 that all fields need copying, and then clear the fields that should
2421 not be copied. That is the sensible default behavior, and forces
2422 us to explicitly document why we are *not* copying a flag. */
2423 x = shallow_copy_rtx (x);
2425 /* We do not copy the USED flag, which is used as a mark bit during
2426 walks over the RTL. */
2427 RTX_FLAG (x, used) = 0;
2429 /* We do not copy FRAME_RELATED for INSNs. */
2431 RTX_FLAG (x, frame_related) = 0;
2433 fmt = GET_RTX_FORMAT (code);
2434 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2436 XEXP (x, i) = cleanup_auto_inc_dec (XEXP (x, i), mem_mode);
2437 else if (fmt[i] == 'E' || fmt[i] == 'V')
2440 XVEC (x, i) = rtvec_alloc (XVECLEN (x, i));
2441 for (j = 0; j < XVECLEN (x, i); j++)
2443 = cleanup_auto_inc_dec (XVECEXP (src, i, j), mem_mode);
2450 /* Auxiliary data structure for propagate_for_debug_stmt. */
2452 struct rtx_subst_pair
2458 /* DATA points to an rtx_subst_pair. Return the value that should be
2462 propagate_for_debug_subst (rtx from, const_rtx old_rtx, void *data)
2464 struct rtx_subst_pair *pair = (struct rtx_subst_pair *)data;
2466 if (!rtx_equal_p (from, old_rtx))
2468 if (!pair->adjusted)
2470 pair->adjusted = true;
2472 pair->to = cleanup_auto_inc_dec (pair->to, VOIDmode);
2474 pair->to = copy_rtx (pair->to);
2476 pair->to = make_compound_operation (pair->to, SET);
2479 return copy_rtx (pair->to);
2482 /* Replace all the occurrences of DEST with SRC in DEBUG_INSNs between INSN
2483 and LAST, not including INSN, but including LAST. Also stop at the end
2484 of THIS_BASIC_BLOCK. */
2487 propagate_for_debug (rtx insn, rtx last, rtx dest, rtx src)
2489 rtx next, loc, end = NEXT_INSN (BB_END (this_basic_block));
2491 struct rtx_subst_pair p;
2495 next = NEXT_INSN (insn);
2496 last = NEXT_INSN (last);
2497 while (next != last && next != end)
2500 next = NEXT_INSN (insn);
2501 if (DEBUG_INSN_P (insn))
2503 loc = simplify_replace_fn_rtx (INSN_VAR_LOCATION_LOC (insn),
2504 dest, propagate_for_debug_subst, &p);
2505 if (loc == INSN_VAR_LOCATION_LOC (insn))
2507 INSN_VAR_LOCATION_LOC (insn) = loc;
2508 df_insn_rescan (insn);
2513 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2514 Note that the INSN should be deleted *after* removing dead edges, so
2515 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2516 but not for a (set (pc) (label_ref FOO)). */
2519 update_cfg_for_uncondjump (rtx insn)
2521 basic_block bb = BLOCK_FOR_INSN (insn);
2522 bool at_end = (BB_END (bb) == insn);
2525 purge_dead_edges (bb);
2528 if (at_end && EDGE_COUNT (bb->succs) == 1)
2532 single_succ_edge (bb)->flags |= EDGE_FALLTHRU;
2534 /* Remove barriers from the footer if there are any. */
2535 for (insn = bb->il.rtl->footer; insn; insn = NEXT_INSN (insn))
2536 if (BARRIER_P (insn))
2538 if (PREV_INSN (insn))
2539 NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
2541 bb->il.rtl->footer = NEXT_INSN (insn);
2542 if (NEXT_INSN (insn))
2543 PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
2545 else if (LABEL_P (insn))
2550 /* Try to combine the insns I0, I1 and I2 into I3.
2551 Here I0, I1 and I2 appear earlier than I3.
2552 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2555 If we are combining more than two insns and the resulting insn is not
2556 recognized, try splitting it into two insns. If that happens, I2 and I3
2557 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2558 Otherwise, I0, I1 and I2 are pseudo-deleted.
2560 Return 0 if the combination does not work. Then nothing is changed.
2561 If we did the combination, return the insn at which combine should
2564 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2565 new direct jump instruction.
2567 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2568 been I3 passed to an earlier try_combine within the same basic
2572 try_combine (rtx i3, rtx i2, rtx i1, rtx i0, int *new_direct_jump_p,
2573 rtx last_combined_insn)
2575 /* New patterns for I3 and I2, respectively. */
2576 rtx newpat, newi2pat = 0;
2577 rtvec newpat_vec_with_clobbers = 0;
2578 int substed_i2 = 0, substed_i1 = 0, substed_i0 = 0;
2579 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2581 int added_sets_0, added_sets_1, added_sets_2;
2582 /* Total number of SETs to put into I3. */
2584 /* Nonzero if I2's or I1's body now appears in I3. */
2585 int i2_is_used = 0, i1_is_used = 0;
2586 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2587 int insn_code_number, i2_code_number = 0, other_code_number = 0;
2588 /* Contains I3 if the destination of I3 is used in its source, which means
2589 that the old life of I3 is being killed. If that usage is placed into
2590 I2 and not in I3, a REG_DEAD note must be made. */
2591 rtx i3dest_killed = 0;
2592 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2593 rtx i2dest = 0, i2src = 0, i1dest = 0, i1src = 0, i0dest = 0, i0src = 0;
2594 /* Copy of SET_SRC of I1 and I0, if needed. */
2595 rtx i1src_copy = 0, i0src_copy = 0, i0src_copy2 = 0;
2596 /* Set if I2DEST was reused as a scratch register. */
2597 bool i2scratch = false;
2598 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2599 rtx i0pat = 0, i1pat = 0, i2pat = 0;
2600 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2601 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
2602 int i0dest_in_i0src = 0, i1dest_in_i0src = 0, i2dest_in_i0src = 0;
2603 int i2dest_killed = 0, i1dest_killed = 0, i0dest_killed = 0;
2604 int i1_feeds_i2_n = 0, i0_feeds_i2_n = 0, i0_feeds_i1_n = 0;
2605 /* Notes that must be added to REG_NOTES in I3 and I2. */
2606 rtx new_i3_notes, new_i2_notes;
2607 /* Notes that we substituted I3 into I2 instead of the normal case. */
2608 int i3_subst_into_i2 = 0;
2609 /* Notes that I1, I2 or I3 is a MULT operation. */
2612 int changed_i3_dest = 0;
2618 rtx new_other_notes;
2621 /* Only try four-insn combinations when there's high likelihood of
2622 success. Look for simple insns, such as loads of constants or
2623 binary operations involving a constant. */
2630 if (!flag_expensive_optimizations)
2633 for (i = 0; i < 4; i++)
2635 rtx insn = i == 0 ? i0 : i == 1 ? i1 : i == 2 ? i2 : i3;
2636 rtx set = single_set (insn);
2640 src = SET_SRC (set);
2641 if (CONSTANT_P (src))
2646 else if (BINARY_P (src) && CONSTANT_P (XEXP (src, 1)))
2648 else if (GET_CODE (src) == ASHIFT || GET_CODE (src) == ASHIFTRT
2649 || GET_CODE (src) == LSHIFTRT)
2652 if (ngood < 2 && nshift < 2)
2656 /* Exit early if one of the insns involved can't be used for
2658 if (cant_combine_insn_p (i3)
2659 || cant_combine_insn_p (i2)
2660 || (i1 && cant_combine_insn_p (i1))
2661 || (i0 && cant_combine_insn_p (i0))
2662 || likely_spilled_retval_p (i3))
2666 undobuf.other_insn = 0;
2668 /* Reset the hard register usage information. */
2669 CLEAR_HARD_REG_SET (newpat_used_regs);
2671 if (dump_file && (dump_flags & TDF_DETAILS))
2674 fprintf (dump_file, "\nTrying %d, %d, %d -> %d:\n",
2675 INSN_UID (i0), INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2677 fprintf (dump_file, "\nTrying %d, %d -> %d:\n",
2678 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2680 fprintf (dump_file, "\nTrying %d -> %d:\n",
2681 INSN_UID (i2), INSN_UID (i3));
2684 /* If multiple insns feed into one of I2 or I3, they can be in any
2685 order. To simplify the code below, reorder them in sequence. */
2686 if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i2))
2687 temp = i2, i2 = i0, i0 = temp;
2688 if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i1))
2689 temp = i1, i1 = i0, i0 = temp;
2690 if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2))
2691 temp = i1, i1 = i2, i2 = temp;
2693 added_links_insn = 0;
2695 /* First check for one important special case that the code below will
2696 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2697 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2698 we may be able to replace that destination with the destination of I3.
2699 This occurs in the common code where we compute both a quotient and
2700 remainder into a structure, in which case we want to do the computation
2701 directly into the structure to avoid register-register copies.
2703 Note that this case handles both multiple sets in I2 and also cases
2704 where I2 has a number of CLOBBERs inside the PARALLEL.
2706 We make very conservative checks below and only try to handle the
2707 most common cases of this. For example, we only handle the case
2708 where I2 and I3 are adjacent to avoid making difficult register
2711 if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
2712 && REG_P (SET_SRC (PATTERN (i3)))
2713 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
2714 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
2715 && GET_CODE (PATTERN (i2)) == PARALLEL
2716 && ! side_effects_p (SET_DEST (PATTERN (i3)))
2717 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2718 below would need to check what is inside (and reg_overlap_mentioned_p
2719 doesn't support those codes anyway). Don't allow those destinations;
2720 the resulting insn isn't likely to be recognized anyway. */
2721 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
2722 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
2723 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
2724 SET_DEST (PATTERN (i3)))
2725 && next_active_insn (i2) == i3)
2727 rtx p2 = PATTERN (i2);
2729 /* Make sure that the destination of I3,
2730 which we are going to substitute into one output of I2,
2731 is not used within another output of I2. We must avoid making this:
2732 (parallel [(set (mem (reg 69)) ...)
2733 (set (reg 69) ...)])
2734 which is not well-defined as to order of actions.
2735 (Besides, reload can't handle output reloads for this.)
2737 The problem can also happen if the dest of I3 is a memory ref,
2738 if another dest in I2 is an indirect memory ref. */
2739 for (i = 0; i < XVECLEN (p2, 0); i++)
2740 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2741 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2742 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
2743 SET_DEST (XVECEXP (p2, 0, i))))
2746 if (i == XVECLEN (p2, 0))
2747 for (i = 0; i < XVECLEN (p2, 0); i++)
2748 if (GET_CODE (XVECEXP (p2, 0, i)) == SET
2749 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
2754 subst_low_luid = DF_INSN_LUID (i2);
2756 added_sets_2 = added_sets_1 = added_sets_0 = 0;
2757 i2src = SET_SRC (XVECEXP (p2, 0, i));
2758 i2dest = SET_DEST (XVECEXP (p2, 0, i));
2759 i2dest_killed = dead_or_set_p (i2, i2dest);
2761 /* Replace the dest in I2 with our dest and make the resulting
2762 insn the new pattern for I3. Then skip to where we validate
2763 the pattern. Everything was set up above. */
2764 SUBST (SET_DEST (XVECEXP (p2, 0, i)), SET_DEST (PATTERN (i3)));
2766 i3_subst_into_i2 = 1;
2767 goto validate_replacement;
2771 /* If I2 is setting a pseudo to a constant and I3 is setting some
2772 sub-part of it to another constant, merge them by making a new
2775 && (temp = single_set (i2)) != 0
2776 && (CONST_INT_P (SET_SRC (temp))
2777 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
2778 && GET_CODE (PATTERN (i3)) == SET
2779 && (CONST_INT_P (SET_SRC (PATTERN (i3)))
2780 || GET_CODE (SET_SRC (PATTERN (i3))) == CONST_DOUBLE)
2781 && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
2783 rtx dest = SET_DEST (PATTERN (i3));
2787 if (GET_CODE (dest) == ZERO_EXTRACT)
2789 if (CONST_INT_P (XEXP (dest, 1))
2790 && CONST_INT_P (XEXP (dest, 2)))
2792 width = INTVAL (XEXP (dest, 1));
2793 offset = INTVAL (XEXP (dest, 2));
2794 dest = XEXP (dest, 0);
2795 if (BITS_BIG_ENDIAN)
2796 offset = GET_MODE_BITSIZE (GET_MODE (dest)) - width - offset;
2801 if (GET_CODE (dest) == STRICT_LOW_PART)
2802 dest = XEXP (dest, 0);
2803 width = GET_MODE_BITSIZE (GET_MODE (dest));
2809 /* If this is the low part, we're done. */
2810 if (subreg_lowpart_p (dest))
2812 /* Handle the case where inner is twice the size of outer. */
2813 else if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2814 == 2 * GET_MODE_BITSIZE (GET_MODE (dest)))
2815 offset += GET_MODE_BITSIZE (GET_MODE (dest));
2816 /* Otherwise give up for now. */
2822 && (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2823 <= HOST_BITS_PER_DOUBLE_INT))
2826 rtx inner = SET_SRC (PATTERN (i3));
2827 rtx outer = SET_SRC (temp);
2829 o = rtx_to_double_int (outer);
2830 i = rtx_to_double_int (inner);
2832 m = double_int_mask (width);
2833 i = double_int_and (i, m);
2834 m = double_int_lshift (m, offset, HOST_BITS_PER_DOUBLE_INT, false);
2835 i = double_int_lshift (i, offset, HOST_BITS_PER_DOUBLE_INT, false);
2836 o = double_int_ior (double_int_and_not (o, m), i);
2840 subst_low_luid = DF_INSN_LUID (i2);
2841 added_sets_2 = added_sets_1 = added_sets_0 = 0;
2842 i2dest = SET_DEST (temp);
2843 i2dest_killed = dead_or_set_p (i2, i2dest);
2845 /* Replace the source in I2 with the new constant and make the
2846 resulting insn the new pattern for I3. Then skip to where we
2847 validate the pattern. Everything was set up above. */
2848 SUBST (SET_SRC (temp),
2849 immed_double_int_const (o, GET_MODE (SET_DEST (temp))));
2851 newpat = PATTERN (i2);
2853 /* The dest of I3 has been replaced with the dest of I2. */
2854 changed_i3_dest = 1;
2855 goto validate_replacement;
2860 /* If we have no I1 and I2 looks like:
2861 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2863 make up a dummy I1 that is
2866 (set (reg:CC X) (compare:CC Y (const_int 0)))
2868 (We can ignore any trailing CLOBBERs.)
2870 This undoes a previous combination and allows us to match a branch-and-
2873 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2874 && XVECLEN (PATTERN (i2), 0) >= 2
2875 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2876 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2878 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2879 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2880 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2881 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2882 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2883 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2885 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2886 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2891 /* We make I1 with the same INSN_UID as I2. This gives it
2892 the same DF_INSN_LUID for value tracking. Our fake I1 will
2893 never appear in the insn stream so giving it the same INSN_UID
2894 as I2 will not cause a problem. */
2896 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
2897 BLOCK_FOR_INSN (i2), XVECEXP (PATTERN (i2), 0, 1),
2898 INSN_LOCATOR (i2), -1, NULL_RTX);
2900 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2901 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2902 SET_DEST (PATTERN (i1)));
2903 SUBST_LINK (LOG_LINKS (i2), alloc_INSN_LIST (i1, LOG_LINKS (i2)));
2908 /* Verify that I2 and I1 are valid for combining. */
2909 if (! can_combine_p (i2, i3, i0, i1, NULL_RTX, NULL_RTX, &i2dest, &i2src)
2910 || (i1 && ! can_combine_p (i1, i3, i0, NULL_RTX, i2, NULL_RTX,
2912 || (i0 && ! can_combine_p (i0, i3, NULL_RTX, NULL_RTX, i1, i2,
2919 /* Record whether I2DEST is used in I2SRC and similarly for the other
2920 cases. Knowing this will help in register status updating below. */
2921 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2922 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2923 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2924 i0dest_in_i0src = i0 && reg_overlap_mentioned_p (i0dest, i0src);
2925 i1dest_in_i0src = i0 && reg_overlap_mentioned_p (i1dest, i0src);
2926 i2dest_in_i0src = i0 && reg_overlap_mentioned_p (i2dest, i0src);
2927 i2dest_killed = dead_or_set_p (i2, i2dest);
2928 i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2929 i0dest_killed = i0 && dead_or_set_p (i0, i0dest);
2931 /* For the earlier insns, determine which of the subsequent ones they
2933 i1_feeds_i2_n = i1 && insn_a_feeds_b (i1, i2);
2934 i0_feeds_i1_n = i0 && insn_a_feeds_b (i0, i1);
2935 i0_feeds_i2_n = (i0 && (!i0_feeds_i1_n ? insn_a_feeds_b (i0, i2)
2936 : (!reg_overlap_mentioned_p (i1dest, i0dest)
2937 && reg_overlap_mentioned_p (i0dest, i2src))));
2939 /* Ensure that I3's pattern can be the destination of combines. */
2940 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest, i0dest,
2941 i1 && i2dest_in_i1src && !i1_feeds_i2_n,
2942 i0 && ((i2dest_in_i0src && !i0_feeds_i2_n)
2943 || (i1dest_in_i0src && !i0_feeds_i1_n)),
2950 /* See if any of the insns is a MULT operation. Unless one is, we will
2951 reject a combination that is, since it must be slower. Be conservative
2953 if (GET_CODE (i2src) == MULT
2954 || (i1 != 0 && GET_CODE (i1src) == MULT)
2955 || (i0 != 0 && GET_CODE (i0src) == MULT)
2956 || (GET_CODE (PATTERN (i3)) == SET
2957 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2960 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2961 We used to do this EXCEPT in one case: I3 has a post-inc in an
2962 output operand. However, that exception can give rise to insns like
2964 which is a famous insn on the PDP-11 where the value of r3 used as the
2965 source was model-dependent. Avoid this sort of thing. */
2968 if (!(GET_CODE (PATTERN (i3)) == SET
2969 && REG_P (SET_SRC (PATTERN (i3)))
2970 && MEM_P (SET_DEST (PATTERN (i3)))
2971 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2972 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2973 /* It's not the exception. */
2976 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2977 if (REG_NOTE_KIND (link) == REG_INC
2978 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2980 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2987 /* See if the SETs in I1 or I2 need to be kept around in the merged
2988 instruction: whenever the value set there is still needed past I3.
2989 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2991 For the SET in I1, we have two cases: If I1 and I2 independently
2992 feed into I3, the set in I1 needs to be kept around if I1DEST dies
2993 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2994 in I1 needs to be kept around unless I1DEST dies or is set in either
2995 I2 or I3. The same consideration applies to I0. */
2997 added_sets_2 = !dead_or_set_p (i3, i2dest);
3000 added_sets_1 = !(dead_or_set_p (i3, i1dest)
3001 || (i1_feeds_i2_n && dead_or_set_p (i2, i1dest)));
3006 added_sets_0 = !(dead_or_set_p (i3, i0dest)
3007 || (i0_feeds_i2_n && dead_or_set_p (i2, i0dest))
3008 || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest)));
3012 /* We are about to copy insns for the case where they need to be kept
3013 around. Check that they can be copied in the merged instruction. */
3015 if (targetm.cannot_copy_insn_p
3016 && ((added_sets_2 && targetm.cannot_copy_insn_p (i2))
3017 || (i1 && added_sets_1 && targetm.cannot_copy_insn_p (i1))
3018 || (i0 && added_sets_0 && targetm.cannot_copy_insn_p (i0))))
3024 /* If the set in I2 needs to be kept around, we must make a copy of
3025 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3026 PATTERN (I2), we are only substituting for the original I1DEST, not into
3027 an already-substituted copy. This also prevents making self-referential
3028 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3033 if (GET_CODE (PATTERN (i2)) == PARALLEL)
3034 i2pat = gen_rtx_SET (VOIDmode, i2dest, copy_rtx (i2src));
3036 i2pat = copy_rtx (PATTERN (i2));
3041 if (GET_CODE (PATTERN (i1)) == PARALLEL)
3042 i1pat = gen_rtx_SET (VOIDmode, i1dest, copy_rtx (i1src));
3044 i1pat = copy_rtx (PATTERN (i1));
3049 if (GET_CODE (PATTERN (i0)) == PARALLEL)
3050 i0pat = gen_rtx_SET (VOIDmode, i0dest, copy_rtx (i0src));
3052 i0pat = copy_rtx (PATTERN (i0));
3057 /* Substitute in the latest insn for the regs set by the earlier ones. */
3059 maxreg = max_reg_num ();
3064 /* Many machines that don't use CC0 have insns that can both perform an
3065 arithmetic operation and set the condition code. These operations will
3066 be represented as a PARALLEL with the first element of the vector
3067 being a COMPARE of an arithmetic operation with the constant zero.
3068 The second element of the vector will set some pseudo to the result
3069 of the same arithmetic operation. If we simplify the COMPARE, we won't
3070 match such a pattern and so will generate an extra insn. Here we test
3071 for this case, where both the comparison and the operation result are
3072 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3073 I2SRC. Later we will make the PARALLEL that contains I2. */
3075 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
3076 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
3077 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
3078 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
3080 #ifdef SELECT_CC_MODE
3082 enum machine_mode compare_mode;
3085 newpat = PATTERN (i3);
3086 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
3090 #ifdef SELECT_CC_MODE
3091 /* See if a COMPARE with the operand we substituted in should be done
3092 with the mode that is currently being used. If not, do the same
3093 processing we do in `subst' for a SET; namely, if the destination
3094 is used only once, try to replace it with a register of the proper
3095 mode and also replace the COMPARE. */
3096 if (undobuf.other_insn == 0
3097 && (cc_use = find_single_use (SET_DEST (newpat), i3,
3098 &undobuf.other_insn))
3099 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
3101 != GET_MODE (SET_DEST (newpat))))
3103 if (can_change_dest_mode (SET_DEST (newpat), added_sets_2,
3106 unsigned int regno = REGNO (SET_DEST (newpat));
3109 if (regno < FIRST_PSEUDO_REGISTER)
3110 new_dest = gen_rtx_REG (compare_mode, regno);
3113 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
3114 new_dest = regno_reg_rtx[regno];
3117 SUBST (SET_DEST (newpat), new_dest);
3118 SUBST (XEXP (*cc_use, 0), new_dest);
3119 SUBST (SET_SRC (newpat),
3120 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
3123 undobuf.other_insn = 0;
3130 /* It is possible that the source of I2 or I1 may be performing
3131 an unneeded operation, such as a ZERO_EXTEND of something
3132 that is known to have the high part zero. Handle that case
3133 by letting subst look at the innermost one of them.
3135 Another way to do this would be to have a function that tries
3136 to simplify a single insn instead of merging two or more
3137 insns. We don't do this because of the potential of infinite
3138 loops and because of the potential extra memory required.
3139 However, doing it the way we are is a bit of a kludge and
3140 doesn't catch all cases.
3142 But only do this if -fexpensive-optimizations since it slows
3143 things down and doesn't usually win.
3145 This is not done in the COMPARE case above because the
3146 unmodified I2PAT is used in the PARALLEL and so a pattern
3147 with a modified I2SRC would not match. */
3149 if (flag_expensive_optimizations)
3151 /* Pass pc_rtx so no substitutions are done, just
3155 subst_low_luid = DF_INSN_LUID (i1);
3156 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
3160 subst_low_luid = DF_INSN_LUID (i2);
3161 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
3165 n_occurrences = 0; /* `subst' counts here */
3166 subst_low_luid = DF_INSN_LUID (i2);
3168 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3169 copy of I2SRC each time we substitute it, in order to avoid creating
3170 self-referential RTL when we will be substituting I1SRC for I1DEST
3171 later. Likewise if I0 feeds into I2, either directly or indirectly
3172 through I1, and I0DEST is in I0SRC. */
3173 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
3174 (i1_feeds_i2_n && i1dest_in_i1src)
3175 || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
3176 && i0dest_in_i0src));
3179 /* Record whether I2's body now appears within I3's body. */
3180 i2_is_used = n_occurrences;
3183 /* If we already got a failure, don't try to do more. Otherwise, try to
3184 substitute I1 if we have it. */
3186 if (i1 && GET_CODE (newpat) != CLOBBER)
3188 /* Check that an autoincrement side-effect on I1 has not been lost.
3189 This happens if I1DEST is mentioned in I2 and dies there, and
3190 has disappeared from the new pattern. */
3191 if ((FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3193 && dead_or_set_p (i2, i1dest)
3194 && !reg_overlap_mentioned_p (i1dest, newpat))
3195 /* Before we can do this substitution, we must redo the test done
3196 above (see detailed comments there) that ensures I1DEST isn't
3197 mentioned in any SETs in NEWPAT that are field assignments. */
3198 || !combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX, NULL_RTX,
3206 subst_low_luid = DF_INSN_LUID (i1);
3208 /* If the following substitution will modify I1SRC, make a copy of it
3209 for the case where it is substituted for I1DEST in I2PAT later. */
3210 if (added_sets_2 && i1_feeds_i2_n)
3211 i1src_copy = copy_rtx (i1src);
3213 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3214 copy of I1SRC each time we substitute it, in order to avoid creating
3215 self-referential RTL when we will be substituting I0SRC for I0DEST
3217 newpat = subst (newpat, i1dest, i1src, 0,
3218 i0_feeds_i1_n && i0dest_in_i0src);
3221 /* Record whether I1's body now appears within I3's body. */
3222 i1_is_used = n_occurrences;
3225 /* Likewise for I0 if we have it. */
3227 if (i0 && GET_CODE (newpat) != CLOBBER)
3229 if ((FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3230 && ((i0_feeds_i2_n && dead_or_set_p (i2, i0dest))
3231 || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest)))
3232 && !reg_overlap_mentioned_p (i0dest, newpat))
3233 || !combinable_i3pat (NULL_RTX, &newpat, i0dest, NULL_RTX, NULL_RTX,
3240 /* If the following substitution will modify I0SRC, make a copy of it
3241 for the case where it is substituted for I0DEST in I1PAT later. */
3242 if (added_sets_1 && i0_feeds_i1_n)
3243 i0src_copy = copy_rtx (i0src);
3244 /* And a copy for I0DEST in I2PAT substitution. */
3245 if (added_sets_2 && ((i0_feeds_i1_n && i1_feeds_i2_n)
3246 || (i0_feeds_i2_n)))
3247 i0src_copy2 = copy_rtx (i0src);
3250 subst_low_luid = DF_INSN_LUID (i0);
3251 newpat = subst (newpat, i0dest, i0src, 0, 0);
3255 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3256 to count all the ways that I2SRC and I1SRC can be used. */
3257 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
3258 && i2_is_used + added_sets_2 > 1)
3259 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3260 && (i1_is_used + added_sets_1 + (added_sets_2 && i1_feeds_i2_n)
3262 || (i0 != 0 && FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3263 && (n_occurrences + added_sets_0
3264 + (added_sets_1 && i0_feeds_i1_n)
3265 + (added_sets_2 && i0_feeds_i2_n)
3267 /* Fail if we tried to make a new register. */
3268 || max_reg_num () != maxreg
3269 /* Fail if we couldn't do something and have a CLOBBER. */
3270 || GET_CODE (newpat) == CLOBBER
3271 /* Fail if this new pattern is a MULT and we didn't have one before
3272 at the outer level. */
3273 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
3280 /* If the actions of the earlier insns must be kept
3281 in addition to substituting them into the latest one,
3282 we must make a new PARALLEL for the latest insn
3283 to hold additional the SETs. */
3285 if (added_sets_0 || added_sets_1 || added_sets_2)
3287 int extra_sets = added_sets_0 + added_sets_1 + added_sets_2;
3290 if (GET_CODE (newpat) == PARALLEL)
3292 rtvec old = XVEC (newpat, 0);
3293 total_sets = XVECLEN (newpat, 0) + extra_sets;
3294 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3295 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
3296 sizeof (old->elem[0]) * old->num_elem);
3301 total_sets = 1 + extra_sets;
3302 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3303 XVECEXP (newpat, 0, 0) = old;
3307 XVECEXP (newpat, 0, --total_sets) = i0pat;
3313 t = subst (t, i0dest, i0src_copy ? i0src_copy : i0src, 0, 0);
3315 XVECEXP (newpat, 0, --total_sets) = t;
3321 t = subst (t, i1dest, i1src_copy ? i1src_copy : i1src, 0,
3322 i0_feeds_i1_n && i0dest_in_i0src);
3323 if ((i0_feeds_i1_n && i1_feeds_i2_n) || i0_feeds_i2_n)
3324 t = subst (t, i0dest, i0src_copy2 ? i0src_copy2 : i0src, 0, 0);
3326 XVECEXP (newpat, 0, --total_sets) = t;
3330 validate_replacement:
3332 /* Note which hard regs this insn has as inputs. */
3333 mark_used_regs_combine (newpat);
3335 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3336 consider splitting this pattern, we might need these clobbers. */
3337 if (i1 && GET_CODE (newpat) == PARALLEL
3338 && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
3340 int len = XVECLEN (newpat, 0);
3342 newpat_vec_with_clobbers = rtvec_alloc (len);
3343 for (i = 0; i < len; i++)
3344 RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
3347 /* Is the result of combination a valid instruction? */
3348 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3350 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
3351 the second SET's destination is a register that is unused and isn't
3352 marked as an instruction that might trap in an EH region. In that case,
3353 we just need the first SET. This can occur when simplifying a divmod
3354 insn. We *must* test for this case here because the code below that
3355 splits two independent SETs doesn't handle this case correctly when it
3356 updates the register status.
3358 It's pointless doing this if we originally had two sets, one from
3359 i3, and one from i2. Combining then splitting the parallel results
3360 in the original i2 again plus an invalid insn (which we delete).
3361 The net effect is only to move instructions around, which makes
3362 debug info less accurate.
3364 Also check the case where the first SET's destination is unused.
3365 That would not cause incorrect code, but does cause an unneeded
3368 if (insn_code_number < 0
3369 && !(added_sets_2 && i1 == 0)
3370 && GET_CODE (newpat) == PARALLEL
3371 && XVECLEN (newpat, 0) == 2
3372 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3373 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3374 && asm_noperands (newpat) < 0)
3376 rtx set0 = XVECEXP (newpat, 0, 0);
3377 rtx set1 = XVECEXP (newpat, 0, 1);
3379 if (((REG_P (SET_DEST (set1))
3380 && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
3381 || (GET_CODE (SET_DEST (set1)) == SUBREG
3382 && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
3383 && insn_nothrow_p (i3)
3384 && !side_effects_p (SET_SRC (set1)))
3387 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3390 else if (((REG_P (SET_DEST (set0))
3391 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
3392 || (GET_CODE (SET_DEST (set0)) == SUBREG
3393 && find_reg_note (i3, REG_UNUSED,
3394 SUBREG_REG (SET_DEST (set0)))))
3395 && insn_nothrow_p (i3)
3396 && !side_effects_p (SET_SRC (set0)))
3399 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3401 if (insn_code_number >= 0)
3402 changed_i3_dest = 1;
3406 /* If we were combining three insns and the result is a simple SET
3407 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3408 insns. There are two ways to do this. It can be split using a
3409 machine-specific method (like when you have an addition of a large
3410 constant) or by combine in the function find_split_point. */
3412 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
3413 && asm_noperands (newpat) < 0)
3415 rtx parallel, m_split, *split;
3417 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3418 use I2DEST as a scratch register will help. In the latter case,
3419 convert I2DEST to the mode of the source of NEWPAT if we can. */
3421 m_split = combine_split_insns (newpat, i3);
3423 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3424 inputs of NEWPAT. */
3426 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3427 possible to try that as a scratch reg. This would require adding
3428 more code to make it work though. */
3430 if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
3432 enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
3434 /* First try to split using the original register as a
3435 scratch register. */
3436 parallel = gen_rtx_PARALLEL (VOIDmode,
3437 gen_rtvec (2, newpat,
3438 gen_rtx_CLOBBER (VOIDmode,
3440 m_split = combine_split_insns (parallel, i3);
3442 /* If that didn't work, try changing the mode of I2DEST if
3445 && new_mode != GET_MODE (i2dest)
3446 && new_mode != VOIDmode
3447 && can_change_dest_mode (i2dest, added_sets_2, new_mode))
3449 enum machine_mode old_mode = GET_MODE (i2dest);
3452 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3453 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
3456 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
3457 ni2dest = regno_reg_rtx[REGNO (i2dest)];
3460 parallel = (gen_rtx_PARALLEL
3462 gen_rtvec (2, newpat,
3463 gen_rtx_CLOBBER (VOIDmode,
3465 m_split = combine_split_insns (parallel, i3);
3468 && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
3472 adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode);
3473 buf = undobuf.undos;
3474 undobuf.undos = buf->next;
3475 buf->next = undobuf.frees;
3476 undobuf.frees = buf;
3480 i2scratch = m_split != 0;
3483 /* If recog_for_combine has discarded clobbers, try to use them
3484 again for the split. */
3485 if (m_split == 0 && newpat_vec_with_clobbers)
3487 parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers);
3488 m_split = combine_split_insns (parallel, i3);
3491 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
3493 m_split = PATTERN (m_split);
3494 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
3495 if (insn_code_number >= 0)
3498 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
3499 && (next_real_insn (i2) == i3
3500 || ! use_crosses_set_p (PATTERN (m_split), DF_INSN_LUID (i2))))
3503 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
3504 newi2pat = PATTERN (m_split);
3506 i3set = single_set (NEXT_INSN (m_split));
3507 i2set = single_set (m_split);
3509 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3511 /* If I2 or I3 has multiple SETs, we won't know how to track
3512 register status, so don't use these insns. If I2's destination
3513 is used between I2 and I3, we also can't use these insns. */
3515 if (i2_code_number >= 0 && i2set && i3set
3516 && (next_real_insn (i2) == i3
3517 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
3518 insn_code_number = recog_for_combine (&newi3pat, i3,
3520 if (insn_code_number >= 0)
3523 /* It is possible that both insns now set the destination of I3.
3524 If so, we must show an extra use of it. */
3526 if (insn_code_number >= 0)
3528 rtx new_i3_dest = SET_DEST (i3set);
3529 rtx new_i2_dest = SET_DEST (i2set);
3531 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
3532 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
3533 || GET_CODE (new_i3_dest) == SUBREG)
3534 new_i3_dest = XEXP (new_i3_dest, 0);
3536 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
3537 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
3538 || GET_CODE (new_i2_dest) == SUBREG)
3539 new_i2_dest = XEXP (new_i2_dest, 0);
3541 if (REG_P (new_i3_dest)
3542 && REG_P (new_i2_dest)
3543 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
3544 INC_REG_N_SETS (REGNO (new_i2_dest), 1);
3548 /* If we can split it and use I2DEST, go ahead and see if that
3549 helps things be recognized. Verify that none of the registers
3550 are set between I2 and I3. */
3551 if (insn_code_number < 0
3552 && (split = find_split_point (&newpat, i3, false)) != 0
3556 /* We need I2DEST in the proper mode. If it is a hard register
3557 or the only use of a pseudo, we can change its mode.
3558 Make sure we don't change a hard register to have a mode that
3559 isn't valid for it, or change the number of registers. */
3560 && (GET_MODE (*split) == GET_MODE (i2dest)
3561 || GET_MODE (*split) == VOIDmode
3562 || can_change_dest_mode (i2dest, added_sets_2,
3564 && (next_real_insn (i2) == i3
3565 || ! use_crosses_set_p (*split, DF_INSN_LUID (i2)))
3566 /* We can't overwrite I2DEST if its value is still used by
3568 && ! reg_referenced_p (i2dest, newpat))
3570 rtx newdest = i2dest;
3571 enum rtx_code split_code = GET_CODE (*split);
3572 enum machine_mode split_mode = GET_MODE (*split);
3573 bool subst_done = false;
3574 newi2pat = NULL_RTX;
3578 /* *SPLIT may be part of I2SRC, so make sure we have the
3579 original expression around for later debug processing.
3580 We should not need I2SRC any more in other cases. */
3581 if (MAY_HAVE_DEBUG_INSNS)
3582 i2src = copy_rtx (i2src);
3586 /* Get NEWDEST as a register in the proper mode. We have already
3587 validated that we can do this. */
3588 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
3590 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3591 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
3594 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
3595 newdest = regno_reg_rtx[REGNO (i2dest)];
3599 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3600 an ASHIFT. This can occur if it was inside a PLUS and hence
3601 appeared to be a memory address. This is a kludge. */
3602 if (split_code == MULT
3603 && CONST_INT_P (XEXP (*split, 1))
3604 && INTVAL (XEXP (*split, 1)) > 0
3605 && (i = exact_log2 (UINTVAL (XEXP (*split, 1)))) >= 0)
3607 SUBST (*split, gen_rtx_ASHIFT (split_mode,
3608 XEXP (*split, 0), GEN_INT (i)));
3609 /* Update split_code because we may not have a multiply
3611 split_code = GET_CODE (*split);
3614 #ifdef INSN_SCHEDULING
3615 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3616 be written as a ZERO_EXTEND. */
3617 if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
3619 #ifdef LOAD_EXTEND_OP
3620 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3621 what it really is. */
3622 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
3624 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
3625 SUBREG_REG (*split)));
3628 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
3629 SUBREG_REG (*split)));
3633 /* Attempt to split binary operators using arithmetic identities. */
3634 if (BINARY_P (SET_SRC (newpat))
3635 && split_mode == GET_MODE (SET_SRC (newpat))
3636 && ! side_effects_p (SET_SRC (newpat)))
3638 rtx setsrc = SET_SRC (newpat);
3639 enum machine_mode mode = GET_MODE (setsrc);
3640 enum rtx_code code = GET_CODE (setsrc);
3641 rtx src_op0 = XEXP (setsrc, 0);
3642 rtx src_op1 = XEXP (setsrc, 1);
3644 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3645 if (rtx_equal_p (src_op0, src_op1))
3647 newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
3648 SUBST (XEXP (setsrc, 0), newdest);
3649 SUBST (XEXP (setsrc, 1), newdest);
3652 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3653 else if ((code == PLUS || code == MULT)
3654 && GET_CODE (src_op0) == code
3655 && GET_CODE (XEXP (src_op0, 0)) == code
3656 && (INTEGRAL_MODE_P (mode)
3657 || (FLOAT_MODE_P (mode)
3658 && flag_unsafe_math_optimizations)))
3660 rtx p = XEXP (XEXP (src_op0, 0), 0);
3661 rtx q = XEXP (XEXP (src_op0, 0), 1);
3662 rtx r = XEXP (src_op0, 1);
3665 /* Split both "((X op Y) op X) op Y" and
3666 "((X op Y) op Y) op X" as "T op T" where T is
3668 if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
3669 || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
3671 newi2pat = gen_rtx_SET (VOIDmode, newdest,
3673 SUBST (XEXP (setsrc, 0), newdest);
3674 SUBST (XEXP (setsrc, 1), newdest);
3677 /* Split "((X op X) op Y) op Y)" as "T op T" where
3679 else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
3681 rtx tmp = simplify_gen_binary (code, mode, p, r);
3682 newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
3683 SUBST (XEXP (setsrc, 0), newdest);
3684 SUBST (XEXP (setsrc, 1), newdest);
3692 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
3693 SUBST (*split, newdest);
3696 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3698 /* recog_for_combine might have added CLOBBERs to newi2pat.
3699 Make sure NEWPAT does not depend on the clobbered regs. */
3700 if (GET_CODE (newi2pat) == PARALLEL)
3701 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3702 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3704 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3705 if (reg_overlap_mentioned_p (reg, newpat))
3712 /* If the split point was a MULT and we didn't have one before,
3713 don't use one now. */
3714 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
3715 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3719 /* Check for a case where we loaded from memory in a narrow mode and
3720 then sign extended it, but we need both registers. In that case,
3721 we have a PARALLEL with both loads from the same memory location.
3722 We can split this into a load from memory followed by a register-register
3723 copy. This saves at least one insn, more if register allocation can
3726 We cannot do this if the destination of the first assignment is a
3727 condition code register or cc0. We eliminate this case by making sure
3728 the SET_DEST and SET_SRC have the same mode.
3730 We cannot do this if the destination of the second assignment is
3731 a register that we have already assumed is zero-extended. Similarly
3732 for a SUBREG of such a register. */
3734 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3735 && GET_CODE (newpat) == PARALLEL
3736 && XVECLEN (newpat, 0) == 2
3737 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3738 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
3739 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
3740 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
3741 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3742 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3743 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
3744 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3746 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3747 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3748 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
3750 && VEC_index (reg_stat_type, reg_stat,
3751 REGNO (temp))->nonzero_bits != 0
3752 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3753 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3754 && (VEC_index (reg_stat_type, reg_stat,
3755 REGNO (temp))->nonzero_bits
3756 != GET_MODE_MASK (word_mode))))
3757 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
3758 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
3760 && VEC_index (reg_stat_type, reg_stat,
3761 REGNO (temp))->nonzero_bits != 0
3762 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3763 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3764 && (VEC_index (reg_stat_type, reg_stat,
3765 REGNO (temp))->nonzero_bits
3766 != GET_MODE_MASK (word_mode)))))
3767 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3768 SET_SRC (XVECEXP (newpat, 0, 1)))
3769 && ! find_reg_note (i3, REG_UNUSED,
3770 SET_DEST (XVECEXP (newpat, 0, 0))))
3774 newi2pat = XVECEXP (newpat, 0, 0);
3775 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
3776 newpat = XVECEXP (newpat, 0, 1);
3777 SUBST (SET_SRC (newpat),
3778 gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
3779 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3781 if (i2_code_number >= 0)
3782 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3784 if (insn_code_number >= 0)
3788 /* Similarly, check for a case where we have a PARALLEL of two independent
3789 SETs but we started with three insns. In this case, we can do the sets
3790 as two separate insns. This case occurs when some SET allows two
3791 other insns to combine, but the destination of that SET is still live. */
3793 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3794 && GET_CODE (newpat) == PARALLEL
3795 && XVECLEN (newpat, 0) == 2
3796 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3797 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
3798 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
3799 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3800 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3801 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3802 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3803 XVECEXP (newpat, 0, 0))
3804 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
3805 XVECEXP (newpat, 0, 1))
3806 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
3807 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
3809 /* Normally, it doesn't matter which of the two is done first,
3810 but the one that references cc0 can't be the second, and
3811 one which uses any regs/memory set in between i2 and i3 can't
3813 if (!use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3816 && !reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0))
3820 newi2pat = XVECEXP (newpat, 0, 1);
3821 newpat = XVECEXP (newpat, 0, 0);
3823 else if (!use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 0)),
3826 && !reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 1))
3830 newi2pat = XVECEXP (newpat, 0, 0);
3831 newpat = XVECEXP (newpat, 0, 1);
3839 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3841 if (i2_code_number >= 0)
3843 /* recog_for_combine might have added CLOBBERs to newi2pat.
3844 Make sure NEWPAT does not depend on the clobbered regs. */
3845 if (GET_CODE (newi2pat) == PARALLEL)
3847 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3848 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3850 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3851 if (reg_overlap_mentioned_p (reg, newpat))
3859 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3863 /* If it still isn't recognized, fail and change things back the way they
3865 if ((insn_code_number < 0
3866 /* Is the result a reasonable ASM_OPERANDS? */
3867 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
3873 /* If we had to change another insn, make sure it is valid also. */
3874 if (undobuf.other_insn)
3876 CLEAR_HARD_REG_SET (newpat_used_regs);
3878 other_pat = PATTERN (undobuf.other_insn);
3879 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
3882 if (other_code_number < 0 && ! check_asm_operands (other_pat))
3890 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3891 they are adjacent to each other or not. */
3893 rtx p = prev_nonnote_insn (i3);
3894 if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
3895 && sets_cc0_p (newi2pat))
3903 /* Only allow this combination if insn_rtx_costs reports that the
3904 replacement instructions are cheaper than the originals. */
3905 if (!combine_validate_cost (i0, i1, i2, i3, newpat, newi2pat, other_pat))
3911 if (MAY_HAVE_DEBUG_INSNS)
3915 for (undo = undobuf.undos; undo; undo = undo->next)
3916 if (undo->kind == UNDO_MODE)
3918 rtx reg = *undo->where.r;
3919 enum machine_mode new_mode = GET_MODE (reg);
3920 enum machine_mode old_mode = undo->old_contents.m;
3922 /* Temporarily revert mode back. */
3923 adjust_reg_mode (reg, old_mode);
3925 if (reg == i2dest && i2scratch)
3927 /* If we used i2dest as a scratch register with a
3928 different mode, substitute it for the original
3929 i2src while its original mode is temporarily
3930 restored, and then clear i2scratch so that we don't
3931 do it again later. */
3932 propagate_for_debug (i2, last_combined_insn, reg, i2src);
3934 /* Put back the new mode. */
3935 adjust_reg_mode (reg, new_mode);
3939 rtx tempreg = gen_raw_REG (old_mode, REGNO (reg));
3945 last = last_combined_insn;
3950 last = undobuf.other_insn;
3952 if (DF_INSN_LUID (last)
3953 < DF_INSN_LUID (last_combined_insn))
3954 last = last_combined_insn;
3957 /* We're dealing with a reg that changed mode but not
3958 meaning, so we want to turn it into a subreg for
3959 the new mode. However, because of REG sharing and
3960 because its mode had already changed, we have to do
3961 it in two steps. First, replace any debug uses of
3962 reg, with its original mode temporarily restored,
3963 with this copy we have created; then, replace the
3964 copy with the SUBREG of the original shared reg,
3965 once again changed to the new mode. */
3966 propagate_for_debug (first, last, reg, tempreg);
3967 adjust_reg_mode (reg, new_mode);
3968 propagate_for_debug (first, last, tempreg,
3969 lowpart_subreg (old_mode, reg, new_mode));
3974 /* If we will be able to accept this, we have made a
3975 change to the destination of I3. This requires us to
3976 do a few adjustments. */
3978 if (changed_i3_dest)
3980 PATTERN (i3) = newpat;
3981 adjust_for_new_dest (i3);
3984 /* We now know that we can do this combination. Merge the insns and
3985 update the status of registers and LOG_LINKS. */
3987 if (undobuf.other_insn)
3991 PATTERN (undobuf.other_insn) = other_pat;
3993 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
3994 are still valid. Then add any non-duplicate notes added by
3995 recog_for_combine. */
3996 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
3998 next = XEXP (note, 1);
4000 if (REG_NOTE_KIND (note) == REG_UNUSED
4001 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
4002 remove_note (undobuf.other_insn, note);
4005 distribute_notes (new_other_notes, undobuf.other_insn,
4006 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX,
4016 /* I3 now uses what used to be its destination and which is now
4017 I2's destination. This requires us to do a few adjustments. */
4018 PATTERN (i3) = newpat;
4019 adjust_for_new_dest (i3);
4021 /* We need a LOG_LINK from I3 to I2. But we used to have one,
4024 However, some later insn might be using I2's dest and have
4025 a LOG_LINK pointing at I3. We must remove this link.
4026 The simplest way to remove the link is to point it at I1,
4027 which we know will be a NOTE. */
4029 /* newi2pat is usually a SET here; however, recog_for_combine might
4030 have added some clobbers. */
4031 if (GET_CODE (newi2pat) == PARALLEL)
4032 ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
4034 ni2dest = SET_DEST (newi2pat);
4036 for (insn = NEXT_INSN (i3);
4037 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
4038 || insn != BB_HEAD (this_basic_block->next_bb));
4039 insn = NEXT_INSN (insn))
4041 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
4043 for (link = LOG_LINKS (insn); link;
4044 link = XEXP (link, 1))
4045 if (XEXP (link, 0) == i3)
4046 XEXP (link, 0) = i1;
4054 rtx i3notes, i2notes, i1notes = 0, i0notes = 0;
4055 rtx i3links, i2links, i1links = 0, i0links = 0;
4059 /* Compute which registers we expect to eliminate. newi2pat may be setting
4060 either i3dest or i2dest, so we must check it. Also, i1dest may be the
4061 same as i3dest, in which case newi2pat may be setting i1dest. */
4062 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
4063 || i2dest_in_i2src || i2dest_in_i1src || i2dest_in_i0src
4066 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src || i1dest_in_i0src
4067 || (newi2pat && reg_set_p (i1dest, newi2pat))
4070 rtx elim_i0 = (i0 == 0 || i0dest_in_i0src
4071 || (newi2pat && reg_set_p (i0dest, newi2pat))
4075 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4077 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
4078 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
4080 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
4082 i0notes = REG_NOTES (i0), i0links = LOG_LINKS (i0);
4084 /* Ensure that we do not have something that should not be shared but
4085 occurs multiple times in the new insns. Check this by first
4086 resetting all the `used' flags and then copying anything is shared. */
4088 reset_used_flags (i3notes);
4089 reset_used_flags (i2notes);
4090 reset_used_flags (i1notes);
4091 reset_used_flags (i0notes);
4092 reset_used_flags (newpat);
4093 reset_used_flags (newi2pat);
4094 if (undobuf.other_insn)
4095 reset_used_flags (PATTERN (undobuf.other_insn));
4097 i3notes = copy_rtx_if_shared (i3notes);
4098 i2notes = copy_rtx_if_shared (i2notes);
4099 i1notes = copy_rtx_if_shared (i1notes);
4100 i0notes = copy_rtx_if_shared (i0notes);
4101 newpat = copy_rtx_if_shared (newpat);
4102 newi2pat = copy_rtx_if_shared (newi2pat);
4103 if (undobuf.other_insn)
4104 reset_used_flags (PATTERN (undobuf.other_insn));
4106 INSN_CODE (i3) = insn_code_number;
4107 PATTERN (i3) = newpat;
4109 if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
4111 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
4113 reset_used_flags (call_usage);
4114 call_usage = copy_rtx (call_usage);
4118 /* I2SRC must still be meaningful at this point. Some splitting
4119 operations can invalidate I2SRC, but those operations do not
4122 replace_rtx (call_usage, i2dest, i2src);
4126 replace_rtx (call_usage, i1dest, i1src);
4128 replace_rtx (call_usage, i0dest, i0src);
4130 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
4133 if (undobuf.other_insn)
4134 INSN_CODE (undobuf.other_insn) = other_code_number;
4136 /* We had one special case above where I2 had more than one set and
4137 we replaced a destination of one of those sets with the destination
4138 of I3. In that case, we have to update LOG_LINKS of insns later
4139 in this basic block. Note that this (expensive) case is rare.
4141 Also, in this case, we must pretend that all REG_NOTEs for I2
4142 actually came from I3, so that REG_UNUSED notes from I2 will be
4143 properly handled. */
4145 if (i3_subst_into_i2)
4147 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
4148 if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
4149 || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
4150 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
4151 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
4152 && ! find_reg_note (i2, REG_UNUSED,
4153 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
4154 for (temp = NEXT_INSN (i2);
4155 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
4156 || BB_HEAD (this_basic_block) != temp);
4157 temp = NEXT_INSN (temp))
4158 if (temp != i3 && INSN_P (temp))
4159 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
4160 if (XEXP (link, 0) == i2)
4161 XEXP (link, 0) = i3;
4166 while (XEXP (link, 1))
4167 link = XEXP (link, 1);
4168 XEXP (link, 1) = i2notes;
4182 if (MAY_HAVE_DEBUG_INSNS && i2scratch)
4183 propagate_for_debug (i2, last_combined_insn, i2dest, i2src);
4184 INSN_CODE (i2) = i2_code_number;
4185 PATTERN (i2) = newi2pat;
4189 if (MAY_HAVE_DEBUG_INSNS && i2src)
4190 propagate_for_debug (i2, last_combined_insn, i2dest, i2src);
4191 SET_INSN_DELETED (i2);
4198 if (MAY_HAVE_DEBUG_INSNS)
4199 propagate_for_debug (i1, last_combined_insn, i1dest, i1src);
4200 SET_INSN_DELETED (i1);
4207 if (MAY_HAVE_DEBUG_INSNS)
4208 propagate_for_debug (i0, last_combined_insn, i0dest, i0src);
4209 SET_INSN_DELETED (i0);
4212 /* Get death notes for everything that is now used in either I3 or
4213 I2 and used to die in a previous insn. If we built two new
4214 patterns, move from I1 to I2 then I2 to I3 so that we get the
4215 proper movement on registers that I2 modifies. */
4218 from_luid = DF_INSN_LUID (i0);
4220 from_luid = DF_INSN_LUID (i1);
4222 from_luid = DF_INSN_LUID (i2);
4224 move_deaths (newi2pat, NULL_RTX, from_luid, i2, &midnotes);
4225 move_deaths (newpat, newi2pat, from_luid, i3, &midnotes);
4227 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4229 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
4230 elim_i2, elim_i1, elim_i0);
4232 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
4233 elim_i2, elim_i1, elim_i0);
4235 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
4236 elim_i2, elim_i1, elim_i0);
4238 distribute_notes (i0notes, i0, i3, newi2pat ? i2 : NULL_RTX,
4239 elim_i2, elim_i1, elim_i0);
4241 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4242 elim_i2, elim_i1, elim_i0);
4244 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4245 know these are REG_UNUSED and want them to go to the desired insn,
4246 so we always pass it as i3. */
4248 if (newi2pat && new_i2_notes)
4249 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX,
4253 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX,
4256 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4257 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4258 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4259 in that case, it might delete I2. Similarly for I2 and I1.
4260 Show an additional death due to the REG_DEAD note we make here. If
4261 we discard it in distribute_notes, we will decrement it again. */
4265 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
4266 distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
4268 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1, elim_i0);
4270 distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
4272 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4273 elim_i2, elim_i1, elim_i0);
4276 if (i2dest_in_i2src)
4278 rtx new_note = alloc_reg_note (REG_DEAD, i2dest, NULL_RTX);
4279 if (newi2pat && reg_set_p (i2dest, newi2pat))
4280 distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4281 NULL_RTX, NULL_RTX);
4283 distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4284 NULL_RTX, NULL_RTX, NULL_RTX);
4287 if (i1dest_in_i1src)
4289 rtx new_note = alloc_reg_note (REG_DEAD, i1dest, NULL_RTX);
4290 if (newi2pat && reg_set_p (i1dest, newi2pat))
4291 distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4292 NULL_RTX, NULL_RTX);
4294 distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4295 NULL_RTX, NULL_RTX, NULL_RTX);
4298 if (i0dest_in_i0src)
4300 rtx new_note = alloc_reg_note (REG_DEAD, i0dest, NULL_RTX);
4301 if (newi2pat && reg_set_p (i0dest, newi2pat))
4302 distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4303 NULL_RTX, NULL_RTX);
4305 distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4306 NULL_RTX, NULL_RTX, NULL_RTX);
4309 distribute_links (i3links);
4310 distribute_links (i2links);
4311 distribute_links (i1links);
4312 distribute_links (i0links);
4317 rtx i2_insn = 0, i2_val = 0, set;
4319 /* The insn that used to set this register doesn't exist, and
4320 this life of the register may not exist either. See if one of
4321 I3's links points to an insn that sets I2DEST. If it does,
4322 that is now the last known value for I2DEST. If we don't update
4323 this and I2 set the register to a value that depended on its old
4324 contents, we will get confused. If this insn is used, thing
4325 will be set correctly in combine_instructions. */
4327 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
4328 if ((set = single_set (XEXP (link, 0))) != 0
4329 && rtx_equal_p (i2dest, SET_DEST (set)))
4330 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
4332 record_value_for_reg (i2dest, i2_insn, i2_val);
4334 /* If the reg formerly set in I2 died only once and that was in I3,
4335 zero its use count so it won't make `reload' do any work. */
4337 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
4338 && ! i2dest_in_i2src)
4340 regno = REGNO (i2dest);
4341 INC_REG_N_SETS (regno, -1);
4345 if (i1 && REG_P (i1dest))
4348 rtx i1_insn = 0, i1_val = 0, set;
4350 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
4351 if ((set = single_set (XEXP (link, 0))) != 0
4352 && rtx_equal_p (i1dest, SET_DEST (set)))
4353 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
4355 record_value_for_reg (i1dest, i1_insn, i1_val);
4357 regno = REGNO (i1dest);
4358 if (! added_sets_1 && ! i1dest_in_i1src)
4359 INC_REG_N_SETS (regno, -1);
4362 if (i0 && REG_P (i0dest))
4365 rtx i0_insn = 0, i0_val = 0, set;
4367 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
4368 if ((set = single_set (XEXP (link, 0))) != 0
4369 && rtx_equal_p (i0dest, SET_DEST (set)))
4370 i0_insn = XEXP (link, 0), i0_val = SET_SRC (set);
4372 record_value_for_reg (i0dest, i0_insn, i0_val);
4374 regno = REGNO (i0dest);
4375 if (! added_sets_0 && ! i0dest_in_i0src)
4376 INC_REG_N_SETS (regno, -1);
4379 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4380 been made to this insn. The order of
4381 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
4382 can affect nonzero_bits of newpat */
4384 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
4385 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
4388 if (undobuf.other_insn != NULL_RTX)
4392 fprintf (dump_file, "modifying other_insn ");
4393 dump_insn_slim (dump_file, undobuf.other_insn);
4395 df_insn_rescan (undobuf.other_insn);
4398 if (i0 && !(NOTE_P(i0) && (NOTE_KIND (i0) == NOTE_INSN_DELETED)))
4402 fprintf (dump_file, "modifying insn i1 ");
4403 dump_insn_slim (dump_file, i0);
4405 df_insn_rescan (i0);
4408 if (i1 && !(NOTE_P(i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED)))
4412 fprintf (dump_file, "modifying insn i1 ");
4413 dump_insn_slim (dump_file, i1);
4415 df_insn_rescan (i1);
4418 if (i2 && !(NOTE_P(i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED)))
4422 fprintf (dump_file, "modifying insn i2 ");
4423 dump_insn_slim (dump_file, i2);
4425 df_insn_rescan (i2);
4428 if (i3 && !(NOTE_P(i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED)))
4432 fprintf (dump_file, "modifying insn i3 ");
4433 dump_insn_slim (dump_file, i3);
4435 df_insn_rescan (i3);
4438 /* Set new_direct_jump_p if a new return or simple jump instruction
4439 has been created. Adjust the CFG accordingly. */
4441 if (returnjump_p (i3) || any_uncondjump_p (i3))
4443 *new_direct_jump_p = 1;
4444 mark_jump_label (PATTERN (i3), i3, 0);
4445 update_cfg_for_uncondjump (i3);
4448 if (undobuf.other_insn != NULL_RTX
4449 && (returnjump_p (undobuf.other_insn)
4450 || any_uncondjump_p (undobuf.other_insn)))
4452 *new_direct_jump_p = 1;
4453 update_cfg_for_uncondjump (undobuf.other_insn);
4456 /* A noop might also need cleaning up of CFG, if it comes from the
4457 simplification of a jump. */
4458 if (GET_CODE (newpat) == SET
4459 && SET_SRC (newpat) == pc_rtx
4460 && SET_DEST (newpat) == pc_rtx)
4462 *new_direct_jump_p = 1;
4463 update_cfg_for_uncondjump (i3);
4466 if (undobuf.other_insn != NULL_RTX
4467 && GET_CODE (PATTERN (undobuf.other_insn)) == SET
4468 && SET_SRC (PATTERN (undobuf.other_insn)) == pc_rtx
4469 && SET_DEST (PATTERN (undobuf.other_insn)) == pc_rtx)
4471 *new_direct_jump_p = 1;
4472 update_cfg_for_uncondjump (undobuf.other_insn);
4475 combine_successes++;
4478 if (added_links_insn
4479 && (newi2pat == 0 || DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i2))
4480 && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i3))
4481 return added_links_insn;
4483 return newi2pat ? i2 : i3;
4486 /* Undo all the modifications recorded in undobuf. */
4491 struct undo *undo, *next;
4493 for (undo = undobuf.undos; undo; undo = next)
4499 *undo->where.r = undo->old_contents.r;
4502 *undo->where.i = undo->old_contents.i;
4505 adjust_reg_mode (*undo->where.r, undo->old_contents.m);
4509 *undo->where.r = undo->old_contents.r;
4516 undo->next = undobuf.frees;
4517 undobuf.frees = undo;
4523 /* We've committed to accepting the changes we made. Move all
4524 of the undos to the free list. */
4529 struct undo *undo, *next;
4531 for (undo = undobuf.undos; undo; undo = next)
4534 undo->next = undobuf.frees;
4535 undobuf.frees = undo;
4540 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4541 where we have an arithmetic expression and return that point. LOC will
4544 try_combine will call this function to see if an insn can be split into
4548 find_split_point (rtx *loc, rtx insn, bool set_src)
4551 enum rtx_code code = GET_CODE (x);
4553 unsigned HOST_WIDE_INT len = 0;
4554 HOST_WIDE_INT pos = 0;
4556 rtx inner = NULL_RTX;
4558 /* First special-case some codes. */
4562 #ifdef INSN_SCHEDULING
4563 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4565 if (MEM_P (SUBREG_REG (x)))
4568 return find_split_point (&SUBREG_REG (x), insn, false);
4572 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4573 using LO_SUM and HIGH. */
4574 if (GET_CODE (XEXP (x, 0)) == CONST
4575 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
4577 enum machine_mode address_mode
4578 = targetm.addr_space.address_mode (MEM_ADDR_SPACE (x));
4581 gen_rtx_LO_SUM (address_mode,
4582 gen_rtx_HIGH (address_mode, XEXP (x, 0)),
4584 return &XEXP (XEXP (x, 0), 0);
4588 /* If we have a PLUS whose second operand is a constant and the
4589 address is not valid, perhaps will can split it up using
4590 the machine-specific way to split large constants. We use
4591 the first pseudo-reg (one of the virtual regs) as a placeholder;
4592 it will not remain in the result. */
4593 if (GET_CODE (XEXP (x, 0)) == PLUS
4594 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
4595 && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4596 MEM_ADDR_SPACE (x)))
4598 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
4599 rtx seq = combine_split_insns (gen_rtx_SET (VOIDmode, reg,
4603 /* This should have produced two insns, each of which sets our
4604 placeholder. If the source of the second is a valid address,
4605 we can make put both sources together and make a split point
4609 && NEXT_INSN (seq) != NULL_RTX
4610 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
4611 && NONJUMP_INSN_P (seq)
4612 && GET_CODE (PATTERN (seq)) == SET
4613 && SET_DEST (PATTERN (seq)) == reg
4614 && ! reg_mentioned_p (reg,
4615 SET_SRC (PATTERN (seq)))
4616 && NONJUMP_INSN_P (NEXT_INSN (seq))
4617 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
4618 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
4619 && memory_address_addr_space_p
4620 (GET_MODE (x), SET_SRC (PATTERN (NEXT_INSN (seq))),
4621 MEM_ADDR_SPACE (x)))
4623 rtx src1 = SET_SRC (PATTERN (seq));
4624 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
4626 /* Replace the placeholder in SRC2 with SRC1. If we can
4627 find where in SRC2 it was placed, that can become our
4628 split point and we can replace this address with SRC2.
4629 Just try two obvious places. */
4631 src2 = replace_rtx (src2, reg, src1);
4633 if (XEXP (src2, 0) == src1)
4634 split = &XEXP (src2, 0);
4635 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
4636 && XEXP (XEXP (src2, 0), 0) == src1)
4637 split = &XEXP (XEXP (src2, 0), 0);
4641 SUBST (XEXP (x, 0), src2);
4646 /* If that didn't work, perhaps the first operand is complex and
4647 needs to be computed separately, so make a split point there.
4648 This will occur on machines that just support REG + CONST
4649 and have a constant moved through some previous computation. */
4651 else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
4652 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4653 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4654 return &XEXP (XEXP (x, 0), 0);
4657 /* If we have a PLUS whose first operand is complex, try computing it
4658 separately by making a split there. */
4659 if (GET_CODE (XEXP (x, 0)) == PLUS
4660 && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4662 && ! OBJECT_P (XEXP (XEXP (x, 0), 0))
4663 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4664 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4665 return &XEXP (XEXP (x, 0), 0);
4670 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4671 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4672 we need to put the operand into a register. So split at that
4675 if (SET_DEST (x) == cc0_rtx
4676 && GET_CODE (SET_SRC (x)) != COMPARE
4677 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
4678 && !OBJECT_P (SET_SRC (x))
4679 && ! (GET_CODE (SET_SRC (x)) == SUBREG
4680 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
4681 return &SET_SRC (x);
4684 /* See if we can split SET_SRC as it stands. */
4685 split = find_split_point (&SET_SRC (x), insn, true);
4686 if (split && split != &SET_SRC (x))
4689 /* See if we can split SET_DEST as it stands. */
4690 split = find_split_point (&SET_DEST (x), insn, false);
4691 if (split && split != &SET_DEST (x))
4694 /* See if this is a bitfield assignment with everything constant. If
4695 so, this is an IOR of an AND, so split it into that. */
4696 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
4697 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
4698 <= HOST_BITS_PER_WIDE_INT)
4699 && CONST_INT_P (XEXP (SET_DEST (x), 1))
4700 && CONST_INT_P (XEXP (SET_DEST (x), 2))
4701 && CONST_INT_P (SET_SRC (x))
4702 && ((INTVAL (XEXP (SET_DEST (x), 1))
4703 + INTVAL (XEXP (SET_DEST (x), 2)))
4704 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
4705 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
4707 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
4708 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
4709 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
4710 rtx dest = XEXP (SET_DEST (x), 0);
4711 enum machine_mode mode = GET_MODE (dest);
4712 unsigned HOST_WIDE_INT mask
4713 = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
4716 if (BITS_BIG_ENDIAN)
4717 pos = GET_MODE_BITSIZE (mode) - len - pos;
4719 or_mask = gen_int_mode (src << pos, mode);
4722 simplify_gen_binary (IOR, mode, dest, or_mask));
4725 rtx negmask = gen_int_mode (~(mask << pos), mode);
4727 simplify_gen_binary (IOR, mode,
4728 simplify_gen_binary (AND, mode,
4733 SUBST (SET_DEST (x), dest);
4735 split = find_split_point (&SET_SRC (x), insn, true);
4736 if (split && split != &SET_SRC (x))
4740 /* Otherwise, see if this is an operation that we can split into two.
4741 If so, try to split that. */
4742 code = GET_CODE (SET_SRC (x));
4747 /* If we are AND'ing with a large constant that is only a single
4748 bit and the result is only being used in a context where we
4749 need to know if it is zero or nonzero, replace it with a bit
4750 extraction. This will avoid the large constant, which might
4751 have taken more than one insn to make. If the constant were
4752 not a valid argument to the AND but took only one insn to make,
4753 this is no worse, but if it took more than one insn, it will
4756 if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4757 && REG_P (XEXP (SET_SRC (x), 0))
4758 && (pos = exact_log2 (UINTVAL (XEXP (SET_SRC (x), 1)))) >= 7
4759 && REG_P (SET_DEST (x))
4760 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
4761 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
4762 && XEXP (*split, 0) == SET_DEST (x)
4763 && XEXP (*split, 1) == const0_rtx)
4765 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
4766 XEXP (SET_SRC (x), 0),
4767 pos, NULL_RTX, 1, 1, 0, 0);
4768 if (extraction != 0)
4770 SUBST (SET_SRC (x), extraction);
4771 return find_split_point (loc, insn, false);
4777 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4778 is known to be on, this can be converted into a NEG of a shift. */
4779 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
4780 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
4781 && 1 <= (pos = exact_log2
4782 (nonzero_bits (XEXP (SET_SRC (x), 0),
4783 GET_MODE (XEXP (SET_SRC (x), 0))))))
4785 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
4789 gen_rtx_LSHIFTRT (mode,
4790 XEXP (SET_SRC (x), 0),
4793 split = find_split_point (&SET_SRC (x), insn, true);
4794 if (split && split != &SET_SRC (x))
4800 inner = XEXP (SET_SRC (x), 0);
4802 /* We can't optimize if either mode is a partial integer
4803 mode as we don't know how many bits are significant
4805 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
4806 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
4810 len = GET_MODE_BITSIZE (GET_MODE (inner));
4816 if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4817 && CONST_INT_P (XEXP (SET_SRC (x), 2)))
4819 inner = XEXP (SET_SRC (x), 0);
4820 len = INTVAL (XEXP (SET_SRC (x), 1));
4821 pos = INTVAL (XEXP (SET_SRC (x), 2));
4823 if (BITS_BIG_ENDIAN)
4824 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
4825 unsignedp = (code == ZERO_EXTRACT);
4833 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
4835 enum machine_mode mode = GET_MODE (SET_SRC (x));
4837 /* For unsigned, we have a choice of a shift followed by an
4838 AND or two shifts. Use two shifts for field sizes where the
4839 constant might be too large. We assume here that we can
4840 always at least get 8-bit constants in an AND insn, which is
4841 true for every current RISC. */
4843 if (unsignedp && len <= 8)
4848 (mode, gen_lowpart (mode, inner),
4850 GEN_INT (((unsigned HOST_WIDE_INT) 1 << len)
4853 split = find_split_point (&SET_SRC (x), insn, true);
4854 if (split && split != &SET_SRC (x))
4861 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
4862 gen_rtx_ASHIFT (mode,
4863 gen_lowpart (mode, inner),
4864 GEN_INT (GET_MODE_BITSIZE (mode)
4866 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
4868 split = find_split_point (&SET_SRC (x), insn, true);
4869 if (split && split != &SET_SRC (x))
4874 /* See if this is a simple operation with a constant as the second
4875 operand. It might be that this constant is out of range and hence
4876 could be used as a split point. */
4877 if (BINARY_P (SET_SRC (x))
4878 && CONSTANT_P (XEXP (SET_SRC (x), 1))
4879 && (OBJECT_P (XEXP (SET_SRC (x), 0))
4880 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
4881 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
4882 return &XEXP (SET_SRC (x), 1);
4884 /* Finally, see if this is a simple operation with its first operand
4885 not in a register. The operation might require this operand in a
4886 register, so return it as a split point. We can always do this
4887 because if the first operand were another operation, we would have
4888 already found it as a split point. */
4889 if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
4890 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
4891 return &XEXP (SET_SRC (x), 0);
4897 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4898 it is better to write this as (not (ior A B)) so we can split it.
4899 Similarly for IOR. */
4900 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
4903 gen_rtx_NOT (GET_MODE (x),
4904 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
4906 XEXP (XEXP (x, 0), 0),
4907 XEXP (XEXP (x, 1), 0))));
4908 return find_split_point (loc, insn, set_src);
4911 /* Many RISC machines have a large set of logical insns. If the
4912 second operand is a NOT, put it first so we will try to split the
4913 other operand first. */
4914 if (GET_CODE (XEXP (x, 1)) == NOT)
4916 rtx tem = XEXP (x, 0);
4917 SUBST (XEXP (x, 0), XEXP (x, 1));
4918 SUBST (XEXP (x, 1), tem);
4924 /* Canonicalization can produce (minus A (mult B C)), where C is a
4925 constant. It may be better to try splitting (plus (mult B -C) A)
4926 instead if this isn't a multiply by a power of two. */
4927 if (set_src && code == MINUS && GET_CODE (XEXP (x, 1)) == MULT
4928 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4929 && exact_log2 (INTVAL (XEXP (XEXP (x, 1), 1))) < 0)
4931 enum machine_mode mode = GET_MODE (x);
4932 unsigned HOST_WIDE_INT this_int = INTVAL (XEXP (XEXP (x, 1), 1));
4933 HOST_WIDE_INT other_int = trunc_int_for_mode (-this_int, mode);
4934 SUBST (*loc, gen_rtx_PLUS (mode, gen_rtx_MULT (mode,
4935 XEXP (XEXP (x, 1), 0),
4936 GEN_INT (other_int)),
4938 return find_split_point (loc, insn, set_src);
4941 /* Split at a multiply-accumulate instruction. However if this is
4942 the SET_SRC, we likely do not have such an instruction and it's
4943 worthless to try this split. */
4944 if (!set_src && GET_CODE (XEXP (x, 0)) == MULT)
4951 /* Otherwise, select our actions depending on our rtx class. */
4952 switch (GET_RTX_CLASS (code))
4954 case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
4956 split = find_split_point (&XEXP (x, 2), insn, false);
4959 /* ... fall through ... */
4961 case RTX_COMM_ARITH:
4963 case RTX_COMM_COMPARE:
4964 split = find_split_point (&XEXP (x, 1), insn, false);
4967 /* ... fall through ... */
4969 /* Some machines have (and (shift ...) ...) insns. If X is not
4970 an AND, but XEXP (X, 0) is, use it as our split point. */
4971 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
4972 return &XEXP (x, 0);
4974 split = find_split_point (&XEXP (x, 0), insn, false);
4980 /* Otherwise, we don't have a split point. */
4985 /* Throughout X, replace FROM with TO, and return the result.
4986 The result is TO if X is FROM;
4987 otherwise the result is X, but its contents may have been modified.
4988 If they were modified, a record was made in undobuf so that
4989 undo_all will (among other things) return X to its original state.
4991 If the number of changes necessary is too much to record to undo,
4992 the excess changes are not made, so the result is invalid.
4993 The changes already made can still be undone.
4994 undobuf.num_undo is incremented for such changes, so by testing that
4995 the caller can tell whether the result is valid.
4997 `n_occurrences' is incremented each time FROM is replaced.
4999 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5001 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5002 by copying if `n_occurrences' is nonzero. */
5005 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
5007 enum rtx_code code = GET_CODE (x);
5008 enum machine_mode op0_mode = VOIDmode;
5013 /* Two expressions are equal if they are identical copies of a shared
5014 RTX or if they are both registers with the same register number
5017 #define COMBINE_RTX_EQUAL_P(X,Y) \
5019 || (REG_P (X) && REG_P (Y) \
5020 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5022 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
5025 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
5028 /* If X and FROM are the same register but different modes, they
5029 will not have been seen as equal above. However, the log links code
5030 will make a LOG_LINKS entry for that case. If we do nothing, we
5031 will try to rerecognize our original insn and, when it succeeds,
5032 we will delete the feeding insn, which is incorrect.
5034 So force this insn not to match in this (rare) case. */
5035 if (! in_dest && code == REG && REG_P (from)
5036 && reg_overlap_mentioned_p (x, from))
5037 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
5039 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5040 of which may contain things that can be combined. */
5041 if (code != MEM && code != LO_SUM && OBJECT_P (x))
5044 /* It is possible to have a subexpression appear twice in the insn.
5045 Suppose that FROM is a register that appears within TO.
5046 Then, after that subexpression has been scanned once by `subst',
5047 the second time it is scanned, TO may be found. If we were
5048 to scan TO here, we would find FROM within it and create a
5049 self-referent rtl structure which is completely wrong. */
5050 if (COMBINE_RTX_EQUAL_P (x, to))
5053 /* Parallel asm_operands need special attention because all of the
5054 inputs are shared across the arms. Furthermore, unsharing the
5055 rtl results in recognition failures. Failure to handle this case
5056 specially can result in circular rtl.
5058 Solve this by doing a normal pass across the first entry of the
5059 parallel, and only processing the SET_DESTs of the subsequent
5062 if (code == PARALLEL
5063 && GET_CODE (XVECEXP (x, 0, 0)) == SET
5064 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
5066 new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
5068 /* If this substitution failed, this whole thing fails. */
5069 if (GET_CODE (new_rtx) == CLOBBER
5070 && XEXP (new_rtx, 0) == const0_rtx)
5073 SUBST (XVECEXP (x, 0, 0), new_rtx);
5075 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
5077 rtx dest = SET_DEST (XVECEXP (x, 0, i));
5080 && GET_CODE (dest) != CC0
5081 && GET_CODE (dest) != PC)
5083 new_rtx = subst (dest, from, to, 0, unique_copy);
5085 /* If this substitution failed, this whole thing fails. */
5086 if (GET_CODE (new_rtx) == CLOBBER
5087 && XEXP (new_rtx, 0) == const0_rtx)
5090 SUBST (SET_DEST (XVECEXP (x, 0, i)), new_rtx);
5096 len = GET_RTX_LENGTH (code);
5097 fmt = GET_RTX_FORMAT (code);
5099 /* We don't need to process a SET_DEST that is a register, CC0,
5100 or PC, so set up to skip this common case. All other cases
5101 where we want to suppress replacing something inside a
5102 SET_SRC are handled via the IN_DEST operand. */
5104 && (REG_P (SET_DEST (x))
5105 || GET_CODE (SET_DEST (x)) == CC0
5106 || GET_CODE (SET_DEST (x)) == PC))
5109 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5112 op0_mode = GET_MODE (XEXP (x, 0));
5114 for (i = 0; i < len; i++)
5119 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5121 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
5123 new_rtx = (unique_copy && n_occurrences
5124 ? copy_rtx (to) : to);
5129 new_rtx = subst (XVECEXP (x, i, j), from, to, 0,
5132 /* If this substitution failed, this whole thing
5134 if (GET_CODE (new_rtx) == CLOBBER
5135 && XEXP (new_rtx, 0) == const0_rtx)
5139 SUBST (XVECEXP (x, i, j), new_rtx);
5142 else if (fmt[i] == 'e')
5144 /* If this is a register being set, ignore it. */
5145 new_rtx = XEXP (x, i);
5148 && (((code == SUBREG || code == ZERO_EXTRACT)
5150 || code == STRICT_LOW_PART))
5153 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
5155 /* In general, don't install a subreg involving two
5156 modes not tieable. It can worsen register
5157 allocation, and can even make invalid reload
5158 insns, since the reg inside may need to be copied
5159 from in the outside mode, and that may be invalid
5160 if it is an fp reg copied in integer mode.
5162 We allow two exceptions to this: It is valid if
5163 it is inside another SUBREG and the mode of that
5164 SUBREG and the mode of the inside of TO is
5165 tieable and it is valid if X is a SET that copies
5168 if (GET_CODE (to) == SUBREG
5169 && ! MODES_TIEABLE_P (GET_MODE (to),
5170 GET_MODE (SUBREG_REG (to)))
5171 && ! (code == SUBREG
5172 && MODES_TIEABLE_P (GET_MODE (x),
5173 GET_MODE (SUBREG_REG (to))))
5175 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
5178 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5180 #ifdef CANNOT_CHANGE_MODE_CLASS
5183 && REGNO (to) < FIRST_PSEUDO_REGISTER
5184 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
5187 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5190 new_rtx = (unique_copy && n_occurrences ? copy_rtx (to) : to);
5194 /* If we are in a SET_DEST, suppress most cases unless we
5195 have gone inside a MEM, in which case we want to
5196 simplify the address. We assume here that things that
5197 are actually part of the destination have their inner
5198 parts in the first expression. This is true for SUBREG,
5199 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5200 things aside from REG and MEM that should appear in a
5202 new_rtx = subst (XEXP (x, i), from, to,
5204 && (code == SUBREG || code == STRICT_LOW_PART
5205 || code == ZERO_EXTRACT))
5207 && i == 0), unique_copy);
5209 /* If we found that we will have to reject this combination,
5210 indicate that by returning the CLOBBER ourselves, rather than
5211 an expression containing it. This will speed things up as
5212 well as prevent accidents where two CLOBBERs are considered
5213 to be equal, thus producing an incorrect simplification. */
5215 if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx)
5218 if (GET_CODE (x) == SUBREG
5219 && (CONST_INT_P (new_rtx)
5220 || GET_CODE (new_rtx) == CONST_DOUBLE))
5222 enum machine_mode mode = GET_MODE (x);
5224 x = simplify_subreg (GET_MODE (x), new_rtx,
5225 GET_MODE (SUBREG_REG (x)),
5228 x = gen_rtx_CLOBBER (mode, const0_rtx);
5230 else if (CONST_INT_P (new_rtx)
5231 && GET_CODE (x) == ZERO_EXTEND)
5233 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
5234 new_rtx, GET_MODE (XEXP (x, 0)));
5238 SUBST (XEXP (x, i), new_rtx);
5243 /* Check if we are loading something from the constant pool via float
5244 extension; in this case we would undo compress_float_constant
5245 optimization and degenerate constant load to an immediate value. */
5246 if (GET_CODE (x) == FLOAT_EXTEND
5247 && MEM_P (XEXP (x, 0))
5248 && MEM_READONLY_P (XEXP (x, 0)))
5250 rtx tmp = avoid_constant_pool_reference (x);
5255 /* Try to simplify X. If the simplification changed the code, it is likely
5256 that further simplification will help, so loop, but limit the number
5257 of repetitions that will be performed. */
5259 for (i = 0; i < 4; i++)
5261 /* If X is sufficiently simple, don't bother trying to do anything
5263 if (code != CONST_INT && code != REG && code != CLOBBER)
5264 x = combine_simplify_rtx (x, op0_mode, in_dest);
5266 if (GET_CODE (x) == code)
5269 code = GET_CODE (x);
5271 /* We no longer know the original mode of operand 0 since we
5272 have changed the form of X) */
5273 op0_mode = VOIDmode;
5279 /* Simplify X, a piece of RTL. We just operate on the expression at the
5280 outer level; call `subst' to simplify recursively. Return the new
5283 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5284 if we are inside a SET_DEST. */
5287 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
5289 enum rtx_code code = GET_CODE (x);
5290 enum machine_mode mode = GET_MODE (x);
5294 /* If this is a commutative operation, put a constant last and a complex
5295 expression first. We don't need to do this for comparisons here. */
5296 if (COMMUTATIVE_ARITH_P (x)
5297 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
5300 SUBST (XEXP (x, 0), XEXP (x, 1));
5301 SUBST (XEXP (x, 1), temp);
5304 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5305 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5306 things. Check for cases where both arms are testing the same
5309 Don't do anything if all operands are very simple. */
5312 && ((!OBJECT_P (XEXP (x, 0))
5313 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5314 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
5315 || (!OBJECT_P (XEXP (x, 1))
5316 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
5317 && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
5319 && (!OBJECT_P (XEXP (x, 0))
5320 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5321 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
5323 rtx cond, true_rtx, false_rtx;
5325 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
5327 /* If everything is a comparison, what we have is highly unlikely
5328 to be simpler, so don't use it. */
5329 && ! (COMPARISON_P (x)
5330 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
5332 rtx cop1 = const0_rtx;
5333 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
5335 if (cond_code == NE && COMPARISON_P (cond))
5338 /* Simplify the alternative arms; this may collapse the true and
5339 false arms to store-flag values. Be careful to use copy_rtx
5340 here since true_rtx or false_rtx might share RTL with x as a
5341 result of the if_then_else_cond call above. */
5342 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
5343 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
5345 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5346 is unlikely to be simpler. */
5347 if (general_operand (true_rtx, VOIDmode)
5348 && general_operand (false_rtx, VOIDmode))
5350 enum rtx_code reversed;
5352 /* Restarting if we generate a store-flag expression will cause
5353 us to loop. Just drop through in this case. */
5355 /* If the result values are STORE_FLAG_VALUE and zero, we can
5356 just make the comparison operation. */
5357 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
5358 x = simplify_gen_relational (cond_code, mode, VOIDmode,
5360 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
5361 && ((reversed = reversed_comparison_code_parts
5362 (cond_code, cond, cop1, NULL))
5364 x = simplify_gen_relational (reversed, mode, VOIDmode,
5367 /* Likewise, we can make the negate of a comparison operation
5368 if the result values are - STORE_FLAG_VALUE and zero. */
5369 else if (CONST_INT_P (true_rtx)
5370 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
5371 && false_rtx == const0_rtx)
5372 x = simplify_gen_unary (NEG, mode,
5373 simplify_gen_relational (cond_code,
5377 else if (CONST_INT_P (false_rtx)
5378 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
5379 && true_rtx == const0_rtx
5380 && ((reversed = reversed_comparison_code_parts
5381 (cond_code, cond, cop1, NULL))
5383 x = simplify_gen_unary (NEG, mode,
5384 simplify_gen_relational (reversed,
5389 return gen_rtx_IF_THEN_ELSE (mode,
5390 simplify_gen_relational (cond_code,
5395 true_rtx, false_rtx);
5397 code = GET_CODE (x);
5398 op0_mode = VOIDmode;
5403 /* Try to fold this expression in case we have constants that weren't
5406 switch (GET_RTX_CLASS (code))
5409 if (op0_mode == VOIDmode)
5410 op0_mode = GET_MODE (XEXP (x, 0));
5411 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
5414 case RTX_COMM_COMPARE:
5416 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
5417 if (cmp_mode == VOIDmode)
5419 cmp_mode = GET_MODE (XEXP (x, 1));
5420 if (cmp_mode == VOIDmode)
5421 cmp_mode = op0_mode;
5423 temp = simplify_relational_operation (code, mode, cmp_mode,
5424 XEXP (x, 0), XEXP (x, 1));
5427 case RTX_COMM_ARITH:
5429 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
5431 case RTX_BITFIELD_OPS:
5433 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
5434 XEXP (x, 1), XEXP (x, 2));
5443 code = GET_CODE (temp);
5444 op0_mode = VOIDmode;
5445 mode = GET_MODE (temp);
5448 /* First see if we can apply the inverse distributive law. */
5449 if (code == PLUS || code == MINUS
5450 || code == AND || code == IOR || code == XOR)
5452 x = apply_distributive_law (x);
5453 code = GET_CODE (x);
5454 op0_mode = VOIDmode;
5457 /* If CODE is an associative operation not otherwise handled, see if we
5458 can associate some operands. This can win if they are constants or
5459 if they are logically related (i.e. (a & b) & a). */
5460 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
5461 || code == AND || code == IOR || code == XOR
5462 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
5463 && ((INTEGRAL_MODE_P (mode) && code != DIV)
5464 || (flag_associative_math && FLOAT_MODE_P (mode))))
5466 if (GET_CODE (XEXP (x, 0)) == code)
5468 rtx other = XEXP (XEXP (x, 0), 0);
5469 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
5470 rtx inner_op1 = XEXP (x, 1);
5473 /* Make sure we pass the constant operand if any as the second
5474 one if this is a commutative operation. */
5475 if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
5477 rtx tem = inner_op0;
5478 inner_op0 = inner_op1;
5481 inner = simplify_binary_operation (code == MINUS ? PLUS
5482 : code == DIV ? MULT
5484 mode, inner_op0, inner_op1);
5486 /* For commutative operations, try the other pair if that one
5488 if (inner == 0 && COMMUTATIVE_ARITH_P (x))
5490 other = XEXP (XEXP (x, 0), 1);
5491 inner = simplify_binary_operation (code, mode,
5492 XEXP (XEXP (x, 0), 0),
5497 return simplify_gen_binary (code, mode, other, inner);
5501 /* A little bit of algebraic simplification here. */
5505 /* Ensure that our address has any ASHIFTs converted to MULT in case
5506 address-recognizing predicates are called later. */
5507 temp = make_compound_operation (XEXP (x, 0), MEM);
5508 SUBST (XEXP (x, 0), temp);
5512 if (op0_mode == VOIDmode)
5513 op0_mode = GET_MODE (SUBREG_REG (x));
5515 /* See if this can be moved to simplify_subreg. */
5516 if (CONSTANT_P (SUBREG_REG (x))
5517 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
5518 /* Don't call gen_lowpart if the inner mode
5519 is VOIDmode and we cannot simplify it, as SUBREG without
5520 inner mode is invalid. */
5521 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
5522 || gen_lowpart_common (mode, SUBREG_REG (x))))
5523 return gen_lowpart (mode, SUBREG_REG (x));
5525 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
5529 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
5535 /* Don't change the mode of the MEM if that would change the meaning
5537 if (MEM_P (SUBREG_REG (x))
5538 && (MEM_VOLATILE_P (SUBREG_REG (x))
5539 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
5540 return gen_rtx_CLOBBER (mode, const0_rtx);
5542 /* Note that we cannot do any narrowing for non-constants since
5543 we might have been counting on using the fact that some bits were
5544 zero. We now do this in the SET. */
5549 temp = expand_compound_operation (XEXP (x, 0));
5551 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5552 replaced by (lshiftrt X C). This will convert
5553 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5555 if (GET_CODE (temp) == ASHIFTRT
5556 && CONST_INT_P (XEXP (temp, 1))
5557 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
5558 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
5559 INTVAL (XEXP (temp, 1)));
5561 /* If X has only a single bit that might be nonzero, say, bit I, convert
5562 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5563 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5564 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5565 or a SUBREG of one since we'd be making the expression more
5566 complex if it was just a register. */
5569 && ! (GET_CODE (temp) == SUBREG
5570 && REG_P (SUBREG_REG (temp)))
5571 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
5573 rtx temp1 = simplify_shift_const
5574 (NULL_RTX, ASHIFTRT, mode,
5575 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
5576 GET_MODE_BITSIZE (mode) - 1 - i),
5577 GET_MODE_BITSIZE (mode) - 1 - i);
5579 /* If all we did was surround TEMP with the two shifts, we
5580 haven't improved anything, so don't use it. Otherwise,
5581 we are better off with TEMP1. */
5582 if (GET_CODE (temp1) != ASHIFTRT
5583 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
5584 || XEXP (XEXP (temp1, 0), 0) != temp)
5590 /* We can't handle truncation to a partial integer mode here
5591 because we don't know the real bitsize of the partial
5593 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
5596 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5598 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
5599 GET_MODE_MASK (mode), 0));
5601 /* We can truncate a constant value and return it. */
5602 if (CONST_INT_P (XEXP (x, 0)))
5603 return gen_int_mode (INTVAL (XEXP (x, 0)), mode);
5605 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5606 whose value is a comparison can be replaced with a subreg if
5607 STORE_FLAG_VALUE permits. */
5608 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5609 && (STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
5610 && (temp = get_last_value (XEXP (x, 0)))
5611 && COMPARISON_P (temp))
5612 return gen_lowpart (mode, XEXP (x, 0));
5616 /* (const (const X)) can become (const X). Do it this way rather than
5617 returning the inner CONST since CONST can be shared with a
5619 if (GET_CODE (XEXP (x, 0)) == CONST)
5620 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
5625 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5626 can add in an offset. find_split_point will split this address up
5627 again if it doesn't match. */
5628 if (GET_CODE (XEXP (x, 0)) == HIGH
5629 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
5635 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5636 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5637 bit-field and can be replaced by either a sign_extend or a
5638 sign_extract. The `and' may be a zero_extend and the two
5639 <c>, -<c> constants may be reversed. */
5640 if (GET_CODE (XEXP (x, 0)) == XOR
5641 && CONST_INT_P (XEXP (x, 1))
5642 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
5643 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
5644 && ((i = exact_log2 (UINTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
5645 || (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0)
5646 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5647 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
5648 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
5649 && (UINTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
5650 == ((unsigned HOST_WIDE_INT) 1 << (i + 1)) - 1))
5651 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
5652 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
5653 == (unsigned int) i + 1))))
5654 return simplify_shift_const
5655 (NULL_RTX, ASHIFTRT, mode,
5656 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5657 XEXP (XEXP (XEXP (x, 0), 0), 0),
5658 GET_MODE_BITSIZE (mode) - (i + 1)),
5659 GET_MODE_BITSIZE (mode) - (i + 1));
5661 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5662 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5663 the bitsize of the mode - 1. This allows simplification of
5664 "a = (b & 8) == 0;" */
5665 if (XEXP (x, 1) == constm1_rtx
5666 && !REG_P (XEXP (x, 0))
5667 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5668 && REG_P (SUBREG_REG (XEXP (x, 0))))
5669 && nonzero_bits (XEXP (x, 0), mode) == 1)
5670 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
5671 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5672 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
5673 GET_MODE_BITSIZE (mode) - 1),
5674 GET_MODE_BITSIZE (mode) - 1);
5676 /* If we are adding two things that have no bits in common, convert
5677 the addition into an IOR. This will often be further simplified,
5678 for example in cases like ((a & 1) + (a & 2)), which can
5681 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5682 && (nonzero_bits (XEXP (x, 0), mode)
5683 & nonzero_bits (XEXP (x, 1), mode)) == 0)
5685 /* Try to simplify the expression further. */
5686 rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
5687 temp = combine_simplify_rtx (tor, VOIDmode, in_dest);
5689 /* If we could, great. If not, do not go ahead with the IOR
5690 replacement, since PLUS appears in many special purpose
5691 address arithmetic instructions. */
5692 if (GET_CODE (temp) != CLOBBER && temp != tor)
5698 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5699 (and <foo> (const_int pow2-1)) */
5700 if (GET_CODE (XEXP (x, 1)) == AND
5701 && CONST_INT_P (XEXP (XEXP (x, 1), 1))
5702 && exact_log2 (-UINTVAL (XEXP (XEXP (x, 1), 1))) >= 0
5703 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
5704 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
5705 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
5709 /* If we have (mult (plus A B) C), apply the distributive law and then
5710 the inverse distributive law to see if things simplify. This
5711 occurs mostly in addresses, often when unrolling loops. */
5713 if (GET_CODE (XEXP (x, 0)) == PLUS)
5715 rtx result = distribute_and_simplify_rtx (x, 0);
5720 /* Try simplify a*(b/c) as (a*b)/c. */
5721 if (FLOAT_MODE_P (mode) && flag_associative_math
5722 && GET_CODE (XEXP (x, 0)) == DIV)
5724 rtx tem = simplify_binary_operation (MULT, mode,
5725 XEXP (XEXP (x, 0), 0),
5728 return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
5733 /* If this is a divide by a power of two, treat it as a shift if
5734 its first operand is a shift. */
5735 if (CONST_INT_P (XEXP (x, 1))
5736 && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0
5737 && (GET_CODE (XEXP (x, 0)) == ASHIFT
5738 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
5739 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
5740 || GET_CODE (XEXP (x, 0)) == ROTATE
5741 || GET_CODE (XEXP (x, 0)) == ROTATERT))
5742 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
5746 case GT: case GTU: case GE: case GEU:
5747 case LT: case LTU: case LE: case LEU:
5748 case UNEQ: case LTGT:
5749 case UNGT: case UNGE:
5750 case UNLT: case UNLE:
5751 case UNORDERED: case ORDERED:
5752 /* If the first operand is a condition code, we can't do anything
5754 if (GET_CODE (XEXP (x, 0)) == COMPARE
5755 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
5756 && ! CC0_P (XEXP (x, 0))))
5758 rtx op0 = XEXP (x, 0);
5759 rtx op1 = XEXP (x, 1);
5760 enum rtx_code new_code;
5762 if (GET_CODE (op0) == COMPARE)
5763 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
5765 /* Simplify our comparison, if possible. */
5766 new_code = simplify_comparison (code, &op0, &op1);
5768 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5769 if only the low-order bit is possibly nonzero in X (such as when
5770 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5771 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5772 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5775 Remove any ZERO_EXTRACT we made when thinking this was a
5776 comparison. It may now be simpler to use, e.g., an AND. If a
5777 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5778 the call to make_compound_operation in the SET case. */
5780 if (STORE_FLAG_VALUE == 1
5781 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5782 && op1 == const0_rtx
5783 && mode == GET_MODE (op0)
5784 && nonzero_bits (op0, mode) == 1)
5785 return gen_lowpart (mode,
5786 expand_compound_operation (op0));
5788 else if (STORE_FLAG_VALUE == 1
5789 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5790 && op1 == const0_rtx
5791 && mode == GET_MODE (op0)
5792 && (num_sign_bit_copies (op0, mode)
5793 == GET_MODE_BITSIZE (mode)))
5795 op0 = expand_compound_operation (op0);
5796 return simplify_gen_unary (NEG, mode,
5797 gen_lowpart (mode, op0),
5801 else if (STORE_FLAG_VALUE == 1
5802 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5803 && op1 == const0_rtx
5804 && mode == GET_MODE (op0)
5805 && nonzero_bits (op0, mode) == 1)
5807 op0 = expand_compound_operation (op0);
5808 return simplify_gen_binary (XOR, mode,
5809 gen_lowpart (mode, op0),
5813 else if (STORE_FLAG_VALUE == 1
5814 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5815 && op1 == const0_rtx
5816 && mode == GET_MODE (op0)
5817 && (num_sign_bit_copies (op0, mode)
5818 == GET_MODE_BITSIZE (mode)))
5820 op0 = expand_compound_operation (op0);
5821 return plus_constant (gen_lowpart (mode, op0), 1);
5824 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5826 if (STORE_FLAG_VALUE == -1
5827 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5828 && op1 == const0_rtx
5829 && (num_sign_bit_copies (op0, mode)
5830 == GET_MODE_BITSIZE (mode)))
5831 return gen_lowpart (mode,
5832 expand_compound_operation (op0));
5834 else if (STORE_FLAG_VALUE == -1
5835 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5836 && op1 == const0_rtx
5837 && mode == GET_MODE (op0)
5838 && nonzero_bits (op0, mode) == 1)
5840 op0 = expand_compound_operation (op0);
5841 return simplify_gen_unary (NEG, mode,
5842 gen_lowpart (mode, op0),
5846 else if (STORE_FLAG_VALUE == -1
5847 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5848 && op1 == const0_rtx
5849 && mode == GET_MODE (op0)
5850 && (num_sign_bit_copies (op0, mode)
5851 == GET_MODE_BITSIZE (mode)))
5853 op0 = expand_compound_operation (op0);
5854 return simplify_gen_unary (NOT, mode,
5855 gen_lowpart (mode, op0),
5859 /* If X is 0/1, (eq X 0) is X-1. */
5860 else if (STORE_FLAG_VALUE == -1
5861 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5862 && op1 == const0_rtx
5863 && mode == GET_MODE (op0)
5864 && nonzero_bits (op0, mode) == 1)
5866 op0 = expand_compound_operation (op0);
5867 return plus_constant (gen_lowpart (mode, op0), -1);
5870 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5871 one bit that might be nonzero, we can convert (ne x 0) to
5872 (ashift x c) where C puts the bit in the sign bit. Remove any
5873 AND with STORE_FLAG_VALUE when we are done, since we are only
5874 going to test the sign bit. */
5875 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5876 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5877 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5878 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5879 && op1 == const0_rtx
5880 && mode == GET_MODE (op0)
5881 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
5883 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
5884 expand_compound_operation (op0),
5885 GET_MODE_BITSIZE (mode) - 1 - i);
5886 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
5892 /* If the code changed, return a whole new comparison. */
5893 if (new_code != code)
5894 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
5896 /* Otherwise, keep this operation, but maybe change its operands.
5897 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5898 SUBST (XEXP (x, 0), op0);
5899 SUBST (XEXP (x, 1), op1);
5904 return simplify_if_then_else (x);
5910 /* If we are processing SET_DEST, we are done. */
5914 return expand_compound_operation (x);
5917 return simplify_set (x);
5921 return simplify_logical (x);
5928 /* If this is a shift by a constant amount, simplify it. */
5929 if (CONST_INT_P (XEXP (x, 1)))
5930 return simplify_shift_const (x, code, mode, XEXP (x, 0),
5931 INTVAL (XEXP (x, 1)));
5933 else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
5935 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
5936 ((unsigned HOST_WIDE_INT) 1
5937 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
5949 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5952 simplify_if_then_else (rtx x)
5954 enum machine_mode mode = GET_MODE (x);
5955 rtx cond = XEXP (x, 0);
5956 rtx true_rtx = XEXP (x, 1);
5957 rtx false_rtx = XEXP (x, 2);
5958 enum rtx_code true_code = GET_CODE (cond);
5959 int comparison_p = COMPARISON_P (cond);
5962 enum rtx_code false_code;
5965 /* Simplify storing of the truth value. */
5966 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
5967 return simplify_gen_relational (true_code, mode, VOIDmode,
5968 XEXP (cond, 0), XEXP (cond, 1));
5970 /* Also when the truth value has to be reversed. */
5972 && true_rtx == const0_rtx && false_rtx == const_true_rtx
5973 && (reversed = reversed_comparison (cond, mode)))
5976 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5977 in it is being compared against certain values. Get the true and false
5978 comparisons and see if that says anything about the value of each arm. */
5981 && ((false_code = reversed_comparison_code (cond, NULL))
5983 && REG_P (XEXP (cond, 0)))
5986 rtx from = XEXP (cond, 0);
5987 rtx true_val = XEXP (cond, 1);
5988 rtx false_val = true_val;
5991 /* If FALSE_CODE is EQ, swap the codes and arms. */
5993 if (false_code == EQ)
5995 swapped = 1, true_code = EQ, false_code = NE;
5996 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5999 /* If we are comparing against zero and the expression being tested has
6000 only a single bit that might be nonzero, that is its value when it is
6001 not equal to zero. Similarly if it is known to be -1 or 0. */
6003 if (true_code == EQ && true_val == const0_rtx
6004 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
6007 false_val = GEN_INT (trunc_int_for_mode (nzb, GET_MODE (from)));
6009 else if (true_code == EQ && true_val == const0_rtx
6010 && (num_sign_bit_copies (from, GET_MODE (from))
6011 == GET_MODE_BITSIZE (GET_MODE (from))))
6014 false_val = constm1_rtx;
6017 /* Now simplify an arm if we know the value of the register in the
6018 branch and it is used in the arm. Be careful due to the potential
6019 of locally-shared RTL. */
6021 if (reg_mentioned_p (from, true_rtx))
6022 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
6024 pc_rtx, pc_rtx, 0, 0);
6025 if (reg_mentioned_p (from, false_rtx))
6026 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
6028 pc_rtx, pc_rtx, 0, 0);
6030 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
6031 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
6033 true_rtx = XEXP (x, 1);
6034 false_rtx = XEXP (x, 2);
6035 true_code = GET_CODE (cond);
6038 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6039 reversed, do so to avoid needing two sets of patterns for
6040 subtract-and-branch insns. Similarly if we have a constant in the true
6041 arm, the false arm is the same as the first operand of the comparison, or
6042 the false arm is more complicated than the true arm. */
6045 && reversed_comparison_code (cond, NULL) != UNKNOWN
6046 && (true_rtx == pc_rtx
6047 || (CONSTANT_P (true_rtx)
6048 && !CONST_INT_P (false_rtx) && false_rtx != pc_rtx)
6049 || true_rtx == const0_rtx
6050 || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
6051 || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
6052 && !OBJECT_P (false_rtx))
6053 || reg_mentioned_p (true_rtx, false_rtx)
6054 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
6056 true_code = reversed_comparison_code (cond, NULL);
6057 SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
6058 SUBST (XEXP (x, 1), false_rtx);
6059 SUBST (XEXP (x, 2), true_rtx);
6061 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
6064 /* It is possible that the conditional has been simplified out. */
6065 true_code = GET_CODE (cond);
6066 comparison_p = COMPARISON_P (cond);
6069 /* If the two arms are identical, we don't need the comparison. */
6071 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
6074 /* Convert a == b ? b : a to "a". */
6075 if (true_code == EQ && ! side_effects_p (cond)
6076 && !HONOR_NANS (mode)
6077 && rtx_equal_p (XEXP (cond, 0), false_rtx)
6078 && rtx_equal_p (XEXP (cond, 1), true_rtx))
6080 else if (true_code == NE && ! side_effects_p (cond)
6081 && !HONOR_NANS (mode)
6082 && rtx_equal_p (XEXP (cond, 0), true_rtx)
6083 && rtx_equal_p (XEXP (cond, 1), false_rtx))
6086 /* Look for cases where we have (abs x) or (neg (abs X)). */
6088 if (GET_MODE_CLASS (mode) == MODE_INT
6090 && XEXP (cond, 1) == const0_rtx
6091 && GET_CODE (false_rtx) == NEG
6092 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
6093 && rtx_equal_p (true_rtx, XEXP (cond, 0))
6094 && ! side_effects_p (true_rtx))
6099 return simplify_gen_unary (ABS, mode, true_rtx, mode);
6103 simplify_gen_unary (NEG, mode,
6104 simplify_gen_unary (ABS, mode, true_rtx, mode),
6110 /* Look for MIN or MAX. */
6112 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
6114 && rtx_equal_p (XEXP (cond, 0), true_rtx)
6115 && rtx_equal_p (XEXP (cond, 1), false_rtx)
6116 && ! side_effects_p (cond))
6121 return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
6124 return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
6127 return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
6130 return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
6135 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6136 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6137 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6138 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6139 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6140 neither 1 or -1, but it isn't worth checking for. */
6142 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6144 && GET_MODE_CLASS (mode) == MODE_INT
6145 && ! side_effects_p (x))
6147 rtx t = make_compound_operation (true_rtx, SET);
6148 rtx f = make_compound_operation (false_rtx, SET);
6149 rtx cond_op0 = XEXP (cond, 0);
6150 rtx cond_op1 = XEXP (cond, 1);
6151 enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
6152 enum machine_mode m = mode;
6153 rtx z = 0, c1 = NULL_RTX;
6155 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
6156 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
6157 || GET_CODE (t) == ASHIFT
6158 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
6159 && rtx_equal_p (XEXP (t, 0), f))
6160 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
6162 /* If an identity-zero op is commutative, check whether there
6163 would be a match if we swapped the operands. */
6164 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
6165 || GET_CODE (t) == XOR)
6166 && rtx_equal_p (XEXP (t, 1), f))
6167 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
6168 else if (GET_CODE (t) == SIGN_EXTEND
6169 && (GET_CODE (XEXP (t, 0)) == PLUS
6170 || GET_CODE (XEXP (t, 0)) == MINUS
6171 || GET_CODE (XEXP (t, 0)) == IOR
6172 || GET_CODE (XEXP (t, 0)) == XOR
6173 || GET_CODE (XEXP (t, 0)) == ASHIFT
6174 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6175 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6176 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6177 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6178 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6179 && (num_sign_bit_copies (f, GET_MODE (f))
6181 (GET_MODE_BITSIZE (mode)
6182 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
6184 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6185 extend_op = SIGN_EXTEND;
6186 m = GET_MODE (XEXP (t, 0));
6188 else if (GET_CODE (t) == SIGN_EXTEND
6189 && (GET_CODE (XEXP (t, 0)) == PLUS
6190 || GET_CODE (XEXP (t, 0)) == IOR
6191 || GET_CODE (XEXP (t, 0)) == XOR)
6192 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6193 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6194 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6195 && (num_sign_bit_copies (f, GET_MODE (f))
6197 (GET_MODE_BITSIZE (mode)
6198 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
6200 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6201 extend_op = SIGN_EXTEND;
6202 m = GET_MODE (XEXP (t, 0));
6204 else if (GET_CODE (t) == ZERO_EXTEND
6205 && (GET_CODE (XEXP (t, 0)) == PLUS
6206 || GET_CODE (XEXP (t, 0)) == MINUS
6207 || GET_CODE (XEXP (t, 0)) == IOR
6208 || GET_CODE (XEXP (t, 0)) == XOR
6209 || GET_CODE (XEXP (t, 0)) == ASHIFT
6210 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6211 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6212 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6213 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
6214 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6215 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6216 && ((nonzero_bits (f, GET_MODE (f))
6217 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
6220 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6221 extend_op = ZERO_EXTEND;
6222 m = GET_MODE (XEXP (t, 0));
6224 else if (GET_CODE (t) == ZERO_EXTEND
6225 && (GET_CODE (XEXP (t, 0)) == PLUS
6226 || GET_CODE (XEXP (t, 0)) == IOR
6227 || GET_CODE (XEXP (t, 0)) == XOR)
6228 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6229 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
6230 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6231 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6232 && ((nonzero_bits (f, GET_MODE (f))
6233 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
6236 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6237 extend_op = ZERO_EXTEND;
6238 m = GET_MODE (XEXP (t, 0));
6243 temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
6244 cond_op0, cond_op1),
6245 pc_rtx, pc_rtx, 0, 0);
6246 temp = simplify_gen_binary (MULT, m, temp,
6247 simplify_gen_binary (MULT, m, c1,
6249 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
6250 temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
6252 if (extend_op != UNKNOWN)
6253 temp = simplify_gen_unary (extend_op, mode, temp, m);
6259 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6260 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6261 negation of a single bit, we can convert this operation to a shift. We
6262 can actually do this more generally, but it doesn't seem worth it. */
6264 if (true_code == NE && XEXP (cond, 1) == const0_rtx
6265 && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6266 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
6267 && (i = exact_log2 (UINTVAL (true_rtx))) >= 0)
6268 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
6269 == GET_MODE_BITSIZE (mode))
6270 && (i = exact_log2 (-UINTVAL (true_rtx))) >= 0)))
6272 simplify_shift_const (NULL_RTX, ASHIFT, mode,
6273 gen_lowpart (mode, XEXP (cond, 0)), i);
6275 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
6276 if (true_code == NE && XEXP (cond, 1) == const0_rtx
6277 && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6278 && GET_MODE (XEXP (cond, 0)) == mode
6279 && (UINTVAL (true_rtx) & GET_MODE_MASK (mode))
6280 == nonzero_bits (XEXP (cond, 0), mode)
6281 && (i = exact_log2 (UINTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
6282 return XEXP (cond, 0);
6287 /* Simplify X, a SET expression. Return the new expression. */
6290 simplify_set (rtx x)
6292 rtx src = SET_SRC (x);
6293 rtx dest = SET_DEST (x);
6294 enum machine_mode mode
6295 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
6299 /* (set (pc) (return)) gets written as (return). */
6300 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
6303 /* Now that we know for sure which bits of SRC we are using, see if we can
6304 simplify the expression for the object knowing that we only need the
6307 if (GET_MODE_CLASS (mode) == MODE_INT
6308 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
6310 src = force_to_mode (src, mode, ~(unsigned HOST_WIDE_INT) 0, 0);
6311 SUBST (SET_SRC (x), src);
6314 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6315 the comparison result and try to simplify it unless we already have used
6316 undobuf.other_insn. */
6317 if ((GET_MODE_CLASS (mode) == MODE_CC
6318 || GET_CODE (src) == COMPARE
6320 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
6321 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
6322 && COMPARISON_P (*cc_use)
6323 && rtx_equal_p (XEXP (*cc_use, 0), dest))
6325 enum rtx_code old_code = GET_CODE (*cc_use);
6326 enum rtx_code new_code;
6328 int other_changed = 0;
6329 enum machine_mode compare_mode = GET_MODE (dest);
6331 if (GET_CODE (src) == COMPARE)
6332 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
6334 op0 = src, op1 = CONST0_RTX (GET_MODE (src));
6336 tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
6339 new_code = old_code;
6340 else if (!CONSTANT_P (tmp))
6342 new_code = GET_CODE (tmp);
6343 op0 = XEXP (tmp, 0);
6344 op1 = XEXP (tmp, 1);
6348 rtx pat = PATTERN (other_insn);
6349 undobuf.other_insn = other_insn;
6350 SUBST (*cc_use, tmp);
6352 /* Attempt to simplify CC user. */
6353 if (GET_CODE (pat) == SET)
6355 rtx new_rtx = simplify_rtx (SET_SRC (pat));
6356 if (new_rtx != NULL_RTX)
6357 SUBST (SET_SRC (pat), new_rtx);
6360 /* Convert X into a no-op move. */
6361 SUBST (SET_DEST (x), pc_rtx);
6362 SUBST (SET_SRC (x), pc_rtx);
6366 /* Simplify our comparison, if possible. */
6367 new_code = simplify_comparison (new_code, &op0, &op1);
6369 #ifdef SELECT_CC_MODE
6370 /* If this machine has CC modes other than CCmode, check to see if we
6371 need to use a different CC mode here. */
6372 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
6373 compare_mode = GET_MODE (op0);
6375 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
6378 /* If the mode changed, we have to change SET_DEST, the mode in the
6379 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6380 a hard register, just build new versions with the proper mode. If it
6381 is a pseudo, we lose unless it is only time we set the pseudo, in
6382 which case we can safely change its mode. */
6383 if (compare_mode != GET_MODE (dest))
6385 if (can_change_dest_mode (dest, 0, compare_mode))
6387 unsigned int regno = REGNO (dest);
6390 if (regno < FIRST_PSEUDO_REGISTER)
6391 new_dest = gen_rtx_REG (compare_mode, regno);
6394 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
6395 new_dest = regno_reg_rtx[regno];
6398 SUBST (SET_DEST (x), new_dest);
6399 SUBST (XEXP (*cc_use, 0), new_dest);
6406 #endif /* SELECT_CC_MODE */
6408 /* If the code changed, we have to build a new comparison in
6409 undobuf.other_insn. */
6410 if (new_code != old_code)
6412 int other_changed_previously = other_changed;
6413 unsigned HOST_WIDE_INT mask;
6414 rtx old_cc_use = *cc_use;
6416 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
6420 /* If the only change we made was to change an EQ into an NE or
6421 vice versa, OP0 has only one bit that might be nonzero, and OP1
6422 is zero, check if changing the user of the condition code will
6423 produce a valid insn. If it won't, we can keep the original code
6424 in that insn by surrounding our operation with an XOR. */
6426 if (((old_code == NE && new_code == EQ)
6427 || (old_code == EQ && new_code == NE))
6428 && ! other_changed_previously && op1 == const0_rtx
6429 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
6430 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
6432 rtx pat = PATTERN (other_insn), note = 0;
6434 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
6435 && ! check_asm_operands (pat)))
6437 *cc_use = old_cc_use;
6440 op0 = simplify_gen_binary (XOR, GET_MODE (op0),
6441 op0, GEN_INT (mask));
6447 undobuf.other_insn = other_insn;
6449 /* Otherwise, if we didn't previously have a COMPARE in the
6450 correct mode, we need one. */
6451 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
6453 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6456 else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
6458 SUBST (SET_SRC (x), op0);
6461 /* Otherwise, update the COMPARE if needed. */
6462 else if (XEXP (src, 0) != op0 || XEXP (src, 1) != op1)
6464 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6470 /* Get SET_SRC in a form where we have placed back any
6471 compound expressions. Then do the checks below. */
6472 src = make_compound_operation (src, SET);
6473 SUBST (SET_SRC (x), src);
6476 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6477 and X being a REG or (subreg (reg)), we may be able to convert this to
6478 (set (subreg:m2 x) (op)).
6480 We can always do this if M1 is narrower than M2 because that means that
6481 we only care about the low bits of the result.
6483 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6484 perform a narrower operation than requested since the high-order bits will
6485 be undefined. On machine where it is defined, this transformation is safe
6486 as long as M1 and M2 have the same number of words. */
6488 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6489 && !OBJECT_P (SUBREG_REG (src))
6490 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
6492 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
6493 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
6494 #ifndef WORD_REGISTER_OPERATIONS
6495 && (GET_MODE_SIZE (GET_MODE (src))
6496 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
6498 #ifdef CANNOT_CHANGE_MODE_CLASS
6499 && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
6500 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
6501 GET_MODE (SUBREG_REG (src)),
6505 || (GET_CODE (dest) == SUBREG
6506 && REG_P (SUBREG_REG (dest)))))
6508 SUBST (SET_DEST (x),
6509 gen_lowpart (GET_MODE (SUBREG_REG (src)),
6511 SUBST (SET_SRC (x), SUBREG_REG (src));
6513 src = SET_SRC (x), dest = SET_DEST (x);
6517 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6520 && GET_CODE (src) == SUBREG
6521 && subreg_lowpart_p (src)
6522 && (GET_MODE_BITSIZE (GET_MODE (src))
6523 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
6525 rtx inner = SUBREG_REG (src);
6526 enum machine_mode inner_mode = GET_MODE (inner);
6528 /* Here we make sure that we don't have a sign bit on. */
6529 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
6530 && (nonzero_bits (inner, inner_mode)
6531 < ((unsigned HOST_WIDE_INT) 1
6532 << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
6534 SUBST (SET_SRC (x), inner);
6540 #ifdef LOAD_EXTEND_OP
6541 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6542 would require a paradoxical subreg. Replace the subreg with a
6543 zero_extend to avoid the reload that would otherwise be required. */
6545 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6546 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src)))
6547 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
6548 && SUBREG_BYTE (src) == 0
6549 && (GET_MODE_SIZE (GET_MODE (src))
6550 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
6551 && MEM_P (SUBREG_REG (src)))
6554 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
6555 GET_MODE (src), SUBREG_REG (src)));
6561 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6562 are comparing an item known to be 0 or -1 against 0, use a logical
6563 operation instead. Check for one of the arms being an IOR of the other
6564 arm with some value. We compute three terms to be IOR'ed together. In
6565 practice, at most two will be nonzero. Then we do the IOR's. */
6567 if (GET_CODE (dest) != PC
6568 && GET_CODE (src) == IF_THEN_ELSE
6569 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
6570 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
6571 && XEXP (XEXP (src, 0), 1) == const0_rtx
6572 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
6573 #ifdef HAVE_conditional_move
6574 && ! can_conditionally_move_p (GET_MODE (src))
6576 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
6577 GET_MODE (XEXP (XEXP (src, 0), 0)))
6578 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
6579 && ! side_effects_p (src))
6581 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
6582 ? XEXP (src, 1) : XEXP (src, 2));
6583 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
6584 ? XEXP (src, 2) : XEXP (src, 1));
6585 rtx term1 = const0_rtx, term2, term3;
6587 if (GET_CODE (true_rtx) == IOR
6588 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
6589 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
6590 else if (GET_CODE (true_rtx) == IOR
6591 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
6592 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
6593 else if (GET_CODE (false_rtx) == IOR
6594 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
6595 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
6596 else if (GET_CODE (false_rtx) == IOR
6597 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
6598 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
6600 term2 = simplify_gen_binary (AND, GET_MODE (src),
6601 XEXP (XEXP (src, 0), 0), true_rtx);
6602 term3 = simplify_gen_binary (AND, GET_MODE (src),
6603 simplify_gen_unary (NOT, GET_MODE (src),
6604 XEXP (XEXP (src, 0), 0),
6609 simplify_gen_binary (IOR, GET_MODE (src),
6610 simplify_gen_binary (IOR, GET_MODE (src),
6617 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6618 whole thing fail. */
6619 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
6621 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
6624 /* Convert this into a field assignment operation, if possible. */
6625 return make_field_assignment (x);
6628 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6632 simplify_logical (rtx x)
6634 enum machine_mode mode = GET_MODE (x);
6635 rtx op0 = XEXP (x, 0);
6636 rtx op1 = XEXP (x, 1);
6638 switch (GET_CODE (x))
6641 /* We can call simplify_and_const_int only if we don't lose
6642 any (sign) bits when converting INTVAL (op1) to
6643 "unsigned HOST_WIDE_INT". */
6644 if (CONST_INT_P (op1)
6645 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
6646 || INTVAL (op1) > 0))
6648 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
6649 if (GET_CODE (x) != AND)
6656 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6657 apply the distributive law and then the inverse distributive
6658 law to see if things simplify. */
6659 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
6661 rtx result = distribute_and_simplify_rtx (x, 0);
6665 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
6667 rtx result = distribute_and_simplify_rtx (x, 1);
6674 /* If we have (ior (and A B) C), apply the distributive law and then
6675 the inverse distributive law to see if things simplify. */
6677 if (GET_CODE (op0) == AND)
6679 rtx result = distribute_and_simplify_rtx (x, 0);
6684 if (GET_CODE (op1) == AND)
6686 rtx result = distribute_and_simplify_rtx (x, 1);
6699 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6700 operations" because they can be replaced with two more basic operations.
6701 ZERO_EXTEND is also considered "compound" because it can be replaced with
6702 an AND operation, which is simpler, though only one operation.
6704 The function expand_compound_operation is called with an rtx expression
6705 and will convert it to the appropriate shifts and AND operations,
6706 simplifying at each stage.
6708 The function make_compound_operation is called to convert an expression
6709 consisting of shifts and ANDs into the equivalent compound expression.
6710 It is the inverse of this function, loosely speaking. */
6713 expand_compound_operation (rtx x)
6715 unsigned HOST_WIDE_INT pos = 0, len;
6717 unsigned int modewidth;
6720 switch (GET_CODE (x))
6725 /* We can't necessarily use a const_int for a multiword mode;
6726 it depends on implicitly extending the value.
6727 Since we don't know the right way to extend it,
6728 we can't tell whether the implicit way is right.
6730 Even for a mode that is no wider than a const_int,
6731 we can't win, because we need to sign extend one of its bits through
6732 the rest of it, and we don't know which bit. */
6733 if (CONST_INT_P (XEXP (x, 0)))
6736 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6737 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6738 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6739 reloaded. If not for that, MEM's would very rarely be safe.
6741 Reject MODEs bigger than a word, because we might not be able
6742 to reference a two-register group starting with an arbitrary register
6743 (and currently gen_lowpart might crash for a SUBREG). */
6745 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
6748 /* Reject MODEs that aren't scalar integers because turning vector
6749 or complex modes into shifts causes problems. */
6751 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6754 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
6755 /* If the inner object has VOIDmode (the only way this can happen
6756 is if it is an ASM_OPERANDS), we can't do anything since we don't
6757 know how much masking to do. */
6766 /* ... fall through ... */
6769 /* If the operand is a CLOBBER, just return it. */
6770 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
6773 if (!CONST_INT_P (XEXP (x, 1))
6774 || !CONST_INT_P (XEXP (x, 2))
6775 || GET_MODE (XEXP (x, 0)) == VOIDmode)
6778 /* Reject MODEs that aren't scalar integers because turning vector
6779 or complex modes into shifts causes problems. */
6781 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6784 len = INTVAL (XEXP (x, 1));
6785 pos = INTVAL (XEXP (x, 2));
6787 /* This should stay within the object being extracted, fail otherwise. */
6788 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
6791 if (BITS_BIG_ENDIAN)
6792 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
6799 /* Convert sign extension to zero extension, if we know that the high
6800 bit is not set, as this is easier to optimize. It will be converted
6801 back to cheaper alternative in make_extraction. */
6802 if (GET_CODE (x) == SIGN_EXTEND
6803 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6804 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6805 & ~(((unsigned HOST_WIDE_INT)
6806 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
6810 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
6811 rtx temp2 = expand_compound_operation (temp);
6813 /* Make sure this is a profitable operation. */
6814 if (rtx_cost (x, SET, optimize_this_for_speed_p)
6815 > rtx_cost (temp2, SET, optimize_this_for_speed_p))
6817 else if (rtx_cost (x, SET, optimize_this_for_speed_p)
6818 > rtx_cost (temp, SET, optimize_this_for_speed_p))
6824 /* We can optimize some special cases of ZERO_EXTEND. */
6825 if (GET_CODE (x) == ZERO_EXTEND)
6827 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6828 know that the last value didn't have any inappropriate bits
6830 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6831 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6832 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6833 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
6834 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6835 return XEXP (XEXP (x, 0), 0);
6837 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6838 if (GET_CODE (XEXP (x, 0)) == SUBREG
6839 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6840 && subreg_lowpart_p (XEXP (x, 0))
6841 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6842 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
6843 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6844 return SUBREG_REG (XEXP (x, 0));
6846 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6847 is a comparison and STORE_FLAG_VALUE permits. This is like
6848 the first case, but it works even when GET_MODE (x) is larger
6849 than HOST_WIDE_INT. */
6850 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6851 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6852 && COMPARISON_P (XEXP (XEXP (x, 0), 0))
6853 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6854 <= HOST_BITS_PER_WIDE_INT)
6855 && (STORE_FLAG_VALUE & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6856 return XEXP (XEXP (x, 0), 0);
6858 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6859 if (GET_CODE (XEXP (x, 0)) == SUBREG
6860 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6861 && subreg_lowpart_p (XEXP (x, 0))
6862 && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
6863 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6864 <= HOST_BITS_PER_WIDE_INT)
6865 && (STORE_FLAG_VALUE & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6866 return SUBREG_REG (XEXP (x, 0));
6870 /* If we reach here, we want to return a pair of shifts. The inner
6871 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6872 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6873 logical depending on the value of UNSIGNEDP.
6875 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6876 converted into an AND of a shift.
6878 We must check for the case where the left shift would have a negative
6879 count. This can happen in a case like (x >> 31) & 255 on machines
6880 that can't shift by a constant. On those machines, we would first
6881 combine the shift with the AND to produce a variable-position
6882 extraction. Then the constant of 31 would be substituted in
6883 to produce such a position. */
6885 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
6886 if (modewidth >= pos + len)
6888 enum machine_mode mode = GET_MODE (x);
6889 tem = gen_lowpart (mode, XEXP (x, 0));
6890 if (!tem || GET_CODE (tem) == CLOBBER)
6892 tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
6893 tem, modewidth - pos - len);
6894 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
6895 mode, tem, modewidth - len);
6897 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
6898 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
6899 simplify_shift_const (NULL_RTX, LSHIFTRT,
6902 ((unsigned HOST_WIDE_INT) 1 << len) - 1);
6904 /* Any other cases we can't handle. */
6907 /* If we couldn't do this for some reason, return the original
6909 if (GET_CODE (tem) == CLOBBER)
6915 /* X is a SET which contains an assignment of one object into
6916 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6917 or certain SUBREGS). If possible, convert it into a series of
6920 We half-heartedly support variable positions, but do not at all
6921 support variable lengths. */
6924 expand_field_assignment (const_rtx x)
6927 rtx pos; /* Always counts from low bit. */
6929 rtx mask, cleared, masked;
6930 enum machine_mode compute_mode;
6932 /* Loop until we find something we can't simplify. */
6935 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
6936 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
6938 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
6939 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
6940 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
6942 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
6943 && CONST_INT_P (XEXP (SET_DEST (x), 1)))
6945 inner = XEXP (SET_DEST (x), 0);
6946 len = INTVAL (XEXP (SET_DEST (x), 1));
6947 pos = XEXP (SET_DEST (x), 2);
6949 /* A constant position should stay within the width of INNER. */
6950 if (CONST_INT_P (pos)
6951 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
6954 if (BITS_BIG_ENDIAN)
6956 if (CONST_INT_P (pos))
6957 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
6959 else if (GET_CODE (pos) == MINUS
6960 && CONST_INT_P (XEXP (pos, 1))
6961 && (INTVAL (XEXP (pos, 1))
6962 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
6963 /* If position is ADJUST - X, new position is X. */
6964 pos = XEXP (pos, 0);
6966 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
6967 GEN_INT (GET_MODE_BITSIZE (
6974 /* A SUBREG between two modes that occupy the same numbers of words
6975 can be done by moving the SUBREG to the source. */
6976 else if (GET_CODE (SET_DEST (x)) == SUBREG
6977 /* We need SUBREGs to compute nonzero_bits properly. */
6978 && nonzero_sign_valid
6979 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
6980 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
6981 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
6982 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
6984 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
6986 (GET_MODE (SUBREG_REG (SET_DEST (x))),
6993 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6994 inner = SUBREG_REG (inner);
6996 compute_mode = GET_MODE (inner);
6998 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6999 if (! SCALAR_INT_MODE_P (compute_mode))
7001 enum machine_mode imode;
7003 /* Don't do anything for vector or complex integral types. */
7004 if (! FLOAT_MODE_P (compute_mode))
7007 /* Try to find an integral mode to pun with. */
7008 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
7009 if (imode == BLKmode)
7012 compute_mode = imode;
7013 inner = gen_lowpart (imode, inner);
7016 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7017 if (len >= HOST_BITS_PER_WIDE_INT)
7020 /* Now compute the equivalent expression. Make a copy of INNER
7021 for the SET_DEST in case it is a MEM into which we will substitute;
7022 we don't want shared RTL in that case. */
7023 mask = GEN_INT (((unsigned HOST_WIDE_INT) 1 << len) - 1);
7024 cleared = simplify_gen_binary (AND, compute_mode,
7025 simplify_gen_unary (NOT, compute_mode,
7026 simplify_gen_binary (ASHIFT,
7031 masked = simplify_gen_binary (ASHIFT, compute_mode,
7032 simplify_gen_binary (
7034 gen_lowpart (compute_mode, SET_SRC (x)),
7038 x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
7039 simplify_gen_binary (IOR, compute_mode,
7046 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7047 it is an RTX that represents a variable starting position; otherwise,
7048 POS is the (constant) starting bit position (counted from the LSB).
7050 UNSIGNEDP is nonzero for an unsigned reference and zero for a
7053 IN_DEST is nonzero if this is a reference in the destination of a
7054 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7055 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7058 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7059 ZERO_EXTRACT should be built even for bits starting at bit 0.
7061 MODE is the desired mode of the result (if IN_DEST == 0).
7063 The result is an RTX for the extraction or NULL_RTX if the target
7067 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
7068 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
7069 int in_dest, int in_compare)
7071 /* This mode describes the size of the storage area
7072 to fetch the overall value from. Within that, we
7073 ignore the POS lowest bits, etc. */
7074 enum machine_mode is_mode = GET_MODE (inner);
7075 enum machine_mode inner_mode;
7076 enum machine_mode wanted_inner_mode;
7077 enum machine_mode wanted_inner_reg_mode = word_mode;
7078 enum machine_mode pos_mode = word_mode;
7079 enum machine_mode extraction_mode = word_mode;
7080 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
7082 rtx orig_pos_rtx = pos_rtx;
7083 HOST_WIDE_INT orig_pos;
7085 if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
7087 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7088 consider just the QI as the memory to extract from.
7089 The subreg adds or removes high bits; its mode is
7090 irrelevant to the meaning of this extraction,
7091 since POS and LEN count from the lsb. */
7092 if (MEM_P (SUBREG_REG (inner)))
7093 is_mode = GET_MODE (SUBREG_REG (inner));
7094 inner = SUBREG_REG (inner);
7096 else if (GET_CODE (inner) == ASHIFT
7097 && CONST_INT_P (XEXP (inner, 1))
7098 && pos_rtx == 0 && pos == 0
7099 && len > UINTVAL (XEXP (inner, 1)))
7101 /* We're extracting the least significant bits of an rtx
7102 (ashift X (const_int C)), where LEN > C. Extract the
7103 least significant (LEN - C) bits of X, giving an rtx
7104 whose mode is MODE, then shift it left C times. */
7105 new_rtx = make_extraction (mode, XEXP (inner, 0),
7106 0, 0, len - INTVAL (XEXP (inner, 1)),
7107 unsignedp, in_dest, in_compare);
7109 return gen_rtx_ASHIFT (mode, new_rtx, XEXP (inner, 1));
7112 inner_mode = GET_MODE (inner);
7114 if (pos_rtx && CONST_INT_P (pos_rtx))
7115 pos = INTVAL (pos_rtx), pos_rtx = 0;
7117 /* See if this can be done without an extraction. We never can if the
7118 width of the field is not the same as that of some integer mode. For
7119 registers, we can only avoid the extraction if the position is at the
7120 low-order bit and this is either not in the destination or we have the
7121 appropriate STRICT_LOW_PART operation available.
7123 For MEM, we can avoid an extract if the field starts on an appropriate
7124 boundary and we can change the mode of the memory reference. */
7126 if (tmode != BLKmode
7127 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
7129 && (inner_mode == tmode
7131 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
7132 GET_MODE_BITSIZE (inner_mode))
7133 || reg_truncated_to_mode (tmode, inner))
7136 && have_insn_for (STRICT_LOW_PART, tmode))))
7137 || (MEM_P (inner) && pos_rtx == 0
7139 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
7140 : BITS_PER_UNIT)) == 0
7141 /* We can't do this if we are widening INNER_MODE (it
7142 may not be aligned, for one thing). */
7143 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
7144 && (inner_mode == tmode
7145 || (! mode_dependent_address_p (XEXP (inner, 0))
7146 && ! MEM_VOLATILE_P (inner))))))
7148 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7149 field. If the original and current mode are the same, we need not
7150 adjust the offset. Otherwise, we do if bytes big endian.
7152 If INNER is not a MEM, get a piece consisting of just the field
7153 of interest (in this case POS % BITS_PER_WORD must be 0). */
7157 HOST_WIDE_INT offset;
7159 /* POS counts from lsb, but make OFFSET count in memory order. */
7160 if (BYTES_BIG_ENDIAN)
7161 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
7163 offset = pos / BITS_PER_UNIT;
7165 new_rtx = adjust_address_nv (inner, tmode, offset);
7167 else if (REG_P (inner))
7169 if (tmode != inner_mode)
7171 /* We can't call gen_lowpart in a DEST since we
7172 always want a SUBREG (see below) and it would sometimes
7173 return a new hard register. */
7176 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
7178 if (WORDS_BIG_ENDIAN
7179 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
7180 final_word = ((GET_MODE_SIZE (inner_mode)
7181 - GET_MODE_SIZE (tmode))
7182 / UNITS_PER_WORD) - final_word;
7184 final_word *= UNITS_PER_WORD;
7185 if (BYTES_BIG_ENDIAN &&
7186 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
7187 final_word += (GET_MODE_SIZE (inner_mode)
7188 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
7190 /* Avoid creating invalid subregs, for example when
7191 simplifying (x>>32)&255. */
7192 if (!validate_subreg (tmode, inner_mode, inner, final_word))
7195 new_rtx = gen_rtx_SUBREG (tmode, inner, final_word);
7198 new_rtx = gen_lowpart (tmode, inner);
7204 new_rtx = force_to_mode (inner, tmode,
7205 len >= HOST_BITS_PER_WIDE_INT
7206 ? ~(unsigned HOST_WIDE_INT) 0
7207 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7210 /* If this extraction is going into the destination of a SET,
7211 make a STRICT_LOW_PART unless we made a MEM. */
7214 return (MEM_P (new_rtx) ? new_rtx
7215 : (GET_CODE (new_rtx) != SUBREG
7216 ? gen_rtx_CLOBBER (tmode, const0_rtx)
7217 : gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx)));
7222 if (CONST_INT_P (new_rtx)
7223 || GET_CODE (new_rtx) == CONST_DOUBLE)
7224 return simplify_unary_operation (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7225 mode, new_rtx, tmode);
7227 /* If we know that no extraneous bits are set, and that the high
7228 bit is not set, convert the extraction to the cheaper of
7229 sign and zero extension, that are equivalent in these cases. */
7230 if (flag_expensive_optimizations
7231 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
7232 && ((nonzero_bits (new_rtx, tmode)
7233 & ~(((unsigned HOST_WIDE_INT)
7234 GET_MODE_MASK (tmode))
7238 rtx temp = gen_rtx_ZERO_EXTEND (mode, new_rtx);
7239 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new_rtx);
7241 /* Prefer ZERO_EXTENSION, since it gives more information to
7243 if (rtx_cost (temp, SET, optimize_this_for_speed_p)
7244 <= rtx_cost (temp1, SET, optimize_this_for_speed_p))
7249 /* Otherwise, sign- or zero-extend unless we already are in the
7252 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7256 /* Unless this is a COMPARE or we have a funny memory reference,
7257 don't do anything with zero-extending field extracts starting at
7258 the low-order bit since they are simple AND operations. */
7259 if (pos_rtx == 0 && pos == 0 && ! in_dest
7260 && ! in_compare && unsignedp)
7263 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7264 if the position is not a constant and the length is not 1. In all
7265 other cases, we would only be going outside our object in cases when
7266 an original shift would have been undefined. */
7268 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
7269 || (pos_rtx != 0 && len != 1)))
7272 /* Get the mode to use should INNER not be a MEM, the mode for the position,
7273 and the mode for the result. */
7274 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
7276 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
7277 pos_mode = mode_for_extraction (EP_insv, 2);
7278 extraction_mode = mode_for_extraction (EP_insv, 3);
7281 if (! in_dest && unsignedp
7282 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
7284 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
7285 pos_mode = mode_for_extraction (EP_extzv, 3);
7286 extraction_mode = mode_for_extraction (EP_extzv, 0);
7289 if (! in_dest && ! unsignedp
7290 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
7292 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
7293 pos_mode = mode_for_extraction (EP_extv, 3);
7294 extraction_mode = mode_for_extraction (EP_extv, 0);
7297 /* Never narrow an object, since that might not be safe. */
7299 if (mode != VOIDmode
7300 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
7301 extraction_mode = mode;
7303 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
7304 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
7305 pos_mode = GET_MODE (pos_rtx);
7307 /* If this is not from memory, the desired mode is the preferred mode
7308 for an extraction pattern's first input operand, or word_mode if there
7311 wanted_inner_mode = wanted_inner_reg_mode;
7314 /* Be careful not to go beyond the extracted object and maintain the
7315 natural alignment of the memory. */
7316 wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
7317 while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
7318 > GET_MODE_BITSIZE (wanted_inner_mode))
7320 wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
7321 gcc_assert (wanted_inner_mode != VOIDmode);
7324 /* If we have to change the mode of memory and cannot, the desired mode
7325 is EXTRACTION_MODE. */
7326 if (inner_mode != wanted_inner_mode
7327 && (mode_dependent_address_p (XEXP (inner, 0))
7328 || MEM_VOLATILE_P (inner)
7330 wanted_inner_mode = extraction_mode;
7335 if (BITS_BIG_ENDIAN)
7337 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7338 BITS_BIG_ENDIAN style. If position is constant, compute new
7339 position. Otherwise, build subtraction.
7340 Note that POS is relative to the mode of the original argument.
7341 If it's a MEM we need to recompute POS relative to that.
7342 However, if we're extracting from (or inserting into) a register,
7343 we want to recompute POS relative to wanted_inner_mode. */
7344 int width = (MEM_P (inner)
7345 ? GET_MODE_BITSIZE (is_mode)
7346 : GET_MODE_BITSIZE (wanted_inner_mode));
7349 pos = width - len - pos;
7352 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
7353 /* POS may be less than 0 now, but we check for that below.
7354 Note that it can only be less than 0 if !MEM_P (inner). */
7357 /* If INNER has a wider mode, and this is a constant extraction, try to
7358 make it smaller and adjust the byte to point to the byte containing
7360 if (wanted_inner_mode != VOIDmode
7361 && inner_mode != wanted_inner_mode
7363 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
7365 && ! mode_dependent_address_p (XEXP (inner, 0))
7366 && ! MEM_VOLATILE_P (inner))
7370 /* The computations below will be correct if the machine is big
7371 endian in both bits and bytes or little endian in bits and bytes.
7372 If it is mixed, we must adjust. */
7374 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7375 adjust OFFSET to compensate. */
7376 if (BYTES_BIG_ENDIAN
7377 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
7378 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
7380 /* We can now move to the desired byte. */
7381 offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
7382 * GET_MODE_SIZE (wanted_inner_mode);
7383 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
7385 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
7386 && is_mode != wanted_inner_mode)
7387 offset = (GET_MODE_SIZE (is_mode)
7388 - GET_MODE_SIZE (wanted_inner_mode) - offset);
7390 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
7393 /* If INNER is not memory, get it into the proper mode. If we are changing
7394 its mode, POS must be a constant and smaller than the size of the new
7396 else if (!MEM_P (inner))
7398 /* On the LHS, don't create paradoxical subregs implicitely truncating
7399 the register unless TRULY_NOOP_TRUNCATION. */
7401 && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE (inner)),
7402 GET_MODE_BITSIZE (wanted_inner_mode)))
7405 if (GET_MODE (inner) != wanted_inner_mode
7407 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
7413 inner = force_to_mode (inner, wanted_inner_mode,
7415 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
7416 ? ~(unsigned HOST_WIDE_INT) 0
7417 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
7422 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7423 have to zero extend. Otherwise, we can just use a SUBREG. */
7425 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
7427 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
7429 /* If we know that no extraneous bits are set, and that the high
7430 bit is not set, convert extraction to cheaper one - either
7431 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7433 if (flag_expensive_optimizations
7434 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
7435 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
7436 & ~(((unsigned HOST_WIDE_INT)
7437 GET_MODE_MASK (GET_MODE (pos_rtx)))
7441 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
7443 /* Prefer ZERO_EXTENSION, since it gives more information to
7445 if (rtx_cost (temp1, SET, optimize_this_for_speed_p)
7446 < rtx_cost (temp, SET, optimize_this_for_speed_p))
7451 else if (pos_rtx != 0
7452 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
7453 pos_rtx = gen_lowpart (pos_mode, pos_rtx);
7455 /* Make POS_RTX unless we already have it and it is correct. If we don't
7456 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7458 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
7459 pos_rtx = orig_pos_rtx;
7461 else if (pos_rtx == 0)
7462 pos_rtx = GEN_INT (pos);
7464 /* Make the required operation. See if we can use existing rtx. */
7465 new_rtx = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
7466 extraction_mode, inner, GEN_INT (len), pos_rtx);
7468 new_rtx = gen_lowpart (mode, new_rtx);
7473 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7474 with any other operations in X. Return X without that shift if so. */
7477 extract_left_shift (rtx x, int count)
7479 enum rtx_code code = GET_CODE (x);
7480 enum machine_mode mode = GET_MODE (x);
7486 /* This is the shift itself. If it is wide enough, we will return
7487 either the value being shifted if the shift count is equal to
7488 COUNT or a shift for the difference. */
7489 if (CONST_INT_P (XEXP (x, 1))
7490 && INTVAL (XEXP (x, 1)) >= count)
7491 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
7492 INTVAL (XEXP (x, 1)) - count);
7496 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7497 return simplify_gen_unary (code, mode, tem, mode);
7501 case PLUS: case IOR: case XOR: case AND:
7502 /* If we can safely shift this constant and we find the inner shift,
7503 make a new operation. */
7504 if (CONST_INT_P (XEXP (x, 1))
7505 && (UINTVAL (XEXP (x, 1))
7506 & ((((unsigned HOST_WIDE_INT) 1 << count)) - 1)) == 0
7507 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7508 return simplify_gen_binary (code, mode, tem,
7509 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
7520 /* Look at the expression rooted at X. Look for expressions
7521 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7522 Form these expressions.
7524 Return the new rtx, usually just X.
7526 Also, for machines like the VAX that don't have logical shift insns,
7527 try to convert logical to arithmetic shift operations in cases where
7528 they are equivalent. This undoes the canonicalizations to logical
7529 shifts done elsewhere.
7531 We try, as much as possible, to re-use rtl expressions to save memory.
7533 IN_CODE says what kind of expression we are processing. Normally, it is
7534 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
7535 being kludges), it is MEM. When processing the arguments of a comparison
7536 or a COMPARE against zero, it is COMPARE. */
7539 make_compound_operation (rtx x, enum rtx_code in_code)
7541 enum rtx_code code = GET_CODE (x);
7542 enum machine_mode mode = GET_MODE (x);
7543 int mode_width = GET_MODE_BITSIZE (mode);
7545 enum rtx_code next_code;
7551 /* Select the code to be used in recursive calls. Once we are inside an
7552 address, we stay there. If we have a comparison, set to COMPARE,
7553 but once inside, go back to our default of SET. */
7555 next_code = (code == MEM ? MEM
7556 : ((code == PLUS || code == MINUS)
7557 && SCALAR_INT_MODE_P (mode)) ? MEM
7558 : ((code == COMPARE || COMPARISON_P (x))
7559 && XEXP (x, 1) == const0_rtx) ? COMPARE
7560 : in_code == COMPARE ? SET : in_code);
7562 /* Process depending on the code of this operation. If NEW is set
7563 nonzero, it will be returned. */
7568 /* Convert shifts by constants into multiplications if inside
7570 if (in_code == MEM && CONST_INT_P (XEXP (x, 1))
7571 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7572 && INTVAL (XEXP (x, 1)) >= 0
7573 && SCALAR_INT_MODE_P (mode))
7575 HOST_WIDE_INT count = INTVAL (XEXP (x, 1));
7576 HOST_WIDE_INT multval = (HOST_WIDE_INT) 1 << count;
7578 new_rtx = make_compound_operation (XEXP (x, 0), next_code);
7579 if (GET_CODE (new_rtx) == NEG)
7581 new_rtx = XEXP (new_rtx, 0);
7584 multval = trunc_int_for_mode (multval, mode);
7585 new_rtx = gen_rtx_MULT (mode, new_rtx, GEN_INT (multval));
7592 lhs = make_compound_operation (lhs, next_code);
7593 rhs = make_compound_operation (rhs, next_code);
7594 if (GET_CODE (lhs) == MULT && GET_CODE (XEXP (lhs, 0)) == NEG
7595 && SCALAR_INT_MODE_P (mode))
7597 tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (lhs, 0), 0),
7599 new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
7601 else if (GET_CODE (lhs) == MULT
7602 && (CONST_INT_P (XEXP (lhs, 1)) && INTVAL (XEXP (lhs, 1)) < 0))
7604 tem = simplify_gen_binary (MULT, mode, XEXP (lhs, 0),
7605 simplify_gen_unary (NEG, mode,
7608 new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
7612 SUBST (XEXP (x, 0), lhs);
7613 SUBST (XEXP (x, 1), rhs);
7616 x = gen_lowpart (mode, new_rtx);
7622 lhs = make_compound_operation (lhs, next_code);
7623 rhs = make_compound_operation (rhs, next_code);
7624 if (GET_CODE (rhs) == MULT && GET_CODE (XEXP (rhs, 0)) == NEG
7625 && SCALAR_INT_MODE_P (mode))
7627 tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (rhs, 0), 0),
7629 new_rtx = simplify_gen_binary (PLUS, mode, tem, lhs);
7631 else if (GET_CODE (rhs) == MULT
7632 && (CONST_INT_P (XEXP (rhs, 1)) && INTVAL (XEXP (rhs, 1)) < 0))
7634 tem = simplify_gen_binary (MULT, mode, XEXP (rhs, 0),
7635 simplify_gen_unary (NEG, mode,
7638 new_rtx = simplify_gen_binary (PLUS, mode, tem, lhs);
7642 SUBST (XEXP (x, 0), lhs);
7643 SUBST (XEXP (x, 1), rhs);
7646 return gen_lowpart (mode, new_rtx);
7649 /* If the second operand is not a constant, we can't do anything
7651 if (!CONST_INT_P (XEXP (x, 1)))
7654 /* If the constant is a power of two minus one and the first operand
7655 is a logical right shift, make an extraction. */
7656 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7657 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7659 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7660 new_rtx = make_extraction (mode, new_rtx, 0, XEXP (XEXP (x, 0), 1), i, 1,
7661 0, in_code == COMPARE);
7664 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7665 else if (GET_CODE (XEXP (x, 0)) == SUBREG
7666 && subreg_lowpart_p (XEXP (x, 0))
7667 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
7668 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7670 new_rtx = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
7672 new_rtx = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new_rtx, 0,
7673 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
7674 0, in_code == COMPARE);
7676 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7677 else if ((GET_CODE (XEXP (x, 0)) == XOR
7678 || GET_CODE (XEXP (x, 0)) == IOR)
7679 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
7680 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
7681 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7683 /* Apply the distributive law, and then try to make extractions. */
7684 new_rtx = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
7685 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
7687 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
7689 new_rtx = make_compound_operation (new_rtx, in_code);
7692 /* If we are have (and (rotate X C) M) and C is larger than the number
7693 of bits in M, this is an extraction. */
7695 else if (GET_CODE (XEXP (x, 0)) == ROTATE
7696 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7697 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0
7698 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
7700 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7701 new_rtx = make_extraction (mode, new_rtx,
7702 (GET_MODE_BITSIZE (mode)
7703 - INTVAL (XEXP (XEXP (x, 0), 1))),
7704 NULL_RTX, i, 1, 0, in_code == COMPARE);
7707 /* On machines without logical shifts, if the operand of the AND is
7708 a logical shift and our mask turns off all the propagated sign
7709 bits, we can replace the logical shift with an arithmetic shift. */
7710 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7711 && !have_insn_for (LSHIFTRT, mode)
7712 && have_insn_for (ASHIFTRT, mode)
7713 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7714 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7715 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7716 && mode_width <= HOST_BITS_PER_WIDE_INT)
7718 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
7720 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
7721 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
7723 gen_rtx_ASHIFTRT (mode,
7724 make_compound_operation
7725 (XEXP (XEXP (x, 0), 0), next_code),
7726 XEXP (XEXP (x, 0), 1)));
7729 /* If the constant is one less than a power of two, this might be
7730 representable by an extraction even if no shift is present.
7731 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7732 we are in a COMPARE. */
7733 else if ((i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7734 new_rtx = make_extraction (mode,
7735 make_compound_operation (XEXP (x, 0),
7737 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
7739 /* If we are in a comparison and this is an AND with a power of two,
7740 convert this into the appropriate bit extract. */
7741 else if (in_code == COMPARE
7742 && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0)
7743 new_rtx = make_extraction (mode,
7744 make_compound_operation (XEXP (x, 0),
7746 i, NULL_RTX, 1, 1, 0, 1);
7751 /* If the sign bit is known to be zero, replace this with an
7752 arithmetic shift. */
7753 if (have_insn_for (ASHIFTRT, mode)
7754 && ! have_insn_for (LSHIFTRT, mode)
7755 && mode_width <= HOST_BITS_PER_WIDE_INT
7756 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
7758 new_rtx = gen_rtx_ASHIFTRT (mode,
7759 make_compound_operation (XEXP (x, 0),
7765 /* ... fall through ... */
7771 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7772 this is a SIGN_EXTRACT. */
7773 if (CONST_INT_P (rhs)
7774 && GET_CODE (lhs) == ASHIFT
7775 && CONST_INT_P (XEXP (lhs, 1))
7776 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))
7777 && INTVAL (XEXP (lhs, 1)) >= 0
7778 && INTVAL (rhs) < mode_width)
7780 new_rtx = make_compound_operation (XEXP (lhs, 0), next_code);
7781 new_rtx = make_extraction (mode, new_rtx,
7782 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
7783 NULL_RTX, mode_width - INTVAL (rhs),
7784 code == LSHIFTRT, 0, in_code == COMPARE);
7788 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7789 If so, try to merge the shifts into a SIGN_EXTEND. We could
7790 also do this for some cases of SIGN_EXTRACT, but it doesn't
7791 seem worth the effort; the case checked for occurs on Alpha. */
7794 && ! (GET_CODE (lhs) == SUBREG
7795 && (OBJECT_P (SUBREG_REG (lhs))))
7796 && CONST_INT_P (rhs)
7797 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
7798 && INTVAL (rhs) < mode_width
7799 && (new_rtx = extract_left_shift (lhs, INTVAL (rhs))) != 0)
7800 new_rtx = make_extraction (mode, make_compound_operation (new_rtx, next_code),
7801 0, NULL_RTX, mode_width - INTVAL (rhs),
7802 code == LSHIFTRT, 0, in_code == COMPARE);
7807 /* Call ourselves recursively on the inner expression. If we are
7808 narrowing the object and it has a different RTL code from
7809 what it originally did, do this SUBREG as a force_to_mode. */
7811 rtx inner = SUBREG_REG (x), simplified;
7813 tem = make_compound_operation (inner, in_code);
7816 = simplify_subreg (mode, tem, GET_MODE (inner), SUBREG_BYTE (x));
7820 if (GET_CODE (tem) != GET_CODE (inner)
7821 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (inner))
7822 && subreg_lowpart_p (x))
7825 = force_to_mode (tem, mode, ~(unsigned HOST_WIDE_INT) 0, 0);
7827 /* If we have something other than a SUBREG, we might have
7828 done an expansion, so rerun ourselves. */
7829 if (GET_CODE (newer) != SUBREG)
7830 newer = make_compound_operation (newer, in_code);
7832 /* force_to_mode can expand compounds. If it just re-expanded the
7833 compound, use gen_lowpart to convert to the desired mode. */
7834 if (rtx_equal_p (newer, x)
7835 /* Likewise if it re-expanded the compound only partially.
7836 This happens for SUBREG of ZERO_EXTRACT if they extract
7837 the same number of bits. */
7838 || (GET_CODE (newer) == SUBREG
7839 && (GET_CODE (SUBREG_REG (newer)) == LSHIFTRT
7840 || GET_CODE (SUBREG_REG (newer)) == ASHIFTRT)
7841 && GET_CODE (inner) == AND
7842 && rtx_equal_p (SUBREG_REG (newer), XEXP (inner, 0))))
7843 return gen_lowpart (GET_MODE (x), tem);
7859 x = gen_lowpart (mode, new_rtx);
7860 code = GET_CODE (x);
7863 /* Now recursively process each operand of this operation. */
7864 fmt = GET_RTX_FORMAT (code);
7865 for (i = 0; i < GET_RTX_LENGTH (code); i++)
7868 new_rtx = make_compound_operation (XEXP (x, i), next_code);
7869 SUBST (XEXP (x, i), new_rtx);
7871 else if (fmt[i] == 'E')
7872 for (j = 0; j < XVECLEN (x, i); j++)
7874 new_rtx = make_compound_operation (XVECEXP (x, i, j), next_code);
7875 SUBST (XVECEXP (x, i, j), new_rtx);
7879 /* If this is a commutative operation, the changes to the operands
7880 may have made it noncanonical. */
7881 if (COMMUTATIVE_ARITH_P (x)
7882 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
7885 SUBST (XEXP (x, 0), XEXP (x, 1));
7886 SUBST (XEXP (x, 1), tem);
7892 /* Given M see if it is a value that would select a field of bits
7893 within an item, but not the entire word. Return -1 if not.
7894 Otherwise, return the starting position of the field, where 0 is the
7897 *PLEN is set to the length of the field. */
7900 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
7902 /* Get the bit number of the first 1 bit from the right, -1 if none. */
7903 int pos = m ? ctz_hwi (m) : -1;
7907 /* Now shift off the low-order zero bits and see if we have a
7908 power of two minus 1. */
7909 len = exact_log2 ((m >> pos) + 1);
7918 /* If X refers to a register that equals REG in value, replace these
7919 references with REG. */
7921 canon_reg_for_combine (rtx x, rtx reg)
7928 enum rtx_code code = GET_CODE (x);
7929 switch (GET_RTX_CLASS (code))
7932 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7933 if (op0 != XEXP (x, 0))
7934 return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
7939 case RTX_COMM_ARITH:
7940 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7941 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7942 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7943 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
7947 case RTX_COMM_COMPARE:
7948 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7949 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7950 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7951 return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
7952 GET_MODE (op0), op0, op1);
7956 case RTX_BITFIELD_OPS:
7957 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7958 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7959 op2 = canon_reg_for_combine (XEXP (x, 2), reg);
7960 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
7961 return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
7962 GET_MODE (op0), op0, op1, op2);
7967 if (rtx_equal_p (get_last_value (reg), x)
7968 || rtx_equal_p (reg, get_last_value (x)))
7977 fmt = GET_RTX_FORMAT (code);
7979 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7982 rtx op = canon_reg_for_combine (XEXP (x, i), reg);
7983 if (op != XEXP (x, i))
7993 else if (fmt[i] == 'E')
7996 for (j = 0; j < XVECLEN (x, i); j++)
7998 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
7999 if (op != XVECEXP (x, i, j))
8006 XVECEXP (x, i, j) = op;
8017 /* Return X converted to MODE. If the value is already truncated to
8018 MODE we can just return a subreg even though in the general case we
8019 would need an explicit truncation. */
8022 gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
8024 if (!CONST_INT_P (x)
8025 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
8026 && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
8027 GET_MODE_BITSIZE (GET_MODE (x)))
8028 && !(REG_P (x) && reg_truncated_to_mode (mode, x)))
8030 /* Bit-cast X into an integer mode. */
8031 if (!SCALAR_INT_MODE_P (GET_MODE (x)))
8032 x = gen_lowpart (int_mode_for_mode (GET_MODE (x)), x);
8033 x = simplify_gen_unary (TRUNCATE, int_mode_for_mode (mode),
8037 return gen_lowpart (mode, x);
8040 /* See if X can be simplified knowing that we will only refer to it in
8041 MODE and will only refer to those bits that are nonzero in MASK.
8042 If other bits are being computed or if masking operations are done
8043 that select a superset of the bits in MASK, they can sometimes be
8046 Return a possibly simplified expression, but always convert X to
8047 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8049 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8050 are all off in X. This is used when X will be complemented, by either
8051 NOT, NEG, or XOR. */
8054 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
8057 enum rtx_code code = GET_CODE (x);
8058 int next_select = just_select || code == XOR || code == NOT || code == NEG;
8059 enum machine_mode op_mode;
8060 unsigned HOST_WIDE_INT fuller_mask, nonzero;
8063 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8064 code below will do the wrong thing since the mode of such an
8065 expression is VOIDmode.
8067 Also do nothing if X is a CLOBBER; this can happen if X was
8068 the return value from a call to gen_lowpart. */
8069 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
8072 /* We want to perform the operation is its present mode unless we know
8073 that the operation is valid in MODE, in which case we do the operation
8075 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
8076 && have_insn_for (code, mode))
8077 ? mode : GET_MODE (x));
8079 /* It is not valid to do a right-shift in a narrower mode
8080 than the one it came in with. */
8081 if ((code == LSHIFTRT || code == ASHIFTRT)
8082 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
8083 op_mode = GET_MODE (x);
8085 /* Truncate MASK to fit OP_MODE. */
8087 mask &= GET_MODE_MASK (op_mode);
8089 /* When we have an arithmetic operation, or a shift whose count we
8090 do not know, we need to assume that all bits up to the highest-order
8091 bit in MASK will be needed. This is how we form such a mask. */
8092 if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
8093 fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
8095 fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
8098 /* Determine what bits of X are guaranteed to be (non)zero. */
8099 nonzero = nonzero_bits (x, mode);
8101 /* If none of the bits in X are needed, return a zero. */
8102 if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
8105 /* If X is a CONST_INT, return a new one. Do this here since the
8106 test below will fail. */
8107 if (CONST_INT_P (x))
8109 if (SCALAR_INT_MODE_P (mode))
8110 return gen_int_mode (INTVAL (x) & mask, mode);
8113 x = GEN_INT (INTVAL (x) & mask);
8114 return gen_lowpart_common (mode, x);
8118 /* If X is narrower than MODE and we want all the bits in X's mode, just
8119 get X in the proper mode. */
8120 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
8121 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
8122 return gen_lowpart (mode, x);
8124 /* We can ignore the effect of a SUBREG if it narrows the mode or
8125 if the constant masks to zero all the bits the mode doesn't have. */
8126 if (GET_CODE (x) == SUBREG
8127 && subreg_lowpart_p (x)
8128 && ((GET_MODE_SIZE (GET_MODE (x))
8129 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8131 & GET_MODE_MASK (GET_MODE (x))
8132 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
8133 return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
8135 /* The arithmetic simplifications here only work for scalar integer modes. */
8136 if (!SCALAR_INT_MODE_P (mode) || !SCALAR_INT_MODE_P (GET_MODE (x)))
8137 return gen_lowpart_or_truncate (mode, x);
8142 /* If X is a (clobber (const_int)), return it since we know we are
8143 generating something that won't match. */
8150 x = expand_compound_operation (x);
8151 if (GET_CODE (x) != code)
8152 return force_to_mode (x, mode, mask, next_select);
8156 /* Similarly for a truncate. */
8157 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8160 /* If this is an AND with a constant, convert it into an AND
8161 whose constant is the AND of that constant with MASK. If it
8162 remains an AND of MASK, delete it since it is redundant. */
8164 if (CONST_INT_P (XEXP (x, 1)))
8166 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
8167 mask & INTVAL (XEXP (x, 1)));
8169 /* If X is still an AND, see if it is an AND with a mask that
8170 is just some low-order bits. If so, and it is MASK, we don't
8173 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8174 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
8178 /* If it remains an AND, try making another AND with the bits
8179 in the mode mask that aren't in MASK turned on. If the
8180 constant in the AND is wide enough, this might make a
8181 cheaper constant. */
8183 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8184 && GET_MODE_MASK (GET_MODE (x)) != mask
8185 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
8187 unsigned HOST_WIDE_INT cval
8188 = UINTVAL (XEXP (x, 1))
8189 | (GET_MODE_MASK (GET_MODE (x)) & ~mask);
8190 int width = GET_MODE_BITSIZE (GET_MODE (x));
8193 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
8194 number, sign extend it. */
8195 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
8196 && (cval & ((unsigned HOST_WIDE_INT) 1 << (width - 1))) != 0)
8197 cval |= (unsigned HOST_WIDE_INT) -1 << width;
8199 y = simplify_gen_binary (AND, GET_MODE (x),
8200 XEXP (x, 0), GEN_INT (cval));
8201 if (rtx_cost (y, SET, optimize_this_for_speed_p)
8202 < rtx_cost (x, SET, optimize_this_for_speed_p))
8212 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8213 low-order bits (as in an alignment operation) and FOO is already
8214 aligned to that boundary, mask C1 to that boundary as well.
8215 This may eliminate that PLUS and, later, the AND. */
8218 unsigned int width = GET_MODE_BITSIZE (mode);
8219 unsigned HOST_WIDE_INT smask = mask;
8221 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8222 number, sign extend it. */
8224 if (width < HOST_BITS_PER_WIDE_INT
8225 && (smask & ((unsigned HOST_WIDE_INT) 1 << (width - 1))) != 0)
8226 smask |= (unsigned HOST_WIDE_INT) (-1) << width;
8228 if (CONST_INT_P (XEXP (x, 1))
8229 && exact_log2 (- smask) >= 0
8230 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
8231 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
8232 return force_to_mode (plus_constant (XEXP (x, 0),
8233 (INTVAL (XEXP (x, 1)) & smask)),
8234 mode, smask, next_select);
8237 /* ... fall through ... */
8240 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8241 most significant bit in MASK since carries from those bits will
8242 affect the bits we are interested in. */
8247 /* If X is (minus C Y) where C's least set bit is larger than any bit
8248 in the mask, then we may replace with (neg Y). */
8249 if (CONST_INT_P (XEXP (x, 0))
8250 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
8251 & -INTVAL (XEXP (x, 0))))
8254 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
8256 return force_to_mode (x, mode, mask, next_select);
8259 /* Similarly, if C contains every bit in the fuller_mask, then we may
8260 replace with (not Y). */
8261 if (CONST_INT_P (XEXP (x, 0))
8262 && ((UINTVAL (XEXP (x, 0)) | fuller_mask) == UINTVAL (XEXP (x, 0))))
8264 x = simplify_gen_unary (NOT, GET_MODE (x),
8265 XEXP (x, 1), GET_MODE (x));
8266 return force_to_mode (x, mode, mask, next_select);
8274 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8275 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8276 operation which may be a bitfield extraction. Ensure that the
8277 constant we form is not wider than the mode of X. */
8279 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8280 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8281 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8282 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
8283 && CONST_INT_P (XEXP (x, 1))
8284 && ((INTVAL (XEXP (XEXP (x, 0), 1))
8285 + floor_log2 (INTVAL (XEXP (x, 1))))
8286 < GET_MODE_BITSIZE (GET_MODE (x)))
8287 && (UINTVAL (XEXP (x, 1))
8288 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
8290 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
8291 << INTVAL (XEXP (XEXP (x, 0), 1)));
8292 temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
8293 XEXP (XEXP (x, 0), 0), temp);
8294 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
8295 XEXP (XEXP (x, 0), 1));
8296 return force_to_mode (x, mode, mask, next_select);
8300 /* For most binary operations, just propagate into the operation and
8301 change the mode if we have an operation of that mode. */
8303 op0 = force_to_mode (XEXP (x, 0), mode, mask, next_select);
8304 op1 = force_to_mode (XEXP (x, 1), mode, mask, next_select);
8306 /* If we ended up truncating both operands, truncate the result of the
8307 operation instead. */
8308 if (GET_CODE (op0) == TRUNCATE
8309 && GET_CODE (op1) == TRUNCATE)
8311 op0 = XEXP (op0, 0);
8312 op1 = XEXP (op1, 0);
8315 op0 = gen_lowpart_or_truncate (op_mode, op0);
8316 op1 = gen_lowpart_or_truncate (op_mode, op1);
8318 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8319 x = simplify_gen_binary (code, op_mode, op0, op1);
8323 /* For left shifts, do the same, but just for the first operand.
8324 However, we cannot do anything with shifts where we cannot
8325 guarantee that the counts are smaller than the size of the mode
8326 because such a count will have a different meaning in a
8329 if (! (CONST_INT_P (XEXP (x, 1))
8330 && INTVAL (XEXP (x, 1)) >= 0
8331 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
8332 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
8333 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
8334 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
8337 /* If the shift count is a constant and we can do arithmetic in
8338 the mode of the shift, refine which bits we need. Otherwise, use the
8339 conservative form of the mask. */
8340 if (CONST_INT_P (XEXP (x, 1))
8341 && INTVAL (XEXP (x, 1)) >= 0
8342 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
8343 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
8344 mask >>= INTVAL (XEXP (x, 1));
8348 op0 = gen_lowpart_or_truncate (op_mode,
8349 force_to_mode (XEXP (x, 0), op_mode,
8350 mask, next_select));
8352 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8353 x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
8357 /* Here we can only do something if the shift count is a constant,
8358 this shift constant is valid for the host, and we can do arithmetic
8361 if (CONST_INT_P (XEXP (x, 1))
8362 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
8363 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
8365 rtx inner = XEXP (x, 0);
8366 unsigned HOST_WIDE_INT inner_mask;
8368 /* Select the mask of the bits we need for the shift operand. */
8369 inner_mask = mask << INTVAL (XEXP (x, 1));
8371 /* We can only change the mode of the shift if we can do arithmetic
8372 in the mode of the shift and INNER_MASK is no wider than the
8373 width of X's mode. */
8374 if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
8375 op_mode = GET_MODE (x);
8377 inner = force_to_mode (inner, op_mode, inner_mask, next_select);
8379 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
8380 x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
8383 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8384 shift and AND produces only copies of the sign bit (C2 is one less
8385 than a power of two), we can do this with just a shift. */
8387 if (GET_CODE (x) == LSHIFTRT
8388 && CONST_INT_P (XEXP (x, 1))
8389 /* The shift puts one of the sign bit copies in the least significant
8391 && ((INTVAL (XEXP (x, 1))
8392 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
8393 >= GET_MODE_BITSIZE (GET_MODE (x)))
8394 && exact_log2 (mask + 1) >= 0
8395 /* Number of bits left after the shift must be more than the mask
8397 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
8398 <= GET_MODE_BITSIZE (GET_MODE (x)))
8399 /* Must be more sign bit copies than the mask needs. */
8400 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
8401 >= exact_log2 (mask + 1)))
8402 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
8403 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
8404 - exact_log2 (mask + 1)));
8409 /* If we are just looking for the sign bit, we don't need this shift at
8410 all, even if it has a variable count. */
8411 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
8412 && (mask == ((unsigned HOST_WIDE_INT) 1
8413 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8414 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8416 /* If this is a shift by a constant, get a mask that contains those bits
8417 that are not copies of the sign bit. We then have two cases: If
8418 MASK only includes those bits, this can be a logical shift, which may
8419 allow simplifications. If MASK is a single-bit field not within
8420 those bits, we are requesting a copy of the sign bit and hence can
8421 shift the sign bit to the appropriate location. */
8423 if (CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) >= 0
8424 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8428 /* If the considered data is wider than HOST_WIDE_INT, we can't
8429 represent a mask for all its bits in a single scalar.
8430 But we only care about the lower bits, so calculate these. */
8432 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
8434 nonzero = ~(unsigned HOST_WIDE_INT) 0;
8436 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8437 is the number of bits a full-width mask would have set.
8438 We need only shift if these are fewer than nonzero can
8439 hold. If not, we must keep all bits set in nonzero. */
8441 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8442 < HOST_BITS_PER_WIDE_INT)
8443 nonzero >>= INTVAL (XEXP (x, 1))
8444 + HOST_BITS_PER_WIDE_INT
8445 - GET_MODE_BITSIZE (GET_MODE (x)) ;
8449 nonzero = GET_MODE_MASK (GET_MODE (x));
8450 nonzero >>= INTVAL (XEXP (x, 1));
8453 if ((mask & ~nonzero) == 0)
8455 x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
8456 XEXP (x, 0), INTVAL (XEXP (x, 1)));
8457 if (GET_CODE (x) != ASHIFTRT)
8458 return force_to_mode (x, mode, mask, next_select);
8461 else if ((i = exact_log2 (mask)) >= 0)
8463 x = simplify_shift_const
8464 (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
8465 GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
8467 if (GET_CODE (x) != ASHIFTRT)
8468 return force_to_mode (x, mode, mask, next_select);
8472 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8473 even if the shift count isn't a constant. */
8475 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8476 XEXP (x, 0), XEXP (x, 1));
8480 /* If this is a zero- or sign-extension operation that just affects bits
8481 we don't care about, remove it. Be sure the call above returned
8482 something that is still a shift. */
8484 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
8485 && CONST_INT_P (XEXP (x, 1))
8486 && INTVAL (XEXP (x, 1)) >= 0
8487 && (INTVAL (XEXP (x, 1))
8488 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
8489 && GET_CODE (XEXP (x, 0)) == ASHIFT
8490 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
8491 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
8498 /* If the shift count is constant and we can do computations
8499 in the mode of X, compute where the bits we care about are.
8500 Otherwise, we can't do anything. Don't change the mode of
8501 the shift or propagate MODE into the shift, though. */
8502 if (CONST_INT_P (XEXP (x, 1))
8503 && INTVAL (XEXP (x, 1)) >= 0)
8505 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
8506 GET_MODE (x), GEN_INT (mask),
8508 if (temp && CONST_INT_P (temp))
8510 force_to_mode (XEXP (x, 0), GET_MODE (x),
8511 INTVAL (temp), next_select));
8516 /* If we just want the low-order bit, the NEG isn't needed since it
8517 won't change the low-order bit. */
8519 return force_to_mode (XEXP (x, 0), mode, mask, just_select);
8521 /* We need any bits less significant than the most significant bit in
8522 MASK since carries from those bits will affect the bits we are
8528 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8529 same as the XOR case above. Ensure that the constant we form is not
8530 wider than the mode of X. */
8532 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8533 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8534 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8535 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
8536 < GET_MODE_BITSIZE (GET_MODE (x)))
8537 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
8539 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
8541 temp = simplify_gen_binary (XOR, GET_MODE (x),
8542 XEXP (XEXP (x, 0), 0), temp);
8543 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8544 temp, XEXP (XEXP (x, 0), 1));
8546 return force_to_mode (x, mode, mask, next_select);
8549 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8550 use the full mask inside the NOT. */
8554 op0 = gen_lowpart_or_truncate (op_mode,
8555 force_to_mode (XEXP (x, 0), mode, mask,
8557 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8558 x = simplify_gen_unary (code, op_mode, op0, op_mode);
8562 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8563 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8564 which is equal to STORE_FLAG_VALUE. */
8565 if ((mask & ~STORE_FLAG_VALUE) == 0
8566 && XEXP (x, 1) == const0_rtx
8567 && GET_MODE (XEXP (x, 0)) == mode
8568 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
8569 && (nonzero_bits (XEXP (x, 0), mode)
8570 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
8571 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8576 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8577 written in a narrower mode. We play it safe and do not do so. */
8580 gen_lowpart_or_truncate (GET_MODE (x),
8581 force_to_mode (XEXP (x, 1), mode,
8582 mask, next_select)));
8584 gen_lowpart_or_truncate (GET_MODE (x),
8585 force_to_mode (XEXP (x, 2), mode,
8586 mask, next_select)));
8593 /* Ensure we return a value of the proper mode. */
8594 return gen_lowpart_or_truncate (mode, x);
8597 /* Return nonzero if X is an expression that has one of two values depending on
8598 whether some other value is zero or nonzero. In that case, we return the
8599 value that is being tested, *PTRUE is set to the value if the rtx being
8600 returned has a nonzero value, and *PFALSE is set to the other alternative.
8602 If we return zero, we set *PTRUE and *PFALSE to X. */
8605 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
8607 enum machine_mode mode = GET_MODE (x);
8608 enum rtx_code code = GET_CODE (x);
8609 rtx cond0, cond1, true0, true1, false0, false1;
8610 unsigned HOST_WIDE_INT nz;
8612 /* If we are comparing a value against zero, we are done. */
8613 if ((code == NE || code == EQ)
8614 && XEXP (x, 1) == const0_rtx)
8616 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
8617 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
8621 /* If this is a unary operation whose operand has one of two values, apply
8622 our opcode to compute those values. */
8623 else if (UNARY_P (x)
8624 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
8626 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
8627 *pfalse = simplify_gen_unary (code, mode, false0,
8628 GET_MODE (XEXP (x, 0)));
8632 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8633 make can't possibly match and would suppress other optimizations. */
8634 else if (code == COMPARE)
8637 /* If this is a binary operation, see if either side has only one of two
8638 values. If either one does or if both do and they are conditional on
8639 the same value, compute the new true and false values. */
8640 else if (BINARY_P (x))
8642 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
8643 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
8645 if ((cond0 != 0 || cond1 != 0)
8646 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
8648 /* If if_then_else_cond returned zero, then true/false are the
8649 same rtl. We must copy one of them to prevent invalid rtl
8652 true0 = copy_rtx (true0);
8653 else if (cond1 == 0)
8654 true1 = copy_rtx (true1);
8656 if (COMPARISON_P (x))
8658 *ptrue = simplify_gen_relational (code, mode, VOIDmode,
8660 *pfalse = simplify_gen_relational (code, mode, VOIDmode,
8665 *ptrue = simplify_gen_binary (code, mode, true0, true1);
8666 *pfalse = simplify_gen_binary (code, mode, false0, false1);
8669 return cond0 ? cond0 : cond1;
8672 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8673 operands is zero when the other is nonzero, and vice-versa,
8674 and STORE_FLAG_VALUE is 1 or -1. */
8676 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8677 && (code == PLUS || code == IOR || code == XOR || code == MINUS
8679 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8681 rtx op0 = XEXP (XEXP (x, 0), 1);
8682 rtx op1 = XEXP (XEXP (x, 1), 1);
8684 cond0 = XEXP (XEXP (x, 0), 0);
8685 cond1 = XEXP (XEXP (x, 1), 0);
8687 if (COMPARISON_P (cond0)
8688 && COMPARISON_P (cond1)
8689 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8690 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8691 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8692 || ((swap_condition (GET_CODE (cond0))
8693 == reversed_comparison_code (cond1, NULL))
8694 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8695 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8696 && ! side_effects_p (x))
8698 *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
8699 *pfalse = simplify_gen_binary (MULT, mode,
8701 ? simplify_gen_unary (NEG, mode,
8709 /* Similarly for MULT, AND and UMIN, except that for these the result
8711 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8712 && (code == MULT || code == AND || code == UMIN)
8713 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8715 cond0 = XEXP (XEXP (x, 0), 0);
8716 cond1 = XEXP (XEXP (x, 1), 0);
8718 if (COMPARISON_P (cond0)
8719 && COMPARISON_P (cond1)
8720 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8721 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8722 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8723 || ((swap_condition (GET_CODE (cond0))
8724 == reversed_comparison_code (cond1, NULL))
8725 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8726 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8727 && ! side_effects_p (x))
8729 *ptrue = *pfalse = const0_rtx;
8735 else if (code == IF_THEN_ELSE)
8737 /* If we have IF_THEN_ELSE already, extract the condition and
8738 canonicalize it if it is NE or EQ. */
8739 cond0 = XEXP (x, 0);
8740 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
8741 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
8742 return XEXP (cond0, 0);
8743 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
8745 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
8746 return XEXP (cond0, 0);
8752 /* If X is a SUBREG, we can narrow both the true and false values
8753 if the inner expression, if there is a condition. */
8754 else if (code == SUBREG
8755 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
8758 true0 = simplify_gen_subreg (mode, true0,
8759 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8760 false0 = simplify_gen_subreg (mode, false0,
8761 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8762 if (true0 && false0)
8770 /* If X is a constant, this isn't special and will cause confusions
8771 if we treat it as such. Likewise if it is equivalent to a constant. */
8772 else if (CONSTANT_P (x)
8773 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
8776 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8777 will be least confusing to the rest of the compiler. */
8778 else if (mode == BImode)
8780 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
8784 /* If X is known to be either 0 or -1, those are the true and
8785 false values when testing X. */
8786 else if (x == constm1_rtx || x == const0_rtx
8787 || (mode != VOIDmode
8788 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
8790 *ptrue = constm1_rtx, *pfalse = const0_rtx;
8794 /* Likewise for 0 or a single bit. */
8795 else if (SCALAR_INT_MODE_P (mode)
8796 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8797 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
8799 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
8803 /* Otherwise fail; show no condition with true and false values the same. */
8804 *ptrue = *pfalse = x;
8808 /* Return the value of expression X given the fact that condition COND
8809 is known to be true when applied to REG as its first operand and VAL
8810 as its second. X is known to not be shared and so can be modified in
8813 We only handle the simplest cases, and specifically those cases that
8814 arise with IF_THEN_ELSE expressions. */
8817 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
8819 enum rtx_code code = GET_CODE (x);
8824 if (side_effects_p (x))
8827 /* If either operand of the condition is a floating point value,
8828 then we have to avoid collapsing an EQ comparison. */
8830 && rtx_equal_p (x, reg)
8831 && ! FLOAT_MODE_P (GET_MODE (x))
8832 && ! FLOAT_MODE_P (GET_MODE (val)))
8835 if (cond == UNEQ && rtx_equal_p (x, reg))
8838 /* If X is (abs REG) and we know something about REG's relationship
8839 with zero, we may be able to simplify this. */
8841 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
8844 case GE: case GT: case EQ:
8847 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
8849 GET_MODE (XEXP (x, 0)));
8854 /* The only other cases we handle are MIN, MAX, and comparisons if the
8855 operands are the same as REG and VAL. */
8857 else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
8859 if (rtx_equal_p (XEXP (x, 0), val))
8860 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
8862 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
8864 if (COMPARISON_P (x))
8866 if (comparison_dominates_p (cond, code))
8867 return const_true_rtx;
8869 code = reversed_comparison_code (x, NULL);
8871 && comparison_dominates_p (cond, code))
8876 else if (code == SMAX || code == SMIN
8877 || code == UMIN || code == UMAX)
8879 int unsignedp = (code == UMIN || code == UMAX);
8881 /* Do not reverse the condition when it is NE or EQ.
8882 This is because we cannot conclude anything about
8883 the value of 'SMAX (x, y)' when x is not equal to y,
8884 but we can when x equals y. */
8885 if ((code == SMAX || code == UMAX)
8886 && ! (cond == EQ || cond == NE))
8887 cond = reverse_condition (cond);
8892 return unsignedp ? x : XEXP (x, 1);
8894 return unsignedp ? x : XEXP (x, 0);
8896 return unsignedp ? XEXP (x, 1) : x;
8898 return unsignedp ? XEXP (x, 0) : x;
8905 else if (code == SUBREG)
8907 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
8908 rtx new_rtx, r = known_cond (SUBREG_REG (x), cond, reg, val);
8910 if (SUBREG_REG (x) != r)
8912 /* We must simplify subreg here, before we lose track of the
8913 original inner_mode. */
8914 new_rtx = simplify_subreg (GET_MODE (x), r,
8915 inner_mode, SUBREG_BYTE (x));
8919 SUBST (SUBREG_REG (x), r);
8924 /* We don't have to handle SIGN_EXTEND here, because even in the
8925 case of replacing something with a modeless CONST_INT, a
8926 CONST_INT is already (supposed to be) a valid sign extension for
8927 its narrower mode, which implies it's already properly
8928 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
8929 story is different. */
8930 else if (code == ZERO_EXTEND)
8932 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
8933 rtx new_rtx, r = known_cond (XEXP (x, 0), cond, reg, val);
8935 if (XEXP (x, 0) != r)
8937 /* We must simplify the zero_extend here, before we lose
8938 track of the original inner_mode. */
8939 new_rtx = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
8944 SUBST (XEXP (x, 0), r);
8950 fmt = GET_RTX_FORMAT (code);
8951 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8954 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
8955 else if (fmt[i] == 'E')
8956 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8957 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
8964 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8965 assignment as a field assignment. */
8968 rtx_equal_for_field_assignment_p (rtx x, rtx y)
8970 if (x == y || rtx_equal_p (x, y))
8973 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
8976 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8977 Note that all SUBREGs of MEM are paradoxical; otherwise they
8978 would have been rewritten. */
8979 if (MEM_P (x) && GET_CODE (y) == SUBREG
8980 && MEM_P (SUBREG_REG (y))
8981 && rtx_equal_p (SUBREG_REG (y),
8982 gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
8985 if (MEM_P (y) && GET_CODE (x) == SUBREG
8986 && MEM_P (SUBREG_REG (x))
8987 && rtx_equal_p (SUBREG_REG (x),
8988 gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
8991 /* We used to see if get_last_value of X and Y were the same but that's
8992 not correct. In one direction, we'll cause the assignment to have
8993 the wrong destination and in the case, we'll import a register into this
8994 insn that might have already have been dead. So fail if none of the
8995 above cases are true. */
8999 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9000 Return that assignment if so.
9002 We only handle the most common cases. */
9005 make_field_assignment (rtx x)
9007 rtx dest = SET_DEST (x);
9008 rtx src = SET_SRC (x);
9013 unsigned HOST_WIDE_INT len;
9015 enum machine_mode mode;
9017 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9018 a clear of a one-bit field. We will have changed it to
9019 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9022 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
9023 && CONST_INT_P (XEXP (XEXP (src, 0), 0))
9024 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
9025 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9027 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
9030 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
9034 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
9035 && subreg_lowpart_p (XEXP (src, 0))
9036 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
9037 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
9038 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
9039 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src, 0)), 0))
9040 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
9041 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9043 assign = make_extraction (VOIDmode, dest, 0,
9044 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
9047 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
9051 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9053 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
9054 && XEXP (XEXP (src, 0), 0) == const1_rtx
9055 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9057 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
9060 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
9064 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9065 SRC is an AND with all bits of that field set, then we can discard
9067 if (GET_CODE (dest) == ZERO_EXTRACT
9068 && CONST_INT_P (XEXP (dest, 1))
9069 && GET_CODE (src) == AND
9070 && CONST_INT_P (XEXP (src, 1)))
9072 HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
9073 unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
9074 unsigned HOST_WIDE_INT ze_mask;
9076 if (width >= HOST_BITS_PER_WIDE_INT)
9079 ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
9081 /* Complete overlap. We can remove the source AND. */
9082 if ((and_mask & ze_mask) == ze_mask)
9083 return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
9085 /* Partial overlap. We can reduce the source AND. */
9086 if ((and_mask & ze_mask) != and_mask)
9088 mode = GET_MODE (src);
9089 src = gen_rtx_AND (mode, XEXP (src, 0),
9090 gen_int_mode (and_mask & ze_mask, mode));
9091 return gen_rtx_SET (VOIDmode, dest, src);
9095 /* The other case we handle is assignments into a constant-position
9096 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9097 a mask that has all one bits except for a group of zero bits and
9098 OTHER is known to have zeros where C1 has ones, this is such an
9099 assignment. Compute the position and length from C1. Shift OTHER
9100 to the appropriate position, force it to the required mode, and
9101 make the extraction. Check for the AND in both operands. */
9103 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
9106 rhs = expand_compound_operation (XEXP (src, 0));
9107 lhs = expand_compound_operation (XEXP (src, 1));
9109 if (GET_CODE (rhs) == AND
9110 && CONST_INT_P (XEXP (rhs, 1))
9111 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
9112 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
9113 else if (GET_CODE (lhs) == AND
9114 && CONST_INT_P (XEXP (lhs, 1))
9115 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
9116 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
9120 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
9121 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
9122 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
9123 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
9126 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
9130 /* The mode to use for the source is the mode of the assignment, or of
9131 what is inside a possible STRICT_LOW_PART. */
9132 mode = (GET_CODE (assign) == STRICT_LOW_PART
9133 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
9135 /* Shift OTHER right POS places and make it the source, restricting it
9136 to the proper length and mode. */
9138 src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
9142 src = force_to_mode (src, mode,
9143 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
9144 ? ~(unsigned HOST_WIDE_INT) 0
9145 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
9148 /* If SRC is masked by an AND that does not make a difference in
9149 the value being stored, strip it. */
9150 if (GET_CODE (assign) == ZERO_EXTRACT
9151 && CONST_INT_P (XEXP (assign, 1))
9152 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
9153 && GET_CODE (src) == AND
9154 && CONST_INT_P (XEXP (src, 1))
9155 && UINTVAL (XEXP (src, 1))
9156 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1)
9157 src = XEXP (src, 0);
9159 return gen_rtx_SET (VOIDmode, assign, src);
9162 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9166 apply_distributive_law (rtx x)
9168 enum rtx_code code = GET_CODE (x);
9169 enum rtx_code inner_code;
9170 rtx lhs, rhs, other;
9173 /* Distributivity is not true for floating point as it can change the
9174 value. So we don't do it unless -funsafe-math-optimizations. */
9175 if (FLOAT_MODE_P (GET_MODE (x))
9176 && ! flag_unsafe_math_optimizations)
9179 /* The outer operation can only be one of the following: */
9180 if (code != IOR && code != AND && code != XOR
9181 && code != PLUS && code != MINUS)
9187 /* If either operand is a primitive we can't do anything, so get out
9189 if (OBJECT_P (lhs) || OBJECT_P (rhs))
9192 lhs = expand_compound_operation (lhs);
9193 rhs = expand_compound_operation (rhs);
9194 inner_code = GET_CODE (lhs);
9195 if (inner_code != GET_CODE (rhs))
9198 /* See if the inner and outer operations distribute. */
9205 /* These all distribute except over PLUS. */
9206 if (code == PLUS || code == MINUS)
9211 if (code != PLUS && code != MINUS)
9216 /* This is also a multiply, so it distributes over everything. */
9220 /* Non-paradoxical SUBREGs distributes over all operations,
9221 provided the inner modes and byte offsets are the same, this
9222 is an extraction of a low-order part, we don't convert an fp
9223 operation to int or vice versa, this is not a vector mode,
9224 and we would not be converting a single-word operation into a
9225 multi-word operation. The latter test is not required, but
9226 it prevents generating unneeded multi-word operations. Some
9227 of the previous tests are redundant given the latter test,
9228 but are retained because they are required for correctness.
9230 We produce the result slightly differently in this case. */
9232 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
9233 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
9234 || ! subreg_lowpart_p (lhs)
9235 || (GET_MODE_CLASS (GET_MODE (lhs))
9236 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
9237 || (GET_MODE_SIZE (GET_MODE (lhs))
9238 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
9239 || VECTOR_MODE_P (GET_MODE (lhs))
9240 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD
9241 /* Result might need to be truncated. Don't change mode if
9242 explicit truncation is needed. */
9243 || !TRULY_NOOP_TRUNCATION
9244 (GET_MODE_BITSIZE (GET_MODE (x)),
9245 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (lhs)))))
9248 tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
9249 SUBREG_REG (lhs), SUBREG_REG (rhs));
9250 return gen_lowpart (GET_MODE (x), tem);
9256 /* Set LHS and RHS to the inner operands (A and B in the example
9257 above) and set OTHER to the common operand (C in the example).
9258 There is only one way to do this unless the inner operation is
9260 if (COMMUTATIVE_ARITH_P (lhs)
9261 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
9262 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
9263 else if (COMMUTATIVE_ARITH_P (lhs)
9264 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
9265 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
9266 else if (COMMUTATIVE_ARITH_P (lhs)
9267 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
9268 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
9269 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
9270 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
9274 /* Form the new inner operation, seeing if it simplifies first. */
9275 tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
9277 /* There is one exception to the general way of distributing:
9278 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9279 if (code == XOR && inner_code == IOR)
9282 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
9285 /* We may be able to continuing distributing the result, so call
9286 ourselves recursively on the inner operation before forming the
9287 outer operation, which we return. */
9288 return simplify_gen_binary (inner_code, GET_MODE (x),
9289 apply_distributive_law (tem), other);
9292 /* See if X is of the form (* (+ A B) C), and if so convert to
9293 (+ (* A C) (* B C)) and try to simplify.
9295 Most of the time, this results in no change. However, if some of
9296 the operands are the same or inverses of each other, simplifications
9299 For example, (and (ior A B) (not B)) can occur as the result of
9300 expanding a bit field assignment. When we apply the distributive
9301 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9302 which then simplifies to (and (A (not B))).
9304 Note that no checks happen on the validity of applying the inverse
9305 distributive law. This is pointless since we can do it in the
9306 few places where this routine is called.
9308 N is the index of the term that is decomposed (the arithmetic operation,
9309 i.e. (+ A B) in the first example above). !N is the index of the term that
9310 is distributed, i.e. of C in the first example above. */
9312 distribute_and_simplify_rtx (rtx x, int n)
9314 enum machine_mode mode;
9315 enum rtx_code outer_code, inner_code;
9316 rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
9318 /* Distributivity is not true for floating point as it can change the
9319 value. So we don't do it unless -funsafe-math-optimizations. */
9320 if (FLOAT_MODE_P (GET_MODE (x))
9321 && ! flag_unsafe_math_optimizations)
9324 decomposed = XEXP (x, n);
9325 if (!ARITHMETIC_P (decomposed))
9328 mode = GET_MODE (x);
9329 outer_code = GET_CODE (x);
9330 distributed = XEXP (x, !n);
9332 inner_code = GET_CODE (decomposed);
9333 inner_op0 = XEXP (decomposed, 0);
9334 inner_op1 = XEXP (decomposed, 1);
9336 /* Special case (and (xor B C) (not A)), which is equivalent to
9337 (xor (ior A B) (ior A C)) */
9338 if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
9340 distributed = XEXP (distributed, 0);
9346 /* Distribute the second term. */
9347 new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
9348 new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
9352 /* Distribute the first term. */
9353 new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
9354 new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
9357 tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
9359 if (GET_CODE (tmp) != outer_code
9360 && rtx_cost (tmp, SET, optimize_this_for_speed_p)
9361 < rtx_cost (x, SET, optimize_this_for_speed_p))
9367 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9368 in MODE. Return an equivalent form, if different from (and VAROP
9369 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9372 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
9373 unsigned HOST_WIDE_INT constop)
9375 unsigned HOST_WIDE_INT nonzero;
9376 unsigned HOST_WIDE_INT orig_constop;
9381 orig_constop = constop;
9382 if (GET_CODE (varop) == CLOBBER)
9385 /* Simplify VAROP knowing that we will be only looking at some of the
9388 Note by passing in CONSTOP, we guarantee that the bits not set in
9389 CONSTOP are not significant and will never be examined. We must
9390 ensure that is the case by explicitly masking out those bits
9391 before returning. */
9392 varop = force_to_mode (varop, mode, constop, 0);
9394 /* If VAROP is a CLOBBER, we will fail so return it. */
9395 if (GET_CODE (varop) == CLOBBER)
9398 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9399 to VAROP and return the new constant. */
9400 if (CONST_INT_P (varop))
9401 return gen_int_mode (INTVAL (varop) & constop, mode);
9403 /* See what bits may be nonzero in VAROP. Unlike the general case of
9404 a call to nonzero_bits, here we don't care about bits outside
9407 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
9409 /* Turn off all bits in the constant that are known to already be zero.
9410 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9411 which is tested below. */
9415 /* If we don't have any bits left, return zero. */
9419 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9420 a power of two, we can replace this with an ASHIFT. */
9421 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
9422 && (i = exact_log2 (constop)) >= 0)
9423 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
9425 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9426 or XOR, then try to apply the distributive law. This may eliminate
9427 operations if either branch can be simplified because of the AND.
9428 It may also make some cases more complex, but those cases probably
9429 won't match a pattern either with or without this. */
9431 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
9435 apply_distributive_law
9436 (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
9437 simplify_and_const_int (NULL_RTX,
9441 simplify_and_const_int (NULL_RTX,
9446 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9447 the AND and see if one of the operands simplifies to zero. If so, we
9448 may eliminate it. */
9450 if (GET_CODE (varop) == PLUS
9451 && exact_log2 (constop + 1) >= 0)
9455 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
9456 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
9457 if (o0 == const0_rtx)
9459 if (o1 == const0_rtx)
9463 /* Make a SUBREG if necessary. If we can't make it, fail. */
9464 varop = gen_lowpart (mode, varop);
9465 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
9468 /* If we are only masking insignificant bits, return VAROP. */
9469 if (constop == nonzero)
9472 if (varop == orig_varop && constop == orig_constop)
9475 /* Otherwise, return an AND. */
9476 return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
9480 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9483 Return an equivalent form, if different from X. Otherwise, return X. If
9484 X is zero, we are to always construct the equivalent form. */
9487 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
9488 unsigned HOST_WIDE_INT constop)
9490 rtx tem = simplify_and_const_int_1 (mode, varop, constop);
9495 x = simplify_gen_binary (AND, GET_MODE (varop), varop,
9496 gen_int_mode (constop, mode));
9497 if (GET_MODE (x) != mode)
9498 x = gen_lowpart (mode, x);
9502 /* Given a REG, X, compute which bits in X can be nonzero.
9503 We don't care about bits outside of those defined in MODE.
9505 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9506 a shift, AND, or zero_extract, we can do better. */
9509 reg_nonzero_bits_for_combine (const_rtx x, enum machine_mode mode,
9510 const_rtx known_x ATTRIBUTE_UNUSED,
9511 enum machine_mode known_mode ATTRIBUTE_UNUSED,
9512 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
9513 unsigned HOST_WIDE_INT *nonzero)
9518 /* If X is a register whose nonzero bits value is current, use it.
9519 Otherwise, if X is a register whose value we can find, use that
9520 value. Otherwise, use the previously-computed global nonzero bits
9521 for this register. */
9523 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
9524 if (rsp->last_set_value != 0
9525 && (rsp->last_set_mode == mode
9526 || (GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT
9527 && GET_MODE_CLASS (mode) == MODE_INT))
9528 && ((rsp->last_set_label >= label_tick_ebb_start
9529 && rsp->last_set_label < label_tick)
9530 || (rsp->last_set_label == label_tick
9531 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9532 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9533 && REG_N_SETS (REGNO (x)) == 1
9535 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9537 *nonzero &= rsp->last_set_nonzero_bits;
9541 tem = get_last_value (x);
9545 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9546 /* If X is narrower than MODE and TEM is a non-negative
9547 constant that would appear negative in the mode of X,
9548 sign-extend it for use in reg_nonzero_bits because some
9549 machines (maybe most) will actually do the sign-extension
9550 and this is the conservative approach.
9552 ??? For 2.5, try to tighten up the MD files in this regard
9553 instead of this kludge. */
9555 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)
9556 && CONST_INT_P (tem)
9558 && 0 != (UINTVAL (tem)
9559 & ((unsigned HOST_WIDE_INT) 1
9560 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
9561 tem = GEN_INT (UINTVAL (tem)
9562 | ((unsigned HOST_WIDE_INT) (-1)
9563 << GET_MODE_BITSIZE (GET_MODE (x))));
9567 else if (nonzero_sign_valid && rsp->nonzero_bits)
9569 unsigned HOST_WIDE_INT mask = rsp->nonzero_bits;
9571 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode))
9572 /* We don't know anything about the upper bits. */
9573 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
9580 /* Return the number of bits at the high-order end of X that are known to
9581 be equal to the sign bit. X will be used in mode MODE; if MODE is
9582 VOIDmode, X will be used in its own mode. The returned value will always
9583 be between 1 and the number of bits in MODE. */
9586 reg_num_sign_bit_copies_for_combine (const_rtx x, enum machine_mode mode,
9587 const_rtx known_x ATTRIBUTE_UNUSED,
9588 enum machine_mode known_mode
9590 unsigned int known_ret ATTRIBUTE_UNUSED,
9591 unsigned int *result)
9596 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
9597 if (rsp->last_set_value != 0
9598 && rsp->last_set_mode == mode
9599 && ((rsp->last_set_label >= label_tick_ebb_start
9600 && rsp->last_set_label < label_tick)
9601 || (rsp->last_set_label == label_tick
9602 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9603 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9604 && REG_N_SETS (REGNO (x)) == 1
9606 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9608 *result = rsp->last_set_sign_bit_copies;
9612 tem = get_last_value (x);
9616 if (nonzero_sign_valid && rsp->sign_bit_copies != 0
9617 && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode))
9618 *result = rsp->sign_bit_copies;
9623 /* Return the number of "extended" bits there are in X, when interpreted
9624 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9625 unsigned quantities, this is the number of high-order zero bits.
9626 For signed quantities, this is the number of copies of the sign bit
9627 minus 1. In both case, this function returns the number of "spare"
9628 bits. For example, if two quantities for which this function returns
9629 at least 1 are added, the addition is known not to overflow.
9631 This function will always return 0 unless called during combine, which
9632 implies that it must be called from a define_split. */
9635 extended_count (const_rtx x, enum machine_mode mode, int unsignedp)
9637 if (nonzero_sign_valid == 0)
9641 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9642 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
9643 - floor_log2 (nonzero_bits (x, mode)))
9645 : num_sign_bit_copies (x, mode) - 1);
9648 /* This function is called from `simplify_shift_const' to merge two
9649 outer operations. Specifically, we have already found that we need
9650 to perform operation *POP0 with constant *PCONST0 at the outermost
9651 position. We would now like to also perform OP1 with constant CONST1
9652 (with *POP0 being done last).
9654 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9655 the resulting operation. *PCOMP_P is set to 1 if we would need to
9656 complement the innermost operand, otherwise it is unchanged.
9658 MODE is the mode in which the operation will be done. No bits outside
9659 the width of this mode matter. It is assumed that the width of this mode
9660 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9662 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9663 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9664 result is simply *PCONST0.
9666 If the resulting operation cannot be expressed as one operation, we
9667 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9670 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
9672 enum rtx_code op0 = *pop0;
9673 HOST_WIDE_INT const0 = *pconst0;
9675 const0 &= GET_MODE_MASK (mode);
9676 const1 &= GET_MODE_MASK (mode);
9678 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9682 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9685 if (op1 == UNKNOWN || op0 == SET)
9688 else if (op0 == UNKNOWN)
9689 op0 = op1, const0 = const1;
9691 else if (op0 == op1)
9715 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9716 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
9719 /* If the two constants aren't the same, we can't do anything. The
9720 remaining six cases can all be done. */
9721 else if (const0 != const1)
9729 /* (a & b) | b == b */
9731 else /* op1 == XOR */
9732 /* (a ^ b) | b == a | b */
9738 /* (a & b) ^ b == (~a) & b */
9739 op0 = AND, *pcomp_p = 1;
9740 else /* op1 == IOR */
9741 /* (a | b) ^ b == a & ~b */
9742 op0 = AND, const0 = ~const0;
9747 /* (a | b) & b == b */
9749 else /* op1 == XOR */
9750 /* (a ^ b) & b) == (~a) & b */
9757 /* Check for NO-OP cases. */
9758 const0 &= GET_MODE_MASK (mode);
9760 && (op0 == IOR || op0 == XOR || op0 == PLUS))
9762 else if (const0 == 0 && op0 == AND)
9764 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
9770 /* ??? Slightly redundant with the above mask, but not entirely.
9771 Moving this above means we'd have to sign-extend the mode mask
9772 for the final test. */
9773 if (op0 != UNKNOWN && op0 != NEG)
9774 *pconst0 = trunc_int_for_mode (const0, mode);
9779 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9780 the shift in. The original shift operation CODE is performed on OP in
9781 ORIG_MODE. Return the wider mode MODE if we can perform the operation
9782 in that mode. Return ORIG_MODE otherwise. We can also assume that the
9783 result of the shift is subject to operation OUTER_CODE with operand
9786 static enum machine_mode
9787 try_widen_shift_mode (enum rtx_code code, rtx op, int count,
9788 enum machine_mode orig_mode, enum machine_mode mode,
9789 enum rtx_code outer_code, HOST_WIDE_INT outer_const)
9791 if (orig_mode == mode)
9793 gcc_assert (GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (orig_mode));
9795 /* In general we can't perform in wider mode for right shift and rotate. */
9799 /* We can still widen if the bits brought in from the left are identical
9800 to the sign bit of ORIG_MODE. */
9801 if (num_sign_bit_copies (op, mode)
9802 > (unsigned) (GET_MODE_BITSIZE (mode)
9803 - GET_MODE_BITSIZE (orig_mode)))
9808 /* Similarly here but with zero bits. */
9809 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9810 && (nonzero_bits (op, mode) & ~GET_MODE_MASK (orig_mode)) == 0)
9813 /* We can also widen if the bits brought in will be masked off. This
9814 operation is performed in ORIG_MODE. */
9815 if (outer_code == AND)
9817 int care_bits = low_bitmask_len (orig_mode, outer_const);
9820 && GET_MODE_BITSIZE (orig_mode) - care_bits >= count)
9836 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9837 The result of the shift is RESULT_MODE. Return NULL_RTX if we cannot
9838 simplify it. Otherwise, return a simplified value.
9840 The shift is normally computed in the widest mode we find in VAROP, as
9841 long as it isn't a different number of words than RESULT_MODE. Exceptions
9842 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9845 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
9846 rtx varop, int orig_count)
9848 enum rtx_code orig_code = code;
9849 rtx orig_varop = varop;
9851 enum machine_mode mode = result_mode;
9852 enum machine_mode shift_mode, tmode;
9853 unsigned int mode_words
9854 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
9855 /* We form (outer_op (code varop count) (outer_const)). */
9856 enum rtx_code outer_op = UNKNOWN;
9857 HOST_WIDE_INT outer_const = 0;
9858 int complement_p = 0;
9861 /* Make sure and truncate the "natural" shift on the way in. We don't
9862 want to do this inside the loop as it makes it more difficult to
9864 if (SHIFT_COUNT_TRUNCATED)
9865 orig_count &= GET_MODE_BITSIZE (mode) - 1;
9867 /* If we were given an invalid count, don't do anything except exactly
9868 what was requested. */
9870 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
9875 /* Unless one of the branches of the `if' in this loop does a `continue',
9876 we will `break' the loop after the `if'. */
9880 /* If we have an operand of (clobber (const_int 0)), fail. */
9881 if (GET_CODE (varop) == CLOBBER)
9884 /* Convert ROTATERT to ROTATE. */
9885 if (code == ROTATERT)
9887 unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
9889 if (VECTOR_MODE_P (result_mode))
9890 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
9892 count = bitsize - count;
9895 shift_mode = try_widen_shift_mode (code, varop, count, result_mode,
9896 mode, outer_op, outer_const);
9898 /* Handle cases where the count is greater than the size of the mode
9899 minus 1. For ASHIFT, use the size minus one as the count (this can
9900 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9901 take the count modulo the size. For other shifts, the result is
9904 Since these shifts are being produced by the compiler by combining
9905 multiple operations, each of which are defined, we know what the
9906 result is supposed to be. */
9908 if (count > (GET_MODE_BITSIZE (shift_mode) - 1))
9910 if (code == ASHIFTRT)
9911 count = GET_MODE_BITSIZE (shift_mode) - 1;
9912 else if (code == ROTATE || code == ROTATERT)
9913 count %= GET_MODE_BITSIZE (shift_mode);
9916 /* We can't simply return zero because there may be an
9924 /* If we discovered we had to complement VAROP, leave. Making a NOT
9925 here would cause an infinite loop. */
9929 /* An arithmetic right shift of a quantity known to be -1 or 0
9931 if (code == ASHIFTRT
9932 && (num_sign_bit_copies (varop, shift_mode)
9933 == GET_MODE_BITSIZE (shift_mode)))
9939 /* If we are doing an arithmetic right shift and discarding all but
9940 the sign bit copies, this is equivalent to doing a shift by the
9941 bitsize minus one. Convert it into that shift because it will often
9942 allow other simplifications. */
9944 if (code == ASHIFTRT
9945 && (count + num_sign_bit_copies (varop, shift_mode)
9946 >= GET_MODE_BITSIZE (shift_mode)))
9947 count = GET_MODE_BITSIZE (shift_mode) - 1;
9949 /* We simplify the tests below and elsewhere by converting
9950 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9951 `make_compound_operation' will convert it to an ASHIFTRT for
9952 those machines (such as VAX) that don't have an LSHIFTRT. */
9953 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9955 && ((nonzero_bits (varop, shift_mode)
9956 & ((unsigned HOST_WIDE_INT) 1
9957 << (GET_MODE_BITSIZE (shift_mode) - 1))) == 0))
9960 if (((code == LSHIFTRT
9961 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9962 && !(nonzero_bits (varop, shift_mode) >> count))
9964 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9965 && !((nonzero_bits (varop, shift_mode) << count)
9966 & GET_MODE_MASK (shift_mode))))
9967 && !side_effects_p (varop))
9970 switch (GET_CODE (varop))
9976 new_rtx = expand_compound_operation (varop);
9977 if (new_rtx != varop)
9985 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9986 minus the width of a smaller mode, we can do this with a
9987 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9988 if ((code == ASHIFTRT || code == LSHIFTRT)
9989 && ! mode_dependent_address_p (XEXP (varop, 0))
9990 && ! MEM_VOLATILE_P (varop)
9991 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9992 MODE_INT, 1)) != BLKmode)
9994 new_rtx = adjust_address_nv (varop, tmode,
9995 BYTES_BIG_ENDIAN ? 0
9996 : count / BITS_PER_UNIT);
9998 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9999 : ZERO_EXTEND, mode, new_rtx);
10006 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10007 the same number of words as what we've seen so far. Then store
10008 the widest mode in MODE. */
10009 if (subreg_lowpart_p (varop)
10010 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
10011 > GET_MODE_SIZE (GET_MODE (varop)))
10012 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
10013 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
10015 && GET_MODE_CLASS (GET_MODE (varop)) == MODE_INT
10016 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (varop))) == MODE_INT)
10018 varop = SUBREG_REG (varop);
10019 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
10020 mode = GET_MODE (varop);
10026 /* Some machines use MULT instead of ASHIFT because MULT
10027 is cheaper. But it is still better on those machines to
10028 merge two shifts into one. */
10029 if (CONST_INT_P (XEXP (varop, 1))
10030 && exact_log2 (UINTVAL (XEXP (varop, 1))) >= 0)
10033 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
10035 GEN_INT (exact_log2 (
10036 UINTVAL (XEXP (varop, 1)))));
10042 /* Similar, for when divides are cheaper. */
10043 if (CONST_INT_P (XEXP (varop, 1))
10044 && exact_log2 (UINTVAL (XEXP (varop, 1))) >= 0)
10047 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
10049 GEN_INT (exact_log2 (
10050 UINTVAL (XEXP (varop, 1)))));
10056 /* If we are extracting just the sign bit of an arithmetic
10057 right shift, that shift is not needed. However, the sign
10058 bit of a wider mode may be different from what would be
10059 interpreted as the sign bit in a narrower mode, so, if
10060 the result is narrower, don't discard the shift. */
10061 if (code == LSHIFTRT
10062 && count == (GET_MODE_BITSIZE (result_mode) - 1)
10063 && (GET_MODE_BITSIZE (result_mode)
10064 >= GET_MODE_BITSIZE (GET_MODE (varop))))
10066 varop = XEXP (varop, 0);
10070 /* ... fall through ... */
10075 /* Here we have two nested shifts. The result is usually the
10076 AND of a new shift with a mask. We compute the result below. */
10077 if (CONST_INT_P (XEXP (varop, 1))
10078 && INTVAL (XEXP (varop, 1)) >= 0
10079 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
10080 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
10081 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
10082 && !VECTOR_MODE_P (result_mode))
10084 enum rtx_code first_code = GET_CODE (varop);
10085 unsigned int first_count = INTVAL (XEXP (varop, 1));
10086 unsigned HOST_WIDE_INT mask;
10089 /* We have one common special case. We can't do any merging if
10090 the inner code is an ASHIFTRT of a smaller mode. However, if
10091 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10092 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10093 we can convert it to
10094 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
10095 This simplifies certain SIGN_EXTEND operations. */
10096 if (code == ASHIFT && first_code == ASHIFTRT
10097 && count == (GET_MODE_BITSIZE (result_mode)
10098 - GET_MODE_BITSIZE (GET_MODE (varop))))
10100 /* C3 has the low-order C1 bits zero. */
10102 mask = GET_MODE_MASK (mode)
10103 & ~(((unsigned HOST_WIDE_INT) 1 << first_count) - 1);
10105 varop = simplify_and_const_int (NULL_RTX, result_mode,
10106 XEXP (varop, 0), mask);
10107 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
10109 count = first_count;
10114 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10115 than C1 high-order bits equal to the sign bit, we can convert
10116 this to either an ASHIFT or an ASHIFTRT depending on the
10119 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10121 if (code == ASHIFTRT && first_code == ASHIFT
10122 && GET_MODE (varop) == shift_mode
10123 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
10126 varop = XEXP (varop, 0);
10127 count -= first_count;
10137 /* There are some cases we can't do. If CODE is ASHIFTRT,
10138 we can only do this if FIRST_CODE is also ASHIFTRT.
10140 We can't do the case when CODE is ROTATE and FIRST_CODE is
10143 If the mode of this shift is not the mode of the outer shift,
10144 we can't do this if either shift is a right shift or ROTATE.
10146 Finally, we can't do any of these if the mode is too wide
10147 unless the codes are the same.
10149 Handle the case where the shift codes are the same
10152 if (code == first_code)
10154 if (GET_MODE (varop) != result_mode
10155 && (code == ASHIFTRT || code == LSHIFTRT
10156 || code == ROTATE))
10159 count += first_count;
10160 varop = XEXP (varop, 0);
10164 if (code == ASHIFTRT
10165 || (code == ROTATE && first_code == ASHIFTRT)
10166 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
10167 || (GET_MODE (varop) != result_mode
10168 && (first_code == ASHIFTRT || first_code == LSHIFTRT
10169 || first_code == ROTATE
10170 || code == ROTATE)))
10173 /* To compute the mask to apply after the shift, shift the
10174 nonzero bits of the inner shift the same way the
10175 outer shift will. */
10177 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
10180 = simplify_const_binary_operation (code, result_mode, mask_rtx,
10183 /* Give up if we can't compute an outer operation to use. */
10185 || !CONST_INT_P (mask_rtx)
10186 || ! merge_outer_ops (&outer_op, &outer_const, AND,
10188 result_mode, &complement_p))
10191 /* If the shifts are in the same direction, we add the
10192 counts. Otherwise, we subtract them. */
10193 if ((code == ASHIFTRT || code == LSHIFTRT)
10194 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
10195 count += first_count;
10197 count -= first_count;
10199 /* If COUNT is positive, the new shift is usually CODE,
10200 except for the two exceptions below, in which case it is
10201 FIRST_CODE. If the count is negative, FIRST_CODE should
10204 && ((first_code == ROTATE && code == ASHIFT)
10205 || (first_code == ASHIFTRT && code == LSHIFTRT)))
10207 else if (count < 0)
10208 code = first_code, count = -count;
10210 varop = XEXP (varop, 0);
10214 /* If we have (A << B << C) for any shift, we can convert this to
10215 (A << C << B). This wins if A is a constant. Only try this if
10216 B is not a constant. */
10218 else if (GET_CODE (varop) == code
10219 && CONST_INT_P (XEXP (varop, 0))
10220 && !CONST_INT_P (XEXP (varop, 1)))
10222 rtx new_rtx = simplify_const_binary_operation (code, mode,
10225 varop = gen_rtx_fmt_ee (code, mode, new_rtx, XEXP (varop, 1));
10232 if (VECTOR_MODE_P (mode))
10235 /* Make this fit the case below. */
10236 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
10237 GEN_INT (GET_MODE_MASK (mode)));
10243 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10244 with C the size of VAROP - 1 and the shift is logical if
10245 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10246 we have an (le X 0) operation. If we have an arithmetic shift
10247 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10248 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10250 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
10251 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
10252 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
10253 && (code == LSHIFTRT || code == ASHIFTRT)
10254 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
10255 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
10258 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
10261 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
10262 varop = gen_rtx_NEG (GET_MODE (varop), varop);
10267 /* If we have (shift (logical)), move the logical to the outside
10268 to allow it to possibly combine with another logical and the
10269 shift to combine with another shift. This also canonicalizes to
10270 what a ZERO_EXTRACT looks like. Also, some machines have
10271 (and (shift)) insns. */
10273 if (CONST_INT_P (XEXP (varop, 1))
10274 /* We can't do this if we have (ashiftrt (xor)) and the
10275 constant has its sign bit set in shift_mode. */
10276 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
10277 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
10279 && (new_rtx = simplify_const_binary_operation (code, result_mode,
10281 GEN_INT (count))) != 0
10282 && CONST_INT_P (new_rtx)
10283 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
10284 INTVAL (new_rtx), result_mode, &complement_p))
10286 varop = XEXP (varop, 0);
10290 /* If we can't do that, try to simplify the shift in each arm of the
10291 logical expression, make a new logical expression, and apply
10292 the inverse distributive law. This also can't be done
10293 for some (ashiftrt (xor)). */
10294 if (CONST_INT_P (XEXP (varop, 1))
10295 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
10296 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
10299 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
10300 XEXP (varop, 0), count);
10301 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
10302 XEXP (varop, 1), count);
10304 varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
10306 varop = apply_distributive_law (varop);
10314 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10315 says that the sign bit can be tested, FOO has mode MODE, C is
10316 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
10317 that may be nonzero. */
10318 if (code == LSHIFTRT
10319 && XEXP (varop, 1) == const0_rtx
10320 && GET_MODE (XEXP (varop, 0)) == result_mode
10321 && count == (GET_MODE_BITSIZE (result_mode) - 1)
10322 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
10323 && STORE_FLAG_VALUE == -1
10324 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
10325 && merge_outer_ops (&outer_op, &outer_const, XOR, 1, result_mode,
10328 varop = XEXP (varop, 0);
10335 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10336 than the number of bits in the mode is equivalent to A. */
10337 if (code == LSHIFTRT
10338 && count == (GET_MODE_BITSIZE (result_mode) - 1)
10339 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
10341 varop = XEXP (varop, 0);
10346 /* NEG commutes with ASHIFT since it is multiplication. Move the
10347 NEG outside to allow shifts to combine. */
10349 && merge_outer_ops (&outer_op, &outer_const, NEG, 0, result_mode,
10352 varop = XEXP (varop, 0);
10358 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10359 is one less than the number of bits in the mode is
10360 equivalent to (xor A 1). */
10361 if (code == LSHIFTRT
10362 && count == (GET_MODE_BITSIZE (result_mode) - 1)
10363 && XEXP (varop, 1) == constm1_rtx
10364 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
10365 && merge_outer_ops (&outer_op, &outer_const, XOR, 1, result_mode,
10369 varop = XEXP (varop, 0);
10373 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10374 that might be nonzero in BAR are those being shifted out and those
10375 bits are known zero in FOO, we can replace the PLUS with FOO.
10376 Similarly in the other operand order. This code occurs when
10377 we are computing the size of a variable-size array. */
10379 if ((code == ASHIFTRT || code == LSHIFTRT)
10380 && count < HOST_BITS_PER_WIDE_INT
10381 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
10382 && (nonzero_bits (XEXP (varop, 1), result_mode)
10383 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
10385 varop = XEXP (varop, 0);
10388 else if ((code == ASHIFTRT || code == LSHIFTRT)
10389 && count < HOST_BITS_PER_WIDE_INT
10390 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
10391 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
10393 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
10394 & nonzero_bits (XEXP (varop, 1),
10397 varop = XEXP (varop, 1);
10401 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10403 && CONST_INT_P (XEXP (varop, 1))
10404 && (new_rtx = simplify_const_binary_operation (ASHIFT, result_mode,
10406 GEN_INT (count))) != 0
10407 && CONST_INT_P (new_rtx)
10408 && merge_outer_ops (&outer_op, &outer_const, PLUS,
10409 INTVAL (new_rtx), result_mode, &complement_p))
10411 varop = XEXP (varop, 0);
10415 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10416 signbit', and attempt to change the PLUS to an XOR and move it to
10417 the outer operation as is done above in the AND/IOR/XOR case
10418 leg for shift(logical). See details in logical handling above
10419 for reasoning in doing so. */
10420 if (code == LSHIFTRT
10421 && CONST_INT_P (XEXP (varop, 1))
10422 && mode_signbit_p (result_mode, XEXP (varop, 1))
10423 && (new_rtx = simplify_const_binary_operation (code, result_mode,
10425 GEN_INT (count))) != 0
10426 && CONST_INT_P (new_rtx)
10427 && merge_outer_ops (&outer_op, &outer_const, XOR,
10428 INTVAL (new_rtx), result_mode, &complement_p))
10430 varop = XEXP (varop, 0);
10437 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10438 with C the size of VAROP - 1 and the shift is logical if
10439 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10440 we have a (gt X 0) operation. If the shift is arithmetic with
10441 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10442 we have a (neg (gt X 0)) operation. */
10444 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
10445 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
10446 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
10447 && (code == LSHIFTRT || code == ASHIFTRT)
10448 && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
10449 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
10450 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
10453 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
10456 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
10457 varop = gen_rtx_NEG (GET_MODE (varop), varop);
10464 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10465 if the truncate does not affect the value. */
10466 if (code == LSHIFTRT
10467 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
10468 && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
10469 && (INTVAL (XEXP (XEXP (varop, 0), 1))
10470 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
10471 - GET_MODE_BITSIZE (GET_MODE (varop)))))
10473 rtx varop_inner = XEXP (varop, 0);
10476 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
10477 XEXP (varop_inner, 0),
10479 (count + INTVAL (XEXP (varop_inner, 1))));
10480 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
10493 shift_mode = try_widen_shift_mode (code, varop, count, result_mode, mode,
10494 outer_op, outer_const);
10496 /* We have now finished analyzing the shift. The result should be
10497 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10498 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10499 to the result of the shift. OUTER_CONST is the relevant constant,
10500 but we must turn off all bits turned off in the shift. */
10502 if (outer_op == UNKNOWN
10503 && orig_code == code && orig_count == count
10504 && varop == orig_varop
10505 && shift_mode == GET_MODE (varop))
10508 /* Make a SUBREG if necessary. If we can't make it, fail. */
10509 varop = gen_lowpart (shift_mode, varop);
10510 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
10513 /* If we have an outer operation and we just made a shift, it is
10514 possible that we could have simplified the shift were it not
10515 for the outer operation. So try to do the simplification
10518 if (outer_op != UNKNOWN)
10519 x = simplify_shift_const_1 (code, shift_mode, varop, count);
10524 x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
10526 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10527 turn off all the bits that the shift would have turned off. */
10528 if (orig_code == LSHIFTRT && result_mode != shift_mode)
10529 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
10530 GET_MODE_MASK (result_mode) >> orig_count);
10532 /* Do the remainder of the processing in RESULT_MODE. */
10533 x = gen_lowpart_or_truncate (result_mode, x);
10535 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10538 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
10540 if (outer_op != UNKNOWN)
10542 if (GET_RTX_CLASS (outer_op) != RTX_UNARY
10543 && GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
10544 outer_const = trunc_int_for_mode (outer_const, result_mode);
10546 if (outer_op == AND)
10547 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
10548 else if (outer_op == SET)
10550 /* This means that we have determined that the result is
10551 equivalent to a constant. This should be rare. */
10552 if (!side_effects_p (x))
10553 x = GEN_INT (outer_const);
10555 else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
10556 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
10558 x = simplify_gen_binary (outer_op, result_mode, x,
10559 GEN_INT (outer_const));
10565 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10566 The result of the shift is RESULT_MODE. If we cannot simplify it,
10567 return X or, if it is NULL, synthesize the expression with
10568 simplify_gen_binary. Otherwise, return a simplified value.
10570 The shift is normally computed in the widest mode we find in VAROP, as
10571 long as it isn't a different number of words than RESULT_MODE. Exceptions
10572 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10575 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
10576 rtx varop, int count)
10578 rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
10583 x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
10584 if (GET_MODE (x) != result_mode)
10585 x = gen_lowpart (result_mode, x);
10590 /* Like recog, but we receive the address of a pointer to a new pattern.
10591 We try to match the rtx that the pointer points to.
10592 If that fails, we may try to modify or replace the pattern,
10593 storing the replacement into the same pointer object.
10595 Modifications include deletion or addition of CLOBBERs.
10597 PNOTES is a pointer to a location where any REG_UNUSED notes added for
10598 the CLOBBERs are placed.
10600 The value is the final insn code from the pattern ultimately matched,
10604 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
10606 rtx pat = *pnewpat;
10607 int insn_code_number;
10608 int num_clobbers_to_add = 0;
10611 rtx old_notes, old_pat;
10613 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10614 we use to indicate that something didn't match. If we find such a
10615 thing, force rejection. */
10616 if (GET_CODE (pat) == PARALLEL)
10617 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
10618 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
10619 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
10622 old_pat = PATTERN (insn);
10623 old_notes = REG_NOTES (insn);
10624 PATTERN (insn) = pat;
10625 REG_NOTES (insn) = 0;
10627 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10628 if (dump_file && (dump_flags & TDF_DETAILS))
10630 if (insn_code_number < 0)
10631 fputs ("Failed to match this instruction:\n", dump_file);
10633 fputs ("Successfully matched this instruction:\n", dump_file);
10634 print_rtl_single (dump_file, pat);
10637 /* If it isn't, there is the possibility that we previously had an insn
10638 that clobbered some register as a side effect, but the combined
10639 insn doesn't need to do that. So try once more without the clobbers
10640 unless this represents an ASM insn. */
10642 if (insn_code_number < 0 && ! check_asm_operands (pat)
10643 && GET_CODE (pat) == PARALLEL)
10647 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
10648 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
10651 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
10655 SUBST_INT (XVECLEN (pat, 0), pos);
10658 pat = XVECEXP (pat, 0, 0);
10660 PATTERN (insn) = pat;
10661 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10662 if (dump_file && (dump_flags & TDF_DETAILS))
10664 if (insn_code_number < 0)
10665 fputs ("Failed to match this instruction:\n", dump_file);
10667 fputs ("Successfully matched this instruction:\n", dump_file);
10668 print_rtl_single (dump_file, pat);
10671 PATTERN (insn) = old_pat;
10672 REG_NOTES (insn) = old_notes;
10674 /* Recognize all noop sets, these will be killed by followup pass. */
10675 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
10676 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
10678 /* If we had any clobbers to add, make a new pattern than contains
10679 them. Then check to make sure that all of them are dead. */
10680 if (num_clobbers_to_add)
10682 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
10683 rtvec_alloc (GET_CODE (pat) == PARALLEL
10684 ? (XVECLEN (pat, 0)
10685 + num_clobbers_to_add)
10686 : num_clobbers_to_add + 1));
10688 if (GET_CODE (pat) == PARALLEL)
10689 for (i = 0; i < XVECLEN (pat, 0); i++)
10690 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
10692 XVECEXP (newpat, 0, 0) = pat;
10694 add_clobbers (newpat, insn_code_number);
10696 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
10697 i < XVECLEN (newpat, 0); i++)
10699 if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
10700 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
10702 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH)
10704 gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)));
10705 notes = alloc_reg_note (REG_UNUSED,
10706 XEXP (XVECEXP (newpat, 0, i), 0), notes);
10715 return insn_code_number;
10718 /* Like gen_lowpart_general but for use by combine. In combine it
10719 is not possible to create any new pseudoregs. However, it is
10720 safe to create invalid memory addresses, because combine will
10721 try to recognize them and all they will do is make the combine
10724 If for some reason this cannot do its job, an rtx
10725 (clobber (const_int 0)) is returned.
10726 An insn containing that will not be recognized. */
10729 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
10731 enum machine_mode imode = GET_MODE (x);
10732 unsigned int osize = GET_MODE_SIZE (omode);
10733 unsigned int isize = GET_MODE_SIZE (imode);
10736 if (omode == imode)
10739 /* Return identity if this is a CONST or symbolic reference. */
10741 && (GET_CODE (x) == CONST
10742 || GET_CODE (x) == SYMBOL_REF
10743 || GET_CODE (x) == LABEL_REF))
10746 /* We can only support MODE being wider than a word if X is a
10747 constant integer or has a mode the same size. */
10748 if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
10749 && ! ((imode == VOIDmode
10750 && (CONST_INT_P (x)
10751 || GET_CODE (x) == CONST_DOUBLE))
10752 || isize == osize))
10755 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10756 won't know what to do. So we will strip off the SUBREG here and
10757 process normally. */
10758 if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
10760 x = SUBREG_REG (x);
10762 /* For use in case we fall down into the address adjustments
10763 further below, we need to adjust the known mode and size of
10764 x; imode and isize, since we just adjusted x. */
10765 imode = GET_MODE (x);
10767 if (imode == omode)
10770 isize = GET_MODE_SIZE (imode);
10773 result = gen_lowpart_common (omode, x);
10782 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10784 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
10787 /* If we want to refer to something bigger than the original memref,
10788 generate a paradoxical subreg instead. That will force a reload
10789 of the original memref X. */
10791 return gen_rtx_SUBREG (omode, x, 0);
10793 if (WORDS_BIG_ENDIAN)
10794 offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
10796 /* Adjust the address so that the address-after-the-data is
10798 if (BYTES_BIG_ENDIAN)
10799 offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
10801 return adjust_address_nv (x, omode, offset);
10804 /* If X is a comparison operator, rewrite it in a new mode. This
10805 probably won't match, but may allow further simplifications. */
10806 else if (COMPARISON_P (x))
10807 return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
10809 /* If we couldn't simplify X any other way, just enclose it in a
10810 SUBREG. Normally, this SUBREG won't match, but some patterns may
10811 include an explicit SUBREG or we may simplify it further in combine. */
10817 offset = subreg_lowpart_offset (omode, imode);
10818 if (imode == VOIDmode)
10820 imode = int_mode_for_mode (omode);
10821 x = gen_lowpart_common (imode, x);
10825 res = simplify_gen_subreg (omode, x, imode, offset);
10831 return gen_rtx_CLOBBER (omode, const0_rtx);
10834 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10835 comparison code that will be tested.
10837 The result is a possibly different comparison code to use. *POP0 and
10838 *POP1 may be updated.
10840 It is possible that we might detect that a comparison is either always
10841 true or always false. However, we do not perform general constant
10842 folding in combine, so this knowledge isn't useful. Such tautologies
10843 should have been detected earlier. Hence we ignore all such cases. */
10845 static enum rtx_code
10846 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
10852 enum machine_mode mode, tmode;
10854 /* Try a few ways of applying the same transformation to both operands. */
10857 #ifndef WORD_REGISTER_OPERATIONS
10858 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10859 so check specially. */
10860 if (code != GTU && code != GEU && code != LTU && code != LEU
10861 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
10862 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10863 && GET_CODE (XEXP (op1, 0)) == ASHIFT
10864 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
10865 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
10866 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
10867 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
10868 && CONST_INT_P (XEXP (op0, 1))
10869 && XEXP (op0, 1) == XEXP (op1, 1)
10870 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10871 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
10872 && (INTVAL (XEXP (op0, 1))
10873 == (GET_MODE_BITSIZE (GET_MODE (op0))
10874 - (GET_MODE_BITSIZE
10875 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
10877 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
10878 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
10882 /* If both operands are the same constant shift, see if we can ignore the
10883 shift. We can if the shift is a rotate or if the bits shifted out of
10884 this shift are known to be zero for both inputs and if the type of
10885 comparison is compatible with the shift. */
10886 if (GET_CODE (op0) == GET_CODE (op1)
10887 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10888 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
10889 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
10890 && (code != GT && code != LT && code != GE && code != LE))
10891 || (GET_CODE (op0) == ASHIFTRT
10892 && (code != GTU && code != LTU
10893 && code != GEU && code != LEU)))
10894 && CONST_INT_P (XEXP (op0, 1))
10895 && INTVAL (XEXP (op0, 1)) >= 0
10896 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10897 && XEXP (op0, 1) == XEXP (op1, 1))
10899 enum machine_mode mode = GET_MODE (op0);
10900 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10901 int shift_count = INTVAL (XEXP (op0, 1));
10903 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
10904 mask &= (mask >> shift_count) << shift_count;
10905 else if (GET_CODE (op0) == ASHIFT)
10906 mask = (mask & (mask << shift_count)) >> shift_count;
10908 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
10909 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
10910 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
10915 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10916 SUBREGs are of the same mode, and, in both cases, the AND would
10917 be redundant if the comparison was done in the narrower mode,
10918 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10919 and the operand's possibly nonzero bits are 0xffffff01; in that case
10920 if we only care about QImode, we don't need the AND). This case
10921 occurs if the output mode of an scc insn is not SImode and
10922 STORE_FLAG_VALUE == 1 (e.g., the 386).
10924 Similarly, check for a case where the AND's are ZERO_EXTEND
10925 operations from some narrower mode even though a SUBREG is not
10928 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
10929 && CONST_INT_P (XEXP (op0, 1))
10930 && CONST_INT_P (XEXP (op1, 1)))
10932 rtx inner_op0 = XEXP (op0, 0);
10933 rtx inner_op1 = XEXP (op1, 0);
10934 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
10935 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
10938 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
10939 && (GET_MODE_SIZE (GET_MODE (inner_op0))
10940 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
10941 && (GET_MODE (SUBREG_REG (inner_op0))
10942 == GET_MODE (SUBREG_REG (inner_op1)))
10943 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
10944 <= HOST_BITS_PER_WIDE_INT)
10945 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
10946 GET_MODE (SUBREG_REG (inner_op0)))))
10947 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
10948 GET_MODE (SUBREG_REG (inner_op1))))))
10950 op0 = SUBREG_REG (inner_op0);
10951 op1 = SUBREG_REG (inner_op1);
10953 /* The resulting comparison is always unsigned since we masked
10954 off the original sign bit. */
10955 code = unsigned_condition (code);
10961 for (tmode = GET_CLASS_NARROWEST_MODE
10962 (GET_MODE_CLASS (GET_MODE (op0)));
10963 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
10964 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
10966 op0 = gen_lowpart (tmode, inner_op0);
10967 op1 = gen_lowpart (tmode, inner_op1);
10968 code = unsigned_condition (code);
10977 /* If both operands are NOT, we can strip off the outer operation
10978 and adjust the comparison code for swapped operands; similarly for
10979 NEG, except that this must be an equality comparison. */
10980 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
10981 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
10982 && (code == EQ || code == NE)))
10983 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
10989 /* If the first operand is a constant, swap the operands and adjust the
10990 comparison code appropriately, but don't do this if the second operand
10991 is already a constant integer. */
10992 if (swap_commutative_operands_p (op0, op1))
10994 tem = op0, op0 = op1, op1 = tem;
10995 code = swap_condition (code);
10998 /* We now enter a loop during which we will try to simplify the comparison.
10999 For the most part, we only are concerned with comparisons with zero,
11000 but some things may really be comparisons with zero but not start
11001 out looking that way. */
11003 while (CONST_INT_P (op1))
11005 enum machine_mode mode = GET_MODE (op0);
11006 unsigned int mode_width = GET_MODE_BITSIZE (mode);
11007 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
11008 int equality_comparison_p;
11009 int sign_bit_comparison_p;
11010 int unsigned_comparison_p;
11011 HOST_WIDE_INT const_op;
11013 /* We only want to handle integral modes. This catches VOIDmode,
11014 CCmode, and the floating-point modes. An exception is that we
11015 can handle VOIDmode if OP0 is a COMPARE or a comparison
11018 if (GET_MODE_CLASS (mode) != MODE_INT
11019 && ! (mode == VOIDmode
11020 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
11023 /* Get the constant we are comparing against and turn off all bits
11024 not on in our mode. */
11025 const_op = INTVAL (op1);
11026 if (mode != VOIDmode)
11027 const_op = trunc_int_for_mode (const_op, mode);
11028 op1 = GEN_INT (const_op);
11030 /* If we are comparing against a constant power of two and the value
11031 being compared can only have that single bit nonzero (e.g., it was
11032 `and'ed with that bit), we can replace this with a comparison
11035 && (code == EQ || code == NE || code == GE || code == GEU
11036 || code == LT || code == LTU)
11037 && mode_width <= HOST_BITS_PER_WIDE_INT
11038 && exact_log2 (const_op) >= 0
11039 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
11041 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
11042 op1 = const0_rtx, const_op = 0;
11045 /* Similarly, if we are comparing a value known to be either -1 or
11046 0 with -1, change it to the opposite comparison against zero. */
11049 && (code == EQ || code == NE || code == GT || code == LE
11050 || code == GEU || code == LTU)
11051 && num_sign_bit_copies (op0, mode) == mode_width)
11053 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
11054 op1 = const0_rtx, const_op = 0;
11057 /* Do some canonicalizations based on the comparison code. We prefer
11058 comparisons against zero and then prefer equality comparisons.
11059 If we can reduce the size of a constant, we will do that too. */
11064 /* < C is equivalent to <= (C - 1) */
11068 op1 = GEN_INT (const_op);
11070 /* ... fall through to LE case below. */
11076 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11080 op1 = GEN_INT (const_op);
11084 /* If we are doing a <= 0 comparison on a value known to have
11085 a zero sign bit, we can replace this with == 0. */
11086 else if (const_op == 0
11087 && mode_width <= HOST_BITS_PER_WIDE_INT
11088 && (nonzero_bits (op0, mode)
11089 & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11095 /* >= C is equivalent to > (C - 1). */
11099 op1 = GEN_INT (const_op);
11101 /* ... fall through to GT below. */
11107 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11111 op1 = GEN_INT (const_op);
11115 /* If we are doing a > 0 comparison on a value known to have
11116 a zero sign bit, we can replace this with != 0. */
11117 else if (const_op == 0
11118 && mode_width <= HOST_BITS_PER_WIDE_INT
11119 && (nonzero_bits (op0, mode)
11120 & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11126 /* < C is equivalent to <= (C - 1). */
11130 op1 = GEN_INT (const_op);
11132 /* ... fall through ... */
11135 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11136 else if (mode_width <= HOST_BITS_PER_WIDE_INT
11137 && (unsigned HOST_WIDE_INT) const_op
11138 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1))
11140 const_op = 0, op1 = const0_rtx;
11148 /* unsigned <= 0 is equivalent to == 0 */
11152 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11153 else if (mode_width <= HOST_BITS_PER_WIDE_INT
11154 && (unsigned HOST_WIDE_INT) const_op
11155 == ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
11157 const_op = 0, op1 = const0_rtx;
11163 /* >= C is equivalent to > (C - 1). */
11167 op1 = GEN_INT (const_op);
11169 /* ... fall through ... */
11172 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11173 else if (mode_width <= HOST_BITS_PER_WIDE_INT
11174 && (unsigned HOST_WIDE_INT) const_op
11175 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1))
11177 const_op = 0, op1 = const0_rtx;
11185 /* unsigned > 0 is equivalent to != 0 */
11189 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11190 else if (mode_width <= HOST_BITS_PER_WIDE_INT
11191 && (unsigned HOST_WIDE_INT) const_op
11192 == ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
11194 const_op = 0, op1 = const0_rtx;
11203 /* Compute some predicates to simplify code below. */
11205 equality_comparison_p = (code == EQ || code == NE);
11206 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
11207 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
11210 /* If this is a sign bit comparison and we can do arithmetic in
11211 MODE, say that we will only be needing the sign bit of OP0. */
11212 if (sign_bit_comparison_p
11213 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11214 op0 = force_to_mode (op0, mode,
11215 (unsigned HOST_WIDE_INT) 1
11216 << (GET_MODE_BITSIZE (mode) - 1),
11219 /* Now try cases based on the opcode of OP0. If none of the cases
11220 does a "continue", we exit this loop immediately after the
11223 switch (GET_CODE (op0))
11226 /* If we are extracting a single bit from a variable position in
11227 a constant that has only a single bit set and are comparing it
11228 with zero, we can convert this into an equality comparison
11229 between the position and the location of the single bit. */
11230 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11231 have already reduced the shift count modulo the word size. */
11232 if (!SHIFT_COUNT_TRUNCATED
11233 && CONST_INT_P (XEXP (op0, 0))
11234 && XEXP (op0, 1) == const1_rtx
11235 && equality_comparison_p && const_op == 0
11236 && (i = exact_log2 (UINTVAL (XEXP (op0, 0)))) >= 0)
11238 if (BITS_BIG_ENDIAN)
11240 enum machine_mode new_mode
11241 = mode_for_extraction (EP_extzv, 1);
11242 if (new_mode == MAX_MACHINE_MODE)
11243 i = BITS_PER_WORD - 1 - i;
11247 i = (GET_MODE_BITSIZE (mode) - 1 - i);
11251 op0 = XEXP (op0, 2);
11255 /* Result is nonzero iff shift count is equal to I. */
11256 code = reverse_condition (code);
11260 /* ... fall through ... */
11263 tem = expand_compound_operation (op0);
11272 /* If testing for equality, we can take the NOT of the constant. */
11273 if (equality_comparison_p
11274 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
11276 op0 = XEXP (op0, 0);
11281 /* If just looking at the sign bit, reverse the sense of the
11283 if (sign_bit_comparison_p)
11285 op0 = XEXP (op0, 0);
11286 code = (code == GE ? LT : GE);
11292 /* If testing for equality, we can take the NEG of the constant. */
11293 if (equality_comparison_p
11294 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
11296 op0 = XEXP (op0, 0);
11301 /* The remaining cases only apply to comparisons with zero. */
11305 /* When X is ABS or is known positive,
11306 (neg X) is < 0 if and only if X != 0. */
11308 if (sign_bit_comparison_p
11309 && (GET_CODE (XEXP (op0, 0)) == ABS
11310 || (mode_width <= HOST_BITS_PER_WIDE_INT
11311 && (nonzero_bits (XEXP (op0, 0), mode)
11312 & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11315 op0 = XEXP (op0, 0);
11316 code = (code == LT ? NE : EQ);
11320 /* If we have NEG of something whose two high-order bits are the
11321 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11322 if (num_sign_bit_copies (op0, mode) >= 2)
11324 op0 = XEXP (op0, 0);
11325 code = swap_condition (code);
11331 /* If we are testing equality and our count is a constant, we
11332 can perform the inverse operation on our RHS. */
11333 if (equality_comparison_p && CONST_INT_P (XEXP (op0, 1))
11334 && (tem = simplify_binary_operation (ROTATERT, mode,
11335 op1, XEXP (op0, 1))) != 0)
11337 op0 = XEXP (op0, 0);
11342 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11343 a particular bit. Convert it to an AND of a constant of that
11344 bit. This will be converted into a ZERO_EXTRACT. */
11345 if (const_op == 0 && sign_bit_comparison_p
11346 && CONST_INT_P (XEXP (op0, 1))
11347 && mode_width <= HOST_BITS_PER_WIDE_INT)
11349 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11350 ((unsigned HOST_WIDE_INT) 1
11352 - INTVAL (XEXP (op0, 1)))));
11353 code = (code == LT ? NE : EQ);
11357 /* Fall through. */
11360 /* ABS is ignorable inside an equality comparison with zero. */
11361 if (const_op == 0 && equality_comparison_p)
11363 op0 = XEXP (op0, 0);
11369 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11370 (compare FOO CONST) if CONST fits in FOO's mode and we
11371 are either testing inequality or have an unsigned
11372 comparison with ZERO_EXTEND or a signed comparison with
11373 SIGN_EXTEND. But don't do it if we don't have a compare
11374 insn of the given mode, since we'd have to revert it
11375 later on, and then we wouldn't know whether to sign- or
11377 mode = GET_MODE (XEXP (op0, 0));
11378 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11379 && ! unsigned_comparison_p
11380 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11381 && ((unsigned HOST_WIDE_INT) const_op
11382 < (((unsigned HOST_WIDE_INT) 1
11383 << (GET_MODE_BITSIZE (mode) - 1))))
11384 && have_insn_for (COMPARE, mode))
11386 op0 = XEXP (op0, 0);
11392 /* Check for the case where we are comparing A - C1 with C2, that is
11394 (subreg:MODE (plus (A) (-C1))) op (C2)
11396 with C1 a constant, and try to lift the SUBREG, i.e. to do the
11397 comparison in the wider mode. One of the following two conditions
11398 must be true in order for this to be valid:
11400 1. The mode extension results in the same bit pattern being added
11401 on both sides and the comparison is equality or unsigned. As
11402 C2 has been truncated to fit in MODE, the pattern can only be
11405 2. The mode extension results in the sign bit being copied on
11408 The difficulty here is that we have predicates for A but not for
11409 (A - C1) so we need to check that C1 is within proper bounds so
11410 as to perturbate A as little as possible. */
11412 if (mode_width <= HOST_BITS_PER_WIDE_INT
11413 && subreg_lowpart_p (op0)
11414 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) > mode_width
11415 && GET_CODE (SUBREG_REG (op0)) == PLUS
11416 && CONST_INT_P (XEXP (SUBREG_REG (op0), 1)))
11418 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
11419 rtx a = XEXP (SUBREG_REG (op0), 0);
11420 HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
11423 && (unsigned HOST_WIDE_INT) c1
11424 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
11425 && (equality_comparison_p || unsigned_comparison_p)
11426 /* (A - C1) zero-extends if it is positive and sign-extends
11427 if it is negative, C2 both zero- and sign-extends. */
11428 && ((0 == (nonzero_bits (a, inner_mode)
11429 & ~GET_MODE_MASK (mode))
11431 /* (A - C1) sign-extends if it is positive and 1-extends
11432 if it is negative, C2 both sign- and 1-extends. */
11433 || (num_sign_bit_copies (a, inner_mode)
11434 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
11437 || ((unsigned HOST_WIDE_INT) c1
11438 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
11439 /* (A - C1) always sign-extends, like C2. */
11440 && num_sign_bit_copies (a, inner_mode)
11441 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
11442 - (mode_width - 1))))
11444 op0 = SUBREG_REG (op0);
11449 /* If the inner mode is narrower and we are extracting the low part,
11450 we can treat the SUBREG as if it were a ZERO_EXTEND. */
11451 if (subreg_lowpart_p (op0)
11452 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
11453 /* Fall through */ ;
11457 /* ... fall through ... */
11460 mode = GET_MODE (XEXP (op0, 0));
11461 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11462 && (unsigned_comparison_p || equality_comparison_p)
11463 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11464 && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode))
11465 && have_insn_for (COMPARE, mode))
11467 op0 = XEXP (op0, 0);
11473 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
11474 this for equality comparisons due to pathological cases involving
11476 if (equality_comparison_p
11477 && 0 != (tem = simplify_binary_operation (MINUS, mode,
11478 op1, XEXP (op0, 1))))
11480 op0 = XEXP (op0, 0);
11485 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
11486 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
11487 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
11489 op0 = XEXP (XEXP (op0, 0), 0);
11490 code = (code == LT ? EQ : NE);
11496 /* We used to optimize signed comparisons against zero, but that
11497 was incorrect. Unsigned comparisons against zero (GTU, LEU)
11498 arrive here as equality comparisons, or (GEU, LTU) are
11499 optimized away. No need to special-case them. */
11501 /* (eq (minus A B) C) -> (eq A (plus B C)) or
11502 (eq B (minus A C)), whichever simplifies. We can only do
11503 this for equality comparisons due to pathological cases involving
11505 if (equality_comparison_p
11506 && 0 != (tem = simplify_binary_operation (PLUS, mode,
11507 XEXP (op0, 1), op1)))
11509 op0 = XEXP (op0, 0);
11514 if (equality_comparison_p
11515 && 0 != (tem = simplify_binary_operation (MINUS, mode,
11516 XEXP (op0, 0), op1)))
11518 op0 = XEXP (op0, 1);
11523 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11524 of bits in X minus 1, is one iff X > 0. */
11525 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
11526 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11527 && UINTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
11528 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11530 op0 = XEXP (op0, 1);
11531 code = (code == GE ? LE : GT);
11537 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11538 if C is zero or B is a constant. */
11539 if (equality_comparison_p
11540 && 0 != (tem = simplify_binary_operation (XOR, mode,
11541 XEXP (op0, 1), op1)))
11543 op0 = XEXP (op0, 0);
11550 case UNEQ: case LTGT:
11551 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
11552 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
11553 case UNORDERED: case ORDERED:
11554 /* We can't do anything if OP0 is a condition code value, rather
11555 than an actual data value. */
11557 || CC0_P (XEXP (op0, 0))
11558 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
11561 /* Get the two operands being compared. */
11562 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
11563 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
11565 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
11567 /* Check for the cases where we simply want the result of the
11568 earlier test or the opposite of that result. */
11569 if (code == NE || code == EQ
11570 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
11571 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11572 && (STORE_FLAG_VALUE
11573 & (((unsigned HOST_WIDE_INT) 1
11574 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
11575 && (code == LT || code == GE)))
11577 enum rtx_code new_code;
11578 if (code == LT || code == NE)
11579 new_code = GET_CODE (op0);
11581 new_code = reversed_comparison_code (op0, NULL);
11583 if (new_code != UNKNOWN)
11594 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11596 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
11597 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
11598 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11600 op0 = XEXP (op0, 1);
11601 code = (code == GE ? GT : LE);
11607 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11608 will be converted to a ZERO_EXTRACT later. */
11609 if (const_op == 0 && equality_comparison_p
11610 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11611 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
11613 op0 = gen_rtx_LSHIFTRT (mode, XEXP (op0, 1),
11614 XEXP (XEXP (op0, 0), 1));
11615 op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
11619 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11620 zero and X is a comparison and C1 and C2 describe only bits set
11621 in STORE_FLAG_VALUE, we can compare with X. */
11622 if (const_op == 0 && equality_comparison_p
11623 && mode_width <= HOST_BITS_PER_WIDE_INT
11624 && CONST_INT_P (XEXP (op0, 1))
11625 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
11626 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11627 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
11628 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
11630 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11631 << INTVAL (XEXP (XEXP (op0, 0), 1)));
11632 if ((~STORE_FLAG_VALUE & mask) == 0
11633 && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
11634 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
11635 && COMPARISON_P (tem))))
11637 op0 = XEXP (XEXP (op0, 0), 0);
11642 /* If we are doing an equality comparison of an AND of a bit equal
11643 to the sign bit, replace this with a LT or GE comparison of
11644 the underlying value. */
11645 if (equality_comparison_p
11647 && CONST_INT_P (XEXP (op0, 1))
11648 && mode_width <= HOST_BITS_PER_WIDE_INT
11649 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11650 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11652 op0 = XEXP (op0, 0);
11653 code = (code == EQ ? GE : LT);
11657 /* If this AND operation is really a ZERO_EXTEND from a narrower
11658 mode, the constant fits within that mode, and this is either an
11659 equality or unsigned comparison, try to do this comparison in
11664 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11665 -> (ne:DI (reg:SI 4) (const_int 0))
11667 unless TRULY_NOOP_TRUNCATION allows it or the register is
11668 known to hold a value of the required mode the
11669 transformation is invalid. */
11670 if ((equality_comparison_p || unsigned_comparison_p)
11671 && CONST_INT_P (XEXP (op0, 1))
11672 && (i = exact_log2 ((UINTVAL (XEXP (op0, 1))
11673 & GET_MODE_MASK (mode))
11675 && const_op >> i == 0
11676 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode
11677 && (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
11678 GET_MODE_BITSIZE (GET_MODE (op0)))
11679 || (REG_P (XEXP (op0, 0))
11680 && reg_truncated_to_mode (tmode, XEXP (op0, 0)))))
11682 op0 = gen_lowpart (tmode, XEXP (op0, 0));
11686 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11687 fits in both M1 and M2 and the SUBREG is either paradoxical
11688 or represents the low part, permute the SUBREG and the AND
11690 if (GET_CODE (XEXP (op0, 0)) == SUBREG)
11692 unsigned HOST_WIDE_INT c1;
11693 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
11694 /* Require an integral mode, to avoid creating something like
11696 if (SCALAR_INT_MODE_P (tmode)
11697 /* It is unsafe to commute the AND into the SUBREG if the
11698 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11699 not defined. As originally written the upper bits
11700 have a defined value due to the AND operation.
11701 However, if we commute the AND inside the SUBREG then
11702 they no longer have defined values and the meaning of
11703 the code has been changed. */
11705 #ifdef WORD_REGISTER_OPERATIONS
11706 || (mode_width > GET_MODE_BITSIZE (tmode)
11707 && mode_width <= BITS_PER_WORD)
11709 || (mode_width <= GET_MODE_BITSIZE (tmode)
11710 && subreg_lowpart_p (XEXP (op0, 0))))
11711 && CONST_INT_P (XEXP (op0, 1))
11712 && mode_width <= HOST_BITS_PER_WIDE_INT
11713 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
11714 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
11715 && (c1 & ~GET_MODE_MASK (tmode)) == 0
11717 && c1 != GET_MODE_MASK (tmode))
11719 op0 = simplify_gen_binary (AND, tmode,
11720 SUBREG_REG (XEXP (op0, 0)),
11721 gen_int_mode (c1, tmode));
11722 op0 = gen_lowpart (mode, op0);
11727 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
11728 if (const_op == 0 && equality_comparison_p
11729 && XEXP (op0, 1) == const1_rtx
11730 && GET_CODE (XEXP (op0, 0)) == NOT)
11732 op0 = simplify_and_const_int (NULL_RTX, mode,
11733 XEXP (XEXP (op0, 0), 0), 1);
11734 code = (code == NE ? EQ : NE);
11738 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11739 (eq (and (lshiftrt X) 1) 0).
11740 Also handle the case where (not X) is expressed using xor. */
11741 if (const_op == 0 && equality_comparison_p
11742 && XEXP (op0, 1) == const1_rtx
11743 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
11745 rtx shift_op = XEXP (XEXP (op0, 0), 0);
11746 rtx shift_count = XEXP (XEXP (op0, 0), 1);
11748 if (GET_CODE (shift_op) == NOT
11749 || (GET_CODE (shift_op) == XOR
11750 && CONST_INT_P (XEXP (shift_op, 1))
11751 && CONST_INT_P (shift_count)
11752 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
11753 && (UINTVAL (XEXP (shift_op, 1))
11754 == (unsigned HOST_WIDE_INT) 1
11755 << INTVAL (shift_count))))
11758 = gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count);
11759 op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
11760 code = (code == NE ? EQ : NE);
11767 /* If we have (compare (ashift FOO N) (const_int C)) and
11768 the high order N bits of FOO (N+1 if an inequality comparison)
11769 are known to be zero, we can do this by comparing FOO with C
11770 shifted right N bits so long as the low-order N bits of C are
11772 if (CONST_INT_P (XEXP (op0, 1))
11773 && INTVAL (XEXP (op0, 1)) >= 0
11774 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
11775 < HOST_BITS_PER_WIDE_INT)
11776 && (((unsigned HOST_WIDE_INT) const_op
11777 & (((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1)))
11779 && mode_width <= HOST_BITS_PER_WIDE_INT
11780 && (nonzero_bits (XEXP (op0, 0), mode)
11781 & ~(mask >> (INTVAL (XEXP (op0, 1))
11782 + ! equality_comparison_p))) == 0)
11784 /* We must perform a logical shift, not an arithmetic one,
11785 as we want the top N bits of C to be zero. */
11786 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
11788 temp >>= INTVAL (XEXP (op0, 1));
11789 op1 = gen_int_mode (temp, mode);
11790 op0 = XEXP (op0, 0);
11794 /* If we are doing a sign bit comparison, it means we are testing
11795 a particular bit. Convert it to the appropriate AND. */
11796 if (sign_bit_comparison_p && CONST_INT_P (XEXP (op0, 1))
11797 && mode_width <= HOST_BITS_PER_WIDE_INT)
11799 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11800 ((unsigned HOST_WIDE_INT) 1
11802 - INTVAL (XEXP (op0, 1)))));
11803 code = (code == LT ? NE : EQ);
11807 /* If this an equality comparison with zero and we are shifting
11808 the low bit to the sign bit, we can convert this to an AND of the
11810 if (const_op == 0 && equality_comparison_p
11811 && CONST_INT_P (XEXP (op0, 1))
11812 && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
11814 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), 1);
11820 /* If this is an equality comparison with zero, we can do this
11821 as a logical shift, which might be much simpler. */
11822 if (equality_comparison_p && const_op == 0
11823 && CONST_INT_P (XEXP (op0, 1)))
11825 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
11827 INTVAL (XEXP (op0, 1)));
11831 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11832 do the comparison in a narrower mode. */
11833 if (! unsigned_comparison_p
11834 && CONST_INT_P (XEXP (op0, 1))
11835 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11836 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11837 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11838 MODE_INT, 1)) != BLKmode
11839 && (((unsigned HOST_WIDE_INT) const_op
11840 + (GET_MODE_MASK (tmode) >> 1) + 1)
11841 <= GET_MODE_MASK (tmode)))
11843 op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
11847 /* Likewise if OP0 is a PLUS of a sign extension with a
11848 constant, which is usually represented with the PLUS
11849 between the shifts. */
11850 if (! unsigned_comparison_p
11851 && CONST_INT_P (XEXP (op0, 1))
11852 && GET_CODE (XEXP (op0, 0)) == PLUS
11853 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11854 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
11855 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
11856 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11857 MODE_INT, 1)) != BLKmode
11858 && (((unsigned HOST_WIDE_INT) const_op
11859 + (GET_MODE_MASK (tmode) >> 1) + 1)
11860 <= GET_MODE_MASK (tmode)))
11862 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
11863 rtx add_const = XEXP (XEXP (op0, 0), 1);
11864 rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
11865 add_const, XEXP (op0, 1));
11867 op0 = simplify_gen_binary (PLUS, tmode,
11868 gen_lowpart (tmode, inner),
11873 /* ... fall through ... */
11875 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11876 the low order N bits of FOO are known to be zero, we can do this
11877 by comparing FOO with C shifted left N bits so long as no
11878 overflow occurs. Even if the low order N bits of FOO aren't known
11879 to be zero, if the comparison is >= or < we can use the same
11880 optimization and for > or <= by setting all the low
11881 order N bits in the comparison constant. */
11882 if (CONST_INT_P (XEXP (op0, 1))
11883 && INTVAL (XEXP (op0, 1)) > 0
11884 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11885 && mode_width <= HOST_BITS_PER_WIDE_INT
11886 && (((unsigned HOST_WIDE_INT) const_op
11887 + (GET_CODE (op0) != LSHIFTRT
11888 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
11891 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
11893 unsigned HOST_WIDE_INT low_bits
11894 = (nonzero_bits (XEXP (op0, 0), mode)
11895 & (((unsigned HOST_WIDE_INT) 1
11896 << INTVAL (XEXP (op0, 1))) - 1));
11897 if (low_bits == 0 || !equality_comparison_p)
11899 /* If the shift was logical, then we must make the condition
11901 if (GET_CODE (op0) == LSHIFTRT)
11902 code = unsigned_condition (code);
11904 const_op <<= INTVAL (XEXP (op0, 1));
11906 && (code == GT || code == GTU
11907 || code == LE || code == LEU))
11909 |= (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1);
11910 op1 = GEN_INT (const_op);
11911 op0 = XEXP (op0, 0);
11916 /* If we are using this shift to extract just the sign bit, we
11917 can replace this with an LT or GE comparison. */
11919 && (equality_comparison_p || sign_bit_comparison_p)
11920 && CONST_INT_P (XEXP (op0, 1))
11921 && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
11923 op0 = XEXP (op0, 0);
11924 code = (code == NE || code == GT ? LT : GE);
11936 /* Now make any compound operations involved in this comparison. Then,
11937 check for an outmost SUBREG on OP0 that is not doing anything or is
11938 paradoxical. The latter transformation must only be performed when
11939 it is known that the "extra" bits will be the same in op0 and op1 or
11940 that they don't matter. There are three cases to consider:
11942 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11943 care bits and we can assume they have any convenient value. So
11944 making the transformation is safe.
11946 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11947 In this case the upper bits of op0 are undefined. We should not make
11948 the simplification in that case as we do not know the contents of
11951 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11952 UNKNOWN. In that case we know those bits are zeros or ones. We must
11953 also be sure that they are the same as the upper bits of op1.
11955 We can never remove a SUBREG for a non-equality comparison because
11956 the sign bit is in a different place in the underlying object. */
11958 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
11959 op1 = make_compound_operation (op1, SET);
11961 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11962 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11963 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
11964 && (code == NE || code == EQ))
11966 if (GET_MODE_SIZE (GET_MODE (op0))
11967 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
11969 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11971 if (REG_P (SUBREG_REG (op0)))
11973 op0 = SUBREG_REG (op0);
11974 op1 = gen_lowpart (GET_MODE (op0), op1);
11977 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
11978 <= HOST_BITS_PER_WIDE_INT)
11979 && (nonzero_bits (SUBREG_REG (op0),
11980 GET_MODE (SUBREG_REG (op0)))
11981 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11983 tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
11985 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11986 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11987 op0 = SUBREG_REG (op0), op1 = tem;
11991 /* We now do the opposite procedure: Some machines don't have compare
11992 insns in all modes. If OP0's mode is an integer mode smaller than a
11993 word and we can't do a compare in that mode, see if there is a larger
11994 mode for which we can do the compare. There are a number of cases in
11995 which we can use the wider mode. */
11997 mode = GET_MODE (op0);
11998 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11999 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
12000 && ! have_insn_for (COMPARE, mode))
12001 for (tmode = GET_MODE_WIDER_MODE (mode);
12003 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
12004 tmode = GET_MODE_WIDER_MODE (tmode))
12005 if (have_insn_for (COMPARE, tmode))
12009 /* If this is a test for negative, we can make an explicit
12010 test of the sign bit. Test this first so we can use
12011 a paradoxical subreg to extend OP0. */
12013 if (op1 == const0_rtx && (code == LT || code == GE)
12014 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
12016 op0 = simplify_gen_binary (AND, tmode,
12017 gen_lowpart (tmode, op0),
12018 GEN_INT ((unsigned HOST_WIDE_INT) 1
12019 << (GET_MODE_BITSIZE (mode)
12021 code = (code == LT) ? NE : EQ;
12025 /* If the only nonzero bits in OP0 and OP1 are those in the
12026 narrower mode and this is an equality or unsigned comparison,
12027 we can use the wider mode. Similarly for sign-extended
12028 values, in which case it is true for all comparisons. */
12029 zero_extended = ((code == EQ || code == NE
12030 || code == GEU || code == GTU
12031 || code == LEU || code == LTU)
12032 && (nonzero_bits (op0, tmode)
12033 & ~GET_MODE_MASK (mode)) == 0
12034 && ((CONST_INT_P (op1)
12035 || (nonzero_bits (op1, tmode)
12036 & ~GET_MODE_MASK (mode)) == 0)));
12039 || ((num_sign_bit_copies (op0, tmode)
12040 > (unsigned int) (GET_MODE_BITSIZE (tmode)
12041 - GET_MODE_BITSIZE (mode)))
12042 && (num_sign_bit_copies (op1, tmode)
12043 > (unsigned int) (GET_MODE_BITSIZE (tmode)
12044 - GET_MODE_BITSIZE (mode)))))
12046 /* If OP0 is an AND and we don't have an AND in MODE either,
12047 make a new AND in the proper mode. */
12048 if (GET_CODE (op0) == AND
12049 && !have_insn_for (AND, mode))
12050 op0 = simplify_gen_binary (AND, tmode,
12051 gen_lowpart (tmode,
12053 gen_lowpart (tmode,
12059 op0 = simplify_gen_unary (ZERO_EXTEND, tmode, op0, mode);
12060 op1 = simplify_gen_unary (ZERO_EXTEND, tmode, op1, mode);
12064 op0 = simplify_gen_unary (SIGN_EXTEND, tmode, op0, mode);
12065 op1 = simplify_gen_unary (SIGN_EXTEND, tmode, op1, mode);
12072 #ifdef CANONICALIZE_COMPARISON
12073 /* If this machine only supports a subset of valid comparisons, see if we
12074 can convert an unsupported one into a supported one. */
12075 CANONICALIZE_COMPARISON (code, op0, op1);
12084 /* Utility function for record_value_for_reg. Count number of
12089 enum rtx_code code = GET_CODE (x);
12093 if (GET_RTX_CLASS (code) == '2'
12094 || GET_RTX_CLASS (code) == 'c')
12096 rtx x0 = XEXP (x, 0);
12097 rtx x1 = XEXP (x, 1);
12100 return 1 + 2 * count_rtxs (x0);
12102 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
12103 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
12104 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12105 return 2 + 2 * count_rtxs (x0)
12106 + count_rtxs (x == XEXP (x1, 0)
12107 ? XEXP (x1, 1) : XEXP (x1, 0));
12109 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
12110 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
12111 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12112 return 2 + 2 * count_rtxs (x1)
12113 + count_rtxs (x == XEXP (x0, 0)
12114 ? XEXP (x0, 1) : XEXP (x0, 0));
12117 fmt = GET_RTX_FORMAT (code);
12118 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12120 ret += count_rtxs (XEXP (x, i));
12121 else if (fmt[i] == 'E')
12122 for (j = 0; j < XVECLEN (x, i); j++)
12123 ret += count_rtxs (XVECEXP (x, i, j));
12128 /* Utility function for following routine. Called when X is part of a value
12129 being stored into last_set_value. Sets last_set_table_tick
12130 for each register mentioned. Similar to mention_regs in cse.c */
12133 update_table_tick (rtx x)
12135 enum rtx_code code = GET_CODE (x);
12136 const char *fmt = GET_RTX_FORMAT (code);
12141 unsigned int regno = REGNO (x);
12142 unsigned int endregno = END_REGNO (x);
12145 for (r = regno; r < endregno; r++)
12147 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, r);
12148 rsp->last_set_table_tick = label_tick;
12154 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12157 /* Check for identical subexpressions. If x contains
12158 identical subexpression we only have to traverse one of
12160 if (i == 0 && ARITHMETIC_P (x))
12162 /* Note that at this point x1 has already been
12164 rtx x0 = XEXP (x, 0);
12165 rtx x1 = XEXP (x, 1);
12167 /* If x0 and x1 are identical then there is no need to
12172 /* If x0 is identical to a subexpression of x1 then while
12173 processing x1, x0 has already been processed. Thus we
12174 are done with x. */
12175 if (ARITHMETIC_P (x1)
12176 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12179 /* If x1 is identical to a subexpression of x0 then we
12180 still have to process the rest of x0. */
12181 if (ARITHMETIC_P (x0)
12182 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12184 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
12189 update_table_tick (XEXP (x, i));
12191 else if (fmt[i] == 'E')
12192 for (j = 0; j < XVECLEN (x, i); j++)
12193 update_table_tick (XVECEXP (x, i, j));
12196 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12197 are saying that the register is clobbered and we no longer know its
12198 value. If INSN is zero, don't update reg_stat[].last_set; this is
12199 only permitted with VALUE also zero and is used to invalidate the
12203 record_value_for_reg (rtx reg, rtx insn, rtx value)
12205 unsigned int regno = REGNO (reg);
12206 unsigned int endregno = END_REGNO (reg);
12208 reg_stat_type *rsp;
12210 /* If VALUE contains REG and we have a previous value for REG, substitute
12211 the previous value. */
12212 if (value && insn && reg_overlap_mentioned_p (reg, value))
12216 /* Set things up so get_last_value is allowed to see anything set up to
12218 subst_low_luid = DF_INSN_LUID (insn);
12219 tem = get_last_value (reg);
12221 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12222 it isn't going to be useful and will take a lot of time to process,
12223 so just use the CLOBBER. */
12227 if (ARITHMETIC_P (tem)
12228 && GET_CODE (XEXP (tem, 0)) == CLOBBER
12229 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
12230 tem = XEXP (tem, 0);
12231 else if (count_occurrences (value, reg, 1) >= 2)
12233 /* If there are two or more occurrences of REG in VALUE,
12234 prevent the value from growing too much. */
12235 if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
12236 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
12239 value = replace_rtx (copy_rtx (value), reg, tem);
12243 /* For each register modified, show we don't know its value, that
12244 we don't know about its bitwise content, that its value has been
12245 updated, and that we don't know the location of the death of the
12247 for (i = regno; i < endregno; i++)
12249 rsp = VEC_index (reg_stat_type, reg_stat, i);
12252 rsp->last_set = insn;
12254 rsp->last_set_value = 0;
12255 rsp->last_set_mode = VOIDmode;
12256 rsp->last_set_nonzero_bits = 0;
12257 rsp->last_set_sign_bit_copies = 0;
12258 rsp->last_death = 0;
12259 rsp->truncated_to_mode = VOIDmode;
12262 /* Mark registers that are being referenced in this value. */
12264 update_table_tick (value);
12266 /* Now update the status of each register being set.
12267 If someone is using this register in this block, set this register
12268 to invalid since we will get confused between the two lives in this
12269 basic block. This makes using this register always invalid. In cse, we
12270 scan the table to invalidate all entries using this register, but this
12271 is too much work for us. */
12273 for (i = regno; i < endregno; i++)
12275 rsp = VEC_index (reg_stat_type, reg_stat, i);
12276 rsp->last_set_label = label_tick;
12278 || (value && rsp->last_set_table_tick >= label_tick_ebb_start))
12279 rsp->last_set_invalid = 1;
12281 rsp->last_set_invalid = 0;
12284 /* The value being assigned might refer to X (like in "x++;"). In that
12285 case, we must replace it with (clobber (const_int 0)) to prevent
12287 rsp = VEC_index (reg_stat_type, reg_stat, regno);
12288 if (value && !get_last_value_validate (&value, insn, label_tick, 0))
12290 value = copy_rtx (value);
12291 if (!get_last_value_validate (&value, insn, label_tick, 1))
12295 /* For the main register being modified, update the value, the mode, the
12296 nonzero bits, and the number of sign bit copies. */
12298 rsp->last_set_value = value;
12302 enum machine_mode mode = GET_MODE (reg);
12303 subst_low_luid = DF_INSN_LUID (insn);
12304 rsp->last_set_mode = mode;
12305 if (GET_MODE_CLASS (mode) == MODE_INT
12306 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
12307 mode = nonzero_bits_mode;
12308 rsp->last_set_nonzero_bits = nonzero_bits (value, mode);
12309 rsp->last_set_sign_bit_copies
12310 = num_sign_bit_copies (value, GET_MODE (reg));
12314 /* Called via note_stores from record_dead_and_set_regs to handle one
12315 SET or CLOBBER in an insn. DATA is the instruction in which the
12316 set is occurring. */
12319 record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
12321 rtx record_dead_insn = (rtx) data;
12323 if (GET_CODE (dest) == SUBREG)
12324 dest = SUBREG_REG (dest);
12326 if (!record_dead_insn)
12329 record_value_for_reg (dest, NULL_RTX, NULL_RTX);
12335 /* If we are setting the whole register, we know its value. Otherwise
12336 show that we don't know the value. We can handle SUBREG in
12338 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
12339 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
12340 else if (GET_CODE (setter) == SET
12341 && GET_CODE (SET_DEST (setter)) == SUBREG
12342 && SUBREG_REG (SET_DEST (setter)) == dest
12343 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
12344 && subreg_lowpart_p (SET_DEST (setter)))
12345 record_value_for_reg (dest, record_dead_insn,
12346 gen_lowpart (GET_MODE (dest),
12347 SET_SRC (setter)));
12349 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
12351 else if (MEM_P (dest)
12352 /* Ignore pushes, they clobber nothing. */
12353 && ! push_operand (dest, GET_MODE (dest)))
12354 mem_last_set = DF_INSN_LUID (record_dead_insn);
12357 /* Update the records of when each REG was most recently set or killed
12358 for the things done by INSN. This is the last thing done in processing
12359 INSN in the combiner loop.
12361 We update reg_stat[], in particular fields last_set, last_set_value,
12362 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12363 last_death, and also the similar information mem_last_set (which insn
12364 most recently modified memory) and last_call_luid (which insn was the
12365 most recent subroutine call). */
12368 record_dead_and_set_regs (rtx insn)
12373 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
12375 if (REG_NOTE_KIND (link) == REG_DEAD
12376 && REG_P (XEXP (link, 0)))
12378 unsigned int regno = REGNO (XEXP (link, 0));
12379 unsigned int endregno = END_REGNO (XEXP (link, 0));
12381 for (i = regno; i < endregno; i++)
12383 reg_stat_type *rsp;
12385 rsp = VEC_index (reg_stat_type, reg_stat, i);
12386 rsp->last_death = insn;
12389 else if (REG_NOTE_KIND (link) == REG_INC)
12390 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
12395 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
12396 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
12398 reg_stat_type *rsp;
12400 rsp = VEC_index (reg_stat_type, reg_stat, i);
12401 rsp->last_set_invalid = 1;
12402 rsp->last_set = insn;
12403 rsp->last_set_value = 0;
12404 rsp->last_set_mode = VOIDmode;
12405 rsp->last_set_nonzero_bits = 0;
12406 rsp->last_set_sign_bit_copies = 0;
12407 rsp->last_death = 0;
12408 rsp->truncated_to_mode = VOIDmode;
12411 last_call_luid = mem_last_set = DF_INSN_LUID (insn);
12413 /* We can't combine into a call pattern. Remember, though, that
12414 the return value register is set at this LUID. We could
12415 still replace a register with the return value from the
12416 wrong subroutine call! */
12417 note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
12420 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
12423 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12424 register present in the SUBREG, so for each such SUBREG go back and
12425 adjust nonzero and sign bit information of the registers that are
12426 known to have some zero/sign bits set.
12428 This is needed because when combine blows the SUBREGs away, the
12429 information on zero/sign bits is lost and further combines can be
12430 missed because of that. */
12433 record_promoted_value (rtx insn, rtx subreg)
12436 unsigned int regno = REGNO (SUBREG_REG (subreg));
12437 enum machine_mode mode = GET_MODE (subreg);
12439 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
12442 for (links = LOG_LINKS (insn); links;)
12444 reg_stat_type *rsp;
12446 insn = XEXP (links, 0);
12447 set = single_set (insn);
12449 if (! set || !REG_P (SET_DEST (set))
12450 || REGNO (SET_DEST (set)) != regno
12451 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
12453 links = XEXP (links, 1);
12457 rsp = VEC_index (reg_stat_type, reg_stat, regno);
12458 if (rsp->last_set == insn)
12460 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
12461 rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode);
12464 if (REG_P (SET_SRC (set)))
12466 regno = REGNO (SET_SRC (set));
12467 links = LOG_LINKS (insn);
12474 /* Check if X, a register, is known to contain a value already
12475 truncated to MODE. In this case we can use a subreg to refer to
12476 the truncated value even though in the generic case we would need
12477 an explicit truncation. */
12480 reg_truncated_to_mode (enum machine_mode mode, const_rtx x)
12482 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
12483 enum machine_mode truncated = rsp->truncated_to_mode;
12486 || rsp->truncation_label < label_tick_ebb_start)
12488 if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
12490 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
12491 GET_MODE_BITSIZE (truncated)))
12496 /* Callback for for_each_rtx. If *P is a hard reg or a subreg record the mode
12497 that the register is accessed in. For non-TRULY_NOOP_TRUNCATION targets we
12498 might be able to turn a truncate into a subreg using this information.
12499 Return -1 if traversing *P is complete or 0 otherwise. */
12502 record_truncated_value (rtx *p, void *data ATTRIBUTE_UNUSED)
12505 enum machine_mode truncated_mode;
12506 reg_stat_type *rsp;
12508 if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
12510 enum machine_mode original_mode = GET_MODE (SUBREG_REG (x));
12511 truncated_mode = GET_MODE (x);
12513 if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
12516 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (truncated_mode),
12517 GET_MODE_BITSIZE (original_mode)))
12520 x = SUBREG_REG (x);
12522 /* ??? For hard-regs we now record everything. We might be able to
12523 optimize this using last_set_mode. */
12524 else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
12525 truncated_mode = GET_MODE (x);
12529 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
12530 if (rsp->truncated_to_mode == 0
12531 || rsp->truncation_label < label_tick_ebb_start
12532 || (GET_MODE_SIZE (truncated_mode)
12533 < GET_MODE_SIZE (rsp->truncated_to_mode)))
12535 rsp->truncated_to_mode = truncated_mode;
12536 rsp->truncation_label = label_tick;
12542 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12543 the modes they are used in. This can help truning TRUNCATEs into
12547 record_truncated_values (rtx *x, void *data ATTRIBUTE_UNUSED)
12549 for_each_rtx (x, record_truncated_value, NULL);
12552 /* Scan X for promoted SUBREGs. For each one found,
12553 note what it implies to the registers used in it. */
12556 check_promoted_subreg (rtx insn, rtx x)
12558 if (GET_CODE (x) == SUBREG
12559 && SUBREG_PROMOTED_VAR_P (x)
12560 && REG_P (SUBREG_REG (x)))
12561 record_promoted_value (insn, x);
12564 const char *format = GET_RTX_FORMAT (GET_CODE (x));
12567 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
12571 check_promoted_subreg (insn, XEXP (x, i));
12575 if (XVEC (x, i) != 0)
12576 for (j = 0; j < XVECLEN (x, i); j++)
12577 check_promoted_subreg (insn, XVECEXP (x, i, j));
12583 /* Verify that all the registers and memory references mentioned in *LOC are
12584 still valid. *LOC was part of a value set in INSN when label_tick was
12585 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12586 the invalid references with (clobber (const_int 0)) and return 1. This
12587 replacement is useful because we often can get useful information about
12588 the form of a value (e.g., if it was produced by a shift that always
12589 produces -1 or 0) even though we don't know exactly what registers it
12590 was produced from. */
12593 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
12596 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
12597 int len = GET_RTX_LENGTH (GET_CODE (x));
12602 unsigned int regno = REGNO (x);
12603 unsigned int endregno = END_REGNO (x);
12606 for (j = regno; j < endregno; j++)
12608 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, j);
12609 if (rsp->last_set_invalid
12610 /* If this is a pseudo-register that was only set once and not
12611 live at the beginning of the function, it is always valid. */
12612 || (! (regno >= FIRST_PSEUDO_REGISTER
12613 && REG_N_SETS (regno) == 1
12614 && (!REGNO_REG_SET_P
12615 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno)))
12616 && rsp->last_set_label > tick))
12619 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12626 /* If this is a memory reference, make sure that there were no stores after
12627 it that might have clobbered the value. We don't have alias info, so we
12628 assume any store invalidates it. Moreover, we only have local UIDs, so
12629 we also assume that there were stores in the intervening basic blocks. */
12630 else if (MEM_P (x) && !MEM_READONLY_P (x)
12631 && (tick != label_tick || DF_INSN_LUID (insn) <= mem_last_set))
12634 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12638 for (i = 0; i < len; i++)
12642 /* Check for identical subexpressions. If x contains
12643 identical subexpression we only have to traverse one of
12645 if (i == 1 && ARITHMETIC_P (x))
12647 /* Note that at this point x0 has already been checked
12648 and found valid. */
12649 rtx x0 = XEXP (x, 0);
12650 rtx x1 = XEXP (x, 1);
12652 /* If x0 and x1 are identical then x is also valid. */
12656 /* If x1 is identical to a subexpression of x0 then
12657 while checking x0, x1 has already been checked. Thus
12658 it is valid and so as x. */
12659 if (ARITHMETIC_P (x0)
12660 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12663 /* If x0 is identical to a subexpression of x1 then x is
12664 valid iff the rest of x1 is valid. */
12665 if (ARITHMETIC_P (x1)
12666 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12668 get_last_value_validate (&XEXP (x1,
12669 x0 == XEXP (x1, 0) ? 1 : 0),
12670 insn, tick, replace);
12673 if (get_last_value_validate (&XEXP (x, i), insn, tick,
12677 else if (fmt[i] == 'E')
12678 for (j = 0; j < XVECLEN (x, i); j++)
12679 if (get_last_value_validate (&XVECEXP (x, i, j),
12680 insn, tick, replace) == 0)
12684 /* If we haven't found a reason for it to be invalid, it is valid. */
12688 /* Get the last value assigned to X, if known. Some registers
12689 in the value may be replaced with (clobber (const_int 0)) if their value
12690 is known longer known reliably. */
12693 get_last_value (const_rtx x)
12695 unsigned int regno;
12697 reg_stat_type *rsp;
12699 /* If this is a non-paradoxical SUBREG, get the value of its operand and
12700 then convert it to the desired mode. If this is a paradoxical SUBREG,
12701 we cannot predict what values the "extra" bits might have. */
12702 if (GET_CODE (x) == SUBREG
12703 && subreg_lowpart_p (x)
12704 && (GET_MODE_SIZE (GET_MODE (x))
12705 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
12706 && (value = get_last_value (SUBREG_REG (x))) != 0)
12707 return gen_lowpart (GET_MODE (x), value);
12713 rsp = VEC_index (reg_stat_type, reg_stat, regno);
12714 value = rsp->last_set_value;
12716 /* If we don't have a value, or if it isn't for this basic block and
12717 it's either a hard register, set more than once, or it's a live
12718 at the beginning of the function, return 0.
12720 Because if it's not live at the beginning of the function then the reg
12721 is always set before being used (is never used without being set).
12722 And, if it's set only once, and it's always set before use, then all
12723 uses must have the same last value, even if it's not from this basic
12727 || (rsp->last_set_label < label_tick_ebb_start
12728 && (regno < FIRST_PSEUDO_REGISTER
12729 || REG_N_SETS (regno) != 1
12731 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno))))
12734 /* If the value was set in a later insn than the ones we are processing,
12735 we can't use it even if the register was only set once. */
12736 if (rsp->last_set_label == label_tick
12737 && DF_INSN_LUID (rsp->last_set) >= subst_low_luid)
12740 /* If the value has all its registers valid, return it. */
12741 if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 0))
12744 /* Otherwise, make a copy and replace any invalid register with
12745 (clobber (const_int 0)). If that fails for some reason, return 0. */
12747 value = copy_rtx (value);
12748 if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 1))
12754 /* Return nonzero if expression X refers to a REG or to memory
12755 that is set in an instruction more recent than FROM_LUID. */
12758 use_crosses_set_p (const_rtx x, int from_luid)
12762 enum rtx_code code = GET_CODE (x);
12766 unsigned int regno = REGNO (x);
12767 unsigned endreg = END_REGNO (x);
12769 #ifdef PUSH_ROUNDING
12770 /* Don't allow uses of the stack pointer to be moved,
12771 because we don't know whether the move crosses a push insn. */
12772 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
12775 for (; regno < endreg; regno++)
12777 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
12779 && rsp->last_set_label == label_tick
12780 && DF_INSN_LUID (rsp->last_set) > from_luid)
12786 if (code == MEM && mem_last_set > from_luid)
12789 fmt = GET_RTX_FORMAT (code);
12791 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12796 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12797 if (use_crosses_set_p (XVECEXP (x, i, j), from_luid))
12800 else if (fmt[i] == 'e'
12801 && use_crosses_set_p (XEXP (x, i), from_luid))
12807 /* Define three variables used for communication between the following
12810 static unsigned int reg_dead_regno, reg_dead_endregno;
12811 static int reg_dead_flag;
12813 /* Function called via note_stores from reg_dead_at_p.
12815 If DEST is within [reg_dead_regno, reg_dead_endregno), set
12816 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
12819 reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
12821 unsigned int regno, endregno;
12826 regno = REGNO (dest);
12827 endregno = END_REGNO (dest);
12828 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
12829 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
12832 /* Return nonzero if REG is known to be dead at INSN.
12834 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12835 referencing REG, it is dead. If we hit a SET referencing REG, it is
12836 live. Otherwise, see if it is live or dead at the start of the basic
12837 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12838 must be assumed to be always live. */
12841 reg_dead_at_p (rtx reg, rtx insn)
12846 /* Set variables for reg_dead_at_p_1. */
12847 reg_dead_regno = REGNO (reg);
12848 reg_dead_endregno = END_REGNO (reg);
12852 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
12853 we allow the machine description to decide whether use-and-clobber
12854 patterns are OK. */
12855 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
12857 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12858 if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
12862 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12863 beginning of basic block. */
12864 block = BLOCK_FOR_INSN (insn);
12869 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
12871 return reg_dead_flag == 1 ? 1 : 0;
12873 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
12877 if (insn == BB_HEAD (block))
12880 insn = PREV_INSN (insn);
12883 /* Look at live-in sets for the basic block that we were in. */
12884 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12885 if (REGNO_REG_SET_P (df_get_live_in (block), i))
12891 /* Note hard registers in X that are used. */
12894 mark_used_regs_combine (rtx x)
12896 RTX_CODE code = GET_CODE (x);
12897 unsigned int regno;
12910 case ADDR_DIFF_VEC:
12913 /* CC0 must die in the insn after it is set, so we don't need to take
12914 special note of it here. */
12920 /* If we are clobbering a MEM, mark any hard registers inside the
12921 address as used. */
12922 if (MEM_P (XEXP (x, 0)))
12923 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
12928 /* A hard reg in a wide mode may really be multiple registers.
12929 If so, mark all of them just like the first. */
12930 if (regno < FIRST_PSEUDO_REGISTER)
12932 /* None of this applies to the stack, frame or arg pointers. */
12933 if (regno == STACK_POINTER_REGNUM
12934 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
12935 || regno == HARD_FRAME_POINTER_REGNUM
12937 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12938 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
12940 || regno == FRAME_POINTER_REGNUM)
12943 add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno);
12949 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12951 rtx testreg = SET_DEST (x);
12953 while (GET_CODE (testreg) == SUBREG
12954 || GET_CODE (testreg) == ZERO_EXTRACT
12955 || GET_CODE (testreg) == STRICT_LOW_PART)
12956 testreg = XEXP (testreg, 0);
12958 if (MEM_P (testreg))
12959 mark_used_regs_combine (XEXP (testreg, 0));
12961 mark_used_regs_combine (SET_SRC (x));
12969 /* Recursively scan the operands of this expression. */
12972 const char *fmt = GET_RTX_FORMAT (code);
12974 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12977 mark_used_regs_combine (XEXP (x, i));
12978 else if (fmt[i] == 'E')
12982 for (j = 0; j < XVECLEN (x, i); j++)
12983 mark_used_regs_combine (XVECEXP (x, i, j));
12989 /* Remove register number REGNO from the dead registers list of INSN.
12991 Return the note used to record the death, if there was one. */
12994 remove_death (unsigned int regno, rtx insn)
12996 rtx note = find_regno_note (insn, REG_DEAD, regno);
12999 remove_note (insn, note);
13004 /* For each register (hardware or pseudo) used within expression X, if its
13005 death is in an instruction with luid between FROM_LUID (inclusive) and
13006 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13007 list headed by PNOTES.
13009 That said, don't move registers killed by maybe_kill_insn.
13011 This is done when X is being merged by combination into TO_INSN. These
13012 notes will then be distributed as needed. */
13015 move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx to_insn,
13020 enum rtx_code code = GET_CODE (x);
13024 unsigned int regno = REGNO (x);
13025 rtx where_dead = VEC_index (reg_stat_type, reg_stat, regno)->last_death;
13027 /* Don't move the register if it gets killed in between from and to. */
13028 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
13029 && ! reg_referenced_p (x, maybe_kill_insn))
13033 && BLOCK_FOR_INSN (where_dead) == BLOCK_FOR_INSN (to_insn)
13034 && DF_INSN_LUID (where_dead) >= from_luid
13035 && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn))
13037 rtx note = remove_death (regno, where_dead);
13039 /* It is possible for the call above to return 0. This can occur
13040 when last_death points to I2 or I1 that we combined with.
13041 In that case make a new note.
13043 We must also check for the case where X is a hard register
13044 and NOTE is a death note for a range of hard registers
13045 including X. In that case, we must put REG_DEAD notes for
13046 the remaining registers in place of NOTE. */
13048 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
13049 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
13050 > GET_MODE_SIZE (GET_MODE (x))))
13052 unsigned int deadregno = REGNO (XEXP (note, 0));
13053 unsigned int deadend = END_HARD_REGNO (XEXP (note, 0));
13054 unsigned int ourend = END_HARD_REGNO (x);
13057 for (i = deadregno; i < deadend; i++)
13058 if (i < regno || i >= ourend)
13059 add_reg_note (where_dead, REG_DEAD, regno_reg_rtx[i]);
13062 /* If we didn't find any note, or if we found a REG_DEAD note that
13063 covers only part of the given reg, and we have a multi-reg hard
13064 register, then to be safe we must check for REG_DEAD notes
13065 for each register other than the first. They could have
13066 their own REG_DEAD notes lying around. */
13067 else if ((note == 0
13069 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
13070 < GET_MODE_SIZE (GET_MODE (x)))))
13071 && regno < FIRST_PSEUDO_REGISTER
13072 && hard_regno_nregs[regno][GET_MODE (x)] > 1)
13074 unsigned int ourend = END_HARD_REGNO (x);
13075 unsigned int i, offset;
13079 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
13083 for (i = regno + offset; i < ourend; i++)
13084 move_deaths (regno_reg_rtx[i],
13085 maybe_kill_insn, from_luid, to_insn, &oldnotes);
13088 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
13090 XEXP (note, 1) = *pnotes;
13094 *pnotes = alloc_reg_note (REG_DEAD, x, *pnotes);
13100 else if (GET_CODE (x) == SET)
13102 rtx dest = SET_DEST (x);
13104 move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes);
13106 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13107 that accesses one word of a multi-word item, some
13108 piece of everything register in the expression is used by
13109 this insn, so remove any old death. */
13110 /* ??? So why do we test for equality of the sizes? */
13112 if (GET_CODE (dest) == ZERO_EXTRACT
13113 || GET_CODE (dest) == STRICT_LOW_PART
13114 || (GET_CODE (dest) == SUBREG
13115 && (((GET_MODE_SIZE (GET_MODE (dest))
13116 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
13117 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
13118 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
13120 move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes);
13124 /* If this is some other SUBREG, we know it replaces the entire
13125 value, so use that as the destination. */
13126 if (GET_CODE (dest) == SUBREG)
13127 dest = SUBREG_REG (dest);
13129 /* If this is a MEM, adjust deaths of anything used in the address.
13130 For a REG (the only other possibility), the entire value is
13131 being replaced so the old value is not used in this insn. */
13134 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid,
13139 else if (GET_CODE (x) == CLOBBER)
13142 len = GET_RTX_LENGTH (code);
13143 fmt = GET_RTX_FORMAT (code);
13145 for (i = 0; i < len; i++)
13150 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
13151 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid,
13154 else if (fmt[i] == 'e')
13155 move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes);
13159 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13160 pattern of an insn. X must be a REG. */
13163 reg_bitfield_target_p (rtx x, rtx body)
13167 if (GET_CODE (body) == SET)
13169 rtx dest = SET_DEST (body);
13171 unsigned int regno, tregno, endregno, endtregno;
13173 if (GET_CODE (dest) == ZERO_EXTRACT)
13174 target = XEXP (dest, 0);
13175 else if (GET_CODE (dest) == STRICT_LOW_PART)
13176 target = SUBREG_REG (XEXP (dest, 0));
13180 if (GET_CODE (target) == SUBREG)
13181 target = SUBREG_REG (target);
13183 if (!REG_P (target))
13186 tregno = REGNO (target), regno = REGNO (x);
13187 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
13188 return target == x;
13190 endtregno = end_hard_regno (GET_MODE (target), tregno);
13191 endregno = end_hard_regno (GET_MODE (x), regno);
13193 return endregno > tregno && regno < endtregno;
13196 else if (GET_CODE (body) == PARALLEL)
13197 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
13198 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
13204 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13205 as appropriate. I3 and I2 are the insns resulting from the combination
13206 insns including FROM (I2 may be zero).
13208 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13209 not need REG_DEAD notes because they are being substituted for. This
13210 saves searching in the most common cases.
13212 Each note in the list is either ignored or placed on some insns, depending
13213 on the type of note. */
13216 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
13217 rtx elim_i1, rtx elim_i0)
13219 rtx note, next_note;
13222 for (note = notes; note; note = next_note)
13224 rtx place = 0, place2 = 0;
13226 next_note = XEXP (note, 1);
13227 switch (REG_NOTE_KIND (note))
13231 /* Doesn't matter much where we put this, as long as it's somewhere.
13232 It is preferable to keep these notes on branches, which is most
13233 likely to be i3. */
13237 case REG_NON_LOCAL_GOTO:
13242 gcc_assert (i2 && JUMP_P (i2));
13247 case REG_EH_REGION:
13248 /* These notes must remain with the call or trapping instruction. */
13251 else if (i2 && CALL_P (i2))
13255 gcc_assert (cfun->can_throw_non_call_exceptions);
13256 if (may_trap_p (i3))
13258 else if (i2 && may_trap_p (i2))
13260 /* ??? Otherwise assume we've combined things such that we
13261 can now prove that the instructions can't trap. Drop the
13262 note in this case. */
13268 /* These notes must remain with the call. It should not be
13269 possible for both I2 and I3 to be a call. */
13274 gcc_assert (i2 && CALL_P (i2));
13280 /* Any clobbers for i3 may still exist, and so we must process
13281 REG_UNUSED notes from that insn.
13283 Any clobbers from i2 or i1 can only exist if they were added by
13284 recog_for_combine. In that case, recog_for_combine created the
13285 necessary REG_UNUSED notes. Trying to keep any original
13286 REG_UNUSED notes from these insns can cause incorrect output
13287 if it is for the same register as the original i3 dest.
13288 In that case, we will notice that the register is set in i3,
13289 and then add a REG_UNUSED note for the destination of i3, which
13290 is wrong. However, it is possible to have REG_UNUSED notes from
13291 i2 or i1 for register which were both used and clobbered, so
13292 we keep notes from i2 or i1 if they will turn into REG_DEAD
13295 /* If this register is set or clobbered in I3, put the note there
13296 unless there is one already. */
13297 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
13299 if (from_insn != i3)
13302 if (! (REG_P (XEXP (note, 0))
13303 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
13304 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
13307 /* Otherwise, if this register is used by I3, then this register
13308 now dies here, so we must put a REG_DEAD note here unless there
13310 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
13311 && ! (REG_P (XEXP (note, 0))
13312 ? find_regno_note (i3, REG_DEAD,
13313 REGNO (XEXP (note, 0)))
13314 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
13316 PUT_REG_NOTE_KIND (note, REG_DEAD);
13324 /* These notes say something about results of an insn. We can
13325 only support them if they used to be on I3 in which case they
13326 remain on I3. Otherwise they are ignored.
13328 If the note refers to an expression that is not a constant, we
13329 must also ignore the note since we cannot tell whether the
13330 equivalence is still true. It might be possible to do
13331 slightly better than this (we only have a problem if I2DEST
13332 or I1DEST is present in the expression), but it doesn't
13333 seem worth the trouble. */
13335 if (from_insn == i3
13336 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
13341 /* These notes say something about how a register is used. They must
13342 be present on any use of the register in I2 or I3. */
13343 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
13346 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
13355 case REG_LABEL_TARGET:
13356 case REG_LABEL_OPERAND:
13357 /* This can show up in several ways -- either directly in the
13358 pattern, or hidden off in the constant pool with (or without?)
13359 a REG_EQUAL note. */
13360 /* ??? Ignore the without-reg_equal-note problem for now. */
13361 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
13362 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
13363 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
13364 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
13368 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
13369 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
13370 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
13371 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
13379 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13380 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13382 if (place && JUMP_P (place)
13383 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
13384 && (JUMP_LABEL (place) == NULL
13385 || JUMP_LABEL (place) == XEXP (note, 0)))
13387 rtx label = JUMP_LABEL (place);
13390 JUMP_LABEL (place) = XEXP (note, 0);
13391 else if (LABEL_P (label))
13392 LABEL_NUSES (label)--;
13395 if (place2 && JUMP_P (place2)
13396 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
13397 && (JUMP_LABEL (place2) == NULL
13398 || JUMP_LABEL (place2) == XEXP (note, 0)))
13400 rtx label = JUMP_LABEL (place2);
13403 JUMP_LABEL (place2) = XEXP (note, 0);
13404 else if (LABEL_P (label))
13405 LABEL_NUSES (label)--;
13411 /* This note says something about the value of a register prior
13412 to the execution of an insn. It is too much trouble to see
13413 if the note is still correct in all situations. It is better
13414 to simply delete it. */
13418 /* If we replaced the right hand side of FROM_INSN with a
13419 REG_EQUAL note, the original use of the dying register
13420 will not have been combined into I3 and I2. In such cases,
13421 FROM_INSN is guaranteed to be the first of the combined
13422 instructions, so we simply need to search back before
13423 FROM_INSN for the previous use or set of this register,
13424 then alter the notes there appropriately.
13426 If the register is used as an input in I3, it dies there.
13427 Similarly for I2, if it is nonzero and adjacent to I3.
13429 If the register is not used as an input in either I3 or I2
13430 and it is not one of the registers we were supposed to eliminate,
13431 there are two possibilities. We might have a non-adjacent I2
13432 or we might have somehow eliminated an additional register
13433 from a computation. For example, we might have had A & B where
13434 we discover that B will always be zero. In this case we will
13435 eliminate the reference to A.
13437 In both cases, we must search to see if we can find a previous
13438 use of A and put the death note there. */
13441 && from_insn == i2mod
13442 && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
13447 && CALL_P (from_insn)
13448 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
13450 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
13452 else if (i2 != 0 && next_nonnote_nondebug_insn (i2) == i3
13453 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13455 else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
13457 && reg_overlap_mentioned_p (XEXP (note, 0),
13459 || rtx_equal_p (XEXP (note, 0), elim_i1)
13460 || rtx_equal_p (XEXP (note, 0), elim_i0))
13467 basic_block bb = this_basic_block;
13469 for (tem = PREV_INSN (tem); place == 0; tem = PREV_INSN (tem))
13471 if (!NONDEBUG_INSN_P (tem))
13473 if (tem == BB_HEAD (bb))
13478 /* If the register is being set at TEM, see if that is all
13479 TEM is doing. If so, delete TEM. Otherwise, make this
13480 into a REG_UNUSED note instead. Don't delete sets to
13481 global register vars. */
13482 if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
13483 || !global_regs[REGNO (XEXP (note, 0))])
13484 && reg_set_p (XEXP (note, 0), PATTERN (tem)))
13486 rtx set = single_set (tem);
13487 rtx inner_dest = 0;
13489 rtx cc0_setter = NULL_RTX;
13493 for (inner_dest = SET_DEST (set);
13494 (GET_CODE (inner_dest) == STRICT_LOW_PART
13495 || GET_CODE (inner_dest) == SUBREG
13496 || GET_CODE (inner_dest) == ZERO_EXTRACT);
13497 inner_dest = XEXP (inner_dest, 0))
13500 /* Verify that it was the set, and not a clobber that
13501 modified the register.
13503 CC0 targets must be careful to maintain setter/user
13504 pairs. If we cannot delete the setter due to side
13505 effects, mark the user with an UNUSED note instead
13508 if (set != 0 && ! side_effects_p (SET_SRC (set))
13509 && rtx_equal_p (XEXP (note, 0), inner_dest)
13511 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
13512 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
13513 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
13517 /* Move the notes and links of TEM elsewhere.
13518 This might delete other dead insns recursively.
13519 First set the pattern to something that won't use
13521 rtx old_notes = REG_NOTES (tem);
13523 PATTERN (tem) = pc_rtx;
13524 REG_NOTES (tem) = NULL;
13526 distribute_notes (old_notes, tem, tem, NULL_RTX,
13527 NULL_RTX, NULL_RTX, NULL_RTX);
13528 distribute_links (LOG_LINKS (tem));
13530 SET_INSN_DELETED (tem);
13535 /* Delete the setter too. */
13538 PATTERN (cc0_setter) = pc_rtx;
13539 old_notes = REG_NOTES (cc0_setter);
13540 REG_NOTES (cc0_setter) = NULL;
13542 distribute_notes (old_notes, cc0_setter,
13543 cc0_setter, NULL_RTX,
13544 NULL_RTX, NULL_RTX, NULL_RTX);
13545 distribute_links (LOG_LINKS (cc0_setter));
13547 SET_INSN_DELETED (cc0_setter);
13548 if (cc0_setter == i2)
13555 PUT_REG_NOTE_KIND (note, REG_UNUSED);
13557 /* If there isn't already a REG_UNUSED note, put one
13558 here. Do not place a REG_DEAD note, even if
13559 the register is also used here; that would not
13560 match the algorithm used in lifetime analysis
13561 and can cause the consistency check in the
13562 scheduler to fail. */
13563 if (! find_regno_note (tem, REG_UNUSED,
13564 REGNO (XEXP (note, 0))))
13569 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
13571 && find_reg_fusage (tem, USE, XEXP (note, 0))))
13575 /* If we are doing a 3->2 combination, and we have a
13576 register which formerly died in i3 and was not used
13577 by i2, which now no longer dies in i3 and is used in
13578 i2 but does not die in i2, and place is between i2
13579 and i3, then we may need to move a link from place to
13581 if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2)
13583 && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2)
13584 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13586 rtx links = LOG_LINKS (place);
13587 LOG_LINKS (place) = 0;
13588 distribute_links (links);
13593 if (tem == BB_HEAD (bb))
13599 /* If the register is set or already dead at PLACE, we needn't do
13600 anything with this note if it is still a REG_DEAD note.
13601 We check here if it is set at all, not if is it totally replaced,
13602 which is what `dead_or_set_p' checks, so also check for it being
13605 if (place && REG_NOTE_KIND (note) == REG_DEAD)
13607 unsigned int regno = REGNO (XEXP (note, 0));
13608 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
13610 if (dead_or_set_p (place, XEXP (note, 0))
13611 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
13613 /* Unless the register previously died in PLACE, clear
13614 last_death. [I no longer understand why this is
13616 if (rsp->last_death != place)
13617 rsp->last_death = 0;
13621 rsp->last_death = place;
13623 /* If this is a death note for a hard reg that is occupying
13624 multiple registers, ensure that we are still using all
13625 parts of the object. If we find a piece of the object
13626 that is unused, we must arrange for an appropriate REG_DEAD
13627 note to be added for it. However, we can't just emit a USE
13628 and tag the note to it, since the register might actually
13629 be dead; so we recourse, and the recursive call then finds
13630 the previous insn that used this register. */
13632 if (place && regno < FIRST_PSEUDO_REGISTER
13633 && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
13635 unsigned int endregno = END_HARD_REGNO (XEXP (note, 0));
13639 for (i = regno; i < endregno; i++)
13640 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
13641 && ! find_regno_fusage (place, USE, i))
13642 || dead_or_set_regno_p (place, i))
13647 /* Put only REG_DEAD notes for pieces that are
13648 not already dead or set. */
13650 for (i = regno; i < endregno;
13651 i += hard_regno_nregs[i][reg_raw_mode[i]])
13653 rtx piece = regno_reg_rtx[i];
13654 basic_block bb = this_basic_block;
13656 if (! dead_or_set_p (place, piece)
13657 && ! reg_bitfield_target_p (piece,
13660 rtx new_note = alloc_reg_note (REG_DEAD, piece,
13663 distribute_notes (new_note, place, place,
13664 NULL_RTX, NULL_RTX, NULL_RTX,
13667 else if (! refers_to_regno_p (i, i + 1,
13668 PATTERN (place), 0)
13669 && ! find_regno_fusage (place, USE, i))
13670 for (tem = PREV_INSN (place); ;
13671 tem = PREV_INSN (tem))
13673 if (!NONDEBUG_INSN_P (tem))
13675 if (tem == BB_HEAD (bb))
13679 if (dead_or_set_p (tem, piece)
13680 || reg_bitfield_target_p (piece,
13683 add_reg_note (tem, REG_UNUSED, piece);
13697 /* Any other notes should not be present at this point in the
13699 gcc_unreachable ();
13704 XEXP (note, 1) = REG_NOTES (place);
13705 REG_NOTES (place) = note;
13709 add_reg_note (place2, REG_NOTE_KIND (note), XEXP (note, 0));
13713 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13714 I3, I2, and I1 to new locations. This is also called to add a link
13715 pointing at I3 when I3's destination is changed. */
13718 distribute_links (rtx links)
13720 rtx link, next_link;
13722 for (link = links; link; link = next_link)
13728 next_link = XEXP (link, 1);
13730 /* If the insn that this link points to is a NOTE or isn't a single
13731 set, ignore it. In the latter case, it isn't clear what we
13732 can do other than ignore the link, since we can't tell which
13733 register it was for. Such links wouldn't be used by combine
13736 It is not possible for the destination of the target of the link to
13737 have been changed by combine. The only potential of this is if we
13738 replace I3, I2, and I1 by I3 and I2. But in that case the
13739 destination of I2 also remains unchanged. */
13741 if (NOTE_P (XEXP (link, 0))
13742 || (set = single_set (XEXP (link, 0))) == 0)
13745 reg = SET_DEST (set);
13746 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
13747 || GET_CODE (reg) == STRICT_LOW_PART)
13748 reg = XEXP (reg, 0);
13750 /* A LOG_LINK is defined as being placed on the first insn that uses
13751 a register and points to the insn that sets the register. Start
13752 searching at the next insn after the target of the link and stop
13753 when we reach a set of the register or the end of the basic block.
13755 Note that this correctly handles the link that used to point from
13756 I3 to I2. Also note that not much searching is typically done here
13757 since most links don't point very far away. */
13759 for (insn = NEXT_INSN (XEXP (link, 0));
13760 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
13761 || BB_HEAD (this_basic_block->next_bb) != insn));
13762 insn = NEXT_INSN (insn))
13763 if (DEBUG_INSN_P (insn))
13765 else if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
13767 if (reg_referenced_p (reg, PATTERN (insn)))
13771 else if (CALL_P (insn)
13772 && find_reg_fusage (insn, USE, reg))
13777 else if (INSN_P (insn) && reg_set_p (reg, insn))
13780 /* If we found a place to put the link, place it there unless there
13781 is already a link to the same insn as LINK at that point. */
13787 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
13788 if (XEXP (link2, 0) == XEXP (link, 0))
13793 XEXP (link, 1) = LOG_LINKS (place);
13794 LOG_LINKS (place) = link;
13796 /* Set added_links_insn to the earliest insn we added a
13798 if (added_links_insn == 0
13799 || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place))
13800 added_links_insn = place;
13806 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
13807 Check whether the expression pointer to by LOC is a register or
13808 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
13809 Otherwise return zero. */
13812 unmentioned_reg_p_1 (rtx *loc, void *expr)
13817 && (REG_P (x) || MEM_P (x))
13818 && ! reg_mentioned_p (x, (rtx) expr))
13823 /* Check for any register or memory mentioned in EQUIV that is not
13824 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
13825 of EXPR where some registers may have been replaced by constants. */
13828 unmentioned_reg_p (rtx equiv, rtx expr)
13830 return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
13834 dump_combine_stats (FILE *file)
13838 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13839 combine_attempts, combine_merges, combine_extras, combine_successes);
13843 dump_combine_total_stats (FILE *file)
13847 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13848 total_attempts, total_merges, total_extras, total_successes);
13852 gate_handle_combine (void)
13854 return (optimize > 0);
13857 /* Try combining insns through substitution. */
13858 static unsigned int
13859 rest_of_handle_combine (void)
13861 int rebuild_jump_labels_after_combine;
13863 df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN);
13864 df_note_add_problem ();
13867 regstat_init_n_sets_and_refs ();
13869 rebuild_jump_labels_after_combine
13870 = combine_instructions (get_insns (), max_reg_num ());
13872 /* Combining insns may have turned an indirect jump into a
13873 direct jump. Rebuild the JUMP_LABEL fields of jumping
13875 if (rebuild_jump_labels_after_combine)
13877 timevar_push (TV_JUMP);
13878 rebuild_jump_labels (get_insns ());
13880 timevar_pop (TV_JUMP);
13883 regstat_free_n_sets_and_refs ();
13887 struct rtl_opt_pass pass_combine =
13891 "combine", /* name */
13892 gate_handle_combine, /* gate */
13893 rest_of_handle_combine, /* execute */
13896 0, /* static_pass_number */
13897 TV_COMBINE, /* tv_id */
13898 PROP_cfglayout, /* properties_required */
13899 0, /* properties_provided */
13900 0, /* properties_destroyed */
13901 0, /* todo_flags_start */
13903 TODO_df_finish | TODO_verify_rtl_sharing |
13904 TODO_ggc_collect, /* todo_flags_finish */