1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
38 #include "opcode/mips.h"
42 #define DBG(x) printf x
48 /* Clean up namespace so we can include obj-elf.h too. */
49 static int mips_output_flavor PARAMS ((void));
50 static int mips_output_flavor () { return OUTPUT_FLAVOR; }
51 #undef OBJ_PROCESS_STAB
58 #undef obj_frob_file_after_relocs
59 #undef obj_frob_symbol
61 #undef obj_sec_sym_ok_for_reloc
62 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
65 /* Fix any of them that we actually care about. */
67 #define OUTPUT_FLAVOR mips_output_flavor()
74 #ifndef ECOFF_DEBUGGING
75 #define NO_ECOFF_DEBUGGING
76 #define ECOFF_DEBUGGING 0
81 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
82 static char *mips_regmask_frag;
87 #define PIC_CALL_REG 25
95 #define ILLEGAL_REG (32)
97 /* Allow override of standard little-endian ECOFF format. */
99 #ifndef ECOFF_LITTLE_FORMAT
100 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
103 extern int target_big_endian;
105 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
106 32 bit ABI. This has no meaning for ECOFF.
107 Note that the default is always 32 bit, even if "configured" for
108 64 bit [e.g. --target=mips64-elf]. */
111 /* The default target format to use. */
114 mips_target_format ()
116 switch (OUTPUT_FLAVOR)
118 case bfd_target_aout_flavour:
119 return target_big_endian ? "a.out-mips-big" : "a.out-mips-little";
120 case bfd_target_ecoff_flavour:
121 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
122 case bfd_target_coff_flavour:
124 case bfd_target_elf_flavour:
126 /* This is traditional mips */
127 return (target_big_endian
128 ? (mips_64 ? "elf64-tradbigmips" : "elf32-tradbigmips")
129 : (mips_64 ? "elf64-tradlittlemips" : "elf32-tradlittlemips"));
131 return (target_big_endian
132 ? (mips_64 ? "elf64-bigmips" : "elf32-bigmips")
133 : (mips_64 ? "elf64-littlemips" : "elf32-littlemips"));
141 /* The name of the readonly data section. */
142 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
144 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
146 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
148 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
152 /* This is the set of options which may be modified by the .set
153 pseudo-op. We use a struct so that .set push and .set pop are more
156 struct mips_set_options
158 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
159 if it has not been initialized. Changed by `.set mipsN', and the
160 -mipsN command line option, and the default CPU. */
162 /* Whether we are assembling for the mips16 processor. 0 if we are
163 not, 1 if we are, and -1 if the value has not been initialized.
164 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
165 -nomips16 command line options, and the default CPU. */
167 /* Non-zero if we should not reorder instructions. Changed by `.set
168 reorder' and `.set noreorder'. */
170 /* Non-zero if we should not permit the $at ($1) register to be used
171 in instructions. Changed by `.set at' and `.set noat'. */
173 /* Non-zero if we should warn when a macro instruction expands into
174 more than one machine instruction. Changed by `.set nomacro' and
176 int warn_about_macros;
177 /* Non-zero if we should not move instructions. Changed by `.set
178 move', `.set volatile', `.set nomove', and `.set novolatile'. */
180 /* Non-zero if we should not optimize branches by moving the target
181 of the branch into the delay slot. Actually, we don't perform
182 this optimization anyhow. Changed by `.set bopt' and `.set
185 /* Non-zero if we should not autoextend mips16 instructions.
186 Changed by `.set autoextend' and `.set noautoextend'. */
190 /* This is the struct we use to hold the current set of options. Note
191 that we must set the isa field to ISA_UNKNOWN and the mips16 field to
192 -1 to indicate that they have not been initialized. */
194 static struct mips_set_options mips_opts =
196 ISA_UNKNOWN, -1, 0, 0, 0, 0, 0, 0
199 /* These variables are filled in with the masks of registers used.
200 The object format code reads them and puts them in the appropriate
202 unsigned long mips_gprmask;
203 unsigned long mips_cprmask[4];
205 /* MIPS ISA we are using for this output file. */
206 static int file_mips_isa = ISA_UNKNOWN;
208 /* The argument of the -mcpu= flag. Historical for code generation. */
209 static int mips_cpu = CPU_UNKNOWN;
211 /* The argument of the -march= flag. The architecture we are assembling. */
212 static int mips_arch = CPU_UNKNOWN;
214 /* The argument of the -mtune= flag. The architecture for which we
216 static int mips_tune = CPU_UNKNOWN;
218 /* The argument of the -mabi= flag. */
219 static char * mips_abi_string = NULL;
221 /* Whether we should mark the file EABI64 or EABI32. */
222 static int mips_eabi64 = 0;
224 /* If they asked for mips1 or mips2 and a cpu that is
225 mips3 or greater, then mark the object file 32BITMODE. */
226 static int mips_32bitmode = 0;
228 /* True if -mgp32 was passed. */
229 static int mips_gp32 = 0;
231 /* True if -mfp32 was passed. */
232 static int mips_fp32 = 0;
234 /* True if the selected ABI is defined for 32-bit registers only. */
235 static int mips_32bit_abi = 0;
237 /* Some ISA's have delay slots for instructions which read or write
238 from a coprocessor (eg. mips1-mips3); some don't (eg mips4).
239 Return true if instructions marked INSN_LOAD_COPROC_DELAY,
240 INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a
241 delay slot in this ISA. The uses of this macro assume that any
242 ISA that has delay slots for one of these, has them for all. They
243 also assume that ISAs which don't have delays for these insns, don't
244 have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */
245 #define ISA_HAS_COPROC_DELAYS(ISA) ( \
247 || (ISA) == ISA_MIPS2 \
248 || (ISA) == ISA_MIPS3 \
251 /* Return true if ISA supports 64 bit gp register instructions. */
252 #define ISA_HAS_64BIT_REGS(ISA) ( \
254 || (ISA) == ISA_MIPS4 \
255 || (ISA) == ISA_MIPS5 \
256 || (ISA) == ISA_MIPS64 \
259 #define HAVE_32BIT_GPRS \
262 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
264 #define HAVE_32BIT_FPRS \
267 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
269 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
270 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
272 #define HAVE_32BIT_ADDRESSES \
274 || bfd_arch_bits_per_address (stdoutput) == 32)
276 /* Whether the processor uses hardware interlocks to protect
277 reads from the HI and LO registers, and thus does not
278 require nops to be inserted. */
280 #define hilo_interlocks (mips_arch == CPU_R4010 \
283 /* Whether the processor uses hardware interlocks to protect reads
284 from the GPRs, and thus does not require nops to be inserted. */
285 #define gpr_interlocks \
286 (mips_opts.isa != ISA_MIPS1 \
287 || mips_arch == CPU_R3900)
289 /* As with other "interlocks" this is used by hardware that has FP
290 (co-processor) interlocks. */
291 /* Itbl support may require additional care here. */
292 #define cop_interlocks (mips_arch == CPU_R4300 \
295 /* Is this a mfhi or mflo instruction? */
296 #define MF_HILO_INSN(PINFO) \
297 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
299 /* MIPS PIC level. */
303 /* Do not generate PIC code. */
306 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
307 not sure what it is supposed to do. */
310 /* Generate PIC code as in the SVR4 MIPS ABI. */
313 /* Generate PIC code without using a global offset table: the data
314 segment has a maximum size of 64K, all data references are off
315 the $gp register, and all text references are PC relative. This
316 is used on some embedded systems. */
320 static enum mips_pic_level mips_pic;
322 /* Warn about all NOPS that the assembler generates. */
323 static int warn_nops = 0;
325 /* 1 if we should generate 32 bit offsets from the GP register in
326 SVR4_PIC mode. Currently has no meaning in other modes. */
327 static int mips_big_got;
329 /* 1 if trap instructions should used for overflow rather than break
331 static int mips_trap;
333 /* 1 if double width floating point constants should not be constructed
334 by a assembling two single width halves into two single width floating
335 point registers which just happen to alias the double width destination
336 register. On some architectures this aliasing can be disabled by a bit
337 in the status register, and the setting of this bit cannot be determined
338 automatically at assemble time. */
339 static int mips_disable_float_construction;
341 /* Non-zero if any .set noreorder directives were used. */
343 static int mips_any_noreorder;
345 /* Non-zero if nops should be inserted when the register referenced in
346 an mfhi/mflo instruction is read in the next two instructions. */
347 static int mips_7000_hilo_fix;
349 /* The size of the small data section. */
350 static unsigned int g_switch_value = 8;
351 /* Whether the -G option was used. */
352 static int g_switch_seen = 0;
357 /* If we can determine in advance that GP optimization won't be
358 possible, we can skip the relaxation stuff that tries to produce
359 GP-relative references. This makes delay slot optimization work
362 This function can only provide a guess, but it seems to work for
363 gcc output. It needs to guess right for gcc, otherwise gcc
364 will put what it thinks is a GP-relative instruction in a branch
367 I don't know if a fix is needed for the SVR4_PIC mode. I've only
368 fixed it for the non-PIC mode. KR 95/04/07 */
369 static int nopic_need_relax PARAMS ((symbolS *, int));
371 /* handle of the OPCODE hash table */
372 static struct hash_control *op_hash = NULL;
374 /* The opcode hash table we use for the mips16. */
375 static struct hash_control *mips16_op_hash = NULL;
377 /* This array holds the chars that always start a comment. If the
378 pre-processor is disabled, these aren't very useful */
379 const char comment_chars[] = "#";
381 /* This array holds the chars that only start a comment at the beginning of
382 a line. If the line seems to have the form '# 123 filename'
383 .line and .file directives will appear in the pre-processed output */
384 /* Note that input_file.c hand checks for '#' at the beginning of the
385 first line of the input file. This is because the compiler outputs
386 #NO_APP at the beginning of its output. */
387 /* Also note that C style comments are always supported. */
388 const char line_comment_chars[] = "#";
390 /* This array holds machine specific line separator characters. */
391 const char line_separator_chars[] = ";";
393 /* Chars that can be used to separate mant from exp in floating point nums */
394 const char EXP_CHARS[] = "eE";
396 /* Chars that mean this number is a floating point constant */
399 const char FLT_CHARS[] = "rRsSfFdDxXpP";
401 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
402 changed in read.c . Ideally it shouldn't have to know about it at all,
403 but nothing is ideal around here.
406 static char *insn_error;
408 static int auto_align = 1;
410 /* When outputting SVR4 PIC code, the assembler needs to know the
411 offset in the stack frame from which to restore the $gp register.
412 This is set by the .cprestore pseudo-op, and saved in this
414 static offsetT mips_cprestore_offset = -1;
416 /* This is the register which holds the stack frame, as set by the
417 .frame pseudo-op. This is needed to implement .cprestore. */
418 static int mips_frame_reg = SP;
420 /* To output NOP instructions correctly, we need to keep information
421 about the previous two instructions. */
423 /* Whether we are optimizing. The default value of 2 means to remove
424 unneeded NOPs and swap branch instructions when possible. A value
425 of 1 means to not swap branches. A value of 0 means to always
427 static int mips_optimize = 2;
429 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
430 equivalent to seeing no -g option at all. */
431 static int mips_debug = 0;
433 /* The previous instruction. */
434 static struct mips_cl_insn prev_insn;
436 /* The instruction before prev_insn. */
437 static struct mips_cl_insn prev_prev_insn;
439 /* If we don't want information for prev_insn or prev_prev_insn, we
440 point the insn_mo field at this dummy integer. */
441 static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0 };
443 /* Non-zero if prev_insn is valid. */
444 static int prev_insn_valid;
446 /* The frag for the previous instruction. */
447 static struct frag *prev_insn_frag;
449 /* The offset into prev_insn_frag for the previous instruction. */
450 static long prev_insn_where;
452 /* The reloc type for the previous instruction, if any. */
453 static bfd_reloc_code_real_type prev_insn_reloc_type;
455 /* The reloc for the previous instruction, if any. */
456 static fixS *prev_insn_fixp;
458 /* Non-zero if the previous instruction was in a delay slot. */
459 static int prev_insn_is_delay_slot;
461 /* Non-zero if the previous instruction was in a .set noreorder. */
462 static int prev_insn_unreordered;
464 /* Non-zero if the previous instruction uses an extend opcode (if
466 static int prev_insn_extended;
468 /* Non-zero if the previous previous instruction was in a .set
470 static int prev_prev_insn_unreordered;
472 /* If this is set, it points to a frag holding nop instructions which
473 were inserted before the start of a noreorder section. If those
474 nops turn out to be unnecessary, the size of the frag can be
476 static fragS *prev_nop_frag;
478 /* The number of nop instructions we created in prev_nop_frag. */
479 static int prev_nop_frag_holds;
481 /* The number of nop instructions that we know we need in
483 static int prev_nop_frag_required;
485 /* The number of instructions we've seen since prev_nop_frag. */
486 static int prev_nop_frag_since;
488 /* For ECOFF and ELF, relocations against symbols are done in two
489 parts, with a HI relocation and a LO relocation. Each relocation
490 has only 16 bits of space to store an addend. This means that in
491 order for the linker to handle carries correctly, it must be able
492 to locate both the HI and the LO relocation. This means that the
493 relocations must appear in order in the relocation table.
495 In order to implement this, we keep track of each unmatched HI
496 relocation. We then sort them so that they immediately precede the
497 corresponding LO relocation. */
502 struct mips_hi_fixup *next;
505 /* The section this fixup is in. */
509 /* The list of unmatched HI relocs. */
511 static struct mips_hi_fixup *mips_hi_fixup_list;
513 /* Map normal MIPS register numbers to mips16 register numbers. */
515 #define X ILLEGAL_REG
516 static const int mips32_to_16_reg_map[] =
518 X, X, 2, 3, 4, 5, 6, 7,
519 X, X, X, X, X, X, X, X,
520 0, 1, X, X, X, X, X, X,
521 X, X, X, X, X, X, X, X
525 /* Map mips16 register numbers to normal MIPS register numbers. */
527 static const unsigned int mips16_to_32_reg_map[] =
529 16, 17, 2, 3, 4, 5, 6, 7
532 /* Since the MIPS does not have multiple forms of PC relative
533 instructions, we do not have to do relaxing as is done on other
534 platforms. However, we do have to handle GP relative addressing
535 correctly, which turns out to be a similar problem.
537 Every macro that refers to a symbol can occur in (at least) two
538 forms, one with GP relative addressing and one without. For
539 example, loading a global variable into a register generally uses
540 a macro instruction like this:
542 If i can be addressed off the GP register (this is true if it is in
543 the .sbss or .sdata section, or if it is known to be smaller than
544 the -G argument) this will generate the following instruction:
546 This instruction will use a GPREL reloc. If i can not be addressed
547 off the GP register, the following instruction sequence will be used:
550 In this case the first instruction will have a HI16 reloc, and the
551 second reloc will have a LO16 reloc. Both relocs will be against
554 The issue here is that we may not know whether i is GP addressable
555 until after we see the instruction that uses it. Therefore, we
556 want to be able to choose the final instruction sequence only at
557 the end of the assembly. This is similar to the way other
558 platforms choose the size of a PC relative instruction only at the
561 When generating position independent code we do not use GP
562 addressing in quite the same way, but the issue still arises as
563 external symbols and local symbols must be handled differently.
565 We handle these issues by actually generating both possible
566 instruction sequences. The longer one is put in a frag_var with
567 type rs_machine_dependent. We encode what to do with the frag in
568 the subtype field. We encode (1) the number of existing bytes to
569 replace, (2) the number of new bytes to use, (3) the offset from
570 the start of the existing bytes to the first reloc we must generate
571 (that is, the offset is applied from the start of the existing
572 bytes after they are replaced by the new bytes, if any), (4) the
573 offset from the start of the existing bytes to the second reloc,
574 (5) whether a third reloc is needed (the third reloc is always four
575 bytes after the second reloc), and (6) whether to warn if this
576 variant is used (this is sometimes needed if .set nomacro or .set
577 noat is in effect). All these numbers are reasonably small.
579 Generating two instruction sequences must be handled carefully to
580 ensure that delay slots are handled correctly. Fortunately, there
581 are a limited number of cases. When the second instruction
582 sequence is generated, append_insn is directed to maintain the
583 existing delay slot information, so it continues to apply to any
584 code after the second instruction sequence. This means that the
585 second instruction sequence must not impose any requirements not
586 required by the first instruction sequence.
588 These variant frags are then handled in functions called by the
589 machine independent code. md_estimate_size_before_relax returns
590 the final size of the frag. md_convert_frag sets up the final form
591 of the frag. tc_gen_reloc adjust the first reloc and adds a second
593 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
597 | (((reloc1) + 64) << 9) \
598 | (((reloc2) + 64) << 2) \
599 | ((reloc3) ? (1 << 1) : 0) \
601 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
602 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
603 #define RELAX_RELOC1(i) ((valueT) (((i) >> 9) & 0x7f) - 64)
604 #define RELAX_RELOC2(i) ((valueT) (((i) >> 2) & 0x7f) - 64)
605 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
606 #define RELAX_WARN(i) ((i) & 1)
608 /* For mips16 code, we use an entirely different form of relaxation.
609 mips16 supports two versions of most instructions which take
610 immediate values: a small one which takes some small value, and a
611 larger one which takes a 16 bit value. Since branches also follow
612 this pattern, relaxing these values is required.
614 We can assemble both mips16 and normal MIPS code in a single
615 object. Therefore, we need to support this type of relaxation at
616 the same time that we support the relaxation described above. We
617 use the high bit of the subtype field to distinguish these cases.
619 The information we store for this type of relaxation is the
620 argument code found in the opcode file for this relocation, whether
621 the user explicitly requested a small or extended form, and whether
622 the relocation is in a jump or jal delay slot. That tells us the
623 size of the value, and how it should be stored. We also store
624 whether the fragment is considered to be extended or not. We also
625 store whether this is known to be a branch to a different section,
626 whether we have tried to relax this frag yet, and whether we have
627 ever extended a PC relative fragment because of a shift count. */
628 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
631 | ((small) ? 0x100 : 0) \
632 | ((ext) ? 0x200 : 0) \
633 | ((dslot) ? 0x400 : 0) \
634 | ((jal_dslot) ? 0x800 : 0))
635 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
636 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
637 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
638 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
639 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
640 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
641 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
642 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
643 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
644 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
645 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
646 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
648 /* Prototypes for static functions. */
651 #define internalError() \
652 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
654 #define internalError() as_fatal (_("MIPS internal Error"));
657 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
659 static int insn_uses_reg PARAMS ((struct mips_cl_insn *ip,
660 unsigned int reg, enum mips_regclass class));
661 static int reg_needs_delay PARAMS ((unsigned int));
662 static void mips16_mark_labels PARAMS ((void));
663 static void append_insn PARAMS ((char *place,
664 struct mips_cl_insn * ip,
666 bfd_reloc_code_real_type r,
668 static void mips_no_prev_insn PARAMS ((int));
669 static void mips_emit_delays PARAMS ((boolean));
671 static void macro_build PARAMS ((char *place, int *counter, expressionS * ep,
672 const char *name, const char *fmt,
675 static void macro_build ();
677 static void mips16_macro_build PARAMS ((char *, int *, expressionS *,
678 const char *, const char *,
680 static void macro_build_lui PARAMS ((char *place, int *counter,
681 expressionS * ep, int regnum));
682 static void set_at PARAMS ((int *counter, int reg, int unsignedp));
683 static void check_absolute_expr PARAMS ((struct mips_cl_insn * ip,
685 static void load_register PARAMS ((int *, int, expressionS *, int));
686 static void load_address PARAMS ((int *counter, int reg, expressionS *ep));
687 static void move_register PARAMS ((int *, int, int));
688 static void macro PARAMS ((struct mips_cl_insn * ip));
689 static void mips16_macro PARAMS ((struct mips_cl_insn * ip));
690 #ifdef LOSING_COMPILER
691 static void macro2 PARAMS ((struct mips_cl_insn * ip));
693 static void mips_ip PARAMS ((char *str, struct mips_cl_insn * ip));
694 static void mips16_ip PARAMS ((char *str, struct mips_cl_insn * ip));
695 static void mips16_immed PARAMS ((char *, unsigned int, int, offsetT, boolean,
696 boolean, boolean, unsigned long *,
697 boolean *, unsigned short *));
698 static int my_getSmallExpression PARAMS ((expressionS * ep, char *str));
699 static void my_getExpression PARAMS ((expressionS * ep, char *str));
700 static symbolS *get_symbol PARAMS ((void));
701 static void mips_align PARAMS ((int to, int fill, symbolS *label));
702 static void s_align PARAMS ((int));
703 static void s_change_sec PARAMS ((int));
704 static void s_cons PARAMS ((int));
705 static void s_float_cons PARAMS ((int));
706 static void s_mips_globl PARAMS ((int));
707 static void s_option PARAMS ((int));
708 static void s_mipsset PARAMS ((int));
709 static void s_abicalls PARAMS ((int));
710 static void s_cpload PARAMS ((int));
711 static void s_cprestore PARAMS ((int));
712 static void s_gpword PARAMS ((int));
713 static void s_cpadd PARAMS ((int));
714 static void s_insn PARAMS ((int));
715 static void md_obj_begin PARAMS ((void));
716 static void md_obj_end PARAMS ((void));
717 static long get_number PARAMS ((void));
718 static void s_mips_ent PARAMS ((int));
719 static void s_mips_end PARAMS ((int));
720 static void s_mips_frame PARAMS ((int));
721 static void s_mips_mask PARAMS ((int));
722 static void s_mips_stab PARAMS ((int));
723 static void s_mips_weakext PARAMS ((int));
724 static void s_file PARAMS ((int));
725 static int mips16_extended_frag PARAMS ((fragS *, asection *, long));
726 static const char *mips_isa_to_str PARAMS ((int));
727 static const char *mips_cpu_to_str PARAMS ((int));
728 static int validate_mips_insn PARAMS ((const struct mips_opcode *));
729 static void show PARAMS ((FILE *, char *, int *, int *));
731 /* Return values of my_getSmallExpression() */
744 /* Table and functions used to map between CPU/ISA names, and
745 ISA levels, and CPU numbers. */
749 const char *name; /* CPU or ISA name. */
750 int is_isa; /* Is this an ISA? (If 0, a CPU.) */
751 int isa; /* ISA level. */
752 int cpu; /* CPU number (default CPU if ISA). */
755 static const struct mips_cpu_info *mips_cpu_info_from_name PARAMS ((const char *));
756 static const struct mips_cpu_info *mips_cpu_info_from_isa PARAMS ((int));
757 static const struct mips_cpu_info *mips_cpu_info_from_cpu PARAMS ((int));
761 The following pseudo-ops from the Kane and Heinrich MIPS book
762 should be defined here, but are currently unsupported: .alias,
763 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
765 The following pseudo-ops from the Kane and Heinrich MIPS book are
766 specific to the type of debugging information being generated, and
767 should be defined by the object format: .aent, .begin, .bend,
768 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
771 The following pseudo-ops from the Kane and Heinrich MIPS book are
772 not MIPS CPU specific, but are also not specific to the object file
773 format. This file is probably the best place to define them, but
774 they are not currently supported: .asm0, .endr, .lab, .repeat,
777 static const pseudo_typeS mips_pseudo_table[] =
779 /* MIPS specific pseudo-ops. */
780 {"option", s_option, 0},
781 {"set", s_mipsset, 0},
782 {"rdata", s_change_sec, 'r'},
783 {"sdata", s_change_sec, 's'},
784 {"livereg", s_ignore, 0},
785 {"abicalls", s_abicalls, 0},
786 {"cpload", s_cpload, 0},
787 {"cprestore", s_cprestore, 0},
788 {"gpword", s_gpword, 0},
789 {"cpadd", s_cpadd, 0},
792 /* Relatively generic pseudo-ops that happen to be used on MIPS
794 {"asciiz", stringer, 1},
795 {"bss", s_change_sec, 'b'},
798 {"dword", s_cons, 3},
799 {"weakext", s_mips_weakext, 0},
801 /* These pseudo-ops are defined in read.c, but must be overridden
802 here for one reason or another. */
803 {"align", s_align, 0},
805 {"data", s_change_sec, 'd'},
806 {"double", s_float_cons, 'd'},
807 {"float", s_float_cons, 'f'},
808 {"globl", s_mips_globl, 0},
809 {"global", s_mips_globl, 0},
810 {"hword", s_cons, 1},
815 {"short", s_cons, 1},
816 {"single", s_float_cons, 'f'},
817 {"stabn", s_mips_stab, 'n'},
818 {"text", s_change_sec, 't'},
821 #ifdef MIPS_STABS_ELF
822 { "extern", ecoff_directive_extern, 0},
828 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
830 /* These pseudo-ops should be defined by the object file format.
831 However, a.out doesn't support them, so we have versions here. */
832 {"aent", s_mips_ent, 1},
833 {"bgnb", s_ignore, 0},
834 {"end", s_mips_end, 0},
835 {"endb", s_ignore, 0},
836 {"ent", s_mips_ent, 0},
838 {"fmask", s_mips_mask, 'F'},
839 {"frame", s_mips_frame, 0},
840 {"loc", s_ignore, 0},
841 {"mask", s_mips_mask, 'R'},
842 {"verstamp", s_ignore, 0},
846 extern void pop_insert PARAMS ((const pseudo_typeS *));
851 pop_insert (mips_pseudo_table);
852 if (! ECOFF_DEBUGGING)
853 pop_insert (mips_nonecoff_pseudo_table);
856 /* Symbols labelling the current insn. */
858 struct insn_label_list
860 struct insn_label_list *next;
864 static struct insn_label_list *insn_labels;
865 static struct insn_label_list *free_insn_labels;
867 static void mips_clear_insn_labels PARAMS ((void));
870 mips_clear_insn_labels ()
872 register struct insn_label_list **pl;
874 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
880 static char *expr_end;
882 /* Expressions which appear in instructions. These are set by
885 static expressionS imm_expr;
886 static expressionS offset_expr;
888 /* Relocs associated with imm_expr and offset_expr. */
890 static bfd_reloc_code_real_type imm_reloc;
891 static bfd_reloc_code_real_type offset_reloc;
893 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
895 static boolean imm_unmatched_hi;
897 /* These are set by mips16_ip if an explicit extension is used. */
899 static boolean mips16_small, mips16_ext;
901 #ifdef MIPS_STABS_ELF
902 /* The pdr segment for per procedure frame/regmask info */
908 mips_isa_to_str (isa)
911 const struct mips_cpu_info *ci;
914 ci = mips_cpu_info_from_isa (isa);
918 sprintf (s, "ISA#%d", isa);
923 mips_cpu_to_str (cpu)
926 const struct mips_cpu_info *ci;
929 ci = mips_cpu_info_from_cpu (cpu);
933 sprintf (s, "CPU#%d", cpu);
937 /* This function is called once, at assembler startup time. It should
938 set up all the tables, etc. that the MD part of the assembler will need. */
943 register const char *retval = NULL;
948 int mips_isa_from_cpu;
949 int target_cpu_had_mips16 = 0;
950 const struct mips_cpu_info *ci;
952 /* GP relative stuff not working for PE */
953 if (strncmp (TARGET_OS, "pe", 2) == 0
954 && g_switch_value != 0)
957 as_bad (_("-G not supported in this configuration."));
962 if (strcmp (cpu + (sizeof TARGET_CPU) - 3, "el") == 0)
964 a = xmalloc (sizeof TARGET_CPU);
965 strcpy (a, TARGET_CPU);
966 a[(sizeof TARGET_CPU) - 3] = '\0';
970 if (strncmp (cpu, "mips16", sizeof "mips16" - 1) == 0)
972 target_cpu_had_mips16 = 1;
973 cpu += sizeof "mips16" - 1;
976 if (mips_opts.mips16 < 0)
977 mips_opts.mips16 = target_cpu_had_mips16;
979 /* Backward compatibility for historic -mcpu= option. Check for
980 incompatible options, warn if -mcpu is used. */
981 if (mips_cpu != CPU_UNKNOWN
982 && mips_arch != CPU_UNKNOWN
983 && mips_cpu != mips_arch)
985 as_fatal (_("The -mcpu option can't be used together with -march. "
986 "Use -mtune instead of -mcpu."));
989 if (mips_cpu != CPU_UNKNOWN
990 && mips_tune != CPU_UNKNOWN
991 && mips_cpu != mips_tune)
993 as_fatal (_("The -mcpu option can't be used together with -mtune. "
994 "Use -march instead of -mcpu."));
997 if (mips_arch == CPU_UNKNOWN && mips_cpu != CPU_UNKNOWN)
999 ci = mips_cpu_info_from_cpu (mips_cpu);
1000 assert (ci != NULL);
1001 mips_arch = ci->cpu;
1002 as_warn (_("The -mcpu option is deprecated. Please use -march and "
1003 "-mtune instead."));
1006 /* At this point, mips_arch will either be CPU_UNKNOWN if no ARCH was
1007 specified on the command line, or some other value if one was.
1008 Similarly, mips_opts.isa will be ISA_UNKNOWN if not specified on
1009 the command line, or will be set otherwise if one was. */
1010 if (mips_arch != CPU_UNKNOWN && mips_opts.isa != ISA_UNKNOWN)
1012 /* We have to check if the isa is the default isa of arch. Otherwise
1013 we'll get invalid object file headers. */
1014 ci = mips_cpu_info_from_cpu (mips_arch);
1015 assert (ci != NULL);
1016 if (mips_opts.isa != ci->isa)
1018 /* This really should be an error instead of a warning, but old
1019 compilers only have -mcpu which sets both arch and tune. For
1020 now, we discard arch and preserve tune. */
1021 as_warn (_("The -march option is incompatible to -mipsN and "
1022 "therefore ignored."));
1023 if (mips_tune == CPU_UNKNOWN)
1024 mips_tune = mips_arch;
1025 ci = mips_cpu_info_from_isa (mips_opts.isa);
1026 assert (ci != NULL);
1027 mips_arch = ci->cpu;
1030 else if (mips_arch != CPU_UNKNOWN && mips_opts.isa == ISA_UNKNOWN)
1032 /* We have ARCH, we need ISA. */
1033 ci = mips_cpu_info_from_cpu (mips_arch);
1034 assert (ci != NULL);
1035 mips_opts.isa = ci->isa;
1037 else if (mips_arch == CPU_UNKNOWN && mips_opts.isa != ISA_UNKNOWN)
1039 /* We have ISA, we need default ARCH. */
1040 ci = mips_cpu_info_from_isa (mips_opts.isa);
1041 assert (ci != NULL);
1042 mips_arch = ci->cpu;
1046 /* We need to set both ISA and ARCH from target cpu. */
1047 ci = mips_cpu_info_from_name (cpu);
1049 ci = mips_cpu_info_from_cpu (CPU_R3000);
1050 assert (ci != NULL);
1051 mips_opts.isa = ci->isa;
1052 mips_arch = ci->cpu;
1055 if (mips_tune == CPU_UNKNOWN)
1056 mips_tune = mips_arch;
1058 ci = mips_cpu_info_from_cpu (mips_arch);
1059 assert (ci != NULL);
1060 mips_isa_from_cpu = ci->isa;
1062 /* End of TARGET_CPU processing, get rid of malloced memory
1071 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
1072 as_bad (_("trap exception not supported at ISA 1"));
1074 /* Set the EABI kind based on the ISA before the user gets
1075 to change the ISA with directives. This isn't really
1076 the best, but then neither is basing the abi on the isa. */
1077 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
1079 && 0 == strcmp (mips_abi_string, "eabi"))
1082 /* If they asked for mips1 or mips2 and a cpu that is
1083 mips3 or greater, then mark the object file 32BITMODE. */
1084 if (mips_isa_from_cpu != ISA_UNKNOWN
1085 && ! ISA_HAS_64BIT_REGS (mips_opts.isa)
1086 && ISA_HAS_64BIT_REGS (mips_isa_from_cpu))
1089 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, mips_arch))
1090 as_warn (_("Could not set architecture and machine"));
1092 file_mips_isa = mips_opts.isa;
1094 op_hash = hash_new ();
1096 for (i = 0; i < NUMOPCODES;)
1098 const char *name = mips_opcodes[i].name;
1100 retval = hash_insert (op_hash, name, (PTR) &mips_opcodes[i]);
1103 fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
1104 mips_opcodes[i].name, retval);
1105 /* Probably a memory allocation problem? Give up now. */
1106 as_fatal (_("Broken assembler. No assembly attempted."));
1110 if (mips_opcodes[i].pinfo != INSN_MACRO)
1112 if (!validate_mips_insn (&mips_opcodes[i]))
1117 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
1120 mips16_op_hash = hash_new ();
1123 while (i < bfd_mips16_num_opcodes)
1125 const char *name = mips16_opcodes[i].name;
1127 retval = hash_insert (mips16_op_hash, name, (PTR) &mips16_opcodes[i]);
1129 as_fatal (_("internal: can't hash `%s': %s"),
1130 mips16_opcodes[i].name, retval);
1133 if (mips16_opcodes[i].pinfo != INSN_MACRO
1134 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
1135 != mips16_opcodes[i].match))
1137 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
1138 mips16_opcodes[i].name, mips16_opcodes[i].args);
1143 while (i < bfd_mips16_num_opcodes
1144 && strcmp (mips16_opcodes[i].name, name) == 0);
1148 as_fatal (_("Broken assembler. No assembly attempted."));
1150 /* We add all the general register names to the symbol table. This
1151 helps us detect invalid uses of them. */
1152 for (i = 0; i < 32; i++)
1156 sprintf (buf, "$%d", i);
1157 symbol_table_insert (symbol_new (buf, reg_section, i,
1158 &zero_address_frag));
1160 symbol_table_insert (symbol_new ("$fp", reg_section, FP,
1161 &zero_address_frag));
1162 symbol_table_insert (symbol_new ("$sp", reg_section, SP,
1163 &zero_address_frag));
1164 symbol_table_insert (symbol_new ("$gp", reg_section, GP,
1165 &zero_address_frag));
1166 symbol_table_insert (symbol_new ("$at", reg_section, AT,
1167 &zero_address_frag));
1168 symbol_table_insert (symbol_new ("$kt0", reg_section, KT0,
1169 &zero_address_frag));
1170 symbol_table_insert (symbol_new ("$kt1", reg_section, KT1,
1171 &zero_address_frag));
1172 symbol_table_insert (symbol_new ("$pc", reg_section, -1,
1173 &zero_address_frag));
1175 mips_no_prev_insn (false);
1178 mips_cprmask[0] = 0;
1179 mips_cprmask[1] = 0;
1180 mips_cprmask[2] = 0;
1181 mips_cprmask[3] = 0;
1183 /* set the default alignment for the text section (2**2) */
1184 record_alignment (text_section, 2);
1186 if (USE_GLOBAL_POINTER_OPT)
1187 bfd_set_gp_size (stdoutput, g_switch_value);
1189 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1191 /* On a native system, sections must be aligned to 16 byte
1192 boundaries. When configured for an embedded ELF target, we
1194 if (strcmp (TARGET_OS, "elf") != 0)
1196 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
1197 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
1198 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
1201 /* Create a .reginfo section for register masks and a .mdebug
1202 section for debugging information. */
1210 subseg = now_subseg;
1212 /* The ABI says this section should be loaded so that the
1213 running program can access it. However, we don't load it
1214 if we are configured for an embedded target */
1215 flags = SEC_READONLY | SEC_DATA;
1216 if (strcmp (TARGET_OS, "elf") != 0)
1217 flags |= SEC_ALLOC | SEC_LOAD;
1221 sec = subseg_new (".reginfo", (subsegT) 0);
1223 (void) bfd_set_section_flags (stdoutput, sec, flags);
1224 (void) bfd_set_section_alignment (stdoutput, sec, 2);
1227 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
1232 /* The 64-bit ABI uses a .MIPS.options section rather than
1233 .reginfo section. */
1234 sec = subseg_new (".MIPS.options", (subsegT) 0);
1235 (void) bfd_set_section_flags (stdoutput, sec, flags);
1236 (void) bfd_set_section_alignment (stdoutput, sec, 3);
1239 /* Set up the option header. */
1241 Elf_Internal_Options opthdr;
1244 opthdr.kind = ODK_REGINFO;
1245 opthdr.size = (sizeof (Elf_External_Options)
1246 + sizeof (Elf64_External_RegInfo));
1249 f = frag_more (sizeof (Elf_External_Options));
1250 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
1251 (Elf_External_Options *) f);
1253 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
1258 if (ECOFF_DEBUGGING)
1260 sec = subseg_new (".mdebug", (subsegT) 0);
1261 (void) bfd_set_section_flags (stdoutput, sec,
1262 SEC_HAS_CONTENTS | SEC_READONLY);
1263 (void) bfd_set_section_alignment (stdoutput, sec, 2);
1266 #ifdef MIPS_STABS_ELF
1267 pdr_seg = subseg_new (".pdr", (subsegT) 0);
1268 (void) bfd_set_section_flags (stdoutput, pdr_seg,
1269 SEC_READONLY | SEC_RELOC | SEC_DEBUGGING);
1270 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
1273 subseg_set (seg, subseg);
1277 if (! ECOFF_DEBUGGING)
1284 if (! ECOFF_DEBUGGING)
1292 struct mips_cl_insn insn;
1294 imm_expr.X_op = O_absent;
1295 imm_reloc = BFD_RELOC_UNUSED;
1296 imm_unmatched_hi = false;
1297 offset_expr.X_op = O_absent;
1298 offset_reloc = BFD_RELOC_UNUSED;
1300 if (mips_opts.mips16)
1301 mips16_ip (str, &insn);
1304 mips_ip (str, &insn);
1305 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1306 str, insn.insn_opcode));
1311 as_bad ("%s `%s'", insn_error, str);
1315 if (insn.insn_mo->pinfo == INSN_MACRO)
1317 if (mips_opts.mips16)
1318 mips16_macro (&insn);
1324 if (imm_expr.X_op != O_absent)
1325 append_insn ((char *) NULL, &insn, &imm_expr, imm_reloc,
1327 else if (offset_expr.X_op != O_absent)
1328 append_insn ((char *) NULL, &insn, &offset_expr, offset_reloc, false);
1330 append_insn ((char *) NULL, &insn, NULL, BFD_RELOC_UNUSED, false);
1334 /* See whether instruction IP reads register REG. CLASS is the type
1338 insn_uses_reg (ip, reg, class)
1339 struct mips_cl_insn *ip;
1341 enum mips_regclass class;
1343 if (class == MIPS16_REG)
1345 assert (mips_opts.mips16);
1346 reg = mips16_to_32_reg_map[reg];
1347 class = MIPS_GR_REG;
1350 /* Don't report on general register 0, since it never changes. */
1351 if (class == MIPS_GR_REG && reg == 0)
1354 if (class == MIPS_FP_REG)
1356 assert (! mips_opts.mips16);
1357 /* If we are called with either $f0 or $f1, we must check $f0.
1358 This is not optimal, because it will introduce an unnecessary
1359 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1360 need to distinguish reading both $f0 and $f1 or just one of
1361 them. Note that we don't have to check the other way,
1362 because there is no instruction that sets both $f0 and $f1
1363 and requires a delay. */
1364 if ((ip->insn_mo->pinfo & INSN_READ_FPR_S)
1365 && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1)
1366 == (reg &~ (unsigned) 1)))
1368 if ((ip->insn_mo->pinfo & INSN_READ_FPR_T)
1369 && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1)
1370 == (reg &~ (unsigned) 1)))
1373 else if (! mips_opts.mips16)
1375 if ((ip->insn_mo->pinfo & INSN_READ_GPR_S)
1376 && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg)
1378 if ((ip->insn_mo->pinfo & INSN_READ_GPR_T)
1379 && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg)
1384 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X)
1385 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX)
1386 & MIPS16OP_MASK_RX)]
1389 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y)
1390 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY)
1391 & MIPS16OP_MASK_RY)]
1394 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z)
1395 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
1396 & MIPS16OP_MASK_MOVE32Z)]
1399 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG)
1401 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP)
1403 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA)
1405 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X)
1406 && ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
1407 & MIPS16OP_MASK_REGR32) == reg)
1414 /* This function returns true if modifying a register requires a
1418 reg_needs_delay (reg)
1421 unsigned long prev_pinfo;
1423 prev_pinfo = prev_insn.insn_mo->pinfo;
1424 if (! mips_opts.noreorder
1425 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1426 && ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1427 || (! gpr_interlocks
1428 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))))
1430 /* A load from a coprocessor or from memory. All load
1431 delays delay the use of general register rt for one
1432 instruction on the r3000. The r6000 and r4000 use
1434 /* Itbl support may require additional care here. */
1435 know (prev_pinfo & INSN_WRITE_GPR_T);
1436 if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT))
1443 /* Mark instruction labels in mips16 mode. This permits the linker to
1444 handle them specially, such as generating jalx instructions when
1445 needed. We also make them odd for the duration of the assembly, in
1446 order to generate the right sort of code. We will make them even
1447 in the adjust_symtab routine, while leaving them marked. This is
1448 convenient for the debugger and the disassembler. The linker knows
1449 to make them odd again. */
1452 mips16_mark_labels ()
1454 if (mips_opts.mips16)
1456 struct insn_label_list *l;
1459 for (l = insn_labels; l != NULL; l = l->next)
1462 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1463 S_SET_OTHER (l->label, STO_MIPS16);
1465 val = S_GET_VALUE (l->label);
1467 S_SET_VALUE (l->label, val + 1);
1472 /* Output an instruction. PLACE is where to put the instruction; if
1473 it is NULL, this uses frag_more to get room. IP is the instruction
1474 information. ADDRESS_EXPR is an operand of the instruction to be
1475 used with RELOC_TYPE. */
1478 append_insn (place, ip, address_expr, reloc_type, unmatched_hi)
1480 struct mips_cl_insn *ip;
1481 expressionS *address_expr;
1482 bfd_reloc_code_real_type reloc_type;
1483 boolean unmatched_hi;
1485 register unsigned long prev_pinfo, pinfo;
1490 /* Mark instruction labels in mips16 mode. */
1491 if (mips_opts.mips16)
1492 mips16_mark_labels ();
1494 prev_pinfo = prev_insn.insn_mo->pinfo;
1495 pinfo = ip->insn_mo->pinfo;
1497 if (place == NULL && (! mips_opts.noreorder || prev_nop_frag != NULL))
1501 /* If the previous insn required any delay slots, see if we need
1502 to insert a NOP or two. There are eight kinds of possible
1503 hazards, of which an instruction can have at most one type.
1504 (1) a load from memory delay
1505 (2) a load from a coprocessor delay
1506 (3) an unconditional branch delay
1507 (4) a conditional branch delay
1508 (5) a move to coprocessor register delay
1509 (6) a load coprocessor register from memory delay
1510 (7) a coprocessor condition code delay
1511 (8) a HI/LO special register delay
1513 There are a lot of optimizations we could do that we don't.
1514 In particular, we do not, in general, reorder instructions.
1515 If you use gcc with optimization, it will reorder
1516 instructions and generally do much more optimization then we
1517 do here; repeating all that work in the assembler would only
1518 benefit hand written assembly code, and does not seem worth
1521 /* This is how a NOP is emitted. */
1522 #define emit_nop() \
1524 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1525 : md_number_to_chars (frag_more (4), 0, 4))
1527 /* The previous insn might require a delay slot, depending upon
1528 the contents of the current insn. */
1529 if (! mips_opts.mips16
1530 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1531 && (((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1532 && ! cop_interlocks)
1533 || (! gpr_interlocks
1534 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))))
1536 /* A load from a coprocessor or from memory. All load
1537 delays delay the use of general register rt for one
1538 instruction on the r3000. The r6000 and r4000 use
1540 /* Itbl support may require additional care here. */
1541 know (prev_pinfo & INSN_WRITE_GPR_T);
1542 if (mips_optimize == 0
1543 || insn_uses_reg (ip,
1544 ((prev_insn.insn_opcode >> OP_SH_RT)
1549 else if (! mips_opts.mips16
1550 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1551 && (((prev_pinfo & INSN_COPROC_MOVE_DELAY)
1552 && ! cop_interlocks)
1553 || (mips_opts.isa == ISA_MIPS1
1554 && (prev_pinfo & INSN_COPROC_MEMORY_DELAY))))
1556 /* A generic coprocessor delay. The previous instruction
1557 modified a coprocessor general or control register. If
1558 it modified a control register, we need to avoid any
1559 coprocessor instruction (this is probably not always
1560 required, but it sometimes is). If it modified a general
1561 register, we avoid using that register.
1563 On the r6000 and r4000 loading a coprocessor register
1564 from memory is interlocked, and does not require a delay.
1566 This case is not handled very well. There is no special
1567 knowledge of CP0 handling, and the coprocessors other
1568 than the floating point unit are not distinguished at
1570 /* Itbl support may require additional care here. FIXME!
1571 Need to modify this to include knowledge about
1572 user specified delays! */
1573 if (prev_pinfo & INSN_WRITE_FPR_T)
1575 if (mips_optimize == 0
1576 || insn_uses_reg (ip,
1577 ((prev_insn.insn_opcode >> OP_SH_FT)
1582 else if (prev_pinfo & INSN_WRITE_FPR_S)
1584 if (mips_optimize == 0
1585 || insn_uses_reg (ip,
1586 ((prev_insn.insn_opcode >> OP_SH_FS)
1593 /* We don't know exactly what the previous instruction
1594 does. If the current instruction uses a coprocessor
1595 register, we must insert a NOP. If previous
1596 instruction may set the condition codes, and the
1597 current instruction uses them, we must insert two
1599 /* Itbl support may require additional care here. */
1600 if (mips_optimize == 0
1601 || ((prev_pinfo & INSN_WRITE_COND_CODE)
1602 && (pinfo & INSN_READ_COND_CODE)))
1604 else if (pinfo & INSN_COP)
1608 else if (! mips_opts.mips16
1609 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1610 && (prev_pinfo & INSN_WRITE_COND_CODE)
1611 && ! cop_interlocks)
1613 /* The previous instruction sets the coprocessor condition
1614 codes, but does not require a general coprocessor delay
1615 (this means it is a floating point comparison
1616 instruction). If this instruction uses the condition
1617 codes, we need to insert a single NOP. */
1618 /* Itbl support may require additional care here. */
1619 if (mips_optimize == 0
1620 || (pinfo & INSN_READ_COND_CODE))
1624 /* If we're fixing up mfhi/mflo for the r7000 and the
1625 previous insn was an mfhi/mflo and the current insn
1626 reads the register that the mfhi/mflo wrote to, then
1629 else if (mips_7000_hilo_fix
1630 && MF_HILO_INSN (prev_pinfo)
1631 && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD)
1638 /* If we're fixing up mfhi/mflo for the r7000 and the
1639 2nd previous insn was an mfhi/mflo and the current insn
1640 reads the register that the mfhi/mflo wrote to, then
1643 else if (mips_7000_hilo_fix
1644 && MF_HILO_INSN (prev_prev_insn.insn_opcode)
1645 && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD)
1653 else if (prev_pinfo & INSN_READ_LO)
1655 /* The previous instruction reads the LO register; if the
1656 current instruction writes to the LO register, we must
1657 insert two NOPS. Some newer processors have interlocks.
1658 Also the tx39's multiply instructions can be exectuted
1659 immediatly after a read from HI/LO (without the delay),
1660 though the tx39's divide insns still do require the
1662 if (! (hilo_interlocks
1663 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))
1664 && (mips_optimize == 0
1665 || (pinfo & INSN_WRITE_LO)))
1667 /* Most mips16 branch insns don't have a delay slot.
1668 If a read from LO is immediately followed by a branch
1669 to a write to LO we have a read followed by a write
1670 less than 2 insns away. We assume the target of
1671 a branch might be a write to LO, and insert a nop
1672 between a read and an immediately following branch. */
1673 else if (mips_opts.mips16
1674 && (mips_optimize == 0
1675 || (pinfo & MIPS16_INSN_BRANCH)))
1678 else if (prev_insn.insn_mo->pinfo & INSN_READ_HI)
1680 /* The previous instruction reads the HI register; if the
1681 current instruction writes to the HI register, we must
1682 insert a NOP. Some newer processors have interlocks.
1683 Also the note tx39's multiply above. */
1684 if (! (hilo_interlocks
1685 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))
1686 && (mips_optimize == 0
1687 || (pinfo & INSN_WRITE_HI)))
1689 /* Most mips16 branch insns don't have a delay slot.
1690 If a read from HI is immediately followed by a branch
1691 to a write to HI we have a read followed by a write
1692 less than 2 insns away. We assume the target of
1693 a branch might be a write to HI, and insert a nop
1694 between a read and an immediately following branch. */
1695 else if (mips_opts.mips16
1696 && (mips_optimize == 0
1697 || (pinfo & MIPS16_INSN_BRANCH)))
1701 /* If the previous instruction was in a noreorder section, then
1702 we don't want to insert the nop after all. */
1703 /* Itbl support may require additional care here. */
1704 if (prev_insn_unreordered)
1707 /* There are two cases which require two intervening
1708 instructions: 1) setting the condition codes using a move to
1709 coprocessor instruction which requires a general coprocessor
1710 delay and then reading the condition codes 2) reading the HI
1711 or LO register and then writing to it (except on processors
1712 which have interlocks). If we are not already emitting a NOP
1713 instruction, we must check for these cases compared to the
1714 instruction previous to the previous instruction. */
1715 if ((! mips_opts.mips16
1716 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
1717 && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY)
1718 && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
1719 && (pinfo & INSN_READ_COND_CODE)
1720 && ! cop_interlocks)
1721 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)
1722 && (pinfo & INSN_WRITE_LO)
1723 && ! (hilo_interlocks
1724 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT))))
1725 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
1726 && (pinfo & INSN_WRITE_HI)
1727 && ! (hilo_interlocks
1728 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))))
1733 if (prev_prev_insn_unreordered)
1736 if (prev_prev_nop && nops == 0)
1739 /* If we are being given a nop instruction, don't bother with
1740 one of the nops we would otherwise output. This will only
1741 happen when a nop instruction is used with mips_optimize set
1744 && ! mips_opts.noreorder
1745 && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0))
1748 /* Now emit the right number of NOP instructions. */
1749 if (nops > 0 && ! mips_opts.noreorder)
1752 unsigned long old_frag_offset;
1754 struct insn_label_list *l;
1756 old_frag = frag_now;
1757 old_frag_offset = frag_now_fix ();
1759 for (i = 0; i < nops; i++)
1764 listing_prev_line ();
1765 /* We may be at the start of a variant frag. In case we
1766 are, make sure there is enough space for the frag
1767 after the frags created by listing_prev_line. The
1768 argument to frag_grow here must be at least as large
1769 as the argument to all other calls to frag_grow in
1770 this file. We don't have to worry about being in the
1771 middle of a variant frag, because the variants insert
1772 all needed nop instructions themselves. */
1776 for (l = insn_labels; l != NULL; l = l->next)
1780 assert (S_GET_SEGMENT (l->label) == now_seg);
1781 symbol_set_frag (l->label, frag_now);
1782 val = (valueT) frag_now_fix ();
1783 /* mips16 text labels are stored as odd. */
1784 if (mips_opts.mips16)
1786 S_SET_VALUE (l->label, val);
1789 #ifndef NO_ECOFF_DEBUGGING
1790 if (ECOFF_DEBUGGING)
1791 ecoff_fix_loc (old_frag, old_frag_offset);
1794 else if (prev_nop_frag != NULL)
1796 /* We have a frag holding nops we may be able to remove. If
1797 we don't need any nops, we can decrease the size of
1798 prev_nop_frag by the size of one instruction. If we do
1799 need some nops, we count them in prev_nops_required. */
1800 if (prev_nop_frag_since == 0)
1804 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
1805 --prev_nop_frag_holds;
1808 prev_nop_frag_required += nops;
1812 if (prev_prev_nop == 0)
1814 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
1815 --prev_nop_frag_holds;
1818 ++prev_nop_frag_required;
1821 if (prev_nop_frag_holds <= prev_nop_frag_required)
1822 prev_nop_frag = NULL;
1824 ++prev_nop_frag_since;
1826 /* Sanity check: by the time we reach the second instruction
1827 after prev_nop_frag, we should have used up all the nops
1828 one way or another. */
1829 assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL);
1833 if (reloc_type > BFD_RELOC_UNUSED)
1835 /* We need to set up a variant frag. */
1836 assert (mips_opts.mips16 && address_expr != NULL);
1837 f = frag_var (rs_machine_dependent, 4, 0,
1838 RELAX_MIPS16_ENCODE (reloc_type - BFD_RELOC_UNUSED,
1839 mips16_small, mips16_ext,
1841 & INSN_UNCOND_BRANCH_DELAY),
1842 (prev_insn_reloc_type
1843 == BFD_RELOC_MIPS16_JMP)),
1844 make_expr_symbol (address_expr), (offsetT) 0,
1847 else if (place != NULL)
1849 else if (mips_opts.mips16
1851 && reloc_type != BFD_RELOC_MIPS16_JMP)
1853 /* Make sure there is enough room to swap this instruction with
1854 a following jump instruction. */
1860 if (mips_opts.mips16
1861 && mips_opts.noreorder
1862 && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
1863 as_warn (_("extended instruction in delay slot"));
1869 if (address_expr != NULL && reloc_type < BFD_RELOC_UNUSED)
1871 if (address_expr->X_op == O_constant)
1876 ip->insn_opcode |= address_expr->X_add_number;
1879 case BFD_RELOC_LO16:
1880 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
1883 case BFD_RELOC_MIPS_JMP:
1884 if ((address_expr->X_add_number & 3) != 0)
1885 as_bad (_("jump to misaligned address (0x%lx)"),
1886 (unsigned long) address_expr->X_add_number);
1887 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff;
1890 case BFD_RELOC_MIPS16_JMP:
1891 if ((address_expr->X_add_number & 3) != 0)
1892 as_bad (_("jump to misaligned address (0x%lx)"),
1893 (unsigned long) address_expr->X_add_number);
1895 (((address_expr->X_add_number & 0x7c0000) << 3)
1896 | ((address_expr->X_add_number & 0xf800000) >> 7)
1897 | ((address_expr->X_add_number & 0x3fffc) >> 2));
1900 case BFD_RELOC_16_PCREL:
1901 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
1904 case BFD_RELOC_16_PCREL_S2:
1914 /* Don't generate a reloc if we are writing into a variant
1918 fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 4,
1920 (reloc_type == BFD_RELOC_16_PCREL
1921 || reloc_type == BFD_RELOC_16_PCREL_S2),
1925 struct mips_hi_fixup *hi_fixup;
1927 assert (reloc_type == BFD_RELOC_HI16_S);
1928 hi_fixup = ((struct mips_hi_fixup *)
1929 xmalloc (sizeof (struct mips_hi_fixup)));
1930 hi_fixup->fixp = fixp;
1931 hi_fixup->seg = now_seg;
1932 hi_fixup->next = mips_hi_fixup_list;
1933 mips_hi_fixup_list = hi_fixup;
1939 if (! mips_opts.mips16)
1940 md_number_to_chars (f, ip->insn_opcode, 4);
1941 else if (reloc_type == BFD_RELOC_MIPS16_JMP)
1943 md_number_to_chars (f, ip->insn_opcode >> 16, 2);
1944 md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2);
1950 md_number_to_chars (f, 0xf000 | ip->extend, 2);
1953 md_number_to_chars (f, ip->insn_opcode, 2);
1956 /* Update the register mask information. */
1957 if (! mips_opts.mips16)
1959 if (pinfo & INSN_WRITE_GPR_D)
1960 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD);
1961 if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0)
1962 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT);
1963 if (pinfo & INSN_READ_GPR_S)
1964 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS);
1965 if (pinfo & INSN_WRITE_GPR_31)
1966 mips_gprmask |= 1 << 31;
1967 if (pinfo & INSN_WRITE_FPR_D)
1968 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD);
1969 if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0)
1970 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS);
1971 if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0)
1972 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT);
1973 if ((pinfo & INSN_READ_FPR_R) != 0)
1974 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR);
1975 if (pinfo & INSN_COP)
1977 /* We don't keep enough information to sort these cases out.
1978 The itbl support does keep this information however, although
1979 we currently don't support itbl fprmats as part of the cop
1980 instruction. May want to add this support in the future. */
1982 /* Never set the bit for $0, which is always zero. */
1983 mips_gprmask &= ~1 << 0;
1987 if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X))
1988 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX)
1989 & MIPS16OP_MASK_RX);
1990 if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y))
1991 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY)
1992 & MIPS16OP_MASK_RY);
1993 if (pinfo & MIPS16_INSN_WRITE_Z)
1994 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ)
1995 & MIPS16OP_MASK_RZ);
1996 if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T))
1997 mips_gprmask |= 1 << TREG;
1998 if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP))
1999 mips_gprmask |= 1 << SP;
2000 if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31))
2001 mips_gprmask |= 1 << RA;
2002 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
2003 mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
2004 if (pinfo & MIPS16_INSN_READ_Z)
2005 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
2006 & MIPS16OP_MASK_MOVE32Z);
2007 if (pinfo & MIPS16_INSN_READ_GPR_X)
2008 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
2009 & MIPS16OP_MASK_REGR32);
2012 if (place == NULL && ! mips_opts.noreorder)
2014 /* Filling the branch delay slot is more complex. We try to
2015 switch the branch with the previous instruction, which we can
2016 do if the previous instruction does not set up a condition
2017 that the branch tests and if the branch is not itself the
2018 target of any branch. */
2019 if ((pinfo & INSN_UNCOND_BRANCH_DELAY)
2020 || (pinfo & INSN_COND_BRANCH_DELAY))
2022 if (mips_optimize < 2
2023 /* If we have seen .set volatile or .set nomove, don't
2025 || mips_opts.nomove != 0
2026 /* If we had to emit any NOP instructions, then we
2027 already know we can not swap. */
2029 /* If we don't even know the previous insn, we can not
2031 || ! prev_insn_valid
2032 /* If the previous insn is already in a branch delay
2033 slot, then we can not swap. */
2034 || prev_insn_is_delay_slot
2035 /* If the previous previous insn was in a .set
2036 noreorder, we can't swap. Actually, the MIPS
2037 assembler will swap in this situation. However, gcc
2038 configured -with-gnu-as will generate code like
2044 in which we can not swap the bne and INSN. If gcc is
2045 not configured -with-gnu-as, it does not output the
2046 .set pseudo-ops. We don't have to check
2047 prev_insn_unreordered, because prev_insn_valid will
2048 be 0 in that case. We don't want to use
2049 prev_prev_insn_valid, because we do want to be able
2050 to swap at the start of a function. */
2051 || prev_prev_insn_unreordered
2052 /* If the branch is itself the target of a branch, we
2053 can not swap. We cheat on this; all we check for is
2054 whether there is a label on this instruction. If
2055 there are any branches to anything other than a
2056 label, users must use .set noreorder. */
2057 || insn_labels != NULL
2058 /* If the previous instruction is in a variant frag, we
2059 can not do the swap. This does not apply to the
2060 mips16, which uses variant frags for different
2062 || (! mips_opts.mips16
2063 && prev_insn_frag->fr_type == rs_machine_dependent)
2064 /* If the branch reads the condition codes, we don't
2065 even try to swap, because in the sequence
2070 we can not swap, and I don't feel like handling that
2072 || (! mips_opts.mips16
2073 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2074 && (pinfo & INSN_READ_COND_CODE))
2075 /* We can not swap with an instruction that requires a
2076 delay slot, becase the target of the branch might
2077 interfere with that instruction. */
2078 || (! mips_opts.mips16
2079 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2081 /* Itbl support may require additional care here. */
2082 & (INSN_LOAD_COPROC_DELAY
2083 | INSN_COPROC_MOVE_DELAY
2084 | INSN_WRITE_COND_CODE)))
2085 || (! (hilo_interlocks
2086 || (mips_tune == CPU_R3900 && (pinfo & INSN_MULT)))
2090 || (! mips_opts.mips16
2092 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY))
2093 || (! mips_opts.mips16
2094 && mips_opts.isa == ISA_MIPS1
2095 /* Itbl support may require additional care here. */
2096 && (prev_pinfo & INSN_COPROC_MEMORY_DELAY))
2097 /* We can not swap with a branch instruction. */
2099 & (INSN_UNCOND_BRANCH_DELAY
2100 | INSN_COND_BRANCH_DELAY
2101 | INSN_COND_BRANCH_LIKELY))
2102 /* We do not swap with a trap instruction, since it
2103 complicates trap handlers to have the trap
2104 instruction be in a delay slot. */
2105 || (prev_pinfo & INSN_TRAP)
2106 /* If the branch reads a register that the previous
2107 instruction sets, we can not swap. */
2108 || (! mips_opts.mips16
2109 && (prev_pinfo & INSN_WRITE_GPR_T)
2110 && insn_uses_reg (ip,
2111 ((prev_insn.insn_opcode >> OP_SH_RT)
2114 || (! mips_opts.mips16
2115 && (prev_pinfo & INSN_WRITE_GPR_D)
2116 && insn_uses_reg (ip,
2117 ((prev_insn.insn_opcode >> OP_SH_RD)
2120 || (mips_opts.mips16
2121 && (((prev_pinfo & MIPS16_INSN_WRITE_X)
2122 && insn_uses_reg (ip,
2123 ((prev_insn.insn_opcode
2125 & MIPS16OP_MASK_RX),
2127 || ((prev_pinfo & MIPS16_INSN_WRITE_Y)
2128 && insn_uses_reg (ip,
2129 ((prev_insn.insn_opcode
2131 & MIPS16OP_MASK_RY),
2133 || ((prev_pinfo & MIPS16_INSN_WRITE_Z)
2134 && insn_uses_reg (ip,
2135 ((prev_insn.insn_opcode
2137 & MIPS16OP_MASK_RZ),
2139 || ((prev_pinfo & MIPS16_INSN_WRITE_T)
2140 && insn_uses_reg (ip, TREG, MIPS_GR_REG))
2141 || ((prev_pinfo & MIPS16_INSN_WRITE_31)
2142 && insn_uses_reg (ip, RA, MIPS_GR_REG))
2143 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2144 && insn_uses_reg (ip,
2145 MIPS16OP_EXTRACT_REG32R (prev_insn.
2148 /* If the branch writes a register that the previous
2149 instruction sets, we can not swap (we know that
2150 branches write only to RD or to $31). */
2151 || (! mips_opts.mips16
2152 && (prev_pinfo & INSN_WRITE_GPR_T)
2153 && (((pinfo & INSN_WRITE_GPR_D)
2154 && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)
2155 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2156 || ((pinfo & INSN_WRITE_GPR_31)
2157 && (((prev_insn.insn_opcode >> OP_SH_RT)
2160 || (! mips_opts.mips16
2161 && (prev_pinfo & INSN_WRITE_GPR_D)
2162 && (((pinfo & INSN_WRITE_GPR_D)
2163 && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD)
2164 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2165 || ((pinfo & INSN_WRITE_GPR_31)
2166 && (((prev_insn.insn_opcode >> OP_SH_RD)
2169 || (mips_opts.mips16
2170 && (pinfo & MIPS16_INSN_WRITE_31)
2171 && ((prev_pinfo & MIPS16_INSN_WRITE_31)
2172 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2173 && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode)
2175 /* If the branch writes a register that the previous
2176 instruction reads, we can not swap (we know that
2177 branches only write to RD or to $31). */
2178 || (! mips_opts.mips16
2179 && (pinfo & INSN_WRITE_GPR_D)
2180 && insn_uses_reg (&prev_insn,
2181 ((ip->insn_opcode >> OP_SH_RD)
2184 || (! mips_opts.mips16
2185 && (pinfo & INSN_WRITE_GPR_31)
2186 && insn_uses_reg (&prev_insn, 31, MIPS_GR_REG))
2187 || (mips_opts.mips16
2188 && (pinfo & MIPS16_INSN_WRITE_31)
2189 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
2190 /* If we are generating embedded PIC code, the branch
2191 might be expanded into a sequence which uses $at, so
2192 we can't swap with an instruction which reads it. */
2193 || (mips_pic == EMBEDDED_PIC
2194 && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG))
2195 /* If the previous previous instruction has a load
2196 delay, and sets a register that the branch reads, we
2198 || (! mips_opts.mips16
2199 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2200 /* Itbl support may require additional care here. */
2201 && ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY)
2202 || (! gpr_interlocks
2203 && (prev_prev_insn.insn_mo->pinfo
2204 & INSN_LOAD_MEMORY_DELAY)))
2205 && insn_uses_reg (ip,
2206 ((prev_prev_insn.insn_opcode >> OP_SH_RT)
2209 /* If one instruction sets a condition code and the
2210 other one uses a condition code, we can not swap. */
2211 || ((pinfo & INSN_READ_COND_CODE)
2212 && (prev_pinfo & INSN_WRITE_COND_CODE))
2213 || ((pinfo & INSN_WRITE_COND_CODE)
2214 && (prev_pinfo & INSN_READ_COND_CODE))
2215 /* If the previous instruction uses the PC, we can not
2217 || (mips_opts.mips16
2218 && (prev_pinfo & MIPS16_INSN_READ_PC))
2219 /* If the previous instruction was extended, we can not
2221 || (mips_opts.mips16 && prev_insn_extended)
2222 /* If the previous instruction had a fixup in mips16
2223 mode, we can not swap. This normally means that the
2224 previous instruction was a 4 byte branch anyhow. */
2225 || (mips_opts.mips16 && prev_insn_fixp)
2226 /* If the previous instruction is a sync, sync.l, or
2227 sync.p, we can not swap. */
2228 || (prev_pinfo & INSN_SYNC))
2230 /* We could do even better for unconditional branches to
2231 portions of this object file; we could pick up the
2232 instruction at the destination, put it in the delay
2233 slot, and bump the destination address. */
2235 /* Update the previous insn information. */
2236 prev_prev_insn = *ip;
2237 prev_insn.insn_mo = &dummy_opcode;
2241 /* It looks like we can actually do the swap. */
2242 if (! mips_opts.mips16)
2247 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2248 memcpy (temp, prev_f, 4);
2249 memcpy (prev_f, f, 4);
2250 memcpy (f, temp, 4);
2253 prev_insn_fixp->fx_frag = frag_now;
2254 prev_insn_fixp->fx_where = f - frag_now->fr_literal;
2258 fixp->fx_frag = prev_insn_frag;
2259 fixp->fx_where = prev_insn_where;
2267 assert (prev_insn_fixp == NULL);
2268 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2269 memcpy (temp, prev_f, 2);
2270 memcpy (prev_f, f, 2);
2271 if (reloc_type != BFD_RELOC_MIPS16_JMP)
2273 assert (reloc_type == BFD_RELOC_UNUSED);
2274 memcpy (f, temp, 2);
2278 memcpy (f, f + 2, 2);
2279 memcpy (f + 2, temp, 2);
2283 fixp->fx_frag = prev_insn_frag;
2284 fixp->fx_where = prev_insn_where;
2288 /* Update the previous insn information; leave prev_insn
2290 prev_prev_insn = *ip;
2292 prev_insn_is_delay_slot = 1;
2294 /* If that was an unconditional branch, forget the previous
2295 insn information. */
2296 if (pinfo & INSN_UNCOND_BRANCH_DELAY)
2298 prev_prev_insn.insn_mo = &dummy_opcode;
2299 prev_insn.insn_mo = &dummy_opcode;
2302 prev_insn_fixp = NULL;
2303 prev_insn_reloc_type = BFD_RELOC_UNUSED;
2304 prev_insn_extended = 0;
2306 else if (pinfo & INSN_COND_BRANCH_LIKELY)
2308 /* We don't yet optimize a branch likely. What we should do
2309 is look at the target, copy the instruction found there
2310 into the delay slot, and increment the branch to jump to
2311 the next instruction. */
2313 /* Update the previous insn information. */
2314 prev_prev_insn = *ip;
2315 prev_insn.insn_mo = &dummy_opcode;
2316 prev_insn_fixp = NULL;
2317 prev_insn_reloc_type = BFD_RELOC_UNUSED;
2318 prev_insn_extended = 0;
2322 /* Update the previous insn information. */
2324 prev_prev_insn.insn_mo = &dummy_opcode;
2326 prev_prev_insn = prev_insn;
2329 /* Any time we see a branch, we always fill the delay slot
2330 immediately; since this insn is not a branch, we know it
2331 is not in a delay slot. */
2332 prev_insn_is_delay_slot = 0;
2334 prev_insn_fixp = fixp;
2335 prev_insn_reloc_type = reloc_type;
2336 if (mips_opts.mips16)
2337 prev_insn_extended = (ip->use_extend
2338 || reloc_type > BFD_RELOC_UNUSED);
2341 prev_prev_insn_unreordered = prev_insn_unreordered;
2342 prev_insn_unreordered = 0;
2343 prev_insn_frag = frag_now;
2344 prev_insn_where = f - frag_now->fr_literal;
2345 prev_insn_valid = 1;
2347 else if (place == NULL)
2349 /* We need to record a bit of information even when we are not
2350 reordering, in order to determine the base address for mips16
2351 PC relative relocs. */
2352 prev_prev_insn = prev_insn;
2354 prev_insn_reloc_type = reloc_type;
2355 prev_prev_insn_unreordered = prev_insn_unreordered;
2356 prev_insn_unreordered = 1;
2359 /* We just output an insn, so the next one doesn't have a label. */
2360 mips_clear_insn_labels ();
2362 /* We must ensure that a fixup associated with an unmatched %hi
2363 reloc does not become a variant frag. Otherwise, the
2364 rearrangement of %hi relocs in frob_file may confuse
2368 frag_wane (frag_now);
2373 /* This function forgets that there was any previous instruction or
2374 label. If PRESERVE is non-zero, it remembers enough information to
2375 know whether nops are needed before a noreorder section. */
2378 mips_no_prev_insn (preserve)
2383 prev_insn.insn_mo = &dummy_opcode;
2384 prev_prev_insn.insn_mo = &dummy_opcode;
2385 prev_nop_frag = NULL;
2386 prev_nop_frag_holds = 0;
2387 prev_nop_frag_required = 0;
2388 prev_nop_frag_since = 0;
2390 prev_insn_valid = 0;
2391 prev_insn_is_delay_slot = 0;
2392 prev_insn_unreordered = 0;
2393 prev_insn_extended = 0;
2394 prev_insn_reloc_type = BFD_RELOC_UNUSED;
2395 prev_prev_insn_unreordered = 0;
2396 mips_clear_insn_labels ();
2399 /* This function must be called whenever we turn on noreorder or emit
2400 something other than instructions. It inserts any NOPS which might
2401 be needed by the previous instruction, and clears the information
2402 kept for the previous instructions. The INSNS parameter is true if
2403 instructions are to follow. */
2406 mips_emit_delays (insns)
2409 if (! mips_opts.noreorder)
2414 if ((! mips_opts.mips16
2415 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2416 && (! cop_interlocks
2417 && (prev_insn.insn_mo->pinfo
2418 & (INSN_LOAD_COPROC_DELAY
2419 | INSN_COPROC_MOVE_DELAY
2420 | INSN_WRITE_COND_CODE))))
2421 || (! hilo_interlocks
2422 && (prev_insn.insn_mo->pinfo
2425 || (! mips_opts.mips16
2427 && (prev_insn.insn_mo->pinfo
2428 & INSN_LOAD_MEMORY_DELAY))
2429 || (! mips_opts.mips16
2430 && mips_opts.isa == ISA_MIPS1
2431 && (prev_insn.insn_mo->pinfo
2432 & INSN_COPROC_MEMORY_DELAY)))
2434 /* Itbl support may require additional care here. */
2436 if ((! mips_opts.mips16
2437 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2438 && (! cop_interlocks
2439 && prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE))
2440 || (! hilo_interlocks
2441 && ((prev_insn.insn_mo->pinfo & INSN_READ_HI)
2442 || (prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2445 if (prev_insn_unreordered)
2448 else if ((! mips_opts.mips16
2449 && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
2450 && (! cop_interlocks
2451 && prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE))
2452 || (! hilo_interlocks
2453 && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
2454 || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2456 /* Itbl support may require additional care here. */
2457 if (! prev_prev_insn_unreordered)
2463 struct insn_label_list *l;
2467 /* Record the frag which holds the nop instructions, so
2468 that we can remove them if we don't need them. */
2469 frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4);
2470 prev_nop_frag = frag_now;
2471 prev_nop_frag_holds = nops;
2472 prev_nop_frag_required = 0;
2473 prev_nop_frag_since = 0;
2476 for (; nops > 0; --nops)
2481 /* Move on to a new frag, so that it is safe to simply
2482 decrease the size of prev_nop_frag. */
2483 frag_wane (frag_now);
2487 for (l = insn_labels; l != NULL; l = l->next)
2491 assert (S_GET_SEGMENT (l->label) == now_seg);
2492 symbol_set_frag (l->label, frag_now);
2493 val = (valueT) frag_now_fix ();
2494 /* mips16 text labels are stored as odd. */
2495 if (mips_opts.mips16)
2497 S_SET_VALUE (l->label, val);
2502 /* Mark instruction labels in mips16 mode. */
2503 if (mips_opts.mips16 && insns)
2504 mips16_mark_labels ();
2506 mips_no_prev_insn (insns);
2509 /* Build an instruction created by a macro expansion. This is passed
2510 a pointer to the count of instructions created so far, an
2511 expression, the name of the instruction to build, an operand format
2512 string, and corresponding arguments. */
2516 macro_build (char *place,
2524 macro_build (place, counter, ep, name, fmt, va_alist)
2533 struct mips_cl_insn insn;
2534 bfd_reloc_code_real_type r;
2538 va_start (args, fmt);
2544 * If the macro is about to expand into a second instruction,
2545 * print a warning if needed. We need to pass ip as a parameter
2546 * to generate a better warning message here...
2548 if (mips_opts.warn_about_macros && place == NULL && *counter == 1)
2549 as_warn (_("Macro instruction expanded into multiple instructions"));
2552 *counter += 1; /* bump instruction counter */
2554 if (mips_opts.mips16)
2556 mips16_macro_build (place, counter, ep, name, fmt, args);
2561 r = BFD_RELOC_UNUSED;
2562 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
2563 assert (insn.insn_mo);
2564 assert (strcmp (name, insn.insn_mo->name) == 0);
2566 /* Search until we get a match for NAME. */
2569 if (strcmp (fmt, insn.insn_mo->args) == 0
2570 && insn.insn_mo->pinfo != INSN_MACRO
2571 && OPCODE_IS_MEMBER (insn.insn_mo, mips_opts.isa, mips_arch)
2572 && (mips_arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0))
2576 assert (insn.insn_mo->name);
2577 assert (strcmp (name, insn.insn_mo->name) == 0);
2580 insn.insn_opcode = insn.insn_mo->match;
2596 insn.insn_opcode |= va_arg (args, int) << OP_SH_RT;
2600 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE;
2605 insn.insn_opcode |= va_arg (args, int) << OP_SH_FT;
2610 insn.insn_opcode |= va_arg (args, int) << OP_SH_RD;
2615 int tmp = va_arg (args, int);
2617 insn.insn_opcode |= tmp << OP_SH_RT;
2618 insn.insn_opcode |= tmp << OP_SH_RD;
2624 insn.insn_opcode |= va_arg (args, int) << OP_SH_FS;
2631 insn.insn_opcode |= va_arg (args, int) << OP_SH_SHAMT;
2635 insn.insn_opcode |= va_arg (args, int) << OP_SH_FD;
2639 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE20;
2643 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE19;
2647 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE2;
2654 insn.insn_opcode |= va_arg (args, int) << OP_SH_RS;
2660 r = (bfd_reloc_code_real_type) va_arg (args, int);
2661 assert (r == BFD_RELOC_MIPS_GPREL
2662 || r == BFD_RELOC_MIPS_LITERAL
2663 || r == BFD_RELOC_LO16
2664 || r == BFD_RELOC_MIPS_GOT16
2665 || r == BFD_RELOC_MIPS_CALL16
2666 || r == BFD_RELOC_MIPS_GOT_LO16
2667 || r == BFD_RELOC_MIPS_CALL_LO16
2668 || (ep->X_op == O_subtract
2669 && r == BFD_RELOC_PCREL_LO16));
2673 r = (bfd_reloc_code_real_type) va_arg (args, int);
2675 && (ep->X_op == O_constant
2676 || (ep->X_op == O_symbol
2677 && (r == BFD_RELOC_HI16_S
2678 || r == BFD_RELOC_HI16
2679 || r == BFD_RELOC_MIPS_GOT_HI16
2680 || r == BFD_RELOC_MIPS_CALL_HI16))
2681 || (ep->X_op == O_subtract
2682 && r == BFD_RELOC_PCREL_HI16_S)));
2683 if (ep->X_op == O_constant)
2685 insn.insn_opcode |= (ep->X_add_number >> 16) & 0xffff;
2687 r = BFD_RELOC_UNUSED;
2692 assert (ep != NULL);
2694 * This allows macro() to pass an immediate expression for
2695 * creating short branches without creating a symbol.
2696 * Note that the expression still might come from the assembly
2697 * input, in which case the value is not checked for range nor
2698 * is a relocation entry generated (yuck).
2700 if (ep->X_op == O_constant)
2702 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
2706 if (mips_pic == EMBEDDED_PIC)
2707 r = BFD_RELOC_16_PCREL_S2;
2709 r = BFD_RELOC_16_PCREL;
2713 assert (ep != NULL);
2714 r = BFD_RELOC_MIPS_JMP;
2718 insn.insn_opcode |= va_arg (args, unsigned long);
2727 assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
2729 append_insn (place, &insn, ep, r, false);
2733 mips16_macro_build (place, counter, ep, name, fmt, args)
2735 int *counter ATTRIBUTE_UNUSED;
2741 struct mips_cl_insn insn;
2742 bfd_reloc_code_real_type r;
2744 r = BFD_RELOC_UNUSED;
2745 insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
2746 assert (insn.insn_mo);
2747 assert (strcmp (name, insn.insn_mo->name) == 0);
2749 while (strcmp (fmt, insn.insn_mo->args) != 0
2750 || insn.insn_mo->pinfo == INSN_MACRO)
2753 assert (insn.insn_mo->name);
2754 assert (strcmp (name, insn.insn_mo->name) == 0);
2757 insn.insn_opcode = insn.insn_mo->match;
2758 insn.use_extend = false;
2777 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY;
2782 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX;
2786 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ;
2790 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z;
2800 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32;
2807 regno = va_arg (args, int);
2808 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
2809 insn.insn_opcode |= regno << MIPS16OP_SH_REG32R;
2830 assert (ep != NULL);
2832 if (ep->X_op != O_constant)
2833 r = BFD_RELOC_UNUSED + c;
2836 mips16_immed ((char *) NULL, 0, c, ep->X_add_number, false,
2837 false, false, &insn.insn_opcode,
2838 &insn.use_extend, &insn.extend);
2840 r = BFD_RELOC_UNUSED;
2846 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6;
2853 assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
2855 append_insn (place, &insn, ep, r, false);
2859 * Generate a "lui" instruction.
2862 macro_build_lui (place, counter, ep, regnum)
2868 expressionS high_expr;
2869 struct mips_cl_insn insn;
2870 bfd_reloc_code_real_type r;
2871 CONST char *name = "lui";
2872 CONST char *fmt = "t,u";
2874 assert (! mips_opts.mips16);
2880 high_expr.X_op = O_constant;
2881 high_expr.X_add_number = ep->X_add_number;
2884 if (high_expr.X_op == O_constant)
2886 /* we can compute the instruction now without a relocation entry */
2887 high_expr.X_add_number = ((high_expr.X_add_number + 0x8000)
2889 r = BFD_RELOC_UNUSED;
2893 assert (ep->X_op == O_symbol);
2894 /* _gp_disp is a special case, used from s_cpload. */
2895 assert (mips_pic == NO_PIC
2896 || strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0);
2897 r = BFD_RELOC_HI16_S;
2901 * If the macro is about to expand into a second instruction,
2902 * print a warning if needed. We need to pass ip as a parameter
2903 * to generate a better warning message here...
2905 if (mips_opts.warn_about_macros && place == NULL && *counter == 1)
2906 as_warn (_("Macro instruction expanded into multiple instructions"));
2909 *counter += 1; /* bump instruction counter */
2911 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
2912 assert (insn.insn_mo);
2913 assert (strcmp (name, insn.insn_mo->name) == 0);
2914 assert (strcmp (fmt, insn.insn_mo->args) == 0);
2916 insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT);
2917 if (r == BFD_RELOC_UNUSED)
2919 insn.insn_opcode |= high_expr.X_add_number;
2920 append_insn (place, &insn, NULL, r, false);
2923 append_insn (place, &insn, &high_expr, r, false);
2927 * Generates code to set the $at register to true (one)
2928 * if reg is less than the immediate expression.
2931 set_at (counter, reg, unsignedp)
2936 if (imm_expr.X_op == O_constant
2937 && imm_expr.X_add_number >= -0x8000
2938 && imm_expr.X_add_number < 0x8000)
2939 macro_build ((char *) NULL, counter, &imm_expr,
2940 unsignedp ? "sltiu" : "slti",
2941 "t,r,j", AT, reg, (int) BFD_RELOC_LO16);
2944 load_register (counter, AT, &imm_expr, 0);
2945 macro_build ((char *) NULL, counter, NULL,
2946 unsignedp ? "sltu" : "slt",
2947 "d,v,t", AT, reg, AT);
2951 /* Warn if an expression is not a constant. */
2954 check_absolute_expr (ip, ex)
2955 struct mips_cl_insn *ip;
2958 if (ex->X_op == O_big)
2959 as_bad (_("unsupported large constant"));
2960 else if (ex->X_op != O_constant)
2961 as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name);
2964 /* Count the leading zeroes by performing a binary chop. This is a
2965 bulky bit of source, but performance is a LOT better for the
2966 majority of values than a simple loop to count the bits:
2967 for (lcnt = 0; (lcnt < 32); lcnt++)
2968 if ((v) & (1 << (31 - lcnt)))
2970 However it is not code size friendly, and the gain will drop a bit
2971 on certain cached systems.
2973 #define COUNT_TOP_ZEROES(v) \
2974 (((v) & ~0xffff) == 0 \
2975 ? ((v) & ~0xff) == 0 \
2976 ? ((v) & ~0xf) == 0 \
2977 ? ((v) & ~0x3) == 0 \
2978 ? ((v) & ~0x1) == 0 \
2983 : ((v) & ~0x7) == 0 \
2986 : ((v) & ~0x3f) == 0 \
2987 ? ((v) & ~0x1f) == 0 \
2990 : ((v) & ~0x7f) == 0 \
2993 : ((v) & ~0xfff) == 0 \
2994 ? ((v) & ~0x3ff) == 0 \
2995 ? ((v) & ~0x1ff) == 0 \
2998 : ((v) & ~0x7ff) == 0 \
3001 : ((v) & ~0x3fff) == 0 \
3002 ? ((v) & ~0x1fff) == 0 \
3005 : ((v) & ~0x7fff) == 0 \
3008 : ((v) & ~0xffffff) == 0 \
3009 ? ((v) & ~0xfffff) == 0 \
3010 ? ((v) & ~0x3ffff) == 0 \
3011 ? ((v) & ~0x1ffff) == 0 \
3014 : ((v) & ~0x7ffff) == 0 \
3017 : ((v) & ~0x3fffff) == 0 \
3018 ? ((v) & ~0x1fffff) == 0 \
3021 : ((v) & ~0x7fffff) == 0 \
3024 : ((v) & ~0xfffffff) == 0 \
3025 ? ((v) & ~0x3ffffff) == 0 \
3026 ? ((v) & ~0x1ffffff) == 0 \
3029 : ((v) & ~0x7ffffff) == 0 \
3032 : ((v) & ~0x3fffffff) == 0 \
3033 ? ((v) & ~0x1fffffff) == 0 \
3036 : ((v) & ~0x7fffffff) == 0 \
3041 * This routine generates the least number of instructions neccessary to load
3042 * an absolute expression value into a register.
3045 load_register (counter, reg, ep, dbl)
3052 expressionS hi32, lo32;
3054 if (ep->X_op != O_big)
3056 assert (ep->X_op == O_constant);
3057 if (ep->X_add_number < 0x8000
3058 && (ep->X_add_number >= 0
3059 || (ep->X_add_number >= -0x8000
3062 || sizeof (ep->X_add_number) > 4))))
3064 /* We can handle 16 bit signed values with an addiu to
3065 $zero. No need to ever use daddiu here, since $zero and
3066 the result are always correct in 32 bit mode. */
3067 macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0,
3068 (int) BFD_RELOC_LO16);
3071 else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
3073 /* We can handle 16 bit unsigned values with an ori to
3075 macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, 0,
3076 (int) BFD_RELOC_LO16);
3079 else if ((((ep->X_add_number &~ (offsetT) 0x7fffffff) == 0
3080 || ((ep->X_add_number &~ (offsetT) 0x7fffffff)
3081 == ~ (offsetT) 0x7fffffff))
3084 || sizeof (ep->X_add_number) > 4
3085 || (ep->X_add_number & 0x80000000) == 0))
3086 || ((HAVE_32BIT_GPRS || ! dbl)
3087 && (ep->X_add_number &~ (offsetT) 0xffffffff) == 0)
3090 && ((ep->X_add_number &~ (offsetT) 0xffffffff)
3091 == ~ (offsetT) 0xffffffff)))
3093 /* 32 bit values require an lui. */
3094 macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg,
3095 (int) BFD_RELOC_HI16);
3096 if ((ep->X_add_number & 0xffff) != 0)
3097 macro_build ((char *) NULL, counter, ep, "ori", "t,r,i", reg, reg,
3098 (int) BFD_RELOC_LO16);
3103 /* The value is larger than 32 bits. */
3105 if (HAVE_32BIT_GPRS)
3107 as_bad (_("Number larger than 32 bits"));
3108 macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0,
3109 (int) BFD_RELOC_LO16);
3113 if (ep->X_op != O_big)
3116 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3117 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
3118 hi32.X_add_number &= 0xffffffff;
3120 lo32.X_add_number &= 0xffffffff;
3124 assert (ep->X_add_number > 2);
3125 if (ep->X_add_number == 3)
3126 generic_bignum[3] = 0;
3127 else if (ep->X_add_number > 4)
3128 as_bad (_("Number larger than 64 bits"));
3129 lo32.X_op = O_constant;
3130 lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
3131 hi32.X_op = O_constant;
3132 hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
3135 if (hi32.X_add_number == 0)
3140 unsigned long hi, lo;
3142 if (hi32.X_add_number == 0xffffffff)
3144 if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
3146 macro_build ((char *) NULL, counter, &lo32, "addiu", "t,r,j",
3147 reg, 0, (int) BFD_RELOC_LO16);
3150 if (lo32.X_add_number & 0x80000000)
3152 macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg,
3153 (int) BFD_RELOC_HI16);
3154 if (lo32.X_add_number & 0xffff)
3155 macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i",
3156 reg, reg, (int) BFD_RELOC_LO16);
3161 /* Check for 16bit shifted constant. We know that hi32 is
3162 non-zero, so start the mask on the first bit of the hi32
3167 unsigned long himask, lomask;
3171 himask = 0xffff >> (32 - shift);
3172 lomask = (0xffff << shift) & 0xffffffff;
3176 himask = 0xffff << (shift - 32);
3179 if ((hi32.X_add_number & ~(offsetT) himask) == 0
3180 && (lo32.X_add_number & ~(offsetT) lomask) == 0)
3184 tmp.X_op = O_constant;
3186 tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
3187 | (lo32.X_add_number >> shift));
3189 tmp.X_add_number = hi32.X_add_number >> (shift - 32);
3190 macro_build ((char *) NULL, counter, &tmp,
3191 "ori", "t,r,i", reg, 0,
3192 (int) BFD_RELOC_LO16);
3193 macro_build ((char *) NULL, counter, NULL,
3194 (shift >= 32) ? "dsll32" : "dsll",
3196 (shift >= 32) ? shift - 32 : shift);
3201 while (shift <= (64 - 16));
3203 /* Find the bit number of the lowest one bit, and store the
3204 shifted value in hi/lo. */
3205 hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
3206 lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
3210 while ((lo & 1) == 0)
3215 lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
3221 while ((hi & 1) == 0)
3230 /* Optimize if the shifted value is a (power of 2) - 1. */
3231 if ((hi == 0 && ((lo + 1) & lo) == 0)
3232 || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
3234 shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
3239 /* This instruction will set the register to be all
3241 tmp.X_op = O_constant;
3242 tmp.X_add_number = (offsetT) -1;
3243 macro_build ((char *) NULL, counter, &tmp, "addiu", "t,r,j",
3244 reg, 0, (int) BFD_RELOC_LO16);
3248 macro_build ((char *) NULL, counter, NULL,
3249 (bit >= 32) ? "dsll32" : "dsll",
3251 (bit >= 32) ? bit - 32 : bit);
3253 macro_build ((char *) NULL, counter, NULL,
3254 (shift >= 32) ? "dsrl32" : "dsrl",
3256 (shift >= 32) ? shift - 32 : shift);
3261 /* Sign extend hi32 before calling load_register, because we can
3262 generally get better code when we load a sign extended value. */
3263 if ((hi32.X_add_number & 0x80000000) != 0)
3264 hi32.X_add_number |= ~(offsetT) 0xffffffff;
3265 load_register (counter, reg, &hi32, 0);
3268 if ((lo32.X_add_number & 0xffff0000) == 0)
3272 macro_build ((char *) NULL, counter, NULL, "dsll32", "d,w,<", reg,
3281 if ((freg == 0) && (lo32.X_add_number == 0xffffffff))
3283 macro_build ((char *) NULL, counter, &lo32, "lui", "t,u", reg,
3284 (int) BFD_RELOC_HI16);
3285 macro_build ((char *) NULL, counter, NULL, "dsrl32", "d,w,<", reg,
3292 macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg,
3297 mid16.X_add_number >>= 16;
3298 macro_build ((char *) NULL, counter, &mid16, "ori", "t,r,i", reg,
3299 freg, (int) BFD_RELOC_LO16);
3300 macro_build ((char *) NULL, counter, NULL, "dsll", "d,w,<", reg,
3304 if ((lo32.X_add_number & 0xffff) != 0)
3305 macro_build ((char *) NULL, counter, &lo32, "ori", "t,r,i", reg, freg,
3306 (int) BFD_RELOC_LO16);
3309 /* Load an address into a register. */
3312 load_address (counter, reg, ep)
3319 if (ep->X_op != O_constant
3320 && ep->X_op != O_symbol)
3322 as_bad (_("expression too complex"));
3323 ep->X_op = O_constant;
3326 if (ep->X_op == O_constant)
3328 load_register (counter, reg, ep, 0);
3332 if (mips_pic == NO_PIC)
3334 /* If this is a reference to a GP relative symbol, we want
3335 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3337 lui $reg,<sym> (BFD_RELOC_HI16_S)
3338 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3339 If we have an addend, we always use the latter form. */
3340 if ((valueT) ep->X_add_number > MAX_GPREL_OFFSET
3341 || nopic_need_relax (ep->X_add_symbol, 1))
3346 macro_build ((char *) NULL, counter, ep,
3347 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3348 "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL);
3349 p = frag_var (rs_machine_dependent, 8, 0,
3350 RELAX_ENCODE (4, 8, 0, 4, 0,
3351 mips_opts.warn_about_macros),
3352 ep->X_add_symbol, (offsetT) 0, (char *) NULL);
3354 macro_build_lui (p, counter, ep, reg);
3357 macro_build (p, counter, ep,
3358 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3359 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3361 else if (mips_pic == SVR4_PIC && ! mips_big_got)
3365 /* If this is a reference to an external symbol, we want
3366 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3368 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3370 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3371 If there is a constant, it must be added in after. */
3372 ex.X_add_number = ep->X_add_number;
3373 ep->X_add_number = 0;
3375 macro_build ((char *) NULL, counter, ep,
3376 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
3377 "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP);
3378 macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", "");
3379 p = frag_var (rs_machine_dependent, 4, 0,
3380 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts.warn_about_macros),
3381 ep->X_add_symbol, (offsetT) 0, (char *) NULL);
3382 macro_build (p, counter, ep,
3383 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3384 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3385 if (ex.X_add_number != 0)
3387 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3388 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3389 ex.X_op = O_constant;
3390 macro_build ((char *) NULL, counter, &ex,
3391 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3392 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3395 else if (mips_pic == SVR4_PIC)
3400 /* This is the large GOT case. If this is a reference to an
3401 external symbol, we want
3402 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3404 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3405 Otherwise, for a reference to a local symbol, we want
3406 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3408 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3409 If there is a constant, it must be added in after. */
3410 ex.X_add_number = ep->X_add_number;
3411 ep->X_add_number = 0;
3412 if (reg_needs_delay (GP))
3417 macro_build ((char *) NULL, counter, ep, "lui", "t,u", reg,
3418 (int) BFD_RELOC_MIPS_GOT_HI16);
3419 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3420 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
3421 "d,v,t", reg, reg, GP);
3422 macro_build ((char *) NULL, counter, ep,
3423 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
3424 "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg);
3425 p = frag_var (rs_machine_dependent, 12 + off, 0,
3426 RELAX_ENCODE (12, 12 + off, off, 8 + off, 0,
3427 mips_opts.warn_about_macros),
3428 ep->X_add_symbol, (offsetT) 0, (char *) NULL);
3431 /* We need a nop before loading from $gp. This special
3432 check is required because the lui which starts the main
3433 instruction stream does not refer to $gp, and so will not
3434 insert the nop which may be required. */
3435 macro_build (p, counter, (expressionS *) NULL, "nop", "");
3438 macro_build (p, counter, ep, HAVE_32BIT_ADDRESSES ? "lw" : "ld",
3439 "t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP);
3441 macro_build (p, counter, (expressionS *) NULL, "nop", "");
3443 macro_build (p, counter, ep, HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3444 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3445 if (ex.X_add_number != 0)
3447 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3448 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3449 ex.X_op = O_constant;
3450 macro_build ((char *) NULL, counter, &ex,
3451 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3452 "t,r,j", reg, reg, (int) BFD_RELOC_LO16);
3455 else if (mips_pic == EMBEDDED_PIC)
3458 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3460 macro_build ((char *) NULL, counter, ep,
3461 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
3462 "t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL);
3468 /* Move the contents of register SOURCE into register DEST. */
3471 move_register (counter, dest, source)
3476 macro_build ((char *) NULL, counter, (expressionS *) NULL,
3477 HAVE_32BIT_GPRS ? "addu" : "daddu",
3478 "d,v,t", dest, source, 0);
3483 * This routine implements the seemingly endless macro or synthesized
3484 * instructions and addressing modes in the mips assembly language. Many
3485 * of these macros are simple and are similar to each other. These could
3486 * probably be handled by some kind of table or grammer aproach instead of
3487 * this verbose method. Others are not simple macros but are more like
3488 * optimizing code generation.
3489 * One interesting optimization is when several store macros appear
3490 * consecutivly that would load AT with the upper half of the same address.
3491 * The ensuing load upper instructions are ommited. This implies some kind
3492 * of global optimization. We currently only optimize within a single macro.
3493 * For many of the load and store macros if the address is specified as a
3494 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3495 * first load register 'at' with zero and use it as the base register. The
3496 * mips assembler simply uses register $zero. Just one tiny optimization
3501 struct mips_cl_insn *ip;
3503 register int treg, sreg, dreg, breg;
3519 bfd_reloc_code_real_type r;
3521 int hold_mips_optimize;
3523 assert (! mips_opts.mips16);
3525 treg = (ip->insn_opcode >> 16) & 0x1f;
3526 dreg = (ip->insn_opcode >> 11) & 0x1f;
3527 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
3528 mask = ip->insn_mo->mask;
3530 expr1.X_op = O_constant;
3531 expr1.X_op_symbol = NULL;
3532 expr1.X_add_symbol = NULL;
3533 expr1.X_add_number = 1;
3545 mips_emit_delays (true);
3546 ++mips_opts.noreorder;
3547 mips_any_noreorder = 1;
3549 expr1.X_add_number = 8;
3550 macro_build ((char *) NULL, &icnt, &expr1, "bgez", "s,p", sreg);
3552 macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0);
3554 move_register (&icnt, dreg, sreg);
3555 macro_build ((char *) NULL, &icnt, NULL,
3556 dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
3558 --mips_opts.noreorder;
3579 if (imm_expr.X_op == O_constant
3580 && imm_expr.X_add_number >= -0x8000
3581 && imm_expr.X_add_number < 0x8000)
3583 macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg,
3584 (int) BFD_RELOC_LO16);
3587 load_register (&icnt, AT, &imm_expr, dbl);
3588 macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT);
3607 if (imm_expr.X_op == O_constant
3608 && imm_expr.X_add_number >= 0
3609 && imm_expr.X_add_number < 0x10000)
3611 if (mask != M_NOR_I)
3612 macro_build ((char *) NULL, &icnt, &imm_expr, s, "t,r,i", treg,
3613 sreg, (int) BFD_RELOC_LO16);
3616 macro_build ((char *) NULL, &icnt, &imm_expr, "ori", "t,r,i",
3617 treg, sreg, (int) BFD_RELOC_LO16);
3618 macro_build ((char *) NULL, &icnt, NULL, "nor", "d,v,t",
3624 load_register (&icnt, AT, &imm_expr, 0);
3625 macro_build ((char *) NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT);
3642 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
3644 macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg,
3648 load_register (&icnt, AT, &imm_expr, 0);
3649 macro_build ((char *) NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT);
3657 macro_build ((char *) NULL, &icnt, &offset_expr,
3658 likely ? "bgezl" : "bgez",
3664 macro_build ((char *) NULL, &icnt, &offset_expr,
3665 likely ? "blezl" : "blez",
3669 macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg);
3670 macro_build ((char *) NULL, &icnt, &offset_expr,
3671 likely ? "beql" : "beq", "s,t,p", AT, 0);
3677 /* check for > max integer */
3678 maxnum = 0x7fffffff;
3679 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
3686 if (imm_expr.X_op == O_constant
3687 && imm_expr.X_add_number >= maxnum
3688 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
3691 /* result is always false */
3695 as_warn (_("Branch %s is always false (nop)"),
3697 macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0);
3702 as_warn (_("Branch likely %s is always false"),
3704 macro_build ((char *) NULL, &icnt, &offset_expr, "bnel",
3709 if (imm_expr.X_op != O_constant)
3710 as_bad (_("Unsupported large constant"));
3711 imm_expr.X_add_number++;
3715 if (mask == M_BGEL_I)
3717 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
3719 macro_build ((char *) NULL, &icnt, &offset_expr,
3720 likely ? "bgezl" : "bgez", "s,p", sreg);
3723 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
3725 macro_build ((char *) NULL, &icnt, &offset_expr,
3726 likely ? "bgtzl" : "bgtz", "s,p", sreg);
3729 maxnum = 0x7fffffff;
3730 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
3737 maxnum = - maxnum - 1;
3738 if (imm_expr.X_op == O_constant
3739 && imm_expr.X_add_number <= maxnum
3740 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
3743 /* result is always true */
3744 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
3745 macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p");
3748 set_at (&icnt, sreg, 0);
3749 macro_build ((char *) NULL, &icnt, &offset_expr,
3750 likely ? "beql" : "beq", "s,t,p", AT, 0);
3760 macro_build ((char *) NULL, &icnt, &offset_expr,
3761 likely ? "beql" : "beq", "s,t,p", 0, treg);
3764 macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg,
3766 macro_build ((char *) NULL, &icnt, &offset_expr,
3767 likely ? "beql" : "beq", "s,t,p", AT, 0);
3775 && imm_expr.X_op == O_constant
3776 && imm_expr.X_add_number == 0xffffffff))
3778 if (imm_expr.X_op != O_constant)
3779 as_bad (_("Unsupported large constant"));
3780 imm_expr.X_add_number++;
3784 if (mask == M_BGEUL_I)
3786 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
3788 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
3790 macro_build ((char *) NULL, &icnt, &offset_expr,
3791 likely ? "bnel" : "bne", "s,t,p", sreg, 0);
3794 set_at (&icnt, sreg, 1);
3795 macro_build ((char *) NULL, &icnt, &offset_expr,
3796 likely ? "beql" : "beq", "s,t,p", AT, 0);
3804 macro_build ((char *) NULL, &icnt, &offset_expr,
3805 likely ? "bgtzl" : "bgtz", "s,p", sreg);
3810 macro_build ((char *) NULL, &icnt, &offset_expr,
3811 likely ? "bltzl" : "bltz", "s,p", treg);
3814 macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg);
3815 macro_build ((char *) NULL, &icnt, &offset_expr,
3816 likely ? "bnel" : "bne", "s,t,p", AT, 0);
3824 macro_build ((char *) NULL, &icnt, &offset_expr,
3825 likely ? "bnel" : "bne", "s,t,p", sreg, 0);
3830 macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg,
3832 macro_build ((char *) NULL, &icnt, &offset_expr,
3833 likely ? "bnel" : "bne", "s,t,p", AT, 0);
3841 macro_build ((char *) NULL, &icnt, &offset_expr,
3842 likely ? "blezl" : "blez", "s,p", sreg);
3847 macro_build ((char *) NULL, &icnt, &offset_expr,
3848 likely ? "bgezl" : "bgez", "s,p", treg);
3851 macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg);
3852 macro_build ((char *) NULL, &icnt, &offset_expr,
3853 likely ? "beql" : "beq", "s,t,p", AT, 0);
3859 maxnum = 0x7fffffff;
3860 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
3867 if (imm_expr.X_op == O_constant
3868 && imm_expr.X_add_number >= maxnum
3869 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
3871 if (imm_expr.X_op != O_constant)
3872 as_bad (_("Unsupported large constant"));
3873 imm_expr.X_add_number++;
3877 if (mask == M_BLTL_I)
3879 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
3881 macro_build ((char *) NULL, &icnt, &offset_expr,
3882 likely ? "bltzl" : "bltz", "s,p", sreg);
3885 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
3887 macro_build ((char *) NULL, &icnt, &offset_expr,
3888 likely ? "blezl" : "blez", "s,p", sreg);
3891 set_at (&icnt, sreg, 0);
3892 macro_build ((char *) NULL, &icnt, &offset_expr,
3893 likely ? "bnel" : "bne", "s,t,p", AT, 0);
3901 macro_build ((char *) NULL, &icnt, &offset_expr,
3902 likely ? "beql" : "beq", "s,t,p", sreg, 0);
3907 macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg,
3909 macro_build ((char *) NULL, &icnt, &offset_expr,
3910 likely ? "beql" : "beq", "s,t,p", AT, 0);
3918 && imm_expr.X_op == O_constant
3919 && imm_expr.X_add_number == 0xffffffff))
3921 if (imm_expr.X_op != O_constant)
3922 as_bad (_("Unsupported large constant"));
3923 imm_expr.X_add_number++;
3927 if (mask == M_BLTUL_I)
3929 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
3931 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
3933 macro_build ((char *) NULL, &icnt, &offset_expr,
3934 likely ? "beql" : "beq",
3938 set_at (&icnt, sreg, 1);
3939 macro_build ((char *) NULL, &icnt, &offset_expr,
3940 likely ? "bnel" : "bne", "s,t,p", AT, 0);
3948 macro_build ((char *) NULL, &icnt, &offset_expr,
3949 likely ? "bltzl" : "bltz", "s,p", sreg);
3954 macro_build ((char *) NULL, &icnt, &offset_expr,
3955 likely ? "bgtzl" : "bgtz", "s,p", treg);
3958 macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg);
3959 macro_build ((char *) NULL, &icnt, &offset_expr,
3960 likely ? "bnel" : "bne", "s,t,p", AT, 0);
3970 macro_build ((char *) NULL, &icnt, &offset_expr,
3971 likely ? "bnel" : "bne", "s,t,p", 0, treg);
3974 macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg,
3976 macro_build ((char *) NULL, &icnt, &offset_expr,
3977 likely ? "bnel" : "bne", "s,t,p", AT, 0);
3992 as_warn (_("Divide by zero."));
3994 macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0);
3996 macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7);
4000 mips_emit_delays (true);
4001 ++mips_opts.noreorder;
4002 mips_any_noreorder = 1;
4005 macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0);
4006 macro_build ((char *) NULL, &icnt, NULL,
4007 dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
4011 expr1.X_add_number = 8;
4012 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0);
4013 macro_build ((char *) NULL, &icnt, NULL,
4014 dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
4015 macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7);
4017 expr1.X_add_number = -1;
4018 macro_build ((char *) NULL, &icnt, &expr1,
4019 dbl ? "daddiu" : "addiu",
4020 "t,r,j", AT, 0, (int) BFD_RELOC_LO16);
4021 expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
4022 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT);
4025 expr1.X_add_number = 1;
4026 macro_build ((char *) NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0,
4027 (int) BFD_RELOC_LO16);
4028 macro_build ((char *) NULL, &icnt, NULL, "dsll32", "d,w,<", AT, AT,
4033 expr1.X_add_number = 0x80000000;
4034 macro_build ((char *) NULL, &icnt, &expr1, "lui", "t,u", AT,
4035 (int) BFD_RELOC_HI16);
4039 macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", sreg, AT);
4040 /* We want to close the noreorder block as soon as possible, so
4041 that later insns are available for delay slot filling. */
4042 --mips_opts.noreorder;
4046 expr1.X_add_number = 8;
4047 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT);
4048 macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0);
4050 /* We want to close the noreorder block as soon as possible, so
4051 that later insns are available for delay slot filling. */
4052 --mips_opts.noreorder;
4054 macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6);
4056 macro_build ((char *) NULL, &icnt, NULL, s, "d", dreg);
4095 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4097 as_warn (_("Divide by zero."));
4099 macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", 0, 0);
4101 macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7);
4104 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4106 if (strcmp (s2, "mflo") == 0)
4107 move_register (&icnt, dreg, sreg);
4109 move_register (&icnt, dreg, 0);
4112 if (imm_expr.X_op == O_constant
4113 && imm_expr.X_add_number == -1
4114 && s[strlen (s) - 1] != 'u')
4116 if (strcmp (s2, "mflo") == 0)
4118 macro_build ((char *) NULL, &icnt, NULL, dbl ? "dneg" : "neg",
4122 move_register (&icnt, dreg, 0);
4126 load_register (&icnt, AT, &imm_expr, dbl);
4127 macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, AT);
4128 macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg);
4147 mips_emit_delays (true);
4148 ++mips_opts.noreorder;
4149 mips_any_noreorder = 1;
4152 macro_build ((char *) NULL, &icnt, NULL, "teq", "s,t", treg, 0);
4153 macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, treg);
4154 /* We want to close the noreorder block as soon as possible, so
4155 that later insns are available for delay slot filling. */
4156 --mips_opts.noreorder;
4160 expr1.X_add_number = 8;
4161 macro_build ((char *) NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0);
4162 macro_build ((char *) NULL, &icnt, NULL, s, "z,s,t", sreg, treg);
4164 /* We want to close the noreorder block as soon as possible, so
4165 that later insns are available for delay slot filling. */
4166 --mips_opts.noreorder;
4167 macro_build ((char *) NULL, &icnt, NULL, "break", "c", 7);
4169 macro_build ((char *) NULL, &icnt, NULL, s2, "d", dreg);
4175 /* Load the address of a symbol into a register. If breg is not
4176 zero, we then add a base register to it. */
4178 /* When generating embedded PIC code, we permit expressions of
4181 where bar is an address in the current section. These are used
4182 when getting the addresses of functions. We don't permit
4183 X_add_number to be non-zero, because if the symbol is
4184 external the relaxing code needs to know that any addend is
4185 purely the offset to X_op_symbol. */
4186 if (mips_pic == EMBEDDED_PIC
4187 && offset_expr.X_op == O_subtract
4188 && (symbol_constant_p (offset_expr.X_op_symbol)
4189 ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg
4190 : (symbol_equated_p (offset_expr.X_op_symbol)
4192 (symbol_get_value_expression (offset_expr.X_op_symbol)
4196 && (offset_expr.X_add_number == 0
4197 || OUTPUT_FLAVOR == bfd_target_elf_flavour))
4199 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
4200 treg, (int) BFD_RELOC_PCREL_HI16_S);
4201 macro_build ((char *) NULL, &icnt, &offset_expr,
4202 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4203 "t,r,j", treg, treg, (int) BFD_RELOC_PCREL_LO16);
4207 if (offset_expr.X_op != O_symbol
4208 && offset_expr.X_op != O_constant)
4210 as_bad (_("expression too complex"));
4211 offset_expr.X_op = O_constant;
4225 if (offset_expr.X_op == O_constant)
4226 load_register (&icnt, tempreg, &offset_expr, dbl);
4227 else if (mips_pic == NO_PIC)
4229 /* If this is a reference to an GP relative symbol, we want
4230 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4232 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4233 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4234 If we have a constant, we need two instructions anyhow,
4235 so we may as well always use the latter form. */
4236 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
4237 || nopic_need_relax (offset_expr.X_add_symbol, 1))
4242 macro_build ((char *) NULL, &icnt, &offset_expr,
4243 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4244 "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL);
4245 p = frag_var (rs_machine_dependent, 8, 0,
4246 RELAX_ENCODE (4, 8, 0, 4, 0,
4247 mips_opts.warn_about_macros),
4248 offset_expr.X_add_symbol, (offsetT) 0,
4251 macro_build_lui (p, &icnt, &offset_expr, tempreg);
4254 macro_build (p, &icnt, &offset_expr,
4255 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4256 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
4258 else if (mips_pic == SVR4_PIC && ! mips_big_got)
4260 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
4262 /* If this is a reference to an external symbol, and there
4263 is no constant, we want
4264 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4265 or if tempreg is PIC_CALL_REG
4266 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4267 For a local symbol, we want
4268 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4270 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4272 If we have a small constant, and this is a reference to
4273 an external symbol, we want
4274 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4276 addiu $tempreg,$tempreg,<constant>
4277 For a local symbol, we want the same instruction
4278 sequence, but we output a BFD_RELOC_LO16 reloc on the
4281 If we have a large constant, and this is a reference to
4282 an external symbol, we want
4283 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4284 lui $at,<hiconstant>
4285 addiu $at,$at,<loconstant>
4286 addu $tempreg,$tempreg,$at
4287 For a local symbol, we want the same instruction
4288 sequence, but we output a BFD_RELOC_LO16 reloc on the
4289 addiu instruction. */
4290 expr1.X_add_number = offset_expr.X_add_number;
4291 offset_expr.X_add_number = 0;
4293 if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG)
4294 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
4295 macro_build ((char *) NULL, &icnt, &offset_expr,
4297 "t,o(b)", tempreg, lw_reloc_type, GP);
4298 if (expr1.X_add_number == 0)
4306 /* We're going to put in an addu instruction using
4307 tempreg, so we may as well insert the nop right
4309 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4313 p = frag_var (rs_machine_dependent, 8 - off, 0,
4314 RELAX_ENCODE (0, 8 - off, -4 - off, 4 - off, 0,
4316 ? mips_opts.warn_about_macros
4318 offset_expr.X_add_symbol, (offsetT) 0,
4322 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
4325 macro_build (p, &icnt, &expr1,
4326 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4327 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
4328 /* FIXME: If breg == 0, and the next instruction uses
4329 $tempreg, then if this variant case is used an extra
4330 nop will be generated. */
4332 else if (expr1.X_add_number >= -0x8000
4333 && expr1.X_add_number < 0x8000)
4335 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4337 macro_build ((char *) NULL, &icnt, &expr1,
4338 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4339 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
4340 (void) frag_var (rs_machine_dependent, 0, 0,
4341 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4342 offset_expr.X_add_symbol, (offsetT) 0,
4349 /* If we are going to add in a base register, and the
4350 target register and the base register are the same,
4351 then we are using AT as a temporary register. Since
4352 we want to load the constant into AT, we add our
4353 current AT (from the global offset table) and the
4354 register into the register now, and pretend we were
4355 not using a base register. */
4360 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4362 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4363 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4364 "d,v,t", treg, AT, breg);
4370 /* Set mips_optimize around the lui instruction to avoid
4371 inserting an unnecessary nop after the lw. */
4372 hold_mips_optimize = mips_optimize;
4374 macro_build_lui ((char *) NULL, &icnt, &expr1, AT);
4375 mips_optimize = hold_mips_optimize;
4377 macro_build ((char *) NULL, &icnt, &expr1,
4378 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4379 "t,r,j", AT, AT, (int) BFD_RELOC_LO16);
4380 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4381 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4382 "d,v,t", tempreg, tempreg, AT);
4383 (void) frag_var (rs_machine_dependent, 0, 0,
4384 RELAX_ENCODE (0, 0, -16 + off1, -8, 0, 0),
4385 offset_expr.X_add_symbol, (offsetT) 0,
4390 else if (mips_pic == SVR4_PIC)
4393 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
4394 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
4396 /* This is the large GOT case. If this is a reference to an
4397 external symbol, and there is no constant, we want
4398 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4399 addu $tempreg,$tempreg,$gp
4400 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4401 or if tempreg is PIC_CALL_REG
4402 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4403 addu $tempreg,$tempreg,$gp
4404 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
4405 For a local symbol, we want
4406 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4408 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4410 If we have a small constant, and this is a reference to
4411 an external symbol, we want
4412 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4413 addu $tempreg,$tempreg,$gp
4414 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4416 addiu $tempreg,$tempreg,<constant>
4417 For a local symbol, we want
4418 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4420 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
4422 If we have a large constant, and this is a reference to
4423 an external symbol, we want
4424 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4425 addu $tempreg,$tempreg,$gp
4426 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4427 lui $at,<hiconstant>
4428 addiu $at,$at,<loconstant>
4429 addu $tempreg,$tempreg,$at
4430 For a local symbol, we want
4431 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4432 lui $at,<hiconstant>
4433 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
4434 addu $tempreg,$tempreg,$at
4436 expr1.X_add_number = offset_expr.X_add_number;
4437 offset_expr.X_add_number = 0;
4439 if (reg_needs_delay (GP))
4443 if (expr1.X_add_number == 0 && tempreg == PIC_CALL_REG)
4445 lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
4446 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
4448 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
4449 tempreg, lui_reloc_type);
4450 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4451 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4452 "d,v,t", tempreg, tempreg, GP);
4453 macro_build ((char *) NULL, &icnt, &offset_expr,
4455 "t,o(b)", tempreg, lw_reloc_type, tempreg);
4456 if (expr1.X_add_number == 0)
4464 /* We're going to put in an addu instruction using
4465 tempreg, so we may as well insert the nop right
4467 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4472 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
4473 RELAX_ENCODE (12 + off, 12 + gpdel, gpdel,
4476 ? mips_opts.warn_about_macros
4478 offset_expr.X_add_symbol, (offsetT) 0,
4481 else if (expr1.X_add_number >= -0x8000
4482 && expr1.X_add_number < 0x8000)
4484 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4486 macro_build ((char *) NULL, &icnt, &expr1,
4487 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4488 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
4490 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
4491 RELAX_ENCODE (20, 12 + gpdel, gpdel, 8 + gpdel, 0,
4493 ? mips_opts.warn_about_macros
4495 offset_expr.X_add_symbol, (offsetT) 0,
4502 /* If we are going to add in a base register, and the
4503 target register and the base register are the same,
4504 then we are using AT as a temporary register. Since
4505 we want to load the constant into AT, we add our
4506 current AT (from the global offset table) and the
4507 register into the register now, and pretend we were
4508 not using a base register. */
4516 assert (tempreg == AT);
4517 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4519 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4520 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4521 "d,v,t", treg, AT, breg);
4526 /* Set mips_optimize around the lui instruction to avoid
4527 inserting an unnecessary nop after the lw. */
4528 hold_mips_optimize = mips_optimize;
4530 macro_build_lui ((char *) NULL, &icnt, &expr1, AT);
4531 mips_optimize = hold_mips_optimize;
4533 macro_build ((char *) NULL, &icnt, &expr1,
4534 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4535 "t,r,j", AT, AT, (int) BFD_RELOC_LO16);
4536 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4537 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4538 "d,v,t", dreg, dreg, AT);
4540 p = frag_var (rs_machine_dependent, 16 + gpdel + adj, 0,
4541 RELAX_ENCODE (24 + adj, 16 + gpdel + adj, gpdel,
4544 ? mips_opts.warn_about_macros
4546 offset_expr.X_add_symbol, (offsetT) 0,
4554 /* This is needed because this instruction uses $gp, but
4555 the first instruction on the main stream does not. */
4556 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
4559 macro_build (p, &icnt, &offset_expr,
4561 "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP);
4563 if (expr1.X_add_number >= -0x8000
4564 && expr1.X_add_number < 0x8000)
4566 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
4568 macro_build (p, &icnt, &expr1,
4569 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4570 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
4571 /* FIXME: If add_number is 0, and there was no base
4572 register, the external symbol case ended with a load,
4573 so if the symbol turns out to not be external, and
4574 the next instruction uses tempreg, an unnecessary nop
4575 will be inserted. */
4581 /* We must add in the base register now, as in the
4582 external symbol case. */
4583 assert (tempreg == AT);
4584 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
4586 macro_build (p, &icnt, (expressionS *) NULL,
4587 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4588 "d,v,t", treg, AT, breg);
4591 /* We set breg to 0 because we have arranged to add
4592 it in in both cases. */
4596 macro_build_lui (p, &icnt, &expr1, AT);
4598 macro_build (p, &icnt, &expr1,
4599 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4600 "t,r,j", AT, AT, (int) BFD_RELOC_LO16);
4602 macro_build (p, &icnt, (expressionS *) NULL,
4603 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4604 "d,v,t", tempreg, tempreg, AT);
4608 else if (mips_pic == EMBEDDED_PIC)
4611 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4613 macro_build ((char *) NULL, &icnt, &offset_expr,
4614 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4615 "t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL);
4621 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4622 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4623 "d,v,t", treg, tempreg, breg);
4631 /* The j instruction may not be used in PIC code, since it
4632 requires an absolute address. We convert it to a b
4634 if (mips_pic == NO_PIC)
4635 macro_build ((char *) NULL, &icnt, &offset_expr, "j", "a");
4637 macro_build ((char *) NULL, &icnt, &offset_expr, "b", "p");
4640 /* The jal instructions must be handled as macros because when
4641 generating PIC code they expand to multi-instruction
4642 sequences. Normally they are simple instructions. */
4647 if (mips_pic == NO_PIC
4648 || mips_pic == EMBEDDED_PIC)
4649 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr",
4651 else if (mips_pic == SVR4_PIC)
4653 if (sreg != PIC_CALL_REG)
4654 as_warn (_("MIPS PIC call to register other than $25"));
4656 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "jalr",
4658 if (mips_cprestore_offset < 0)
4659 as_warn (_("No .cprestore pseudo-op used in PIC code"));
4662 expr1.X_add_number = mips_cprestore_offset;
4663 macro_build ((char *) NULL, &icnt, &expr1,
4664 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
4665 "t,o(b)", GP, (int) BFD_RELOC_LO16, mips_frame_reg);
4674 if (mips_pic == NO_PIC)
4675 macro_build ((char *) NULL, &icnt, &offset_expr, "jal", "a");
4676 else if (mips_pic == SVR4_PIC)
4678 /* If this is a reference to an external symbol, and we are
4679 using a small GOT, we want
4680 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4684 lw $gp,cprestore($sp)
4685 The cprestore value is set using the .cprestore
4686 pseudo-op. If we are using a big GOT, we want
4687 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4689 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
4693 lw $gp,cprestore($sp)
4694 If the symbol is not external, we want
4695 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4697 addiu $25,$25,<sym> (BFD_RELOC_LO16)
4700 lw $gp,cprestore($sp) */
4704 macro_build ((char *) NULL, &icnt, &offset_expr,
4705 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
4706 "t,o(b)", PIC_CALL_REG,
4707 (int) BFD_RELOC_MIPS_CALL16, GP);
4708 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4710 p = frag_var (rs_machine_dependent, 4, 0,
4711 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4712 offset_expr.X_add_symbol, (offsetT) 0,
4719 if (reg_needs_delay (GP))
4723 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
4724 PIC_CALL_REG, (int) BFD_RELOC_MIPS_CALL_HI16);
4725 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4726 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
4727 "d,v,t", PIC_CALL_REG, PIC_CALL_REG, GP);
4728 macro_build ((char *) NULL, &icnt, &offset_expr,
4729 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
4730 "t,o(b)", PIC_CALL_REG,
4731 (int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG);
4732 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4734 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
4735 RELAX_ENCODE (16, 12 + gpdel, gpdel, 8 + gpdel,
4737 offset_expr.X_add_symbol, (offsetT) 0,
4741 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
4744 macro_build (p, &icnt, &offset_expr,
4745 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
4746 "t,o(b)", PIC_CALL_REG,
4747 (int) BFD_RELOC_MIPS_GOT16, GP);
4749 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
4752 macro_build (p, &icnt, &offset_expr,
4753 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
4754 "t,r,j", PIC_CALL_REG, PIC_CALL_REG,
4755 (int) BFD_RELOC_LO16);
4756 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4757 "jalr", "s", PIC_CALL_REG);
4758 if (mips_cprestore_offset < 0)
4759 as_warn (_("No .cprestore pseudo-op used in PIC code"));
4762 if (mips_opts.noreorder)
4763 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
4765 expr1.X_add_number = mips_cprestore_offset;
4766 macro_build ((char *) NULL, &icnt, &expr1,
4767 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
4768 "t,o(b)", GP, (int) BFD_RELOC_LO16,
4772 else if (mips_pic == EMBEDDED_PIC)
4774 macro_build ((char *) NULL, &icnt, &offset_expr, "bal", "p");
4775 /* The linker may expand the call to a longer sequence which
4776 uses $at, so we must break rather than return. */
4801 /* Itbl support may require additional care here. */
4806 /* Itbl support may require additional care here. */
4811 /* Itbl support may require additional care here. */
4816 /* Itbl support may require additional care here. */
4828 if (mips_arch == CPU_R4650)
4830 as_bad (_("opcode not supported on this processor"));
4834 /* Itbl support may require additional care here. */
4839 /* Itbl support may require additional care here. */
4844 /* Itbl support may require additional care here. */
4864 if (breg == treg || coproc || lr)
4886 /* Itbl support may require additional care here. */
4891 /* Itbl support may require additional care here. */
4896 /* Itbl support may require additional care here. */
4901 /* Itbl support may require additional care here. */
4917 if (mips_arch == CPU_R4650)
4919 as_bad (_("opcode not supported on this processor"));
4924 /* Itbl support may require additional care here. */
4928 /* Itbl support may require additional care here. */
4933 /* Itbl support may require additional care here. */
4945 /* Itbl support may require additional care here. */
4946 if (mask == M_LWC1_AB
4947 || mask == M_SWC1_AB
4948 || mask == M_LDC1_AB
4949 || mask == M_SDC1_AB
4958 if (offset_expr.X_op != O_constant
4959 && offset_expr.X_op != O_symbol)
4961 as_bad (_("expression too complex"));
4962 offset_expr.X_op = O_constant;
4965 /* A constant expression in PIC code can be handled just as it
4966 is in non PIC code. */
4967 if (mips_pic == NO_PIC
4968 || offset_expr.X_op == O_constant)
4970 /* If this is a reference to a GP relative symbol, and there
4971 is no base register, we want
4972 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4973 Otherwise, if there is no base register, we want
4974 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4975 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4976 If we have a constant, we need two instructions anyhow,
4977 so we always use the latter form.
4979 If we have a base register, and this is a reference to a
4980 GP relative symbol, we want
4981 addu $tempreg,$breg,$gp
4982 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4984 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4985 addu $tempreg,$tempreg,$breg
4986 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4987 With a constant we always use the latter case. */
4990 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
4991 || nopic_need_relax (offset_expr.X_add_symbol, 1))
4996 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
4997 treg, (int) BFD_RELOC_MIPS_GPREL, GP);
4998 p = frag_var (rs_machine_dependent, 8, 0,
4999 RELAX_ENCODE (4, 8, 0, 4, 0,
5000 (mips_opts.warn_about_macros
5002 && mips_opts.noat))),
5003 offset_expr.X_add_symbol, (offsetT) 0,
5007 macro_build_lui (p, &icnt, &offset_expr, tempreg);
5010 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
5011 (int) BFD_RELOC_LO16, tempreg);
5015 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
5016 || nopic_need_relax (offset_expr.X_add_symbol, 1))
5021 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5022 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5023 "d,v,t", tempreg, breg, GP);
5024 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
5025 treg, (int) BFD_RELOC_MIPS_GPREL, tempreg);
5026 p = frag_var (rs_machine_dependent, 12, 0,
5027 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
5028 offset_expr.X_add_symbol, (offsetT) 0,
5031 macro_build_lui (p, &icnt, &offset_expr, tempreg);
5034 macro_build (p, &icnt, (expressionS *) NULL,
5035 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5036 "d,v,t", tempreg, tempreg, breg);
5039 macro_build (p, &icnt, &offset_expr, s, fmt, treg,
5040 (int) BFD_RELOC_LO16, tempreg);
5043 else if (mips_pic == SVR4_PIC && ! mips_big_got)
5045 /* If this is a reference to an external symbol, we want
5046 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5048 <op> $treg,0($tempreg)
5050 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5052 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5053 <op> $treg,0($tempreg)
5054 If there is a base register, we add it to $tempreg before
5055 the <op>. If there is a constant, we stick it in the
5056 <op> instruction. We don't handle constants larger than
5057 16 bits, because we have no way to load the upper 16 bits
5058 (actually, we could handle them for the subset of cases
5059 in which we are not using $at). */
5060 assert (offset_expr.X_op == O_symbol);
5061 expr1.X_add_number = offset_expr.X_add_number;
5062 offset_expr.X_add_number = 0;
5063 if (expr1.X_add_number < -0x8000
5064 || expr1.X_add_number >= 0x8000)
5065 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5067 macro_build ((char *) NULL, &icnt, &offset_expr,
5068 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5069 "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP);
5070 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
5071 p = frag_var (rs_machine_dependent, 4, 0,
5072 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5073 offset_expr.X_add_symbol, (offsetT) 0,
5075 macro_build (p, &icnt, &offset_expr,
5076 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5077 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
5079 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5080 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5081 "d,v,t", tempreg, tempreg, breg);
5082 macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg,
5083 (int) BFD_RELOC_LO16, tempreg);
5085 else if (mips_pic == SVR4_PIC)
5089 /* If this is a reference to an external symbol, we want
5090 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5091 addu $tempreg,$tempreg,$gp
5092 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5093 <op> $treg,0($tempreg)
5095 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5097 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5098 <op> $treg,0($tempreg)
5099 If there is a base register, we add it to $tempreg before
5100 the <op>. If there is a constant, we stick it in the
5101 <op> instruction. We don't handle constants larger than
5102 16 bits, because we have no way to load the upper 16 bits
5103 (actually, we could handle them for the subset of cases
5104 in which we are not using $at). */
5105 assert (offset_expr.X_op == O_symbol);
5106 expr1.X_add_number = offset_expr.X_add_number;
5107 offset_expr.X_add_number = 0;
5108 if (expr1.X_add_number < -0x8000
5109 || expr1.X_add_number >= 0x8000)
5110 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5111 if (reg_needs_delay (GP))
5116 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
5117 tempreg, (int) BFD_RELOC_MIPS_GOT_HI16);
5118 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5119 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5120 "d,v,t", tempreg, tempreg, GP);
5121 macro_build ((char *) NULL, &icnt, &offset_expr,
5122 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5123 "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16,
5125 p = frag_var (rs_machine_dependent, 12 + gpdel, 0,
5126 RELAX_ENCODE (12, 12 + gpdel, gpdel, 8 + gpdel, 0, 0),
5127 offset_expr.X_add_symbol, (offsetT) 0, (char *) NULL);
5130 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5133 macro_build (p, &icnt, &offset_expr,
5134 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5135 "t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP);
5137 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5139 macro_build (p, &icnt, &offset_expr,
5140 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5141 "t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
5143 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5144 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5145 "d,v,t", tempreg, tempreg, breg);
5146 macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg,
5147 (int) BFD_RELOC_LO16, tempreg);
5149 else if (mips_pic == EMBEDDED_PIC)
5151 /* If there is no base register, we want
5152 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5153 If there is a base register, we want
5154 addu $tempreg,$breg,$gp
5155 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
5157 assert (offset_expr.X_op == O_symbol);
5160 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
5161 treg, (int) BFD_RELOC_MIPS_GPREL, GP);
5166 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5167 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5168 "d,v,t", tempreg, breg, GP);
5169 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
5170 treg, (int) BFD_RELOC_MIPS_GPREL, tempreg);
5183 load_register (&icnt, treg, &imm_expr, 0);
5187 load_register (&icnt, treg, &imm_expr, 1);
5191 if (imm_expr.X_op == O_constant)
5193 load_register (&icnt, AT, &imm_expr, 0);
5194 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5195 "mtc1", "t,G", AT, treg);
5200 assert (offset_expr.X_op == O_symbol
5201 && strcmp (segment_name (S_GET_SEGMENT
5202 (offset_expr.X_add_symbol)),
5204 && offset_expr.X_add_number == 0);
5205 macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
5206 treg, (int) BFD_RELOC_MIPS_LITERAL, GP);
5211 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
5212 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
5213 order 32 bits of the value and the low order 32 bits are either
5214 zero or in OFFSET_EXPR. */
5215 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
5217 if (HAVE_64BIT_GPRS)
5218 load_register (&icnt, treg, &imm_expr, 1);
5223 if (target_big_endian)
5235 load_register (&icnt, hreg, &imm_expr, 0);
5238 if (offset_expr.X_op == O_absent)
5239 move_register (&icnt, lreg, 0);
5242 assert (offset_expr.X_op == O_constant);
5243 load_register (&icnt, lreg, &offset_expr, 0);
5250 /* We know that sym is in the .rdata section. First we get the
5251 upper 16 bits of the address. */
5252 if (mips_pic == NO_PIC)
5254 /* FIXME: This won't work for a 64 bit address. */
5255 macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT);
5257 else if (mips_pic == SVR4_PIC)
5259 macro_build ((char *) NULL, &icnt, &offset_expr,
5260 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5261 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP);
5263 else if (mips_pic == EMBEDDED_PIC)
5265 /* For embedded PIC we pick up the entire address off $gp in
5266 a single instruction. */
5267 macro_build ((char *) NULL, &icnt, &offset_expr,
5268 HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
5269 "t,r,j", AT, GP, (int) BFD_RELOC_MIPS_GPREL);
5270 offset_expr.X_op = O_constant;
5271 offset_expr.X_add_number = 0;
5276 /* Now we load the register(s). */
5277 if (HAVE_64BIT_GPRS)
5278 macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)",
5279 treg, (int) BFD_RELOC_LO16, AT);
5282 macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)",
5283 treg, (int) BFD_RELOC_LO16, AT);
5286 /* FIXME: How in the world do we deal with the possible
5288 offset_expr.X_add_number += 4;
5289 macro_build ((char *) NULL, &icnt, &offset_expr, "lw", "t,o(b)",
5290 treg + 1, (int) BFD_RELOC_LO16, AT);
5294 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5295 does not become a variant frag. */
5296 frag_wane (frag_now);
5302 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
5303 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
5304 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
5305 the value and the low order 32 bits are either zero or in
5307 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
5309 load_register (&icnt, AT, &imm_expr, HAVE_64BIT_FPRS);
5310 if (HAVE_64BIT_FPRS)
5312 assert (HAVE_64BIT_GPRS);
5313 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5314 "dmtc1", "t,S", AT, treg);
5318 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5319 "mtc1", "t,G", AT, treg + 1);
5320 if (offset_expr.X_op == O_absent)
5321 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5322 "mtc1", "t,G", 0, treg);
5325 assert (offset_expr.X_op == O_constant);
5326 load_register (&icnt, AT, &offset_expr, 0);
5327 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5328 "mtc1", "t,G", AT, treg);
5334 assert (offset_expr.X_op == O_symbol
5335 && offset_expr.X_add_number == 0);
5336 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
5337 if (strcmp (s, ".lit8") == 0)
5339 if (mips_opts.isa != ISA_MIPS1)
5341 macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1",
5342 "T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL, GP);
5346 r = BFD_RELOC_MIPS_LITERAL;
5351 assert (strcmp (s, RDATA_SECTION_NAME) == 0);
5352 if (mips_pic == SVR4_PIC)
5353 macro_build ((char *) NULL, &icnt, &offset_expr,
5354 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5355 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP);
5358 /* FIXME: This won't work for a 64 bit address. */
5359 macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT);
5362 if (mips_opts.isa != ISA_MIPS1)
5364 macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1",
5365 "T,o(b)", treg, (int) BFD_RELOC_LO16, AT);
5367 /* To avoid confusion in tc_gen_reloc, we must ensure
5368 that this does not become a variant frag. */
5369 frag_wane (frag_now);
5380 if (mips_arch == CPU_R4650)
5382 as_bad (_("opcode not supported on this processor"));
5385 /* Even on a big endian machine $fn comes before $fn+1. We have
5386 to adjust when loading from memory. */
5389 assert (mips_opts.isa == ISA_MIPS1);
5390 macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
5391 target_big_endian ? treg + 1 : treg,
5393 /* FIXME: A possible overflow which I don't know how to deal
5395 offset_expr.X_add_number += 4;
5396 macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
5397 target_big_endian ? treg : treg + 1,
5400 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5401 does not become a variant frag. */
5402 frag_wane (frag_now);
5411 * The MIPS assembler seems to check for X_add_number not
5412 * being double aligned and generating:
5415 * addiu at,at,%lo(foo+1)
5418 * But, the resulting address is the same after relocation so why
5419 * generate the extra instruction?
5421 if (mips_arch == CPU_R4650)
5423 as_bad (_("opcode not supported on this processor"));
5426 /* Itbl support may require additional care here. */
5428 if (mips_opts.isa != ISA_MIPS1)
5439 if (mips_arch == CPU_R4650)
5441 as_bad (_("opcode not supported on this processor"));
5445 if (mips_opts.isa != ISA_MIPS1)
5453 /* Itbl support may require additional care here. */
5458 if (HAVE_64BIT_GPRS)
5469 if (HAVE_64BIT_GPRS)
5479 if (offset_expr.X_op != O_symbol
5480 && offset_expr.X_op != O_constant)
5482 as_bad (_("expression too complex"));
5483 offset_expr.X_op = O_constant;
5486 /* Even on a big endian machine $fn comes before $fn+1. We have
5487 to adjust when loading from memory. We set coproc if we must
5488 load $fn+1 first. */
5489 /* Itbl support may require additional care here. */
5490 if (! target_big_endian)
5493 if (mips_pic == NO_PIC
5494 || offset_expr.X_op == O_constant)
5496 /* If this is a reference to a GP relative symbol, we want
5497 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5498 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5499 If we have a base register, we use this
5501 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5502 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5503 If this is not a GP relative symbol, we want
5504 lui $at,<sym> (BFD_RELOC_HI16_S)
5505 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5506 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5507 If there is a base register, we add it to $at after the
5508 lui instruction. If there is a constant, we always use
5510 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
5511 || nopic_need_relax (offset_expr.X_add_symbol, 1))
5530 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5531 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5532 "d,v,t", AT, breg, GP);
5538 /* Itbl support may require additional care here. */
5539 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
5540 coproc ? treg + 1 : treg,
5541 (int) BFD_RELOC_MIPS_GPREL, tempreg);
5542 offset_expr.X_add_number += 4;
5544 /* Set mips_optimize to 2 to avoid inserting an
5546 hold_mips_optimize = mips_optimize;
5548 /* Itbl support may require additional care here. */
5549 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
5550 coproc ? treg : treg + 1,
5551 (int) BFD_RELOC_MIPS_GPREL, tempreg);
5552 mips_optimize = hold_mips_optimize;
5554 p = frag_var (rs_machine_dependent, 12 + off, 0,
5555 RELAX_ENCODE (8 + off, 12 + off, 0, 4 + off, 1,
5556 used_at && mips_opts.noat),
5557 offset_expr.X_add_symbol, (offsetT) 0,
5560 /* We just generated two relocs. When tc_gen_reloc
5561 handles this case, it will skip the first reloc and
5562 handle the second. The second reloc already has an
5563 extra addend of 4, which we added above. We must
5564 subtract it out, and then subtract another 4 to make
5565 the first reloc come out right. The second reloc
5566 will come out right because we are going to add 4 to
5567 offset_expr when we build its instruction below.
5569 If we have a symbol, then we don't want to include
5570 the offset, because it will wind up being included
5571 when we generate the reloc. */
5573 if (offset_expr.X_op == O_constant)
5574 offset_expr.X_add_number -= 8;
5577 offset_expr.X_add_number = -4;
5578 offset_expr.X_op = O_constant;
5581 macro_build_lui (p, &icnt, &offset_expr, AT);
5586 macro_build (p, &icnt, (expressionS *) NULL,
5587 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5588 "d,v,t", AT, breg, AT);
5592 /* Itbl support may require additional care here. */
5593 macro_build (p, &icnt, &offset_expr, s, fmt,
5594 coproc ? treg + 1 : treg,
5595 (int) BFD_RELOC_LO16, AT);
5598 /* FIXME: How do we handle overflow here? */
5599 offset_expr.X_add_number += 4;
5600 /* Itbl support may require additional care here. */
5601 macro_build (p, &icnt, &offset_expr, s, fmt,
5602 coproc ? treg : treg + 1,
5603 (int) BFD_RELOC_LO16, AT);
5605 else if (mips_pic == SVR4_PIC && ! mips_big_got)
5609 /* If this is a reference to an external symbol, we want
5610 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5615 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5617 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5618 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5619 If there is a base register we add it to $at before the
5620 lwc1 instructions. If there is a constant we include it
5621 in the lwc1 instructions. */
5623 expr1.X_add_number = offset_expr.X_add_number;
5624 offset_expr.X_add_number = 0;
5625 if (expr1.X_add_number < -0x8000
5626 || expr1.X_add_number >= 0x8000 - 4)
5627 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5632 frag_grow (24 + off);
5633 macro_build ((char *) NULL, &icnt, &offset_expr,
5634 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5635 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP);
5636 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
5638 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5639 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5640 "d,v,t", AT, breg, AT);
5641 /* Itbl support may require additional care here. */
5642 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
5643 coproc ? treg + 1 : treg,
5644 (int) BFD_RELOC_LO16, AT);
5645 expr1.X_add_number += 4;
5647 /* Set mips_optimize to 2 to avoid inserting an undesired
5649 hold_mips_optimize = mips_optimize;
5651 /* Itbl support may require additional care here. */
5652 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
5653 coproc ? treg : treg + 1,
5654 (int) BFD_RELOC_LO16, AT);
5655 mips_optimize = hold_mips_optimize;
5657 (void) frag_var (rs_machine_dependent, 0, 0,
5658 RELAX_ENCODE (0, 0, -16 - off, -8, 1, 0),
5659 offset_expr.X_add_symbol, (offsetT) 0,
5662 else if (mips_pic == SVR4_PIC)
5666 /* If this is a reference to an external symbol, we want
5667 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5669 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
5674 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5676 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5677 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5678 If there is a base register we add it to $at before the
5679 lwc1 instructions. If there is a constant we include it
5680 in the lwc1 instructions. */
5682 expr1.X_add_number = offset_expr.X_add_number;
5683 offset_expr.X_add_number = 0;
5684 if (expr1.X_add_number < -0x8000
5685 || expr1.X_add_number >= 0x8000 - 4)
5686 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5687 if (reg_needs_delay (GP))
5696 macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
5697 AT, (int) BFD_RELOC_MIPS_GOT_HI16);
5698 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5699 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5700 "d,v,t", AT, AT, GP);
5701 macro_build ((char *) NULL, &icnt, &offset_expr,
5702 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5703 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT_LO16, AT);
5704 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
5706 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5707 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5708 "d,v,t", AT, breg, AT);
5709 /* Itbl support may require additional care here. */
5710 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
5711 coproc ? treg + 1 : treg,
5712 (int) BFD_RELOC_LO16, AT);
5713 expr1.X_add_number += 4;
5715 /* Set mips_optimize to 2 to avoid inserting an undesired
5717 hold_mips_optimize = mips_optimize;
5719 /* Itbl support may require additional care here. */
5720 macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
5721 coproc ? treg : treg + 1,
5722 (int) BFD_RELOC_LO16, AT);
5723 mips_optimize = hold_mips_optimize;
5724 expr1.X_add_number -= 4;
5726 p = frag_var (rs_machine_dependent, 16 + gpdel + off, 0,
5727 RELAX_ENCODE (24 + off, 16 + gpdel + off, gpdel,
5728 8 + gpdel + off, 1, 0),
5729 offset_expr.X_add_symbol, (offsetT) 0,
5733 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5736 macro_build (p, &icnt, &offset_expr,
5737 HAVE_32BIT_ADDRESSES ? "lw" : "ld",
5738 "t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP);
5740 macro_build (p, &icnt, (expressionS *) NULL, "nop", "");
5744 macro_build (p, &icnt, (expressionS *) NULL,
5745 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5746 "d,v,t", AT, breg, AT);
5749 /* Itbl support may require additional care here. */
5750 macro_build (p, &icnt, &expr1, s, fmt,
5751 coproc ? treg + 1 : treg,
5752 (int) BFD_RELOC_LO16, AT);
5754 expr1.X_add_number += 4;
5756 /* Set mips_optimize to 2 to avoid inserting an undesired
5758 hold_mips_optimize = mips_optimize;
5760 /* Itbl support may require additional care here. */
5761 macro_build (p, &icnt, &expr1, s, fmt,
5762 coproc ? treg : treg + 1,
5763 (int) BFD_RELOC_LO16, AT);
5764 mips_optimize = hold_mips_optimize;
5766 else if (mips_pic == EMBEDDED_PIC)
5768 /* If there is no base register, we use
5769 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5770 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5771 If we have a base register, we use
5773 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5774 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5783 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
5784 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
5785 "d,v,t", AT, breg, GP);
5790 /* Itbl support may require additional care here. */
5791 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
5792 coproc ? treg + 1 : treg,
5793 (int) BFD_RELOC_MIPS_GPREL, tempreg);
5794 offset_expr.X_add_number += 4;
5795 /* Itbl support may require additional care here. */
5796 macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
5797 coproc ? treg : treg + 1,
5798 (int) BFD_RELOC_MIPS_GPREL, tempreg);
5814 assert (HAVE_32BIT_ADDRESSES);
5815 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
5816 (int) BFD_RELOC_LO16, breg);
5817 offset_expr.X_add_number += 4;
5818 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1,
5819 (int) BFD_RELOC_LO16, breg);
5822 /* New code added to support COPZ instructions.
5823 This code builds table entries out of the macros in mip_opcodes.
5824 R4000 uses interlocks to handle coproc delays.
5825 Other chips (like the R3000) require nops to be inserted for delays.
5827 FIXME: Currently, we require that the user handle delays.
5828 In order to fill delay slots for non-interlocked chips,
5829 we must have a way to specify delays based on the coprocessor.
5830 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
5831 What are the side-effects of the cop instruction?
5832 What cache support might we have and what are its effects?
5833 Both coprocessor & memory require delays. how long???
5834 What registers are read/set/modified?
5836 If an itbl is provided to interpret cop instructions,
5837 this knowledge can be encoded in the itbl spec. */
5851 /* For now we just do C (same as Cz). The parameter will be
5852 stored in insn_opcode by mips_ip. */
5853 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "C",
5858 move_register (&icnt, dreg, sreg);
5861 #ifdef LOSING_COMPILER
5863 /* Try and see if this is a new itbl instruction.
5864 This code builds table entries out of the macros in mip_opcodes.
5865 FIXME: For now we just assemble the expression and pass it's
5866 value along as a 32-bit immediate.
5867 We may want to have the assembler assemble this value,
5868 so that we gain the assembler's knowledge of delay slots,
5870 Would it be more efficient to use mask (id) here? */
5871 if (itbl_have_entries
5872 && (immed_expr = itbl_assemble (ip->insn_mo->name, "")))
5874 s = ip->insn_mo->name;
5876 coproc = ITBL_DECODE_PNUM (immed_expr);;
5877 macro_build ((char *) NULL, &icnt, &immed_expr, s, "C");
5884 as_warn (_("Macro used $at after \".set noat\""));
5889 struct mips_cl_insn *ip;
5891 register int treg, sreg, dreg, breg;
5907 bfd_reloc_code_real_type r;
5910 treg = (ip->insn_opcode >> 16) & 0x1f;
5911 dreg = (ip->insn_opcode >> 11) & 0x1f;
5912 sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
5913 mask = ip->insn_mo->mask;
5915 expr1.X_op = O_constant;
5916 expr1.X_op_symbol = NULL;
5917 expr1.X_add_symbol = NULL;
5918 expr1.X_add_number = 1;
5922 #endif /* LOSING_COMPILER */
5927 macro_build ((char *) NULL, &icnt, NULL,
5928 dbl ? "dmultu" : "multu",
5930 macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg);
5936 /* The MIPS assembler some times generates shifts and adds. I'm
5937 not trying to be that fancy. GCC should do this for us
5939 load_register (&icnt, AT, &imm_expr, dbl);
5940 macro_build ((char *) NULL, &icnt, NULL,
5941 dbl ? "dmult" : "mult", "s,t", sreg, AT);
5942 macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg);
5955 mips_emit_delays (true);
5956 ++mips_opts.noreorder;
5957 mips_any_noreorder = 1;
5959 load_register (&icnt, AT, &imm_expr, dbl);
5960 macro_build ((char *) NULL, &icnt, NULL,
5961 dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
5962 macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg);
5963 macro_build ((char *) NULL, &icnt, NULL,
5964 dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, 31);
5965 macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT);
5967 macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", dreg, AT);
5970 expr1.X_add_number = 8;
5971 macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", dreg, AT);
5972 macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0);
5973 macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6);
5975 --mips_opts.noreorder;
5976 macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg);
5989 mips_emit_delays (true);
5990 ++mips_opts.noreorder;
5991 mips_any_noreorder = 1;
5993 load_register (&icnt, AT, &imm_expr, dbl);
5994 macro_build ((char *) NULL, &icnt, NULL,
5995 dbl ? "dmultu" : "multu",
5996 "s,t", sreg, imm ? AT : treg);
5997 macro_build ((char *) NULL, &icnt, NULL, "mfhi", "d", AT);
5998 macro_build ((char *) NULL, &icnt, NULL, "mflo", "d", dreg);
6000 macro_build ((char *) NULL, &icnt, NULL, "tne", "s,t", AT, 0);
6003 expr1.X_add_number = 8;
6004 macro_build ((char *) NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0);
6005 macro_build ((char *) NULL, &icnt, NULL, "nop", "", 0);
6006 macro_build ((char *) NULL, &icnt, NULL, "break", "c", 6);
6008 --mips_opts.noreorder;
6012 macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg);
6013 macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", AT, sreg, AT);
6014 macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", dreg, sreg,
6016 macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
6020 if (imm_expr.X_op != O_constant)
6021 as_bad (_("rotate count too large"));
6022 macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", AT, sreg,
6023 (int) (imm_expr.X_add_number & 0x1f));
6024 macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg,
6025 (int) ((0 - imm_expr.X_add_number) & 0x1f));
6026 macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
6030 macro_build ((char *) NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg);
6031 macro_build ((char *) NULL, &icnt, NULL, "sllv", "d,t,s", AT, sreg, AT);
6032 macro_build ((char *) NULL, &icnt, NULL, "srlv", "d,t,s", dreg, sreg,
6034 macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
6038 if (imm_expr.X_op != O_constant)
6039 as_bad (_("rotate count too large"));
6040 macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, sreg,
6041 (int) (imm_expr.X_add_number & 0x1f));
6042 macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", dreg, sreg,
6043 (int) ((0 - imm_expr.X_add_number) & 0x1f));
6044 macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
6048 if (mips_arch == CPU_R4650)
6050 as_bad (_("opcode not supported on this processor"));
6053 assert (mips_opts.isa == ISA_MIPS1);
6054 /* Even on a big endian machine $fn comes before $fn+1. We have
6055 to adjust when storing to memory. */
6056 macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)",
6057 target_big_endian ? treg + 1 : treg,
6058 (int) BFD_RELOC_LO16, breg);
6059 offset_expr.X_add_number += 4;
6060 macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)",
6061 target_big_endian ? treg : treg + 1,
6062 (int) BFD_RELOC_LO16, breg);
6067 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
6068 treg, (int) BFD_RELOC_LO16);
6070 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
6071 sreg, (int) BFD_RELOC_LO16);
6074 macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg,
6076 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
6077 dreg, (int) BFD_RELOC_LO16);
6082 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6084 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg,
6085 sreg, (int) BFD_RELOC_LO16);
6090 as_warn (_("Instruction %s: result is always false"),
6092 move_register (&icnt, dreg, 0);
6095 if (imm_expr.X_op == O_constant
6096 && imm_expr.X_add_number >= 0
6097 && imm_expr.X_add_number < 0x10000)
6099 macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg,
6100 sreg, (int) BFD_RELOC_LO16);
6103 else if (imm_expr.X_op == O_constant
6104 && imm_expr.X_add_number > -0x8000
6105 && imm_expr.X_add_number < 0)
6107 imm_expr.X_add_number = -imm_expr.X_add_number;
6108 macro_build ((char *) NULL, &icnt, &imm_expr,
6109 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
6110 "t,r,j", dreg, sreg,
6111 (int) BFD_RELOC_LO16);
6116 load_register (&icnt, AT, &imm_expr, 0);
6117 macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg,
6121 macro_build ((char *) NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg,
6122 (int) BFD_RELOC_LO16);
6127 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
6133 macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, sreg, treg);
6134 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
6135 (int) BFD_RELOC_LO16);
6138 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
6140 if (imm_expr.X_op == O_constant
6141 && imm_expr.X_add_number >= -0x8000
6142 && imm_expr.X_add_number < 0x8000)
6144 macro_build ((char *) NULL, &icnt, &imm_expr,
6145 mask == M_SGE_I ? "slti" : "sltiu",
6146 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
6151 load_register (&icnt, AT, &imm_expr, 0);
6152 macro_build ((char *) NULL, &icnt, NULL,
6153 mask == M_SGE_I ? "slt" : "sltu",
6154 "d,v,t", dreg, sreg, AT);
6157 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
6158 (int) BFD_RELOC_LO16);
6163 case M_SGT: /* sreg > treg <==> treg < sreg */
6169 macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg);
6172 case M_SGT_I: /* sreg > I <==> I < sreg */
6178 load_register (&icnt, AT, &imm_expr, 0);
6179 macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg);
6182 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
6188 macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg);
6189 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
6190 (int) BFD_RELOC_LO16);
6193 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
6199 load_register (&icnt, AT, &imm_expr, 0);
6200 macro_build ((char *) NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg);
6201 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
6202 (int) BFD_RELOC_LO16);
6206 if (imm_expr.X_op == O_constant
6207 && imm_expr.X_add_number >= -0x8000
6208 && imm_expr.X_add_number < 0x8000)
6210 macro_build ((char *) NULL, &icnt, &imm_expr, "slti", "t,r,j",
6211 dreg, sreg, (int) BFD_RELOC_LO16);
6214 load_register (&icnt, AT, &imm_expr, 0);
6215 macro_build ((char *) NULL, &icnt, NULL, "slt", "d,v,t", dreg, sreg, AT);
6219 if (imm_expr.X_op == O_constant
6220 && imm_expr.X_add_number >= -0x8000
6221 && imm_expr.X_add_number < 0x8000)
6223 macro_build ((char *) NULL, &icnt, &imm_expr, "sltiu", "t,r,j",
6224 dreg, sreg, (int) BFD_RELOC_LO16);
6227 load_register (&icnt, AT, &imm_expr, 0);
6228 macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, sreg,
6234 macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0,
6237 macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0,
6241 macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg,
6243 macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0,
6249 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
6251 macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0,
6257 as_warn (_("Instruction %s: result is always true"),
6259 macro_build ((char *) NULL, &icnt, &expr1,
6260 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
6261 "t,r,j", dreg, 0, (int) BFD_RELOC_LO16);
6264 if (imm_expr.X_op == O_constant
6265 && imm_expr.X_add_number >= 0
6266 && imm_expr.X_add_number < 0x10000)
6268 macro_build ((char *) NULL, &icnt, &imm_expr, "xori", "t,r,i",
6269 dreg, sreg, (int) BFD_RELOC_LO16);
6272 else if (imm_expr.X_op == O_constant
6273 && imm_expr.X_add_number > -0x8000
6274 && imm_expr.X_add_number < 0)
6276 imm_expr.X_add_number = -imm_expr.X_add_number;
6277 macro_build ((char *) NULL, &icnt, &imm_expr,
6278 HAVE_32BIT_GPRS ? "addiu" : "daddiu",
6279 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
6284 load_register (&icnt, AT, &imm_expr, 0);
6285 macro_build ((char *) NULL, &icnt, NULL, "xor", "d,v,t", dreg,
6289 macro_build ((char *) NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg);
6297 if (imm_expr.X_op == O_constant
6298 && imm_expr.X_add_number > -0x8000
6299 && imm_expr.X_add_number <= 0x8000)
6301 imm_expr.X_add_number = -imm_expr.X_add_number;
6302 macro_build ((char *) NULL, &icnt, &imm_expr,
6303 dbl ? "daddi" : "addi",
6304 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
6307 load_register (&icnt, AT, &imm_expr, dbl);
6308 macro_build ((char *) NULL, &icnt, NULL,
6309 dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT);
6315 if (imm_expr.X_op == O_constant
6316 && imm_expr.X_add_number > -0x8000
6317 && imm_expr.X_add_number <= 0x8000)
6319 imm_expr.X_add_number = -imm_expr.X_add_number;
6320 macro_build ((char *) NULL, &icnt, &imm_expr,
6321 dbl ? "daddiu" : "addiu",
6322 "t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
6325 load_register (&icnt, AT, &imm_expr, dbl);
6326 macro_build ((char *) NULL, &icnt, NULL,
6327 dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT);
6348 load_register (&icnt, AT, &imm_expr, 0);
6349 macro_build ((char *) NULL, &icnt, NULL, s, "s,t", sreg, AT);
6354 assert (mips_opts.isa == ISA_MIPS1);
6355 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
6356 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
6359 * Is the double cfc1 instruction a bug in the mips assembler;
6360 * or is there a reason for it?
6362 mips_emit_delays (true);
6363 ++mips_opts.noreorder;
6364 mips_any_noreorder = 1;
6365 macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31);
6366 macro_build ((char *) NULL, &icnt, NULL, "cfc1", "t,G", treg, 31);
6367 macro_build ((char *) NULL, &icnt, NULL, "nop", "");
6368 expr1.X_add_number = 3;
6369 macro_build ((char *) NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg,
6370 (int) BFD_RELOC_LO16);
6371 expr1.X_add_number = 2;
6372 macro_build ((char *) NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT,
6373 (int) BFD_RELOC_LO16);
6374 macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", AT, 31);
6375 macro_build ((char *) NULL, &icnt, NULL, "nop", "");
6376 macro_build ((char *) NULL, &icnt, NULL,
6377 mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S", dreg, sreg);
6378 macro_build ((char *) NULL, &icnt, NULL, "ctc1", "t,G", treg, 31);
6379 macro_build ((char *) NULL, &icnt, NULL, "nop", "");
6380 --mips_opts.noreorder;
6389 if (offset_expr.X_add_number >= 0x7fff)
6390 as_bad (_("operand overflow"));
6391 /* avoid load delay */
6392 if (! target_big_endian)
6393 offset_expr.X_add_number += 1;
6394 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
6395 (int) BFD_RELOC_LO16, breg);
6396 if (! target_big_endian)
6397 offset_expr.X_add_number -= 1;
6399 offset_expr.X_add_number += 1;
6400 macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", AT,
6401 (int) BFD_RELOC_LO16, breg);
6402 macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg, treg, 8);
6403 macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT);
6416 if (offset_expr.X_add_number >= 0x8000 - off)
6417 as_bad (_("operand overflow"));
6418 if (! target_big_endian)
6419 offset_expr.X_add_number += off;
6420 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
6421 (int) BFD_RELOC_LO16, breg);
6422 if (! target_big_endian)
6423 offset_expr.X_add_number -= off;
6425 offset_expr.X_add_number += off;
6426 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg,
6427 (int) BFD_RELOC_LO16, breg);
6440 load_address (&icnt, AT, &offset_expr);
6442 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6443 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6444 "d,v,t", AT, AT, breg);
6445 if (! target_big_endian)
6446 expr1.X_add_number = off;
6448 expr1.X_add_number = 0;
6449 macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg,
6450 (int) BFD_RELOC_LO16, AT);
6451 if (! target_big_endian)
6452 expr1.X_add_number = 0;
6454 expr1.X_add_number = off;
6455 macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg,
6456 (int) BFD_RELOC_LO16, AT);
6461 load_address (&icnt, AT, &offset_expr);
6463 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6464 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6465 "d,v,t", AT, AT, breg);
6466 if (target_big_endian)
6467 expr1.X_add_number = 0;
6468 macro_build ((char *) NULL, &icnt, &expr1,
6469 mask == M_ULH_A ? "lb" : "lbu", "t,o(b)", treg,
6470 (int) BFD_RELOC_LO16, AT);
6471 if (target_big_endian)
6472 expr1.X_add_number = 1;
6474 expr1.X_add_number = 0;
6475 macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT,
6476 (int) BFD_RELOC_LO16, AT);
6477 macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg,
6479 macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg,
6484 if (offset_expr.X_add_number >= 0x7fff)
6485 as_bad (_("operand overflow"));
6486 if (target_big_endian)
6487 offset_expr.X_add_number += 1;
6488 macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg,
6489 (int) BFD_RELOC_LO16, breg);
6490 macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", AT, treg, 8);
6491 if (target_big_endian)
6492 offset_expr.X_add_number -= 1;
6494 offset_expr.X_add_number += 1;
6495 macro_build ((char *) NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT,
6496 (int) BFD_RELOC_LO16, breg);
6509 if (offset_expr.X_add_number >= 0x8000 - off)
6510 as_bad (_("operand overflow"));
6511 if (! target_big_endian)
6512 offset_expr.X_add_number += off;
6513 macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
6514 (int) BFD_RELOC_LO16, breg);
6515 if (! target_big_endian)
6516 offset_expr.X_add_number -= off;
6518 offset_expr.X_add_number += off;
6519 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg,
6520 (int) BFD_RELOC_LO16, breg);
6533 load_address (&icnt, AT, &offset_expr);
6535 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6536 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6537 "d,v,t", AT, AT, breg);
6538 if (! target_big_endian)
6539 expr1.X_add_number = off;
6541 expr1.X_add_number = 0;
6542 macro_build ((char *) NULL, &icnt, &expr1, s, "t,o(b)", treg,
6543 (int) BFD_RELOC_LO16, AT);
6544 if (! target_big_endian)
6545 expr1.X_add_number = 0;
6547 expr1.X_add_number = off;
6548 macro_build ((char *) NULL, &icnt, &expr1, s2, "t,o(b)", treg,
6549 (int) BFD_RELOC_LO16, AT);
6553 load_address (&icnt, AT, &offset_expr);
6555 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6556 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
6557 "d,v,t", AT, AT, breg);
6558 if (! target_big_endian)
6559 expr1.X_add_number = 0;
6560 macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg,
6561 (int) BFD_RELOC_LO16, AT);
6562 macro_build ((char *) NULL, &icnt, NULL, "srl", "d,w,<", treg,
6564 if (! target_big_endian)
6565 expr1.X_add_number = 1;
6567 expr1.X_add_number = 0;
6568 macro_build ((char *) NULL, &icnt, &expr1, "sb", "t,o(b)", treg,
6569 (int) BFD_RELOC_LO16, AT);
6570 if (! target_big_endian)
6571 expr1.X_add_number = 0;
6573 expr1.X_add_number = 1;
6574 macro_build ((char *) NULL, &icnt, &expr1, "lbu", "t,o(b)", AT,
6575 (int) BFD_RELOC_LO16, AT);
6576 macro_build ((char *) NULL, &icnt, NULL, "sll", "d,w,<", treg,
6578 macro_build ((char *) NULL, &icnt, NULL, "or", "d,v,t", treg,
6583 /* FIXME: Check if this is one of the itbl macros, since they
6584 are added dynamically. */
6585 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
6589 as_warn (_("Macro used $at after \".set noat\""));
6592 /* Implement macros in mips16 mode. */
6596 struct mips_cl_insn *ip;
6599 int xreg, yreg, zreg, tmp;
6603 const char *s, *s2, *s3;
6605 mask = ip->insn_mo->mask;
6607 xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
6608 yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY;
6609 zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
6613 expr1.X_op = O_constant;
6614 expr1.X_op_symbol = NULL;
6615 expr1.X_add_symbol = NULL;
6616 expr1.X_add_number = 1;
6635 mips_emit_delays (true);
6636 ++mips_opts.noreorder;
6637 mips_any_noreorder = 1;
6638 macro_build ((char *) NULL, &icnt, NULL,
6639 dbl ? "ddiv" : "div",
6640 "0,x,y", xreg, yreg);
6641 expr1.X_add_number = 2;
6642 macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg);
6643 macro_build ((char *) NULL, &icnt, NULL, "break", "6", 7);
6645 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
6646 since that causes an overflow. We should do that as well,
6647 but I don't see how to do the comparisons without a temporary
6649 --mips_opts.noreorder;
6650 macro_build ((char *) NULL, &icnt, NULL, s, "x", zreg);
6669 mips_emit_delays (true);
6670 ++mips_opts.noreorder;
6671 mips_any_noreorder = 1;
6672 macro_build ((char *) NULL, &icnt, NULL, s, "0,x,y", xreg, yreg);
6673 expr1.X_add_number = 2;
6674 macro_build ((char *) NULL, &icnt, &expr1, "bnez", "x,p", yreg);
6675 macro_build ((char *) NULL, &icnt, NULL, "break", "6", 7);
6676 --mips_opts.noreorder;
6677 macro_build ((char *) NULL, &icnt, NULL, s2, "x", zreg);
6683 macro_build ((char *) NULL, &icnt, NULL,
6684 dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
6685 macro_build ((char *) NULL, &icnt, NULL, "mflo", "x", zreg);
6693 if (imm_expr.X_op != O_constant)
6694 as_bad (_("Unsupported large constant"));
6695 imm_expr.X_add_number = -imm_expr.X_add_number;
6696 macro_build ((char *) NULL, &icnt, &imm_expr,
6697 dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
6701 if (imm_expr.X_op != O_constant)
6702 as_bad (_("Unsupported large constant"));
6703 imm_expr.X_add_number = -imm_expr.X_add_number;
6704 macro_build ((char *) NULL, &icnt, &imm_expr, "addiu",
6709 if (imm_expr.X_op != O_constant)
6710 as_bad (_("Unsupported large constant"));
6711 imm_expr.X_add_number = -imm_expr.X_add_number;
6712 macro_build ((char *) NULL, &icnt, &imm_expr, "daddiu",
6735 goto do_reverse_branch;
6739 goto do_reverse_branch;
6751 goto do_reverse_branch;
6762 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s, "x,y",
6764 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p");
6791 goto do_addone_branch_i;
6796 goto do_addone_branch_i;
6811 goto do_addone_branch_i;
6818 if (imm_expr.X_op != O_constant)
6819 as_bad (_("Unsupported large constant"));
6820 ++imm_expr.X_add_number;
6823 macro_build ((char *) NULL, &icnt, &imm_expr, s, s3, xreg);
6824 macro_build ((char *) NULL, &icnt, &offset_expr, s2, "p");
6828 expr1.X_add_number = 0;
6829 macro_build ((char *) NULL, &icnt, &expr1, "slti", "x,8", yreg);
6831 move_register (&icnt, xreg, yreg);
6832 expr1.X_add_number = 2;
6833 macro_build ((char *) NULL, &icnt, &expr1, "bteqz", "p");
6834 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
6835 "neg", "x,w", xreg, xreg);
6839 /* For consistency checking, verify that all bits are specified either
6840 by the match/mask part of the instruction definition, or by the
6843 validate_mips_insn (opc)
6844 const struct mips_opcode *opc;
6846 const char *p = opc->args;
6848 unsigned long used_bits = opc->mask;
6850 if ((used_bits & opc->match) != opc->match)
6852 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
6853 opc->name, opc->args);
6856 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
6863 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
6864 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
6866 case 'B': USE_BITS (OP_MASK_CODE20, OP_SH_CODE20); break;
6867 case 'C': USE_BITS (OP_MASK_COPZ, OP_SH_COPZ); break;
6868 case 'D': USE_BITS (OP_MASK_FD, OP_SH_FD); break;
6869 case 'E': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
6871 case 'G': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
6872 case 'H': USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
6874 case 'J': USE_BITS (OP_MASK_CODE19, OP_SH_CODE19); break;
6876 case 'M': USE_BITS (OP_MASK_CCC, OP_SH_CCC); break;
6877 case 'N': USE_BITS (OP_MASK_BCC, OP_SH_BCC); break;
6878 case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
6879 case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
6880 case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
6881 case 'V': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
6882 case 'W': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
6883 case 'a': USE_BITS (OP_MASK_TARGET, OP_SH_TARGET); break;
6884 case 'b': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
6885 case 'c': USE_BITS (OP_MASK_CODE, OP_SH_CODE); break;
6886 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
6888 case 'h': USE_BITS (OP_MASK_PREFX, OP_SH_PREFX); break;
6889 case 'i': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
6890 case 'j': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
6891 case 'k': USE_BITS (OP_MASK_CACHE, OP_SH_CACHE); break;
6893 case 'o': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
6894 case 'p': USE_BITS (OP_MASK_DELTA, OP_SH_DELTA); break;
6895 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
6896 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
6897 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
6898 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
6899 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
6900 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
6901 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
6904 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
6905 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
6906 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
6908 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
6909 c, opc->name, opc->args);
6913 if (used_bits != 0xffffffff)
6915 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
6916 ~used_bits & 0xffffffff, opc->name, opc->args);
6922 /* This routine assembles an instruction into its binary format. As a
6923 side effect, it sets one of the global variables imm_reloc or
6924 offset_reloc to the type of relocation to do if one of the operands
6925 is an address expression. */
6930 struct mips_cl_insn *ip;
6935 struct mips_opcode *insn;
6938 unsigned int lastregno = 0;
6941 int full_opcode_match = 1;
6945 /* If the instruction contains a '.', we first try to match an instruction
6946 including the '.'. Then we try again without the '.'. */
6948 for (s = str; *s != '\0' && !ISSPACE (*s); ++s)
6951 /* If we stopped on whitespace, then replace the whitespace with null for
6952 the call to hash_find. Save the character we replaced just in case we
6953 have to re-parse the instruction. */
6960 insn = (struct mips_opcode *) hash_find (op_hash, str);
6962 /* If we didn't find the instruction in the opcode table, try again, but
6963 this time with just the instruction up to, but not including the
6967 /* Restore the character we overwrite above (if any). */
6971 /* Scan up to the first '.' or whitespace. */
6973 *s != '\0' && *s != '.' && !ISSPACE (*s);
6977 /* If we did not find a '.', then we can quit now. */
6980 insn_error = "unrecognized opcode";
6984 /* Lookup the instruction in the hash table. */
6986 if ((insn = (struct mips_opcode *) hash_find (op_hash, str)) == NULL)
6988 insn_error = "unrecognized opcode";
6992 full_opcode_match = 0;
7000 assert (strcmp (insn->name, str) == 0);
7002 if (OPCODE_IS_MEMBER (insn, mips_opts.isa, mips_arch))
7007 if (insn->pinfo != INSN_MACRO)
7009 if (mips_arch == CPU_R4650 && (insn->pinfo & FP_D) != 0)
7015 if (insn + 1 < &mips_opcodes[NUMOPCODES]
7016 && strcmp (insn->name, insn[1].name) == 0)
7025 static char buf[100];
7027 _("opcode not supported on this processor: %s (%s)"),
7028 mips_cpu_to_str (mips_arch),
7029 mips_isa_to_str (mips_opts.isa));
7040 ip->insn_opcode = insn->match;
7042 for (args = insn->args;; ++args)
7048 case '\0': /* end of args */
7061 ip->insn_opcode |= lastregno << OP_SH_RS;
7065 ip->insn_opcode |= lastregno << OP_SH_RT;
7069 ip->insn_opcode |= lastregno << OP_SH_FT;
7073 ip->insn_opcode |= lastregno << OP_SH_FS;
7079 /* Handle optional base register.
7080 Either the base register is omitted or
7081 we must have a left paren. */
7082 /* This is dependent on the next operand specifier
7083 is a base register specification. */
7084 assert (args[1] == 'b' || args[1] == '5'
7085 || args[1] == '-' || args[1] == '4');
7089 case ')': /* these must match exactly */
7094 case '<': /* must be at least one digit */
7096 * According to the manual, if the shift amount is greater
7097 * than 31 or less than 0 the the shift amount should be
7098 * mod 32. In reality the mips assembler issues an error.
7099 * We issue a warning and mask out all but the low 5 bits.
7101 my_getExpression (&imm_expr, s);
7102 check_absolute_expr (ip, &imm_expr);
7103 if ((unsigned long) imm_expr.X_add_number > 31)
7105 as_warn (_("Improper shift amount (%ld)"),
7106 (long) imm_expr.X_add_number);
7107 imm_expr.X_add_number &= OP_MASK_SHAMT;
7109 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SHAMT;
7110 imm_expr.X_op = O_absent;
7114 case '>': /* shift amount minus 32 */
7115 my_getExpression (&imm_expr, s);
7116 check_absolute_expr (ip, &imm_expr);
7117 if ((unsigned long) imm_expr.X_add_number < 32
7118 || (unsigned long) imm_expr.X_add_number > 63)
7120 ip->insn_opcode |= (imm_expr.X_add_number - 32) << OP_SH_SHAMT;
7121 imm_expr.X_op = O_absent;
7125 case 'k': /* cache code */
7126 case 'h': /* prefx code */
7127 my_getExpression (&imm_expr, s);
7128 check_absolute_expr (ip, &imm_expr);
7129 if ((unsigned long) imm_expr.X_add_number > 31)
7131 as_warn (_("Invalid value for `%s' (%lu)"),
7133 (unsigned long) imm_expr.X_add_number);
7134 imm_expr.X_add_number &= 0x1f;
7137 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE;
7139 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX;
7140 imm_expr.X_op = O_absent;
7144 case 'c': /* break code */
7145 my_getExpression (&imm_expr, s);
7146 check_absolute_expr (ip, &imm_expr);
7147 if ((unsigned) imm_expr.X_add_number > 1023)
7149 as_warn (_("Illegal break code (%ld)"),
7150 (long) imm_expr.X_add_number);
7151 imm_expr.X_add_number &= OP_MASK_CODE;
7153 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE;
7154 imm_expr.X_op = O_absent;
7158 case 'q': /* lower break code */
7159 my_getExpression (&imm_expr, s);
7160 check_absolute_expr (ip, &imm_expr);
7161 if ((unsigned) imm_expr.X_add_number > 1023)
7163 as_warn (_("Illegal lower break code (%ld)"),
7164 (long) imm_expr.X_add_number);
7165 imm_expr.X_add_number &= OP_MASK_CODE2;
7167 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE2;
7168 imm_expr.X_op = O_absent;
7172 case 'B': /* 20-bit syscall/break code. */
7173 my_getExpression (&imm_expr, s);
7174 check_absolute_expr (ip, &imm_expr);
7175 if ((unsigned) imm_expr.X_add_number > OP_MASK_CODE20)
7176 as_warn (_("Illegal 20-bit code (%ld)"),
7177 (long) imm_expr.X_add_number);
7178 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE20;
7179 imm_expr.X_op = O_absent;
7183 case 'C': /* Coprocessor code */
7184 my_getExpression (&imm_expr, s);
7185 check_absolute_expr (ip, &imm_expr);
7186 if ((unsigned long) imm_expr.X_add_number >= (1<<25))
7188 as_warn (_("Coproccesor code > 25 bits (%ld)"),
7189 (long) imm_expr.X_add_number);
7190 imm_expr.X_add_number &= ((1<<25) - 1);
7192 ip->insn_opcode |= imm_expr.X_add_number;
7193 imm_expr.X_op = O_absent;
7197 case 'J': /* 19-bit wait code. */
7198 my_getExpression (&imm_expr, s);
7199 check_absolute_expr (ip, &imm_expr);
7200 if ((unsigned) imm_expr.X_add_number > OP_MASK_CODE19)
7201 as_warn (_("Illegal 19-bit code (%ld)"),
7202 (long) imm_expr.X_add_number);
7203 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE19;
7204 imm_expr.X_op = O_absent;
7208 case 'P': /* Performance register */
7209 my_getExpression (&imm_expr, s);
7210 check_absolute_expr (ip, &imm_expr);
7211 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
7213 as_warn (_("Invalid performance register (%ld)"),
7214 (long) imm_expr.X_add_number);
7215 imm_expr.X_add_number &= OP_MASK_PERFREG;
7217 ip->insn_opcode |= (imm_expr.X_add_number << OP_SH_PERFREG);
7218 imm_expr.X_op = O_absent;
7222 case 'b': /* base register */
7223 case 'd': /* destination register */
7224 case 's': /* source register */
7225 case 't': /* target register */
7226 case 'r': /* both target and source */
7227 case 'v': /* both dest and source */
7228 case 'w': /* both dest and target */
7229 case 'E': /* coprocessor target register */
7230 case 'G': /* coprocessor destination register */
7231 case 'x': /* ignore register name */
7232 case 'z': /* must be zero register */
7233 case 'U': /* destination register (clo/clz). */
7248 while (ISDIGIT (*s));
7250 as_bad (_("Invalid register number (%d)"), regno);
7252 else if (*args == 'E' || *args == 'G')
7256 if (s[1] == 'f' && s[2] == 'p')
7261 else if (s[1] == 's' && s[2] == 'p')
7266 else if (s[1] == 'g' && s[2] == 'p')
7271 else if (s[1] == 'a' && s[2] == 't')
7276 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
7281 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
7286 else if (itbl_have_entries)
7291 p = s + 1; /* advance past '$' */
7292 n = itbl_get_field (&p); /* n is name */
7294 /* See if this is a register defined in an
7296 if (itbl_get_reg_val (n, &r))
7298 /* Get_field advances to the start of
7299 the next field, so we need to back
7300 rack to the end of the last field. */
7304 s = strchr (s, '\0');
7317 as_warn (_("Used $at without \".set noat\""));
7323 if (c == 'r' || c == 'v' || c == 'w')
7330 /* 'z' only matches $0. */
7331 if (c == 'z' && regno != 0)
7334 /* Now that we have assembled one operand, we use the args string
7335 * to figure out where it goes in the instruction. */
7342 ip->insn_opcode |= regno << OP_SH_RS;
7346 ip->insn_opcode |= regno << OP_SH_RD;
7349 ip->insn_opcode |= regno << OP_SH_RD;
7350 ip->insn_opcode |= regno << OP_SH_RT;
7355 ip->insn_opcode |= regno << OP_SH_RT;
7358 /* This case exists because on the r3000 trunc
7359 expands into a macro which requires a gp
7360 register. On the r6000 or r4000 it is
7361 assembled into a single instruction which
7362 ignores the register. Thus the insn version
7363 is MIPS_ISA2 and uses 'x', and the macro
7364 version is MIPS_ISA1 and uses 't'. */
7367 /* This case is for the div instruction, which
7368 acts differently if the destination argument
7369 is $0. This only matches $0, and is checked
7370 outside the switch. */
7373 /* Itbl operand; not yet implemented. FIXME ?? */
7375 /* What about all other operands like 'i', which
7376 can be specified in the opcode table? */
7386 ip->insn_opcode |= lastregno << OP_SH_RS;
7389 ip->insn_opcode |= lastregno << OP_SH_RT;
7394 case 'D': /* floating point destination register */
7395 case 'S': /* floating point source register */
7396 case 'T': /* floating point target register */
7397 case 'R': /* floating point source register */
7401 if (s[0] == '$' && s[1] == 'f'
7412 while (ISDIGIT (*s));
7415 as_bad (_("Invalid float register number (%d)"), regno);
7417 if ((regno & 1) != 0
7419 && ! (strcmp (str, "mtc1") == 0
7420 || strcmp (str, "mfc1") == 0
7421 || strcmp (str, "lwc1") == 0
7422 || strcmp (str, "swc1") == 0
7423 || strcmp (str, "l.s") == 0
7424 || strcmp (str, "s.s") == 0))
7425 as_warn (_("Float register should be even, was %d"),
7433 if (c == 'V' || c == 'W')
7443 ip->insn_opcode |= regno << OP_SH_FD;
7447 ip->insn_opcode |= regno << OP_SH_FS;
7451 ip->insn_opcode |= regno << OP_SH_FT;
7454 ip->insn_opcode |= regno << OP_SH_FR;
7464 ip->insn_opcode |= lastregno << OP_SH_FS;
7467 ip->insn_opcode |= lastregno << OP_SH_FT;
7473 my_getExpression (&imm_expr, s);
7474 if (imm_expr.X_op != O_big
7475 && imm_expr.X_op != O_constant)
7476 insn_error = _("absolute expression required");
7481 my_getExpression (&offset_expr, s);
7482 imm_reloc = BFD_RELOC_32;
7495 unsigned char temp[8];
7497 unsigned int length;
7502 /* These only appear as the last operand in an
7503 instruction, and every instruction that accepts
7504 them in any variant accepts them in all variants.
7505 This means we don't have to worry about backing out
7506 any changes if the instruction does not match.
7508 The difference between them is the size of the
7509 floating point constant and where it goes. For 'F'
7510 and 'L' the constant is 64 bits; for 'f' and 'l' it
7511 is 32 bits. Where the constant is placed is based
7512 on how the MIPS assembler does things:
7515 f -- immediate value
7518 The .lit4 and .lit8 sections are only used if
7519 permitted by the -G argument.
7521 When generating embedded PIC code, we use the
7522 .lit8 section but not the .lit4 section (we can do
7523 .lit4 inline easily; we need to put .lit8
7524 somewhere in the data segment, and using .lit8
7525 permits the linker to eventually combine identical
7528 The code below needs to know whether the target register
7529 is 32 or 64 bits wide. It relies on the fact 'f' and
7530 'F' are used with GPR-based instructions and 'l' and
7531 'L' are used with FPR-based instructions. */
7533 f64 = *args == 'F' || *args == 'L';
7534 using_gprs = *args == 'F' || *args == 'f';
7536 save_in = input_line_pointer;
7537 input_line_pointer = s;
7538 err = md_atof (f64 ? 'd' : 'f', (char *) temp, &len);
7540 s = input_line_pointer;
7541 input_line_pointer = save_in;
7542 if (err != NULL && *err != '\0')
7544 as_bad (_("Bad floating point constant: %s"), err);
7545 memset (temp, '\0', sizeof temp);
7546 length = f64 ? 8 : 4;
7549 assert (length == (unsigned) (f64 ? 8 : 4));
7553 && (! USE_GLOBAL_POINTER_OPT
7554 || mips_pic == EMBEDDED_PIC
7555 || g_switch_value < 4
7556 || (temp[0] == 0 && temp[1] == 0)
7557 || (temp[2] == 0 && temp[3] == 0))))
7559 imm_expr.X_op = O_constant;
7560 if (! target_big_endian)
7561 imm_expr.X_add_number = bfd_getl32 (temp);
7563 imm_expr.X_add_number = bfd_getb32 (temp);
7566 && ! mips_disable_float_construction
7567 /* Constants can only be constructed in GPRs and
7568 copied to FPRs if the GPRs are at least as wide
7569 as the FPRs. Force the constant into memory if
7570 we are using 64-bit FPRs but the GPRs are only
7573 || ! (HAVE_64BIT_FPRS && HAVE_32BIT_GPRS))
7574 && ((temp[0] == 0 && temp[1] == 0)
7575 || (temp[2] == 0 && temp[3] == 0))
7576 && ((temp[4] == 0 && temp[5] == 0)
7577 || (temp[6] == 0 && temp[7] == 0)))
7579 /* The value is simple enough to load with a couple of
7580 instructions. If using 32-bit registers, set
7581 imm_expr to the high order 32 bits and offset_expr to
7582 the low order 32 bits. Otherwise, set imm_expr to
7583 the entire 64 bit constant. */
7584 if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS)
7586 imm_expr.X_op = O_constant;
7587 offset_expr.X_op = O_constant;
7588 if (! target_big_endian)
7590 imm_expr.X_add_number = bfd_getl32 (temp + 4);
7591 offset_expr.X_add_number = bfd_getl32 (temp);
7595 imm_expr.X_add_number = bfd_getb32 (temp);
7596 offset_expr.X_add_number = bfd_getb32 (temp + 4);
7598 if (offset_expr.X_add_number == 0)
7599 offset_expr.X_op = O_absent;
7601 else if (sizeof (imm_expr.X_add_number) > 4)
7603 imm_expr.X_op = O_constant;
7604 if (! target_big_endian)
7605 imm_expr.X_add_number = bfd_getl64 (temp);
7607 imm_expr.X_add_number = bfd_getb64 (temp);
7611 imm_expr.X_op = O_big;
7612 imm_expr.X_add_number = 4;
7613 if (! target_big_endian)
7615 generic_bignum[0] = bfd_getl16 (temp);
7616 generic_bignum[1] = bfd_getl16 (temp + 2);
7617 generic_bignum[2] = bfd_getl16 (temp + 4);
7618 generic_bignum[3] = bfd_getl16 (temp + 6);
7622 generic_bignum[0] = bfd_getb16 (temp + 6);
7623 generic_bignum[1] = bfd_getb16 (temp + 4);
7624 generic_bignum[2] = bfd_getb16 (temp + 2);
7625 generic_bignum[3] = bfd_getb16 (temp);
7631 const char *newname;
7634 /* Switch to the right section. */
7636 subseg = now_subseg;
7639 default: /* unused default case avoids warnings. */
7641 newname = RDATA_SECTION_NAME;
7642 if ((USE_GLOBAL_POINTER_OPT && g_switch_value >= 8)
7643 || mips_pic == EMBEDDED_PIC)
7647 if (mips_pic == EMBEDDED_PIC)
7650 newname = RDATA_SECTION_NAME;
7653 assert (!USE_GLOBAL_POINTER_OPT
7654 || g_switch_value >= 4);
7658 new_seg = subseg_new (newname, (subsegT) 0);
7659 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
7660 bfd_set_section_flags (stdoutput, new_seg,
7665 frag_align (*args == 'l' ? 2 : 3, 0, 0);
7666 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
7667 && strcmp (TARGET_OS, "elf") != 0)
7668 record_alignment (new_seg, 4);
7670 record_alignment (new_seg, *args == 'l' ? 2 : 3);
7672 as_bad (_("Can't use floating point insn in this section"));
7674 /* Set the argument to the current address in the
7676 offset_expr.X_op = O_symbol;
7677 offset_expr.X_add_symbol =
7678 symbol_new ("L0\001", now_seg,
7679 (valueT) frag_now_fix (), frag_now);
7680 offset_expr.X_add_number = 0;
7682 /* Put the floating point number into the section. */
7683 p = frag_more ((int) length);
7684 memcpy (p, temp, length);
7686 /* Switch back to the original section. */
7687 subseg_set (seg, subseg);
7692 case 'i': /* 16 bit unsigned immediate */
7693 case 'j': /* 16 bit signed immediate */
7694 imm_reloc = BFD_RELOC_LO16;
7695 c = my_getSmallExpression (&imm_expr, s);
7700 if (imm_expr.X_op == O_constant)
7701 imm_expr.X_add_number =
7702 (imm_expr.X_add_number >> 16) & 0xffff;
7703 else if (c == S_EX_HIGHEST)
7704 imm_reloc = BFD_RELOC_MIPS_HIGHEST;
7705 else if (c == S_EX_HIGHER)
7706 imm_reloc = BFD_RELOC_MIPS_HIGHER;
7707 else if (c == S_EX_HI)
7709 imm_reloc = BFD_RELOC_HI16_S;
7710 imm_unmatched_hi = true;
7713 imm_reloc = BFD_RELOC_HI16;
7715 else if (imm_expr.X_op == O_constant)
7716 imm_expr.X_add_number &= 0xffff;
7720 if ((c == S_EX_NONE && imm_expr.X_op != O_constant)
7721 || ((imm_expr.X_add_number < 0
7722 || imm_expr.X_add_number >= 0x10000)
7723 && imm_expr.X_op == O_constant))
7725 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
7726 !strcmp (insn->name, insn[1].name))
7728 if (imm_expr.X_op == O_constant
7729 || imm_expr.X_op == O_big)
7730 as_bad (_("16 bit expression not in range 0..65535"));
7738 /* The upper bound should be 0x8000, but
7739 unfortunately the MIPS assembler accepts numbers
7740 from 0x8000 to 0xffff and sign extends them, and
7741 we want to be compatible. We only permit this
7742 extended range for an instruction which does not
7743 provide any further alternates, since those
7744 alternates may handle other cases. People should
7745 use the numbers they mean, rather than relying on
7746 a mysterious sign extension. */
7747 more = (insn + 1 < &mips_opcodes[NUMOPCODES] &&
7748 strcmp (insn->name, insn[1].name) == 0);
7753 if ((c == S_EX_NONE && imm_expr.X_op != O_constant)
7754 || ((imm_expr.X_add_number < -0x8000
7755 || imm_expr.X_add_number >= max)
7756 && imm_expr.X_op == O_constant)
7758 && imm_expr.X_add_number < 0
7760 && imm_expr.X_unsigned
7761 && sizeof (imm_expr.X_add_number) <= 4))
7765 if (imm_expr.X_op == O_constant
7766 || imm_expr.X_op == O_big)
7767 as_bad (_("16 bit expression not in range -32768..32767"));
7773 case 'o': /* 16 bit offset */
7774 c = my_getSmallExpression (&offset_expr, s);
7776 /* If this value won't fit into a 16 bit offset, then go
7777 find a macro that will generate the 32 bit offset
7778 code pattern. As a special hack, we accept the
7779 difference of two local symbols as a constant. This
7780 is required to suppose embedded PIC switches, which
7781 use an instruction which looks like
7782 lw $4,$L12-$LS12($4)
7783 The problem with handling this in a more general
7784 fashion is that the macro function doesn't expect to
7785 see anything which can be handled in a single
7786 constant instruction. */
7788 && (offset_expr.X_op != O_constant
7789 || offset_expr.X_add_number >= 0x8000
7790 || offset_expr.X_add_number < -0x8000)
7791 && (mips_pic != EMBEDDED_PIC
7792 || offset_expr.X_op != O_subtract
7793 || (S_GET_SEGMENT (offset_expr.X_add_symbol)
7794 != S_GET_SEGMENT (offset_expr.X_op_symbol))))
7799 if (offset_expr.X_op != O_constant)
7801 offset_expr.X_add_number =
7802 (offset_expr.X_add_number >> 16) & 0xffff;
7804 offset_reloc = BFD_RELOC_LO16;
7808 case 'p': /* pc relative offset */
7809 if (mips_pic == EMBEDDED_PIC)
7810 offset_reloc = BFD_RELOC_16_PCREL_S2;
7812 offset_reloc = BFD_RELOC_16_PCREL;
7813 my_getExpression (&offset_expr, s);
7817 case 'u': /* upper 16 bits */
7818 c = my_getSmallExpression (&imm_expr, s);
7819 imm_reloc = BFD_RELOC_LO16;
7824 if (imm_expr.X_op == O_constant)
7825 imm_expr.X_add_number =
7826 (imm_expr.X_add_number >> 16) & 0xffff;
7827 else if (c == S_EX_HIGHEST)
7828 imm_reloc = BFD_RELOC_MIPS_HIGHEST;
7829 else if (c == S_EX_HI)
7831 imm_reloc = BFD_RELOC_HI16_S;
7832 imm_unmatched_hi = true;
7835 imm_reloc = BFD_RELOC_HI16;
7837 else if (imm_expr.X_op == O_constant)
7838 imm_expr.X_add_number &= 0xffff;
7840 if (imm_expr.X_op == O_constant
7841 && (imm_expr.X_add_number < 0
7842 || imm_expr.X_add_number >= 0x10000))
7843 as_bad (_("lui expression not in range 0..65535"));
7847 case 'a': /* 26 bit address */
7848 my_getExpression (&offset_expr, s);
7850 offset_reloc = BFD_RELOC_MIPS_JMP;
7853 case 'N': /* 3 bit branch condition code */
7854 case 'M': /* 3 bit compare condition code */
7855 if (strncmp (s, "$fcc", 4) != 0)
7865 while (ISDIGIT (*s));
7867 as_bad (_("invalid condition code register $fcc%d"), regno);
7869 ip->insn_opcode |= regno << OP_SH_BCC;
7871 ip->insn_opcode |= regno << OP_SH_CCC;
7875 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
7886 while (ISDIGIT (*s));
7889 c = 8; /* Invalid sel value. */
7892 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
7893 ip->insn_opcode |= c;
7897 as_bad (_("bad char = '%c'\n"), *args);
7902 /* Args don't match. */
7903 if (insn + 1 < &mips_opcodes[NUMOPCODES] &&
7904 !strcmp (insn->name, insn[1].name))
7908 insn_error = _("illegal operands");
7913 insn_error = _("illegal operands");
7918 /* This routine assembles an instruction into its binary format when
7919 assembling for the mips16. As a side effect, it sets one of the
7920 global variables imm_reloc or offset_reloc to the type of
7921 relocation to do if one of the operands is an address expression.
7922 It also sets mips16_small and mips16_ext if the user explicitly
7923 requested a small or extended instruction. */
7928 struct mips_cl_insn *ip;
7932 struct mips_opcode *insn;
7935 unsigned int lastregno = 0;
7940 mips16_small = false;
7943 for (s = str; ISLOWER (*s); ++s)
7955 if (s[1] == 't' && s[2] == ' ')
7958 mips16_small = true;
7962 else if (s[1] == 'e' && s[2] == ' ')
7971 insn_error = _("unknown opcode");
7975 if (mips_opts.noautoextend && ! mips16_ext)
7976 mips16_small = true;
7978 if ((insn = (struct mips_opcode *) hash_find (mips16_op_hash, str)) == NULL)
7980 insn_error = _("unrecognized opcode");
7987 assert (strcmp (insn->name, str) == 0);
7990 ip->insn_opcode = insn->match;
7991 ip->use_extend = false;
7992 imm_expr.X_op = O_absent;
7993 imm_reloc = BFD_RELOC_UNUSED;
7994 offset_expr.X_op = O_absent;
7995 offset_reloc = BFD_RELOC_UNUSED;
7996 for (args = insn->args; 1; ++args)
8003 /* In this switch statement we call break if we did not find
8004 a match, continue if we did find a match, or return if we
8013 /* Stuff the immediate value in now, if we can. */
8014 if (imm_expr.X_op == O_constant
8015 && imm_reloc > BFD_RELOC_UNUSED
8016 && insn->pinfo != INSN_MACRO)
8018 mips16_immed ((char *) NULL, 0,
8019 imm_reloc - BFD_RELOC_UNUSED,
8020 imm_expr.X_add_number, true, mips16_small,
8021 mips16_ext, &ip->insn_opcode,
8022 &ip->use_extend, &ip->extend);
8023 imm_expr.X_op = O_absent;
8024 imm_reloc = BFD_RELOC_UNUSED;
8038 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
8041 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
8057 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
8059 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
8086 while (ISDIGIT (*s));
8089 as_bad (_("invalid register number (%d)"), regno);
8095 if (s[1] == 'f' && s[2] == 'p')
8100 else if (s[1] == 's' && s[2] == 'p')
8105 else if (s[1] == 'g' && s[2] == 'p')
8110 else if (s[1] == 'a' && s[2] == 't')
8115 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
8120 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
8133 if (c == 'v' || c == 'w')
8135 regno = mips16_to_32_reg_map[lastregno];
8149 regno = mips32_to_16_reg_map[regno];
8154 regno = ILLEGAL_REG;
8159 regno = ILLEGAL_REG;
8164 regno = ILLEGAL_REG;
8169 if (regno == AT && ! mips_opts.noat)
8170 as_warn (_("used $at without \".set noat\""));
8177 if (regno == ILLEGAL_REG)
8184 ip->insn_opcode |= regno << MIPS16OP_SH_RX;
8188 ip->insn_opcode |= regno << MIPS16OP_SH_RY;
8191 ip->insn_opcode |= regno << MIPS16OP_SH_RZ;
8194 ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z;
8200 ip->insn_opcode |= regno << MIPS16OP_SH_REGR32;
8203 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
8204 ip->insn_opcode |= regno << MIPS16OP_SH_REG32R;
8214 if (strncmp (s, "$pc", 3) == 0)
8238 && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0)
8240 /* This is %gprel(SYMBOL). We need to read SYMBOL,
8241 and generate the appropriate reloc. If the text
8242 inside %gprel is not a symbol name with an
8243 optional offset, then we generate a normal reloc
8244 and will probably fail later. */
8245 my_getExpression (&imm_expr, s + sizeof "%gprel" - 1);
8246 if (imm_expr.X_op == O_symbol)
8249 imm_reloc = BFD_RELOC_MIPS16_GPREL;
8251 ip->use_extend = true;
8258 /* Just pick up a normal expression. */
8259 my_getExpression (&imm_expr, s);
8262 if (imm_expr.X_op == O_register)
8264 /* What we thought was an expression turned out to
8267 if (s[0] == '(' && args[1] == '(')
8269 /* It looks like the expression was omitted
8270 before a register indirection, which means
8271 that the expression is implicitly zero. We
8272 still set up imm_expr, so that we handle
8273 explicit extensions correctly. */
8274 imm_expr.X_op = O_constant;
8275 imm_expr.X_add_number = 0;
8276 imm_reloc = (int) BFD_RELOC_UNUSED + c;
8283 /* We need to relax this instruction. */
8284 imm_reloc = (int) BFD_RELOC_UNUSED + c;
8293 /* We use offset_reloc rather than imm_reloc for the PC
8294 relative operands. This lets macros with both
8295 immediate and address operands work correctly. */
8296 my_getExpression (&offset_expr, s);
8298 if (offset_expr.X_op == O_register)
8301 /* We need to relax this instruction. */
8302 offset_reloc = (int) BFD_RELOC_UNUSED + c;
8306 case '6': /* break code */
8307 my_getExpression (&imm_expr, s);
8308 check_absolute_expr (ip, &imm_expr);
8309 if ((unsigned long) imm_expr.X_add_number > 63)
8311 as_warn (_("Invalid value for `%s' (%lu)"),
8313 (unsigned long) imm_expr.X_add_number);
8314 imm_expr.X_add_number &= 0x3f;
8316 ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6;
8317 imm_expr.X_op = O_absent;
8321 case 'a': /* 26 bit address */
8322 my_getExpression (&offset_expr, s);
8324 offset_reloc = BFD_RELOC_MIPS16_JMP;
8325 ip->insn_opcode <<= 16;
8328 case 'l': /* register list for entry macro */
8329 case 'L': /* register list for exit macro */
8339 int freg, reg1, reg2;
8341 while (*s == ' ' || *s == ',')
8345 as_bad (_("can't parse register list"));
8357 while (ISDIGIT (*s))
8379 as_bad (_("invalid register list"));
8384 while (ISDIGIT (*s))
8391 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
8396 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
8401 else if (reg1 == 4 && reg2 >= 4 && reg2 <= 7 && c != 'L')
8402 mask |= (reg2 - 3) << 3;
8403 else if (reg1 == 16 && reg2 >= 16 && reg2 <= 17)
8404 mask |= (reg2 - 15) << 1;
8405 else if (reg1 == 31 && reg2 == 31)
8409 as_bad (_("invalid register list"));
8413 /* The mask is filled in in the opcode table for the
8414 benefit of the disassembler. We remove it before
8415 applying the actual mask. */
8416 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
8417 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
8421 case 'e': /* extend code */
8422 my_getExpression (&imm_expr, s);
8423 check_absolute_expr (ip, &imm_expr);
8424 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
8426 as_warn (_("Invalid value for `%s' (%lu)"),
8428 (unsigned long) imm_expr.X_add_number);
8429 imm_expr.X_add_number &= 0x7ff;
8431 ip->insn_opcode |= imm_expr.X_add_number;
8432 imm_expr.X_op = O_absent;
8442 /* Args don't match. */
8443 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes] &&
8444 strcmp (insn->name, insn[1].name) == 0)
8451 insn_error = _("illegal operands");
8457 /* This structure holds information we know about a mips16 immediate
8460 struct mips16_immed_operand
8462 /* The type code used in the argument string in the opcode table. */
8464 /* The number of bits in the short form of the opcode. */
8466 /* The number of bits in the extended form of the opcode. */
8468 /* The amount by which the short form is shifted when it is used;
8469 for example, the sw instruction has a shift count of 2. */
8471 /* The amount by which the short form is shifted when it is stored
8472 into the instruction code. */
8474 /* Non-zero if the short form is unsigned. */
8476 /* Non-zero if the extended form is unsigned. */
8478 /* Non-zero if the value is PC relative. */
8482 /* The mips16 immediate operand types. */
8484 static const struct mips16_immed_operand mips16_immed_operands[] =
8486 { '<', 3, 5, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
8487 { '>', 3, 5, 0, MIPS16OP_SH_RX, 1, 1, 0 },
8488 { '[', 3, 6, 0, MIPS16OP_SH_RZ, 1, 1, 0 },
8489 { ']', 3, 6, 0, MIPS16OP_SH_RX, 1, 1, 0 },
8490 { '4', 4, 15, 0, MIPS16OP_SH_IMM4, 0, 0, 0 },
8491 { '5', 5, 16, 0, MIPS16OP_SH_IMM5, 1, 0, 0 },
8492 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5, 1, 0, 0 },
8493 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 0 },
8494 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 0 },
8495 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5, 0, 0, 0 },
8496 { '8', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 0, 0 },
8497 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 0 },
8498 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8, 1, 0, 0 },
8499 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8, 1, 1, 0 },
8500 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 0 },
8501 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8, 0, 0, 0 },
8502 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
8503 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8, 0, 0, 1 },
8504 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8, 1, 0, 1 },
8505 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5, 1, 0, 1 },
8506 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5, 1, 0, 1 }
8509 #define MIPS16_NUM_IMMED \
8510 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
8512 /* Handle a mips16 instruction with an immediate value. This or's the
8513 small immediate value into *INSN. It sets *USE_EXTEND to indicate
8514 whether an extended value is needed; if one is needed, it sets
8515 *EXTEND to the value. The argument type is TYPE. The value is VAL.
8516 If SMALL is true, an unextended opcode was explicitly requested.
8517 If EXT is true, an extended opcode was explicitly requested. If
8518 WARN is true, warn if EXT does not match reality. */
8521 mips16_immed (file, line, type, val, warn, small, ext, insn, use_extend,
8530 unsigned long *insn;
8531 boolean *use_extend;
8532 unsigned short *extend;
8534 register const struct mips16_immed_operand *op;
8535 int mintiny, maxtiny;
8538 op = mips16_immed_operands;
8539 while (op->type != type)
8542 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
8547 if (type == '<' || type == '>' || type == '[' || type == ']')
8550 maxtiny = 1 << op->nbits;
8555 maxtiny = (1 << op->nbits) - 1;
8560 mintiny = - (1 << (op->nbits - 1));
8561 maxtiny = (1 << (op->nbits - 1)) - 1;
8564 /* Branch offsets have an implicit 0 in the lowest bit. */
8565 if (type == 'p' || type == 'q')
8568 if ((val & ((1 << op->shift) - 1)) != 0
8569 || val < (mintiny << op->shift)
8570 || val > (maxtiny << op->shift))
8575 if (warn && ext && ! needext)
8576 as_warn_where (file, line,
8577 _("extended operand requested but not required"));
8578 if (small && needext)
8579 as_bad_where (file, line, _("invalid unextended operand value"));
8581 if (small || (! ext && ! needext))
8585 *use_extend = false;
8586 insnval = ((val >> op->shift) & ((1 << op->nbits) - 1));
8587 insnval <<= op->op_shift;
8592 long minext, maxext;
8598 maxext = (1 << op->extbits) - 1;
8602 minext = - (1 << (op->extbits - 1));
8603 maxext = (1 << (op->extbits - 1)) - 1;
8605 if (val < minext || val > maxext)
8606 as_bad_where (file, line,
8607 _("operand value out of range for instruction"));
8610 if (op->extbits == 16)
8612 extval = ((val >> 11) & 0x1f) | (val & 0x7e0);
8615 else if (op->extbits == 15)
8617 extval = ((val >> 11) & 0xf) | (val & 0x7f0);
8622 extval = ((val & 0x1f) << 6) | (val & 0x20);
8626 *extend = (unsigned short) extval;
8633 my_getSmallExpression (ep, str)
8645 else if (str[0] == '%'
8646 && TOLOWER (str[1]) == 'l'
8647 && TOLOWER (str[2]) == 'o'
8651 str += sizeof ("%lo(") - 2;
8653 else if (str[0] == '%'
8654 && TOLOWER (str[1]) == 'h'
8655 && TOLOWER (str[2]) == 'i'
8659 str += sizeof ("%hi(") - 2;
8661 else if (str[0] == '%'
8662 && TOLOWER (str[1]) == 'h'
8663 && TOLOWER (str[2]) == 'i'
8664 && TOLOWER (str[3]) == 'g'
8665 && TOLOWER (str[4]) == 'h'
8666 && TOLOWER (str[5]) == 'e'
8667 && TOLOWER (str[6]) == 'r'
8671 str += sizeof ("%higher(") - 2;
8673 else if (str[0] == '%'
8674 && TOLOWER (str[1]) == 'h'
8675 && TOLOWER (str[2]) == 'i'
8676 && TOLOWER (str[3]) == 'g'
8677 && TOLOWER (str[4]) == 'h'
8678 && TOLOWER (str[5]) == 'e'
8679 && TOLOWER (str[6]) == 's'
8680 && TOLOWER (str[7]) == 't'
8684 str += sizeof ("%highest(") - 2;
8686 /* currently unsupported */
8688 else if (str[0] == '%'
8689 && TOLOWER (str[1]) == 'g'
8690 && TOLOWER (str[2]) == 'p'
8691 && TOLOWER (str[3]) == '_'
8692 && TOLOWER (str[4]) == 'r'
8693 && TOLOWER (str[5]) == 'e'
8694 && TOLOWER (str[6]) == 'l'
8698 str += sizeof ("%gp_rel(") - 2;
8700 else if (str[0] == '%'
8701 && TOLOWER (str[1]) == 'n'
8702 && TOLOWER (str[2]) == 'e'
8703 && TOLOWER (str[3]) == 'g'
8707 str += sizeof ("%neg(") - 2;
8712 my_getExpression (ep, str);
8717 * A small expression may be followed by a base register.
8718 * Scan to the end of this operand, and then back over a possible
8719 * base register. Then scan the small expression up to that
8720 * point. (Based on code in sparc.c...)
8722 for (sp = str; *sp && *sp != ','; sp++)
8724 if (sp - 4 >= str && sp[-1] == ')')
8726 if (ISDIGIT (sp[-2]))
8728 for (sp -= 3; sp >= str && ISDIGIT (*sp); sp--)
8730 if (*sp == '$' && sp > str && sp[-1] == '(')
8736 else if (sp - 5 >= str
8739 && ((sp[-3] == 'f' && sp[-2] == 'p')
8740 || (sp[-3] == 's' && sp[-2] == 'p')
8741 || (sp[-3] == 'g' && sp[-2] == 'p')
8742 || (sp[-3] == 'a' && sp[-2] == 't')))
8748 /* no expression means zero offset */
8751 /* %xx(reg) is an error */
8752 ep->X_op = O_absent;
8757 ep->X_op = O_constant;
8760 ep->X_add_symbol = NULL;
8761 ep->X_op_symbol = NULL;
8762 ep->X_add_number = 0;
8767 my_getExpression (ep, str);
8773 my_getExpression (ep, str);
8775 /* => %highest, %higher, %hi, %lo, %gprel, %neg encountered */
8780 my_getExpression (ep, str)
8787 save_in = input_line_pointer;
8788 input_line_pointer = str;
8790 expr_end = input_line_pointer;
8791 input_line_pointer = save_in;
8793 /* If we are in mips16 mode, and this is an expression based on `.',
8794 then we bump the value of the symbol by 1 since that is how other
8795 text symbols are handled. We don't bother to handle complex
8796 expressions, just `.' plus or minus a constant. */
8797 if (mips_opts.mips16
8798 && ep->X_op == O_symbol
8799 && strcmp (S_GET_NAME (ep->X_add_symbol), FAKE_LABEL_NAME) == 0
8800 && S_GET_SEGMENT (ep->X_add_symbol) == now_seg
8801 && symbol_get_frag (ep->X_add_symbol) == frag_now
8802 && symbol_constant_p (ep->X_add_symbol)
8803 && (val = S_GET_VALUE (ep->X_add_symbol)) == frag_now_fix ())
8804 S_SET_VALUE (ep->X_add_symbol, val + 1);
8807 /* Turn a string in input_line_pointer into a floating point constant
8808 of type TYPE, and store the appropriate bytes in *LITP. The number
8809 of LITTLENUMS emitted is stored in *SIZEP. An error message is
8810 returned, or NULL on OK. */
8813 md_atof (type, litP, sizeP)
8819 LITTLENUM_TYPE words[4];
8835 return _("bad call to md_atof");
8838 t = atof_ieee (input_line_pointer, type, words);
8840 input_line_pointer = t;
8844 if (! target_big_endian)
8846 for (i = prec - 1; i >= 0; i--)
8848 md_number_to_chars (litP, (valueT) words[i], 2);
8854 for (i = 0; i < prec; i++)
8856 md_number_to_chars (litP, (valueT) words[i], 2);
8865 md_number_to_chars (buf, val, n)
8870 if (target_big_endian)
8871 number_to_chars_bigendian (buf, val, n);
8873 number_to_chars_littleendian (buf, val, n);
8876 CONST char *md_shortopts = "nO::g::G:";
8878 struct option md_longopts[] =
8880 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
8881 {"mips0", no_argument, NULL, OPTION_MIPS1},
8882 {"mips1", no_argument, NULL, OPTION_MIPS1},
8883 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
8884 {"mips2", no_argument, NULL, OPTION_MIPS2},
8885 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
8886 {"mips3", no_argument, NULL, OPTION_MIPS3},
8887 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
8888 {"mips4", no_argument, NULL, OPTION_MIPS4},
8889 #define OPTION_MCPU (OPTION_MD_BASE + 5)
8890 {"mcpu", required_argument, NULL, OPTION_MCPU},
8891 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
8892 {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC},
8893 #define OPTION_TRAP (OPTION_MD_BASE + 7)
8894 {"trap", no_argument, NULL, OPTION_TRAP},
8895 {"no-break", no_argument, NULL, OPTION_TRAP},
8896 #define OPTION_BREAK (OPTION_MD_BASE + 8)
8897 {"break", no_argument, NULL, OPTION_BREAK},
8898 {"no-trap", no_argument, NULL, OPTION_BREAK},
8899 #define OPTION_EB (OPTION_MD_BASE + 9)
8900 {"EB", no_argument, NULL, OPTION_EB},
8901 #define OPTION_EL (OPTION_MD_BASE + 10)
8902 {"EL", no_argument, NULL, OPTION_EL},
8903 #define OPTION_M4650 (OPTION_MD_BASE + 11)
8904 {"m4650", no_argument, NULL, OPTION_M4650},
8905 #define OPTION_NO_M4650 (OPTION_MD_BASE + 12)
8906 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
8907 #define OPTION_M4010 (OPTION_MD_BASE + 13)
8908 {"m4010", no_argument, NULL, OPTION_M4010},
8909 #define OPTION_NO_M4010 (OPTION_MD_BASE + 14)
8910 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},
8911 #define OPTION_M4100 (OPTION_MD_BASE + 15)
8912 {"m4100", no_argument, NULL, OPTION_M4100},
8913 #define OPTION_NO_M4100 (OPTION_MD_BASE + 16)
8914 {"no-m4100", no_argument, NULL, OPTION_NO_M4100},
8915 #define OPTION_MIPS16 (OPTION_MD_BASE + 17)
8916 {"mips16", no_argument, NULL, OPTION_MIPS16},
8917 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 18)
8918 {"no-mips16", no_argument, NULL, OPTION_NO_MIPS16},
8919 #define OPTION_M3900 (OPTION_MD_BASE + 19)
8920 {"m3900", no_argument, NULL, OPTION_M3900},
8921 #define OPTION_NO_M3900 (OPTION_MD_BASE + 20)
8922 {"no-m3900", no_argument, NULL, OPTION_NO_M3900},
8923 #define OPTION_MABI (OPTION_MD_BASE + 21)
8924 {"mabi", required_argument, NULL, OPTION_MABI},
8925 #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 22)
8926 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
8927 #define OPTION_NO_M7000_HILO_FIX (OPTION_MD_BASE + 23)
8928 {"no-fix-7000", no_argument, NULL, OPTION_NO_M7000_HILO_FIX},
8929 #define OPTION_GP32 (OPTION_MD_BASE + 24)
8930 {"mgp32", no_argument, NULL, OPTION_GP32},
8931 #define OPTION_GP64 (OPTION_MD_BASE + 25)
8932 {"mgp64", no_argument, NULL, OPTION_GP64},
8933 #define OPTION_CONSTRUCT_FLOATS (OPTION_MD_BASE + 26)
8934 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
8935 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MD_BASE + 27)
8936 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
8937 #define OPTION_MIPS32 (OPTION_MD_BASE + 28)
8938 {"mips32", no_argument, NULL, OPTION_MIPS32},
8939 #define OPTION_MIPS5 (OPTION_MD_BASE + 29)
8940 {"mips5", no_argument, NULL, OPTION_MIPS5},
8941 #define OPTION_MIPS64 (OPTION_MD_BASE + 30)
8942 {"mips64", no_argument, NULL, OPTION_MIPS64},
8943 #define OPTION_MARCH (OPTION_MD_BASE + 31)
8944 {"march", required_argument, NULL, OPTION_MARCH},
8945 #define OPTION_MTUNE (OPTION_MD_BASE + 32)
8946 {"mtune", required_argument, NULL, OPTION_MTUNE},
8947 #define OPTION_FP32 (OPTION_MD_BASE + 33)
8948 {"mfp32", no_argument, NULL, OPTION_FP32},
8950 #define OPTION_ELF_BASE (OPTION_MD_BASE + 35)
8951 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
8952 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
8953 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
8954 #define OPTION_32 (OPTION_ELF_BASE + 3)
8955 #define OPTION_64 (OPTION_ELF_BASE + 4)
8956 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
8957 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
8958 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
8959 {"xgot", no_argument, NULL, OPTION_XGOT},
8960 {"32", no_argument, NULL, OPTION_32},
8961 {"64", no_argument, NULL, OPTION_64},
8964 {NULL, no_argument, NULL, 0}
8966 size_t md_longopts_size = sizeof (md_longopts);
8969 md_parse_option (c, arg)
8975 case OPTION_CONSTRUCT_FLOATS:
8976 mips_disable_float_construction = 0;
8979 case OPTION_NO_CONSTRUCT_FLOATS:
8980 mips_disable_float_construction = 1;
8992 target_big_endian = 1;
8996 target_big_endian = 0;
9004 if (arg && arg[1] == '0')
9014 mips_debug = atoi (arg);
9015 /* When the MIPS assembler sees -g or -g2, it does not do
9016 optimizations which limit full symbolic debugging. We take
9017 that to be equivalent to -O0. */
9018 if (mips_debug == 2)
9023 mips_opts.isa = ISA_MIPS1;
9027 mips_opts.isa = ISA_MIPS2;
9031 mips_opts.isa = ISA_MIPS3;
9035 mips_opts.isa = ISA_MIPS4;
9039 mips_opts.isa = ISA_MIPS5;
9043 mips_opts.isa = ISA_MIPS32;
9047 mips_opts.isa = ISA_MIPS64;
9054 int cpu = CPU_UNKNOWN;
9056 /* Identify the processor type. */
9057 if (strcasecmp (arg, "default") != 0)
9059 const struct mips_cpu_info *ci;
9061 ci = mips_cpu_info_from_name (arg);
9062 if (ci == NULL || ci->is_isa)
9067 as_fatal (_("invalid architecture -mtune=%s"), arg);
9070 as_fatal (_("invalid architecture -march=%s"), arg);
9073 as_fatal (_("invalid architecture -mcpu=%s"), arg);
9084 if (mips_tune != CPU_UNKNOWN && mips_tune != cpu)
9085 as_warn(_("A different -mtune= was already specified, is now "
9090 if (mips_arch != CPU_UNKNOWN && mips_arch != cpu)
9091 as_warn(_("A different -march= was already specified, is now "
9096 if (mips_cpu != CPU_UNKNOWN && mips_cpu != cpu)
9097 as_warn(_("A different -mcpu= was already specified, is now "
9105 if ((mips_arch != CPU_UNKNOWN && mips_arch != CPU_R4650)
9106 || (mips_tune != CPU_UNKNOWN && mips_tune != CPU_R4650))
9107 as_warn(_("A different -march= or -mtune= was already specified, "
9109 mips_arch = CPU_R4650;
9110 mips_tune = CPU_R4650;
9113 case OPTION_NO_M4650:
9117 if ((mips_arch != CPU_UNKNOWN && mips_arch != CPU_R4010)
9118 || (mips_tune != CPU_UNKNOWN && mips_tune != CPU_R4010))
9119 as_warn(_("A different -march= or -mtune= was already specified, "
9121 mips_arch = CPU_R4010;
9122 mips_tune = CPU_R4010;
9125 case OPTION_NO_M4010:
9129 if ((mips_arch != CPU_UNKNOWN && mips_arch != CPU_VR4100)
9130 || (mips_tune != CPU_UNKNOWN && mips_tune != CPU_VR4100))
9131 as_warn(_("A different -march= or -mtune= was already specified, "
9133 mips_arch = CPU_VR4100;
9134 mips_tune = CPU_VR4100;
9137 case OPTION_NO_M4100:
9141 if ((mips_arch != CPU_UNKNOWN && mips_arch != CPU_R3900)
9142 || (mips_tune != CPU_UNKNOWN && mips_tune != CPU_R3900))
9143 as_warn(_("A different -march= or -mtune= was already specified, "
9145 mips_arch = CPU_R3900;
9146 mips_tune = CPU_R3900;
9149 case OPTION_NO_M3900:
9153 mips_opts.mips16 = 1;
9154 mips_no_prev_insn (false);
9157 case OPTION_NO_MIPS16:
9158 mips_opts.mips16 = 0;
9159 mips_no_prev_insn (false);
9162 case OPTION_MEMBEDDED_PIC:
9163 mips_pic = EMBEDDED_PIC;
9164 if (USE_GLOBAL_POINTER_OPT && g_switch_seen)
9166 as_bad (_("-G may not be used with embedded PIC code"));
9169 g_switch_value = 0x7fffffff;
9173 /* When generating ELF code, we permit -KPIC and -call_shared to
9174 select SVR4_PIC, and -non_shared to select no PIC. This is
9175 intended to be compatible with Irix 5. */
9176 case OPTION_CALL_SHARED:
9177 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
9179 as_bad (_("-call_shared is supported only for ELF format"));
9182 mips_pic = SVR4_PIC;
9183 if (g_switch_seen && g_switch_value != 0)
9185 as_bad (_("-G may not be used with SVR4 PIC code"));
9191 case OPTION_NON_SHARED:
9192 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
9194 as_bad (_("-non_shared is supported only for ELF format"));
9200 /* The -xgot option tells the assembler to use 32 offsets when
9201 accessing the got in SVR4_PIC mode. It is for Irix
9206 #endif /* OBJ_ELF */
9209 if (! USE_GLOBAL_POINTER_OPT)
9211 as_bad (_("-G is not supported for this configuration"));
9214 else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC)
9216 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
9220 g_switch_value = atoi (arg);
9225 /* The -32 and -64 options tell the assembler to output the 32
9226 bit or the 64 bit MIPS ELF format. */
9233 const char **list, **l;
9235 list = bfd_target_list ();
9236 for (l = list; *l != NULL; l++)
9238 /* This is traditional mips */
9239 if (strcmp (*l, "elf64-tradbigmips") == 0
9240 || strcmp (*l, "elf64-tradlittlemips") == 0)
9242 if (strcmp (*l, "elf64-bigmips") == 0
9243 || strcmp (*l, "elf64-littlemips") == 0)
9247 as_fatal (_("No compiled in support for 64 bit object file format"));
9252 #endif /* OBJ_ELF */
9257 /* We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
9258 flag in object files because to do so would make it
9259 impossible to link with libraries compiled without "-gp32".
9260 This is unnecessarily restrictive.
9262 We could solve this problem by adding "-gp32" multilibs to
9263 gcc, but to set this flag before gcc is built with such
9264 multilibs will break too many systems. */
9283 if (strcmp (arg, "32") == 0
9284 || strcmp (arg, "n32") == 0
9285 || strcmp (arg, "64") == 0
9286 || strcmp (arg, "o64") == 0
9287 || strcmp (arg, "eabi") == 0)
9289 mips_abi_string = arg;
9290 mips_32bit_abi = (strcmp (arg, "32") == 0);
9294 case OPTION_M7000_HILO_FIX:
9295 mips_7000_hilo_fix = true;
9298 case OPTION_NO_M7000_HILO_FIX:
9299 mips_7000_hilo_fix = false;
9310 show (stream, string, col_p, first_p)
9318 fprintf (stream, "%24s", "");
9323 fprintf (stream, ", ");
9327 if (*col_p + strlen (string) > 72)
9329 fprintf (stream, "\n%24s", "");
9333 fprintf (stream, "%s", string);
9334 *col_p += strlen (string);
9340 md_show_usage (stream)
9345 fprintf (stream, _("\
9347 -membedded-pic generate embedded position independent code\n\
9348 -EB generate big endian output\n\
9349 -EL generate little endian output\n\
9350 -g, -g2 do not remove unneeded NOPs or swap branches\n\
9351 -G NUM allow referencing objects up to NUM bytes\n\
9352 implicitly with the gp register [default 8]\n"));
9353 fprintf (stream, _("\
9354 -mips1 generate MIPS ISA I instructions\n\
9355 -mips2 generate MIPS ISA II instructions\n\
9356 -mips3 generate MIPS ISA III instructions\n\
9357 -mips4 generate MIPS ISA IV instructions\n\
9358 -mips5 generate MIPS ISA V instructions\n\
9359 -mips32 generate MIPS32 ISA instructions\n\
9360 -mips64 generate MIPS64 ISA instructions\n\
9361 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
9365 show (stream, "2000", &column, &first);
9366 show (stream, "3000", &column, &first);
9367 show (stream, "3900", &column, &first);
9368 show (stream, "4000", &column, &first);
9369 show (stream, "4010", &column, &first);
9370 show (stream, "4100", &column, &first);
9371 show (stream, "4111", &column, &first);
9372 show (stream, "4300", &column, &first);
9373 show (stream, "4400", &column, &first);
9374 show (stream, "4600", &column, &first);
9375 show (stream, "4650", &column, &first);
9376 show (stream, "5000", &column, &first);
9377 show (stream, "5200", &column, &first);
9378 show (stream, "5230", &column, &first);
9379 show (stream, "5231", &column, &first);
9380 show (stream, "5261", &column, &first);
9381 show (stream, "5721", &column, &first);
9382 show (stream, "6000", &column, &first);
9383 show (stream, "8000", &column, &first);
9384 show (stream, "10000", &column, &first);
9385 show (stream, "12000", &column, &first);
9386 show (stream, "sb-1", &column, &first);
9387 fputc ('\n', stream);
9389 fprintf (stream, _("\
9390 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
9391 -no-mCPU don't generate code specific to CPU.\n\
9392 For -mCPU and -no-mCPU, CPU must be one of:\n"));
9396 show (stream, "3900", &column, &first);
9397 show (stream, "4010", &column, &first);
9398 show (stream, "4100", &column, &first);
9399 show (stream, "4650", &column, &first);
9400 fputc ('\n', stream);
9402 fprintf (stream, _("\
9403 -mips16 generate mips16 instructions\n\
9404 -no-mips16 do not generate mips16 instructions\n"));
9405 fprintf (stream, _("\
9406 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
9407 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
9408 -O0 remove unneeded NOPs, do not swap branches\n\
9409 -O remove unneeded NOPs and swap branches\n\
9410 -n warn about NOPs generated from macros\n\
9411 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
9412 --trap, --no-break trap exception on div by 0 and mult overflow\n\
9413 --break, --no-trap break exception on div by 0 and mult overflow\n"));
9415 fprintf (stream, _("\
9416 -KPIC, -call_shared generate SVR4 position independent code\n\
9417 -non_shared do not generate position independent code\n\
9418 -xgot assume a 32 bit GOT\n\
9419 -32 create 32 bit object file (default)\n\
9420 -64 create 64 bit object file\n"));
9425 mips_init_after_args ()
9427 /* initialize opcodes */
9428 bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
9429 mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
9433 md_pcrel_from (fixP)
9436 if (OUTPUT_FLAVOR != bfd_target_aout_flavour
9437 && fixP->fx_addsy != (symbolS *) NULL
9438 && ! S_IS_DEFINED (fixP->fx_addsy))
9440 if (mips_pic == EMBEDDED_PIC)
9442 /* This makes a branch to an undefined symbol be a branch to the
9443 current location. */
9452 /* return the address of the delay slot */
9453 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
9456 /* This is called before the symbol table is processed. In order to
9457 work with gcc when using mips-tfile, we must keep all local labels.
9458 However, in other cases, we want to discard them. If we were
9459 called with -g, but we didn't see any debugging information, it may
9460 mean that gcc is smuggling debugging information through to
9461 mips-tfile, in which case we must generate all local labels. */
9464 mips_frob_file_before_adjust ()
9466 #ifndef NO_ECOFF_DEBUGGING
9469 && ! ecoff_debugging_seen)
9470 flag_keep_locals = 1;
9474 /* Sort any unmatched HI16_S relocs so that they immediately precede
9475 the corresponding LO reloc. This is called before md_apply_fix and
9476 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
9477 explicit use of the %hi modifier. */
9482 struct mips_hi_fixup *l;
9484 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
9486 segment_info_type *seginfo;
9489 assert (l->fixp->fx_r_type == BFD_RELOC_HI16_S);
9491 /* Check quickly whether the next fixup happens to be a matching
9493 if (l->fixp->fx_next != NULL
9494 && l->fixp->fx_next->fx_r_type == BFD_RELOC_LO16
9495 && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy
9496 && l->fixp->fx_offset == l->fixp->fx_next->fx_offset)
9499 /* Look through the fixups for this segment for a matching %lo.
9500 When we find one, move the %hi just in front of it. We do
9501 this in two passes. In the first pass, we try to find a
9502 unique %lo. In the second pass, we permit multiple %hi
9503 relocs for a single %lo (this is a GNU extension). */
9504 seginfo = seg_info (l->seg);
9505 for (pass = 0; pass < 2; pass++)
9510 for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
9512 /* Check whether this is a %lo fixup which matches l->fixp. */
9513 if (f->fx_r_type == BFD_RELOC_LO16
9514 && f->fx_addsy == l->fixp->fx_addsy
9515 && f->fx_offset == l->fixp->fx_offset
9518 || prev->fx_r_type != BFD_RELOC_HI16_S
9519 || prev->fx_addsy != f->fx_addsy
9520 || prev->fx_offset != f->fx_offset))
9524 /* Move l->fixp before f. */
9525 for (pf = &seginfo->fix_root;
9527 pf = &(*pf)->fx_next)
9528 assert (*pf != NULL);
9530 *pf = l->fixp->fx_next;
9532 l->fixp->fx_next = f;
9534 seginfo->fix_root = l->fixp;
9536 prev->fx_next = l->fixp;
9547 #if 0 /* GCC code motion plus incomplete dead code elimination
9548 can leave a %hi without a %lo. */
9550 as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
9551 _("Unmatched %%hi reloc"));
9557 /* When generating embedded PIC code we need to use a special
9558 relocation to represent the difference of two symbols in the .text
9559 section (switch tables use a difference of this sort). See
9560 include/coff/mips.h for details. This macro checks whether this
9561 fixup requires the special reloc. */
9562 #define SWITCH_TABLE(fixp) \
9563 ((fixp)->fx_r_type == BFD_RELOC_32 \
9564 && OUTPUT_FLAVOR != bfd_target_elf_flavour \
9565 && (fixp)->fx_addsy != NULL \
9566 && (fixp)->fx_subsy != NULL \
9567 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
9568 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
9570 /* When generating embedded PIC code we must keep all PC relative
9571 relocations, in case the linker has to relax a call. We also need
9572 to keep relocations for switch table entries. */
9575 mips_force_relocation (fixp)
9578 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
9579 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
9582 return (mips_pic == EMBEDDED_PIC
9584 || SWITCH_TABLE (fixp)
9585 || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S
9586 || fixp->fx_r_type == BFD_RELOC_PCREL_LO16));
9589 /* Apply a fixup to the object file. */
9592 md_apply_fix (fixP, valueP)
9600 assert (fixP->fx_size == 4
9601 || fixP->fx_r_type == BFD_RELOC_16
9602 || fixP->fx_r_type == BFD_RELOC_64
9603 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
9604 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY);
9608 /* If we aren't adjusting this fixup to be against the section
9609 symbol, we need to adjust the value. */
9611 if (fixP->fx_addsy != NULL && OUTPUT_FLAVOR == bfd_target_elf_flavour)
9613 if (S_GET_OTHER (fixP->fx_addsy) == STO_MIPS16
9614 || ((S_IS_WEAK (fixP->fx_addsy)
9615 || S_IS_EXTERN (fixP->fx_addsy))
9616 && !S_IS_COMMON (fixP->fx_addsy))
9617 || (symbol_used_in_reloc_p (fixP->fx_addsy)
9618 && (((bfd_get_section_flags (stdoutput,
9619 S_GET_SEGMENT (fixP->fx_addsy))
9620 & SEC_LINK_ONCE) != 0)
9621 || !strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)),
9623 sizeof (".gnu.linkonce") - 1))))
9626 valueT symval = S_GET_VALUE (fixP->fx_addsy);
9630 && fixP->fx_r_type != BFD_RELOC_MIPS_GPREL)
9632 /* In this case, the bfd_install_relocation routine will
9633 incorrectly add the symbol value back in. We just want
9634 the addend to appear in the object file. */
9637 /* Make sure the addend is still non-zero. If it became zero
9638 after the last operation, set it to a spurious value and
9639 subtract the same value from the object file's contents. */
9644 /* The in-place addends for LO16 relocations are signed;
9645 leave the matching HI16 in-place addends as zero. */
9646 if (fixP->fx_r_type != BFD_RELOC_HI16_S)
9648 reloc_howto_type *howto;
9649 bfd_vma contents, mask, field;
9651 howto = bfd_reloc_type_lookup (stdoutput,
9654 contents = bfd_get_bits (fixP->fx_frag->fr_literal
9659 /* MASK has bits set where the relocation should go.
9660 FIELD is -value, shifted into the appropriate place
9661 for this relocation. */
9662 mask = 1 << (howto->bitsize - 1);
9663 mask = (((mask - 1) << 1) | 1) << howto->bitpos;
9664 field = (-value >> howto->rightshift) << howto->bitpos;
9666 bfd_put_bits ((field & mask) | (contents & ~mask),
9667 fixP->fx_frag->fr_literal + fixP->fx_where,
9675 /* This code was generated using trial and error and so is
9676 fragile and not trustworthy. If you change it, you should
9677 rerun the elf-rel, elf-rel2, and empic testcases and ensure
9679 if (fixP->fx_pcrel || fixP->fx_subsy != NULL)
9681 value += fixP->fx_frag->fr_address + fixP->fx_where;
9683 /* BFD's REL handling, for MIPS, is _very_ weird.
9684 This gives the right results, but it can't possibly
9685 be the way things are supposed to work. */
9686 if ((fixP->fx_r_type != BFD_RELOC_16_PCREL
9687 && fixP->fx_r_type != BFD_RELOC_16_PCREL_S2)
9688 || S_GET_SEGMENT (fixP->fx_addsy) != undefined_section)
9689 value += fixP->fx_frag->fr_address + fixP->fx_where;
9694 fixP->fx_addnumber = value; /* Remember value for tc_gen_reloc */
9696 if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel)
9699 switch (fixP->fx_r_type)
9701 case BFD_RELOC_MIPS_JMP:
9702 case BFD_RELOC_HI16:
9703 case BFD_RELOC_HI16_S:
9704 case BFD_RELOC_MIPS_GPREL:
9705 case BFD_RELOC_MIPS_LITERAL:
9706 case BFD_RELOC_MIPS_CALL16:
9707 case BFD_RELOC_MIPS_GOT16:
9708 case BFD_RELOC_MIPS_GPREL32:
9709 case BFD_RELOC_MIPS_GOT_HI16:
9710 case BFD_RELOC_MIPS_GOT_LO16:
9711 case BFD_RELOC_MIPS_CALL_HI16:
9712 case BFD_RELOC_MIPS_CALL_LO16:
9713 case BFD_RELOC_MIPS16_GPREL:
9715 as_bad_where (fixP->fx_file, fixP->fx_line,
9716 _("Invalid PC relative reloc"));
9717 /* Nothing needed to do. The value comes from the reloc entry */
9720 case BFD_RELOC_MIPS16_JMP:
9721 /* We currently always generate a reloc against a symbol, which
9722 means that we don't want an addend even if the symbol is
9724 fixP->fx_addnumber = 0;
9727 case BFD_RELOC_PCREL_HI16_S:
9728 /* The addend for this is tricky if it is internal, so we just
9729 do everything here rather than in bfd_install_relocation. */
9730 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
9735 && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0)
9737 /* For an external symbol adjust by the address to make it
9738 pcrel_offset. We use the address of the RELLO reloc
9739 which follows this one. */
9740 value += (fixP->fx_next->fx_frag->fr_address
9741 + fixP->fx_next->fx_where);
9743 value = ((value + 0x8000) >> 16) & 0xffff;
9744 buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where;
9745 if (target_big_endian)
9747 md_number_to_chars (buf, value, 2);
9750 case BFD_RELOC_PCREL_LO16:
9751 /* The addend for this is tricky if it is internal, so we just
9752 do everything here rather than in bfd_install_relocation. */
9753 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
9758 && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0)
9759 value += fixP->fx_frag->fr_address + fixP->fx_where;
9760 buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where;
9761 if (target_big_endian)
9763 md_number_to_chars (buf, value, 2);
9767 /* This is handled like BFD_RELOC_32, but we output a sign
9768 extended value if we are only 32 bits. */
9770 || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
9772 if (8 <= sizeof (valueT))
9773 md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
9780 w1 = w2 = fixP->fx_where;
9781 if (target_big_endian)
9785 md_number_to_chars (fixP->fx_frag->fr_literal + w1, value, 4);
9786 if ((value & 0x80000000) != 0)
9790 md_number_to_chars (fixP->fx_frag->fr_literal + w2, hiv, 4);
9797 /* If we are deleting this reloc entry, we must fill in the
9798 value now. This can happen if we have a .word which is not
9799 resolved when it appears but is later defined. We also need
9800 to fill in the value if this is an embedded PIC switch table
9803 || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
9804 md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
9809 /* If we are deleting this reloc entry, we must fill in the
9811 assert (fixP->fx_size == 2);
9813 md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
9817 case BFD_RELOC_LO16:
9818 /* When handling an embedded PIC switch statement, we can wind
9819 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
9822 if (value + 0x8000 > 0xffff)
9823 as_bad_where (fixP->fx_file, fixP->fx_line,
9824 _("relocation overflow"));
9825 buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where;
9826 if (target_big_endian)
9828 md_number_to_chars (buf, value, 2);
9832 case BFD_RELOC_16_PCREL_S2:
9833 if ((value & 0x3) != 0)
9834 as_bad_where (fixP->fx_file, fixP->fx_line,
9835 _("Branch to odd address (%lx)"), (long) value);
9839 case BFD_RELOC_16_PCREL:
9841 * We need to save the bits in the instruction since fixup_segment()
9842 * might be deleting the relocation entry (i.e., a branch within
9843 * the current segment).
9845 if (!fixP->fx_done && value != 0)
9847 /* If 'value' is zero, the remaining reloc code won't actually
9848 do the store, so it must be done here. This is probably
9851 value -= fixP->fx_frag->fr_address + fixP->fx_where;
9853 value = (offsetT) value >> 2;
9855 /* update old instruction data */
9856 buf = (unsigned char *) (fixP->fx_where + fixP->fx_frag->fr_literal);
9857 if (target_big_endian)
9858 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
9860 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
9862 if (value + 0x8000 <= 0xffff)
9863 insn |= value & 0xffff;
9866 /* The branch offset is too large. If this is an
9867 unconditional branch, and we are not generating PIC code,
9868 we can convert it to an absolute jump instruction. */
9869 if (mips_pic == NO_PIC
9871 && fixP->fx_frag->fr_address >= text_section->vma
9872 && (fixP->fx_frag->fr_address
9873 < text_section->vma + text_section->_raw_size)
9874 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
9875 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
9876 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
9878 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
9879 insn = 0x0c000000; /* jal */
9881 insn = 0x08000000; /* j */
9882 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
9884 fixP->fx_addsy = section_symbol (text_section);
9885 fixP->fx_addnumber = (value << 2) + md_pcrel_from (fixP);
9889 /* FIXME. It would be possible in principle to handle
9890 conditional branches which overflow. They could be
9891 transformed into a branch around a jump. This would
9892 require setting up variant frags for each different
9893 branch type. The native MIPS assembler attempts to
9894 handle these cases, but it appears to do it
9896 as_bad_where (fixP->fx_file, fixP->fx_line,
9897 _("Branch out of range"));
9901 md_number_to_chars ((char *) buf, (valueT) insn, 4);
9904 case BFD_RELOC_VTABLE_INHERIT:
9907 && !S_IS_DEFINED (fixP->fx_addsy)
9908 && !S_IS_WEAK (fixP->fx_addsy))
9909 S_SET_WEAK (fixP->fx_addsy);
9912 case BFD_RELOC_VTABLE_ENTRY:
9928 const struct mips_opcode *p;
9929 int treg, sreg, dreg, shamt;
9934 for (i = 0; i < NUMOPCODES; ++i)
9936 p = &mips_opcodes[i];
9937 if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO))
9939 printf ("%08lx %s\t", oc, p->name);
9940 treg = (oc >> 16) & 0x1f;
9941 sreg = (oc >> 21) & 0x1f;
9942 dreg = (oc >> 11) & 0x1f;
9943 shamt = (oc >> 6) & 0x1f;
9945 for (args = p->args;; ++args)
9956 printf ("%c", *args);
9960 assert (treg == sreg);
9961 printf ("$%d,$%d", treg, sreg);
9966 printf ("$%d", dreg);
9971 printf ("$%d", treg);
9975 printf ("0x%x", treg);
9980 printf ("$%d", sreg);
9984 printf ("0x%08lx", oc & 0x1ffffff);
9996 printf ("$%d", shamt);
10007 printf (_("%08lx UNDEFINED\n"), oc);
10018 name = input_line_pointer;
10019 c = get_symbol_end ();
10020 p = (symbolS *) symbol_find_or_make (name);
10021 *input_line_pointer = c;
10025 /* Align the current frag to a given power of two. The MIPS assembler
10026 also automatically adjusts any preceding label. */
10029 mips_align (to, fill, label)
10034 mips_emit_delays (false);
10035 frag_align (to, fill, 0);
10036 record_alignment (now_seg, to);
10039 assert (S_GET_SEGMENT (label) == now_seg);
10040 symbol_set_frag (label, frag_now);
10041 S_SET_VALUE (label, (valueT) frag_now_fix ());
10045 /* Align to a given power of two. .align 0 turns off the automatic
10046 alignment used by the data creating pseudo-ops. */
10050 int x ATTRIBUTE_UNUSED;
10053 register long temp_fill;
10054 long max_alignment = 15;
10058 o Note that the assembler pulls down any immediately preceeding label
10059 to the aligned address.
10060 o It's not documented but auto alignment is reinstated by
10061 a .align pseudo instruction.
10062 o Note also that after auto alignment is turned off the mips assembler
10063 issues an error on attempt to assemble an improperly aligned data item.
10068 temp = get_absolute_expression ();
10069 if (temp > max_alignment)
10070 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
10073 as_warn (_("Alignment negative: 0 assumed."));
10076 if (*input_line_pointer == ',')
10078 input_line_pointer++;
10079 temp_fill = get_absolute_expression ();
10086 mips_align (temp, (int) temp_fill,
10087 insn_labels != NULL ? insn_labels->label : NULL);
10094 demand_empty_rest_of_line ();
10098 mips_flush_pending_output ()
10100 mips_emit_delays (false);
10101 mips_clear_insn_labels ();
10110 /* When generating embedded PIC code, we only use the .text, .lit8,
10111 .sdata and .sbss sections. We change the .data and .rdata
10112 pseudo-ops to use .sdata. */
10113 if (mips_pic == EMBEDDED_PIC
10114 && (sec == 'd' || sec == 'r'))
10118 /* The ELF backend needs to know that we are changing sections, so
10119 that .previous works correctly. We could do something like check
10120 for a obj_section_change_hook macro, but that might be confusing
10121 as it would not be appropriate to use it in the section changing
10122 functions in read.c, since obj-elf.c intercepts those. FIXME:
10123 This should be cleaner, somehow. */
10124 obj_elf_section_change_hook ();
10127 mips_emit_delays (false);
10137 subseg_set (bss_section, (subsegT) get_absolute_expression ());
10138 demand_empty_rest_of_line ();
10142 if (USE_GLOBAL_POINTER_OPT)
10144 seg = subseg_new (RDATA_SECTION_NAME,
10145 (subsegT) get_absolute_expression ());
10146 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
10148 bfd_set_section_flags (stdoutput, seg,
10154 if (strcmp (TARGET_OS, "elf") != 0)
10155 record_alignment (seg, 4);
10157 demand_empty_rest_of_line ();
10161 as_bad (_("No read only data section in this object file format"));
10162 demand_empty_rest_of_line ();
10168 if (USE_GLOBAL_POINTER_OPT)
10170 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
10171 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
10173 bfd_set_section_flags (stdoutput, seg,
10174 SEC_ALLOC | SEC_LOAD | SEC_RELOC
10176 if (strcmp (TARGET_OS, "elf") != 0)
10177 record_alignment (seg, 4);
10179 demand_empty_rest_of_line ();
10184 as_bad (_("Global pointers not supported; recompile -G 0"));
10185 demand_empty_rest_of_line ();
10194 mips_enable_auto_align ()
10205 label = insn_labels != NULL ? insn_labels->label : NULL;
10206 mips_emit_delays (false);
10207 if (log_size > 0 && auto_align)
10208 mips_align (log_size, 0, label);
10209 mips_clear_insn_labels ();
10210 cons (1 << log_size);
10214 s_float_cons (type)
10219 label = insn_labels != NULL ? insn_labels->label : NULL;
10221 mips_emit_delays (false);
10226 mips_align (3, 0, label);
10228 mips_align (2, 0, label);
10231 mips_clear_insn_labels ();
10236 /* Handle .globl. We need to override it because on Irix 5 you are
10239 where foo is an undefined symbol, to mean that foo should be
10240 considered to be the address of a function. */
10244 int x ATTRIBUTE_UNUSED;
10251 name = input_line_pointer;
10252 c = get_symbol_end ();
10253 symbolP = symbol_find_or_make (name);
10254 *input_line_pointer = c;
10255 SKIP_WHITESPACE ();
10257 /* On Irix 5, every global symbol that is not explicitly labelled as
10258 being a function is apparently labelled as being an object. */
10261 if (! is_end_of_line[(unsigned char) *input_line_pointer])
10266 secname = input_line_pointer;
10267 c = get_symbol_end ();
10268 sec = bfd_get_section_by_name (stdoutput, secname);
10270 as_bad (_("%s: no such section"), secname);
10271 *input_line_pointer = c;
10273 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
10274 flag = BSF_FUNCTION;
10277 symbol_get_bfdsym (symbolP)->flags |= flag;
10279 S_SET_EXTERNAL (symbolP);
10280 demand_empty_rest_of_line ();
10285 int x ATTRIBUTE_UNUSED;
10290 opt = input_line_pointer;
10291 c = get_symbol_end ();
10295 /* FIXME: What does this mean? */
10297 else if (strncmp (opt, "pic", 3) == 0)
10301 i = atoi (opt + 3);
10305 mips_pic = SVR4_PIC;
10307 as_bad (_(".option pic%d not supported"), i);
10309 if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC)
10311 if (g_switch_seen && g_switch_value != 0)
10312 as_warn (_("-G may not be used with SVR4 PIC code"));
10313 g_switch_value = 0;
10314 bfd_set_gp_size (stdoutput, 0);
10318 as_warn (_("Unrecognized option \"%s\""), opt);
10320 *input_line_pointer = c;
10321 demand_empty_rest_of_line ();
10324 /* This structure is used to hold a stack of .set values. */
10326 struct mips_option_stack
10328 struct mips_option_stack *next;
10329 struct mips_set_options options;
10332 static struct mips_option_stack *mips_opts_stack;
10334 /* Handle the .set pseudo-op. */
10338 int x ATTRIBUTE_UNUSED;
10340 char *name = input_line_pointer, ch;
10342 while (!is_end_of_line[(unsigned char) *input_line_pointer])
10343 input_line_pointer++;
10344 ch = *input_line_pointer;
10345 *input_line_pointer = '\0';
10347 if (strcmp (name, "reorder") == 0)
10349 if (mips_opts.noreorder && prev_nop_frag != NULL)
10351 /* If we still have pending nops, we can discard them. The
10352 usual nop handling will insert any that are still
10354 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
10355 * (mips_opts.mips16 ? 2 : 4));
10356 prev_nop_frag = NULL;
10358 mips_opts.noreorder = 0;
10360 else if (strcmp (name, "noreorder") == 0)
10362 mips_emit_delays (true);
10363 mips_opts.noreorder = 1;
10364 mips_any_noreorder = 1;
10366 else if (strcmp (name, "at") == 0)
10368 mips_opts.noat = 0;
10370 else if (strcmp (name, "noat") == 0)
10372 mips_opts.noat = 1;
10374 else if (strcmp (name, "macro") == 0)
10376 mips_opts.warn_about_macros = 0;
10378 else if (strcmp (name, "nomacro") == 0)
10380 if (mips_opts.noreorder == 0)
10381 as_bad (_("`noreorder' must be set before `nomacro'"));
10382 mips_opts.warn_about_macros = 1;
10384 else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
10386 mips_opts.nomove = 0;
10388 else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
10390 mips_opts.nomove = 1;
10392 else if (strcmp (name, "bopt") == 0)
10394 mips_opts.nobopt = 0;
10396 else if (strcmp (name, "nobopt") == 0)
10398 mips_opts.nobopt = 1;
10400 else if (strcmp (name, "mips16") == 0
10401 || strcmp (name, "MIPS-16") == 0)
10402 mips_opts.mips16 = 1;
10403 else if (strcmp (name, "nomips16") == 0
10404 || strcmp (name, "noMIPS-16") == 0)
10405 mips_opts.mips16 = 0;
10406 else if (strncmp (name, "mips", 4) == 0)
10409 static int saved_mips_gp32;
10410 static int saved_mips_fp32;
10411 static int saved_mips_32bit_abi;
10412 static int is_saved;
10414 /* Permit the user to change the ISA on the fly. Needless to
10415 say, misuse can cause serious problems. */
10416 isa = atoi (name + 4);
10420 mips_gp32 = saved_mips_gp32;
10421 mips_fp32 = saved_mips_fp32;
10422 mips_32bit_abi = saved_mips_32bit_abi;
10430 saved_mips_gp32 = mips_gp32;
10431 saved_mips_fp32 = mips_fp32;
10432 saved_mips_32bit_abi = mips_32bit_abi;
10444 saved_mips_gp32 = mips_gp32;
10445 saved_mips_fp32 = mips_fp32;
10446 saved_mips_32bit_abi = mips_32bit_abi;
10450 mips_32bit_abi = 0;
10454 as_bad (_("unknown ISA level"));
10460 case 0: mips_opts.isa = file_mips_isa; break;
10461 case 1: mips_opts.isa = ISA_MIPS1; break;
10462 case 2: mips_opts.isa = ISA_MIPS2; break;
10463 case 3: mips_opts.isa = ISA_MIPS3; break;
10464 case 4: mips_opts.isa = ISA_MIPS4; break;
10465 case 5: mips_opts.isa = ISA_MIPS5; break;
10466 case 32: mips_opts.isa = ISA_MIPS32; break;
10467 case 64: mips_opts.isa = ISA_MIPS64; break;
10468 default: as_bad (_("unknown ISA level")); break;
10471 else if (strcmp (name, "autoextend") == 0)
10472 mips_opts.noautoextend = 0;
10473 else if (strcmp (name, "noautoextend") == 0)
10474 mips_opts.noautoextend = 1;
10475 else if (strcmp (name, "push") == 0)
10477 struct mips_option_stack *s;
10479 s = (struct mips_option_stack *) xmalloc (sizeof *s);
10480 s->next = mips_opts_stack;
10481 s->options = mips_opts;
10482 mips_opts_stack = s;
10484 else if (strcmp (name, "pop") == 0)
10486 struct mips_option_stack *s;
10488 s = mips_opts_stack;
10490 as_bad (_(".set pop with no .set push"));
10493 /* If we're changing the reorder mode we need to handle
10494 delay slots correctly. */
10495 if (s->options.noreorder && ! mips_opts.noreorder)
10496 mips_emit_delays (true);
10497 else if (! s->options.noreorder && mips_opts.noreorder)
10499 if (prev_nop_frag != NULL)
10501 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
10502 * (mips_opts.mips16 ? 2 : 4));
10503 prev_nop_frag = NULL;
10507 mips_opts = s->options;
10508 mips_opts_stack = s->next;
10514 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
10516 *input_line_pointer = ch;
10517 demand_empty_rest_of_line ();
10520 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
10521 .option pic2. It means to generate SVR4 PIC calls. */
10524 s_abicalls (ignore)
10525 int ignore ATTRIBUTE_UNUSED;
10527 mips_pic = SVR4_PIC;
10528 if (USE_GLOBAL_POINTER_OPT)
10530 if (g_switch_seen && g_switch_value != 0)
10531 as_warn (_("-G may not be used with SVR4 PIC code"));
10532 g_switch_value = 0;
10534 bfd_set_gp_size (stdoutput, 0);
10535 demand_empty_rest_of_line ();
10538 /* Handle the .cpload pseudo-op. This is used when generating SVR4
10539 PIC code. It sets the $gp register for the function based on the
10540 function address, which is in the register named in the argument.
10541 This uses a relocation against _gp_disp, which is handled specially
10542 by the linker. The result is:
10543 lui $gp,%hi(_gp_disp)
10544 addiu $gp,$gp,%lo(_gp_disp)
10545 addu $gp,$gp,.cpload argument
10546 The .cpload argument is normally $25 == $t9. */
10550 int ignore ATTRIBUTE_UNUSED;
10555 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
10556 if (mips_pic != SVR4_PIC)
10562 /* .cpload should be a in .set noreorder section. */
10563 if (mips_opts.noreorder == 0)
10564 as_warn (_(".cpload not in noreorder section"));
10566 ex.X_op = O_symbol;
10567 ex.X_add_symbol = symbol_find_or_make ("_gp_disp");
10568 ex.X_op_symbol = NULL;
10569 ex.X_add_number = 0;
10571 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
10572 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
10574 macro_build_lui ((char *) NULL, &icnt, &ex, GP);
10575 macro_build ((char *) NULL, &icnt, &ex, "addiu", "t,r,j", GP, GP,
10576 (int) BFD_RELOC_LO16);
10578 macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "addu", "d,v,t",
10579 GP, GP, tc_get_register (0));
10581 demand_empty_rest_of_line ();
10584 /* Handle the .cprestore pseudo-op. This stores $gp into a given
10585 offset from $sp. The offset is remembered, and after making a PIC
10586 call $gp is restored from that location. */
10589 s_cprestore (ignore)
10590 int ignore ATTRIBUTE_UNUSED;
10595 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
10596 if (mips_pic != SVR4_PIC)
10602 mips_cprestore_offset = get_absolute_expression ();
10604 ex.X_op = O_constant;
10605 ex.X_add_symbol = NULL;
10606 ex.X_op_symbol = NULL;
10607 ex.X_add_number = mips_cprestore_offset;
10609 macro_build ((char *) NULL, &icnt, &ex,
10610 HAVE_32BIT_ADDRESSES ? "sw" : "sd",
10611 "t,o(b)", GP, (int) BFD_RELOC_LO16, SP);
10613 demand_empty_rest_of_line ();
10616 /* Handle the .gpword pseudo-op. This is used when generating PIC
10617 code. It generates a 32 bit GP relative reloc. */
10621 int ignore ATTRIBUTE_UNUSED;
10627 /* When not generating PIC code, this is treated as .word. */
10628 if (mips_pic != SVR4_PIC)
10634 label = insn_labels != NULL ? insn_labels->label : NULL;
10635 mips_emit_delays (true);
10637 mips_align (2, 0, label);
10638 mips_clear_insn_labels ();
10642 if (ex.X_op != O_symbol || ex.X_add_number != 0)
10644 as_bad (_("Unsupported use of .gpword"));
10645 ignore_rest_of_line ();
10649 md_number_to_chars (p, (valueT) 0, 4);
10650 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, 0,
10651 BFD_RELOC_MIPS_GPREL32);
10653 demand_empty_rest_of_line ();
10656 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
10657 tables in SVR4 PIC code. */
10661 int ignore ATTRIBUTE_UNUSED;
10666 /* This is ignored when not generating SVR4 PIC code. */
10667 if (mips_pic != SVR4_PIC)
10673 /* Add $gp to the register named as an argument. */
10674 reg = tc_get_register (0);
10675 macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
10676 HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
10677 "d,v,t", reg, reg, GP);
10679 demand_empty_rest_of_line ();
10682 /* Handle the .insn pseudo-op. This marks instruction labels in
10683 mips16 mode. This permits the linker to handle them specially,
10684 such as generating jalx instructions when needed. We also make
10685 them odd for the duration of the assembly, in order to generate the
10686 right sort of code. We will make them even in the adjust_symtab
10687 routine, while leaving them marked. This is convenient for the
10688 debugger and the disassembler. The linker knows to make them odd
10693 int ignore ATTRIBUTE_UNUSED;
10695 if (mips_opts.mips16)
10696 mips16_mark_labels ();
10698 demand_empty_rest_of_line ();
10701 /* Handle a .stabn directive. We need these in order to mark a label
10702 as being a mips16 text label correctly. Sometimes the compiler
10703 will emit a label, followed by a .stabn, and then switch sections.
10704 If the label and .stabn are in mips16 mode, then the label is
10705 really a mips16 text label. */
10711 if (type == 'n' && mips_opts.mips16)
10712 mips16_mark_labels ();
10717 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
10721 s_mips_weakext (ignore)
10722 int ignore ATTRIBUTE_UNUSED;
10729 name = input_line_pointer;
10730 c = get_symbol_end ();
10731 symbolP = symbol_find_or_make (name);
10732 S_SET_WEAK (symbolP);
10733 *input_line_pointer = c;
10735 SKIP_WHITESPACE ();
10737 if (! is_end_of_line[(unsigned char) *input_line_pointer])
10739 if (S_IS_DEFINED (symbolP))
10741 as_bad ("Ignoring attempt to redefine symbol `%s'.",
10742 S_GET_NAME (symbolP));
10743 ignore_rest_of_line ();
10747 if (*input_line_pointer == ',')
10749 ++input_line_pointer;
10750 SKIP_WHITESPACE ();
10754 if (exp.X_op != O_symbol)
10756 as_bad ("bad .weakext directive");
10757 ignore_rest_of_line();
10760 symbol_set_value_expression (symbolP, &exp);
10763 demand_empty_rest_of_line ();
10766 /* Parse a register string into a number. Called from the ECOFF code
10767 to parse .frame. The argument is non-zero if this is the frame
10768 register, so that we can record it in mips_frame_reg. */
10771 tc_get_register (frame)
10776 SKIP_WHITESPACE ();
10777 if (*input_line_pointer++ != '$')
10779 as_warn (_("expected `$'"));
10782 else if (ISDIGIT (*input_line_pointer))
10784 reg = get_absolute_expression ();
10785 if (reg < 0 || reg >= 32)
10787 as_warn (_("Bad register number"));
10793 if (strncmp (input_line_pointer, "fp", 2) == 0)
10795 else if (strncmp (input_line_pointer, "sp", 2) == 0)
10797 else if (strncmp (input_line_pointer, "gp", 2) == 0)
10799 else if (strncmp (input_line_pointer, "at", 2) == 0)
10803 as_warn (_("Unrecognized register name"));
10806 input_line_pointer += 2;
10809 mips_frame_reg = reg != 0 ? reg : SP;
10814 md_section_align (seg, addr)
10818 int align = bfd_get_section_alignment (stdoutput, seg);
10821 /* We don't need to align ELF sections to the full alignment.
10822 However, Irix 5 may prefer that we align them at least to a 16
10823 byte boundary. We don't bother to align the sections if we are
10824 targeted for an embedded system. */
10825 if (strcmp (TARGET_OS, "elf") == 0)
10831 return ((addr + (1 << align) - 1) & (-1 << align));
10834 /* Utility routine, called from above as well. If called while the
10835 input file is still being read, it's only an approximation. (For
10836 example, a symbol may later become defined which appeared to be
10837 undefined earlier.) */
10840 nopic_need_relax (sym, before_relaxing)
10842 int before_relaxing;
10847 if (USE_GLOBAL_POINTER_OPT)
10849 const char *symname;
10852 /* Find out whether this symbol can be referenced off the GP
10853 register. It can be if it is smaller than the -G size or if
10854 it is in the .sdata or .sbss section. Certain symbols can
10855 not be referenced off the GP, although it appears as though
10857 symname = S_GET_NAME (sym);
10858 if (symname != (const char *) NULL
10859 && (strcmp (symname, "eprol") == 0
10860 || strcmp (symname, "etext") == 0
10861 || strcmp (symname, "_gp") == 0
10862 || strcmp (symname, "edata") == 0
10863 || strcmp (symname, "_fbss") == 0
10864 || strcmp (symname, "_fdata") == 0
10865 || strcmp (symname, "_ftext") == 0
10866 || strcmp (symname, "end") == 0
10867 || strcmp (symname, "_gp_disp") == 0))
10869 else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym))
10871 #ifndef NO_ECOFF_DEBUGGING
10872 || (symbol_get_obj (sym)->ecoff_extern_size != 0
10873 && (symbol_get_obj (sym)->ecoff_extern_size
10874 <= g_switch_value))
10876 /* We must defer this decision until after the whole
10877 file has been read, since there might be a .extern
10878 after the first use of this symbol. */
10879 || (before_relaxing
10880 #ifndef NO_ECOFF_DEBUGGING
10881 && symbol_get_obj (sym)->ecoff_extern_size == 0
10883 && S_GET_VALUE (sym) == 0)
10884 || (S_GET_VALUE (sym) != 0
10885 && S_GET_VALUE (sym) <= g_switch_value)))
10889 const char *segname;
10891 segname = segment_name (S_GET_SEGMENT (sym));
10892 assert (strcmp (segname, ".lit8") != 0
10893 && strcmp (segname, ".lit4") != 0);
10894 change = (strcmp (segname, ".sdata") != 0
10895 && strcmp (segname, ".sbss") != 0
10896 && strncmp (segname, ".sdata.", 7) != 0
10897 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
10902 /* We are not optimizing for the GP register. */
10906 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
10907 extended opcode. SEC is the section the frag is in. */
10910 mips16_extended_frag (fragp, sec, stretch)
10916 register const struct mips16_immed_operand *op;
10918 int mintiny, maxtiny;
10922 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
10924 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
10927 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
10928 op = mips16_immed_operands;
10929 while (op->type != type)
10932 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);
10937 if (type == '<' || type == '>' || type == '[' || type == ']')
10940 maxtiny = 1 << op->nbits;
10945 maxtiny = (1 << op->nbits) - 1;
10950 mintiny = - (1 << (op->nbits - 1));
10951 maxtiny = (1 << (op->nbits - 1)) - 1;
10954 sym_frag = symbol_get_frag (fragp->fr_symbol);
10955 val = S_GET_VALUE (fragp->fr_symbol);
10956 symsec = S_GET_SEGMENT (fragp->fr_symbol);
10962 /* We won't have the section when we are called from
10963 mips_relax_frag. However, we will always have been called
10964 from md_estimate_size_before_relax first. If this is a
10965 branch to a different section, we mark it as such. If SEC is
10966 NULL, and the frag is not marked, then it must be a branch to
10967 the same section. */
10970 if (RELAX_MIPS16_LONG_BRANCH (fragp->fr_subtype))
10975 /* Must have been called from md_estimate_size_before_relax. */
10978 fragp->fr_subtype =
10979 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
10981 /* FIXME: We should support this, and let the linker
10982 catch branches and loads that are out of range. */
10983 as_bad_where (fragp->fr_file, fragp->fr_line,
10984 _("unsupported PC relative reference to different section"));
10988 if (fragp != sym_frag && sym_frag->fr_address == 0)
10989 /* Assume non-extended on the first relaxation pass.
10990 The address we have calculated will be bogus if this is
10991 a forward branch to another frag, as the forward frag
10992 will have fr_address == 0. */
10996 /* In this case, we know for sure that the symbol fragment is in
10997 the same section. If the relax_marker of the symbol fragment
10998 differs from the relax_marker of this fragment, we have not
10999 yet adjusted the symbol fragment fr_address. We want to add
11000 in STRETCH in order to get a better estimate of the address.
11001 This particularly matters because of the shift bits. */
11003 && sym_frag->relax_marker != fragp->relax_marker)
11007 /* Adjust stretch for any alignment frag. Note that if have
11008 been expanding the earlier code, the symbol may be
11009 defined in what appears to be an earlier frag. FIXME:
11010 This doesn't handle the fr_subtype field, which specifies
11011 a maximum number of bytes to skip when doing an
11013 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
11015 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
11018 stretch = - ((- stretch)
11019 & ~ ((1 << (int) f->fr_offset) - 1));
11021 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
11030 addr = fragp->fr_address + fragp->fr_fix;
11032 /* The base address rules are complicated. The base address of
11033 a branch is the following instruction. The base address of a
11034 PC relative load or add is the instruction itself, but if it
11035 is in a delay slot (in which case it can not be extended) use
11036 the address of the instruction whose delay slot it is in. */
11037 if (type == 'p' || type == 'q')
11041 /* If we are currently assuming that this frag should be
11042 extended, then, the current address is two bytes
11044 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
11047 /* Ignore the low bit in the target, since it will be set
11048 for a text label. */
11049 if ((val & 1) != 0)
11052 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
11054 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
11057 val -= addr & ~ ((1 << op->shift) - 1);
11059 /* Branch offsets have an implicit 0 in the lowest bit. */
11060 if (type == 'p' || type == 'q')
11063 /* If any of the shifted bits are set, we must use an extended
11064 opcode. If the address depends on the size of this
11065 instruction, this can lead to a loop, so we arrange to always
11066 use an extended opcode. We only check this when we are in
11067 the main relaxation loop, when SEC is NULL. */
11068 if ((val & ((1 << op->shift) - 1)) != 0 && sec == NULL)
11070 fragp->fr_subtype =
11071 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
11075 /* If we are about to mark a frag as extended because the value
11076 is precisely maxtiny + 1, then there is a chance of an
11077 infinite loop as in the following code:
11082 In this case when the la is extended, foo is 0x3fc bytes
11083 away, so the la can be shrunk, but then foo is 0x400 away, so
11084 the la must be extended. To avoid this loop, we mark the
11085 frag as extended if it was small, and is about to become
11086 extended with a value of maxtiny + 1. */
11087 if (val == ((maxtiny + 1) << op->shift)
11088 && ! RELAX_MIPS16_EXTENDED (fragp->fr_subtype)
11091 fragp->fr_subtype =
11092 RELAX_MIPS16_MARK_LONG_BRANCH (fragp->fr_subtype);
11096 else if (symsec != absolute_section && sec != NULL)
11097 as_bad_where (fragp->fr_file, fragp->fr_line, _("unsupported relocation"));
11099 if ((val & ((1 << op->shift) - 1)) != 0
11100 || val < (mintiny << op->shift)
11101 || val > (maxtiny << op->shift))
11107 /* Estimate the size of a frag before relaxing. Unless this is the
11108 mips16, we are not really relaxing here, and the final size is
11109 encoded in the subtype information. For the mips16, we have to
11110 decide whether we are using an extended opcode or not. */
11113 md_estimate_size_before_relax (fragp, segtype)
11118 boolean linkonce = false;
11120 if (RELAX_MIPS16_P (fragp->fr_subtype))
11122 if (mips16_extended_frag (fragp, segtype, 0))
11124 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
11129 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
11134 if (mips_pic == NO_PIC)
11136 change = nopic_need_relax (fragp->fr_symbol, 0);
11138 else if (mips_pic == SVR4_PIC)
11143 sym = fragp->fr_symbol;
11145 /* Handle the case of a symbol equated to another symbol. */
11146 while (symbol_equated_reloc_p (sym))
11150 /* It's possible to get a loop here in a badly written
11152 n = symbol_get_value_expression (sym)->X_add_symbol;
11158 symsec = S_GET_SEGMENT (sym);
11160 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
11161 if (symsec != segtype && ! S_IS_LOCAL (sym))
11163 if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE)
11167 /* The GNU toolchain uses an extension for ELF: a section
11168 beginning with the magic string .gnu.linkonce is a linkonce
11170 if (strncmp (segment_name (symsec), ".gnu.linkonce",
11171 sizeof ".gnu.linkonce" - 1) == 0)
11175 /* This must duplicate the test in adjust_reloc_syms. */
11176 change = (symsec != &bfd_und_section
11177 && symsec != &bfd_abs_section
11178 && ! bfd_is_com_section (symsec)
11181 /* A global or weak symbol is treated as external. */
11182 && (OUTPUT_FLAVOR == bfd_target_elf_flavour
11183 && ! (S_IS_EXTERN (sym) || S_IS_WEAK (sym)))
11192 /* Record the offset to the first reloc in the fr_opcode field.
11193 This lets md_convert_frag and tc_gen_reloc know that the code
11194 must be expanded. */
11195 fragp->fr_opcode = (fragp->fr_literal
11197 - RELAX_OLD (fragp->fr_subtype)
11198 + RELAX_RELOC1 (fragp->fr_subtype));
11199 /* FIXME: This really needs as_warn_where. */
11200 if (RELAX_WARN (fragp->fr_subtype))
11201 as_warn (_("AT used after \".set noat\" or macro used after "
11202 "\".set nomacro\""));
11204 return RELAX_NEW (fragp->fr_subtype) - RELAX_OLD (fragp->fr_subtype);
11210 /* This is called to see whether a reloc against a defined symbol
11211 should be converted into a reloc against a section. Don't adjust
11212 MIPS16 jump relocations, so we don't have to worry about the format
11213 of the offset in the .o file. Don't adjust relocations against
11214 mips16 symbols, so that the linker can find them if it needs to set
11218 mips_fix_adjustable (fixp)
11222 /* Prevent all adjustments to global symbols. */
11223 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
11224 && (S_IS_EXTERN (fixp->fx_addsy) || S_IS_WEAK (fixp->fx_addsy)))
11227 if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP)
11229 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
11230 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
11232 if (fixp->fx_addsy == NULL)
11235 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
11236 && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16
11237 && fixp->fx_subsy == NULL)
11243 /* Translate internal representation of relocation info to BFD target
11247 tc_gen_reloc (section, fixp)
11248 asection *section ATTRIBUTE_UNUSED;
11251 static arelent *retval[4];
11253 bfd_reloc_code_real_type code;
11255 reloc = retval[0] = (arelent *) xmalloc (sizeof (arelent));
11258 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
11259 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
11260 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
11262 if (mips_pic == EMBEDDED_PIC
11263 && SWITCH_TABLE (fixp))
11265 /* For a switch table entry we use a special reloc. The addend
11266 is actually the difference between the reloc address and the
11268 reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy);
11269 if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour)
11270 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
11271 fixp->fx_r_type = BFD_RELOC_GPREL32;
11273 else if (fixp->fx_pcrel == 0 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
11274 reloc->addend = fixp->fx_addnumber;
11275 else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16)
11277 /* We use a special addend for an internal RELLO reloc. */
11278 if (symbol_section_p (fixp->fx_addsy))
11279 reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy);
11281 reloc->addend = fixp->fx_addnumber + reloc->address;
11283 else if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S)
11285 assert (fixp->fx_next != NULL
11286 && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16);
11287 /* We use a special addend for an internal RELHI reloc. The
11288 reloc is relative to the RELLO; adjust the addend
11290 if (symbol_section_p (fixp->fx_addsy))
11291 reloc->addend = (fixp->fx_next->fx_frag->fr_address
11292 + fixp->fx_next->fx_where
11293 - S_GET_VALUE (fixp->fx_subsy));
11295 reloc->addend = (fixp->fx_addnumber
11296 + fixp->fx_next->fx_frag->fr_address
11297 + fixp->fx_next->fx_where);
11301 if (OUTPUT_FLAVOR != bfd_target_aout_flavour)
11302 /* A gruesome hack which is a result of the gruesome gas reloc
11304 reloc->addend = reloc->address;
11306 reloc->addend = -reloc->address;
11309 /* If this is a variant frag, we may need to adjust the existing
11310 reloc and generate a new one. */
11311 if (fixp->fx_frag->fr_opcode != NULL
11312 && (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL
11313 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT16
11314 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL16
11315 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16
11316 || fixp->fx_r_type == BFD_RELOC_MIPS_GOT_LO16
11317 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16
11318 || fixp->fx_r_type == BFD_RELOC_MIPS_CALL_LO16))
11322 assert (! RELAX_MIPS16_P (fixp->fx_frag->fr_subtype));
11324 /* If this is not the last reloc in this frag, then we have two
11325 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
11326 CALL_HI16/CALL_LO16, both of which are being replaced. Let
11327 the second one handle all of them. */
11328 if (fixp->fx_next != NULL
11329 && fixp->fx_frag == fixp->fx_next->fx_frag)
11331 assert ((fixp->fx_r_type == BFD_RELOC_MIPS_GPREL
11332 && fixp->fx_next->fx_r_type == BFD_RELOC_MIPS_GPREL)
11333 || (fixp->fx_r_type == BFD_RELOC_MIPS_GOT_HI16
11334 && (fixp->fx_next->fx_r_type
11335 == BFD_RELOC_MIPS_GOT_LO16))
11336 || (fixp->fx_r_type == BFD_RELOC_MIPS_CALL_HI16
11337 && (fixp->fx_next->fx_r_type
11338 == BFD_RELOC_MIPS_CALL_LO16)));
11343 fixp->fx_where = fixp->fx_frag->fr_opcode - fixp->fx_frag->fr_literal;
11344 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
11345 reloc2 = retval[1] = (arelent *) xmalloc (sizeof (arelent));
11347 reloc2->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
11348 *reloc2->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
11349 reloc2->address = (reloc->address
11350 + (RELAX_RELOC2 (fixp->fx_frag->fr_subtype)
11351 - RELAX_RELOC1 (fixp->fx_frag->fr_subtype)));
11352 reloc2->addend = fixp->fx_addnumber;
11353 reloc2->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO16);
11354 assert (reloc2->howto != NULL);
11356 if (RELAX_RELOC3 (fixp->fx_frag->fr_subtype))
11360 reloc3 = retval[2] = (arelent *) xmalloc (sizeof (arelent));
11363 reloc3->address += 4;
11366 if (mips_pic == NO_PIC)
11368 assert (fixp->fx_r_type == BFD_RELOC_MIPS_GPREL);
11369 fixp->fx_r_type = BFD_RELOC_HI16_S;
11371 else if (mips_pic == SVR4_PIC)
11373 switch (fixp->fx_r_type)
11377 case BFD_RELOC_MIPS_GOT16:
11379 case BFD_RELOC_MIPS_CALL16:
11380 case BFD_RELOC_MIPS_GOT_LO16:
11381 case BFD_RELOC_MIPS_CALL_LO16:
11382 fixp->fx_r_type = BFD_RELOC_MIPS_GOT16;
11390 /* Since MIPS ELF uses Rel instead of Rela, encode the vtable entry
11391 to be used in the relocation's section offset. */
11392 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
11394 reloc->address = reloc->addend;
11398 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
11399 fixup_segment converted a non-PC relative reloc into a PC
11400 relative reloc. In such a case, we need to convert the reloc
11402 code = fixp->fx_r_type;
11403 if (fixp->fx_pcrel)
11408 code = BFD_RELOC_8_PCREL;
11411 code = BFD_RELOC_16_PCREL;
11414 code = BFD_RELOC_32_PCREL;
11417 code = BFD_RELOC_64_PCREL;
11419 case BFD_RELOC_8_PCREL:
11420 case BFD_RELOC_16_PCREL:
11421 case BFD_RELOC_32_PCREL:
11422 case BFD_RELOC_64_PCREL:
11423 case BFD_RELOC_16_PCREL_S2:
11424 case BFD_RELOC_PCREL_HI16_S:
11425 case BFD_RELOC_PCREL_LO16:
11428 as_bad_where (fixp->fx_file, fixp->fx_line,
11429 _("Cannot make %s relocation PC relative"),
11430 bfd_get_reloc_code_name (code));
11434 /* To support a PC relative reloc when generating embedded PIC code
11435 for ECOFF, we use a Cygnus extension. We check for that here to
11436 make sure that we don't let such a reloc escape normally. */
11437 if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour
11438 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
11439 && code == BFD_RELOC_16_PCREL_S2
11440 && mips_pic != EMBEDDED_PIC)
11441 reloc->howto = NULL;
11443 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
11445 if (reloc->howto == NULL)
11447 as_bad_where (fixp->fx_file, fixp->fx_line,
11448 _("Can not represent %s relocation in this object file format"),
11449 bfd_get_reloc_code_name (code));
11456 /* Relax a machine dependent frag. This returns the amount by which
11457 the current size of the frag should change. */
11460 mips_relax_frag (fragp, stretch)
11464 if (! RELAX_MIPS16_P (fragp->fr_subtype))
11467 if (mips16_extended_frag (fragp, (asection *) NULL, stretch))
11469 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
11471 fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
11476 if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
11478 fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
11485 /* Convert a machine dependent frag. */
11488 md_convert_frag (abfd, asec, fragp)
11489 bfd *abfd ATTRIBUTE_UNUSED;
11496 if (RELAX_MIPS16_P (fragp->fr_subtype))
11499 register const struct mips16_immed_operand *op;
11500 boolean small, ext;
11503 unsigned long insn;
11504 boolean use_extend;
11505 unsigned short extend;
11507 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
11508 op = mips16_immed_operands;
11509 while (op->type != type)
11512 if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
11523 resolve_symbol_value (fragp->fr_symbol);
11524 val = S_GET_VALUE (fragp->fr_symbol);
11529 addr = fragp->fr_address + fragp->fr_fix;
11531 /* The rules for the base address of a PC relative reloc are
11532 complicated; see mips16_extended_frag. */
11533 if (type == 'p' || type == 'q')
11538 /* Ignore the low bit in the target, since it will be
11539 set for a text label. */
11540 if ((val & 1) != 0)
11543 else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
11545 else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
11548 addr &= ~ (addressT) ((1 << op->shift) - 1);
11551 /* Make sure the section winds up with the alignment we have
11554 record_alignment (asec, op->shift);
11558 && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
11559 || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
11560 as_warn_where (fragp->fr_file, fragp->fr_line,
11561 _("extended instruction in delay slot"));
11563 buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
11565 if (target_big_endian)
11566 insn = bfd_getb16 (buf);
11568 insn = bfd_getl16 (buf);
11570 mips16_immed (fragp->fr_file, fragp->fr_line, type, val,
11571 RELAX_MIPS16_USER_EXT (fragp->fr_subtype),
11572 small, ext, &insn, &use_extend, &extend);
11576 md_number_to_chars (buf, 0xf000 | extend, 2);
11577 fragp->fr_fix += 2;
11581 md_number_to_chars (buf, insn, 2);
11582 fragp->fr_fix += 2;
11587 if (fragp->fr_opcode == NULL)
11590 old = RELAX_OLD (fragp->fr_subtype);
11591 new = RELAX_NEW (fragp->fr_subtype);
11592 fixptr = fragp->fr_literal + fragp->fr_fix;
11595 memcpy (fixptr - old, fixptr, new);
11597 fragp->fr_fix += new - old;
11603 /* This function is called after the relocs have been generated.
11604 We've been storing mips16 text labels as odd. Here we convert them
11605 back to even for the convenience of the debugger. */
11608 mips_frob_file_after_relocs ()
11611 unsigned int count, i;
11613 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
11616 syms = bfd_get_outsymbols (stdoutput);
11617 count = bfd_get_symcount (stdoutput);
11618 for (i = 0; i < count; i++, syms++)
11620 if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16
11621 && ((*syms)->value & 1) != 0)
11623 (*syms)->value &= ~1;
11624 /* If the symbol has an odd size, it was probably computed
11625 incorrectly, so adjust that as well. */
11626 if ((elf_symbol (*syms)->internal_elf_sym.st_size & 1) != 0)
11627 ++elf_symbol (*syms)->internal_elf_sym.st_size;
11634 /* This function is called whenever a label is defined. It is used
11635 when handling branch delays; if a branch has a label, we assume we
11636 can not move it. */
11639 mips_define_label (sym)
11642 struct insn_label_list *l;
11644 if (free_insn_labels == NULL)
11645 l = (struct insn_label_list *) xmalloc (sizeof *l);
11648 l = free_insn_labels;
11649 free_insn_labels = l->next;
11653 l->next = insn_labels;
11657 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11659 /* Some special processing for a MIPS ELF file. */
11662 mips_elf_final_processing ()
11664 /* Write out the register information. */
11669 s.ri_gprmask = mips_gprmask;
11670 s.ri_cprmask[0] = mips_cprmask[0];
11671 s.ri_cprmask[1] = mips_cprmask[1];
11672 s.ri_cprmask[2] = mips_cprmask[2];
11673 s.ri_cprmask[3] = mips_cprmask[3];
11674 /* The gp_value field is set by the MIPS ELF backend. */
11676 bfd_mips_elf32_swap_reginfo_out (stdoutput, &s,
11677 ((Elf32_External_RegInfo *)
11678 mips_regmask_frag));
11682 Elf64_Internal_RegInfo s;
11684 s.ri_gprmask = mips_gprmask;
11686 s.ri_cprmask[0] = mips_cprmask[0];
11687 s.ri_cprmask[1] = mips_cprmask[1];
11688 s.ri_cprmask[2] = mips_cprmask[2];
11689 s.ri_cprmask[3] = mips_cprmask[3];
11690 /* The gp_value field is set by the MIPS ELF backend. */
11692 bfd_mips_elf64_swap_reginfo_out (stdoutput, &s,
11693 ((Elf64_External_RegInfo *)
11694 mips_regmask_frag));
11697 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
11698 sort of BFD interface for this. */
11699 if (mips_any_noreorder)
11700 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NOREORDER;
11701 if (mips_pic != NO_PIC)
11702 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
11704 /* Set the MIPS ELF ABI flags. */
11705 if (mips_abi_string == NULL)
11707 else if (strcmp (mips_abi_string, "32") == 0)
11708 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
11709 else if (strcmp (mips_abi_string, "o64") == 0)
11710 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
11711 else if (strcmp (mips_abi_string, "eabi") == 0)
11714 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
11716 elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
11718 else if (strcmp (mips_abi_string, "n32") == 0)
11719 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
11721 /* Nothing to do for "64". */
11723 if (mips_32bitmode)
11724 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
11727 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
11729 typedef struct proc {
11731 unsigned long reg_mask;
11732 unsigned long reg_offset;
11733 unsigned long fpreg_mask;
11734 unsigned long fpreg_offset;
11735 unsigned long frame_offset;
11736 unsigned long frame_reg;
11737 unsigned long pc_reg;
11740 static procS cur_proc;
11741 static procS *cur_proc_ptr;
11742 static int numprocs;
11744 /* Fill in an rs_align_code fragment. */
11747 mips_handle_align (fragp)
11750 if (fragp->fr_type != rs_align_code)
11753 if (mips_opts.mips16)
11755 static const unsigned char be_nop[] = { 0x65, 0x00 };
11756 static const unsigned char le_nop[] = { 0x00, 0x65 };
11761 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
11762 p = fragp->fr_literal + fragp->fr_fix;
11767 fragp->fr_fix += 1;
11770 memcpy (p, (target_big_endian ? be_nop : le_nop), 2);
11774 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
11785 /* check for premature end, nesting errors, etc */
11787 as_warn (_("missing .end at end of assembly"));
11796 if (*input_line_pointer == '-')
11798 ++input_line_pointer;
11801 if (!ISDIGIT (*input_line_pointer))
11802 as_bad (_("Expected simple number."));
11803 if (input_line_pointer[0] == '0')
11805 if (input_line_pointer[1] == 'x')
11807 input_line_pointer += 2;
11808 while (ISXDIGIT (*input_line_pointer))
11811 val |= hex_value (*input_line_pointer++);
11813 return negative ? -val : val;
11817 ++input_line_pointer;
11818 while (ISDIGIT (*input_line_pointer))
11821 val |= *input_line_pointer++ - '0';
11823 return negative ? -val : val;
11826 if (!ISDIGIT (*input_line_pointer))
11828 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
11829 *input_line_pointer, *input_line_pointer);
11830 as_warn (_("Invalid number"));
11833 while (ISDIGIT (*input_line_pointer))
11836 val += *input_line_pointer++ - '0';
11838 return negative ? -val : val;
11841 /* The .file directive; just like the usual .file directive, but there
11842 is an initial number which is the ECOFF file index. */
11846 int x ATTRIBUTE_UNUSED;
11850 line = get_number ();
11854 /* The .end directive. */
11858 int x ATTRIBUTE_UNUSED;
11863 if (!is_end_of_line[(unsigned char) *input_line_pointer])
11866 demand_empty_rest_of_line ();
11871 #ifdef BFD_ASSEMBLER
11872 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
11877 if (now_seg != data_section && now_seg != bss_section)
11884 as_warn (_(".end not in text section"));
11888 as_warn (_(".end directive without a preceding .ent directive."));
11889 demand_empty_rest_of_line ();
11895 assert (S_GET_NAME (p));
11896 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym)))
11897 as_warn (_(".end symbol does not match .ent symbol."));
11900 as_warn (_(".end directive missing or unknown symbol"));
11902 #ifdef MIPS_STABS_ELF
11904 segT saved_seg = now_seg;
11905 subsegT saved_subseg = now_subseg;
11910 dot = frag_now_fix ();
11912 #ifdef md_flush_pending_output
11913 md_flush_pending_output ();
11917 subseg_set (pdr_seg, 0);
11919 /* Write the symbol. */
11920 exp.X_op = O_symbol;
11921 exp.X_add_symbol = p;
11922 exp.X_add_number = 0;
11923 emit_expr (&exp, 4);
11925 fragp = frag_more (7 * 4);
11927 md_number_to_chars (fragp, (valueT) cur_proc_ptr->reg_mask, 4);
11928 md_number_to_chars (fragp + 4, (valueT) cur_proc_ptr->reg_offset, 4);
11929 md_number_to_chars (fragp + 8, (valueT) cur_proc_ptr->fpreg_mask, 4);
11930 md_number_to_chars (fragp + 12, (valueT) cur_proc_ptr->fpreg_offset, 4);
11931 md_number_to_chars (fragp + 16, (valueT) cur_proc_ptr->frame_offset, 4);
11932 md_number_to_chars (fragp + 20, (valueT) cur_proc_ptr->frame_reg, 4);
11933 md_number_to_chars (fragp + 24, (valueT) cur_proc_ptr->pc_reg, 4);
11935 subseg_set (saved_seg, saved_subseg);
11939 cur_proc_ptr = NULL;
11942 /* The .aent and .ent directives. */
11952 symbolP = get_symbol ();
11953 if (*input_line_pointer == ',')
11954 input_line_pointer++;
11955 SKIP_WHITESPACE ();
11956 if (ISDIGIT (*input_line_pointer)
11957 || *input_line_pointer == '-')
11958 number = get_number ();
11960 #ifdef BFD_ASSEMBLER
11961 if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
11966 if (now_seg != data_section && now_seg != bss_section)
11973 as_warn (_(".ent or .aent not in text section."));
11975 if (!aent && cur_proc_ptr)
11976 as_warn (_("missing .end"));
11980 cur_proc_ptr = &cur_proc;
11981 memset (cur_proc_ptr, '\0', sizeof (procS));
11983 cur_proc_ptr->isym = symbolP;
11985 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
11990 demand_empty_rest_of_line ();
11993 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
11994 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
11995 s_mips_frame is used so that we can set the PDR information correctly.
11996 We can't use the ecoff routines because they make reference to the ecoff
11997 symbol table (in the mdebug section). */
12000 s_mips_frame (ignore)
12001 int ignore ATTRIBUTE_UNUSED;
12003 #ifdef MIPS_STABS_ELF
12007 if (cur_proc_ptr == (procS *) NULL)
12009 as_warn (_(".frame outside of .ent"));
12010 demand_empty_rest_of_line ();
12014 cur_proc_ptr->frame_reg = tc_get_register (1);
12016 SKIP_WHITESPACE ();
12017 if (*input_line_pointer++ != ','
12018 || get_absolute_expression_and_terminator (&val) != ',')
12020 as_warn (_("Bad .frame directive"));
12021 --input_line_pointer;
12022 demand_empty_rest_of_line ();
12026 cur_proc_ptr->frame_offset = val;
12027 cur_proc_ptr->pc_reg = tc_get_register (0);
12029 demand_empty_rest_of_line ();
12032 #endif /* MIPS_STABS_ELF */
12035 /* The .fmask and .mask directives. If the mdebug section is present
12036 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
12037 embedded targets, s_mips_mask is used so that we can set the PDR
12038 information correctly. We can't use the ecoff routines because they
12039 make reference to the ecoff symbol table (in the mdebug section). */
12042 s_mips_mask (reg_type)
12045 #ifdef MIPS_STABS_ELF
12048 if (cur_proc_ptr == (procS *) NULL)
12050 as_warn (_(".mask/.fmask outside of .ent"));
12051 demand_empty_rest_of_line ();
12055 if (get_absolute_expression_and_terminator (&mask) != ',')
12057 as_warn (_("Bad .mask/.fmask directive"));
12058 --input_line_pointer;
12059 demand_empty_rest_of_line ();
12063 off = get_absolute_expression ();
12065 if (reg_type == 'F')
12067 cur_proc_ptr->fpreg_mask = mask;
12068 cur_proc_ptr->fpreg_offset = off;
12072 cur_proc_ptr->reg_mask = mask;
12073 cur_proc_ptr->reg_offset = off;
12076 demand_empty_rest_of_line ();
12078 s_ignore (reg_type);
12079 #endif /* MIPS_STABS_ELF */
12082 /* The .loc directive. */
12093 assert (now_seg == text_section);
12095 lineno = get_number ();
12096 addroff = frag_now_fix ();
12098 symbolP = symbol_new ("", N_SLINE, addroff, frag_now);
12099 S_SET_TYPE (symbolP, N_SLINE);
12100 S_SET_OTHER (symbolP, 0);
12101 S_SET_DESC (symbolP, lineno);
12102 symbolP->sy_segment = now_seg;
12106 /* CPU name/ISA/number mapping table.
12108 Entries are grouped by type. The first matching CPU or ISA entry
12109 gets chosen by CPU or ISA, so it should be the 'canonical' name
12110 for that type. Entries after that within the type are sorted
12113 Case is ignored in comparison, so put the canonical entry in the
12114 appropriate case but everything else in lower case to ease eye pain. */
12115 static const struct mips_cpu_info mips_cpu_info_table[] =
12118 { "MIPS1", 1, ISA_MIPS1, CPU_R3000, },
12119 { "mips", 1, ISA_MIPS1, CPU_R3000, },
12122 { "MIPS2", 1, ISA_MIPS2, CPU_R6000, },
12125 { "MIPS3", 1, ISA_MIPS3, CPU_R4000, },
12128 { "MIPS4", 1, ISA_MIPS4, CPU_R8000, },
12131 { "MIPS5", 1, ISA_MIPS5, CPU_MIPS5, },
12132 { "Generic-MIPS5", 0, ISA_MIPS5, CPU_MIPS5, },
12135 { "MIPS32", 1, ISA_MIPS32, CPU_MIPS32, },
12136 { "mipsisa32", 0, ISA_MIPS32, CPU_MIPS32, },
12137 { "Generic-MIPS32", 0, ISA_MIPS32, CPU_MIPS32, },
12138 { "4kc", 0, ISA_MIPS32, CPU_MIPS32, },
12139 { "4km", 0, ISA_MIPS32, CPU_MIPS32, },
12140 { "4kp", 0, ISA_MIPS32, CPU_MIPS32, },
12142 /* For historical reasons. */
12143 { "MIPS64", 1, ISA_MIPS3, CPU_R4000, },
12146 { "mipsisa64", 1, ISA_MIPS64, CPU_MIPS64, },
12147 { "Generic-MIPS64", 0, ISA_MIPS64, CPU_MIPS64, },
12148 { "5kc", 0, ISA_MIPS64, CPU_MIPS64, },
12149 { "20kc", 0, ISA_MIPS64, CPU_MIPS64, },
12152 { "R2000", 0, ISA_MIPS1, CPU_R2000, },
12153 { "2000", 0, ISA_MIPS1, CPU_R2000, },
12154 { "2k", 0, ISA_MIPS1, CPU_R2000, },
12155 { "r2k", 0, ISA_MIPS1, CPU_R2000, },
12158 { "R3000", 0, ISA_MIPS1, CPU_R3000, },
12159 { "3000", 0, ISA_MIPS1, CPU_R3000, },
12160 { "3k", 0, ISA_MIPS1, CPU_R3000, },
12161 { "r3k", 0, ISA_MIPS1, CPU_R3000, },
12164 { "R3900", 0, ISA_MIPS1, CPU_R3900, },
12165 { "3900", 0, ISA_MIPS1, CPU_R3900, },
12166 { "mipstx39", 0, ISA_MIPS1, CPU_R3900, },
12169 { "R4000", 0, ISA_MIPS3, CPU_R4000, },
12170 { "4000", 0, ISA_MIPS3, CPU_R4000, },
12171 { "4k", 0, ISA_MIPS3, CPU_R4000, }, /* beware */
12172 { "r4k", 0, ISA_MIPS3, CPU_R4000, },
12175 { "R4010", 0, ISA_MIPS2, CPU_R4010, },
12176 { "4010", 0, ISA_MIPS2, CPU_R4010, },
12179 { "R4400", 0, ISA_MIPS3, CPU_R4400, },
12180 { "4400", 0, ISA_MIPS3, CPU_R4400, },
12183 { "R4600", 0, ISA_MIPS3, CPU_R4600, },
12184 { "4600", 0, ISA_MIPS3, CPU_R4600, },
12185 { "mips64orion", 0, ISA_MIPS3, CPU_R4600, },
12186 { "orion", 0, ISA_MIPS3, CPU_R4600, },
12189 { "R4650", 0, ISA_MIPS3, CPU_R4650, },
12190 { "4650", 0, ISA_MIPS3, CPU_R4650, },
12193 { "R6000", 0, ISA_MIPS2, CPU_R6000, },
12194 { "6000", 0, ISA_MIPS2, CPU_R6000, },
12195 { "6k", 0, ISA_MIPS2, CPU_R6000, },
12196 { "r6k", 0, ISA_MIPS2, CPU_R6000, },
12199 { "R8000", 0, ISA_MIPS4, CPU_R8000, },
12200 { "8000", 0, ISA_MIPS4, CPU_R8000, },
12201 { "8k", 0, ISA_MIPS4, CPU_R8000, },
12202 { "r8k", 0, ISA_MIPS4, CPU_R8000, },
12205 { "R10000", 0, ISA_MIPS4, CPU_R10000, },
12206 { "10000", 0, ISA_MIPS4, CPU_R10000, },
12207 { "10k", 0, ISA_MIPS4, CPU_R10000, },
12208 { "r10k", 0, ISA_MIPS4, CPU_R10000, },
12211 { "R12000", 0, ISA_MIPS4, CPU_R12000, },
12212 { "12000", 0, ISA_MIPS4, CPU_R12000, },
12213 { "12k", 0, ISA_MIPS4, CPU_R12000, },
12214 { "r12k", 0, ISA_MIPS4, CPU_R12000, },
12217 { "VR4100", 0, ISA_MIPS3, CPU_VR4100, },
12218 { "4100", 0, ISA_MIPS3, CPU_VR4100, },
12219 { "mips64vr4100", 0, ISA_MIPS3, CPU_VR4100, },
12220 { "r4100", 0, ISA_MIPS3, CPU_VR4100, },
12223 { "VR4111", 0, ISA_MIPS3, CPU_R4111, },
12224 { "4111", 0, ISA_MIPS3, CPU_R4111, },
12225 { "mips64vr4111", 0, ISA_MIPS3, CPU_R4111, },
12226 { "r4111", 0, ISA_MIPS3, CPU_R4111, },
12229 { "VR4300", 0, ISA_MIPS3, CPU_R4300, },
12230 { "4300", 0, ISA_MIPS3, CPU_R4300, },
12231 { "mips64vr4300", 0, ISA_MIPS3, CPU_R4300, },
12232 { "r4300", 0, ISA_MIPS3, CPU_R4300, },
12235 { "VR5000", 0, ISA_MIPS4, CPU_R5000, },
12236 { "5000", 0, ISA_MIPS4, CPU_R5000, },
12237 { "5k", 0, ISA_MIPS4, CPU_R5000, },
12238 { "mips64vr5000", 0, ISA_MIPS4, CPU_R5000, },
12239 { "r5000", 0, ISA_MIPS4, CPU_R5000, },
12240 { "r5200", 0, ISA_MIPS4, CPU_R5000, },
12241 { "rm5200", 0, ISA_MIPS4, CPU_R5000, },
12242 { "r5230", 0, ISA_MIPS4, CPU_R5000, },
12243 { "rm5230", 0, ISA_MIPS4, CPU_R5000, },
12244 { "r5231", 0, ISA_MIPS4, CPU_R5000, },
12245 { "rm5231", 0, ISA_MIPS4, CPU_R5000, },
12246 { "r5261", 0, ISA_MIPS4, CPU_R5000, },
12247 { "rm5261", 0, ISA_MIPS4, CPU_R5000, },
12248 { "r5721", 0, ISA_MIPS4, CPU_R5000, },
12249 { "rm5721", 0, ISA_MIPS4, CPU_R5000, },
12250 { "r5k", 0, ISA_MIPS4, CPU_R5000, },
12251 { "r7000", 0, ISA_MIPS4, CPU_R5000, },
12253 /* SiByte SB-1 CPU */
12254 { "SB-1", 0, ISA_MIPS64, CPU_SB1, },
12255 { "sb-1250", 0, ISA_MIPS64, CPU_SB1, },
12256 { "sb1", 0, ISA_MIPS64, CPU_SB1, },
12257 { "sb1250", 0, ISA_MIPS64, CPU_SB1, },
12260 { NULL, 0, 0, 0, },
12263 static const struct mips_cpu_info *
12264 mips_cpu_info_from_name (name)
12269 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
12270 if (strcasecmp (name, mips_cpu_info_table[i].name) == 0)
12271 return (&mips_cpu_info_table[i]);
12276 static const struct mips_cpu_info *
12277 mips_cpu_info_from_isa (isa)
12282 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
12283 if (mips_cpu_info_table[i].is_isa
12284 && isa == mips_cpu_info_table[i].isa)
12285 return (&mips_cpu_info_table[i]);
12290 static const struct mips_cpu_info *
12291 mips_cpu_info_from_cpu (cpu)
12296 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
12297 if (!mips_cpu_info_table[i].is_isa
12298 && cpu == mips_cpu_info_table[i].cpu)
12299 return (&mips_cpu_info_table[i]);