drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Copyright (c) 2018 Synopsys, Inc. and/or its affiliates.
   4  * stmmac XGMAC support.
   5  */
   6
   7 #include <linux/iopoll.h>
   8 #include "stmmac.h"
   9 #include "dwxgmac2.h"
  10
  11 static int dwxgmac2_dma_reset(void __iomem *ioaddr)
  12 {
  13         u32 value = readl(ioaddr + XGMAC_DMA_MODE);
  14
  15         /* DMA SW reset */
  16         writel(value | XGMAC_SWR, ioaddr + XGMAC_DMA_MODE);
  17
  18         return readl_poll_timeout(ioaddr + XGMAC_DMA_MODE, value,
  19                                   !(value & XGMAC_SWR), 0, 100000);
  20 }
  21
  22 static void dwxgmac2_dma_init(void __iomem *ioaddr,
  23                               struct stmmac_dma_cfg *dma_cfg, int atds)
  24 {
  25         u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE);
  26
  27         if (dma_cfg->aal)
  28                 value |= XGMAC_AAL;
  29
  30         if (dma_cfg->eame)
  31                 value |= XGMAC_EAME;
  32
  33         writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE);
  34 }
  35
  36 static void dwxgmac2_dma_init_chan(void __iomem *ioaddr,
  37                                    struct stmmac_dma_cfg *dma_cfg, u32 chan)
  38 {
  39         u32 value = readl(ioaddr + XGMAC_DMA_CH_CONTROL(chan));
  40
  41         if (dma_cfg->pblx8)
  42                 value |= XGMAC_PBLx8;
  43
  44         writel(value, ioaddr + XGMAC_DMA_CH_CONTROL(chan));
  45         writel(XGMAC_DMA_INT_DEFAULT_EN, ioaddr + XGMAC_DMA_CH_INT_EN(chan));
  46 }
  47
  48 static void dwxgmac2_dma_init_rx_chan(void __iomem *ioaddr,
  49                                       struct stmmac_dma_cfg *dma_cfg,
  50                                       dma_addr_t phy, u32 chan)
  51 {
  52         u32 rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl;
  53         u32 value;
  54
  55         value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
  56         value &= ~XGMAC_RxPBL;
  57         value |= (rxpbl << XGMAC_RxPBL_SHIFT) & XGMAC_RxPBL;
  58         writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
  59
  60         writel(upper_32_bits(phy), ioaddr + XGMAC_DMA_CH_RxDESC_HADDR(chan));
  61         writel(lower_32_bits(phy), ioaddr + XGMAC_DMA_CH_RxDESC_LADDR(chan));
  62 }
  63
  64 static void dwxgmac2_dma_init_tx_chan(void __iomem *ioaddr,
  65                                       struct stmmac_dma_cfg *dma_cfg,
  66                                       dma_addr_t phy, u32 chan)
  67 {
  68         u32 txpbl = dma_cfg->txpbl ?: dma_cfg->pbl;
  69         u32 value;
  70
  71         value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
  72         value &= ~XGMAC_TxPBL;
  73         value |= (txpbl << XGMAC_TxPBL_SHIFT) & XGMAC_TxPBL;
  74         value |= XGMAC_OSP;
  75         writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
  76
  77         writel(upper_32_bits(phy), ioaddr + XGMAC_DMA_CH_TxDESC_HADDR(chan));
  78         writel(lower_32_bits(phy), ioaddr + XGMAC_DMA_CH_TxDESC_LADDR(chan));
  79 }
  80
  81 static void dwxgmac2_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)
  82 {
  83         u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE);
  84         int i;
  85
  86         if (axi->axi_lpi_en)
  87                 value |= XGMAC_EN_LPI;
  88         if (axi->axi_xit_frm)
  89                 value |= XGMAC_LPI_XIT_PKT;
  90
  91         value &= ~XGMAC_WR_OSR_LMT;
  92         value |= (axi->axi_wr_osr_lmt << XGMAC_WR_OSR_LMT_SHIFT) &
  93                 XGMAC_WR_OSR_LMT;
  94
  95         value &= ~XGMAC_RD_OSR_LMT;
  96         value |= (axi->axi_rd_osr_lmt << XGMAC_RD_OSR_LMT_SHIFT) &
  97                 XGMAC_RD_OSR_LMT;
  98
  99         if (!axi->axi_fb)
 100                 value |= XGMAC_UNDEF;
 101
 102         value &= ~XGMAC_BLEN;
 103         for (i = 0; i < AXI_BLEN; i++) {
 104                 switch (axi->axi_blen[i]) {
 105                 case 256:
 106                         value |= XGMAC_BLEN256;
 107                         break;
 108                 case 128:
 109                         value |= XGMAC_BLEN128;
 110                         break;
 111                 case 64:
 112                         value |= XGMAC_BLEN64;
 113                         break;
 114                 case 32:
 115                         value |= XGMAC_BLEN32;
 116                         break;
 117                 case 16:
 118                         value |= XGMAC_BLEN16;
 119                         break;
 120                 case 8:
 121                         value |= XGMAC_BLEN8;
 122                         break;
 123                 case 4:
 124                         value |= XGMAC_BLEN4;
 125                         break;
 126                 }
 127         }
 128
 129         writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE);
 130         writel(XGMAC_TDPS, ioaddr + XGMAC_TX_EDMA_CTRL);
 131         writel(XGMAC_RDPS, ioaddr + XGMAC_RX_EDMA_CTRL);
 132 }
 133
 134 static void dwxgmac2_dma_dump_regs(void __iomem *ioaddr, u32 *reg_space)
 135 {
 136         int i;
 137
 138         for (i = (XGMAC_DMA_MODE / 4); i < XGMAC_REGSIZE; i++)
 139                 reg_space[i] = readl(ioaddr + i * 4);
 140 }
 141
 142 static void dwxgmac2_dma_rx_mode(void __iomem *ioaddr, int mode,
 143                                  u32 channel, int fifosz, u8 qmode)
 144 {
 145         u32 value = readl(ioaddr + XGMAC_MTL_RXQ_OPMODE(channel));
 146         unsigned int rqs = fifosz / 256 - 1;
 147
 148         if (mode == SF_DMA_MODE) {
 149                 value |= XGMAC_RSF;
 150         } else {
 151                 value &= ~XGMAC_RSF;
 152                 value &= ~XGMAC_RTC;
 153
 154                 if (mode <= 64)
 155                         value |= 0x0 << XGMAC_RTC_SHIFT;
 156                 else if (mode <= 96)
 157                         value |= 0x2 << XGMAC_RTC_SHIFT;
 158                 else
 159                         value |= 0x3 << XGMAC_RTC_SHIFT;
 160         }
 161
 162         value &= ~XGMAC_RQS;
 163         value |= (rqs << XGMAC_RQS_SHIFT) & XGMAC_RQS;
 164
 165         if ((fifosz >= 4096) && (qmode != MTL_QUEUE_AVB)) {
 166                 u32 flow = readl(ioaddr + XGMAC_MTL_RXQ_FLOW_CONTROL(channel));
 167                 unsigned int rfd, rfa;
 168
 169                 value |= XGMAC_EHFC;
 170
 171                 /* Set Threshold for Activating Flow Control to min 2 frames,
 172                  * i.e. 1500 * 2 = 3000 bytes.
 173                  *
 174                  * Set Threshold for Deactivating Flow Control to min 1 frame,
 175                  * i.e. 1500 bytes.
 176                  */
 177                 switch (fifosz) {
 178                 case 4096:
 179                         /* This violates the above formula because of FIFO size
 180                          * limit therefore overflow may occur in spite of this.
 181                          */
 182                         rfd = 0x03; /* Full-2.5K */
 183                         rfa = 0x01; /* Full-1.5K */
 184                         break;
 185
 186                 default:
 187                         rfd = 0x07; /* Full-4.5K */
 188                         rfa = 0x04; /* Full-3K */
 189                         break;
 190                 }
 191
 192                 flow &= ~XGMAC_RFD;
 193                 flow |= rfd << XGMAC_RFD_SHIFT;
 194
 195                 flow &= ~XGMAC_RFA;
 196                 flow |= rfa << XGMAC_RFA_SHIFT;
 197
 198                 writel(flow, ioaddr + XGMAC_MTL_RXQ_FLOW_CONTROL(channel));
 199         }
 200
 201         writel(value, ioaddr + XGMAC_MTL_RXQ_OPMODE(channel));
 202
 203         /* Enable MTL RX overflow */
 204         value = readl(ioaddr + XGMAC_MTL_QINTEN(channel));
 205         writel(value | XGMAC_RXOIE, ioaddr + XGMAC_MTL_QINTEN(channel));
 206 }
 207
 208 static void dwxgmac2_dma_tx_mode(void __iomem *ioaddr, int mode,
 209                                  u32 channel, int fifosz, u8 qmode)
 210 {
 211         u32 value = readl(ioaddr + XGMAC_MTL_TXQ_OPMODE(channel));
 212         unsigned int tqs = fifosz / 256 - 1;
 213
 214         if (mode == SF_DMA_MODE) {
 215                 value |= XGMAC_TSF;
 216         } else {
 217                 value &= ~XGMAC_TSF;
 218                 value &= ~XGMAC_TTC;
 219
 220                 if (mode <= 64)
 221                         value |= 0x0 << XGMAC_TTC_SHIFT;
 222                 else if (mode <= 96)
 223                         value |= 0x2 << XGMAC_TTC_SHIFT;
 224                 else if (mode <= 128)
 225                         value |= 0x3 << XGMAC_TTC_SHIFT;
 226                 else if (mode <= 192)
 227                         value |= 0x4 << XGMAC_TTC_SHIFT;
 228                 else if (mode <= 256)
 229                         value |= 0x5 << XGMAC_TTC_SHIFT;
 230                 else if (mode <= 384)
 231                         value |= 0x6 << XGMAC_TTC_SHIFT;
 232                 else
 233                         value |= 0x7 << XGMAC_TTC_SHIFT;
 234         }
 235
 236         /* Use static TC to Queue mapping */
 237         value |= (channel << XGMAC_Q2TCMAP_SHIFT) & XGMAC_Q2TCMAP;
 238
 239         value &= ~XGMAC_TXQEN;
 240         if (qmode != MTL_QUEUE_AVB)
 241                 value |= 0x2 << XGMAC_TXQEN_SHIFT;
 242         else
 243                 value |= 0x1 << XGMAC_TXQEN_SHIFT;
 244
 245         value &= ~XGMAC_TQS;
 246         value |= (tqs << XGMAC_TQS_SHIFT) & XGMAC_TQS;
 247
 248         writel(value, ioaddr +  XGMAC_MTL_TXQ_OPMODE(channel));
 249 }
 250
 251 static void dwxgmac2_enable_dma_irq(void __iomem *ioaddr, u32 chan)
 252 {
 253         writel(XGMAC_DMA_INT_DEFAULT_EN, ioaddr + XGMAC_DMA_CH_INT_EN(chan));
 254 }
 255
 256 static void dwxgmac2_disable_dma_irq(void __iomem *ioaddr, u32 chan)
 257 {
 258         writel(0, ioaddr + XGMAC_DMA_CH_INT_EN(chan));
 259 }
 260
 261 static void dwxgmac2_dma_start_tx(void __iomem *ioaddr, u32 chan)
 262 {
 263         u32 value;
 264
 265         value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
 266         value |= XGMAC_TXST;
 267         writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
 268
 269         value = readl(ioaddr + XGMAC_TX_CONFIG);
 270         value |= XGMAC_CONFIG_TE;
 271         writel(value, ioaddr + XGMAC_TX_CONFIG);
 272 }
 273
 274 static void dwxgmac2_dma_stop_tx(void __iomem *ioaddr, u32 chan)
 275 {
 276         u32 value;
 277
 278         value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
 279         value &= ~XGMAC_TXST;
 280         writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
 281
 282         value = readl(ioaddr + XGMAC_TX_CONFIG);
 283         value &= ~XGMAC_CONFIG_TE;
 284         writel(value, ioaddr + XGMAC_TX_CONFIG);
 285 }
 286
 287 static void dwxgmac2_dma_start_rx(void __iomem *ioaddr, u32 chan)
 288 {
 289         u32 value;
 290
 291         value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
 292         value |= XGMAC_RXST;
 293         writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
 294
 295         value = readl(ioaddr + XGMAC_RX_CONFIG);
 296         value |= XGMAC_CONFIG_RE;
 297         writel(value, ioaddr + XGMAC_RX_CONFIG);
 298 }
 299
 300 static void dwxgmac2_dma_stop_rx(void __iomem *ioaddr, u32 chan)
 301 {
 302         u32 value;
 303
 304         value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
 305         value &= ~XGMAC_RXST;
 306         writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
 307 }
 308
 309 static int dwxgmac2_dma_interrupt(void __iomem *ioaddr,
 310                                   struct stmmac_extra_stats *x, u32 chan)
 311 {
 312         u32 intr_status = readl(ioaddr + XGMAC_DMA_CH_STATUS(chan));
 313         u32 intr_en = readl(ioaddr + XGMAC_DMA_CH_INT_EN(chan));
 314         int ret = 0;
 315
 316         /* ABNORMAL interrupts */
 317         if (unlikely(intr_status & XGMAC_AIS)) {
 318                 if (unlikely(intr_status & XGMAC_RBU)) {
 319                         x->rx_buf_unav_irq++;
 320                         ret |= handle_rx;
 321                 }
 322                 if (unlikely(intr_status & XGMAC_TPS)) {
 323                         x->tx_process_stopped_irq++;
 324                         ret |= tx_hard_error;
 325                 }
 326                 if (unlikely(intr_status & XGMAC_FBE)) {
 327                         x->fatal_bus_error_irq++;
 328                         ret |= tx_hard_error;
 329                 }
 330         }
 331
 332         /* TX/RX NORMAL interrupts */
 333         if (likely(intr_status & XGMAC_NIS)) {
 334                 x->normal_irq_n++;
 335
 336                 if (likely(intr_status & XGMAC_RI)) {
 337                         x->rx_normal_irq_n++;
 338                         ret |= handle_rx;
 339                 }
 340                 if (likely(intr_status & (XGMAC_TI | XGMAC_TBU))) {
 341                         x->tx_normal_irq_n++;
 342                         ret |= handle_tx;
 343                 }
 344         }
 345
 346         /* Clear interrupts */
 347         writel(intr_en & intr_status, ioaddr + XGMAC_DMA_CH_STATUS(chan));
 348
 349         return ret;
 350 }
 351
 352 static void dwxgmac2_get_hw_feature(void __iomem *ioaddr,
 353                                     struct dma_features *dma_cap)
 354 {
 355         u32 hw_cap;
 356
 357         /*  MAC HW feature 0 */
 358         hw_cap = readl(ioaddr + XGMAC_HW_FEATURE0);
 359         dma_cap->vlins = (hw_cap & XGMAC_HWFEAT_SAVLANINS) >> 27;
 360         dma_cap->rx_coe = (hw_cap & XGMAC_HWFEAT_RXCOESEL) >> 16;
 361         dma_cap->tx_coe = (hw_cap & XGMAC_HWFEAT_TXCOESEL) >> 14;
 362         dma_cap->eee = (hw_cap & XGMAC_HWFEAT_EEESEL) >> 13;
 363         dma_cap->atime_stamp = (hw_cap & XGMAC_HWFEAT_TSSEL) >> 12;
 364         dma_cap->av = (hw_cap & XGMAC_HWFEAT_AVSEL) >> 11;
 365         dma_cap->av &= !((hw_cap & XGMAC_HWFEAT_RAVSEL) >> 10);
 366         dma_cap->arpoffsel = (hw_cap & XGMAC_HWFEAT_ARPOFFSEL) >> 9;
 367         dma_cap->rmon = (hw_cap & XGMAC_HWFEAT_MMCSEL) >> 8;
 368         dma_cap->pmt_magic_frame = (hw_cap & XGMAC_HWFEAT_MGKSEL) >> 7;
 369         dma_cap->pmt_remote_wake_up = (hw_cap & XGMAC_HWFEAT_RWKSEL) >> 6;
 370         dma_cap->vlhash = (hw_cap & XGMAC_HWFEAT_VLHASH) >> 4;
 371         dma_cap->mbps_1000 = (hw_cap & XGMAC_HWFEAT_GMIISEL) >> 1;
 372
 373         /* MAC HW feature 1 */
 374         hw_cap = readl(ioaddr + XGMAC_HW_FEATURE1);
 375         dma_cap->l3l4fnum = (hw_cap & XGMAC_HWFEAT_L3L4FNUM) >> 27;
 376         dma_cap->hash_tb_sz = (hw_cap & XGMAC_HWFEAT_HASHTBLSZ) >> 24;
 377         dma_cap->rssen = (hw_cap & XGMAC_HWFEAT_RSSEN) >> 20;
 378         dma_cap->tsoen = (hw_cap & XGMAC_HWFEAT_TSOEN) >> 18;
 379         dma_cap->sphen = (hw_cap & XGMAC_HWFEAT_SPHEN) >> 17;
 380
 381         dma_cap->addr64 = (hw_cap & XGMAC_HWFEAT_ADDR64) >> 14;
 382         switch (dma_cap->addr64) {
 383         case 0:
 384                 dma_cap->addr64 = 32;
 385                 break;
 386         case 1:
 387                 dma_cap->addr64 = 40;
 388                 break;
 389         case 2:
 390                 dma_cap->addr64 = 48;
 391                 break;
 392         default:
 393                 dma_cap->addr64 = 32;
 394                 break;
 395         }
 396
 397         dma_cap->tx_fifo_size =
 398                 128 << ((hw_cap & XGMAC_HWFEAT_TXFIFOSIZE) >> 6);
 399         dma_cap->rx_fifo_size =
 400                 128 << ((hw_cap & XGMAC_HWFEAT_RXFIFOSIZE) >> 0);
 401
 402         /* MAC HW feature 2 */
 403         hw_cap = readl(ioaddr + XGMAC_HW_FEATURE2);
 404         dma_cap->pps_out_num = (hw_cap & XGMAC_HWFEAT_PPSOUTNUM) >> 24;
 405         dma_cap->number_tx_channel =
 406                 ((hw_cap & XGMAC_HWFEAT_TXCHCNT) >> 18) + 1;
 407         dma_cap->number_rx_channel =
 408                 ((hw_cap & XGMAC_HWFEAT_RXCHCNT) >> 12) + 1;
 409         dma_cap->number_tx_queues =
 410                 ((hw_cap & XGMAC_HWFEAT_TXQCNT) >> 6) + 1;
 411         dma_cap->number_rx_queues =
 412                 ((hw_cap & XGMAC_HWFEAT_RXQCNT) >> 0) + 1;
 413
 414         /* MAC HW feature 3 */
 415         hw_cap = readl(ioaddr + XGMAC_HW_FEATURE3);
 416         dma_cap->asp = (hw_cap & XGMAC_HWFEAT_ASP) >> 14;
 417         dma_cap->dvlan = (hw_cap & XGMAC_HWFEAT_DVLAN) >> 13;
 418         dma_cap->frpes = (hw_cap & XGMAC_HWFEAT_FRPES) >> 11;
 419         dma_cap->frpbs = (hw_cap & XGMAC_HWFEAT_FRPPB) >> 9;
 420         dma_cap->frpsel = (hw_cap & XGMAC_HWFEAT_FRPSEL) >> 3;
 421 }
 422
 423 static void dwxgmac2_rx_watchdog(void __iomem *ioaddr, u32 riwt, u32 nchan)
 424 {
 425         u32 i;
 426
 427         for (i = 0; i < nchan; i++)
 428                 writel(riwt & XGMAC_RWT, ioaddr + XGMAC_DMA_CH_Rx_WATCHDOG(i));
 429 }
 430
 431 static void dwxgmac2_set_rx_ring_len(void __iomem *ioaddr, u32 len, u32 chan)
 432 {
 433         writel(len, ioaddr + XGMAC_DMA_CH_RxDESC_RING_LEN(chan));
 434 }
 435
 436 static void dwxgmac2_set_tx_ring_len(void __iomem *ioaddr, u32 len, u32 chan)
 437 {
 438         writel(len, ioaddr + XGMAC_DMA_CH_TxDESC_RING_LEN(chan));
 439 }
 440
 441 static void dwxgmac2_set_rx_tail_ptr(void __iomem *ioaddr, u32 ptr, u32 chan)
 442 {
 443         writel(ptr, ioaddr + XGMAC_DMA_CH_RxDESC_TAIL_LPTR(chan));
 444 }
 445
 446 static void dwxgmac2_set_tx_tail_ptr(void __iomem *ioaddr, u32 ptr, u32 chan)
 447 {
 448         writel(ptr, ioaddr + XGMAC_DMA_CH_TxDESC_TAIL_LPTR(chan));
 449 }
 450
 451 static void dwxgmac2_enable_tso(void __iomem *ioaddr, bool en, u32 chan)
 452 {
 453         u32 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
 454
 455         if (en)
 456                 value |= XGMAC_TSE;
 457         else
 458                 value &= ~XGMAC_TSE;
 459
 460         writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));
 461 }
 462
 463 static void dwxgmac2_qmode(void __iomem *ioaddr, u32 channel, u8 qmode)
 464 {
 465         u32 value = readl(ioaddr + XGMAC_MTL_TXQ_OPMODE(channel));
 466         u32 flow = readl(ioaddr + XGMAC_RX_FLOW_CTRL);
 467
 468         value &= ~XGMAC_TXQEN;
 469         if (qmode != MTL_QUEUE_AVB) {
 470                 value |= 0x2 << XGMAC_TXQEN_SHIFT;
 471                 writel(0, ioaddr + XGMAC_MTL_TCx_ETS_CONTROL(channel));
 472         } else {
 473                 value |= 0x1 << XGMAC_TXQEN_SHIFT;
 474                 writel(flow & (~XGMAC_RFE), ioaddr + XGMAC_RX_FLOW_CTRL);
 475         }
 476
 477         writel(value, ioaddr +  XGMAC_MTL_TXQ_OPMODE(channel));
 478 }
 479
 480 static void dwxgmac2_set_bfsize(void __iomem *ioaddr, int bfsize, u32 chan)
 481 {
 482         u32 value;
 483
 484         value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
 485         value &= ~XGMAC_RBSZ;
 486         value |= bfsize << XGMAC_RBSZ_SHIFT;
 487         writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));
 488 }
 489
 490 static void dwxgmac2_enable_sph(void __iomem *ioaddr, bool en, u32 chan)
 491 {
 492         u32 value = readl(ioaddr + XGMAC_RX_CONFIG);
 493
 494         value &= ~XGMAC_CONFIG_HDSMS;
 495         value |= XGMAC_CONFIG_HDSMS_256; /* Segment max 256 bytes */
 496         writel(value, ioaddr + XGMAC_RX_CONFIG);
 497
 498         value = readl(ioaddr + XGMAC_DMA_CH_CONTROL(chan));
 499         if (en)
 500                 value |= XGMAC_SPH;
 501         else
 502                 value &= ~XGMAC_SPH;
 503         writel(value, ioaddr + XGMAC_DMA_CH_CONTROL(chan));
 504 }
 505
 506 const struct stmmac_dma_ops dwxgmac210_dma_ops = {
 507         .reset = dwxgmac2_dma_reset,
 508         .init = dwxgmac2_dma_init,
 509         .init_chan = dwxgmac2_dma_init_chan,
 510         .init_rx_chan = dwxgmac2_dma_init_rx_chan,
 511         .init_tx_chan = dwxgmac2_dma_init_tx_chan,
 512         .axi = dwxgmac2_dma_axi,
 513         .dump_regs = dwxgmac2_dma_dump_regs,
 514         .dma_rx_mode = dwxgmac2_dma_rx_mode,
 515         .dma_tx_mode = dwxgmac2_dma_tx_mode,
 516         .enable_dma_irq = dwxgmac2_enable_dma_irq,
 517         .disable_dma_irq = dwxgmac2_disable_dma_irq,
 518         .start_tx = dwxgmac2_dma_start_tx,
 519         .stop_tx = dwxgmac2_dma_stop_tx,
 520         .start_rx = dwxgmac2_dma_start_rx,
 521         .stop_rx = dwxgmac2_dma_stop_rx,
 522         .dma_interrupt = dwxgmac2_dma_interrupt,
 523         .get_hw_feature = dwxgmac2_get_hw_feature,
 524         .rx_watchdog = dwxgmac2_rx_watchdog,
 525         .set_rx_ring_len = dwxgmac2_set_rx_ring_len,
 526         .set_tx_ring_len = dwxgmac2_set_tx_ring_len,
 527         .set_rx_tail_ptr = dwxgmac2_set_rx_tail_ptr,
 528         .set_tx_tail_ptr = dwxgmac2_set_tx_tail_ptr,
 529         .enable_tso = dwxgmac2_enable_tso,
 530         .qmode = dwxgmac2_qmode,
 531         .set_bfsize = dwxgmac2_set_bfsize,
 532         .enable_sph = dwxgmac2_enable_sph,
 533 };