1 ; Generate .c/.h versions of main elements of cpu description file.
2 ; Copyright (C) 2000, 2001, 2002, 2003 Red Hat, Inc.
3 ; This file is part of CGEN.
7 (define (-gen-isa-table-defns)
8 (logit 2 "Generating isa table defns ...\n")
12 /* Instruction set variants. */
14 static const CGEN_ISA @arch@_cgen_isa_table[] = {
16 (string-list-map (lambda (isa)
20 "\"" (obj:str-name isa) "\", "
22 (isa-default-insn-bitsize isa))
25 (isa-base-insn-bitsize isa))
28 (isa-min-insn-bitsize isa))
31 (isa-max-insn-bitsize isa))
43 ; Return C code to describe the various cpu variants.
44 ; Currently this is quite simple, the various cpu names and their mach numbers
45 ; are recorded in a "keyword" table.
46 ; ??? No longer used as there is the mach attribute.
48 ;(set! mach-table (make <keyword> 'mach "machine list"
49 ; (make <attr-list> "" nil) ; FIXME: sanitization?
50 ; (map (lambda (elm) (list (obj:name elm) (mach-number elm)))
51 ; (current-mach-list))))
53 (define (-gen-mach-table-decls)
54 (logit 2 "Generating machine table decls ...\n")
55 "" ; (gen-decl mach-table)
58 (define (-gen-mach-table-defns)
59 (logit 2 "Generating machine table defns ...\n")
63 /* Machine variants. */
65 static const CGEN_MACH @arch@_cgen_mach_table[] = {
67 (string-list-map (lambda (mach)
71 "\"" (obj:str-name mach) "\", "
72 "\"" (mach-bfd-name mach) "\", "
74 (number->string (cpu-insn-chunk-bitsize (mach-cpu mach)))
84 ; Attribute support code.
86 ; Return C code to describe the various attributes.
88 (define (-gen-attr-table-decls)
89 (logit 2 "Generating attribute table decls ...\n")
92 "extern const CGEN_ATTR_TABLE @arch@_cgen_hardware_attr_table[];\n"
93 "extern const CGEN_ATTR_TABLE @arch@_cgen_ifield_attr_table[];\n"
94 "extern const CGEN_ATTR_TABLE @arch@_cgen_operand_attr_table[];\n"
95 "extern const CGEN_ATTR_TABLE @arch@_cgen_insn_attr_table[];\n"
100 ; Alternative GEN-MASK argument to gen-bool-attrs.
101 ; This uses the `A' macro to abbreviate the attribute definition.
103 (define (gen-A-attr-mask prefix name)
104 (string-append "A(" (string-upcase (gen-c-symbol name)) ")")
107 ; Instruction fields support code.
109 ; Return C code to declare various ifield bits.
111 (define (gen-ifld-decls)
112 (logit 2 "Generating instruction field decls ...\n")
114 "/* Ifield support. */\n\n"
115 "extern const struct cgen_ifld @arch@_cgen_ifld_table[];\n\n"
116 "/* Ifield attribute indices. */\n\n"
117 (gen-attr-enum-decl "cgen_ifld" (current-ifld-attr-list))
118 (gen-enum-decl 'ifield_type "@arch@ ifield types"
120 (append (gen-obj-list-enums (non-derived-ifields (current-ifld-list)))
122 "#define MAX_IFLD ((int) @ARCH@_F_MAX)\n\n"
126 ; Return C code to define the instruction field table,
127 ; and any other ifield related definitions.
129 (define (gen-ifld-defns)
130 (logit 2 "Generating ifield table ...\n")
131 (let* ((ifld-list (current-ifld-list))
132 (all-attrs (current-ifld-attr-list))
133 (num-non-bools (attr-count-non-bools all-attrs)))
136 /* The instruction field table. */
139 (gen-define-with-symcat "A(a) (1 << CGEN_IFLD_" "a)")
141 const CGEN_IFLD @arch@_cgen_ifld_table[] =
146 (gen-obj-sanitize ifld
149 (ifld-enum ifld) ", "
150 "\"" (obj:str-name ifld) "\", "
152 (or (has-attr? ifld 'VIRTUAL)
153 (derived-ifield? ifld))
156 (number->string (ifld-word-offset ifld)) ", "
157 (number->string (ifld-word-length ifld)) ", "
158 (number->string (ifld-start ifld #f)) ", "
159 (number->string (ifld-length ifld)) ", "))
160 (gen-obj-attr-defn 'ifld ifld all-attrs
161 num-non-bools gen-A-attr-mask)
165 { 0, 0, 0, 0, 0, 0, {0, {0}} }
176 ; Return C code to declare the various hardware bits
177 ; that can be (or must be) defined before including opcode/cgen.h.
179 (define (gen-hw-decls)
180 (logit 2 "Generating hardware decls ...\n")
182 "/* Hardware attribute indices. */\n\n"
183 (gen-attr-enum-decl "cgen_hw" (current-hw-attr-list))
184 (gen-enum-decl 'cgen_hw_type "@arch@ hardware types"
185 "HW_" ; FIXME: @ARCH@_
186 (append (nub (map (lambda (hw)
187 (cons (hw-sem-name hw)
192 (lambda (elm) (car elm)))
194 "#define MAX_HW ((int) HW_MAX)\n\n"
198 ; Return declarations of variables tables used by HW.
200 (define (-gen-hw-decl hw)
202 (if (and (hw-indices hw)
203 ; ??? Commented out as opcode changes are needed
204 ) ; (not (obj-has-attr? (hw-indices hw) 'PRIVATE)))
205 (gen-decl (hw-indices hw))
207 (if (and (hw-values hw)
208 ; ??? Commented out as opcode changes are needed
209 ) ; (not (obj-has-attr? (hw-values hw) 'PRIVATE)))
210 (gen-decl (hw-values hw))
215 ; Return C code to declare the various hardware bits
216 ; that must be defined after including opcode/cgen.h.
218 (define (gen-hw-table-decls)
219 (logit 2 "Generating hardware table decls ...\n")
221 "/* Hardware decls. */\n\n"
222 (string-map -gen-hw-decl (current-hw-list))
224 "extern const CGEN_HW_ENTRY @arch@_cgen_hw_table[];\n"
228 ; Return definitions of variables tables used by HW.
229 ; Only do this for `PRIVATE' elements. Public ones are emitted elsewhere.
231 (define (-gen-hw-defn hw)
233 (if (and (hw-indices hw)
234 (obj-has-attr? (hw-indices hw) 'PRIVATE))
235 (gen-defn (hw-indices hw))
237 (if (and (hw-values hw)
238 (obj-has-attr? (hw-values hw) 'PRIVATE))
239 (gen-defn (hw-values hw))
244 ; Generate the tables for the various hardware bits (register names, etc.).
245 ; A table is generated for each element, and then another table is generated
246 ; which collects them all together.
247 ; Uses include looking up a particular register set so that a new reg
248 ; can be added to it [at runtime].
250 (define (gen-hw-table-defns)
251 (logit 2 "Generating hardware table ...\n")
252 (let* ((all-attrs (current-hw-attr-list))
253 (num-non-bools (attr-count-non-bools all-attrs)))
255 (string-list-map gen-defn (current-kw-list))
256 (string-list-map -gen-hw-defn (current-hw-list))
258 /* The hardware table. */
261 (gen-define-with-symcat "A(a) (1 << CGEN_HW_" "a)")
263 const CGEN_HW_ENTRY @arch@_cgen_hw_table[] =
271 "\"" (obj:str-name hw) "\", "
273 ; ??? No element currently requires both indices and
274 ; values specs so we only output the needed one.
275 (or (and (hw-indices hw)
276 (send (hw-indices hw) 'gen-table-entry))
278 (send (hw-values hw) 'gen-table-entry))
279 "CGEN_ASM_NONE, 0, ")
280 (gen-obj-attr-defn 'hw hw all-attrs
281 num-non-bools gen-A-attr-mask)
285 { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} }
294 ; Utilities of cgen-opc.h.
296 ; Return #define's of several constants.
297 ; FIXME: Some of these to be moved into table of structs, one per cpu family.
299 (define (-gen-hash-defines)
300 (logit 2 "Generating #define's ...\n")
302 "#define CGEN_ARCH @arch@\n\n"
303 "/* Given symbol S, return @arch@_cgen_<S>. */\n"
304 (gen-define-with-symcat "CGEN_SYM(s) @arch@" "_cgen_" "s")
305 "\n\n/* Selected cpu families. */\n"
306 ; FIXME: Move to sim's arch.h.
307 (string-map (lambda (cpu)
308 (gen-obj-sanitize cpu
309 (string-append "#define HAVE_CPU_"
310 (string-upcase (gen-sym cpu))
314 "#define CGEN_INSN_LSB0_P " (if (current-arch-insn-lsb0?) "1" "0")
316 "/* Minimum size of any insn (in bytes). */\n"
317 "#define CGEN_MIN_INSN_SIZE "
318 (number->string (bits->bytes
319 (apply min (map isa-min-insn-bitsize (current-isa-list)))))
321 "/* Maximum size of any insn (in bytes). */\n"
322 "#define CGEN_MAX_INSN_SIZE "
323 (number->string (bits->bytes
324 (apply max (map isa-max-insn-bitsize (current-isa-list)))))
326 ; This tells the assembler/disassembler whether or not it can use an int to
327 ; record insns, which is faster. Since this controls the typedef of the
328 ; insn buffer, only enable this if all isas support it.
329 "#define CGEN_INT_INSN_P "
330 (if (all-true? (map isa-integral-insn? (current-isa-list))) "1" "0")
333 "/* Maximum number of syntax elements in an instruction. */\n"
334 "#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS "
335 ; The +2 account for the leading "MNEM" and trailing 0.
336 (number->string (+ 2 (apply max (map (lambda (insn)
337 (length (syntax-break-out (insn-syntax insn))))
338 (current-insn-list)))))
341 "/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.\n"
342 " e.g. In \"b,a foo\" the \",a\" is an operand. If mnemonics have operands\n"
343 " we can't hash on everything up to the space. */\n"
345 "/*#define CGEN_MNEMONIC_OPERANDS*/\n"
346 "#define CGEN_MNEMONIC_OPERANDS\n")
348 ; "/* Maximum number of operands any insn or macro-insn has. */\n"
349 ; FIXME: Should compute.
350 ; "#define CGEN_MAX_INSN_OPERANDS 16\n"
352 "/* Maximum number of fields in an instruction. */\n"
353 "#define CGEN_ACTUAL_MAX_IFMT_OPERANDS "
354 (number->string (apply max (map (lambda (f) (length (ifmt-ifields f)))
355 (current-ifmt-list))))
362 ; Return C code to declare various operand bits.
364 (define (gen-operand-decls)
365 (logit 2 "Generating operand decls ...\n")
367 "/* Operand attribute indices. */\n\n"
368 (gen-attr-enum-decl "cgen_operand" (current-op-attr-list))
369 (gen-enum-decl 'cgen_operand_type "@arch@ operand types"
371 (nub (append (gen-obj-list-enums (current-op-list))
374 "/* Number of operands types. */\n"
375 "#define MAX_OPERANDS " (number->string (length (gen-obj-list-enums (current-op-list)))) "\n\n"
376 ; was: "#define MAX_OPERANDS ((int) @ARCH@_OPERAND_MAX)\n\n"
377 "/* Maximum number of operands referenced by any insn. */\n"
378 "#define MAX_OPERAND_INSTANCES "
379 (number->string (max-operand-instances))
384 ; Generate C code to define the operand table.
386 (define ifld-number-cache #f)
387 (define (ifld-number f)
388 (if (not ifld-number-cache)
389 (let* ((ls (find (lambda (f) (not (has-attr? f 'VIRTUAL)))
390 (non-derived-ifields (current-ifld-list))))
391 (numls (iota (length ls))))
392 (set! ifld-number-cache
393 (map (lambda (elt num) (cons (obj:name elt) num))
395 (number->string (cdr (assoc (obj:name f) ifld-number-cache))))
397 (define (gen-maybe-multi-ifld-of-op op)
398 (let* ((idx (op:index op))
399 (ty (hw-index:type idx))
400 (fld (hw-index:value idx)))
401 (gen-maybe-multi-ifld ty fld)))
403 (define (gen-maybe-multi-ifld ty fld)
404 (let* ((field-ref "0")
406 (if (equal? ty 'ifield)
407 (if (multi-ifield? fld)
409 (set! field-ref (string-append "&" (ifld-enum fld) "_MULTI_IFIELD[0]"))
410 (set! field-count (number->string (length (elm-get fld 'subfields)))))
412 (set! field-ref (string-append "&@arch@_cgen_ifld_table[" (ifld-enum fld) "]"))))
413 (string-append "{ " field-count ", { (const PTR) " field-ref " } }")))
415 (define (gen-multi-ifield-nodes)
416 (let ((multis (find multi-ifield? (current-ifld-list))))
420 '("\n\n/* multi ifield declarations */\n\n")
424 "const CGEN_MAYBE_MULTI_IFLD "
425 (ifld-enum ifld) "_MULTI_IFIELD [];\n"))
428 '("\n\n/* multi ifield definitions */\n\n")
432 "const CGEN_MAYBE_MULTI_IFLD "
433 (ifld-enum ifld) "_MULTI_IFIELD [] =\n{"
435 (map (lambda (x) (string-append "\n " (gen-maybe-multi-ifld 'ifield x) ","))
436 (elm-get ifld 'subfields)))
437 "\n { 0, { (const PTR) 0 } }\n};\n"))
440 (define (gen-operand-table)
441 (logit 2 "Generating operand table ...\n")
442 (let* ((all-attrs (current-op-attr-list))
443 (num-non-bools (attr-count-non-bools all-attrs)))
446 /* The operand table. */
449 (gen-define-with-symcat "A(a) (1 << CGEN_OPERAND_" "a)")
450 (gen-define-with-symcat "OPERAND(op) @ARCH@_OPERAND_" "op")
452 const CGEN_OPERAND @arch@_cgen_operand_table[] =
459 "/* " (obj:str-name op) ": " (obj:comment op) " */\n"
460 (if (or (derived-operand? op)
465 "\"" (obj:str-name op) "\", "
467 (hw-enum (op:hw-name op)) ", "
468 (number->string (op:start op)) ", "
469 (number->string (op:length op)) ",\n"
471 (gen-maybe-multi-ifld-of-op op) ", \n"
473 (gen-obj-attr-defn 'operand op all-attrs
474 num-non-bools gen-A-attr-mask)
479 { 0, 0, 0, 0, 0,\n { 0, { (const PTR) 0 } },\n { 0, { 0 } } }
489 ; Instruction table support.
491 ; Return C code to declare various insn bits.
493 (define (gen-insn-decls)
494 (logit 2 "Generating instruction decls ...\n")
496 "/* Insn attribute indices. */\n\n"
497 (gen-attr-enum-decl "cgen_insn" (current-insn-attr-list))
501 ; Generate an insn table entry for INSN.
502 ; ALL-ATTRS is a list of all instruction attributes.
503 ; NUM-NON-BOOLS is the number of non-boolean insn attributes.
505 (define (gen-insn-table-entry insn all-attrs num-non-bools)
509 "/* " (insn-syntax insn) " */\n"
512 (if (has-attr? insn 'ALIAS) "-1" (insn-enum insn)) ", "
513 "\"" (obj:str-name insn) "\", "
514 "\"" (insn-mnemonic insn) "\", "
515 ;(if (has-attr? insn 'ALIAS) "0" (number->string (insn-length insn))) ",\n"
516 (number->string (insn-length insn)) ",\n"
517 ; ??? There is currently a problem with embedded newlines, and this might
518 ; best be put in another file [the table is already pretty big].
519 ; Might also wish to output bytecodes instead.
521 ; (if (insn-semantics insn)
522 ; (string-append "\""
523 ; (with-output-to-string
524 ; ; ??? Should we do macro expansion here?
525 ; (lambda () (display (insn-semantics insn))))
529 ; ??? Might wish to output the raw format spec here instead
530 ; (either as plain text or bytecodes).
531 ; Values could be lazily computed and cached.
533 (gen-obj-attr-defn 'insn insn all-attrs num-non-bools gen-A-attr-mask)
537 ; Generate insn table.
539 (define (gen-insn-table)
540 (logit 2 "Generating instruction table ...\n")
541 (let* ((all-attrs (current-insn-attr-list))
542 (num-non-bools (attr-count-non-bools all-attrs)))
545 /* The instruction table. */
547 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
549 (gen-define-with-symcat "A(a) (1 << CGEN_INSN_" "a)")
551 static const CGEN_IBASE @arch@_cgen_insn_table[MAX_INSNS] =
553 /* Special null first entry.
554 A `num' value of zero is thus invalid.
555 Also, the special `invalid' insn resides here. */
556 { 0, 0, 0, 0, {0, {0}} },\n"
559 (string-write-map (lambda (insn)
560 (logit 3 "Generating insn table entry for " (obj:name insn) " ...\n")
561 (gen-insn-table-entry insn all-attrs num-non-bools))
562 (non-multi-insns (current-insn-list))))
575 ; Cpu table handling support.
577 ; ??? A lot of this can live in a machine independent file, but there's
578 ; currently no place to put this file (there's no libcgen). libopcodes is the
579 ; wrong place as some simulator ports use this but they don't use libopcodes.
581 ; Return C routines to open/close a cpu description table.
582 ; This is defined here and not in cgen-opc.in because it refers to
583 ; CGEN_{ASM,DIS}_HASH and insn_table/macro_insn_table which is defined
584 ; earlier in the file. ??? Things can certainly be rearranged though
585 ; and opcodes/cgen.sh modified to insert the generated part into the middle
586 ; of the file like is done for assembler/disassembler support.
588 (define (-gen-cpu-open)
591 static const CGEN_MACH * lookup_mach_via_bfd_name
592 PARAMS ((const CGEN_MACH *, const char *));
593 static void build_hw_table PARAMS ((CGEN_CPU_TABLE *));
594 static void build_ifield_table PARAMS ((CGEN_CPU_TABLE *));
595 static void build_operand_table PARAMS ((CGEN_CPU_TABLE *));
596 static void build_insn_table PARAMS ((CGEN_CPU_TABLE *));
597 static void @arch@_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *));
599 /* Subroutine of @arch@_cgen_cpu_open to look up a mach via its bfd name. */
601 static const CGEN_MACH *
602 lookup_mach_via_bfd_name (table, name)
603 const CGEN_MACH *table;
608 if (strcmp (name, table->bfd_name) == 0)
615 /* Subroutine of @arch@_cgen_cpu_open to build the hardware table. */
622 int machs = cd->machs;
623 const CGEN_HW_ENTRY *init = & @arch@_cgen_hw_table[0];
624 /* MAX_HW is only an upper bound on the number of selected entries.
625 However each entry is indexed by it's enum so there can be holes in
627 const CGEN_HW_ENTRY **selected =
628 (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
630 cd->hw_table.init_entries = init;
631 cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
632 memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
633 /* ??? For now we just use machs to determine which ones we want. */
634 for (i = 0; init[i].name != NULL; ++i)
635 if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
637 selected[init[i].type] = &init[i];
638 cd->hw_table.entries = selected;
639 cd->hw_table.num_entries = MAX_HW;
642 /* Subroutine of @arch@_cgen_cpu_open to build the hardware table. */
645 build_ifield_table (cd)
648 cd->ifld_table = & @arch@_cgen_ifld_table[0];
651 /* Subroutine of @arch@_cgen_cpu_open to build the hardware table. */
654 build_operand_table (cd)
658 int machs = cd->machs;
659 const CGEN_OPERAND *init = & @arch@_cgen_operand_table[0];
660 /* MAX_OPERANDS is only an upper bound on the number of selected entries.
661 However each entry is indexed by it's enum so there can be holes in
663 const CGEN_OPERAND **selected =
664 (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *));
666 cd->operand_table.init_entries = init;
667 cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
668 memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
669 /* ??? For now we just use mach to determine which ones we want. */
670 for (i = 0; init[i].name != NULL; ++i)
671 if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
673 selected[init[i].type] = &init[i];
674 cd->operand_table.entries = selected;
675 cd->operand_table.num_entries = MAX_OPERANDS;
678 /* Subroutine of @arch@_cgen_cpu_open to build the hardware table.
679 ??? This could leave out insns not supported by the specified mach/isa,
680 but that would cause errors like \"foo only supported by bar\" to become
681 \"unknown insn\", so for now we include all insns and require the app to
682 do the checking later.
683 ??? On the other hand, parsing of such insns may require their hardware or
684 operand elements to be in the table [which they mightn't be]. */
687 build_insn_table (cd)
691 const CGEN_IBASE *ib = & @arch@_cgen_insn_table[0];
692 CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
694 memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
695 for (i = 0; i < MAX_INSNS; ++i)
696 insns[i].base = &ib[i];
697 cd->insn_table.init_entries = insns;
698 cd->insn_table.entry_size = sizeof (CGEN_IBASE);
699 cd->insn_table.num_init_entries = MAX_INSNS;
702 /* Subroutine of @arch@_cgen_cpu_open to rebuild the tables. */
705 @arch@_cgen_rebuild_tables (cd)
709 unsigned int isas = cd->isas;
710 unsigned int machs = cd->machs;
712 cd->int_insn_p = CGEN_INT_INSN_P;
714 /* Data derived from the isa spec. */
715 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
716 cd->default_insn_bitsize = UNSET;
717 cd->base_insn_bitsize = UNSET;
718 cd->min_insn_bitsize = 65535; /* some ridiculously big number */
719 cd->max_insn_bitsize = 0;
720 for (i = 0; i < MAX_ISAS; ++i)
721 if (((1 << i) & isas) != 0)
723 const CGEN_ISA *isa = & @arch@_cgen_isa_table[i];
725 /* Default insn sizes of all selected isas must be
726 equal or we set the result to 0, meaning \"unknown\". */
727 if (cd->default_insn_bitsize == UNSET)
728 cd->default_insn_bitsize = isa->default_insn_bitsize;
729 else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
732 cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
734 /* Base insn sizes of all selected isas must be equal
735 or we set the result to 0, meaning \"unknown\". */
736 if (cd->base_insn_bitsize == UNSET)
737 cd->base_insn_bitsize = isa->base_insn_bitsize;
738 else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
741 cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
743 /* Set min,max insn sizes. */
744 if (isa->min_insn_bitsize < cd->min_insn_bitsize)
745 cd->min_insn_bitsize = isa->min_insn_bitsize;
746 if (isa->max_insn_bitsize > cd->max_insn_bitsize)
747 cd->max_insn_bitsize = isa->max_insn_bitsize;
750 /* Data derived from the mach spec. */
751 for (i = 0; i < MAX_MACHS; ++i)
752 if (((1 << i) & machs) != 0)
754 const CGEN_MACH *mach = & @arch@_cgen_mach_table[i];
756 if (mach->insn_chunk_bitsize != 0)
758 if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
760 fprintf (stderr, \"@arch@_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\\n\",
761 cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
765 cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
769 /* Determine which hw elements are used by MACH. */
772 /* Build the ifield table. */
773 build_ifield_table (cd);
775 /* Determine which operands are used by MACH/ISA. */
776 build_operand_table (cd);
778 /* Build the instruction table. */
779 build_insn_table (cd);
782 /* Initialize a cpu table and return a descriptor.
783 It's much like opening a file, and must be the first function called.
784 The arguments are a set of (type/value) pairs, terminated with
787 Currently supported values:
788 CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr
789 CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr
790 CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
791 CGEN_CPU_OPEN_ENDIAN: specify endian choice
792 CGEN_CPU_OPEN_END: terminates arguments
794 ??? Simultaneous multiple isas might not make sense, but it's not (yet)
797 ??? We only support ISO C stdargs here, not K&R.
798 Laziness, plus experiment to see if anything requires K&R - eventually
799 K&R will no longer be supported - e.g. GDB is currently trying this. */
802 @arch@_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
804 CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
806 unsigned int isas = 0; /* 0 = \"unspecified\" */
807 unsigned int machs = 0; /* 0 = \"unspecified\" */
808 enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
817 memset (cd, 0, sizeof (*cd));
819 va_start (ap, arg_type);
820 while (arg_type != CGEN_CPU_OPEN_END)
824 case CGEN_CPU_OPEN_ISAS :
825 isas = va_arg (ap, unsigned int);
827 case CGEN_CPU_OPEN_MACHS :
828 machs = va_arg (ap, unsigned int);
830 case CGEN_CPU_OPEN_BFDMACH :
832 const char *name = va_arg (ap, const char *);
833 const CGEN_MACH *mach =
834 lookup_mach_via_bfd_name (@arch@_cgen_mach_table, name);
836 machs |= 1 << mach->num;
839 case CGEN_CPU_OPEN_ENDIAN :
840 endian = va_arg (ap, enum cgen_endian);
843 fprintf (stderr, \"@arch@_cgen_cpu_open: unsupported argument `%d'\\n\",
845 abort (); /* ??? return NULL? */
847 arg_type = va_arg (ap, enum cgen_cpu_open_arg);
851 /* mach unspecified means \"all\" */
853 machs = (1 << MAX_MACHS) - 1;
854 /* base mach is always selected */
856 /* isa unspecified means \"all\" */
858 isas = (1 << MAX_ISAS) - 1;
859 if (endian == CGEN_ENDIAN_UNKNOWN)
861 /* ??? If target has only one, could have a default. */
862 fprintf (stderr, \"@arch@_cgen_cpu_open: no endianness specified\\n\");
869 /* FIXME: for the sparc case we can determine insn-endianness statically.
870 The worry here is where both data and insn endian can be independently
871 chosen, in which case this function will need another argument.
872 Actually, will want to allow for more arguments in the future anyway. */
873 cd->insn_endian = endian;
875 /* Table (re)builder. */
876 cd->rebuild_tables = @arch@_cgen_rebuild_tables;
877 @arch@_cgen_rebuild_tables (cd);
879 /* Default to not allowing signed overflow. */
880 cd->signed_overflow_ok_p = 0;
882 return (CGEN_CPU_DESC) cd;
885 /* Cover fn to @arch@_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
886 MACH_NAME is the bfd name of the mach. */
889 @arch@_cgen_cpu_open_1 (mach_name, endian)
890 const char *mach_name;
891 enum cgen_endian endian;
893 return @arch@_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
894 CGEN_CPU_OPEN_ENDIAN, endian,
898 /* Close a cpu table.
899 ??? This can live in a machine independent file, but there's currently
900 no place to put this file (there's no libcgen). libopcodes is the wrong
901 place as some simulator ports use this but they don't use libopcodes. */
904 @arch@_cgen_cpu_close (cd)
908 const CGEN_INSN *insns;
910 if (cd->macro_insn_table.init_entries)
912 insns = cd->macro_insn_table.init_entries;
913 for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
915 if (CGEN_INSN_RX ((insns)))
916 regfree (CGEN_INSN_RX (insns));
920 if (cd->insn_table.init_entries)
922 insns = cd->insn_table.init_entries;
923 for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
925 if (CGEN_INSN_RX (insns))
926 regfree (CGEN_INSN_RX (insns));
932 if (cd->macro_insn_table.init_entries)
933 free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
935 if (cd->insn_table.init_entries)
936 free ((CGEN_INSN *) cd->insn_table.init_entries);
938 if (cd->hw_table.entries)
939 free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
941 if (cd->operand_table.entries)
942 free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
950 ; General initialization C code
951 ; Code is appended during processing.
953 (define -cputab-init-code "")
954 (define (cputab-add-init! code)
955 (set! -cputab-init-code (string-append -cputab-init-code code))
958 ; Return the C code to define the various initialization functions.
959 ; This does not include assembler/disassembler specific stuff.
960 ; Generally, this function doesn't do anything.
961 ; It exists to allow a global-static-constructor kind of thing should
962 ; one ever be necessary.
964 (define (gen-init-fns)
965 (logit 2 "Generating init fns ...\n")
968 /* Initialize anything needed to be done once, before any cpu_open call. */
969 static void init_tables PARAMS ((void));
979 ; Top level C code generators
981 ; FIXME: Create enum objects for all the enums we explicitly declare here.
982 ; Then they'd be usable and we wouldn't have to special case them here.
984 (define (cgen-desc.h)
985 (logit 1 "Generating " (current-arch-name) " desc.h ...\n")
987 (gen-c-copyright "CPU data header for @arch@."
988 CURRENT-COPYRIGHT CURRENT-PACKAGE)
995 ; This is defined in arch.h. It's not defined here as there is yet to
996 ; be a need for it in the assembler/disassembler.
997 ;(gen-enum-decl 'model_type "model types"
999 ; (append (map list (map obj:name (current-model-list))) '((max))))
1000 ;"#define MAX_MODELS ((int) MODEL_MAX)\n\n"
1002 (string-map gen-decl (current-enum-list))
1003 "/* Attributes. */\n\n"
1004 (string-map gen-decl (current-attr-list))
1005 "/* Number of architecture variants. */\n"
1006 ; If there is only 1 isa, leave out special handling. */
1007 (if (= (length (current-isa-list)) 1)
1008 "#define MAX_ISAS 1\n"
1009 "#define MAX_ISAS ((int) ISA_MAX)\n")
1010 "#define MAX_MACHS ((int) MACH_MAX)\n\n"
1015 "/* cgen.h uses things we just defined. */\n"
1016 "#include \"opcode/cgen.h\"\n\n"
1017 -gen-attr-table-decls
1018 -gen-mach-table-decls
1021 (lambda () (gen-extra-cpu.h (opc-file-path) (current-arch-name)))
1024 #endif /* @ARCH@_CPU_H */
1029 ; This file contains the "top level" definitions of the cpu.
1030 ; This includes various elements of the description file, expressed in C.
1032 ; ??? A lot of this file can go in a machine-independent file! However,
1033 ; some simulators don't use the cgen opcodes support so there is currently
1034 ; no place to put this file. To be revisited when we do have such a place.
1036 (define (cgen-desc.c)
1037 (logit 1 "Generating " (current-arch-name) " desc.c ...\n")
1039 (gen-c-copyright "CPU data for @arch@."
1040 CURRENT-COPYRIGHT CURRENT-PACKAGE)
1042 #include \"sysdep.h\"
1045 #include \"ansidecl.h\"
1047 #include \"symcat.h\"
1048 #include \"@arch@-desc.h\"
1049 #include \"@arch@-opc.h\"
1050 #include \"opintl.h\"
1051 #include \"libiberty.h\"
1052 #include \"xregex.h\"
1054 (lambda () (gen-extra-cpu.c (opc-file-path) (current-arch-name)))
1055 gen-attr-table-defns
1056 -gen-isa-table-defns
1057 -gen-mach-table-defns
1060 gen-multi-ifield-nodes