1 ; Generate .c/.h versions of main elements of cpu description file.
2 ; Copyright (C) 2000, 2001, 2002, 2003 Red Hat, Inc.
3 ; This file is part of CGEN.
7 (define (-gen-isa-table-defns)
8 (logit 2 "Generating isa table defns ...\n")
12 /* Instruction set variants. */
14 static const CGEN_ISA @arch@_cgen_isa_table[] = {
16 (string-list-map (lambda (isa)
20 "\"" (obj:str-name isa) "\", "
22 (isa-default-insn-bitsize isa))
25 (isa-base-insn-bitsize isa))
28 (isa-min-insn-bitsize isa))
31 (isa-max-insn-bitsize isa))
43 ; Return C code to describe the various cpu variants.
44 ; Currently this is quite simple, the various cpu names and their mach numbers
45 ; are recorded in a "keyword" table.
46 ; ??? No longer used as there is the mach attribute.
48 ;(set! mach-table (make <keyword> 'mach "machine list"
49 ; (make <attr-list> "" nil) ; FIXME: sanitization?
50 ; (map (lambda (elm) (list (obj:name elm) (mach-number elm)))
51 ; (current-mach-list))))
53 (define (-gen-mach-table-decls)
54 (logit 2 "Generating machine table decls ...\n")
55 "" ; (gen-decl mach-table)
58 (define (-gen-mach-table-defns)
59 (logit 2 "Generating machine table defns ...\n")
63 /* Machine variants. */
65 static const CGEN_MACH @arch@_cgen_mach_table[] = {
67 (string-list-map (lambda (mach)
71 "\"" (obj:str-name mach) "\", "
72 "\"" (mach-bfd-name mach) "\", "
74 (number->string (cpu-insn-chunk-bitsize (mach-cpu mach)))
84 ; Attribute support code.
86 ; Return C code to describe the various attributes.
88 (define (-gen-attr-table-decls)
89 (logit 2 "Generating attribute table decls ...\n")
92 "extern const CGEN_ATTR_TABLE @arch@_cgen_hardware_attr_table[];\n"
93 "extern const CGEN_ATTR_TABLE @arch@_cgen_ifield_attr_table[];\n"
94 "extern const CGEN_ATTR_TABLE @arch@_cgen_operand_attr_table[];\n"
95 "extern const CGEN_ATTR_TABLE @arch@_cgen_insn_attr_table[];\n"
100 ; Alternative GEN-MASK argument to gen-bool-attrs.
101 ; This uses the `A' macro to abbreviate the attribute definition.
103 (define (gen-A-attr-mask prefix name)
104 (string-append "A(" (string-upcase (gen-c-symbol name)) ")")
107 ; Instruction fields support code.
109 ; Return C code to declare various ifield bits.
111 (define (gen-ifld-decls)
112 (logit 2 "Generating instruction field decls ...\n")
114 "/* Ifield support. */\n\n"
115 "/* Ifield attribute indices. */\n\n"
116 (gen-attr-enum-decl "cgen_ifld" (current-ifld-attr-list))
117 (gen-enum-decl 'ifield_type "@arch@ ifield types"
119 (append (gen-obj-list-enums (non-derived-ifields (current-ifld-list)))
121 "#define MAX_IFLD ((int) @ARCH@_F_MAX)\n\n"
125 ; Return C code to define the instruction field table,
126 ; and any other ifield related definitions.
128 (define (gen-ifld-defns)
129 (logit 2 "Generating ifield table ...\n")
130 (let* ((ifld-list (current-ifld-list))
131 (all-attrs (current-ifld-attr-list))
132 (num-non-bools (attr-count-non-bools all-attrs)))
135 /* The instruction field table. */
138 (gen-define-with-symcat "A(a) (1 << CGEN_IFLD_" "a)")
140 const CGEN_IFLD @arch@_cgen_ifld_table[] =
145 (gen-obj-sanitize ifld
148 (ifld-enum ifld) ", "
149 "\"" (obj:str-name ifld) "\", "
151 (or (has-attr? ifld 'VIRTUAL)
152 (derived-ifield? ifld))
155 (number->string (ifld-word-offset ifld)) ", "
156 (number->string (ifld-word-length ifld)) ", "
157 (number->string (ifld-start ifld #f)) ", "
158 (number->string (ifld-length ifld)) ", "))
159 (gen-obj-attr-defn 'ifld ifld all-attrs
160 num-non-bools gen-A-attr-mask)
164 { 0, 0, 0, 0, 0, 0, {0, {0}} }
175 ; Return C code to declare the various hardware bits
176 ; that can be (or must be) defined before including opcode/cgen.h.
178 (define (gen-hw-decls)
179 (logit 2 "Generating hardware decls ...\n")
181 "/* Hardware attribute indices. */\n\n"
182 (gen-attr-enum-decl "cgen_hw" (current-hw-attr-list))
183 (gen-enum-decl 'cgen_hw_type "@arch@ hardware types"
184 "HW_" ; FIXME: @ARCH@_
185 (append (nub (map (lambda (hw)
186 (cons (hw-sem-name hw)
191 (lambda (elm) (car elm)))
193 "#define MAX_HW ((int) HW_MAX)\n\n"
197 ; Return declarations of variables tables used by HW.
199 (define (-gen-hw-decl hw)
201 (if (and (hw-indices hw)
202 ; ??? Commented out as opcode changes are needed
203 ) ; (not (obj-has-attr? (hw-indices hw) 'PRIVATE)))
204 (gen-decl (hw-indices hw))
206 (if (and (hw-values hw)
207 ; ??? Commented out as opcode changes are needed
208 ) ; (not (obj-has-attr? (hw-values hw) 'PRIVATE)))
209 (gen-decl (hw-values hw))
214 ; Return C code to declare the various hardware bits
215 ; that must be defined after including opcode/cgen.h.
217 (define (gen-hw-table-decls)
218 (logit 2 "Generating hardware table decls ...\n")
220 "/* Hardware decls. */\n\n"
221 (string-map -gen-hw-decl (current-hw-list))
223 "extern const CGEN_HW_ENTRY @arch@_cgen_hw_table[];\n"
227 ; Return definitions of variables tables used by HW.
228 ; Only do this for `PRIVATE' elements. Public ones are emitted elsewhere.
230 (define (-gen-hw-defn hw)
232 (if (and (hw-indices hw)
233 (obj-has-attr? (hw-indices hw) 'PRIVATE))
234 (gen-defn (hw-indices hw))
236 (if (and (hw-values hw)
237 (obj-has-attr? (hw-values hw) 'PRIVATE))
238 (gen-defn (hw-values hw))
243 ; Generate the tables for the various hardware bits (register names, etc.).
244 ; A table is generated for each element, and then another table is generated
245 ; which collects them all together.
246 ; Uses include looking up a particular register set so that a new reg
247 ; can be added to it [at runtime].
249 (define (gen-hw-table-defns)
250 (logit 2 "Generating hardware table ...\n")
251 (let* ((all-attrs (current-hw-attr-list))
252 (num-non-bools (attr-count-non-bools all-attrs)))
254 (string-list-map gen-defn (current-kw-list))
255 (string-list-map -gen-hw-defn (current-hw-list))
257 /* The hardware table. */
260 (gen-define-with-symcat "A(a) (1 << CGEN_HW_" "a)")
262 const CGEN_HW_ENTRY @arch@_cgen_hw_table[] =
270 "\"" (obj:str-name hw) "\", "
272 ; ??? No element currently requires both indices and
273 ; values specs so we only output the needed one.
274 (or (and (hw-indices hw)
275 (send (hw-indices hw) 'gen-table-entry))
277 (send (hw-values hw) 'gen-table-entry))
278 "CGEN_ASM_NONE, 0, ")
279 (gen-obj-attr-defn 'hw hw all-attrs
280 num-non-bools gen-A-attr-mask)
284 { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} }
293 ; Utilities of cgen-opc.h.
295 ; Return #define's of several constants.
296 ; FIXME: Some of these to be moved into table of structs, one per cpu family.
298 (define (-gen-hash-defines)
299 (logit 2 "Generating #define's ...\n")
301 "#define CGEN_ARCH @arch@\n\n"
302 "/* Given symbol S, return @arch@_cgen_<S>. */\n"
303 (gen-define-with-symcat "CGEN_SYM(s) @arch@" "_cgen_" "s")
304 "\n\n/* Selected cpu families. */\n"
305 ; FIXME: Move to sim's arch.h.
306 (string-map (lambda (cpu)
307 (gen-obj-sanitize cpu
308 (string-append "#define HAVE_CPU_"
309 (string-upcase (gen-sym cpu))
313 "#define CGEN_INSN_LSB0_P " (if (current-arch-insn-lsb0?) "1" "0")
315 "/* Minimum size of any insn (in bytes). */\n"
316 "#define CGEN_MIN_INSN_SIZE "
317 (number->string (bits->bytes
318 (apply min (map isa-min-insn-bitsize (current-isa-list)))))
320 "/* Maximum size of any insn (in bytes). */\n"
321 "#define CGEN_MAX_INSN_SIZE "
322 (number->string (bits->bytes
323 (apply max (map isa-max-insn-bitsize (current-isa-list)))))
325 ; This tells the assembler/disassembler whether or not it can use an int to
326 ; record insns, which is faster. Since this controls the typedef of the
327 ; insn buffer, only enable this if all isas support it.
328 "#define CGEN_INT_INSN_P "
329 (if (all-true? (map isa-integral-insn? (current-isa-list))) "1" "0")
332 "/* Maximum number of syntax elements in an instruction. */\n"
333 "#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS "
334 ; The +2 account for the leading "MNEM" and trailing 0.
335 (number->string (+ 2 (apply max (map (lambda (insn)
336 (length (syntax-break-out (insn-syntax insn))))
337 (current-insn-list)))))
340 "/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.\n"
341 " e.g. In \"b,a foo\" the \",a\" is an operand. If mnemonics have operands\n"
342 " we can't hash on everything up to the space. */\n"
344 "/*#define CGEN_MNEMONIC_OPERANDS*/\n"
345 "#define CGEN_MNEMONIC_OPERANDS\n")
347 ; "/* Maximum number of operands any insn or macro-insn has. */\n"
348 ; FIXME: Should compute.
349 ; "#define CGEN_MAX_INSN_OPERANDS 16\n"
351 "/* Maximum number of fields in an instruction. */\n"
352 "#define CGEN_ACTUAL_MAX_IFMT_OPERANDS "
353 (number->string (apply max (map (lambda (f) (length (ifmt-ifields f)))
354 (current-ifmt-list))))
361 ; Return C code to declare various operand bits.
363 (define (gen-operand-decls)
364 (logit 2 "Generating operand decls ...\n")
366 "/* Operand attribute indices. */\n\n"
367 (gen-attr-enum-decl "cgen_operand" (current-op-attr-list))
368 (gen-enum-decl 'cgen_operand_type "@arch@ operand types"
370 (nub (append (gen-obj-list-enums (current-op-list))
373 "/* Number of operands types. */\n"
374 "#define MAX_OPERANDS " (number->string (length (gen-obj-list-enums (current-op-list)))) "\n\n"
375 ; was: "#define MAX_OPERANDS ((int) @ARCH@_OPERAND_MAX)\n\n"
376 "/* Maximum number of operands referenced by any insn. */\n"
377 "#define MAX_OPERAND_INSTANCES "
378 (number->string (max-operand-instances))
383 ; Generate C code to define the operand table.
385 (define ifld-number-cache #f)
386 (define (ifld-number f)
387 (if (not ifld-number-cache)
388 (let* ((ls (find (lambda (f) (not (has-attr? f 'VIRTUAL)))
389 (non-derived-ifields (current-ifld-list))))
390 (numls (iota (length ls))))
391 (set! ifld-number-cache
392 (map (lambda (elt num) (cons (obj:name elt) num))
394 (number->string (cdr (assoc (obj:name f) ifld-number-cache))))
396 (define (gen-maybe-multi-ifld-of-op op)
397 (let* ((idx (op:index op))
398 (ty (hw-index:type idx))
399 (fld (hw-index:value idx)))
400 (gen-maybe-multi-ifld ty fld)))
402 (define (gen-maybe-multi-ifld ty fld)
403 (let* ((field-ref "0")
405 (if (equal? ty 'ifield)
406 (if (multi-ifield? fld)
408 (set! field-ref (string-append "&" (ifld-enum fld) "_MULTI_IFIELD[0]"))
409 (set! field-count (number->string (length (elm-get fld 'subfields)))))
411 (set! field-ref (string-append "&@arch@_cgen_ifld_table[" (ifld-enum fld) "]"))))
412 (string-append "{ " field-count ", { (const PTR) " field-ref " } }")))
414 (define (gen-multi-ifield-nodes)
415 (let ((multis (find multi-ifield? (current-ifld-list))))
419 '("\n\n/* multi ifield declarations */\n\n")
423 "const CGEN_MAYBE_MULTI_IFLD "
424 (ifld-enum ifld) "_MULTI_IFIELD [];\n"))
427 '("\n\n/* multi ifield definitions */\n\n")
431 "const CGEN_MAYBE_MULTI_IFLD "
432 (ifld-enum ifld) "_MULTI_IFIELD [] =\n{"
434 (map (lambda (x) (string-append "\n " (gen-maybe-multi-ifld 'ifield x) ","))
435 (elm-get ifld 'subfields)))
436 "\n { 0, { (const PTR) 0 } }\n};\n"))
439 (define (gen-operand-table)
440 (logit 2 "Generating operand table ...\n")
441 (let* ((all-attrs (current-op-attr-list))
442 (num-non-bools (attr-count-non-bools all-attrs)))
445 /* The operand table. */
448 (gen-define-with-symcat "A(a) (1 << CGEN_OPERAND_" "a)")
449 (gen-define-with-symcat "OPERAND(op) @ARCH@_OPERAND_" "op")
451 const CGEN_OPERAND @arch@_cgen_operand_table[] =
458 "/* " (obj:str-name op) ": " (obj:comment op) " */\n"
459 (if (or (derived-operand? op)
464 "\"" (obj:str-name op) "\", "
466 (hw-enum (op:hw-name op)) ", "
467 (number->string (op:start op)) ", "
468 (number->string (op:length op)) ",\n"
470 (gen-maybe-multi-ifld-of-op op) ", \n"
472 (gen-obj-attr-defn 'operand op all-attrs
473 num-non-bools gen-A-attr-mask)
478 { 0, 0, 0, 0, 0,\n { 0, { (const PTR) 0 } },\n { 0, { 0 } } }
488 ; Instruction table support.
490 ; Return C code to declare various insn bits.
492 (define (gen-insn-decls)
493 (logit 2 "Generating instruction decls ...\n")
495 "/* Insn attribute indices. */\n\n"
496 (gen-attr-enum-decl "cgen_insn" (current-insn-attr-list))
500 ; Generate an insn table entry for INSN.
501 ; ALL-ATTRS is a list of all instruction attributes.
502 ; NUM-NON-BOOLS is the number of non-boolean insn attributes.
504 (define (gen-insn-table-entry insn all-attrs num-non-bools)
508 "/* " (insn-syntax insn) " */\n"
511 (if (has-attr? insn 'ALIAS) "-1" (insn-enum insn)) ", "
512 "\"" (obj:str-name insn) "\", "
513 "\"" (insn-mnemonic insn) "\", "
514 ;(if (has-attr? insn 'ALIAS) "0" (number->string (insn-length insn))) ",\n"
515 (number->string (insn-length insn)) ",\n"
516 ; ??? There is currently a problem with embedded newlines, and this might
517 ; best be put in another file [the table is already pretty big].
518 ; Might also wish to output bytecodes instead.
520 ; (if (insn-semantics insn)
521 ; (string-append "\""
522 ; (with-output-to-string
523 ; ; ??? Should we do macro expansion here?
524 ; (lambda () (display (insn-semantics insn))))
528 ; ??? Might wish to output the raw format spec here instead
529 ; (either as plain text or bytecodes).
530 ; Values could be lazily computed and cached.
532 (gen-obj-attr-defn 'insn insn all-attrs num-non-bools gen-A-attr-mask)
536 ; Generate insn table.
538 (define (gen-insn-table)
539 (logit 2 "Generating instruction table ...\n")
540 (let* ((all-attrs (current-insn-attr-list))
541 (num-non-bools (attr-count-non-bools all-attrs)))
544 /* The instruction table. */
546 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
548 (gen-define-with-symcat "A(a) (1 << CGEN_INSN_" "a)")
550 static const CGEN_IBASE @arch@_cgen_insn_table[MAX_INSNS] =
552 /* Special null first entry.
553 A `num' value of zero is thus invalid.
554 Also, the special `invalid' insn resides here. */
555 { 0, 0, 0, 0, {0, {0}} },\n"
558 (string-write-map (lambda (insn)
559 (logit 3 "Generating insn table entry for " (obj:name insn) " ...\n")
560 (gen-insn-table-entry insn all-attrs num-non-bools))
561 (non-multi-insns (current-insn-list))))
574 ; Cpu table handling support.
576 ; ??? A lot of this can live in a machine independent file, but there's
577 ; currently no place to put this file (there's no libcgen). libopcodes is the
578 ; wrong place as some simulator ports use this but they don't use libopcodes.
580 ; Return C routines to open/close a cpu description table.
581 ; This is defined here and not in cgen-opc.in because it refers to
582 ; CGEN_{ASM,DIS}_HASH and insn_table/macro_insn_table which is defined
583 ; earlier in the file. ??? Things can certainly be rearranged though
584 ; and opcodes/cgen.sh modified to insert the generated part into the middle
585 ; of the file like is done for assembler/disassembler support.
587 (define (-gen-cpu-open)
590 static const CGEN_MACH * lookup_mach_via_bfd_name
591 PARAMS ((const CGEN_MACH *, const char *));
592 static void build_hw_table PARAMS ((CGEN_CPU_TABLE *));
593 static void build_ifield_table PARAMS ((CGEN_CPU_TABLE *));
594 static void build_operand_table PARAMS ((CGEN_CPU_TABLE *));
595 static void build_insn_table PARAMS ((CGEN_CPU_TABLE *));
596 static void @arch@_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *));
598 /* Subroutine of @arch@_cgen_cpu_open to look up a mach via its bfd name. */
600 static const CGEN_MACH *
601 lookup_mach_via_bfd_name (table, name)
602 const CGEN_MACH *table;
607 if (strcmp (name, table->bfd_name) == 0)
614 /* Subroutine of @arch@_cgen_cpu_open to build the hardware table. */
621 int machs = cd->machs;
622 const CGEN_HW_ENTRY *init = & @arch@_cgen_hw_table[0];
623 /* MAX_HW is only an upper bound on the number of selected entries.
624 However each entry is indexed by it's enum so there can be holes in
626 const CGEN_HW_ENTRY **selected =
627 (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
629 cd->hw_table.init_entries = init;
630 cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
631 memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
632 /* ??? For now we just use machs to determine which ones we want. */
633 for (i = 0; init[i].name != NULL; ++i)
634 if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
636 selected[init[i].type] = &init[i];
637 cd->hw_table.entries = selected;
638 cd->hw_table.num_entries = MAX_HW;
641 /* Subroutine of @arch@_cgen_cpu_open to build the hardware table. */
644 build_ifield_table (cd)
647 cd->ifld_table = & @arch@_cgen_ifld_table[0];
650 /* Subroutine of @arch@_cgen_cpu_open to build the hardware table. */
653 build_operand_table (cd)
657 int machs = cd->machs;
658 const CGEN_OPERAND *init = & @arch@_cgen_operand_table[0];
659 /* MAX_OPERANDS is only an upper bound on the number of selected entries.
660 However each entry is indexed by it's enum so there can be holes in
662 const CGEN_OPERAND **selected =
663 (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *));
665 cd->operand_table.init_entries = init;
666 cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
667 memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
668 /* ??? For now we just use mach to determine which ones we want. */
669 for (i = 0; init[i].name != NULL; ++i)
670 if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
672 selected[init[i].type] = &init[i];
673 cd->operand_table.entries = selected;
674 cd->operand_table.num_entries = MAX_OPERANDS;
677 /* Subroutine of @arch@_cgen_cpu_open to build the hardware table.
678 ??? This could leave out insns not supported by the specified mach/isa,
679 but that would cause errors like \"foo only supported by bar\" to become
680 \"unknown insn\", so for now we include all insns and require the app to
681 do the checking later.
682 ??? On the other hand, parsing of such insns may require their hardware or
683 operand elements to be in the table [which they mightn't be]. */
686 build_insn_table (cd)
690 const CGEN_IBASE *ib = & @arch@_cgen_insn_table[0];
691 CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
693 memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
694 for (i = 0; i < MAX_INSNS; ++i)
695 insns[i].base = &ib[i];
696 cd->insn_table.init_entries = insns;
697 cd->insn_table.entry_size = sizeof (CGEN_IBASE);
698 cd->insn_table.num_init_entries = MAX_INSNS;
701 /* Subroutine of @arch@_cgen_cpu_open to rebuild the tables. */
704 @arch@_cgen_rebuild_tables (cd)
708 unsigned int isas = cd->isas;
709 unsigned int machs = cd->machs;
711 cd->int_insn_p = CGEN_INT_INSN_P;
713 /* Data derived from the isa spec. */
714 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
715 cd->default_insn_bitsize = UNSET;
716 cd->base_insn_bitsize = UNSET;
717 cd->min_insn_bitsize = 65535; /* some ridiculously big number */
718 cd->max_insn_bitsize = 0;
719 for (i = 0; i < MAX_ISAS; ++i)
720 if (((1 << i) & isas) != 0)
722 const CGEN_ISA *isa = & @arch@_cgen_isa_table[i];
724 /* Default insn sizes of all selected isas must be
725 equal or we set the result to 0, meaning \"unknown\". */
726 if (cd->default_insn_bitsize == UNSET)
727 cd->default_insn_bitsize = isa->default_insn_bitsize;
728 else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
731 cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
733 /* Base insn sizes of all selected isas must be equal
734 or we set the result to 0, meaning \"unknown\". */
735 if (cd->base_insn_bitsize == UNSET)
736 cd->base_insn_bitsize = isa->base_insn_bitsize;
737 else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
740 cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
742 /* Set min,max insn sizes. */
743 if (isa->min_insn_bitsize < cd->min_insn_bitsize)
744 cd->min_insn_bitsize = isa->min_insn_bitsize;
745 if (isa->max_insn_bitsize > cd->max_insn_bitsize)
746 cd->max_insn_bitsize = isa->max_insn_bitsize;
749 /* Data derived from the mach spec. */
750 for (i = 0; i < MAX_MACHS; ++i)
751 if (((1 << i) & machs) != 0)
753 const CGEN_MACH *mach = & @arch@_cgen_mach_table[i];
755 if (mach->insn_chunk_bitsize != 0)
757 if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
759 fprintf (stderr, \"@arch@_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\\n\",
760 cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
764 cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
768 /* Determine which hw elements are used by MACH. */
771 /* Build the ifield table. */
772 build_ifield_table (cd);
774 /* Determine which operands are used by MACH/ISA. */
775 build_operand_table (cd);
777 /* Build the instruction table. */
778 build_insn_table (cd);
781 /* Initialize a cpu table and return a descriptor.
782 It's much like opening a file, and must be the first function called.
783 The arguments are a set of (type/value) pairs, terminated with
786 Currently supported values:
787 CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr
788 CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr
789 CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
790 CGEN_CPU_OPEN_ENDIAN: specify endian choice
791 CGEN_CPU_OPEN_END: terminates arguments
793 ??? Simultaneous multiple isas might not make sense, but it's not (yet)
796 ??? We only support ISO C stdargs here, not K&R.
797 Laziness, plus experiment to see if anything requires K&R - eventually
798 K&R will no longer be supported - e.g. GDB is currently trying this. */
801 @arch@_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
803 CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
805 unsigned int isas = 0; /* 0 = \"unspecified\" */
806 unsigned int machs = 0; /* 0 = \"unspecified\" */
807 enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
816 memset (cd, 0, sizeof (*cd));
818 va_start (ap, arg_type);
819 while (arg_type != CGEN_CPU_OPEN_END)
823 case CGEN_CPU_OPEN_ISAS :
824 isas = va_arg (ap, unsigned int);
826 case CGEN_CPU_OPEN_MACHS :
827 machs = va_arg (ap, unsigned int);
829 case CGEN_CPU_OPEN_BFDMACH :
831 const char *name = va_arg (ap, const char *);
832 const CGEN_MACH *mach =
833 lookup_mach_via_bfd_name (@arch@_cgen_mach_table, name);
835 machs |= 1 << mach->num;
838 case CGEN_CPU_OPEN_ENDIAN :
839 endian = va_arg (ap, enum cgen_endian);
842 fprintf (stderr, \"@arch@_cgen_cpu_open: unsupported argument `%d'\\n\",
844 abort (); /* ??? return NULL? */
846 arg_type = va_arg (ap, enum cgen_cpu_open_arg);
850 /* mach unspecified means \"all\" */
852 machs = (1 << MAX_MACHS) - 1;
853 /* base mach is always selected */
855 /* isa unspecified means \"all\" */
857 isas = (1 << MAX_ISAS) - 1;
858 if (endian == CGEN_ENDIAN_UNKNOWN)
860 /* ??? If target has only one, could have a default. */
861 fprintf (stderr, \"@arch@_cgen_cpu_open: no endianness specified\\n\");
868 /* FIXME: for the sparc case we can determine insn-endianness statically.
869 The worry here is where both data and insn endian can be independently
870 chosen, in which case this function will need another argument.
871 Actually, will want to allow for more arguments in the future anyway. */
872 cd->insn_endian = endian;
874 /* Table (re)builder. */
875 cd->rebuild_tables = @arch@_cgen_rebuild_tables;
876 @arch@_cgen_rebuild_tables (cd);
878 /* Default to not allowing signed overflow. */
879 cd->signed_overflow_ok_p = 0;
881 return (CGEN_CPU_DESC) cd;
884 /* Cover fn to @arch@_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
885 MACH_NAME is the bfd name of the mach. */
888 @arch@_cgen_cpu_open_1 (mach_name, endian)
889 const char *mach_name;
890 enum cgen_endian endian;
892 return @arch@_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
893 CGEN_CPU_OPEN_ENDIAN, endian,
897 /* Close a cpu table.
898 ??? This can live in a machine independent file, but there's currently
899 no place to put this file (there's no libcgen). libopcodes is the wrong
900 place as some simulator ports use this but they don't use libopcodes. */
903 @arch@_cgen_cpu_close (cd)
907 const CGEN_INSN *insns;
909 if (cd->macro_insn_table.init_entries)
911 insns = cd->macro_insn_table.init_entries;
912 for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
914 if (CGEN_INSN_RX ((insns)))
915 regfree (CGEN_INSN_RX (insns));
919 if (cd->insn_table.init_entries)
921 insns = cd->insn_table.init_entries;
922 for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
924 if (CGEN_INSN_RX (insns))
925 regfree (CGEN_INSN_RX (insns));
931 if (cd->macro_insn_table.init_entries)
932 free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
934 if (cd->insn_table.init_entries)
935 free ((CGEN_INSN *) cd->insn_table.init_entries);
937 if (cd->hw_table.entries)
938 free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
940 if (cd->operand_table.entries)
941 free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
949 ; General initialization C code
950 ; Code is appended during processing.
952 (define -cputab-init-code "")
953 (define (cputab-add-init! code)
954 (set! -cputab-init-code (string-append -cputab-init-code code))
957 ; Return the C code to define the various initialization functions.
958 ; This does not include assembler/disassembler specific stuff.
959 ; Generally, this function doesn't do anything.
960 ; It exists to allow a global-static-constructor kind of thing should
961 ; one ever be necessary.
963 (define (gen-init-fns)
964 (logit 2 "Generating init fns ...\n")
967 /* Initialize anything needed to be done once, before any cpu_open call. */
968 static void init_tables PARAMS ((void));
978 ; Top level C code generators
980 ; FIXME: Create enum objects for all the enums we explicitly declare here.
981 ; Then they'd be usable and we wouldn't have to special case them here.
983 (define (cgen-desc.h)
984 (logit 1 "Generating " (current-arch-name) " desc.h ...\n")
986 (gen-c-copyright "CPU data header for @arch@."
987 CURRENT-COPYRIGHT CURRENT-PACKAGE)
994 ; This is defined in arch.h. It's not defined here as there is yet to
995 ; be a need for it in the assembler/disassembler.
996 ;(gen-enum-decl 'model_type "model types"
998 ; (append (map list (map obj:name (current-model-list))) '((max))))
999 ;"#define MAX_MODELS ((int) MODEL_MAX)\n\n"
1001 (string-map gen-decl (current-enum-list))
1002 "/* Attributes. */\n\n"
1003 (string-map gen-decl (current-attr-list))
1004 "/* Number of architecture variants. */\n"
1005 ; If there is only 1 isa, leave out special handling. */
1006 (if (= (length (current-isa-list)) 1)
1007 "#define MAX_ISAS 1\n"
1008 "#define MAX_ISAS ((int) ISA_MAX)\n")
1009 "#define MAX_MACHS ((int) MACH_MAX)\n\n"
1014 "/* cgen.h uses things we just defined. */\n"
1015 "#include \"opcode/cgen.h\"\n\n"
1016 "extern const struct cgen_ifld @arch@_cgen_ifld_table[];\n\n"
1017 -gen-attr-table-decls
1018 -gen-mach-table-decls
1021 (lambda () (gen-extra-cpu.h (opc-file-path) (current-arch-name)))
1024 #endif /* @ARCH@_CPU_H */
1029 ; This file contains the "top level" definitions of the cpu.
1030 ; This includes various elements of the description file, expressed in C.
1032 ; ??? A lot of this file can go in a machine-independent file! However,
1033 ; some simulators don't use the cgen opcodes support so there is currently
1034 ; no place to put this file. To be revisited when we do have such a place.
1036 (define (cgen-desc.c)
1037 (logit 1 "Generating " (current-arch-name) " desc.c ...\n")
1039 (gen-c-copyright "CPU data for @arch@."
1040 CURRENT-COPYRIGHT CURRENT-PACKAGE)
1042 #include \"sysdep.h\"
1045 #include \"ansidecl.h\"
1047 #include \"symcat.h\"
1048 #include \"@arch@-desc.h\"
1049 #include \"@arch@-opc.h\"
1050 #include \"opintl.h\"
1051 #include \"libiberty.h\"
1052 #include \"xregex.h\"
1054 (lambda () (gen-extra-cpu.c (opc-file-path) (current-arch-name)))
1055 gen-attr-table-defns
1056 -gen-isa-table-defns
1057 -gen-mach-table-defns
1060 gen-multi-ifield-nodes