1 ; Generate .c/.h versions of main elements of cpu description file.
2 ; Copyright (C) 2000, 2001, 2002, 2003, 2005, 2009 Red Hat, Inc.
3 ; This file is part of CGEN.
7 (define (/gen-isa-table-defns)
8 (logit 2 "Generating isa table defns ...\n")
12 /* Instruction set variants. */
14 static const CGEN_ISA @arch@_cgen_isa_table[] = {
16 (string-list-map (lambda (isa)
20 "\"" (obj:str-name isa) "\", "
22 (isa-default-insn-bitsize isa))
25 (isa-base-insn-bitsize isa))
28 (isa-min-insn-bitsize isa))
31 (isa-max-insn-bitsize isa))
43 ; Return C code to describe the various cpu variants.
44 ; Currently this is quite simple, the various cpu names and their mach numbers
45 ; are recorded in a "keyword" table.
46 ; ??? No longer used as there is the mach attribute.
48 ;(set! mach-table (make <keyword> 'mach "machine list"
49 ; (make <attr-list> "" nil) ; FIXME: sanitization?
50 ; (map (lambda (elm) (list (obj:name elm) (mach-number elm)))
51 ; (current-mach-list))))
53 (define (/gen-mach-table-decls)
54 (logit 2 "Generating machine table decls ...\n")
55 "" ; (gen-decl mach-table)
58 (define (/gen-mach-table-defns)
59 (logit 2 "Generating machine table defns ...\n")
63 /* Machine variants. */
65 static const CGEN_MACH @arch@_cgen_mach_table[] = {
67 (string-list-map (lambda (mach)
71 "\"" (obj:str-name mach) "\", "
72 "\"" (mach-bfd-name mach) "\", "
74 (number->string (cpu-insn-chunk-bitsize (mach-cpu mach)))
84 ; Attribute support code.
86 ; Return C code to describe the various attributes.
88 (define (/gen-attr-table-decls)
89 (logit 2 "Generating attribute table decls ...\n")
92 "extern const CGEN_ATTR_TABLE @arch@_cgen_hardware_attr_table[];\n"
93 "extern const CGEN_ATTR_TABLE @arch@_cgen_ifield_attr_table[];\n"
94 "extern const CGEN_ATTR_TABLE @arch@_cgen_operand_attr_table[];\n"
95 "extern const CGEN_ATTR_TABLE @arch@_cgen_insn_attr_table[];\n"
100 ; Alternative GEN-MASK argument to gen-bool-attrs.
101 ; This uses the `A' macro to abbreviate the attribute definition.
103 (define (gen-A-attr-mask prefix name)
104 (string-append "A(" (string-upcase (gen-c-symbol name)) ")")
107 ; Instruction fields support code.
109 ; Return C code to declare various ifield bits.
111 (define (gen-ifld-decls)
112 (logit 2 "Generating instruction field decls ...\n")
114 "/* Ifield support. */\n\n"
115 "/* Ifield attribute indices. */\n\n"
116 (gen-attr-enum-decl "cgen_ifld" (current-ifld-attr-list))
117 (gen-attr-accessors "cgen_ifld" (current-ifld-attr-list))
118 (gen-enum-decl 'ifield_type "@arch@ ifield types"
120 (append (gen-obj-list-enums (non-derived-ifields (current-ifld-list)))
122 "#define MAX_IFLD ((int) @ARCH@_F_MAX)\n\n"
126 ; Return C code to define the instruction field table,
127 ; and any other ifield related definitions.
129 (define (gen-ifld-defns)
130 (logit 2 "Generating ifield table ...\n")
131 (let* ((ifld-list (current-ifld-list))
132 (all-attrs (current-ifld-attr-list))
133 (num-non-bools (attr-count-non-bools all-attrs)))
136 /* The instruction field table. */
139 (gen-define-with-symcat "A(a) (1 << CGEN_IFLD_" "a)")
141 const CGEN_IFLD @arch@_cgen_ifld_table[] =
146 (gen-obj-sanitize ifld
149 (ifld-enum ifld) ", "
150 "\"" (obj:str-name ifld) "\", "
152 (or (has-attr? ifld 'VIRTUAL)
153 (derived-ifield? ifld))
156 (number->string (ifld-word-offset ifld)) ", "
157 (number->string (ifld-word-length ifld)) ", "
158 (number->string (ifld-start ifld)) ", "
159 (number->string (ifld-length ifld)) ", "))
160 (gen-obj-attr-defn 'ifld ifld all-attrs
161 num-non-bools gen-A-attr-mask)
165 { 0, 0, 0, 0, 0, 0, " (gen-obj-attr-end-defn all-attrs num-non-bools) " }
176 ; Return C code to declare the various hardware bits
177 ; that can be (or must be) defined before including opcode/cgen.h.
179 (define (gen-hw-decls)
180 (logit 2 "Generating hardware decls ...\n")
182 "/* Hardware attribute indices. */\n\n"
183 (gen-attr-enum-decl "cgen_hw" (current-hw-attr-list))
184 (gen-attr-accessors "cgen_hw" (current-hw-attr-list))
185 (gen-enum-decl 'cgen_hw_type "@arch@ hardware types"
186 "HW_" ; FIXME: @ARCH@_
187 (append (nub (map (lambda (hw)
188 (cons (hw-sem-name hw)
193 (lambda (elm) (car elm)))
195 "#define MAX_HW ((int) HW_MAX)\n\n"
199 ; Return declarations of variables tables used by HW.
201 (define (/gen-hw-decl hw)
204 (gen-decl (hw-indices hw))
207 (gen-decl (hw-values hw))
212 ; Return C code to declare the various hardware bits
213 ; that must be defined after including opcode/cgen.h.
215 (define (gen-hw-table-decls)
216 (logit 2 "Generating hardware table decls ...\n")
218 "/* Hardware decls. */\n\n"
219 (string-map /gen-hw-decl (current-hw-list))
221 "extern const CGEN_HW_ENTRY @arch@_cgen_hw_table[];\n"
225 ; Return definitions of variables tables used by HW.
226 ; Only do this for `PRIVATE' elements. Public ones are emitted elsewhere.
228 (define (/gen-hw-defn hw)
230 (if (and (hw-indices hw)
231 (obj-has-attr? (hw-indices hw) 'PRIVATE))
232 (gen-defn (hw-indices hw))
234 (if (and (hw-values hw)
235 (obj-has-attr? (hw-values hw) 'PRIVATE))
236 (gen-defn (hw-values hw))
241 ; Generate the tables for the various hardware bits (register names, etc.).
242 ; A table is generated for each element, and then another table is generated
243 ; which collects them all together.
244 ; Uses include looking up a particular register set so that a new reg
245 ; can be added to it [at runtime].
247 (define (gen-hw-table-defns)
248 (logit 2 "Generating hardware table ...\n")
249 (let* ((all-attrs (current-hw-attr-list))
250 (num-non-bools (attr-count-non-bools all-attrs)))
252 (string-list-map gen-defn (current-kw-list))
253 (string-list-map /gen-hw-defn (current-hw-list))
255 /* The hardware table. */
258 (gen-define-with-symcat "A(a) (1 << CGEN_HW_" "a)")
260 const CGEN_HW_ENTRY @arch@_cgen_hw_table[] =
268 "\"" (obj:str-name hw) "\", "
270 ; ??? No element currently requires both indices and
271 ; values specs so we only output the needed one.
272 (or (and (hw-indices hw)
273 (send (hw-indices hw) 'gen-table-entry))
275 (send (hw-values hw) 'gen-table-entry))
276 "CGEN_ASM_NONE, 0, ")
277 (gen-obj-attr-defn 'hw hw all-attrs
278 num-non-bools gen-A-attr-mask)
282 { 0, 0, CGEN_ASM_NONE, 0, " (gen-obj-attr-end-defn all-attrs num-non-bools) " }
291 ; Utilities of cgen-opc.h.
293 ; Return #define's of several constants.
294 ; FIXME: Some of these to be moved into table of structs, one per cpu family.
296 (define (/gen-hash-defines)
297 (logit 2 "Generating #define's ...\n")
299 "#include \"opcode/cgen-bitset.h\"\n"
301 "#define CGEN_ARCH @arch@\n\n"
302 "/* Given symbol S, return @arch@_cgen_<S>. */\n"
303 (gen-define-with-symcat "CGEN_SYM(s) @arch@" "_cgen_" "s")
304 "\n\n/* Selected cpu families. */\n"
305 ; FIXME: Move to sim's arch.h.
306 (string-map (lambda (cpu)
307 (gen-obj-sanitize cpu
308 (string-append "#define HAVE_CPU_"
309 (string-upcase (gen-sym cpu))
313 "#define CGEN_INSN_LSB0_P " (if (current-arch-insn-lsb0?) "1" "0")
315 "/* Minimum size of any insn (in bytes). */\n"
316 "#define CGEN_MIN_INSN_SIZE "
317 (number->string (bits->bytes
318 (apply min (map isa-min-insn-bitsize (current-isa-list)))))
320 "/* Maximum size of any insn (in bytes). */\n"
321 "#define CGEN_MAX_INSN_SIZE "
322 (number->string (bits->bytes
323 (apply max (map isa-max-insn-bitsize (current-isa-list)))))
325 ; This tells the assembler/disassembler whether or not it can use an int to
326 ; record insns, which is faster. Since this controls the typedef of the
327 ; insn buffer, only enable this if all isas support it.
328 "#define CGEN_INT_INSN_P "
329 (if (all-true? (map isa-integral-insn? (current-isa-list))) "1" "0")
332 "/* Maximum number of syntax elements in an instruction. */\n"
333 "#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS "
334 ; The +2 account for the leading "MNEM" and trailing 0.
335 (number->string (+ 2 (apply max (map (lambda (insn)
336 (length (syntax-break-out (insn-syntax insn))))
337 (current-insn-list)))))
340 "/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.\n"
341 " e.g. In \"b,a foo\" the \",a\" is an operand. If mnemonics have operands\n"
342 " we can't hash on everything up to the space. */\n"
344 "/*#define CGEN_MNEMONIC_OPERANDS*/\n"
345 "#define CGEN_MNEMONIC_OPERANDS\n")
347 ; "/* Maximum number of operands any insn or macro-insn has. */\n"
348 ; FIXME: Should compute.
349 ; "#define CGEN_MAX_INSN_OPERANDS 16\n"
351 "/* Maximum number of fields in an instruction. */\n"
352 "#define CGEN_ACTUAL_MAX_IFMT_OPERANDS "
353 (number->string (apply max (map (lambda (f) (length (ifmt-ifields f)))
354 (current-ifmt-list))))
361 ; Return C code to declare various operand bits.
363 (define (gen-operand-decls)
364 (logit 2 "Generating operand decls ...\n")
366 "/* Operand attribute indices. */\n\n"
367 (gen-attr-enum-decl "cgen_operand" (current-op-attr-list))
368 (gen-attr-accessors "cgen_operand" (current-op-attr-list))
369 (gen-enum-decl 'cgen_operand_type "@arch@ operand types"
371 (nub (append (gen-obj-list-enums (current-op-list))
374 "/* Number of operands types. */\n"
375 "#define MAX_OPERANDS " (number->string (length (gen-obj-list-enums (current-op-list)))) "\n\n"
376 ; was: "#define MAX_OPERANDS ((int) @ARCH@_OPERAND_MAX)\n\n"
377 "/* Maximum number of operands referenced by any insn. */\n"
378 "#define MAX_OPERAND_INSTANCES "
379 (number->string (max-operand-instances))
384 ; Generate C code to define the operand table.
386 (define ifld-number-cache #f)
387 (define (ifld-number f)
388 (if (not ifld-number-cache)
389 (let* ((ls (find (lambda (f) (not (has-attr? f 'VIRTUAL)))
390 (non-derived-ifields (current-ifld-list))))
391 (numls (iota (length ls))))
392 (set! ifld-number-cache
393 (map (lambda (elt num) (cons (obj:name elt) num))
395 (number->string (cdr (assoc (obj:name f) ifld-number-cache))))
397 (define (gen-maybe-multi-ifld-of-op op)
398 (let* ((idx (op:index op))
399 (ty (hw-index:type idx))
400 (fld (hw-index:value idx)))
401 (gen-maybe-multi-ifld ty fld)))
403 (define (gen-maybe-multi-ifld ty fld)
404 (let* ((field-ref "0")
406 (if (equal? ty 'ifield)
407 (if (multi-ifield? fld)
409 (set! field-ref (string-append "&" (ifld-enum fld) "_MULTI_IFIELD[0]"))
410 (set! field-count (number->string (length (elm-get fld 'subfields)))))
412 (set! field-ref (string-append "&@arch@_cgen_ifld_table[" (ifld-enum fld) "]"))))
413 (string-append "{ " field-count ", { (const PTR) " field-ref " } }")))
415 (define (gen-multi-ifield-nodes)
416 (let ((multis (find multi-ifield? (current-ifld-list))))
420 '("\n\n/* multi ifield declarations */\n\n")
424 "const CGEN_MAYBE_MULTI_IFLD "
425 (ifld-enum ifld) "_MULTI_IFIELD [];\n"))
428 '("\n\n/* multi ifield definitions */\n\n")
432 "const CGEN_MAYBE_MULTI_IFLD "
433 (ifld-enum ifld) "_MULTI_IFIELD [] =\n{"
435 (map (lambda (x) (string-append "\n " (gen-maybe-multi-ifld 'ifield x) ","))
436 (elm-get ifld 'subfields)))
437 "\n { 0, { (const PTR) 0 } }\n};\n"))
440 (define (gen-operand-table)
441 (logit 2 "Generating operand table ...\n")
442 (let* ((all-attrs (current-op-attr-list))
443 (num-non-bools (attr-count-non-bools all-attrs)))
446 /* The operand table. */
449 (gen-define-with-symcat "A(a) (1 << CGEN_OPERAND_" "a)")
450 (gen-define-with-symcat "OPERAND(op) @ARCH@_OPERAND_" "op")
452 const CGEN_OPERAND @arch@_cgen_operand_table[] =
459 "/* " (obj:str-name op) ": " (obj:comment op) " */\n"
460 (if (or (derived-operand? op)
465 "\"" (obj:str-name op) "\", "
467 (hw-enum (op:hw-name op)) ", "
468 (number->string (op:start op)) ", "
469 (number->string (op:length op)) ",\n"
471 (gen-maybe-multi-ifld-of-op op) ", \n"
473 (gen-obj-attr-defn 'operand op all-attrs
474 num-non-bools gen-A-attr-mask)
479 { 0, 0, 0, 0, 0,\n { 0, { (const PTR) 0 } },\n " (gen-obj-attr-end-defn all-attrs num-non-bools) " }
489 ; Instruction table support.
491 ; Return C code to declare various insn bits.
493 (define (gen-insn-decls)
494 (logit 2 "Generating instruction decls ...\n")
496 "/* Insn attribute indices. */\n\n"
497 (gen-attr-enum-decl "cgen_insn" (current-insn-attr-list))
498 (gen-attr-accessors "cgen_insn" (current-insn-attr-list))
502 ; Generate an insn table entry for INSN.
503 ; ALL-ATTRS is a list of all instruction attributes.
504 ; NUM-NON-BOOLS is the number of non-boolean insn attributes.
506 (define (gen-insn-table-entry insn all-attrs num-non-bools)
510 "/* " (insn-syntax insn) " */\n"
513 (if (has-attr? insn 'ALIAS) "-1" (insn-enum insn)) ", "
514 "\"" (obj:str-name insn) "\", "
515 "\"" (insn-mnemonic insn) "\", "
516 ;(if (has-attr? insn 'ALIAS) "0" (number->string (insn-length insn))) ",\n"
517 (number->string (insn-length insn)) ",\n"
518 ; ??? There is currently a problem with embedded newlines, and this might
519 ; best be put in another file [the table is already pretty big].
520 ; Might also wish to output bytecodes instead.
522 ; (if (insn-semantics insn)
523 ; (string-append "\""
524 ; (with-output-to-string
525 ; ; ??? Should we do macro expansion here?
526 ; (lambda () (display (insn-semantics insn))))
530 ; ??? Might wish to output the raw format spec here instead
531 ; (either as plain text or bytecodes).
532 ; Values could be lazily computed and cached.
534 (gen-obj-attr-defn 'insn insn all-attrs num-non-bools gen-A-attr-mask)
538 ; Generate insn table.
540 (define (gen-insn-table)
541 (logit 2 "Generating instruction table ...\n")
542 (let* ((all-attrs (current-insn-attr-list))
543 (num-non-bools (attr-count-non-bools all-attrs)))
546 /* The instruction table. */
548 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
550 (gen-define-with-symcat "A(a) (1 << CGEN_INSN_" "a)")
552 static const CGEN_IBASE @arch@_cgen_insn_table[MAX_INSNS] =
554 /* Special null first entry.
555 A `num' value of zero is thus invalid.
556 Also, the special `invalid' insn resides here. */
557 { 0, 0, 0, 0, " (gen-obj-attr-end-defn all-attrs num-non-bools) " },\n"
560 (string-write-map (lambda (insn)
561 (logit 3 "Generating insn table entry for " (obj:name insn) " ...\n")
562 (gen-insn-table-entry insn all-attrs num-non-bools))
563 (non-multi-insns (current-insn-list))))
576 ; Cpu table handling support.
578 ; ??? A lot of this can live in a machine independent file, but there's
579 ; currently no place to put this file (there's no libcgen). libopcodes is the
580 ; wrong place as some simulator ports use this but they don't use libopcodes.
582 ; Return C routines to open/close a cpu description table.
583 ; This is defined here and not in cgen-opc.in because it refers to
584 ; CGEN_{ASM,DIS}_HASH and insn_table/macro_insn_table which is defined
585 ; earlier in the file. ??? Things can certainly be rearranged though
586 ; and opcodes/cgen.sh modified to insert the generated part into the middle
587 ; of the file like is done for assembler/disassembler support.
589 (define (/gen-cpu-open)
592 static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
593 static void build_hw_table (CGEN_CPU_TABLE *);
594 static void build_ifield_table (CGEN_CPU_TABLE *);
595 static void build_operand_table (CGEN_CPU_TABLE *);
596 static void build_insn_table (CGEN_CPU_TABLE *);
597 static void @arch@_cgen_rebuild_tables (CGEN_CPU_TABLE *);
599 /* Subroutine of @arch@_cgen_cpu_open to look up a mach via its bfd name. */
601 static const CGEN_MACH *
602 lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
606 if (strcmp (name, table->bfd_name) == 0)
613 /* Subroutine of @arch@_cgen_cpu_open to build the hardware table. */
616 build_hw_table (CGEN_CPU_TABLE *cd)
619 int machs = cd->machs;
620 const CGEN_HW_ENTRY *init = & @arch@_cgen_hw_table[0];
621 /* MAX_HW is only an upper bound on the number of selected entries.
622 However each entry is indexed by it's enum so there can be holes in
624 const CGEN_HW_ENTRY **selected =
625 (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
627 cd->hw_table.init_entries = init;
628 cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
629 memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
630 /* ??? For now we just use machs to determine which ones we want. */
631 for (i = 0; init[i].name != NULL; ++i)
632 if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
634 selected[init[i].type] = &init[i];
635 cd->hw_table.entries = selected;
636 cd->hw_table.num_entries = MAX_HW;
639 /* Subroutine of @arch@_cgen_cpu_open to build the hardware table. */
642 build_ifield_table (CGEN_CPU_TABLE *cd)
644 cd->ifld_table = & @arch@_cgen_ifld_table[0];
647 /* Subroutine of @arch@_cgen_cpu_open to build the hardware table. */
650 build_operand_table (CGEN_CPU_TABLE *cd)
653 int machs = cd->machs;
654 const CGEN_OPERAND *init = & @arch@_cgen_operand_table[0];
655 /* MAX_OPERANDS is only an upper bound on the number of selected entries.
656 However each entry is indexed by it's enum so there can be holes in
658 const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
660 cd->operand_table.init_entries = init;
661 cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
662 memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
663 /* ??? For now we just use mach to determine which ones we want. */
664 for (i = 0; init[i].name != NULL; ++i)
665 if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
667 selected[init[i].type] = &init[i];
668 cd->operand_table.entries = selected;
669 cd->operand_table.num_entries = MAX_OPERANDS;
672 /* Subroutine of @arch@_cgen_cpu_open to build the hardware table.
673 ??? This could leave out insns not supported by the specified mach/isa,
674 but that would cause errors like \"foo only supported by bar\" to become
675 \"unknown insn\", so for now we include all insns and require the app to
676 do the checking later.
677 ??? On the other hand, parsing of such insns may require their hardware or
678 operand elements to be in the table [which they mightn't be]. */
681 build_insn_table (CGEN_CPU_TABLE *cd)
684 const CGEN_IBASE *ib = & @arch@_cgen_insn_table[0];
685 CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
687 memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
688 for (i = 0; i < MAX_INSNS; ++i)
689 insns[i].base = &ib[i];
690 cd->insn_table.init_entries = insns;
691 cd->insn_table.entry_size = sizeof (CGEN_IBASE);
692 cd->insn_table.num_init_entries = MAX_INSNS;
695 /* Subroutine of @arch@_cgen_cpu_open to rebuild the tables. */
698 @arch@_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
701 CGEN_BITSET *isas = cd->isas;
702 unsigned int machs = cd->machs;
704 cd->int_insn_p = CGEN_INT_INSN_P;
706 /* Data derived from the isa spec. */
707 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
708 cd->default_insn_bitsize = UNSET;
709 cd->base_insn_bitsize = UNSET;
710 cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */
711 cd->max_insn_bitsize = 0;
712 for (i = 0; i < MAX_ISAS; ++i)
713 if (cgen_bitset_contains (isas, i))
715 const CGEN_ISA *isa = & @arch@_cgen_isa_table[i];
717 /* Default insn sizes of all selected isas must be
718 equal or we set the result to 0, meaning \"unknown\". */
719 if (cd->default_insn_bitsize == UNSET)
720 cd->default_insn_bitsize = isa->default_insn_bitsize;
721 else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
724 cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
726 /* Base insn sizes of all selected isas must be equal
727 or we set the result to 0, meaning \"unknown\". */
728 if (cd->base_insn_bitsize == UNSET)
729 cd->base_insn_bitsize = isa->base_insn_bitsize;
730 else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
733 cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
735 /* Set min,max insn sizes. */
736 if (isa->min_insn_bitsize < cd->min_insn_bitsize)
737 cd->min_insn_bitsize = isa->min_insn_bitsize;
738 if (isa->max_insn_bitsize > cd->max_insn_bitsize)
739 cd->max_insn_bitsize = isa->max_insn_bitsize;
742 /* Data derived from the mach spec. */
743 for (i = 0; i < MAX_MACHS; ++i)
744 if (((1 << i) & machs) != 0)
746 const CGEN_MACH *mach = & @arch@_cgen_mach_table[i];
748 if (mach->insn_chunk_bitsize != 0)
750 if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
752 fprintf (stderr, \"@arch@_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\\n\",
753 cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
757 cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
761 /* Determine which hw elements are used by MACH. */
764 /* Build the ifield table. */
765 build_ifield_table (cd);
767 /* Determine which operands are used by MACH/ISA. */
768 build_operand_table (cd);
770 /* Build the instruction table. */
771 build_insn_table (cd);
774 /* Initialize a cpu table and return a descriptor.
775 It's much like opening a file, and must be the first function called.
776 The arguments are a set of (type/value) pairs, terminated with
779 Currently supported values:
780 CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr
781 CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr
782 CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
783 CGEN_CPU_OPEN_ENDIAN: specify endian choice
784 CGEN_CPU_OPEN_END: terminates arguments
786 ??? Simultaneous multiple isas might not make sense, but it's not (yet)
789 ??? We only support ISO C stdargs here, not K&R.
790 Laziness, plus experiment to see if anything requires K&R - eventually
791 K&R will no longer be supported - e.g. GDB is currently trying this. */
794 @arch@_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
796 CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
798 CGEN_BITSET *isas = 0; /* 0 = \"unspecified\" */
799 unsigned int machs = 0; /* 0 = \"unspecified\" */
800 enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
809 memset (cd, 0, sizeof (*cd));
811 va_start (ap, arg_type);
812 while (arg_type != CGEN_CPU_OPEN_END)
816 case CGEN_CPU_OPEN_ISAS :
817 isas = va_arg (ap, CGEN_BITSET *);
819 case CGEN_CPU_OPEN_MACHS :
820 machs = va_arg (ap, unsigned int);
822 case CGEN_CPU_OPEN_BFDMACH :
824 const char *name = va_arg (ap, const char *);
825 const CGEN_MACH *mach =
826 lookup_mach_via_bfd_name (@arch@_cgen_mach_table, name);
828 machs |= 1 << mach->num;
831 case CGEN_CPU_OPEN_ENDIAN :
832 endian = va_arg (ap, enum cgen_endian);
835 fprintf (stderr, \"@arch@_cgen_cpu_open: unsupported argument `%d'\\n\",
837 abort (); /* ??? return NULL? */
839 arg_type = va_arg (ap, enum cgen_cpu_open_arg);
843 /* Mach unspecified means \"all\". */
845 machs = (1 << MAX_MACHS) - 1;
846 /* Base mach is always selected. */
848 if (endian == CGEN_ENDIAN_UNKNOWN)
850 /* ??? If target has only one, could have a default. */
851 fprintf (stderr, \"@arch@_cgen_cpu_open: no endianness specified\\n\");
855 cd->isas = cgen_bitset_copy (isas);
858 /* FIXME: for the sparc case we can determine insn-endianness statically.
859 The worry here is where both data and insn endian can be independently
860 chosen, in which case this function will need another argument.
861 Actually, will want to allow for more arguments in the future anyway. */
862 cd->insn_endian = endian;
864 /* Table (re)builder. */
865 cd->rebuild_tables = @arch@_cgen_rebuild_tables;
866 @arch@_cgen_rebuild_tables (cd);
868 /* Default to not allowing signed overflow. */
869 cd->signed_overflow_ok_p = 0;
871 return (CGEN_CPU_DESC) cd;
874 /* Cover fn to @arch@_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
875 MACH_NAME is the bfd name of the mach. */
878 @arch@_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
880 return @arch@_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
881 CGEN_CPU_OPEN_ENDIAN, endian,
885 /* Close a cpu table.
886 ??? This can live in a machine independent file, but there's currently
887 no place to put this file (there's no libcgen). libopcodes is the wrong
888 place as some simulator ports use this but they don't use libopcodes. */
891 @arch@_cgen_cpu_close (CGEN_CPU_DESC cd)
894 const CGEN_INSN *insns;
896 if (cd->macro_insn_table.init_entries)
898 insns = cd->macro_insn_table.init_entries;
899 for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
900 if (CGEN_INSN_RX ((insns)))
901 regfree (CGEN_INSN_RX (insns));
904 if (cd->insn_table.init_entries)
906 insns = cd->insn_table.init_entries;
907 for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
908 if (CGEN_INSN_RX (insns))
909 regfree (CGEN_INSN_RX (insns));
912 if (cd->macro_insn_table.init_entries)
913 free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
915 if (cd->insn_table.init_entries)
916 free ((CGEN_INSN *) cd->insn_table.init_entries);
918 if (cd->hw_table.entries)
919 free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
921 if (cd->operand_table.entries)
922 free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
930 ; General initialization C code
931 ; Code is appended during processing.
933 (define /cputab-init-code "")
934 (define (cputab-add-init! code)
935 (set! /cputab-init-code (string-append /cputab-init-code code))
938 ; Return the C code to define the various initialization functions.
939 ; This does not include assembler/disassembler specific stuff.
940 ; Generally, this function doesn't do anything.
941 ; It exists to allow a global-static-constructor kind of thing should
942 ; one ever be necessary.
944 (define (gen-init-fns)
945 (logit 2 "Generating init fns ...\n")
948 /* Initialize anything needed to be done once, before any cpu_open call. */
958 ; Top level C code generators
960 ; FIXME: Create enum objects for all the enums we explicitly declare here.
961 ; Then they'd be usable and we wouldn't have to special case them here.
963 (define (cgen-desc.h)
964 (logit 1 "Generating " (current-arch-name) "-desc.h ...\n")
966 (gen-c-copyright "CPU data header for @arch@."
967 CURRENT-COPYRIGHT CURRENT-PACKAGE)
974 ; This is defined in arch.h. It's not defined here as there is yet to
975 ; be a need for it in the assembler/disassembler.
976 ;(gen-enum-decl 'model_type "model types"
978 ; (append (map list (map obj:name (current-model-list))) '((max))))
979 ;"#define MAX_MODELS ((int) MODEL_MAX)\n\n"
981 (string-map gen-decl (current-enum-list))
982 "/* Attributes. */\n\n"
983 (string-map gen-decl (current-attr-list))
984 "/* Number of architecture variants. */\n"
985 ; If there is only 1 isa, leave out special handling. */
986 (if (= (length (current-isa-list)) 1)
987 "#define MAX_ISAS 1\n"
988 "#define MAX_ISAS ((int) ISA_MAX)\n")
989 "#define MAX_MACHS ((int) MACH_MAX)\n\n"
994 "/* cgen.h uses things we just defined. */\n"
995 "#include \"opcode/cgen.h\"\n\n"
996 "extern const struct cgen_ifld @arch@_cgen_ifld_table[];\n\n"
997 /gen-attr-table-decls
998 /gen-mach-table-decls
1002 (if (opc-file-provided?)
1003 (gen-extra-cpu.h (opc-file-path) (current-arch-name))
1007 #endif /* @ARCH@_CPU_H */
1012 ; This file contains the "top level" definitions of the cpu.
1013 ; This includes various elements of the description file, expressed in C.
1015 ; ??? A lot of this file can go in a machine-independent file! However,
1016 ; some simulators don't use the cgen opcodes support so there is currently
1017 ; no place to put this file. To be revisited when we do have such a place.
1019 (define (cgen-desc.c)
1020 (logit 1 "Generating " (current-arch-name) "-desc.c ...\n")
1022 (gen-c-copyright "CPU data for @arch@."
1023 CURRENT-COPYRIGHT CURRENT-PACKAGE)
1025 #include \"sysdep.h\"
1028 #include \"ansidecl.h\"
1030 #include \"symcat.h\"
1031 #include \"@arch@-desc.h\"
1032 #include \"@arch@-opc.h\"
1033 #include \"opintl.h\"
1034 #include \"libiberty.h\"
1035 #include \"xregex.h\"
1038 (if (opc-file-provided?)
1039 (gen-extra-cpu.c (opc-file-path) (current-arch-name))
1041 gen-attr-table-defns
1042 /gen-isa-table-defns
1043 /gen-mach-table-defns
1046 gen-multi-ifield-nodes