1 /* Xtensa configuration-specific ISA information.
2 Copyright 2003 Free Software Foundation, Inc.
4 This file is part of BFD, the Binary File Descriptor library.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
20 /* Automatically generated by gen-opcode-code - DO NOT EDIT! */
22 #include <xtensa-isa.h>
23 #include "xtensa-isa-internal.h"
27 #define WINDEX(_n) ((_n) / BPW)
28 #define BINDEX(_n) ((_n) %% BPW)
30 static uint32 tie_do_reloc_l (uint32, uint32) ATTRIBUTE_UNUSED;
31 static uint32 tie_undo_reloc_l (uint32, uint32) ATTRIBUTE_UNUSED;
34 tie_do_reloc_l (uint32 addr, uint32 pc)
40 tie_undo_reloc_l (uint32 offset, uint32 pc)
45 xtensa_opcode_internal** get_opcodes (void);
46 const int get_num_opcodes (void);
47 int decode_insn (const xtensa_insnbuf);
48 int interface_version (void);
50 uint32 get_bbi_field (const xtensa_insnbuf);
51 void set_bbi_field (xtensa_insnbuf, uint32);
52 uint32 get_bbi4_field (const xtensa_insnbuf);
53 void set_bbi4_field (xtensa_insnbuf, uint32);
54 uint32 get_i_field (const xtensa_insnbuf);
55 void set_i_field (xtensa_insnbuf, uint32);
56 uint32 get_imm12_field (const xtensa_insnbuf);
57 void set_imm12_field (xtensa_insnbuf, uint32);
58 uint32 get_imm12b_field (const xtensa_insnbuf);
59 void set_imm12b_field (xtensa_insnbuf, uint32);
60 uint32 get_imm16_field (const xtensa_insnbuf);
61 void set_imm16_field (xtensa_insnbuf, uint32);
62 uint32 get_imm4_field (const xtensa_insnbuf);
63 void set_imm4_field (xtensa_insnbuf, uint32);
64 uint32 get_imm6_field (const xtensa_insnbuf);
65 void set_imm6_field (xtensa_insnbuf, uint32);
66 uint32 get_imm6hi_field (const xtensa_insnbuf);
67 void set_imm6hi_field (xtensa_insnbuf, uint32);
68 uint32 get_imm6lo_field (const xtensa_insnbuf);
69 void set_imm6lo_field (xtensa_insnbuf, uint32);
70 uint32 get_imm7_field (const xtensa_insnbuf);
71 void set_imm7_field (xtensa_insnbuf, uint32);
72 uint32 get_imm7hi_field (const xtensa_insnbuf);
73 void set_imm7hi_field (xtensa_insnbuf, uint32);
74 uint32 get_imm7lo_field (const xtensa_insnbuf);
75 void set_imm7lo_field (xtensa_insnbuf, uint32);
76 uint32 get_imm8_field (const xtensa_insnbuf);
77 void set_imm8_field (xtensa_insnbuf, uint32);
78 uint32 get_m_field (const xtensa_insnbuf);
79 void set_m_field (xtensa_insnbuf, uint32);
80 uint32 get_mn_field (const xtensa_insnbuf);
81 void set_mn_field (xtensa_insnbuf, uint32);
82 uint32 get_n_field (const xtensa_insnbuf);
83 void set_n_field (xtensa_insnbuf, uint32);
84 uint32 get_none_field (const xtensa_insnbuf);
85 void set_none_field (xtensa_insnbuf, uint32);
86 uint32 get_offset_field (const xtensa_insnbuf);
87 void set_offset_field (xtensa_insnbuf, uint32);
88 uint32 get_op0_field (const xtensa_insnbuf);
89 void set_op0_field (xtensa_insnbuf, uint32);
90 uint32 get_op1_field (const xtensa_insnbuf);
91 void set_op1_field (xtensa_insnbuf, uint32);
92 uint32 get_op2_field (const xtensa_insnbuf);
93 void set_op2_field (xtensa_insnbuf, uint32);
94 uint32 get_r_field (const xtensa_insnbuf);
95 void set_r_field (xtensa_insnbuf, uint32);
96 uint32 get_s_field (const xtensa_insnbuf);
97 void set_s_field (xtensa_insnbuf, uint32);
98 uint32 get_sa4_field (const xtensa_insnbuf);
99 void set_sa4_field (xtensa_insnbuf, uint32);
100 uint32 get_sae_field (const xtensa_insnbuf);
101 void set_sae_field (xtensa_insnbuf, uint32);
102 uint32 get_sae4_field (const xtensa_insnbuf);
103 void set_sae4_field (xtensa_insnbuf, uint32);
104 uint32 get_sal_field (const xtensa_insnbuf);
105 void set_sal_field (xtensa_insnbuf, uint32);
106 uint32 get_sar_field (const xtensa_insnbuf);
107 void set_sar_field (xtensa_insnbuf, uint32);
108 uint32 get_sas_field (const xtensa_insnbuf);
109 void set_sas_field (xtensa_insnbuf, uint32);
110 uint32 get_sas4_field (const xtensa_insnbuf);
111 void set_sas4_field (xtensa_insnbuf, uint32);
112 uint32 get_sr_field (const xtensa_insnbuf);
113 void set_sr_field (xtensa_insnbuf, uint32);
114 uint32 get_t_field (const xtensa_insnbuf);
115 void set_t_field (xtensa_insnbuf, uint32);
116 uint32 get_thi3_field (const xtensa_insnbuf);
117 void set_thi3_field (xtensa_insnbuf, uint32);
118 uint32 get_z_field (const xtensa_insnbuf);
119 void set_z_field (xtensa_insnbuf, uint32);
123 get_bbi_field (const xtensa_insnbuf insn)
125 return ((insn[0] & 0xf0000) >> 16) |
126 ((insn[0] & 0x100) >> 4);
130 set_bbi_field (xtensa_insnbuf insn, uint32 val)
132 insn[0] = (insn[0] & 0xfff0ffff) | ((val << 16) & 0xf0000);
133 insn[0] = (insn[0] & 0xfffffeff) | ((val << 4) & 0x100);
137 get_bbi4_field (const xtensa_insnbuf insn)
139 return ((insn[0] & 0x100) >> 8);
143 set_bbi4_field (xtensa_insnbuf insn, uint32 val)
145 insn[0] = (insn[0] & 0xfffffeff) | ((val << 8) & 0x100);
149 get_i_field (const xtensa_insnbuf insn)
151 return ((insn[0] & 0x80000) >> 19);
155 set_i_field (xtensa_insnbuf insn, uint32 val)
157 insn[0] = (insn[0] & 0xfff7ffff) | ((val << 19) & 0x80000);
161 get_imm12_field (const xtensa_insnbuf insn)
163 return ((insn[0] & 0xfff));
167 set_imm12_field (xtensa_insnbuf insn, uint32 val)
169 insn[0] = (insn[0] & 0xfffff000) | (val & 0xfff);
173 get_imm12b_field (const xtensa_insnbuf insn)
175 return ((insn[0] & 0xff)) |
176 ((insn[0] & 0xf000) >> 4);
180 set_imm12b_field (xtensa_insnbuf insn, uint32 val)
182 insn[0] = (insn[0] & 0xffffff00) | (val & 0xff);
183 insn[0] = (insn[0] & 0xffff0fff) | ((val << 4) & 0xf000);
187 get_imm16_field (const xtensa_insnbuf insn)
189 return ((insn[0] & 0xffff));
193 set_imm16_field (xtensa_insnbuf insn, uint32 val)
195 insn[0] = (insn[0] & 0xffff0000) | (val & 0xffff);
199 get_imm4_field (const xtensa_insnbuf insn)
201 return ((insn[0] & 0xf00) >> 8);
205 set_imm4_field (xtensa_insnbuf insn, uint32 val)
207 insn[0] = (insn[0] & 0xfffff0ff) | ((val << 8) & 0xf00);
211 get_imm6_field (const xtensa_insnbuf insn)
213 return ((insn[0] & 0xf00) >> 8) |
214 ((insn[0] & 0x30000) >> 12);
218 set_imm6_field (xtensa_insnbuf insn, uint32 val)
220 insn[0] = (insn[0] & 0xfffff0ff) | ((val << 8) & 0xf00);
221 insn[0] = (insn[0] & 0xfffcffff) | ((val << 12) & 0x30000);
225 get_imm6hi_field (const xtensa_insnbuf insn)
227 return ((insn[0] & 0x30000) >> 16);
231 set_imm6hi_field (xtensa_insnbuf insn, uint32 val)
233 insn[0] = (insn[0] & 0xfffcffff) | ((val << 16) & 0x30000);
237 get_imm6lo_field (const xtensa_insnbuf insn)
239 return ((insn[0] & 0xf00) >> 8);
243 set_imm6lo_field (xtensa_insnbuf insn, uint32 val)
245 insn[0] = (insn[0] & 0xfffff0ff) | ((val << 8) & 0xf00);
249 get_imm7_field (const xtensa_insnbuf insn)
251 return ((insn[0] & 0xf00) >> 8) |
252 ((insn[0] & 0x70000) >> 12);
256 set_imm7_field (xtensa_insnbuf insn, uint32 val)
258 insn[0] = (insn[0] & 0xfffff0ff) | ((val << 8) & 0xf00);
259 insn[0] = (insn[0] & 0xfff8ffff) | ((val << 12) & 0x70000);
263 get_imm7hi_field (const xtensa_insnbuf insn)
265 return ((insn[0] & 0x70000) >> 16);
269 set_imm7hi_field (xtensa_insnbuf insn, uint32 val)
271 insn[0] = (insn[0] & 0xfff8ffff) | ((val << 16) & 0x70000);
275 get_imm7lo_field (const xtensa_insnbuf insn)
277 return ((insn[0] & 0xf00) >> 8);
281 set_imm7lo_field (xtensa_insnbuf insn, uint32 val)
283 insn[0] = (insn[0] & 0xfffff0ff) | ((val << 8) & 0xf00);
287 get_imm8_field (const xtensa_insnbuf insn)
289 return ((insn[0] & 0xff));
293 set_imm8_field (xtensa_insnbuf insn, uint32 val)
295 insn[0] = (insn[0] & 0xffffff00) | (val & 0xff);
299 get_m_field (const xtensa_insnbuf insn)
301 return ((insn[0] & 0x30000) >> 16);
305 set_m_field (xtensa_insnbuf insn, uint32 val)
307 insn[0] = (insn[0] & 0xfffcffff) | ((val << 16) & 0x30000);
311 get_mn_field (const xtensa_insnbuf insn)
313 return ((insn[0] & 0x30000) >> 16) |
314 ((insn[0] & 0xc0000) >> 16);
318 set_mn_field (xtensa_insnbuf insn, uint32 val)
320 insn[0] = (insn[0] & 0xfffcffff) | ((val << 16) & 0x30000);
321 insn[0] = (insn[0] & 0xfff3ffff) | ((val << 16) & 0xc0000);
325 get_n_field (const xtensa_insnbuf insn)
327 return ((insn[0] & 0xc0000) >> 18);
331 set_n_field (xtensa_insnbuf insn, uint32 val)
333 insn[0] = (insn[0] & 0xfff3ffff) | ((val << 18) & 0xc0000);
337 get_none_field (const xtensa_insnbuf insn)
339 return ((insn[0] & 0x0));
343 set_none_field (xtensa_insnbuf insn, uint32 val)
345 insn[0] = (insn[0] & 0xffffffff) | (val & 0x0);
349 get_offset_field (const xtensa_insnbuf insn)
351 return ((insn[0] & 0x3ffff));
355 set_offset_field (xtensa_insnbuf insn, uint32 val)
357 insn[0] = (insn[0] & 0xfffc0000) | (val & 0x3ffff);
361 get_op0_field (const xtensa_insnbuf insn)
363 return ((insn[0] & 0xf00000) >> 20);
367 set_op0_field (xtensa_insnbuf insn, uint32 val)
369 insn[0] = (insn[0] & 0xff0fffff) | ((val << 20) & 0xf00000);
373 get_op1_field (const xtensa_insnbuf insn)
375 return ((insn[0] & 0xf0) >> 4);
379 set_op1_field (xtensa_insnbuf insn, uint32 val)
381 insn[0] = (insn[0] & 0xffffff0f) | ((val << 4) & 0xf0);
385 get_op2_field (const xtensa_insnbuf insn)
387 return ((insn[0] & 0xf));
391 set_op2_field (xtensa_insnbuf insn, uint32 val)
393 insn[0] = (insn[0] & 0xfffffff0) | (val & 0xf);
397 get_r_field (const xtensa_insnbuf insn)
399 return ((insn[0] & 0xf00) >> 8);
403 set_r_field (xtensa_insnbuf insn, uint32 val)
405 insn[0] = (insn[0] & 0xfffff0ff) | ((val << 8) & 0xf00);
409 get_s_field (const xtensa_insnbuf insn)
411 return ((insn[0] & 0xf000) >> 12);
415 set_s_field (xtensa_insnbuf insn, uint32 val)
417 insn[0] = (insn[0] & 0xffff0fff) | ((val << 12) & 0xf000);
421 get_sa4_field (const xtensa_insnbuf insn)
423 return ((insn[0] & 0x1));
427 set_sa4_field (xtensa_insnbuf insn, uint32 val)
429 insn[0] = (insn[0] & 0xfffffffe) | (val & 0x1);
433 get_sae_field (const xtensa_insnbuf insn)
435 return ((insn[0] & 0xf000) >> 12) |
440 set_sae_field (xtensa_insnbuf insn, uint32 val)
442 insn[0] = (insn[0] & 0xffff0fff) | ((val << 12) & 0xf000);
443 insn[0] = (insn[0] & 0xffffffef) | (val & 0x10);
447 get_sae4_field (const xtensa_insnbuf insn)
449 return ((insn[0] & 0x10) >> 4);
453 set_sae4_field (xtensa_insnbuf insn, uint32 val)
455 insn[0] = (insn[0] & 0xffffffef) | ((val << 4) & 0x10);
459 get_sal_field (const xtensa_insnbuf insn)
461 return ((insn[0] & 0xf0000) >> 16) |
462 ((insn[0] & 0x1) << 4);
466 set_sal_field (xtensa_insnbuf insn, uint32 val)
468 insn[0] = (insn[0] & 0xfff0ffff) | ((val << 16) & 0xf0000);
469 insn[0] = (insn[0] & 0xfffffffe) | ((val >> 4) & 0x1);
473 get_sar_field (const xtensa_insnbuf insn)
475 return ((insn[0] & 0xf000) >> 12) |
476 ((insn[0] & 0x1) << 4);
480 set_sar_field (xtensa_insnbuf insn, uint32 val)
482 insn[0] = (insn[0] & 0xffff0fff) | ((val << 12) & 0xf000);
483 insn[0] = (insn[0] & 0xfffffffe) | ((val >> 4) & 0x1);
487 get_sas_field (const xtensa_insnbuf insn)
489 return ((insn[0] & 0xf000) >> 12) |
490 ((insn[0] & 0x10000) >> 12);
494 set_sas_field (xtensa_insnbuf insn, uint32 val)
496 insn[0] = (insn[0] & 0xffff0fff) | ((val << 12) & 0xf000);
497 insn[0] = (insn[0] & 0xfffeffff) | ((val << 12) & 0x10000);
501 get_sas4_field (const xtensa_insnbuf insn)
503 return ((insn[0] & 0x10000) >> 16);
507 set_sas4_field (xtensa_insnbuf insn, uint32 val)
509 insn[0] = (insn[0] & 0xfffeffff) | ((val << 16) & 0x10000);
513 get_sr_field (const xtensa_insnbuf insn)
515 return ((insn[0] & 0xf00) >> 8) |
516 ((insn[0] & 0xf000) >> 8);
520 set_sr_field (xtensa_insnbuf insn, uint32 val)
522 insn[0] = (insn[0] & 0xfffff0ff) | ((val << 8) & 0xf00);
523 insn[0] = (insn[0] & 0xffff0fff) | ((val << 8) & 0xf000);
527 get_t_field (const xtensa_insnbuf insn)
529 return ((insn[0] & 0xf0000) >> 16);
533 set_t_field (xtensa_insnbuf insn, uint32 val)
535 insn[0] = (insn[0] & 0xfff0ffff) | ((val << 16) & 0xf0000);
539 get_thi3_field (const xtensa_insnbuf insn)
541 return ((insn[0] & 0xe0000) >> 17);
545 set_thi3_field (xtensa_insnbuf insn, uint32 val)
547 insn[0] = (insn[0] & 0xfff1ffff) | ((val << 17) & 0xe0000);
551 get_z_field (const xtensa_insnbuf insn)
553 return ((insn[0] & 0x40000) >> 18);
557 set_z_field (xtensa_insnbuf insn, uint32 val)
559 insn[0] = (insn[0] & 0xfffbffff) | ((val << 18) & 0x40000);
562 uint32 decode_b4constu (uint32);
563 xtensa_encode_result encode_b4constu (uint32 *);
564 uint32 decode_simm8x256 (uint32);
565 xtensa_encode_result encode_simm8x256 (uint32 *);
566 uint32 decode_soffset (uint32);
567 xtensa_encode_result encode_soffset (uint32 *);
568 uint32 decode_imm4 (uint32);
569 xtensa_encode_result encode_imm4 (uint32 *);
570 uint32 decode_op0 (uint32);
571 xtensa_encode_result encode_op0 (uint32 *);
572 uint32 decode_op1 (uint32);
573 xtensa_encode_result encode_op1 (uint32 *);
574 uint32 decode_imm6 (uint32);
575 xtensa_encode_result encode_imm6 (uint32 *);
576 uint32 decode_op2 (uint32);
577 xtensa_encode_result encode_op2 (uint32 *);
578 uint32 decode_imm7 (uint32);
579 xtensa_encode_result encode_imm7 (uint32 *);
580 uint32 decode_simm4 (uint32);
581 xtensa_encode_result encode_simm4 (uint32 *);
582 uint32 decode_ai4const (uint32);
583 xtensa_encode_result encode_ai4const (uint32 *);
584 uint32 decode_imm8 (uint32);
585 xtensa_encode_result encode_imm8 (uint32 *);
586 uint32 decode_sae (uint32);
587 xtensa_encode_result encode_sae (uint32 *);
588 uint32 decode_imm7lo (uint32);
589 xtensa_encode_result encode_imm7lo (uint32 *);
590 uint32 decode_simm7 (uint32);
591 xtensa_encode_result encode_simm7 (uint32 *);
592 uint32 decode_simm8 (uint32);
593 xtensa_encode_result encode_simm8 (uint32 *);
594 uint32 decode_uimm12x8 (uint32);
595 xtensa_encode_result encode_uimm12x8 (uint32 *);
596 uint32 decode_sal (uint32);
597 xtensa_encode_result encode_sal (uint32 *);
598 uint32 decode_uimm6 (uint32);
599 xtensa_encode_result encode_uimm6 (uint32 *);
600 uint32 decode_sas4 (uint32);
601 xtensa_encode_result encode_sas4 (uint32 *);
602 uint32 decode_uimm8 (uint32);
603 xtensa_encode_result encode_uimm8 (uint32 *);
604 uint32 decode_uimm16x4 (uint32);
605 xtensa_encode_result encode_uimm16x4 (uint32 *);
606 uint32 decode_sar (uint32);
607 xtensa_encode_result encode_sar (uint32 *);
608 uint32 decode_sa4 (uint32);
609 xtensa_encode_result encode_sa4 (uint32 *);
610 uint32 decode_sas (uint32);
611 xtensa_encode_result encode_sas (uint32 *);
612 uint32 decode_imm6hi (uint32);
613 xtensa_encode_result encode_imm6hi (uint32 *);
614 uint32 decode_bbi (uint32);
615 xtensa_encode_result encode_bbi (uint32 *);
616 uint32 decode_uimm8x2 (uint32);
617 xtensa_encode_result encode_uimm8x2 (uint32 *);
618 uint32 decode_uimm8x4 (uint32);
619 xtensa_encode_result encode_uimm8x4 (uint32 *);
620 uint32 decode_msalp32 (uint32);
621 xtensa_encode_result encode_msalp32 (uint32 *);
622 uint32 decode_bbi4 (uint32);
623 xtensa_encode_result encode_bbi4 (uint32 *);
624 uint32 decode_op2p1 (uint32);
625 xtensa_encode_result encode_op2p1 (uint32 *);
626 uint32 decode_soffsetx4 (uint32);
627 xtensa_encode_result encode_soffsetx4 (uint32 *);
628 uint32 decode_imm6lo (uint32);
629 xtensa_encode_result encode_imm6lo (uint32 *);
630 uint32 decode_imm12 (uint32);
631 xtensa_encode_result encode_imm12 (uint32 *);
632 uint32 decode_b4const (uint32);
633 xtensa_encode_result encode_b4const (uint32 *);
634 uint32 decode_i (uint32);
635 xtensa_encode_result encode_i (uint32 *);
636 uint32 decode_imm16 (uint32);
637 xtensa_encode_result encode_imm16 (uint32 *);
638 uint32 decode_mn (uint32);
639 xtensa_encode_result encode_mn (uint32 *);
640 uint32 decode_m (uint32);
641 xtensa_encode_result encode_m (uint32 *);
642 uint32 decode_n (uint32);
643 xtensa_encode_result encode_n (uint32 *);
644 uint32 decode_none (uint32);
645 xtensa_encode_result encode_none (uint32 *);
646 uint32 decode_imm12b (uint32);
647 xtensa_encode_result encode_imm12b (uint32 *);
648 uint32 decode_r (uint32);
649 xtensa_encode_result encode_r (uint32 *);
650 uint32 decode_s (uint32);
651 xtensa_encode_result encode_s (uint32 *);
652 uint32 decode_t (uint32);
653 xtensa_encode_result encode_t (uint32 *);
654 uint32 decode_thi3 (uint32);
655 xtensa_encode_result encode_thi3 (uint32 *);
656 uint32 decode_sae4 (uint32);
657 xtensa_encode_result encode_sae4 (uint32 *);
658 uint32 decode_offset (uint32);
659 xtensa_encode_result encode_offset (uint32 *);
660 uint32 decode_imm7hi (uint32);
661 xtensa_encode_result encode_imm7hi (uint32 *);
662 uint32 decode_uimm4x16 (uint32);
663 xtensa_encode_result encode_uimm4x16 (uint32 *);
664 uint32 decode_simm12b (uint32);
665 xtensa_encode_result encode_simm12b (uint32 *);
666 uint32 decode_lsi4x4 (uint32);
667 xtensa_encode_result encode_lsi4x4 (uint32 *);
668 uint32 decode_z (uint32);
669 xtensa_encode_result encode_z (uint32 *);
670 uint32 decode_simm12 (uint32);
671 xtensa_encode_result encode_simm12 (uint32 *);
672 uint32 decode_sr (uint32);
673 xtensa_encode_result encode_sr (uint32 *);
674 uint32 decode_nimm4x2 (uint32);
675 xtensa_encode_result encode_nimm4x2 (uint32 *);
678 static const uint32 b4constu_table[] = {
698 decode_b4constu (uint32 val)
700 val = b4constu_table[val];
705 encode_b4constu (uint32 *valp)
709 for (i = 0; i < (1 << 4); i += 1)
710 if (b4constu_table[i] == val) goto found;
711 return xtensa_encode_result_not_in_table;
715 return xtensa_encode_result_ok;
719 decode_simm8x256 (uint32 val)
721 val = (val ^ 0x80) - 0x80;
727 encode_simm8x256 (uint32 *valp)
730 if ((val & ((1 << 8) - 1)) != 0)
731 return xtensa_encode_result_align;
732 val = (signed int) val >> 8;
733 if (((val + (1 << 7)) >> 8) != 0)
735 if ((signed int) val > 0)
736 return xtensa_encode_result_too_high;
738 return xtensa_encode_result_too_low;
741 return xtensa_encode_result_ok;
745 decode_soffset (uint32 val)
747 val = (val ^ 0x20000) - 0x20000;
752 encode_soffset (uint32 *valp)
755 if (((val + (1 << 17)) >> 18) != 0)
757 if ((signed int) val > 0)
758 return xtensa_encode_result_too_high;
760 return xtensa_encode_result_too_low;
763 return xtensa_encode_result_ok;
767 decode_imm4 (uint32 val)
773 encode_imm4 (uint32 *valp)
777 return xtensa_encode_result_too_high;
779 return xtensa_encode_result_ok;
783 decode_op0 (uint32 val)
789 encode_op0 (uint32 *valp)
793 return xtensa_encode_result_too_high;
795 return xtensa_encode_result_ok;
799 decode_op1 (uint32 val)
805 encode_op1 (uint32 *valp)
809 return xtensa_encode_result_too_high;
811 return xtensa_encode_result_ok;
815 decode_imm6 (uint32 val)
821 encode_imm6 (uint32 *valp)
825 return xtensa_encode_result_too_high;
827 return xtensa_encode_result_ok;
831 decode_op2 (uint32 val)
837 encode_op2 (uint32 *valp)
841 return xtensa_encode_result_too_high;
843 return xtensa_encode_result_ok;
847 decode_imm7 (uint32 val)
853 encode_imm7 (uint32 *valp)
857 return xtensa_encode_result_too_high;
859 return xtensa_encode_result_ok;
863 decode_simm4 (uint32 val)
865 val = (val ^ 0x8) - 0x8;
870 encode_simm4 (uint32 *valp)
873 if (((val + (1 << 3)) >> 4) != 0)
875 if ((signed int) val > 0)
876 return xtensa_encode_result_too_high;
878 return xtensa_encode_result_too_low;
881 return xtensa_encode_result_ok;
884 static const uint32 ai4const_table[] = {
904 decode_ai4const (uint32 val)
906 val = ai4const_table[val];
911 encode_ai4const (uint32 *valp)
915 for (i = 0; i < (1 << 4); i += 1)
916 if (ai4const_table[i] == val) goto found;
917 return xtensa_encode_result_not_in_table;
921 return xtensa_encode_result_ok;
925 decode_imm8 (uint32 val)
931 encode_imm8 (uint32 *valp)
935 return xtensa_encode_result_too_high;
937 return xtensa_encode_result_ok;
941 decode_sae (uint32 val)
947 encode_sae (uint32 *valp)
951 return xtensa_encode_result_too_high;
953 return xtensa_encode_result_ok;
957 decode_imm7lo (uint32 val)
963 encode_imm7lo (uint32 *valp)
967 return xtensa_encode_result_too_high;
969 return xtensa_encode_result_ok;
973 decode_simm7 (uint32 val)
981 encode_simm7 (uint32 *valp)
984 if ((signed int) val < -32)
985 return xtensa_encode_result_too_low;
986 if ((signed int) val > 95)
987 return xtensa_encode_result_too_high;
989 return xtensa_encode_result_ok;
993 decode_simm8 (uint32 val)
995 val = (val ^ 0x80) - 0x80;
1000 encode_simm8 (uint32 *valp)
1003 if (((val + (1 << 7)) >> 8) != 0)
1005 if ((signed int) val > 0)
1006 return xtensa_encode_result_too_high;
1008 return xtensa_encode_result_too_low;
1011 return xtensa_encode_result_ok;
1015 decode_uimm12x8 (uint32 val)
1021 xtensa_encode_result
1022 encode_uimm12x8 (uint32 *valp)
1025 if ((val & ((1 << 3) - 1)) != 0)
1026 return xtensa_encode_result_align;
1027 val = (signed int) val >> 3;
1028 if ((val >> 12) != 0)
1029 return xtensa_encode_result_too_high;
1031 return xtensa_encode_result_ok;
1035 decode_sal (uint32 val)
1040 xtensa_encode_result
1041 encode_sal (uint32 *valp)
1044 if ((val >> 5) != 0)
1045 return xtensa_encode_result_too_high;
1047 return xtensa_encode_result_ok;
1051 decode_uimm6 (uint32 val)
1056 xtensa_encode_result
1057 encode_uimm6 (uint32 *valp)
1060 if ((val >> 6) != 0)
1061 return xtensa_encode_result_too_high;
1063 return xtensa_encode_result_ok;
1067 decode_sas4 (uint32 val)
1072 xtensa_encode_result
1073 encode_sas4 (uint32 *valp)
1076 if ((val >> 1) != 0)
1077 return xtensa_encode_result_too_high;
1079 return xtensa_encode_result_ok;
1083 decode_uimm8 (uint32 val)
1088 xtensa_encode_result
1089 encode_uimm8 (uint32 *valp)
1092 if ((val >> 8) != 0)
1093 return xtensa_encode_result_too_high;
1095 return xtensa_encode_result_ok;
1099 decode_uimm16x4 (uint32 val)
1106 xtensa_encode_result
1107 encode_uimm16x4 (uint32 *valp)
1110 if ((val & ((1 << 2) - 1)) != 0)
1111 return xtensa_encode_result_align;
1112 val = (signed int) val >> 2;
1113 if ((signed int) val >> 16 != -1)
1115 if ((signed int) val >= 0)
1116 return xtensa_encode_result_too_high;
1118 return xtensa_encode_result_too_low;
1121 return xtensa_encode_result_ok;
1125 decode_sar (uint32 val)
1130 xtensa_encode_result
1131 encode_sar (uint32 *valp)
1134 if ((val >> 5) != 0)
1135 return xtensa_encode_result_too_high;
1137 return xtensa_encode_result_ok;
1141 decode_sa4 (uint32 val)
1146 xtensa_encode_result
1147 encode_sa4 (uint32 *valp)
1150 if ((val >> 1) != 0)
1151 return xtensa_encode_result_too_high;
1153 return xtensa_encode_result_ok;
1157 decode_sas (uint32 val)
1162 xtensa_encode_result
1163 encode_sas (uint32 *valp)
1166 if ((val >> 5) != 0)
1167 return xtensa_encode_result_too_high;
1169 return xtensa_encode_result_ok;
1173 decode_imm6hi (uint32 val)
1178 xtensa_encode_result
1179 encode_imm6hi (uint32 *valp)
1182 if ((val >> 2) != 0)
1183 return xtensa_encode_result_too_high;
1185 return xtensa_encode_result_ok;
1189 decode_bbi (uint32 val)
1194 xtensa_encode_result
1195 encode_bbi (uint32 *valp)
1198 if ((val >> 5) != 0)
1199 return xtensa_encode_result_too_high;
1201 return xtensa_encode_result_ok;
1205 decode_uimm8x2 (uint32 val)
1211 xtensa_encode_result
1212 encode_uimm8x2 (uint32 *valp)
1215 if ((val & ((1 << 1) - 1)) != 0)
1216 return xtensa_encode_result_align;
1217 val = (signed int) val >> 1;
1218 if ((val >> 8) != 0)
1219 return xtensa_encode_result_too_high;
1221 return xtensa_encode_result_ok;
1225 decode_uimm8x4 (uint32 val)
1231 xtensa_encode_result
1232 encode_uimm8x4 (uint32 *valp)
1235 if ((val & ((1 << 2) - 1)) != 0)
1236 return xtensa_encode_result_align;
1237 val = (signed int) val >> 2;
1238 if ((val >> 8) != 0)
1239 return xtensa_encode_result_too_high;
1241 return xtensa_encode_result_ok;
1244 static const uint32 mip32const_table[] = {
1280 decode_msalp32 (uint32 val)
1282 val = mip32const_table[val];
1286 xtensa_encode_result
1287 encode_msalp32 (uint32 *valp)
1291 for (i = 0; i < (1 << 5); i += 1)
1292 if (mip32const_table[i] == val) goto found;
1293 return xtensa_encode_result_not_in_table;
1297 return xtensa_encode_result_ok;
1301 decode_bbi4 (uint32 val)
1306 xtensa_encode_result
1307 encode_bbi4 (uint32 *valp)
1310 if ((val >> 1) != 0)
1311 return xtensa_encode_result_too_high;
1313 return xtensa_encode_result_ok;
1316 static const uint32 i4p1const_table[] = {
1336 decode_op2p1 (uint32 val)
1338 val = i4p1const_table[val];
1342 xtensa_encode_result
1343 encode_op2p1 (uint32 *valp)
1347 for (i = 0; i < (1 << 4); i += 1)
1348 if (i4p1const_table[i] == val) goto found;
1349 return xtensa_encode_result_not_in_table;
1353 return xtensa_encode_result_ok;
1357 decode_soffsetx4 (uint32 val)
1359 val = (val ^ 0x20000) - 0x20000;
1364 xtensa_encode_result
1365 encode_soffsetx4 (uint32 *valp)
1368 if ((val & ((1 << 2) - 1)) != 0)
1369 return xtensa_encode_result_align;
1370 val = (signed int) val >> 2;
1371 if (((val + (1 << 17)) >> 18) != 0)
1373 if ((signed int) val > 0)
1374 return xtensa_encode_result_too_high;
1376 return xtensa_encode_result_too_low;
1379 return xtensa_encode_result_ok;
1383 decode_imm6lo (uint32 val)
1388 xtensa_encode_result
1389 encode_imm6lo (uint32 *valp)
1392 if ((val >> 4) != 0)
1393 return xtensa_encode_result_too_high;
1395 return xtensa_encode_result_ok;
1399 decode_imm12 (uint32 val)
1404 xtensa_encode_result
1405 encode_imm12 (uint32 *valp)
1408 if ((val >> 12) != 0)
1409 return xtensa_encode_result_too_high;
1411 return xtensa_encode_result_ok;
1414 static const uint32 b4const_table[] = {
1434 decode_b4const (uint32 val)
1436 val = b4const_table[val];
1440 xtensa_encode_result
1441 encode_b4const (uint32 *valp)
1445 for (i = 0; i < (1 << 4); i += 1)
1446 if (b4const_table[i] == val) goto found;
1447 return xtensa_encode_result_not_in_table;
1451 return xtensa_encode_result_ok;
1455 decode_i (uint32 val)
1460 xtensa_encode_result
1461 encode_i (uint32 *valp)
1464 if ((val >> 1) != 0)
1465 return xtensa_encode_result_too_high;
1467 return xtensa_encode_result_ok;
1471 decode_imm16 (uint32 val)
1476 xtensa_encode_result
1477 encode_imm16 (uint32 *valp)
1480 if ((val >> 16) != 0)
1481 return xtensa_encode_result_too_high;
1483 return xtensa_encode_result_ok;
1487 decode_mn (uint32 val)
1492 xtensa_encode_result
1493 encode_mn (uint32 *valp)
1496 if ((val >> 4) != 0)
1497 return xtensa_encode_result_too_high;
1499 return xtensa_encode_result_ok;
1503 decode_m (uint32 val)
1508 xtensa_encode_result
1509 encode_m (uint32 *valp)
1512 if ((val >> 2) != 0)
1513 return xtensa_encode_result_too_high;
1515 return xtensa_encode_result_ok;
1519 decode_n (uint32 val)
1524 xtensa_encode_result
1525 encode_n (uint32 *valp)
1528 if ((val >> 2) != 0)
1529 return xtensa_encode_result_too_high;
1531 return xtensa_encode_result_ok;
1535 decode_none (uint32 val)
1540 xtensa_encode_result
1541 encode_none (uint32 *valp)
1544 if ((val >> 0) != 0)
1545 return xtensa_encode_result_too_high;
1547 return xtensa_encode_result_ok;
1551 decode_imm12b (uint32 val)
1556 xtensa_encode_result
1557 encode_imm12b (uint32 *valp)
1560 if ((val >> 12) != 0)
1561 return xtensa_encode_result_too_high;
1563 return xtensa_encode_result_ok;
1567 decode_r (uint32 val)
1572 xtensa_encode_result
1573 encode_r (uint32 *valp)
1576 if ((val >> 4) != 0)
1577 return xtensa_encode_result_too_high;
1579 return xtensa_encode_result_ok;
1583 decode_s (uint32 val)
1588 xtensa_encode_result
1589 encode_s (uint32 *valp)
1592 if ((val >> 4) != 0)
1593 return xtensa_encode_result_too_high;
1595 return xtensa_encode_result_ok;
1599 decode_t (uint32 val)
1604 xtensa_encode_result
1605 encode_t (uint32 *valp)
1608 if ((val >> 4) != 0)
1609 return xtensa_encode_result_too_high;
1611 return xtensa_encode_result_ok;
1615 decode_thi3 (uint32 val)
1620 xtensa_encode_result
1621 encode_thi3 (uint32 *valp)
1624 if ((val >> 3) != 0)
1625 return xtensa_encode_result_too_high;
1627 return xtensa_encode_result_ok;
1631 decode_sae4 (uint32 val)
1636 xtensa_encode_result
1637 encode_sae4 (uint32 *valp)
1640 if ((val >> 1) != 0)
1641 return xtensa_encode_result_too_high;
1643 return xtensa_encode_result_ok;
1647 decode_offset (uint32 val)
1652 xtensa_encode_result
1653 encode_offset (uint32 *valp)
1656 if ((val >> 18) != 0)
1657 return xtensa_encode_result_too_high;
1659 return xtensa_encode_result_ok;
1663 decode_imm7hi (uint32 val)
1668 xtensa_encode_result
1669 encode_imm7hi (uint32 *valp)
1672 if ((val >> 3) != 0)
1673 return xtensa_encode_result_too_high;
1675 return xtensa_encode_result_ok;
1679 decode_uimm4x16 (uint32 val)
1685 xtensa_encode_result
1686 encode_uimm4x16 (uint32 *valp)
1689 if ((val & ((1 << 4) - 1)) != 0)
1690 return xtensa_encode_result_align;
1691 val = (signed int) val >> 4;
1692 if ((val >> 4) != 0)
1693 return xtensa_encode_result_too_high;
1695 return xtensa_encode_result_ok;
1699 decode_simm12b (uint32 val)
1701 val = (val ^ 0x800) - 0x800;
1705 xtensa_encode_result
1706 encode_simm12b (uint32 *valp)
1709 if (((val + (1 << 11)) >> 12) != 0)
1711 if ((signed int) val > 0)
1712 return xtensa_encode_result_too_high;
1714 return xtensa_encode_result_too_low;
1717 return xtensa_encode_result_ok;
1721 decode_lsi4x4 (uint32 val)
1727 xtensa_encode_result
1728 encode_lsi4x4 (uint32 *valp)
1731 if ((val & ((1 << 2) - 1)) != 0)
1732 return xtensa_encode_result_align;
1733 val = (signed int) val >> 2;
1734 if ((val >> 4) != 0)
1735 return xtensa_encode_result_too_high;
1737 return xtensa_encode_result_ok;
1741 decode_z (uint32 val)
1746 xtensa_encode_result
1747 encode_z (uint32 *valp)
1750 if ((val >> 1) != 0)
1751 return xtensa_encode_result_too_high;
1753 return xtensa_encode_result_ok;
1757 decode_simm12 (uint32 val)
1759 val = (val ^ 0x800) - 0x800;
1763 xtensa_encode_result
1764 encode_simm12 (uint32 *valp)
1767 if (((val + (1 << 11)) >> 12) != 0)
1769 if ((signed int) val > 0)
1770 return xtensa_encode_result_too_high;
1772 return xtensa_encode_result_too_low;
1775 return xtensa_encode_result_ok;
1779 decode_sr (uint32 val)
1784 xtensa_encode_result
1785 encode_sr (uint32 *valp)
1788 if ((val >> 8) != 0)
1789 return xtensa_encode_result_too_high;
1791 return xtensa_encode_result_ok;
1795 decode_nimm4x2 (uint32 val)
1802 xtensa_encode_result
1803 encode_nimm4x2 (uint32 *valp)
1806 if ((val & ((1 << 2) - 1)) != 0)
1807 return xtensa_encode_result_align;
1808 val = (signed int) val >> 2;
1809 if ((signed int) val >> 4 != -1)
1811 if ((signed int) val >= 0)
1812 return xtensa_encode_result_too_high;
1814 return xtensa_encode_result_too_low;
1817 return xtensa_encode_result_ok;
1822 uint32 do_reloc_l (uint32, uint32);
1823 uint32 undo_reloc_l (uint32, uint32);
1824 uint32 do_reloc_L (uint32, uint32);
1825 uint32 undo_reloc_L (uint32, uint32);
1826 uint32 do_reloc_r (uint32, uint32);
1827 uint32 undo_reloc_r (uint32, uint32);
1831 do_reloc_l (uint32 addr, uint32 pc)
1833 return addr - pc - 4;
1837 undo_reloc_l (uint32 offset, uint32 pc)
1839 return pc + offset + 4;
1843 do_reloc_L (uint32 addr, uint32 pc)
1845 return addr - (pc & -4) - 4;
1849 undo_reloc_L (uint32 offset, uint32 pc)
1851 return (pc & -4) + offset + 4;
1855 do_reloc_r (uint32 addr, uint32 pc)
1857 return addr - ((pc+3) & -4);
1861 undo_reloc_r (uint32 offset, uint32 pc)
1863 return ((pc+3) & -4) + offset;
1866 static xtensa_operand_internal iib4const_operand = {
1878 static xtensa_operand_internal iiuimm8_operand = {
1890 static xtensa_operand_internal lisoffsetx4_operand = {
1902 static xtensa_operand_internal iisimm8x256_operand = {
1914 static xtensa_operand_internal lisimm12_operand = {
1926 static xtensa_operand_internal iiop2p1_operand = {
1938 static xtensa_operand_internal iisae_operand = {
1950 static xtensa_operand_internal iis_operand = {
1962 static xtensa_operand_internal iit_operand = {
1974 static xtensa_operand_internal iisimm12b_operand = {
1986 static xtensa_operand_internal iinimm4x2_operand = {
1998 static xtensa_operand_internal iiuimm4x16_operand = {
2010 static xtensa_operand_internal abs_operand = {
2022 static xtensa_operand_internal iisar_operand = {
2034 static xtensa_operand_internal abt_operand = {
2046 static xtensa_operand_internal iisas_operand = {
2058 static xtensa_operand_internal amr_operand = {
2070 static xtensa_operand_internal iib4constu_operand = {
2082 static xtensa_operand_internal iisr_operand = {
2094 static xtensa_operand_internal iibbi_operand = {
2106 static xtensa_operand_internal iiai4const_operand = {
2118 static xtensa_operand_internal iiuimm12x8_operand = {
2130 static xtensa_operand_internal riuimm16x4_operand = {
2142 static xtensa_operand_internal lisimm8_operand = {
2154 static xtensa_operand_internal iilsi4x4_operand = {
2166 static xtensa_operand_internal iiuimm8x2_operand = {
2178 static xtensa_operand_internal iisimm4_operand = {
2190 static xtensa_operand_internal iimsalp32_operand = {
2202 static xtensa_operand_internal liuimm6_operand = {
2214 static xtensa_operand_internal iiuimm8x4_operand = {
2226 static xtensa_operand_internal lisoffset_operand = {
2238 static xtensa_operand_internal iisimm7_operand = {
2250 static xtensa_operand_internal ais_operand = {
2262 static xtensa_operand_internal liuimm8_operand = {
2274 static xtensa_operand_internal ait_operand = {
2286 static xtensa_operand_internal iisimm8_operand = {
2298 static xtensa_operand_internal aor_operand = {
2310 static xtensa_operand_internal aos_operand = {
2322 static xtensa_operand_internal aot_operand = {
2334 static xtensa_iclass_internal nopn_iclass = {
2339 static xtensa_operand_internal *movi_operand_list[] = {
2344 static xtensa_iclass_internal movi_iclass = {
2346 &movi_operand_list[0]
2349 static xtensa_operand_internal *bsi8u_operand_list[] = {
2351 &iib4constu_operand,
2355 static xtensa_iclass_internal bsi8u_iclass = {
2357 &bsi8u_operand_list[0]
2360 static xtensa_operand_internal *itlb_operand_list[] = {
2364 static xtensa_iclass_internal itlb_iclass = {
2366 &itlb_operand_list[0]
2369 static xtensa_operand_internal *shiftst_operand_list[] = {
2375 static xtensa_iclass_internal shiftst_iclass = {
2377 &shiftst_operand_list[0]
2380 static xtensa_operand_internal *l32r_operand_list[] = {
2385 static xtensa_iclass_internal l32r_iclass = {
2387 &l32r_operand_list[0]
2390 static xtensa_iclass_internal rfe_iclass = {
2395 static xtensa_operand_internal *wait_operand_list[] = {
2399 static xtensa_iclass_internal wait_iclass = {
2401 &wait_operand_list[0]
2404 static xtensa_operand_internal *rfi_operand_list[] = {
2408 static xtensa_iclass_internal rfi_iclass = {
2410 &rfi_operand_list[0]
2413 static xtensa_operand_internal *movz_operand_list[] = {
2419 static xtensa_iclass_internal movz_iclass = {
2421 &movz_operand_list[0]
2424 static xtensa_operand_internal *callx_operand_list[] = {
2428 static xtensa_iclass_internal callx_iclass = {
2430 &callx_operand_list[0]
2433 static xtensa_operand_internal *mov_n_operand_list[] = {
2438 static xtensa_iclass_internal mov_n_iclass = {
2440 &mov_n_operand_list[0]
2443 static xtensa_operand_internal *loadi4_operand_list[] = {
2449 static xtensa_iclass_internal loadi4_iclass = {
2451 &loadi4_operand_list[0]
2454 static xtensa_operand_internal *exti_operand_list[] = {
2461 static xtensa_iclass_internal exti_iclass = {
2463 &exti_operand_list[0]
2466 static xtensa_operand_internal *break_operand_list[] = {
2471 static xtensa_iclass_internal break_iclass = {
2473 &break_operand_list[0]
2476 static xtensa_operand_internal *slli_operand_list[] = {
2482 static xtensa_iclass_internal slli_iclass = {
2484 &slli_operand_list[0]
2487 static xtensa_operand_internal *s16i_operand_list[] = {
2493 static xtensa_iclass_internal s16i_iclass = {
2495 &s16i_operand_list[0]
2498 static xtensa_operand_internal *call_operand_list[] = {
2499 &lisoffsetx4_operand
2502 static xtensa_iclass_internal call_iclass = {
2504 &call_operand_list[0]
2507 static xtensa_operand_internal *shifts_operand_list[] = {
2512 static xtensa_iclass_internal shifts_iclass = {
2514 &shifts_operand_list[0]
2517 static xtensa_operand_internal *shiftt_operand_list[] = {
2522 static xtensa_iclass_internal shiftt_iclass = {
2524 &shiftt_operand_list[0]
2527 static xtensa_operand_internal *rotw_operand_list[] = {
2531 static xtensa_iclass_internal rotw_iclass = {
2533 &rotw_operand_list[0]
2536 static xtensa_operand_internal *addsub_operand_list[] = {
2542 static xtensa_iclass_internal addsub_iclass = {
2544 &addsub_operand_list[0]
2547 static xtensa_operand_internal *l8i_operand_list[] = {
2553 static xtensa_iclass_internal l8i_iclass = {
2555 &l8i_operand_list[0]
2558 static xtensa_operand_internal *sari_operand_list[] = {
2562 static xtensa_iclass_internal sari_iclass = {
2564 &sari_operand_list[0]
2567 static xtensa_operand_internal *xsr_operand_list[] = {
2572 static xtensa_iclass_internal xsr_iclass = {
2574 &xsr_operand_list[0]
2577 static xtensa_operand_internal *rsil_operand_list[] = {
2582 static xtensa_iclass_internal rsil_iclass = {
2584 &rsil_operand_list[0]
2587 static xtensa_operand_internal *bst8_operand_list[] = {
2593 static xtensa_iclass_internal bst8_iclass = {
2595 &bst8_operand_list[0]
2598 static xtensa_operand_internal *addi_operand_list[] = {
2604 static xtensa_iclass_internal addi_iclass = {
2606 &addi_operand_list[0]
2609 static xtensa_operand_internal *callx12_operand_list[] = {
2613 static xtensa_iclass_internal callx12_iclass = {
2615 &callx12_operand_list[0]
2618 static xtensa_operand_internal *bsi8_operand_list[] = {
2624 static xtensa_iclass_internal bsi8_iclass = {
2626 &bsi8_operand_list[0]
2629 static xtensa_operand_internal *jumpx_operand_list[] = {
2633 static xtensa_iclass_internal jumpx_iclass = {
2635 &jumpx_operand_list[0]
2638 static xtensa_iclass_internal retn_iclass = {
2643 static xtensa_operand_internal *nsa_operand_list[] = {
2648 static xtensa_iclass_internal nsa_iclass = {
2650 &nsa_operand_list[0]
2653 static xtensa_operand_internal *storei4_operand_list[] = {
2659 static xtensa_iclass_internal storei4_iclass = {
2661 &storei4_operand_list[0]
2664 static xtensa_operand_internal *wtlb_operand_list[] = {
2669 static xtensa_iclass_internal wtlb_iclass = {
2671 &wtlb_operand_list[0]
2674 static xtensa_operand_internal *dce_operand_list[] = {
2679 static xtensa_iclass_internal dce_iclass = {
2681 &dce_operand_list[0]
2684 static xtensa_operand_internal *l16i_operand_list[] = {
2690 static xtensa_iclass_internal l16i_iclass = {
2692 &l16i_operand_list[0]
2695 static xtensa_operand_internal *callx4_operand_list[] = {
2699 static xtensa_iclass_internal callx4_iclass = {
2701 &callx4_operand_list[0]
2704 static xtensa_operand_internal *callx8_operand_list[] = {
2708 static xtensa_iclass_internal callx8_iclass = {
2710 &callx8_operand_list[0]
2713 static xtensa_operand_internal *movsp_operand_list[] = {
2718 static xtensa_iclass_internal movsp_iclass = {
2720 &movsp_operand_list[0]
2723 static xtensa_operand_internal *wsr_operand_list[] = {
2728 static xtensa_iclass_internal wsr_iclass = {
2730 &wsr_operand_list[0]
2733 static xtensa_operand_internal *call12_operand_list[] = {
2734 &lisoffsetx4_operand
2737 static xtensa_iclass_internal call12_iclass = {
2739 &call12_operand_list[0]
2742 static xtensa_operand_internal *call4_operand_list[] = {
2743 &lisoffsetx4_operand
2746 static xtensa_iclass_internal call4_iclass = {
2748 &call4_operand_list[0]
2751 static xtensa_operand_internal *addmi_operand_list[] = {
2754 &iisimm8x256_operand
2757 static xtensa_iclass_internal addmi_iclass = {
2759 &addmi_operand_list[0]
2762 static xtensa_operand_internal *bit_operand_list[] = {
2768 static xtensa_iclass_internal bit_iclass = {
2770 &bit_operand_list[0]
2773 static xtensa_operand_internal *call8_operand_list[] = {
2774 &lisoffsetx4_operand
2777 static xtensa_iclass_internal call8_iclass = {
2779 &call8_operand_list[0]
2782 static xtensa_iclass_internal itlba_iclass = {
2787 static xtensa_operand_internal *break_n_operand_list[] = {
2791 static xtensa_iclass_internal break_n_iclass = {
2793 &break_n_operand_list[0]
2796 static xtensa_operand_internal *sar_operand_list[] = {
2800 static xtensa_iclass_internal sar_iclass = {
2802 &sar_operand_list[0]
2805 static xtensa_operand_internal *s32e_operand_list[] = {
2811 static xtensa_iclass_internal s32e_iclass = {
2813 &s32e_operand_list[0]
2816 static xtensa_operand_internal *bz6_operand_list[] = {
2821 static xtensa_iclass_internal bz6_iclass = {
2823 &bz6_operand_list[0]
2826 static xtensa_operand_internal *loop_operand_list[] = {
2831 static xtensa_iclass_internal loop_iclass = {
2833 &loop_operand_list[0]
2836 static xtensa_operand_internal *rsr_operand_list[] = {
2841 static xtensa_iclass_internal rsr_iclass = {
2843 &rsr_operand_list[0]
2846 static xtensa_operand_internal *icache_operand_list[] = {
2851 static xtensa_iclass_internal icache_iclass = {
2853 &icache_operand_list[0]
2856 static xtensa_operand_internal *s8i_operand_list[] = {
2862 static xtensa_iclass_internal s8i_iclass = {
2864 &s8i_operand_list[0]
2867 static xtensa_iclass_internal return_iclass = {
2872 static xtensa_operand_internal *dcache_operand_list[] = {
2877 static xtensa_iclass_internal dcache_iclass = {
2879 &dcache_operand_list[0]
2882 static xtensa_operand_internal *s32i_operand_list[] = {
2888 static xtensa_iclass_internal s32i_iclass = {
2890 &s32i_operand_list[0]
2893 static xtensa_operand_internal *jump_operand_list[] = {
2897 static xtensa_iclass_internal jump_iclass = {
2899 &jump_operand_list[0]
2902 static xtensa_operand_internal *addi_n_operand_list[] = {
2908 static xtensa_iclass_internal addi_n_iclass = {
2910 &addi_n_operand_list[0]
2913 static xtensa_iclass_internal sync_iclass = {
2918 static xtensa_operand_internal *neg_operand_list[] = {
2923 static xtensa_iclass_internal neg_iclass = {
2925 &neg_operand_list[0]
2928 static xtensa_iclass_internal syscall_iclass = {
2933 static xtensa_operand_internal *bsz12_operand_list[] = {
2938 static xtensa_iclass_internal bsz12_iclass = {
2940 &bsz12_operand_list[0]
2943 static xtensa_iclass_internal excw_iclass = {
2948 static xtensa_operand_internal *movi_n_operand_list[] = {
2953 static xtensa_iclass_internal movi_n_iclass = {
2955 &movi_n_operand_list[0]
2958 static xtensa_operand_internal *rtlb_operand_list[] = {
2963 static xtensa_iclass_internal rtlb_iclass = {
2965 &rtlb_operand_list[0]
2968 static xtensa_operand_internal *actl_operand_list[] = {
2973 static xtensa_iclass_internal actl_iclass = {
2975 &actl_operand_list[0]
2978 static xtensa_operand_internal *srli_operand_list[] = {
2984 static xtensa_iclass_internal srli_iclass = {
2986 &srli_operand_list[0]
2989 static xtensa_operand_internal *bsi8b_operand_list[] = {
2995 static xtensa_iclass_internal bsi8b_iclass = {
2997 &bsi8b_operand_list[0]
3000 static xtensa_operand_internal *acts_operand_list[] = {
3005 static xtensa_iclass_internal acts_iclass = {
3007 &acts_operand_list[0]
3010 static xtensa_operand_internal *add_n_operand_list[] = {
3016 static xtensa_iclass_internal add_n_iclass = {
3018 &add_n_operand_list[0]
3021 static xtensa_operand_internal *srai_operand_list[] = {
3027 static xtensa_iclass_internal srai_iclass = {
3029 &srai_operand_list[0]
3032 static xtensa_operand_internal *entry_operand_list[] = {
3037 static xtensa_iclass_internal entry_iclass = {
3039 &entry_operand_list[0]
3042 static xtensa_operand_internal *l32e_operand_list[] = {
3048 static xtensa_iclass_internal l32e_iclass = {
3050 &l32e_operand_list[0]
3053 static xtensa_operand_internal *dpf_operand_list[] = {
3058 static xtensa_iclass_internal dpf_iclass = {
3060 &dpf_operand_list[0]
3063 static xtensa_operand_internal *l32i_operand_list[] = {
3069 static xtensa_iclass_internal l32i_iclass = {
3071 &l32i_operand_list[0]
3074 static xtensa_insnbuf abs_template (void);
3075 static xtensa_insnbuf add_template (void);
3076 static xtensa_insnbuf add_n_template (void);
3077 static xtensa_insnbuf addi_template (void);
3078 static xtensa_insnbuf addi_n_template (void);
3079 static xtensa_insnbuf addmi_template (void);
3080 static xtensa_insnbuf addx2_template (void);
3081 static xtensa_insnbuf addx4_template (void);
3082 static xtensa_insnbuf addx8_template (void);
3083 static xtensa_insnbuf and_template (void);
3084 static xtensa_insnbuf ball_template (void);
3085 static xtensa_insnbuf bany_template (void);
3086 static xtensa_insnbuf bbc_template (void);
3087 static xtensa_insnbuf bbci_template (void);
3088 static xtensa_insnbuf bbs_template (void);
3089 static xtensa_insnbuf bbsi_template (void);
3090 static xtensa_insnbuf beq_template (void);
3091 static xtensa_insnbuf beqi_template (void);
3092 static xtensa_insnbuf beqz_template (void);
3093 static xtensa_insnbuf beqz_n_template (void);
3094 static xtensa_insnbuf bge_template (void);
3095 static xtensa_insnbuf bgei_template (void);
3096 static xtensa_insnbuf bgeu_template (void);
3097 static xtensa_insnbuf bgeui_template (void);
3098 static xtensa_insnbuf bgez_template (void);
3099 static xtensa_insnbuf blt_template (void);
3100 static xtensa_insnbuf blti_template (void);
3101 static xtensa_insnbuf bltu_template (void);
3102 static xtensa_insnbuf bltui_template (void);
3103 static xtensa_insnbuf bltz_template (void);
3104 static xtensa_insnbuf bnall_template (void);
3105 static xtensa_insnbuf bne_template (void);
3106 static xtensa_insnbuf bnei_template (void);
3107 static xtensa_insnbuf bnez_template (void);
3108 static xtensa_insnbuf bnez_n_template (void);
3109 static xtensa_insnbuf bnone_template (void);
3110 static xtensa_insnbuf break_template (void);
3111 static xtensa_insnbuf break_n_template (void);
3112 static xtensa_insnbuf call0_template (void);
3113 static xtensa_insnbuf call12_template (void);
3114 static xtensa_insnbuf call4_template (void);
3115 static xtensa_insnbuf call8_template (void);
3116 static xtensa_insnbuf callx0_template (void);
3117 static xtensa_insnbuf callx12_template (void);
3118 static xtensa_insnbuf callx4_template (void);
3119 static xtensa_insnbuf callx8_template (void);
3120 static xtensa_insnbuf dhi_template (void);
3121 static xtensa_insnbuf dhwb_template (void);
3122 static xtensa_insnbuf dhwbi_template (void);
3123 static xtensa_insnbuf dii_template (void);
3124 static xtensa_insnbuf diwb_template (void);
3125 static xtensa_insnbuf diwbi_template (void);
3126 static xtensa_insnbuf dpfr_template (void);
3127 static xtensa_insnbuf dpfro_template (void);
3128 static xtensa_insnbuf dpfw_template (void);
3129 static xtensa_insnbuf dpfwo_template (void);
3130 static xtensa_insnbuf dsync_template (void);
3131 static xtensa_insnbuf entry_template (void);
3132 static xtensa_insnbuf esync_template (void);
3133 static xtensa_insnbuf excw_template (void);
3134 static xtensa_insnbuf extui_template (void);
3135 static xtensa_insnbuf idtlb_template (void);
3136 static xtensa_insnbuf idtlba_template (void);
3137 static xtensa_insnbuf ihi_template (void);
3138 static xtensa_insnbuf iii_template (void);
3139 static xtensa_insnbuf iitlb_template (void);
3140 static xtensa_insnbuf iitlba_template (void);
3141 static xtensa_insnbuf ipf_template (void);
3142 static xtensa_insnbuf isync_template (void);
3143 static xtensa_insnbuf j_template (void);
3144 static xtensa_insnbuf jx_template (void);
3145 static xtensa_insnbuf l16si_template (void);
3146 static xtensa_insnbuf l16ui_template (void);
3147 static xtensa_insnbuf l32e_template (void);
3148 static xtensa_insnbuf l32i_template (void);
3149 static xtensa_insnbuf l32i_n_template (void);
3150 static xtensa_insnbuf l32r_template (void);
3151 static xtensa_insnbuf l8ui_template (void);
3152 static xtensa_insnbuf ldct_template (void);
3153 static xtensa_insnbuf lict_template (void);
3154 static xtensa_insnbuf licw_template (void);
3155 static xtensa_insnbuf loop_template (void);
3156 static xtensa_insnbuf loopgtz_template (void);
3157 static xtensa_insnbuf loopnez_template (void);
3158 static xtensa_insnbuf memw_template (void);
3159 static xtensa_insnbuf mov_n_template (void);
3160 static xtensa_insnbuf moveqz_template (void);
3161 static xtensa_insnbuf movgez_template (void);
3162 static xtensa_insnbuf movi_template (void);
3163 static xtensa_insnbuf movi_n_template (void);
3164 static xtensa_insnbuf movltz_template (void);
3165 static xtensa_insnbuf movnez_template (void);
3166 static xtensa_insnbuf movsp_template (void);
3167 static xtensa_insnbuf neg_template (void);
3168 static xtensa_insnbuf nop_n_template (void);
3169 static xtensa_insnbuf nsa_template (void);
3170 static xtensa_insnbuf nsau_template (void);
3171 static xtensa_insnbuf or_template (void);
3172 static xtensa_insnbuf pdtlb_template (void);
3173 static xtensa_insnbuf pitlb_template (void);
3174 static xtensa_insnbuf rdtlb0_template (void);
3175 static xtensa_insnbuf rdtlb1_template (void);
3176 static xtensa_insnbuf ret_template (void);
3177 static xtensa_insnbuf ret_n_template (void);
3178 static xtensa_insnbuf retw_template (void);
3179 static xtensa_insnbuf retw_n_template (void);
3180 static xtensa_insnbuf rfde_template (void);
3181 static xtensa_insnbuf rfe_template (void);
3182 static xtensa_insnbuf rfi_template (void);
3183 static xtensa_insnbuf rfwo_template (void);
3184 static xtensa_insnbuf rfwu_template (void);
3185 static xtensa_insnbuf ritlb0_template (void);
3186 static xtensa_insnbuf ritlb1_template (void);
3187 static xtensa_insnbuf rotw_template (void);
3188 static xtensa_insnbuf rsil_template (void);
3189 static xtensa_insnbuf rsr_template (void);
3190 static xtensa_insnbuf rsync_template (void);
3191 static xtensa_insnbuf s16i_template (void);
3192 static xtensa_insnbuf s32e_template (void);
3193 static xtensa_insnbuf s32i_template (void);
3194 static xtensa_insnbuf s32i_n_template (void);
3195 static xtensa_insnbuf s8i_template (void);
3196 static xtensa_insnbuf sdct_template (void);
3197 static xtensa_insnbuf sict_template (void);
3198 static xtensa_insnbuf sicw_template (void);
3199 static xtensa_insnbuf simcall_template (void);
3200 static xtensa_insnbuf sll_template (void);
3201 static xtensa_insnbuf slli_template (void);
3202 static xtensa_insnbuf sra_template (void);
3203 static xtensa_insnbuf srai_template (void);
3204 static xtensa_insnbuf src_template (void);
3205 static xtensa_insnbuf srl_template (void);
3206 static xtensa_insnbuf srli_template (void);
3207 static xtensa_insnbuf ssa8b_template (void);
3208 static xtensa_insnbuf ssa8l_template (void);
3209 static xtensa_insnbuf ssai_template (void);
3210 static xtensa_insnbuf ssl_template (void);
3211 static xtensa_insnbuf ssr_template (void);
3212 static xtensa_insnbuf sub_template (void);
3213 static xtensa_insnbuf subx2_template (void);
3214 static xtensa_insnbuf subx4_template (void);
3215 static xtensa_insnbuf subx8_template (void);
3216 static xtensa_insnbuf syscall_template (void);
3217 static xtensa_insnbuf waiti_template (void);
3218 static xtensa_insnbuf wdtlb_template (void);
3219 static xtensa_insnbuf witlb_template (void);
3220 static xtensa_insnbuf wsr_template (void);
3221 static xtensa_insnbuf xor_template (void);
3222 static xtensa_insnbuf xsr_template (void);
3224 static xtensa_insnbuf
3227 static xtensa_insnbuf_word template[] = { 0x00001006 };
3228 return &template[0];
3231 static xtensa_insnbuf
3234 static xtensa_insnbuf_word template[] = { 0x00000008 };
3235 return &template[0];
3238 static xtensa_insnbuf
3239 add_n_template (void)
3241 static xtensa_insnbuf_word template[] = { 0x00a00000 };
3242 return &template[0];
3245 static xtensa_insnbuf
3246 addi_template (void)
3248 static xtensa_insnbuf_word template[] = { 0x00200c00 };
3249 return &template[0];
3252 static xtensa_insnbuf
3253 addi_n_template (void)
3255 static xtensa_insnbuf_word template[] = { 0x00b00000 };
3256 return &template[0];
3259 static xtensa_insnbuf
3260 addmi_template (void)
3262 static xtensa_insnbuf_word template[] = { 0x00200d00 };
3263 return &template[0];
3266 static xtensa_insnbuf
3267 addx2_template (void)
3269 static xtensa_insnbuf_word template[] = { 0x00000009 };
3270 return &template[0];
3273 static xtensa_insnbuf
3274 addx4_template (void)
3276 static xtensa_insnbuf_word template[] = { 0x0000000a };
3277 return &template[0];
3280 static xtensa_insnbuf
3281 addx8_template (void)
3283 static xtensa_insnbuf_word template[] = { 0x0000000b };
3284 return &template[0];
3287 static xtensa_insnbuf
3290 static xtensa_insnbuf_word template[] = { 0x00000001 };
3291 return &template[0];
3294 static xtensa_insnbuf
3295 ball_template (void)
3297 static xtensa_insnbuf_word template[] = { 0x00700400 };
3298 return &template[0];
3301 static xtensa_insnbuf
3302 bany_template (void)
3304 static xtensa_insnbuf_word template[] = { 0x00700800 };
3305 return &template[0];
3308 static xtensa_insnbuf
3311 static xtensa_insnbuf_word template[] = { 0x00700500 };
3312 return &template[0];
3315 static xtensa_insnbuf
3316 bbci_template (void)
3318 static xtensa_insnbuf_word template[] = { 0x00700600 };
3319 return &template[0];
3322 static xtensa_insnbuf
3325 static xtensa_insnbuf_word template[] = { 0x00700d00 };
3326 return &template[0];
3329 static xtensa_insnbuf
3330 bbsi_template (void)
3332 static xtensa_insnbuf_word template[] = { 0x00700e00 };
3333 return &template[0];
3336 static xtensa_insnbuf
3339 static xtensa_insnbuf_word template[] = { 0x00700100 };
3340 return &template[0];
3343 static xtensa_insnbuf
3344 beqi_template (void)
3346 static xtensa_insnbuf_word template[] = { 0x00680000 };
3347 return &template[0];
3350 static xtensa_insnbuf
3351 beqz_template (void)
3353 static xtensa_insnbuf_word template[] = { 0x00640000 };
3354 return &template[0];
3357 static xtensa_insnbuf
3358 beqz_n_template (void)
3360 static xtensa_insnbuf_word template[] = { 0x00c80000 };
3361 return &template[0];
3364 static xtensa_insnbuf
3367 static xtensa_insnbuf_word template[] = { 0x00700a00 };
3368 return &template[0];
3371 static xtensa_insnbuf
3372 bgei_template (void)
3374 static xtensa_insnbuf_word template[] = { 0x006b0000 };
3375 return &template[0];
3378 static xtensa_insnbuf
3379 bgeu_template (void)
3381 static xtensa_insnbuf_word template[] = { 0x00700b00 };
3382 return &template[0];
3385 static xtensa_insnbuf
3386 bgeui_template (void)
3388 static xtensa_insnbuf_word template[] = { 0x006f0000 };
3389 return &template[0];
3392 static xtensa_insnbuf
3393 bgez_template (void)
3395 static xtensa_insnbuf_word template[] = { 0x00670000 };
3396 return &template[0];
3399 static xtensa_insnbuf
3402 static xtensa_insnbuf_word template[] = { 0x00700200 };
3403 return &template[0];
3406 static xtensa_insnbuf
3407 blti_template (void)
3409 static xtensa_insnbuf_word template[] = { 0x006a0000 };
3410 return &template[0];
3413 static xtensa_insnbuf
3414 bltu_template (void)
3416 static xtensa_insnbuf_word template[] = { 0x00700300 };
3417 return &template[0];
3420 static xtensa_insnbuf
3421 bltui_template (void)
3423 static xtensa_insnbuf_word template[] = { 0x006e0000 };
3424 return &template[0];
3427 static xtensa_insnbuf
3428 bltz_template (void)
3430 static xtensa_insnbuf_word template[] = { 0x00660000 };
3431 return &template[0];
3434 static xtensa_insnbuf
3435 bnall_template (void)
3437 static xtensa_insnbuf_word template[] = { 0x00700c00 };
3438 return &template[0];
3441 static xtensa_insnbuf
3444 static xtensa_insnbuf_word template[] = { 0x00700900 };
3445 return &template[0];
3448 static xtensa_insnbuf
3449 bnei_template (void)
3451 static xtensa_insnbuf_word template[] = { 0x00690000 };
3452 return &template[0];
3455 static xtensa_insnbuf
3456 bnez_template (void)
3458 static xtensa_insnbuf_word template[] = { 0x00650000 };
3459 return &template[0];
3462 static xtensa_insnbuf
3463 bnez_n_template (void)
3465 static xtensa_insnbuf_word template[] = { 0x00cc0000 };
3466 return &template[0];
3469 static xtensa_insnbuf
3470 bnone_template (void)
3472 static xtensa_insnbuf_word template[] = { 0x00700000 };
3473 return &template[0];
3476 static xtensa_insnbuf
3477 break_template (void)
3479 static xtensa_insnbuf_word template[] = { 0x00000400 };
3480 return &template[0];
3483 static xtensa_insnbuf
3484 break_n_template (void)
3486 static xtensa_insnbuf_word template[] = { 0x00d20f00 };
3487 return &template[0];
3490 static xtensa_insnbuf
3491 call0_template (void)
3493 static xtensa_insnbuf_word template[] = { 0x00500000 };
3494 return &template[0];
3497 static xtensa_insnbuf
3498 call12_template (void)
3500 static xtensa_insnbuf_word template[] = { 0x005c0000 };
3501 return &template[0];
3504 static xtensa_insnbuf
3505 call4_template (void)
3507 static xtensa_insnbuf_word template[] = { 0x00540000 };
3508 return &template[0];
3511 static xtensa_insnbuf
3512 call8_template (void)
3514 static xtensa_insnbuf_word template[] = { 0x00580000 };
3515 return &template[0];
3518 static xtensa_insnbuf
3519 callx0_template (void)
3521 static xtensa_insnbuf_word template[] = { 0x00030000 };
3522 return &template[0];
3525 static xtensa_insnbuf
3526 callx12_template (void)
3528 static xtensa_insnbuf_word template[] = { 0x000f0000 };
3529 return &template[0];
3532 static xtensa_insnbuf
3533 callx4_template (void)
3535 static xtensa_insnbuf_word template[] = { 0x00070000 };
3536 return &template[0];
3539 static xtensa_insnbuf
3540 callx8_template (void)
3542 static xtensa_insnbuf_word template[] = { 0x000b0000 };
3543 return &template[0];
3546 static xtensa_insnbuf
3549 static xtensa_insnbuf_word template[] = { 0x00260700 };
3550 return &template[0];
3553 static xtensa_insnbuf
3554 dhwb_template (void)
3556 static xtensa_insnbuf_word template[] = { 0x00240700 };
3557 return &template[0];
3560 static xtensa_insnbuf
3561 dhwbi_template (void)
3563 static xtensa_insnbuf_word template[] = { 0x00250700 };
3564 return &template[0];
3567 static xtensa_insnbuf
3570 static xtensa_insnbuf_word template[] = { 0x00270700 };
3571 return &template[0];
3574 static xtensa_insnbuf
3575 diwb_template (void)
3577 static xtensa_insnbuf_word template[] = { 0x00280740 };
3578 return &template[0];
3581 static xtensa_insnbuf
3582 diwbi_template (void)
3584 static xtensa_insnbuf_word template[] = { 0x00280750 };
3585 return &template[0];
3588 static xtensa_insnbuf
3589 dpfr_template (void)
3591 static xtensa_insnbuf_word template[] = { 0x00200700 };
3592 return &template[0];
3595 static xtensa_insnbuf
3596 dpfro_template (void)
3598 static xtensa_insnbuf_word template[] = { 0x00220700 };
3599 return &template[0];
3602 static xtensa_insnbuf
3603 dpfw_template (void)
3605 static xtensa_insnbuf_word template[] = { 0x00210700 };
3606 return &template[0];
3609 static xtensa_insnbuf
3610 dpfwo_template (void)
3612 static xtensa_insnbuf_word template[] = { 0x00230700 };
3613 return &template[0];
3616 static xtensa_insnbuf
3617 dsync_template (void)
3619 static xtensa_insnbuf_word template[] = { 0x00030200 };
3620 return &template[0];
3623 static xtensa_insnbuf
3624 entry_template (void)
3626 static xtensa_insnbuf_word template[] = { 0x006c0000 };
3627 return &template[0];
3630 static xtensa_insnbuf
3631 esync_template (void)
3633 static xtensa_insnbuf_word template[] = { 0x00020200 };
3634 return &template[0];
3637 static xtensa_insnbuf
3638 excw_template (void)
3640 static xtensa_insnbuf_word template[] = { 0x00080200 };
3641 return &template[0];
3644 static xtensa_insnbuf
3645 extui_template (void)
3647 static xtensa_insnbuf_word template[] = { 0x00000040 };
3648 return &template[0];
3651 static xtensa_insnbuf
3652 idtlb_template (void)
3654 static xtensa_insnbuf_word template[] = { 0x00000c05 };
3655 return &template[0];
3658 static xtensa_insnbuf
3659 idtlba_template (void)
3661 static xtensa_insnbuf_word template[] = { 0x00000805 };
3662 return &template[0];
3665 static xtensa_insnbuf
3668 static xtensa_insnbuf_word template[] = { 0x002e0700 };
3669 return &template[0];
3672 static xtensa_insnbuf
3675 static xtensa_insnbuf_word template[] = { 0x002f0700 };
3676 return &template[0];
3679 static xtensa_insnbuf
3680 iitlb_template (void)
3682 static xtensa_insnbuf_word template[] = { 0x00000405 };
3683 return &template[0];
3686 static xtensa_insnbuf
3687 iitlba_template (void)
3689 static xtensa_insnbuf_word template[] = { 0x00000005 };
3690 return &template[0];
3693 static xtensa_insnbuf
3696 static xtensa_insnbuf_word template[] = { 0x002c0700 };
3697 return &template[0];
3700 static xtensa_insnbuf
3701 isync_template (void)
3703 static xtensa_insnbuf_word template[] = { 0x00000200 };
3704 return &template[0];
3707 static xtensa_insnbuf
3710 static xtensa_insnbuf_word template[] = { 0x00600000 };
3711 return &template[0];
3714 static xtensa_insnbuf
3717 static xtensa_insnbuf_word template[] = { 0x000a0000 };
3718 return &template[0];
3721 static xtensa_insnbuf
3722 l16si_template (void)
3724 static xtensa_insnbuf_word template[] = { 0x00200900 };
3725 return &template[0];
3728 static xtensa_insnbuf
3729 l16ui_template (void)
3731 static xtensa_insnbuf_word template[] = { 0x00200100 };
3732 return &template[0];
3735 static xtensa_insnbuf
3736 l32e_template (void)
3738 static xtensa_insnbuf_word template[] = { 0x00000090 };
3739 return &template[0];
3742 static xtensa_insnbuf
3743 l32i_template (void)
3745 static xtensa_insnbuf_word template[] = { 0x00200200 };
3746 return &template[0];
3749 static xtensa_insnbuf
3750 l32i_n_template (void)
3752 static xtensa_insnbuf_word template[] = { 0x00800000 };
3753 return &template[0];
3756 static xtensa_insnbuf
3757 l32r_template (void)
3759 static xtensa_insnbuf_word template[] = { 0x00100000 };
3760 return &template[0];
3763 static xtensa_insnbuf
3764 l8ui_template (void)
3766 static xtensa_insnbuf_word template[] = { 0x00200000 };
3767 return &template[0];
3770 static xtensa_insnbuf
3771 ldct_template (void)
3773 static xtensa_insnbuf_word template[] = { 0x0000081f };
3774 return &template[0];
3777 static xtensa_insnbuf
3778 lict_template (void)
3780 static xtensa_insnbuf_word template[] = { 0x0000001f };
3781 return &template[0];
3784 static xtensa_insnbuf
3785 licw_template (void)
3787 static xtensa_insnbuf_word template[] = { 0x0000021f };
3788 return &template[0];
3791 static xtensa_insnbuf
3792 loop_template (void)
3794 static xtensa_insnbuf_word template[] = { 0x006d0800 };
3795 return &template[0];
3798 static xtensa_insnbuf
3799 loopgtz_template (void)
3801 static xtensa_insnbuf_word template[] = { 0x006d0a00 };
3802 return &template[0];
3805 static xtensa_insnbuf
3806 loopnez_template (void)
3808 static xtensa_insnbuf_word template[] = { 0x006d0900 };
3809 return &template[0];
3812 static xtensa_insnbuf
3813 memw_template (void)
3815 static xtensa_insnbuf_word template[] = { 0x000c0200 };
3816 return &template[0];
3819 static xtensa_insnbuf
3820 mov_n_template (void)
3822 static xtensa_insnbuf_word template[] = { 0x00d00000 };
3823 return &template[0];
3826 static xtensa_insnbuf
3827 moveqz_template (void)
3829 static xtensa_insnbuf_word template[] = { 0x00000038 };
3830 return &template[0];
3833 static xtensa_insnbuf
3834 movgez_template (void)
3836 static xtensa_insnbuf_word template[] = { 0x0000003b };
3837 return &template[0];
3840 static xtensa_insnbuf
3841 movi_template (void)
3843 static xtensa_insnbuf_word template[] = { 0x00200a00 };
3844 return &template[0];
3847 static xtensa_insnbuf
3848 movi_n_template (void)
3850 static xtensa_insnbuf_word template[] = { 0x00c00000 };
3851 return &template[0];
3854 static xtensa_insnbuf
3855 movltz_template (void)
3857 static xtensa_insnbuf_word template[] = { 0x0000003a };
3858 return &template[0];
3861 static xtensa_insnbuf
3862 movnez_template (void)
3864 static xtensa_insnbuf_word template[] = { 0x00000039 };
3865 return &template[0];
3868 static xtensa_insnbuf
3869 movsp_template (void)
3871 static xtensa_insnbuf_word template[] = { 0x00000100 };
3872 return &template[0];
3875 static xtensa_insnbuf
3878 static xtensa_insnbuf_word template[] = { 0x00000006 };
3879 return &template[0];
3882 static xtensa_insnbuf
3883 nop_n_template (void)
3885 static xtensa_insnbuf_word template[] = { 0x00d30f00 };
3886 return &template[0];
3889 static xtensa_insnbuf
3892 static xtensa_insnbuf_word template[] = { 0x00000e04 };
3893 return &template[0];
3896 static xtensa_insnbuf
3897 nsau_template (void)
3899 static xtensa_insnbuf_word template[] = { 0x00000f04 };
3900 return &template[0];
3903 static xtensa_insnbuf
3906 static xtensa_insnbuf_word template[] = { 0x00000002 };
3907 return &template[0];
3910 static xtensa_insnbuf
3911 pdtlb_template (void)
3913 static xtensa_insnbuf_word template[] = { 0x00000d05 };
3914 return &template[0];
3917 static xtensa_insnbuf
3918 pitlb_template (void)
3920 static xtensa_insnbuf_word template[] = { 0x00000505 };
3921 return &template[0];
3924 static xtensa_insnbuf
3925 rdtlb0_template (void)
3927 static xtensa_insnbuf_word template[] = { 0x00000b05 };
3928 return &template[0];
3931 static xtensa_insnbuf
3932 rdtlb1_template (void)
3934 static xtensa_insnbuf_word template[] = { 0x00000f05 };
3935 return &template[0];
3938 static xtensa_insnbuf
3941 static xtensa_insnbuf_word template[] = { 0x00020000 };
3942 return &template[0];
3945 static xtensa_insnbuf
3946 ret_n_template (void)
3948 static xtensa_insnbuf_word template[] = { 0x00d00f00 };
3949 return &template[0];
3952 static xtensa_insnbuf
3953 retw_template (void)
3955 static xtensa_insnbuf_word template[] = { 0x00060000 };
3956 return &template[0];
3959 static xtensa_insnbuf
3960 retw_n_template (void)
3962 static xtensa_insnbuf_word template[] = { 0x00d10f00 };
3963 return &template[0];
3966 static xtensa_insnbuf
3967 rfde_template (void)
3969 static xtensa_insnbuf_word template[] = { 0x00002300 };
3970 return &template[0];
3973 static xtensa_insnbuf
3976 static xtensa_insnbuf_word template[] = { 0x00000300 };
3977 return &template[0];
3980 static xtensa_insnbuf
3983 static xtensa_insnbuf_word template[] = { 0x00010300 };
3984 return &template[0];
3987 static xtensa_insnbuf
3988 rfwo_template (void)
3990 static xtensa_insnbuf_word template[] = { 0x00004300 };
3991 return &template[0];
3994 static xtensa_insnbuf
3995 rfwu_template (void)
3997 static xtensa_insnbuf_word template[] = { 0x00005300 };
3998 return &template[0];
4001 static xtensa_insnbuf
4002 ritlb0_template (void)
4004 static xtensa_insnbuf_word template[] = { 0x00000305 };
4005 return &template[0];
4008 static xtensa_insnbuf
4009 ritlb1_template (void)
4011 static xtensa_insnbuf_word template[] = { 0x00000705 };
4012 return &template[0];
4015 static xtensa_insnbuf
4016 rotw_template (void)
4018 static xtensa_insnbuf_word template[] = { 0x00000804 };
4019 return &template[0];
4022 static xtensa_insnbuf
4023 rsil_template (void)
4025 static xtensa_insnbuf_word template[] = { 0x00000600 };
4026 return &template[0];
4029 static xtensa_insnbuf
4032 static xtensa_insnbuf_word template[] = { 0x00000030 };
4033 return &template[0];
4036 static xtensa_insnbuf
4037 rsync_template (void)
4039 static xtensa_insnbuf_word template[] = { 0x00010200 };
4040 return &template[0];
4043 static xtensa_insnbuf
4044 s16i_template (void)
4046 static xtensa_insnbuf_word template[] = { 0x00200500 };
4047 return &template[0];
4050 static xtensa_insnbuf
4051 s32e_template (void)
4053 static xtensa_insnbuf_word template[] = { 0x00000094 };
4054 return &template[0];
4057 static xtensa_insnbuf
4058 s32i_template (void)
4060 static xtensa_insnbuf_word template[] = { 0x00200600 };
4061 return &template[0];
4064 static xtensa_insnbuf
4065 s32i_n_template (void)
4067 static xtensa_insnbuf_word template[] = { 0x00900000 };
4068 return &template[0];
4071 static xtensa_insnbuf
4074 static xtensa_insnbuf_word template[] = { 0x00200400 };
4075 return &template[0];
4078 static xtensa_insnbuf
4079 sdct_template (void)
4081 static xtensa_insnbuf_word template[] = { 0x0000091f };
4082 return &template[0];
4085 static xtensa_insnbuf
4086 sict_template (void)
4088 static xtensa_insnbuf_word template[] = { 0x0000011f };
4089 return &template[0];
4092 static xtensa_insnbuf
4093 sicw_template (void)
4095 static xtensa_insnbuf_word template[] = { 0x0000031f };
4096 return &template[0];
4099 static xtensa_insnbuf
4100 simcall_template (void)
4102 static xtensa_insnbuf_word template[] = { 0x00001500 };
4103 return &template[0];
4106 static xtensa_insnbuf
4109 static xtensa_insnbuf_word template[] = { 0x0000001a };
4110 return &template[0];
4113 static xtensa_insnbuf
4114 slli_template (void)
4116 static xtensa_insnbuf_word template[] = { 0x00000010 };
4117 return &template[0];
4120 static xtensa_insnbuf
4123 static xtensa_insnbuf_word template[] = { 0x0000001b };
4124 return &template[0];
4127 static xtensa_insnbuf
4128 srai_template (void)
4130 static xtensa_insnbuf_word template[] = { 0x00000012 };
4131 return &template[0];
4134 static xtensa_insnbuf
4137 static xtensa_insnbuf_word template[] = { 0x00000018 };
4138 return &template[0];
4141 static xtensa_insnbuf
4144 static xtensa_insnbuf_word template[] = { 0x00000019 };
4145 return &template[0];
4148 static xtensa_insnbuf
4149 srli_template (void)
4151 static xtensa_insnbuf_word template[] = { 0x00000014 };
4152 return &template[0];
4155 static xtensa_insnbuf
4156 ssa8b_template (void)
4158 static xtensa_insnbuf_word template[] = { 0x00000304 };
4159 return &template[0];
4162 static xtensa_insnbuf
4163 ssa8l_template (void)
4165 static xtensa_insnbuf_word template[] = { 0x00000204 };
4166 return &template[0];
4169 static xtensa_insnbuf
4170 ssai_template (void)
4172 static xtensa_insnbuf_word template[] = { 0x00000404 };
4173 return &template[0];
4176 static xtensa_insnbuf
4179 static xtensa_insnbuf_word template[] = { 0x00000104 };
4180 return &template[0];
4183 static xtensa_insnbuf
4186 static xtensa_insnbuf_word template[] = { 0x00000004 };
4187 return &template[0];
4190 static xtensa_insnbuf
4193 static xtensa_insnbuf_word template[] = { 0x0000000c };
4194 return &template[0];
4197 static xtensa_insnbuf
4198 subx2_template (void)
4200 static xtensa_insnbuf_word template[] = { 0x0000000d };
4201 return &template[0];
4204 static xtensa_insnbuf
4205 subx4_template (void)
4207 static xtensa_insnbuf_word template[] = { 0x0000000e };
4208 return &template[0];
4211 static xtensa_insnbuf
4212 subx8_template (void)
4214 static xtensa_insnbuf_word template[] = { 0x0000000f };
4215 return &template[0];
4218 static xtensa_insnbuf
4219 syscall_template (void)
4221 static xtensa_insnbuf_word template[] = { 0x00000500 };
4222 return &template[0];
4225 static xtensa_insnbuf
4226 waiti_template (void)
4228 static xtensa_insnbuf_word template[] = { 0x00000700 };
4229 return &template[0];
4232 static xtensa_insnbuf
4233 wdtlb_template (void)
4235 static xtensa_insnbuf_word template[] = { 0x00000e05 };
4236 return &template[0];
4239 static xtensa_insnbuf
4240 witlb_template (void)
4242 static xtensa_insnbuf_word template[] = { 0x00000605 };
4243 return &template[0];
4246 static xtensa_insnbuf
4249 static xtensa_insnbuf_word template[] = { 0x00000031 };
4250 return &template[0];
4253 static xtensa_insnbuf
4256 static xtensa_insnbuf_word template[] = { 0x00000003 };
4257 return &template[0];
4260 static xtensa_insnbuf
4263 static xtensa_insnbuf_word template[] = { 0x00000016 };
4264 return &template[0];
4267 static xtensa_opcode_internal abs_opcode = {
4274 static xtensa_opcode_internal add_opcode = {
4281 static xtensa_opcode_internal add_n_opcode = {
4288 static xtensa_opcode_internal addi_opcode = {
4295 static xtensa_opcode_internal addi_n_opcode = {
4302 static xtensa_opcode_internal addmi_opcode = {
4309 static xtensa_opcode_internal addx2_opcode = {
4316 static xtensa_opcode_internal addx4_opcode = {
4323 static xtensa_opcode_internal addx8_opcode = {
4330 static xtensa_opcode_internal and_opcode = {
4337 static xtensa_opcode_internal ball_opcode = {
4344 static xtensa_opcode_internal bany_opcode = {
4351 static xtensa_opcode_internal bbc_opcode = {
4358 static xtensa_opcode_internal bbci_opcode = {
4365 static xtensa_opcode_internal bbs_opcode = {
4372 static xtensa_opcode_internal bbsi_opcode = {
4379 static xtensa_opcode_internal beq_opcode = {
4386 static xtensa_opcode_internal beqi_opcode = {
4393 static xtensa_opcode_internal beqz_opcode = {
4400 static xtensa_opcode_internal beqz_n_opcode = {
4407 static xtensa_opcode_internal bge_opcode = {
4414 static xtensa_opcode_internal bgei_opcode = {
4421 static xtensa_opcode_internal bgeu_opcode = {
4428 static xtensa_opcode_internal bgeui_opcode = {
4435 static xtensa_opcode_internal bgez_opcode = {
4442 static xtensa_opcode_internal blt_opcode = {
4449 static xtensa_opcode_internal blti_opcode = {
4456 static xtensa_opcode_internal bltu_opcode = {
4463 static xtensa_opcode_internal bltui_opcode = {
4470 static xtensa_opcode_internal bltz_opcode = {
4477 static xtensa_opcode_internal bnall_opcode = {
4484 static xtensa_opcode_internal bne_opcode = {
4491 static xtensa_opcode_internal bnei_opcode = {
4498 static xtensa_opcode_internal bnez_opcode = {
4505 static xtensa_opcode_internal bnez_n_opcode = {
4512 static xtensa_opcode_internal bnone_opcode = {
4519 static xtensa_opcode_internal break_opcode = {
4526 static xtensa_opcode_internal break_n_opcode = {
4533 static xtensa_opcode_internal call0_opcode = {
4540 static xtensa_opcode_internal call12_opcode = {
4547 static xtensa_opcode_internal call4_opcode = {
4554 static xtensa_opcode_internal call8_opcode = {
4561 static xtensa_opcode_internal callx0_opcode = {
4568 static xtensa_opcode_internal callx12_opcode = {
4575 static xtensa_opcode_internal callx4_opcode = {
4582 static xtensa_opcode_internal callx8_opcode = {
4589 static xtensa_opcode_internal dhi_opcode = {
4596 static xtensa_opcode_internal dhwb_opcode = {
4603 static xtensa_opcode_internal dhwbi_opcode = {
4610 static xtensa_opcode_internal dii_opcode = {
4617 static xtensa_opcode_internal diwb_opcode = {
4624 static xtensa_opcode_internal diwbi_opcode = {
4631 static xtensa_opcode_internal dpfr_opcode = {
4638 static xtensa_opcode_internal dpfro_opcode = {
4645 static xtensa_opcode_internal dpfw_opcode = {
4652 static xtensa_opcode_internal dpfwo_opcode = {
4659 static xtensa_opcode_internal dsync_opcode = {
4666 static xtensa_opcode_internal entry_opcode = {
4673 static xtensa_opcode_internal esync_opcode = {
4680 static xtensa_opcode_internal excw_opcode = {
4687 static xtensa_opcode_internal extui_opcode = {
4694 static xtensa_opcode_internal idtlb_opcode = {
4701 static xtensa_opcode_internal idtlba_opcode = {
4708 static xtensa_opcode_internal ihi_opcode = {
4715 static xtensa_opcode_internal iii_opcode = {
4722 static xtensa_opcode_internal iitlb_opcode = {
4729 static xtensa_opcode_internal iitlba_opcode = {
4736 static xtensa_opcode_internal ipf_opcode = {
4743 static xtensa_opcode_internal isync_opcode = {
4750 static xtensa_opcode_internal j_opcode = {
4757 static xtensa_opcode_internal jx_opcode = {
4764 static xtensa_opcode_internal l16si_opcode = {
4771 static xtensa_opcode_internal l16ui_opcode = {
4778 static xtensa_opcode_internal l32e_opcode = {
4785 static xtensa_opcode_internal l32i_opcode = {
4792 static xtensa_opcode_internal l32i_n_opcode = {
4799 static xtensa_opcode_internal l32r_opcode = {
4806 static xtensa_opcode_internal l8ui_opcode = {
4813 static xtensa_opcode_internal ldct_opcode = {
4820 static xtensa_opcode_internal lict_opcode = {
4827 static xtensa_opcode_internal licw_opcode = {
4834 static xtensa_opcode_internal loop_opcode = {
4841 static xtensa_opcode_internal loopgtz_opcode = {
4848 static xtensa_opcode_internal loopnez_opcode = {
4855 static xtensa_opcode_internal memw_opcode = {
4862 static xtensa_opcode_internal mov_n_opcode = {
4869 static xtensa_opcode_internal moveqz_opcode = {
4876 static xtensa_opcode_internal movgez_opcode = {
4883 static xtensa_opcode_internal movi_opcode = {
4890 static xtensa_opcode_internal movi_n_opcode = {
4897 static xtensa_opcode_internal movltz_opcode = {
4904 static xtensa_opcode_internal movnez_opcode = {
4911 static xtensa_opcode_internal movsp_opcode = {
4918 static xtensa_opcode_internal neg_opcode = {
4925 static xtensa_opcode_internal nop_n_opcode = {
4932 static xtensa_opcode_internal nsa_opcode = {
4939 static xtensa_opcode_internal nsau_opcode = {
4946 static xtensa_opcode_internal or_opcode = {
4953 static xtensa_opcode_internal pdtlb_opcode = {
4960 static xtensa_opcode_internal pitlb_opcode = {
4967 static xtensa_opcode_internal rdtlb0_opcode = {
4974 static xtensa_opcode_internal rdtlb1_opcode = {
4981 static xtensa_opcode_internal ret_opcode = {
4988 static xtensa_opcode_internal ret_n_opcode = {
4995 static xtensa_opcode_internal retw_opcode = {
5002 static xtensa_opcode_internal retw_n_opcode = {
5009 static xtensa_opcode_internal rfde_opcode = {
5016 static xtensa_opcode_internal rfe_opcode = {
5023 static xtensa_opcode_internal rfi_opcode = {
5030 static xtensa_opcode_internal rfwo_opcode = {
5037 static xtensa_opcode_internal rfwu_opcode = {
5044 static xtensa_opcode_internal ritlb0_opcode = {
5051 static xtensa_opcode_internal ritlb1_opcode = {
5058 static xtensa_opcode_internal rotw_opcode = {
5065 static xtensa_opcode_internal rsil_opcode = {
5072 static xtensa_opcode_internal rsr_opcode = {
5079 static xtensa_opcode_internal rsync_opcode = {
5086 static xtensa_opcode_internal s16i_opcode = {
5093 static xtensa_opcode_internal s32e_opcode = {
5100 static xtensa_opcode_internal s32i_opcode = {
5107 static xtensa_opcode_internal s32i_n_opcode = {
5114 static xtensa_opcode_internal s8i_opcode = {
5121 static xtensa_opcode_internal sdct_opcode = {
5128 static xtensa_opcode_internal sict_opcode = {
5135 static xtensa_opcode_internal sicw_opcode = {
5142 static xtensa_opcode_internal simcall_opcode = {
5149 static xtensa_opcode_internal sll_opcode = {
5156 static xtensa_opcode_internal slli_opcode = {
5163 static xtensa_opcode_internal sra_opcode = {
5170 static xtensa_opcode_internal srai_opcode = {
5177 static xtensa_opcode_internal src_opcode = {
5184 static xtensa_opcode_internal srl_opcode = {
5191 static xtensa_opcode_internal srli_opcode = {
5198 static xtensa_opcode_internal ssa8b_opcode = {
5205 static xtensa_opcode_internal ssa8l_opcode = {
5212 static xtensa_opcode_internal ssai_opcode = {
5219 static xtensa_opcode_internal ssl_opcode = {
5226 static xtensa_opcode_internal ssr_opcode = {
5233 static xtensa_opcode_internal sub_opcode = {
5240 static xtensa_opcode_internal subx2_opcode = {
5247 static xtensa_opcode_internal subx4_opcode = {
5254 static xtensa_opcode_internal subx8_opcode = {
5261 static xtensa_opcode_internal syscall_opcode = {
5268 static xtensa_opcode_internal waiti_opcode = {
5275 static xtensa_opcode_internal wdtlb_opcode = {
5282 static xtensa_opcode_internal witlb_opcode = {
5289 static xtensa_opcode_internal wsr_opcode = {
5296 static xtensa_opcode_internal xor_opcode = {
5303 static xtensa_opcode_internal xsr_opcode = {
5310 static xtensa_opcode_internal * opcodes[149] = {
5462 xtensa_opcode_internal **
5469 get_num_opcodes (void)
5474 #define xtensa_abs_op 0
5475 #define xtensa_add_op 1
5476 #define xtensa_add_n_op 2
5477 #define xtensa_addi_op 3
5478 #define xtensa_addi_n_op 4
5479 #define xtensa_addmi_op 5
5480 #define xtensa_addx2_op 6
5481 #define xtensa_addx4_op 7
5482 #define xtensa_addx8_op 8
5483 #define xtensa_and_op 9
5484 #define xtensa_ball_op 10
5485 #define xtensa_bany_op 11
5486 #define xtensa_bbc_op 12
5487 #define xtensa_bbci_op 13
5488 #define xtensa_bbs_op 14
5489 #define xtensa_bbsi_op 15
5490 #define xtensa_beq_op 16
5491 #define xtensa_beqi_op 17
5492 #define xtensa_beqz_op 18
5493 #define xtensa_beqz_n_op 19
5494 #define xtensa_bge_op 20
5495 #define xtensa_bgei_op 21
5496 #define xtensa_bgeu_op 22
5497 #define xtensa_bgeui_op 23
5498 #define xtensa_bgez_op 24
5499 #define xtensa_blt_op 25
5500 #define xtensa_blti_op 26
5501 #define xtensa_bltu_op 27
5502 #define xtensa_bltui_op 28
5503 #define xtensa_bltz_op 29
5504 #define xtensa_bnall_op 30
5505 #define xtensa_bne_op 31
5506 #define xtensa_bnei_op 32
5507 #define xtensa_bnez_op 33
5508 #define xtensa_bnez_n_op 34
5509 #define xtensa_bnone_op 35
5510 #define xtensa_break_op 36
5511 #define xtensa_break_n_op 37
5512 #define xtensa_call0_op 38
5513 #define xtensa_call12_op 39
5514 #define xtensa_call4_op 40
5515 #define xtensa_call8_op 41
5516 #define xtensa_callx0_op 42
5517 #define xtensa_callx12_op 43
5518 #define xtensa_callx4_op 44
5519 #define xtensa_callx8_op 45
5520 #define xtensa_dhi_op 46
5521 #define xtensa_dhwb_op 47
5522 #define xtensa_dhwbi_op 48
5523 #define xtensa_dii_op 49
5524 #define xtensa_diwb_op 50
5525 #define xtensa_diwbi_op 51
5526 #define xtensa_dpfr_op 52
5527 #define xtensa_dpfro_op 53
5528 #define xtensa_dpfw_op 54
5529 #define xtensa_dpfwo_op 55
5530 #define xtensa_dsync_op 56
5531 #define xtensa_entry_op 57
5532 #define xtensa_esync_op 58
5533 #define xtensa_excw_op 59
5534 #define xtensa_extui_op 60
5535 #define xtensa_idtlb_op 61
5536 #define xtensa_idtlba_op 62
5537 #define xtensa_ihi_op 63
5538 #define xtensa_iii_op 64
5539 #define xtensa_iitlb_op 65
5540 #define xtensa_iitlba_op 66
5541 #define xtensa_ipf_op 67
5542 #define xtensa_isync_op 68
5543 #define xtensa_j_op 69
5544 #define xtensa_jx_op 70
5545 #define xtensa_l16si_op 71
5546 #define xtensa_l16ui_op 72
5547 #define xtensa_l32e_op 73
5548 #define xtensa_l32i_op 74
5549 #define xtensa_l32i_n_op 75
5550 #define xtensa_l32r_op 76
5551 #define xtensa_l8ui_op 77
5552 #define xtensa_ldct_op 78
5553 #define xtensa_lict_op 79
5554 #define xtensa_licw_op 80
5555 #define xtensa_loop_op 81
5556 #define xtensa_loopgtz_op 82
5557 #define xtensa_loopnez_op 83
5558 #define xtensa_memw_op 84
5559 #define xtensa_mov_n_op 85
5560 #define xtensa_moveqz_op 86
5561 #define xtensa_movgez_op 87
5562 #define xtensa_movi_op 88
5563 #define xtensa_movi_n_op 89
5564 #define xtensa_movltz_op 90
5565 #define xtensa_movnez_op 91
5566 #define xtensa_movsp_op 92
5567 #define xtensa_neg_op 93
5568 #define xtensa_nop_n_op 94
5569 #define xtensa_nsa_op 95
5570 #define xtensa_nsau_op 96
5571 #define xtensa_or_op 97
5572 #define xtensa_pdtlb_op 98
5573 #define xtensa_pitlb_op 99
5574 #define xtensa_rdtlb0_op 100
5575 #define xtensa_rdtlb1_op 101
5576 #define xtensa_ret_op 102
5577 #define xtensa_ret_n_op 103
5578 #define xtensa_retw_op 104
5579 #define xtensa_retw_n_op 105
5580 #define xtensa_rfde_op 106
5581 #define xtensa_rfe_op 107
5582 #define xtensa_rfi_op 108
5583 #define xtensa_rfwo_op 109
5584 #define xtensa_rfwu_op 110
5585 #define xtensa_ritlb0_op 111
5586 #define xtensa_ritlb1_op 112
5587 #define xtensa_rotw_op 113
5588 #define xtensa_rsil_op 114
5589 #define xtensa_rsr_op 115
5590 #define xtensa_rsync_op 116
5591 #define xtensa_s16i_op 117
5592 #define xtensa_s32e_op 118
5593 #define xtensa_s32i_op 119
5594 #define xtensa_s32i_n_op 120
5595 #define xtensa_s8i_op 121
5596 #define xtensa_sdct_op 122
5597 #define xtensa_sict_op 123
5598 #define xtensa_sicw_op 124
5599 #define xtensa_simcall_op 125
5600 #define xtensa_sll_op 126
5601 #define xtensa_slli_op 127
5602 #define xtensa_sra_op 128
5603 #define xtensa_srai_op 129
5604 #define xtensa_src_op 130
5605 #define xtensa_srl_op 131
5606 #define xtensa_srli_op 132
5607 #define xtensa_ssa8b_op 133
5608 #define xtensa_ssa8l_op 134
5609 #define xtensa_ssai_op 135
5610 #define xtensa_ssl_op 136
5611 #define xtensa_ssr_op 137
5612 #define xtensa_sub_op 138
5613 #define xtensa_subx2_op 139
5614 #define xtensa_subx4_op 140
5615 #define xtensa_subx8_op 141
5616 #define xtensa_syscall_op 142
5617 #define xtensa_waiti_op 143
5618 #define xtensa_wdtlb_op 144
5619 #define xtensa_witlb_op 145
5620 #define xtensa_wsr_op 146
5621 #define xtensa_xor_op 147
5622 #define xtensa_xsr_op 148
5625 decode_insn (const xtensa_insnbuf insn)
5627 switch (get_op0_field (insn)) {
5628 case 0: /* QRST: op0=0000 */
5629 switch (get_op1_field (insn)) {
5630 case 3: /* RST3: op1=0011 */
5631 switch (get_op2_field (insn)) {
5632 case 8: /* MOVEQZ: op2=1000 */
5633 return xtensa_moveqz_op;
5634 case 9: /* MOVNEZ: op2=1001 */
5635 return xtensa_movnez_op;
5636 case 10: /* MOVLTZ: op2=1010 */
5637 return xtensa_movltz_op;
5638 case 11: /* MOVGEZ: op2=1011 */
5639 return xtensa_movgez_op;
5640 case 0: /* RSR: op2=0000 */
5641 return xtensa_rsr_op;
5642 case 1: /* WSR: op2=0001 */
5643 return xtensa_wsr_op;
5646 case 9: /* LSI4: op1=1001 */
5647 switch (get_op2_field (insn)) {
5648 case 4: /* S32E: op2=0100 */
5649 return xtensa_s32e_op;
5650 case 0: /* L32E: op2=0000 */
5651 return xtensa_l32e_op;
5654 case 4: /* EXTUI: op1=010x */
5655 case 5: /* EXTUI: op1=010x */
5656 return xtensa_extui_op;
5657 case 0: /* RST0: op1=0000 */
5658 switch (get_op2_field (insn)) {
5659 case 15: /* SUBX8: op2=1111 */
5660 return xtensa_subx8_op;
5661 case 0: /* ST0: op2=0000 */
5662 switch (get_r_field (insn)) {
5663 case 0: /* SNM0: r=0000 */
5664 switch (get_m_field (insn)) {
5665 case 2: /* JR: m=10 */
5666 switch (get_n_field (insn)) {
5667 case 0: /* RET: n=00 */
5668 return xtensa_ret_op;
5669 case 1: /* RETW: n=01 */
5670 return xtensa_retw_op;
5671 case 2: /* JX: n=10 */
5672 return xtensa_jx_op;
5675 case 3: /* CALLX: m=11 */
5676 switch (get_n_field (insn)) {
5677 case 0: /* CALLX0: n=00 */
5678 return xtensa_callx0_op;
5679 case 1: /* CALLX4: n=01 */
5680 return xtensa_callx4_op;
5681 case 2: /* CALLX8: n=10 */
5682 return xtensa_callx8_op;
5683 case 3: /* CALLX12: n=11 */
5684 return xtensa_callx12_op;
5689 case 1: /* MOVSP: r=0001 */
5690 return xtensa_movsp_op;
5691 case 2: /* SYNC: r=0010 */
5692 switch (get_s_field (insn)) {
5693 case 0: /* SYNCT: s=0000 */
5694 switch (get_t_field (insn)) {
5695 case 2: /* ESYNC: t=0010 */
5696 return xtensa_esync_op;
5697 case 3: /* DSYNC: t=0011 */
5698 return xtensa_dsync_op;
5699 case 8: /* EXCW: t=1000 */
5700 return xtensa_excw_op;
5701 case 12: /* MEMW: t=1100 */
5702 return xtensa_memw_op;
5703 case 0: /* ISYNC: t=0000 */
5704 return xtensa_isync_op;
5705 case 1: /* RSYNC: t=0001 */
5706 return xtensa_rsync_op;
5711 case 4: /* BREAK: r=0100 */
5712 return xtensa_break_op;
5713 case 3: /* RFEI: r=0011 */
5714 switch (get_t_field (insn)) {
5715 case 0: /* RFET: t=0000 */
5716 switch (get_s_field (insn)) {
5717 case 2: /* RFDE: s=0010 */
5718 return xtensa_rfde_op;
5719 case 4: /* RFWO: s=0100 */
5720 return xtensa_rfwo_op;
5721 case 5: /* RFWU: s=0101 */
5722 return xtensa_rfwu_op;
5723 case 0: /* RFE: s=0000 */
5724 return xtensa_rfe_op;
5727 case 1: /* RFI: t=0001 */
5728 return xtensa_rfi_op;
5731 case 5: /* SCALL: r=0101 */
5732 switch (get_s_field (insn)) {
5733 case 0: /* SYSCALL: s=0000 */
5734 return xtensa_syscall_op;
5735 case 1: /* SIMCALL: s=0001 */
5736 return xtensa_simcall_op;
5739 case 6: /* RSIL: r=0110 */
5740 return xtensa_rsil_op;
5741 case 7: /* WAITI: r=0111 */
5742 return xtensa_waiti_op;
5745 case 1: /* AND: op2=0001 */
5746 return xtensa_and_op;
5747 case 2: /* OR: op2=0010 */
5748 return xtensa_or_op;
5749 case 3: /* XOR: op2=0011 */
5750 return xtensa_xor_op;
5751 case 4: /* ST1: op2=0100 */
5752 switch (get_r_field (insn)) {
5753 case 15: /* NSAU: r=1111 */
5754 return xtensa_nsau_op;
5755 case 0: /* SSR: r=0000 */
5756 return xtensa_ssr_op;
5757 case 1: /* SSL: r=0001 */
5758 return xtensa_ssl_op;
5759 case 2: /* SSA8L: r=0010 */
5760 return xtensa_ssa8l_op;
5761 case 3: /* SSA8B: r=0011 */
5762 return xtensa_ssa8b_op;
5763 case 4: /* SSAI: r=0100 */
5764 return xtensa_ssai_op;
5765 case 8: /* ROTW: r=1000 */
5766 return xtensa_rotw_op;
5767 case 14: /* NSA: r=1110 */
5768 return xtensa_nsa_op;
5771 case 8: /* ADD: op2=1000 */
5772 return xtensa_add_op;
5773 case 5: /* ST4: op2=0101 */
5774 switch (get_r_field (insn)) {
5775 case 15: /* RDTLB1: r=1111 */
5776 return xtensa_rdtlb1_op;
5777 case 0: /* IITLBA: r=0000 */
5778 return xtensa_iitlba_op;
5779 case 3: /* RITLB0: r=0011 */
5780 return xtensa_ritlb0_op;
5781 case 4: /* IITLB: r=0100 */
5782 return xtensa_iitlb_op;
5783 case 8: /* IDTLBA: r=1000 */
5784 return xtensa_idtlba_op;
5785 case 5: /* PITLB: r=0101 */
5786 return xtensa_pitlb_op;
5787 case 6: /* WITLB: r=0110 */
5788 return xtensa_witlb_op;
5789 case 7: /* RITLB1: r=0111 */
5790 return xtensa_ritlb1_op;
5791 case 11: /* RDTLB0: r=1011 */
5792 return xtensa_rdtlb0_op;
5793 case 12: /* IDTLB: r=1100 */
5794 return xtensa_idtlb_op;
5795 case 13: /* PDTLB: r=1101 */
5796 return xtensa_pdtlb_op;
5797 case 14: /* WDTLB: r=1110 */
5798 return xtensa_wdtlb_op;
5801 case 6: /* RT0: op2=0110 */
5802 switch (get_s_field (insn)) {
5803 case 0: /* NEG: s=0000 */
5804 return xtensa_neg_op;
5805 case 1: /* ABS: s=0001 */
5806 return xtensa_abs_op;
5809 case 9: /* ADDX2: op2=1001 */
5810 return xtensa_addx2_op;
5811 case 10: /* ADDX4: op2=1010 */
5812 return xtensa_addx4_op;
5813 case 11: /* ADDX8: op2=1011 */
5814 return xtensa_addx8_op;
5815 case 12: /* SUB: op2=1100 */
5816 return xtensa_sub_op;
5817 case 13: /* SUBX2: op2=1101 */
5818 return xtensa_subx2_op;
5819 case 14: /* SUBX4: op2=1110 */
5820 return xtensa_subx4_op;
5823 case 1: /* RST1: op1=0001 */
5824 switch (get_op2_field (insn)) {
5825 case 15: /* IMP: op2=1111 */
5826 switch (get_r_field (insn)) {
5827 case 0: /* LICT: r=0000 */
5828 return xtensa_lict_op;
5829 case 1: /* SICT: r=0001 */
5830 return xtensa_sict_op;
5831 case 2: /* LICW: r=0010 */
5832 return xtensa_licw_op;
5833 case 3: /* SICW: r=0011 */
5834 return xtensa_sicw_op;
5835 case 8: /* LDCT: r=1000 */
5836 return xtensa_ldct_op;
5837 case 9: /* SDCT: r=1001 */
5838 return xtensa_sdct_op;
5841 case 0: /* SLLI: op2=000x */
5842 case 1: /* SLLI: op2=000x */
5843 return xtensa_slli_op;
5844 case 2: /* SRAI: op2=001x */
5845 case 3: /* SRAI: op2=001x */
5846 return xtensa_srai_op;
5847 case 4: /* SRLI: op2=0100 */
5848 return xtensa_srli_op;
5849 case 8: /* SRC: op2=1000 */
5850 return xtensa_src_op;
5851 case 9: /* SRL: op2=1001 */
5852 return xtensa_srl_op;
5853 case 6: /* XSR: op2=0110 */
5854 return xtensa_xsr_op;
5855 case 10: /* SLL: op2=1010 */
5856 return xtensa_sll_op;
5857 case 11: /* SRA: op2=1011 */
5858 return xtensa_sra_op;
5863 case 1: /* L32R: op0=0001 */
5864 return xtensa_l32r_op;
5865 case 2: /* LSAI: op0=0010 */
5866 switch (get_r_field (insn)) {
5867 case 0: /* L8UI: r=0000 */
5868 return xtensa_l8ui_op;
5869 case 1: /* L16UI: r=0001 */
5870 return xtensa_l16ui_op;
5871 case 2: /* L32I: r=0010 */
5872 return xtensa_l32i_op;
5873 case 4: /* S8I: r=0100 */
5874 return xtensa_s8i_op;
5875 case 5: /* S16I: r=0101 */
5876 return xtensa_s16i_op;
5877 case 9: /* L16SI: r=1001 */
5878 return xtensa_l16si_op;
5879 case 6: /* S32I: r=0110 */
5880 return xtensa_s32i_op;
5881 case 7: /* CACHE: r=0111 */
5882 switch (get_t_field (insn)) {
5883 case 15: /* III: t=1111 */
5884 return xtensa_iii_op;
5885 case 0: /* DPFR: t=0000 */
5886 return xtensa_dpfr_op;
5887 case 1: /* DPFW: t=0001 */
5888 return xtensa_dpfw_op;
5889 case 2: /* DPFRO: t=0010 */
5890 return xtensa_dpfro_op;
5891 case 4: /* DHWB: t=0100 */
5892 return xtensa_dhwb_op;
5893 case 3: /* DPFWO: t=0011 */
5894 return xtensa_dpfwo_op;
5895 case 8: /* DCE: t=1000 */
5896 switch (get_op1_field (insn)) {
5897 case 4: /* DIWB: op1=0100 */
5898 return xtensa_diwb_op;
5899 case 5: /* DIWBI: op1=0101 */
5900 return xtensa_diwbi_op;
5903 case 5: /* DHWBI: t=0101 */
5904 return xtensa_dhwbi_op;
5905 case 6: /* DHI: t=0110 */
5906 return xtensa_dhi_op;
5907 case 7: /* DII: t=0111 */
5908 return xtensa_dii_op;
5909 case 12: /* IPF: t=1100 */
5910 return xtensa_ipf_op;
5911 case 14: /* IHI: t=1110 */
5912 return xtensa_ihi_op;
5915 case 10: /* MOVI: r=1010 */
5916 return xtensa_movi_op;
5917 case 12: /* ADDI: r=1100 */
5918 return xtensa_addi_op;
5919 case 13: /* ADDMI: r=1101 */
5920 return xtensa_addmi_op;
5923 case 8: /* L32I.N: op0=1000 */
5924 return xtensa_l32i_n_op;
5925 case 5: /* CALL: op0=0101 */
5926 switch (get_n_field (insn)) {
5927 case 0: /* CALL0: n=00 */
5928 return xtensa_call0_op;
5929 case 1: /* CALL4: n=01 */
5930 return xtensa_call4_op;
5931 case 2: /* CALL8: n=10 */
5932 return xtensa_call8_op;
5933 case 3: /* CALL12: n=11 */
5934 return xtensa_call12_op;
5937 case 6: /* SI: op0=0110 */
5938 switch (get_n_field (insn)) {
5939 case 0: /* J: n=00 */
5941 case 1: /* BZ: n=01 */
5942 switch (get_m_field (insn)) {
5943 case 0: /* BEQZ: m=00 */
5944 return xtensa_beqz_op;
5945 case 1: /* BNEZ: m=01 */
5946 return xtensa_bnez_op;
5947 case 2: /* BLTZ: m=10 */
5948 return xtensa_bltz_op;
5949 case 3: /* BGEZ: m=11 */
5950 return xtensa_bgez_op;
5953 case 2: /* BI0: n=10 */
5954 switch (get_m_field (insn)) {
5955 case 0: /* BEQI: m=00 */
5956 return xtensa_beqi_op;
5957 case 1: /* BNEI: m=01 */
5958 return xtensa_bnei_op;
5959 case 2: /* BLTI: m=10 */
5960 return xtensa_blti_op;
5961 case 3: /* BGEI: m=11 */
5962 return xtensa_bgei_op;
5965 case 3: /* BI1: n=11 */
5966 switch (get_m_field (insn)) {
5967 case 0: /* ENTRY: m=00 */
5968 return xtensa_entry_op;
5969 case 1: /* B1: m=01 */
5970 switch (get_r_field (insn)) {
5971 case 8: /* LOOP: r=1000 */
5972 return xtensa_loop_op;
5973 case 9: /* LOOPNEZ: r=1001 */
5974 return xtensa_loopnez_op;
5975 case 10: /* LOOPGTZ: r=1010 */
5976 return xtensa_loopgtz_op;
5979 case 2: /* BLTUI: m=10 */
5980 return xtensa_bltui_op;
5981 case 3: /* BGEUI: m=11 */
5982 return xtensa_bgeui_op;
5987 case 9: /* S32I.N: op0=1001 */
5988 return xtensa_s32i_n_op;
5989 case 10: /* ADD.N: op0=1010 */
5990 return xtensa_add_n_op;
5991 case 7: /* B: op0=0111 */
5992 switch (get_r_field (insn)) {
5993 case 6: /* BBCI: r=011x */
5994 case 7: /* BBCI: r=011x */
5995 return xtensa_bbci_op;
5996 case 0: /* BNONE: r=0000 */
5997 return xtensa_bnone_op;
5998 case 1: /* BEQ: r=0001 */
5999 return xtensa_beq_op;
6000 case 2: /* BLT: r=0010 */
6001 return xtensa_blt_op;
6002 case 4: /* BALL: r=0100 */
6003 return xtensa_ball_op;
6004 case 14: /* BBSI: r=111x */
6005 case 15: /* BBSI: r=111x */
6006 return xtensa_bbsi_op;
6007 case 3: /* BLTU: r=0011 */
6008 return xtensa_bltu_op;
6009 case 5: /* BBC: r=0101 */
6010 return xtensa_bbc_op;
6011 case 8: /* BANY: r=1000 */
6012 return xtensa_bany_op;
6013 case 9: /* BNE: r=1001 */
6014 return xtensa_bne_op;
6015 case 10: /* BGE: r=1010 */
6016 return xtensa_bge_op;
6017 case 11: /* BGEU: r=1011 */
6018 return xtensa_bgeu_op;
6019 case 12: /* BNALL: r=1100 */
6020 return xtensa_bnall_op;
6021 case 13: /* BBS: r=1101 */
6022 return xtensa_bbs_op;
6025 case 11: /* ADDI.N: op0=1011 */
6026 return xtensa_addi_n_op;
6027 case 12: /* ST2: op0=1100 */
6028 switch (get_i_field (insn)) {
6029 case 0: /* MOVI.N: i=0 */
6030 return xtensa_movi_n_op;
6031 case 1: /* BZ6: i=1 */
6032 switch (get_z_field (insn)) {
6033 case 0: /* BEQZ.N: z=0 */
6034 return xtensa_beqz_n_op;
6035 case 1: /* BNEZ.N: z=1 */
6036 return xtensa_bnez_n_op;
6041 case 13: /* ST3: op0=1101 */
6042 switch (get_r_field (insn)) {
6043 case 15: /* S3: r=1111 */
6044 switch (get_t_field (insn)) {
6045 case 0: /* RET.N: t=0000 */
6046 return xtensa_ret_n_op;
6047 case 1: /* RETW.N: t=0001 */
6048 return xtensa_retw_n_op;
6049 case 2: /* BREAK.N: t=0010 */
6050 return xtensa_break_n_op;
6051 case 3: /* NOP.N: t=0011 */
6052 return xtensa_nop_n_op;
6055 case 0: /* MOV.N: r=0000 */
6056 return xtensa_mov_n_op;
6060 return XTENSA_UNDEFINED;
6064 interface_version (void)
6069 static struct config_struct config_table[] = {
6070 {"IsaMemoryOrder", "BigEndian"},
6071 {"PIFReadDataBits", "128"},
6072 {"PIFWriteDataBits", "128"},
6073 {"IsaCoprocessorCount", "0"},
6074 {"IsaUseBooleans", "0"},
6075 {"IsaUseDensityInstruction", "1"},
6079 struct config_struct * get_config_table (void);
6081 struct config_struct *
6082 get_config_table (void)
6084 return config_table;
6087 xtensa_isa_module xtensa_isa_modules[] = {
6088 { get_num_opcodes, get_opcodes, decode_insn, get_config_table },