From eaf7c63943573e430f06d4001bdb2bc2941f666e Mon Sep 17 00:00:00 2001 From: ebotcazou Date: Thu, 14 Mar 2013 18:52:18 +0000 Subject: [PATCH] PR target/56351 Backport from mainline 2012-10-22 Julian Brown * config/arm/arm.h (CANNOT_CHANGE_MODE_CLASS): Avoid subreg'ing VFP D registers in big-endian mode. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_7-branch@196664 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 9 +++++++++ gcc/config/arm/arm.h | 15 +++++++++++---- 2 files changed, 20 insertions(+), 4 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 9c68a7e1aad..0743138f770 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2013-03-14 Seth LaForge + + PR target/56351 + Backport from mainline + 2012-10-22 Julian Brown + + * config/arm/arm.h (CANNOT_CHANGE_MODE_CLASS): Avoid subreg'ing + VFP D registers in big-endian mode. + 2013-03-08 Joey Ye Backport from mainline diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index a3db5c4d600..fbbf041a4fb 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -1126,11 +1126,18 @@ enum reg_class /* FPA registers can't do subreg as all values are reformatted to internal precision. In VFPv1, VFP registers could only be accessed in the mode they were set, so subregs would be invalid there too. However, we don't - support VFPv1 at the moment, and the restriction was lifted in VFPv2. */ + support VFPv1 at the moment, and the restriction was lifted in VFPv2. + In big-endian mode, modes greater than word size (i.e. DFmode) are stored in + VFP registers in little-endian order. We can't describe that accurately to + GCC, so avoid taking subregs of such values. */ #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ - (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ - ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \ - : 0) + (TARGET_VFP \ + ? TARGET_BIG_END \ + && (GET_MODE_SIZE (FROM) > UNITS_PER_WORD \ + || GET_MODE_SIZE (TO) > UNITS_PER_WORD) \ + && reg_classes_intersect_p (VFP_REGS, (CLASS)) \ + : GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ + && reg_classes_intersect_p (FPA_REGS, (CLASS))) /* The class value for index registers, and the one for base regs. */ #define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS) -- 2.11.0