From e52ea37010b3a045128dffdacef97b2affd63a48 Mon Sep 17 00:00:00 2001 From: bwilson Date: Tue, 19 Mar 2002 20:16:35 +0000 Subject: [PATCH] * config/xtensa/xtensa.md (adddi3, adddi_carry, subdi3, subdi_carry): Define. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@51039 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 5 ++++ gcc/config/xtensa/xtensa.md | 69 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 74 insertions(+) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 2f3b701864c..70b9756c522 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2002-03-19 Bob Wilson + + * config/xtensa/xtensa.md (adddi3, adddi_carry, subdi3, + subdi_carry): Define. + 2002-03-19 David Edelsohn * config/rs6000/rs6000.c (rs6000_override_options): Only warn diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md index d1fd5edf4c7..abf8307f8bb 100644 --- a/gcc/config/xtensa/xtensa.md +++ b/gcc/config/xtensa/xtensa.md @@ -89,6 +89,43 @@ ;; .................... ;; +(define_expand "adddi3" + [(set (match_operand:DI 0 "register_operand" "") + (plus:DI (match_operand:DI 1 "register_operand" "") + (match_operand:DI 2 "register_operand" "")))] + "" + " +{ + rtx dstlo = gen_lowpart (SImode, operands[0]); + rtx src1lo = gen_lowpart (SImode, operands[1]); + rtx src2lo = gen_lowpart (SImode, operands[2]); + + rtx dsthi = gen_highpart (SImode, operands[0]); + rtx src1hi = gen_highpart (SImode, operands[1]); + rtx src2hi = gen_highpart (SImode, operands[2]); + + emit_insn (gen_addsi3 (dstlo, src1lo, src2lo)); + emit_insn (gen_addsi3 (dsthi, src1hi, src2hi)); + emit_insn (gen_adddi_carry (dsthi, dstlo, src2lo)); + DONE; +}") + +;; Represent the add-carry operation as an atomic operation instead of +;; expanding it to a conditional branch. Otherwise, the edge +;; profiling code breaks because inserting the count increment code +;; causes a new jump insn to be added. + +(define_insn "adddi_carry" + [(set (match_operand:SI 0 "register_operand" "+a") + (plus:SI (ltu:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")) + (match_dup 0)))] + "" + "bgeu\\t%1, %2, 0f\;addi\\t%0, %0, 1\;0:" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "6")]) + (define_insn "addsi3" [(set (match_operand:SI 0 "register_operand" "=D,D,a,a,a") (plus:SI (match_operand:SI 1 "register_operand" "%d,d,r,r,r") @@ -156,6 +193,38 @@ ;; .................... ;; +(define_expand "subdi3" + [(set (match_operand:DI 0 "register_operand" "") + (minus:DI (match_operand:DI 1 "register_operand" "") + (match_operand:DI 2 "register_operand" "")))] + "" + " +{ + rtx dstlo = gen_lowpart (SImode, operands[0]); + rtx src1lo = gen_lowpart (SImode, operands[1]); + rtx src2lo = gen_lowpart (SImode, operands[2]); + + rtx dsthi = gen_highpart (SImode, operands[0]); + rtx src1hi = gen_highpart (SImode, operands[1]); + rtx src2hi = gen_highpart (SImode, operands[2]); + + emit_insn (gen_subsi3 (dstlo, src1lo, src2lo)); + emit_insn (gen_subsi3 (dsthi, src1hi, src2hi)); + emit_insn (gen_subdi_carry (dsthi, src1lo, src2lo)); + DONE; +}") + +(define_insn "subdi_carry" + [(set (match_operand:SI 0 "register_operand" "+a") + (minus:SI (match_dup 0) + (ltu:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r"))))] + "" + "bgeu\\t%1, %2, 0f\;addi\\t%0, %0, -1\;0:" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "6")]) + (define_insn "subsi3" [(set (match_operand:SI 0 "register_operand" "=a") (minus:SI (match_operand:SI 1 "register_operand" "r") -- 2.11.0