From d168b988efe56d68f7b6c9e7351a86f7ef4d0a41 Mon Sep 17 00:00:00 2001 From: meissner Date: Wed, 24 Mar 2010 20:59:24 +0000 Subject: [PATCH] Fix 43484, swap registers if one is R0 for multiword moves git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@157709 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 6 ++++++ gcc/config/rs6000/rs6000.c | 10 ++++++++++ 2 files changed, 16 insertions(+) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index e6d05fe1671..d2872bc3e0d 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2010-03-24 Michael Meissner + + PR target/43484 + * config/rs6000/rs6000.c (rs6000_split_multireg_move): If r0 is + used in reg+reg addressing, swap registers. + 2010-03-24 Jakub Jelinek PR debug/43293 diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index ab48e82d9fc..98b4d942541 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -16832,6 +16832,16 @@ rs6000_split_multireg_move (rtx dst, rtx src) { rtx basereg = XEXP (XEXP (dst, 0), 0); rtx offsetreg = XEXP (XEXP (dst, 0), 1); + gcc_assert (GET_CODE (XEXP (dst, 0)) == PLUS + && REG_P (basereg) + && REG_P (offsetreg) + && REGNO (basereg) != REGNO (offsetreg)); + if (REGNO (basereg) == 0) + { + rtx tmp = offsetreg; + offsetreg = basereg; + basereg = tmp; + } emit_insn (gen_add3_insn (basereg, basereg, offsetreg)); restore_basereg = gen_sub3_insn (basereg, basereg, offsetreg); dst = replace_equiv_address (dst, basereg); -- 2.11.0