From 960e6739f5c05d5ef8cb5f9471718f90e42ec690 Mon Sep 17 00:00:00 2001 From: bernie Date: Thu, 21 Aug 2003 01:03:37 +0000 Subject: [PATCH] * config/m68k/m68k-none.h: Introduce new ColdFire archs. * config/m68k/m68k.h: Likewise. * config/m68k/lb1sf68.asm: Rename __mcf5200__ to __mcoldfire__. * config/m68k/coff.h: Rename TARGET_5200 to TARGET_COLDFIRE. * config/m68k/linux.h: Likewise. * config/m68k/m68k.c: Likewise. * config/m68k/m68k.md: Likewise. * config/m68k/m68kelf.h: Likewise. * config/m68k/netbsd-elf.h: Likewise. * config/m68k/t-m68kelf: Add multilib targets for new ColdFire archs. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@70630 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 14 ++ gcc/config/m68k/coff.h | 2 +- gcc/config/m68k/lb1sf68.asm | 362 ++++++++++++++++++------------------- gcc/config/m68k/linux.h | 2 +- gcc/config/m68k/m68k-none.h | 21 ++- gcc/config/m68k/m68k.c | 34 ++-- gcc/config/m68k/m68k.h | 76 ++++++-- gcc/config/m68k/m68k.md | 420 ++++++++++++++++++++++++------------------- gcc/config/m68k/m68kelf.h | 2 +- gcc/config/m68k/netbsd-elf.h | 2 +- gcc/config/m68k/t-m68kelf | 11 +- 11 files changed, 533 insertions(+), 413 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 2e140c82047..30394f9e085 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,17 @@ +2003-08-06 Peter Barada + Bernardo Innocenti + + * config/m68k/m68k-none.h: Introduce new ColdFire archs. + * config/m68k/m68k.h: Likewise. + * config/m68k/lb1sf68.asm: Rename __mcf5200__ to __mcoldfire__. + * config/m68k/coff.h: Rename TARGET_5200 to TARGET_COLDFIRE. + * config/m68k/linux.h: Likewise. + * config/m68k/m68k.c: Likewise. + * config/m68k/m68k.md: Likewise. + * config/m68k/m68kelf.h: Likewise. + * config/m68k/netbsd-elf.h: Likewise. + * config/m68k/t-m68kelf: Add multilib targets for new ColdFire archs. + 2003-08-20 Bernardo Innocenti * config/m68k/m68k.c: Strip away code depending on NO_ADDSUB_Q definition. diff --git a/gcc/config/m68k/coff.h b/gcc/config/m68k/coff.h index 77be8b9743c..7b9565ebf2c 100644 --- a/gcc/config/m68k/coff.h +++ b/gcc/config/m68k/coff.h @@ -57,7 +57,7 @@ Boston, MA 02111-1307, USA. */ #define ASM_RETURN_CASE_JUMP \ do { \ - if (TARGET_5200) \ + if (TARGET_COLDFIRE) \ { \ if (ADDRESS_REG_P (operands[0])) \ return "jmp %%pc@(2,%0:l)"; \ diff --git a/gcc/config/m68k/lb1sf68.asm b/gcc/config/m68k/lb1sf68.asm index 7bcee2eabe4..d424e9787f1 100644 --- a/gcc/config/m68k/lb1sf68.asm +++ b/gcc/config/m68k/lb1sf68.asm @@ -214,7 +214,7 @@ TRUNCDFSF = 7 | void __clear_sticky_bits(void); SYM (__clear_sticky_bit): lea SYM (_fpCCR),a0 -#ifndef __mcf5200__ +#ifndef __mcoldfire__ movew IMM (0),a0@(STICK) #else clr.w a0@(STICK) @@ -248,7 +248,7 @@ FPTRAP = 15 $_exception_handler: lea SYM (_fpCCR),a0 movew d7,a0@(EBITS) | set __exception_bits -#ifndef __mcf5200__ +#ifndef __mcoldfire__ orw d7,a0@(STICK) | and __sticky_bits #else movew a0@(STICK),d4 @@ -259,7 +259,7 @@ $_exception_handler: movew d5,a0@(LASTO) | and __last_operation | Now put the operands in place: -#ifndef __mcf5200__ +#ifndef __mcoldfire__ cmpw IMM (SINGLE_FLOAT),d6 #else cmpl IMM (SINGLE_FLOAT),d6 @@ -274,7 +274,7 @@ $_exception_handler: movel a6@(12),a0@(OPER2) 2: | And check whether the exception is trap-enabled: -#ifndef __mcf5200__ +#ifndef __mcoldfire__ andw a0@(TRAPE),d7 | is exception trap-enabled? #else clrl d6 @@ -284,7 +284,7 @@ $_exception_handler: beq 1f | no, exit pea SYM (_fpCCR) | yes, push address of _fpCCR trap IMM (FPTRAP) | and trap -#ifndef __mcf5200__ +#ifndef __mcoldfire__ 1: moveml sp@+,d2-d7 | restore data registers #else 1: moveml sp@,d2-d7 @@ -304,7 +304,7 @@ SYM (__mulsi3): muluw sp@(10), d0 /* x0*y1 */ movew sp@(6), d1 /* x1 -> d1 */ muluw sp@(8), d1 /* x1*y0 */ -#ifndef __mcf5200__ +#ifndef __mcoldfire__ addw d1, d0 #else addl d1, d0 @@ -323,7 +323,7 @@ SYM (__mulsi3): .proc .globl SYM (__udivsi3) SYM (__udivsi3): -#ifndef __mcf5200__ +#ifndef __mcoldfire__ movel d2, sp@- movel sp@(12), d1 /* d1 = divisor */ movel sp@(8), d0 /* d0 = dividend */ @@ -368,7 +368,7 @@ L5: subql IMM (1), d0 /* adjust quotient */ L6: movel sp@+, d2 rts -#else /* __mcf5200__ */ +#else /* __mcoldfire__ */ /* Coldfire implementation of non-restoring division algorithm from Hennessy & Patterson, Appendix A. */ @@ -390,7 +390,7 @@ L2: subql IMM (1),d4 moveml sp@,d2-d4 | restore data registers unlk a6 | and return rts -#endif /* __mcf5200__ */ +#endif /* __mcoldfire__ */ #endif /* L_udivsi3 */ @@ -405,7 +405,7 @@ SYM (__divsi3): movel sp@(12), d1 /* d1 = divisor */ jpl L1 negl d1 -#ifndef __mcf5200__ +#ifndef __mcoldfire__ negb d2 /* change sign because divisor <0 */ #else negl d2 /* change sign because divisor <0 */ @@ -413,7 +413,7 @@ SYM (__divsi3): L1: movel sp@(8), d0 /* d0 = dividend */ jpl L2 negl d0 -#ifndef __mcf5200__ +#ifndef __mcoldfire__ negb d2 #else negl d2 @@ -444,7 +444,7 @@ SYM (__umodsi3): jbsr SYM (__udivsi3) addql IMM (8), sp movel sp@(8), d1 /* d1 = divisor */ -#ifndef __mcf5200__ +#ifndef __mcoldfire__ movel d1, sp@- movel d0, sp@- jbsr SYM (__mulsi3) /* d0 = (a/b)*b */ @@ -470,7 +470,7 @@ SYM (__modsi3): jbsr SYM (__divsi3) addql IMM (8), sp movel sp@(8), d1 /* d1 = divisor */ -#ifndef __mcf5200__ +#ifndef __mcoldfire__ movel d1, sp@- movel d0, sp@- jbsr SYM (__mulsi3) /* d0 = (a/b)*b */ @@ -611,7 +611,7 @@ SYM (__subdf3): | double __adddf3(double, double); SYM (__adddf3): -#ifndef __mcf5200__ +#ifndef __mcoldfire__ link a6,IMM (0) | everything will be done in registers moveml d2-d7,sp@- | save all data registers and a2 (but d0-d1) #else @@ -635,7 +635,7 @@ SYM (__adddf3): andl IMM (0x80000000),d7 | isolate a's sign bit ' swap d6 | and also b's sign bit ' -#ifndef __mcf5200__ +#ifndef __mcoldfire__ andw IMM (0x8000),d6 | orw d6,d7 | and combine them into d7, so that a's sign ' | bit is in the high word and b's is in the ' @@ -662,7 +662,7 @@ SYM (__adddf3): orl d7,d0 | and put hidden bit back Ladddf$1: swap d4 | shift right exponent so that it starts -#ifndef __mcf5200__ +#ifndef __mcoldfire__ lsrw IMM (5),d4 | in bit 0 and not bit 20 #else lsrl IMM (5),d4 | in bit 0 and not bit 20 @@ -678,7 +678,7 @@ Ladddf$1: orl d7,d2 | and put hidden bit back Ladddf$2: swap d5 | shift right exponent so that it starts -#ifndef __mcf5200__ +#ifndef __mcoldfire__ lsrw IMM (5),d5 | in bit 0 and not bit 20 #else lsrl IMM (5),d5 | in bit 0 and not bit 20 @@ -693,7 +693,7 @@ Ladddf$2: | and d4-d5-d6-d7 for the second. To do this we store (temporarily) the | exponents in a2-a3. -#ifndef __mcf5200__ +#ifndef __mcoldfire__ moveml a2-a3,sp@- | save the address registers #else movel a2,sp@- @@ -713,7 +713,7 @@ Ladddf$2: | Here we shift the numbers until the exponents are the same, and put | the largest exponent in a2. -#ifndef __mcf5200__ +#ifndef __mcoldfire__ exg d4,a2 | get exponents back exg d5,a3 | cmpw d4,d5 | compare the exponents @@ -732,7 +732,7 @@ Ladddf$2: | Here we have a's exponent larger than b's, so we have to shift b. We do | this by using as counter d2: 1: movew d4,d2 | move largest exponent to d2 -#ifndef __mcf5200__ +#ifndef __mcoldfire__ subw d5,d2 | and subtract second exponent exg d4,a2 | get back the longs we saved exg d5,a3 | @@ -746,20 +746,20 @@ Ladddf$2: movel a4,a3 #endif | if difference is too large we don't shift (actually, we can just exit) ' -#ifndef __mcf5200__ +#ifndef __mcoldfire__ cmpw IMM (DBL_MANT_DIG+2),d2 #else cmpl IMM (DBL_MANT_DIG+2),d2 #endif bge Ladddf$b$small -#ifndef __mcf5200__ +#ifndef __mcoldfire__ cmpw IMM (32),d2 | if difference >= 32, shift by longs #else cmpl IMM (32),d2 | if difference >= 32, shift by longs #endif bge 5f 2: -#ifndef __mcf5200__ +#ifndef __mcoldfire__ cmpw IMM (16),d2 | if difference >= 16, shift by words #else cmpl IMM (16),d2 | if difference >= 16, shift by words @@ -768,7 +768,7 @@ Ladddf$2: bra 3f | enter dbra loop 4: -#ifndef __mcf5200__ +#ifndef __mcoldfire__ lsrl IMM (1),d4 roxrl IMM (1),d5 roxrl IMM (1),d6 @@ -789,7 +789,7 @@ Ladddf$2: 12: lsrl IMM (1),d4 #endif 3: -#ifndef __mcf5200__ +#ifndef __mcoldfire__ dbra d2,4b #else subql IMM (1),d2 @@ -803,7 +803,7 @@ Ladddf$2: movel d5,d6 movel d4,d5 movel IMM (0),d4 -#ifndef __mcf5200__ +#ifndef __mcoldfire__ subw IMM (32),d2 #else subl IMM (32),d2 @@ -818,7 +818,7 @@ Ladddf$2: swap d5 movew IMM (0),d4 swap d4 -#ifndef __mcf5200__ +#ifndef __mcoldfire__ subw IMM (16),d2 #else subl IMM (16),d2 @@ -826,7 +826,7 @@ Ladddf$2: bra 3b 9: -#ifndef __mcf5200__ +#ifndef __mcoldfire__ exg d4,d5 movew d4,d6 subw d5,d6 | keep d5 (largest exponent) in d4 @@ -845,20 +845,20 @@ Ladddf$2: movel a4,a3 #endif | if difference is too large we don't shift (actually, we can just exit) ' -#ifndef __mcf5200__ +#ifndef __mcoldfire__ cmpw IMM (DBL_MANT_DIG+2),d6 #else cmpl IMM (DBL_MANT_DIG+2),d6 #endif bge Ladddf$a$small -#ifndef __mcf5200__ +#ifndef __mcoldfire__ cmpw IMM (32),d6 | if difference >= 32, shift by longs #else cmpl IMM (32),d6 | if difference >= 32, shift by longs #endif bge 5f 2: -#ifndef __mcf5200__ +#ifndef __mcoldfire__ cmpw IMM (16),d6 | if difference >= 16, shift by words #else cmpl IMM (16),d6 | if difference >= 16, shift by words @@ -867,7 +867,7 @@ Ladddf$2: bra 3f | enter dbra loop 4: -#ifndef __mcf5200__ +#ifndef __mcoldfire__ lsrl IMM (1),d0 roxrl IMM (1),d1 roxrl IMM (1),d2 @@ -888,7 +888,7 @@ Ladddf$2: 12: lsrl IMM (1),d0 #endif 3: -#ifndef __mcf5200__ +#ifndef __mcoldfire__ dbra d6,4b #else subql IMM (1),d6 @@ -902,7 +902,7 @@ Ladddf$2: movel d1,d2 movel d0,d1 movel IMM (0),d0 -#ifndef __mcf5200__ +#ifndef __mcoldfire__ subw IMM (32),d6 #else subl IMM (32),d6 @@ -917,14 +917,14 @@ Ladddf$2: swap d1 movew IMM (0),d0 swap d0 -#ifndef __mcf5200__ +#ifndef __mcoldfire__ subw IMM (16),d6 #else subl IMM (16),d6 #endif bra 3b Ladddf$3: -#ifndef __mcf5200__ +#ifndef __mcoldfire__ exg d4,a2 exg d5,a3 #else @@ -940,7 +940,7 @@ Ladddf$4: | the signs in a4. | Here we have to decide whether to add or subtract the numbers: -#ifndef __mcf5200__ +#ifndef __mcoldfire__ exg d7,a0 | get the signs exg d6,a3 | a3 is free to be used #else @@ -958,7 +958,7 @@ Ladddf$4: eorl d7,d6 | compare the signs bmi Lsubdf$0 | if the signs are different we have | to subtract -#ifndef __mcf5200__ +#ifndef __mcoldfire__ exg d7,a0 | else we add the numbers exg d6,a3 | #else @@ -978,7 +978,7 @@ Ladddf$4: movel a0,d7 | andl IMM (0x80000000),d7 | d7 now has the sign -#ifndef __mcf5200__ +#ifndef __mcoldfire__ moveml sp@+,a2-a3 #else movel sp@+,a4 @@ -992,7 +992,7 @@ Ladddf$4: | one more bit we check this: btst IMM (DBL_MANT_DIG+1),d0 beq 1f -#ifndef __mcf5200__ +#ifndef __mcoldfire__ lsrl IMM (1),d0 roxrl IMM (1),d1 roxrl IMM (1),d2 @@ -1017,12 +1017,12 @@ Ladddf$4: 1: lea Ladddf$5,a0 | to return from rounding routine lea SYM (_fpCCR),a1 | check the rounding mode -#ifdef __mcf5200__ +#ifdef __mcoldfire__ clrl d6 #endif movew a1@(6),d6 | rounding mode in d6 beq Lround$to$nearest -#ifndef __mcf5200__ +#ifndef __mcoldfire__ cmpw IMM (ROUND_TO_PLUS),d6 #else cmpl IMM (ROUND_TO_PLUS),d6 @@ -1032,20 +1032,20 @@ Ladddf$4: bra Lround$to$plus Ladddf$5: | Put back the exponent and check for overflow -#ifndef __mcf5200__ +#ifndef __mcoldfire__ cmpw IMM (0x7ff),d4 | is the exponent big? #else cmpl IMM (0x7ff),d4 | is the exponent big? #endif bge 1f bclr IMM (DBL_MANT_DIG-1),d0 -#ifndef __mcf5200__ +#ifndef __mcoldfire__ lslw IMM (4),d4 | put exponent back into position #else lsll IMM (4),d4 | put exponent back into position #endif swap d0 | -#ifndef __mcf5200__ +#ifndef __mcoldfire__ orw d4,d0 | #else orl d4,d0 | @@ -1058,7 +1058,7 @@ Ladddf$5: Lsubdf$0: | Here we do the subtraction. -#ifndef __mcf5200__ +#ifndef __mcoldfire__ exg d7,a0 | put sign back in a0 exg d6,a3 | #else @@ -1086,7 +1086,7 @@ Lsubdf$0: movel a2,d4 | return exponent to d4 movel a0,d7 andl IMM (0x80000000),d7 | isolate sign bit -#ifndef __mcf5200__ +#ifndef __mcoldfire__ moveml sp@+,a2-a3 | #else movel sp@+,a4 @@ -1100,7 +1100,7 @@ Lsubdf$0: | one more bit we check this: btst IMM (DBL_MANT_DIG+1),d0 beq 1f -#ifndef __mcf5200__ +#ifndef __mcoldfire__ lsrl IMM (1),d0 roxrl IMM (1),d1 roxrl IMM (1),d2 @@ -1125,12 +1125,12 @@ Lsubdf$0: 1: lea Lsubdf$1,a0 | to return from rounding routine lea SYM (_fpCCR),a1 | check the rounding mode -#ifdef __mcf5200__ +#ifdef __mcoldfire__ clrl d6 #endif movew a1@(6),d6 | rounding mode in d6 beq Lround$to$nearest -#ifndef __mcf5200__ +#ifndef __mcoldfire__ cmpw IMM (ROUND_TO_PLUS),d6 #else cmpl IMM (ROUND_TO_PLUS),d6 @@ -1141,13 +1141,13 @@ Lsubdf$0: Lsubdf$1: | Put back the exponent and sign (we don't have overflow). ' bclr IMM (DBL_MANT_DIG-1),d0 -#ifndef __mcf5200__ +#ifndef __mcoldfire__ lslw IMM (4),d4 | put exponent back into position #else lsll IMM (4),d4 | put exponent back into position #endif swap d0 | -#ifndef __mcf5200__ +#ifndef __mcoldfire__ orw d4,d0 | #else orl d4,d0 | @@ -1159,7 +1159,7 @@ Lsubdf$1: | DBL_MANT_DIG+1) we return the other (and now we don't have to ' | check for finiteness or zero). Ladddf$a$small: -#ifndef __mcf5200__ +#ifndef __mcoldfire__ moveml sp@+,a2-a3 #else movel sp@+,a4 @@ -1170,7 +1170,7 @@ Ladddf$a$small: movel a6@(20),d1 lea SYM (_fpCCR),a0 movew IMM (0),a0@ -#ifndef __mcf5200__ +#ifndef __mcoldfire__ moveml sp@+,d2-d7 | restore data registers #else moveml sp@,d2-d7 @@ -1181,7 +1181,7 @@ Ladddf$a$small: rts Ladddf$b$small: -#ifndef __mcf5200__ +#ifndef __mcoldfire__ moveml sp@+,a2-a3 #else movel sp@+,a4 @@ -1192,7 +1192,7 @@ Ladddf$b$small: movel a6@(12),d1 lea SYM (_fpCCR),a0 movew IMM (0),a0@ -#ifndef __mcf5200__ +#ifndef __mcoldfire__ moveml sp@+,d2-d7 | restore data registers #else moveml sp@,d2-d7 @@ -1238,7 +1238,7 @@ Ladddf$a: bra Ld$infty | Ladddf$ret$1: -#ifndef __mcf5200__ +#ifndef __mcoldfire__ moveml sp@+,a2-a3 | restore regs and exit #else movel sp@+,a4 @@ -1251,7 +1251,7 @@ Ladddf$ret: lea SYM (_fpCCR),a0 movew IMM (0),a0@ orl d7,d0 | put sign bit back -#ifndef __mcf5200__ +#ifndef __mcoldfire__ moveml sp@+,d2-d7 #else moveml sp@,d2-d7 @@ -1263,7 +1263,7 @@ Ladddf$ret: Ladddf$ret$den: | Return a denormalized number. -#ifndef __mcf5200__ +#ifndef __mcoldfire__ lsrl IMM (1),d0 | shift right once more roxrl IMM (1),d1 | #else @@ -1329,7 +1329,7 @@ Ladddf$nf: | double __muldf3(double, double); SYM (__muldf3): -#ifndef __mcf5200__ +#ifndef __mcoldfire__ link a6,IMM (0) moveml d2-d7,sp@- #else @@ -1370,7 +1370,7 @@ SYM (__muldf3): andl d6,d0 | isolate fraction orl IMM (0x00100000),d0 | and put hidden bit back swap d4 | I like exponents in the first byte -#ifndef __mcf5200__ +#ifndef __mcoldfire__ lsrw IMM (4),d4 | #else lsrl IMM (4),d4 | @@ -1381,13 +1381,13 @@ Lmuldf$1: andl d6,d2 | orl IMM (0x00100000),d2 | and put hidden bit back swap d5 | -#ifndef __mcf5200__ +#ifndef __mcoldfire__ lsrw IMM (4),d5 | #else lsrl IMM (4),d5 | #endif Lmuldf$2: | -#ifndef __mcf5200__ +#ifndef __mcoldfire__ addw d5,d4 | add exponents subw IMM (D_BIAS+1),d4 | and subtract bias (plus one) #else @@ -1405,7 +1405,7 @@ Lmuldf$2: | | enough to keep everything in them. So we use the address registers to keep | some intermediate data. -#ifndef __mcf5200__ +#ifndef __mcoldfire__ moveml a2-a3,sp@- | save a2 and a3 for temporary use #else movel a2,sp@- @@ -1416,7 +1416,7 @@ Lmuldf$2: | movel d4,a3 | and a3 will preserve the exponent | First, shift d2-d3 so bit 20 becomes bit 31: -#ifndef __mcf5200__ +#ifndef __mcoldfire__ rorl IMM (5),d2 | rotate d2 5 places right swap d2 | and swap it rorl IMM (5),d3 | do the same thing with d3 @@ -1447,7 +1447,7 @@ Lmuldf$2: | | We use a1 as counter: movel IMM (DBL_MANT_DIG-1),a1 -#ifndef __mcf5200__ +#ifndef __mcoldfire__ exg d7,a1 #else movel d7,a4 @@ -1456,7 +1456,7 @@ Lmuldf$2: | #endif 1: -#ifndef __mcf5200__ +#ifndef __mcoldfire__ exg d7,a1 | put counter back in a1 #else movel d7,a4 @@ -1470,7 +1470,7 @@ Lmuldf$2: | addl d7,d7 | addxl d6,d6 | bcc 2f | if bit clear skip the following -#ifndef __mcf5200__ +#ifndef __mcoldfire__ exg d7,a2 | #else movel d7,a4 @@ -1481,7 +1481,7 @@ Lmuldf$2: | addxl d4,d2 | addxl d7,d1 | addxl d7,d0 | -#ifndef __mcf5200__ +#ifndef __mcoldfire__ exg d7,a2 | #else movel d7,a4 @@ -1489,7 +1489,7 @@ Lmuldf$2: | movel a4,a2 #endif 2: -#ifndef __mcf5200__ +#ifndef __mcoldfire__ exg d7,a1 | put counter in d7 dbf d7,1b | decrement and branch #else @@ -1501,7 +1501,7 @@ Lmuldf$2: | #endif movel a3,d4 | restore exponent -#ifndef __mcf5200__ +#ifndef __mcoldfire__ moveml sp@+,a2-a3 #else movel sp@+,a4 @@ -1520,7 +1520,7 @@ Lmuldf$2: | swap d3 movew d3,d2 movew IMM (0),d3 -#ifndef __mcf5200__ +#ifndef __mcoldfire__ lsrl IMM (1),d0 roxrl IMM (1),d1 roxrl IMM (1),d2 @@ -1556,7 +1556,7 @@ Lmuldf$2: | btst IMM (DBL_MANT_DIG+1-32),d0 beq Lround$exit -#ifndef __mcf5200__ +#ifndef __mcoldfire__ lsrl IMM (1),d0 roxrl IMM (1),d1 addw IMM (1),d4 @@ -1592,7 +1592,7 @@ Lmuldf$a$nf: | NaN, in which case we return NaN. Lmuldf$b$0: movew IMM (MULTIPLY),d5 -#ifndef __mcf5200__ +#ifndef __mcoldfire__ exg d2,d0 | put b (==0) into d0-d1 exg d3,d1 | and a (with sign bit cleared) into d2-d3 #else @@ -1612,7 +1612,7 @@ Lmuldf$a$0: bge Ld$inop | in case NaN or +/-INFINITY return NaN lea SYM (_fpCCR),a0 movew IMM (0),a0@ -#ifndef __mcf5200__ +#ifndef __mcoldfire__ moveml sp@+,d2-d7 #else moveml sp@,d2-d7 @@ -1631,7 +1631,7 @@ Lmuldf$a$den: andl d6,d0 1: addl d1,d1 | shift a left until bit 20 is set addxl d0,d0 | -#ifndef __mcf5200__ +#ifndef __mcoldfire__ subw IMM (1),d4 | and adjust exponent #else subl IMM (1),d4 | and adjust exponent @@ -1645,7 +1645,7 @@ Lmuldf$b$den: andl d6,d2 1: addl d3,d3 | shift b left until bit 20 is set addxl d2,d2 | -#ifndef __mcf5200__ +#ifndef __mcoldfire__ subw IMM (1),d5 | and adjust exponent #else subql IMM (1),d5 | and adjust exponent @@ -1661,7 +1661,7 @@ Lmuldf$b$den: | double __divdf3(double, double); SYM (__divdf3): -#ifndef __mcf5200__ +#ifndef __mcoldfire__ link a6,IMM (0) moveml d2-d7,sp@- #else @@ -1706,7 +1706,7 @@ SYM (__divdf3): andl d6,d0 | and isolate fraction orl IMM (0x00100000),d0 | and put hidden bit back swap d4 | I like exponents in the first byte -#ifndef __mcf5200__ +#ifndef __mcoldfire__ lsrw IMM (4),d4 | #else lsrl IMM (4),d4 | @@ -1717,13 +1717,13 @@ Ldivdf$1: | andl d6,d2 | orl IMM (0x00100000),d2 swap d5 | -#ifndef __mcf5200__ +#ifndef __mcoldfire__ lsrw IMM (4),d5 | #else lsrl IMM (4),d5 | #endif Ldivdf$2: | -#ifndef __mcf5200__ +#ifndef __mcoldfire__ subw d5,d4 | subtract exponents addw IMM (D_BIAS),d4 | and add bias #else @@ -1760,7 +1760,7 @@ Ldivdf$2: | bset d5,d6 | set the corresponding bit in d6 3: addl d1,d1 | shift a by 1 addxl d0,d0 | -#ifndef __mcf5200__ +#ifndef __mcoldfire__ dbra d5,1b | and branch back #else subql IMM (1), d5 @@ -1782,7 +1782,7 @@ Ldivdf$2: | bset d5,d7 | set the corresponding bit in d7 3: addl d1,d1 | shift a by 1 addxl d0,d0 | -#ifndef __mcf5200__ +#ifndef __mcoldfire__ dbra d5,1b | and branch back #else subql IMM (1), d5 @@ -1800,7 +1800,7 @@ Ldivdf$2: | beq 3f | if d0==d2 check d1 and d3 2: addl d1,d1 | shift a by 1 addxl d0,d0 | -#ifndef __mcf5200__ +#ifndef __mcoldfire__ dbra d5,1b | and branch back #else subql IMM (1), d5 @@ -1816,7 +1816,7 @@ Ldivdf$2: | | to it; if you don't do this the algorithm loses in some cases). ' movel IMM (0),d2 movel d2,d3 -#ifndef __mcf5200__ +#ifndef __mcoldfire__ subw IMM (DBL_MANT_DIG),d5 addw IMM (63),d5 cmpw IMM (31),d5 @@ -1828,7 +1828,7 @@ Ldivdf$2: | bhi 2f 1: bset d5,d3 bra 5f -#ifndef __mcf5200__ +#ifndef __mcoldfire__ subw IMM (32),d5 #else subl IMM (32),d5 @@ -1847,7 +1847,7 @@ Ldivdf$2: | | not set: btst IMM (DBL_MANT_DIG-32+1),d0 beq 1f -#ifndef __mcf5200__ +#ifndef __mcoldfire__ lsrl IMM (1),d0 roxrl IMM (1),d1 roxrl IMM (1),d2 @@ -1897,7 +1897,7 @@ Ldivdf$a$0: movel d0,d1 | lea SYM (_fpCCR),a0 | clear exception flags movew IMM (0),a0@ | -#ifndef __mcf5200__ +#ifndef __mcoldfire__ moveml sp@+,d2-d7 | #else moveml sp@,d2-d7 | @@ -1945,7 +1945,7 @@ Ldivdf$a$den: andl d6,d0 1: addl d1,d1 | shift a left until bit 20 is set addxl d0,d0 -#ifndef __mcf5200__ +#ifndef __mcoldfire__ subw IMM (1),d4 | and adjust exponent #else subl IMM (1),d4 | and adjust exponent @@ -1959,7 +1959,7 @@ Ldivdf$b$den: andl d6,d2 1: addl d3,d3 | shift b left until bit 20 is set addxl d2,d2 -#ifndef __mcf5200__ +#ifndef __mcoldfire__ subw IMM (1),d5 | and adjust exponent #else subql IMM (1),d5 | and adjust exponent @@ -1974,7 +1974,7 @@ Lround$exit: | so that 2^21 <= d0 < 2^22, and the exponent is in the lower byte of d4. | First check for underlow in the exponent: -#ifndef __mcf5200__ +#ifndef __mcoldfire__ cmpw IMM (-DBL_MANT_DIG-1),d4 #else cmpl IMM (-DBL_MANT_DIG-1),d4 @@ -1987,14 +1987,14 @@ Lround$exit: movel d7,a0 | movel IMM (0),d6 | use d6-d7 to collect bits flushed right movel d6,d7 | use d6-d7 to collect bits flushed right -#ifndef __mcf5200__ +#ifndef __mcoldfire__ cmpw IMM (1),d4 | if the exponent is less than 1 we #else cmpl IMM (1),d4 | if the exponent is less than 1 we #endif bge 2f | have to shift right (denormalize) 1: -#ifndef __mcf5200__ +#ifndef __mcoldfire__ addw IMM (1),d4 | adjust the exponent lsrl IMM (1),d0 | shift right once roxrl IMM (1),d1 | @@ -2037,12 +2037,12 @@ Lround$exit: | Now call the rounding routine (which takes care of denormalized numbers): lea Lround$0,a0 | to return from rounding routine lea SYM (_fpCCR),a1 | check the rounding mode -#ifdef __mcf5200__ +#ifdef __mcoldfire__ clrl d6 #endif movew a1@(6),d6 | rounding mode in d6 beq Lround$to$nearest -#ifndef __mcf5200__ +#ifndef __mcoldfire__ cmpw IMM (ROUND_TO_PLUS),d6 #else cmpl IMM (ROUND_TO_PLUS),d6 @@ -2058,7 +2058,7 @@ Lround$0: | check again for underflow!). We have to check for overflow or for a | denormalized number (which also signals underflow). | Check for overflow (i.e., exponent >= 0x7ff). -#ifndef __mcf5200__ +#ifndef __mcoldfire__ cmpw IMM (0x07ff),d4 #else cmpl IMM (0x07ff),d4 @@ -2069,14 +2069,14 @@ Lround$0: beq Ld$den 1: | Put back the exponents and sign and return. -#ifndef __mcf5200__ +#ifndef __mcoldfire__ lslw IMM (4),d4 | exponent back to fourth byte #else lsll IMM (4),d4 | exponent back to fourth byte #endif bclr IMM (DBL_MANT_DIG-32-1),d0 swap d0 | and put back exponent -#ifndef __mcf5200__ +#ifndef __mcoldfire__ orw d4,d0 | #else orl d4,d0 | @@ -2086,7 +2086,7 @@ Lround$0: lea SYM (_fpCCR),a0 movew IMM (0),a0@ -#ifndef __mcf5200__ +#ifndef __mcoldfire__ moveml sp@+,d2-d7 #else moveml sp@,d2-d7 @@ -2102,7 +2102,7 @@ Lround$0: | double __negdf2(double, double); SYM (__negdf2): -#ifndef __mcf5200__ +#ifndef __mcoldfire__ link a6,IMM (0) moveml d2-d7,sp@- #else @@ -2128,7 +2128,7 @@ SYM (__negdf2): bra Ld$infty 1: lea SYM (_fpCCR),a0 movew IMM (0),a0@ -#ifndef __mcf5200__ +#ifndef __mcoldfire__ moveml sp@+,d2-d7 #else moveml sp@,d2-d7 @@ -2150,7 +2150,7 @@ EQUAL = 0 | int __cmpdf2(double, double); SYM (__cmpdf2): -#ifndef __mcf5200__ +#ifndef __mcoldfire__ link a6,IMM (0) moveml d2-d7,sp@- | save registers #else @@ -2194,7 +2194,7 @@ Lcmpdf$1: tstl d6 bpl 1f | If both are negative exchange them -#ifndef __mcf5200__ +#ifndef __mcoldfire__ exg d0,d2 exg d1,d3 #else @@ -2217,7 +2217,7 @@ Lcmpdf$1: bne Lcmpdf$a$gt$b | |b| < |a| | If we got here a == b. movel IMM (EQUAL),d0 -#ifndef __mcf5200__ +#ifndef __mcoldfire__ moveml sp@+,d2-d7 | put back the registers #else moveml sp@,d2-d7 @@ -2228,7 +2228,7 @@ Lcmpdf$1: rts Lcmpdf$a$gt$b: movel IMM (GREATER),d0 -#ifndef __mcf5200__ +#ifndef __mcoldfire__ moveml sp@+,d2-d7 | put back the registers #else moveml sp@,d2-d7 @@ -2239,7 +2239,7 @@ Lcmpdf$a$gt$b: rts Lcmpdf$b$gt$a: movel IMM (LESS),d0 -#ifndef __mcf5200__ +#ifndef __mcoldfire__ moveml sp@+,d2-d7 | put back the registers #else moveml sp@,d2-d7 @@ -2287,7 +2287,7 @@ Lround$to$nearest: | Normalize shifting left until bit #DBL_MANT_DIG-32 is set or the exponent | is one (remember that a denormalized number corresponds to an | exponent of -D_BIAS+1). -#ifndef __mcf5200__ +#ifndef __mcoldfire__ cmpw IMM (1),d4 | remember that the exponent is at least one #else cmpl IMM (1),d4 | remember that the exponent is at least one @@ -2297,7 +2297,7 @@ Lround$to$nearest: addxl d2,d2 | addxl d1,d1 | addxl d0,d0 | -#ifndef __mcf5200__ +#ifndef __mcoldfire__ dbra d4,1b | #else subql IMM (1), d4 @@ -2325,7 +2325,7 @@ Lround$to$nearest: addxl d2,d0 | Shift right once (because we used bit #DBL_MANT_DIG-32!). 2: -#ifndef __mcf5200__ +#ifndef __mcoldfire__ lsrl IMM (1),d0 roxrl IMM (1),d1 #else @@ -2340,7 +2340,7 @@ Lround$to$nearest: | 'fraction overflow' ...). btst IMM (DBL_MANT_DIG-32),d0 beq 1f -#ifndef __mcf5200__ +#ifndef __mcoldfire__ lsrl IMM (1),d0 roxrl IMM (1),d1 addw IMM (1),d4 @@ -2491,7 +2491,7 @@ SYM (__subsf3): | float __addsf3(float, float); SYM (__addsf3): -#ifndef __mcf5200__ +#ifndef __mcoldfire__ link a6,IMM (0) | everything will be done in registers moveml d2-d7,sp@- | save all data registers but d0-d1 #else @@ -2551,7 +2551,7 @@ Laddsf$2: | same, and put the largest exponent in d6. Note that we are using two | registers for each number (see the discussion by D. Knuth in "Seminumerical | Algorithms"). -#ifndef __mcf5200__ +#ifndef __mcoldfire__ cmpw d6,d7 | compare exponents #else cmpl d6,d7 | compare exponents @@ -2561,32 +2561,32 @@ Laddsf$2: 1: subl d6,d7 | keep the largest exponent negl d7 -#ifndef __mcf5200__ +#ifndef __mcoldfire__ lsrw IMM (8),d7 | put difference in lower byte #else lsrl IMM (8),d7 | put difference in lower byte #endif | if difference is too large we don't shift (actually, we can just exit) ' -#ifndef __mcf5200__ +#ifndef __mcoldfire__ cmpw IMM (FLT_MANT_DIG+2),d7 #else cmpl IMM (FLT_MANT_DIG+2),d7 #endif bge Laddsf$b$small -#ifndef __mcf5200__ +#ifndef __mcoldfire__ cmpw IMM (16),d7 | if difference >= 16 swap #else cmpl IMM (16),d7 | if difference >= 16 swap #endif bge 4f 2: -#ifndef __mcf5200__ +#ifndef __mcoldfire__ subw IMM (1),d7 #else subql IMM (1), d7 #endif 3: -#ifndef __mcf5200__ +#ifndef __mcoldfire__ lsrl IMM (1),d2 | shift right second operand roxrl IMM (1),d3 dbra d7,3b @@ -2605,7 +2605,7 @@ Laddsf$2: swap d3 movew d3,d2 swap d2 -#ifndef __mcf5200__ +#ifndef __mcoldfire__ subw IMM (16),d7 #else subl IMM (16),d7 @@ -2613,7 +2613,7 @@ Laddsf$2: bne 2b | if still more bits, go back to normal case bra Laddsf$3 5: -#ifndef __mcf5200__ +#ifndef __mcoldfire__ exg d6,d7 | exchange the exponents #else eorl d6,d7 @@ -2622,32 +2622,32 @@ Laddsf$2: #endif subl d6,d7 | keep the largest exponent negl d7 | -#ifndef __mcf5200__ +#ifndef __mcoldfire__ lsrw IMM (8),d7 | put difference in lower byte #else lsrl IMM (8),d7 | put difference in lower byte #endif | if difference is too large we don't shift (and exit!) ' -#ifndef __mcf5200__ +#ifndef __mcoldfire__ cmpw IMM (FLT_MANT_DIG+2),d7 #else cmpl IMM (FLT_MANT_DIG+2),d7 #endif bge Laddsf$a$small -#ifndef __mcf5200__ +#ifndef __mcoldfire__ cmpw IMM (16),d7 | if difference >= 16 swap #else cmpl IMM (16),d7 | if difference >= 16 swap #endif bge 8f 6: -#ifndef __mcf5200__ +#ifndef __mcoldfire__ subw IMM (1),d7 #else subl IMM (1),d7 #endif 7: -#ifndef __mcf5200__ +#ifndef __mcoldfire__ lsrl IMM (1),d0 | shift right first operand roxrl IMM (1),d1 dbra d7,7b @@ -2666,7 +2666,7 @@ Laddsf$2: swap d1 movew d1,d0 swap d0 -#ifndef __mcf5200__ +#ifndef __mcoldfire__ subw IMM (16),d7 #else subl IMM (16),d7 @@ -2679,7 +2679,7 @@ Laddsf$2: Laddsf$3: | Here we have to decide whether to add or subtract the numbers -#ifndef __mcf5200__ +#ifndef __mcoldfire__ exg d6,a0 | get signs back exg d7,a1 | and save the exponents #else @@ -2696,7 +2696,7 @@ Laddsf$3: | numbers | Here we have both positive or both negative -#ifndef __mcf5200__ +#ifndef __mcoldfire__ exg d6,a0 | now we have the exponent in d6 #else movel d6,d4 @@ -2713,7 +2713,7 @@ Laddsf$3: | Put the exponent, in the first byte, in d2, to use the "standard" rounding | routines: movel d6,d2 -#ifndef __mcf5200__ +#ifndef __mcoldfire__ lsrw IMM (8),d2 #else lsrl IMM (8),d2 @@ -2725,7 +2725,7 @@ Laddsf$3: | one more bit we check this: btst IMM (FLT_MANT_DIG+1),d0 beq 1f -#ifndef __mcf5200__ +#ifndef __mcoldfire__ lsrl IMM (1),d0 roxrl IMM (1),d1 #else @@ -2739,12 +2739,12 @@ Laddsf$3: 1: lea Laddsf$4,a0 | to return from rounding routine lea SYM (_fpCCR),a1 | check the rounding mode -#ifdef __mcf5200__ +#ifdef __mcoldfire__ clrl d6 #endif movew a1@(6),d6 | rounding mode in d6 beq Lround$to$nearest -#ifndef __mcf5200__ +#ifndef __mcoldfire__ cmpw IMM (ROUND_TO_PLUS),d6 #else cmpl IMM (ROUND_TO_PLUS),d6 @@ -2754,14 +2754,14 @@ Laddsf$3: bra Lround$to$plus Laddsf$4: | Put back the exponent, but check for overflow. -#ifndef __mcf5200__ +#ifndef __mcoldfire__ cmpw IMM (0xff),d2 #else cmpl IMM (0xff),d2 #endif bhi 1f bclr IMM (FLT_MANT_DIG-1),d0 -#ifndef __mcf5200__ +#ifndef __mcoldfire__ lslw IMM (7),d2 #else lsll IMM (7),d2 @@ -2787,7 +2787,7 @@ Lsubsf$0: negl d1 negxl d0 1: -#ifndef __mcf5200__ +#ifndef __mcoldfire__ exg d2,a0 | now we have the exponent in d2 lsrw IMM (8),d2 | put it in the first byte #else @@ -2804,12 +2804,12 @@ Lsubsf$0: | the rounding routines themselves. lea Lsubsf$1,a0 | to return from rounding routine lea SYM (_fpCCR),a1 | check the rounding mode -#ifdef __mcf5200__ +#ifdef __mcoldfire__ clrl d6 #endif movew a1@(6),d6 | rounding mode in d6 beq Lround$to$nearest -#ifndef __mcf5200__ +#ifndef __mcoldfire__ cmpw IMM (ROUND_TO_PLUS),d6 #else cmpl IMM (ROUND_TO_PLUS),d6 @@ -2820,7 +2820,7 @@ Lsubsf$0: Lsubsf$1: | Put back the exponent (we can't have overflow!). ' bclr IMM (FLT_MANT_DIG-1),d0 -#ifndef __mcf5200__ +#ifndef __mcoldfire__ lslw IMM (7),d2 #else lsll IMM (7),d2 @@ -2836,7 +2836,7 @@ Laddsf$a$small: movel a6@(12),d0 lea SYM (_fpCCR),a0 movew IMM (0),a0@ -#ifndef __mcf5200__ +#ifndef __mcoldfire__ moveml sp@+,d2-d7 | restore data registers #else moveml sp@,d2-d7 @@ -2850,7 +2850,7 @@ Laddsf$b$small: movel a6@(8),d0 lea SYM (_fpCCR),a0 movew IMM (0),a0@ -#ifndef __mcf5200__ +#ifndef __mcoldfire__ moveml sp@+,d2-d7 | restore data registers #else moveml sp@,d2-d7 @@ -2908,7 +2908,7 @@ Laddsf$ret: lea SYM (_fpCCR),a0 movew IMM (0),a0@ orl d7,d0 | put sign bit -#ifndef __mcf5200__ +#ifndef __mcoldfire__ moveml sp@+,d2-d7 | restore data registers #else moveml sp@,d2-d7 @@ -2975,7 +2975,7 @@ Laddsf$nf: | float __mulsf3(float, float); SYM (__mulsf3): -#ifndef __mcf5200__ +#ifndef __mcoldfire__ link a6,IMM (0) moveml d2-d7,sp@- #else @@ -3010,7 +3010,7 @@ SYM (__mulsf3): andl d5,d0 | and isolate fraction orl d4,d0 | and put hidden bit back swap d2 | I like exponents in the first byte -#ifndef __mcf5200__ +#ifndef __mcoldfire__ lsrw IMM (7),d2 | #else lsrl IMM (7),d2 | @@ -3021,13 +3021,13 @@ Lmulsf$1: | number andl d5,d1 | orl d4,d1 | swap d3 | -#ifndef __mcf5200__ +#ifndef __mcoldfire__ lsrw IMM (7),d3 | #else lsrl IMM (7),d3 | #endif Lmulsf$2: | -#ifndef __mcf5200__ +#ifndef __mcoldfire__ addw d3,d2 | add exponents subw IMM (F_BIAS+1),d2 | and subtract bias (plus one) #else @@ -3060,7 +3060,7 @@ Lmulsf$2: | addl d5,d1 | add a addxl d4,d0 2: -#ifndef __mcf5200__ +#ifndef __mcoldfire__ dbf d3,1b | loop back #else subql IMM (1),d3 @@ -3070,7 +3070,7 @@ Lmulsf$2: | | Now we have the product in d0-d1, with bit (FLT_MANT_DIG - 1) + FLT_MANT_DIG | (mod 32) of d0 set. The first thing to do now is to normalize it so bit | FLT_MANT_DIG is set (to do the rounding). -#ifndef __mcf5200__ +#ifndef __mcoldfire__ rorl IMM (6),d1 swap d1 movew d1,d3 @@ -3089,7 +3089,7 @@ Lmulsf$2: | lsll IMM (8),d0 addl d0,d0 addl d0,d0 -#ifndef __mcf5200__ +#ifndef __mcoldfire__ orw d3,d0 #else orl d3,d0 @@ -3099,7 +3099,7 @@ Lmulsf$2: | btst IMM (FLT_MANT_DIG+1),d0 beq Lround$exit -#ifndef __mcf5200__ +#ifndef __mcoldfire__ lsrl IMM (1),d0 roxrl IMM (1),d1 addw IMM (1),d2 @@ -3143,7 +3143,7 @@ Lmulsf$a$0: bge Lf$inop | if b is +/-INFINITY or NaN return NaN lea SYM (_fpCCR),a0 | else return zero movew IMM (0),a0@ | -#ifndef __mcf5200__ +#ifndef __mcoldfire__ moveml sp@+,d2-d7 | #else moveml sp@,d2-d7 @@ -3161,7 +3161,7 @@ Lmulsf$a$den: movel IMM (1),d2 andl d5,d0 1: addl d0,d0 | shift a left (until bit 23 is set) -#ifndef __mcf5200__ +#ifndef __mcoldfire__ subw IMM (1),d2 | and adjust exponent #else subql IMM (1),d2 | and adjust exponent @@ -3174,7 +3174,7 @@ Lmulsf$b$den: movel IMM (1),d3 andl d5,d1 1: addl d1,d1 | shift b left until bit 23 is set -#ifndef __mcf5200__ +#ifndef __mcoldfire__ subw IMM (1),d3 | and adjust exponent #else subl IMM (1),d3 | and adjust exponent @@ -3189,7 +3189,7 @@ Lmulsf$b$den: | float __divsf3(float, float); SYM (__divsf3): -#ifndef __mcf5200__ +#ifndef __mcoldfire__ link a6,IMM (0) moveml d2-d7,sp@- #else @@ -3226,7 +3226,7 @@ SYM (__divsf3): andl d5,d0 | and isolate fraction orl d4,d0 | and put hidden bit back swap d2 | I like exponents in the first byte -#ifndef __mcf5200__ +#ifndef __mcoldfire__ lsrw IMM (7),d2 | #else lsrl IMM (7),d2 | @@ -3237,13 +3237,13 @@ Ldivsf$1: | andl d5,d1 | orl d4,d1 | swap d3 | -#ifndef __mcf5200__ +#ifndef __mcoldfire__ lsrw IMM (7),d3 | #else lsrl IMM (7),d3 | #endif Ldivsf$2: | -#ifndef __mcf5200__ +#ifndef __mcoldfire__ subw d3,d2 | subtract exponents addw IMM (F_BIAS),d2 | and add bias #else @@ -3270,7 +3270,7 @@ Ldivsf$2: | subl d1,d0 | if a >= b a <-- a-b beq 3f | if a is zero, exit 2: addl d0,d0 | multiply a by 2 -#ifndef __mcf5200__ +#ifndef __mcoldfire__ dbra d3,1b #else subql IMM (1),d3 @@ -3282,7 +3282,7 @@ Ldivsf$2: | 1: cmpl d0,d1 ble 2f addl d0,d0 -#ifndef __mcf5200__ +#ifndef __mcoldfire__ dbra d3,1b #else subql IMM(1),d3 @@ -3291,7 +3291,7 @@ Ldivsf$2: | movel IMM (0),d1 bra 3f 2: movel IMM (0),d1 -#ifndef __mcf5200__ +#ifndef __mcoldfire__ subw IMM (FLT_MANT_DIG),d3 addw IMM (31),d3 #else @@ -3309,7 +3309,7 @@ Ldivsf$2: | btst IMM (FLT_MANT_DIG+1),d0 beq 1f | if it is not set, then bit 24 is set lsrl IMM (1),d0 | -#ifndef __mcf5200__ +#ifndef __mcoldfire__ addw IMM (1),d2 | #else addl IMM (1),d2 | @@ -3343,7 +3343,7 @@ Ldivsf$a$0: movel IMM (0),d0 | else return zero lea SYM (_fpCCR),a0 | movew IMM (0),a0@ | -#ifndef __mcf5200__ +#ifndef __mcoldfire__ moveml sp@+,d2-d7 | #else moveml sp@,d2-d7 | @@ -3375,7 +3375,7 @@ Ldivsf$a$den: movel IMM (1),d2 andl d5,d0 1: addl d0,d0 | shift a left until bit FLT_MANT_DIG-1 is set -#ifndef __mcf5200__ +#ifndef __mcoldfire__ subw IMM (1),d2 | and adjust exponent #else subl IMM (1),d2 | and adjust exponent @@ -3388,7 +3388,7 @@ Ldivsf$b$den: movel IMM (1),d3 andl d5,d1 1: addl d1,d1 | shift b left until bit FLT_MANT_DIG is set -#ifndef __mcf5200__ +#ifndef __mcoldfire__ subw IMM (1),d3 | and adjust exponent #else subl IMM (1),d3 | and adjust exponent @@ -3401,7 +3401,7 @@ Lround$exit: | This is a common exit point for __mulsf3 and __divsf3. | First check for underlow in the exponent: -#ifndef __mcf5200__ +#ifndef __mcoldfire__ cmpw IMM (-FLT_MANT_DIG-1),d2 #else cmpl IMM (-FLT_MANT_DIG-1),d2 @@ -3412,14 +3412,14 @@ Lround$exit: | exponent until it becomes 1 or the fraction is zero (in the latter case | we signal underflow and return zero). movel IMM (0),d6 | d6 is used temporarily -#ifndef __mcf5200__ +#ifndef __mcoldfire__ cmpw IMM (1),d2 | if the exponent is less than 1 we #else cmpl IMM (1),d2 | if the exponent is less than 1 we #endif bge 2f | have to shift right (denormalize) 1: -#ifndef __mcf5200__ +#ifndef __mcoldfire__ addw IMM (1),d2 | adjust the exponent lsrl IMM (1),d0 | shift right once roxrl IMM (1),d1 | @@ -3446,12 +3446,12 @@ Lround$exit: | Now call the rounding routine (which takes care of denormalized numbers): lea Lround$0,a0 | to return from rounding routine lea SYM (_fpCCR),a1 | check the rounding mode -#ifdef __mcf5200__ +#ifdef __mcoldfire__ clrl d6 #endif movew a1@(6),d6 | rounding mode in d6 beq Lround$to$nearest -#ifndef __mcf5200__ +#ifndef __mcoldfire__ cmpw IMM (ROUND_TO_PLUS),d6 #else cmpl IMM (ROUND_TO_PLUS),d6 @@ -3467,7 +3467,7 @@ Lround$0: | check again for underflow!). We have to check for overflow or for a | denormalized number (which also signals underflow). | Check for overflow (i.e., exponent >= 255). -#ifndef __mcf5200__ +#ifndef __mcoldfire__ cmpw IMM (0x00ff),d2 #else cmpl IMM (0x00ff),d2 @@ -3478,14 +3478,14 @@ Lround$0: beq Lf$den 1: | Put back the exponents and sign and return. -#ifndef __mcf5200__ +#ifndef __mcoldfire__ lslw IMM (7),d2 | exponent back to fourth byte #else lsll IMM (7),d2 | exponent back to fourth byte #endif bclr IMM (FLT_MANT_DIG-1),d0 swap d0 | and put back exponent -#ifndef __mcf5200__ +#ifndef __mcoldfire__ orw d2,d0 | #else orl d2,d0 @@ -3495,7 +3495,7 @@ Lround$0: lea SYM (_fpCCR),a0 movew IMM (0),a0@ -#ifndef __mcf5200__ +#ifndef __mcoldfire__ moveml sp@+,d2-d7 #else moveml sp@,d2-d7 @@ -3514,7 +3514,7 @@ Lround$0: | float __negsf2(float); SYM (__negsf2): -#ifndef __mcf5200__ +#ifndef __mcoldfire__ link a6,IMM (0) moveml d2-d7,sp@- #else @@ -3536,7 +3536,7 @@ SYM (__negsf2): bra Lf$infty 1: lea SYM (_fpCCR),a0 movew IMM (0),a0@ -#ifndef __mcf5200__ +#ifndef __mcoldfire__ moveml sp@+,d2-d7 #else moveml sp@,d2-d7 @@ -3558,7 +3558,7 @@ EQUAL = 0 | int __cmpsf2(float, float); SYM (__cmpsf2): -#ifndef __mcf5200__ +#ifndef __mcoldfire__ link a6,IMM (0) moveml d2-d7,sp@- | save registers #else @@ -3595,7 +3595,7 @@ Lcmpsf$2: tstl d6 bpl 1f | If both are negative exchange them -#ifndef __mcf5200__ +#ifndef __mcoldfire__ exg d0,d1 #else movel d0,d7 @@ -3610,7 +3610,7 @@ Lcmpsf$2: bne Lcmpsf$a$gt$b | |b| < |a| | If we got here a == b. movel IMM (EQUAL),d0 -#ifndef __mcf5200__ +#ifndef __mcoldfire__ moveml sp@+,d2-d7 | put back the registers #else moveml sp@,d2-d7 @@ -3619,7 +3619,7 @@ Lcmpsf$2: rts Lcmpsf$a$gt$b: movel IMM (GREATER),d0 -#ifndef __mcf5200__ +#ifndef __mcoldfire__ moveml sp@+,d2-d7 | put back the registers #else moveml sp@,d2-d7 @@ -3630,7 +3630,7 @@ Lcmpsf$a$gt$b: rts Lcmpsf$b$gt$a: movel IMM (LESS),d0 -#ifndef __mcf5200__ +#ifndef __mcoldfire__ moveml sp@+,d2-d7 | put back the registers #else moveml sp@,d2-d7 @@ -3668,7 +3668,7 @@ Lround$to$nearest: | Normalize shifting left until bit #FLT_MANT_DIG is set or the exponent | is one (remember that a denormalized number corresponds to an | exponent of -F_BIAS+1). -#ifndef __mcf5200__ +#ifndef __mcoldfire__ cmpw IMM (1),d2 | remember that the exponent is at least one #else cmpl IMM (1),d2 | remember that the exponent is at least one @@ -3676,7 +3676,7 @@ Lround$to$nearest: beq 2f | an exponent of one means denormalized addl d1,d1 | else shift and adjust the exponent addxl d0,d0 | -#ifndef __mcf5200__ +#ifndef __mcoldfire__ dbra d2,1b | #else subql IMM (1),d2 @@ -3705,7 +3705,7 @@ Lround$to$nearest: btst IMM (FLT_MANT_DIG),d0 beq 1f lsrl IMM (1),d0 -#ifndef __mcf5200__ +#ifndef __mcoldfire__ addw IMM (1),d2 #else addql IMM (1),d2 diff --git a/gcc/config/m68k/linux.h b/gcc/config/m68k/linux.h index efedd4f2d1e..99996a4e670 100644 --- a/gcc/config/m68k/linux.h +++ b/gcc/config/m68k/linux.h @@ -171,7 +171,7 @@ Boston, MA 02111-1307, USA. */ #undef ASM_OUTPUT_CASE_LABEL #define ASM_RETURN_CASE_JUMP \ do { \ - if (TARGET_5200) \ + if (TARGET_COLDFIRE) \ { \ if (ADDRESS_REG_P (operands[0])) \ return "jmp %%pc@(2,%0:l)"; \ diff --git a/gcc/config/m68k/m68k-none.h b/gcc/config/m68k/m68k-none.h index 0c9514b89ca..8bd885521e3 100644 --- a/gcc/config/m68k/m68k-none.h +++ b/gcc/config/m68k/m68k-none.h @@ -91,7 +91,7 @@ Unrecognized value in TARGET_CPU_DEFAULT. #undef CPP_FPU_SPEC #if TARGET_DEFAULT & MASK_68881 #define CPP_FPU_SPEC "\ -%{!mc68000:%{!m68000:%{!m68302:%{!mcpu32:%{!m68332:%{!m5200:%{!msoft-float:%{!mno-68881:-D__HAVE_68881__ }}}}}}}} \ +%{!mc68000:%{!m68000:%{!m68302:%{!mcpu32:%{!m68332:%{!m5200:%{!m5206e:%{!m528x:%{!m5307:%{!m5407:%{!msoft-float:%{!mno-68881:-D__HAVE_68881__ }}}}}}}}}}}} \ %{m68881:-D__HAVE_68881__ }" #else #define CPP_FPU_SPEC "\ @@ -113,7 +113,12 @@ Unrecognized value in TARGET_CPU_DEFAULT. -m68302: define mc68302 -m68332: define mc68332 mcpu32 -mcpu32: define mcpu32 - -m5200: define mcf5200 + -m5200: define mcoldfire mcf5200 + -m5206e: define mcoldfire mcf5200 mcf5206e + -m528x: define mcoldfire mc5200 mc528x + -m5307: define mcoldfire mc5300 mc5307 + -m5407: define mcoldfire mc5400 mc5407 + default: define as above appropriately GCC won't automatically add __'d versions, we have to mention them @@ -121,9 +126,13 @@ Unrecognized value in TARGET_CPU_DEFAULT. #undef CPP_SPEC #define CPP_SPEC "\ -%(cpp_fpu)%{!ansi:%{m68302:-Dmc68302 }%{m68010:-Dmc68010 }%{m68020:-Dmc68020 }%{mc68020:-Dmc68020 }%{m68030:-Dmc68030 }%{m68040:-Dmc68040 }%{m68020-40:-Dmc68020 -Dmc68030 -Dmc68040 }%{m68020-60:-Dmc68020 -Dmc68030 -Dmc68040 -Dmc68060 }%{m68060:-Dmc68060 }%{mcpu32:-Dmcpu32 } %{m68332:-Dmc68332 -Dmcpu32 }%{m5200:-Dmcf5200 }} \ -%{m68302:-D__mc68302__ -D__mc68302 }%{m68010:-D__mc68010__ -D__mc68010 }%{m68020:-D__mc68020__ -D__mc68020 }%{mc68020:-D__mc68020__ -D__mc68020 }%{m68030:-D__mc68030__ -D__mc68030 }%{m68040:-D__mc68040__ -D__mc68040 }%{m68020-40:-D__mc68020__ -D__mc68030__ -D__mc68040__ -D__mc68020 -D__mc68030 -D__mc68040 }%{m68020-60:-D__mc68020__ -D__mc68030__ -D__mc68040__ -D__mc68020 -D__mc68030 -D__mc68040 -D__mc68060__ -D__mc68060 }%{m68060:-D__mc68060__ -D__mc68060 }%{mcpu32:-D__mcpu32__ -D__mcpu32 }%{m68332:-D__mc68332__ -D__mc68332 -D__mcpu32__ -D__mcpu32 }%{m5200:-D__mcf5200__ -D__mcf5200 } \ -%{!mc68000:%{!m68000:%{!m68302:%{!m68010:%{!mc68020:%{!m68020:%{!m68030:%{!m68040:%{!m68020-40:%{!m68020-60:%{!m68060:%{!mcpu32: %{!m68332:%{!m5200:%(cpp_cpu_default)}}}}}}}}}}}}}} \ +%(cpp_fpu)%{!ansi:%{m68302:-Dmc68302 }%{m68010:-Dmc68010 }%{m68020:-Dmc68020 }%{mc68020:-Dmc68020 }%{m68030:-Dmc68030 }%{m68040:-Dmc68040 }%{m68020-40:-Dmc68020 -Dmc68030 -Dmc68040 }%{m68020-60:-Dmc68020 -Dmc68030 -Dmc68040 -Dmc68060 }%{m68060:-Dmc68060 }%{mcpu32:-Dmcpu32 } %{m68332:-Dmc68332 -Dmcpu32 }%{m5200:-Dmcoldfire -Dmcf5200 }%{m5206e:-Dmcoldfire -Dmcf5200 -Dmcf5206e }%{m528x:-Dmcoldfire -Dmcf5200 -Dmcf528x }%{m5307:-Dmcoldfire -Dmcf5300 -Dmcf5307 }%{m5407: -Dmcoldfire -Dmcf5400 -Dmcf5407 }} \ +%{m68302:-D__mc68302__ -D__mc68302 }%{m68010:-D__mc68010__ -D__mc68010 }%{m68020:-D__mc68020__ -D__mc68020 }%{mc68020:-D__mc68020__ -D__mc68020 }%{m68030:-D__mc68030__ -D__mc68030 }%{m68040:-D__mc68040__ -D__mc68040 }%{m68020-40:-D__mc68020__ -D__mc68030__ -D__mc68040__ -D__mc68020 -D__mc68030 -D__mc68040 }%{m68020-60:-D__mc68020__ -D__mc68030__ -D__mc68040__ -D__mc68020 -D__mc68030 -D__mc68040 -D__mc68060__ -D__mc68060 }%{m68060:-D__mc68060__ -D__mc68060 }%{mcpu32:-D__mcpu32__ -D__mcpu32 }%{m68332:-D__mc68332__ -D__mc68332 -D__mcpu32__ -D__mcpu32 }%{m5200:-D__mcf5200__ -D__mcf5200 -D__mcoldfire__ } \ +%{m5206e:-D__mcoldfire__ -D__mcf5200__ -D__mcf5200 -D__mcf5206e__ -D__mcf5206e } \ +%{m528x:-D__mcoldfire__ -D__mcf5200__ -D__mcf5200 -D__mcf528x__ -D__mcf528x } \ +%{m5307:-D__mcoldfire__ -D__mcf5300__ -D__mcf5300 -D__mcf5307__ -D__mcf5307 } \ +%{m5407:-D__mcoldfire__ -D__mcf5400__ -D__mcf5400 -D__mcf5407__ -D__mcf5407 } \ +%{!mc68000:%{!m68000:%{!m68302:%{!m68010:%{!mc68020:%{!m68020:%{!m68030:%{!m68040:%{!m68020-40:%{!m68020-60:%{!m68060:%{!mcpu32: %{!m68332:%{!m5200:%{!m5206e:%{!m528x:%{!m5307:%{!m5407:%(cpp_cpu_default)}}}}}}}}}}}}}}}}}} \ %(cpp_subtarget) \ " @@ -131,7 +140,7 @@ Unrecognized value in TARGET_CPU_DEFAULT. #undef ASM_SPEC #define ASM_SPEC "\ -%{m68851}%{mno-68851}%{m68881}%{mno-68881}%{msoft-float:-mno-68881} %{m68000}%{m68302}%{mc68000}%{m68010}%{m68020}%{mc68020}%{m68030}%{m68040}%{m68020-40:-mc68040} %{m68020-60:-mc68040} %{m68060}%{mcpu32}%{m68332}%{m5200}%{!mc68000:%{!m68000:%{!m68302:%{!m68010:%{!mc68020:%{!m68020:%{!m68030:%{!m68040:%{!m68020-40:%{!m68020-60:%{!m68060:%{!mcpu32:%{!m68332:%{!m5200:%(asm_cpu_default)}}}}}}}}}}}}}} \ +%{m68851}%{mno-68851}%{m68881}%{mno-68881}%{msoft-float:-mno-68881} %{m68000}%{m68302}%{mc68000}%{m68010}%{m68020}%{mc68020}%{m68030}%{m68040}%{m68020-40:-mc68040} %{m68020-60:-mc68040} %{m68060}%{mcpu32}%{m68332}%{m5200}%{m5206e}%{m528x}%{m5307}%{m5407}%{!mc68000:%{!m68000:%{!m68302:%{!m68010:%{!mc68020:%{!m68020:%{!m68030:%{!m68040:%{!m68020-40:%{!m68020-60:%{!m68060:%{!mcpu32:%{!m68332:%{!m5200:%{!m5206e:%{!m528x:%{!m5307:%{!m5407:%(asm_cpu_default)}}}}}}}}}}}}}}}}}} \ " /* cc1/cc1plus always receives all the -m flags. If the specs strings above diff --git a/gcc/config/m68k/m68k.c b/gcc/config/m68k/m68k.c index 31da70bf609..e304a655962 100644 --- a/gcc/config/m68k/m68k.c +++ b/gcc/config/m68k/m68k.c @@ -347,7 +347,7 @@ m68k_output_function_prologue (stream, size) { if (fsize + 4 <= 8) { - if (!TARGET_5200) + if (!TARGET_COLDFIRE) { /* asm_fprintf() cannot handle %. */ #ifdef MOTOROLA @@ -511,7 +511,7 @@ m68k_output_function_prologue (stream, size) } else if (mask) { - if (TARGET_5200) + if (TARGET_COLDFIRE) { /* The coldfire does not support the predecrement form of the movml instruction, so we must adjust the stack pointer and @@ -666,7 +666,7 @@ m68k_output_function_epilogue (stream, size) #endif fsize = 0, big = 1; } - if (TARGET_5200 || nregs <= 2) + if (TARGET_COLDFIRE || nregs <= 2) { /* Restore each separately in the same order moveml does. Using two movel instructions instead of a single moveml @@ -799,7 +799,7 @@ m68k_output_function_epilogue (stream, size) { if (fsize + 4 <= 8) { - if (!TARGET_5200) + if (!TARGET_COLDFIRE) { #ifdef MOTOROLA asm_fprintf (stream, "\taddq.w %I%wd,%Rsp\n", fsize + 4); @@ -1091,7 +1091,7 @@ output_scc_di(op, operand1, operand2, dest) } else { - if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (loperands[0])) + if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (loperands[0])) output_asm_insn ("tst%.l %0", loperands); else { @@ -1108,7 +1108,7 @@ output_scc_di(op, operand1, operand2, dest) output_asm_insn ("jne %l4", loperands); #endif - if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (loperands[1])) + if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (loperands[1])) output_asm_insn ("tst%.l %1", loperands); else { @@ -1426,7 +1426,7 @@ const_method (constant) /* The Coldfire doesn't have byte or word operations. */ /* FIXME: This may not be useful for the m68060 either */ - if (!TARGET_5200) + if (!TARGET_COLDFIRE) { /* if -256 < N < 256 but N is not in range for a moveq N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */ @@ -1630,7 +1630,7 @@ output_move_simode_const (operands) || GET_CODE (operands[0]) == MEM) /* clr insns on 68000 read before writing. This isn't so on the 68010, but we have no TARGET_68010. */ - && ((TARGET_68020 || TARGET_5200) + && ((TARGET_68020 || TARGET_COLDFIRE) || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))) return "clr%.l %0"; @@ -1680,7 +1680,7 @@ output_move_himode (operands) || GET_CODE (operands[0]) == MEM) /* clr insns on 68000 read before writing. This isn't so on the 68010, but we have no TARGET_68010. */ - && ((TARGET_68020 || TARGET_5200) + && ((TARGET_68020 || TARGET_COLDFIRE) || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))) return "clr%.w %0"; @@ -1746,7 +1746,7 @@ output_move_qimode (operands) && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC && XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx && ! ADDRESS_REG_P (operands[1]) - && ! TARGET_5200) + && ! TARGET_COLDFIRE) { xoperands[1] = operands[1]; xoperands[2] @@ -1767,12 +1767,12 @@ output_move_qimode (operands) /* clr and st insns on 68000 read before writing. This isn't so on the 68010, but we have no TARGET_68010. */ if (!ADDRESS_REG_P (operands[0]) - && ((TARGET_68020 || TARGET_5200) + && ((TARGET_68020 || TARGET_COLDFIRE) || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))) { if (operands[1] == const0_rtx) return "clr%.b %0"; - if ((!TARGET_5200 || DATA_REG_P (operands[0])) + if ((!TARGET_COLDFIRE || DATA_REG_P (operands[0])) && GET_CODE (operands[1]) == CONST_INT && (INTVAL (operands[1]) & 255) == 255) { @@ -1805,7 +1805,7 @@ output_move_stricthi (operands) if (operands[1] == const0_rtx /* clr insns on 68000 read before writing. This isn't so on the 68010, but we have no TARGET_68010. */ - && ((TARGET_68020 || TARGET_5200) + && ((TARGET_68020 || TARGET_COLDFIRE) || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))) return "clr%.w %0"; return "move%.w %1,%0"; @@ -1818,7 +1818,7 @@ output_move_strictqi (operands) if (operands[1] == const0_rtx /* clr insns on 68000 read before writing. This isn't so on the 68010, but we have no TARGET_68010. */ - && ((TARGET_68020 || TARGET_5200) + && ((TARGET_68020 || TARGET_COLDFIRE) || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))) return "clr%.b %0"; return "move%.b %1,%0"; @@ -3303,7 +3303,7 @@ output_andsi3 (operands) && (INTVAL (operands[2]) | 0xffff) == 0xffffffff && (DATA_REG_P (operands[0]) || offsettable_memref_p (operands[0])) - && !TARGET_5200) + && !TARGET_COLDFIRE) { if (GET_CODE (operands[0]) != REG) operands[0] = adjust_address (operands[0], HImode, 2); @@ -3344,7 +3344,7 @@ output_iorsi3 (operands) && INTVAL (operands[2]) >> 16 == 0 && (DATA_REG_P (operands[0]) || offsettable_memref_p (operands[0])) - && !TARGET_5200) + && !TARGET_COLDFIRE) { if (GET_CODE (operands[0]) != REG) operands[0] = adjust_address (operands[0], HImode, 2); @@ -3380,7 +3380,7 @@ output_xorsi3 (operands) if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >> 16 == 0 && (offsettable_memref_p (operands[0]) || DATA_REG_P (operands[0])) - && !TARGET_5200) + && !TARGET_COLDFIRE) { if (! DATA_REG_P (operands[0])) operands[0] = adjust_address (operands[0], HImode, 2); diff --git a/gcc/config/m68k/m68k.h b/gcc/config/m68k/m68k.h index 8ee78ba9aa9..808a93a73d0 100644 --- a/gcc/config/m68k/m68k.h +++ b/gcc/config/m68k/m68k.h @@ -143,6 +143,30 @@ extern int target_flags; #define MASK_NO_STRICT_ALIGNMENT 16384 #define TARGET_STRICT_ALIGNMENT (~target_flags & MASK_NO_STRICT_ALIGNMENT) +/* Build for ColdFire v3 */ +#define MASK_CFV3 0x8000 +#define TARGET_CFV3 (target_flags & MASK_CFV3) + +/* Build for ColdFire v4 */ +#define MASK_CFV4 0x10000 +#define TARGET_CFV4 (target_flags & MASK_CFV4) + +/* Divide support for ColdFire */ +#define MASK_CF_HWDIV 0x40000 +#define TARGET_CF_HWDIV (target_flags & MASK_CF_HWDIV) + +/* Compile for mcf582 */ +#define MASK_528x 0x80000 +#define TARGET_528x (target_flags & MASK_528x) + + +/* Is the target a coldfire */ +#define MASK_COLDFIRE (MASK_5200|MASK_528x|MASK_CFV3|MASK_CFV4) +#define TARGET_COLDFIRE (target_flags & MASK_COLDFIRE) + +/* Which bits can be set by specifying a coldfire */ +#define MASK_ALL_CF_BITS (MASK_COLDFIRE|MASK_CF_HWDIV) + /* Macro to define tables used to set the flags. This is a list in braces of pairs in braces, each pair being { "NAME", VALUE } @@ -150,16 +174,16 @@ extern int target_flags; An empty string NAME is used to identify the default VALUE. */ #define TARGET_SWITCHES \ - { { "68020", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY), \ + { { "68020", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY), \ N_("Generate code for a 68020") }, \ - { "c68020", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY), \ + { "c68020", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY), \ N_("Generate code for a 68020") }, \ { "68020", (MASK_68020|MASK_BITFIELD), "" }, \ { "c68020", (MASK_68020|MASK_BITFIELD), "" }, \ - { "68000", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \ + { "68000", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \ |MASK_68020|MASK_BITFIELD|MASK_68881), \ N_("Generate code for a 68000") }, \ - { "c68000", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \ + { "c68000", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \ |MASK_68020|MASK_BITFIELD|MASK_68881), \ N_("Generate code for a 68000") }, \ { "bitfield", MASK_BITFIELD, \ @@ -177,40 +201,56 @@ extern int target_flags; { "68881", MASK_68881, "" }, \ { "soft-float", - (MASK_68040_ONLY|MASK_68881), \ N_("Generate code with library calls for floating point") }, \ - { "68020-40", -(MASK_5200|MASK_68060|MASK_68040_ONLY), \ + { "68020-40", -(MASK_ALL_CF_BITS|MASK_68060|MASK_68040_ONLY), \ N_("Generate code for a 68040, without any new instructions") }, \ { "68020-40", (MASK_BITFIELD|MASK_68881|MASK_68020|MASK_68040), ""},\ - { "68020-60", -(MASK_5200|MASK_68040_ONLY), \ + { "68020-60", -(MASK_ALL_CF_BITS|MASK_68040_ONLY), \ N_("Generate code for a 68060, without any new instructions") }, \ { "68020-60", (MASK_BITFIELD|MASK_68881|MASK_68020|MASK_68040 \ |MASK_68060), "" }, \ - { "68030", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY), \ + { "68030", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY), \ N_("Generate code for a 68030") }, \ { "68030", (MASK_68020|MASK_BITFIELD), "" }, \ - { "68040", - (MASK_5200|MASK_68060), \ + { "68040", - (MASK_ALL_CF_BITS|MASK_68060), \ N_("Generate code for a 68040") }, \ { "68040", (MASK_68020|MASK_68881|MASK_BITFIELD \ |MASK_68040_ONLY|MASK_68040), "" }, \ - { "68060", - (MASK_5200|MASK_68040), \ + { "68060", - (MASK_ALL_CF_BITS|MASK_68040), \ N_("Generate code for a 68060") }, \ { "68060", (MASK_68020|MASK_68881|MASK_BITFIELD \ |MASK_68040_ONLY|MASK_68060), "" }, \ - { "5200", - (MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \ + { "5200", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \ |MASK_BITFIELD|MASK_68881), \ N_("Generate code for a 520X") }, \ { "5200", (MASK_5200), "" }, \ + { "5206e", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \ + |MASK_BITFIELD|MASK_68881), \ + N_("Generate code for a 5206e") }, \ + { "5206e", (MASK_5200|MASK_CF_HWDIV), "" }, \ + { "528x", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \ + |MASK_BITFIELD|MASK_68881), \ + N_("Generate code for a 528x") }, \ + { "528x", (MASK_528x|MASK_CF_HWDIV), "" }, \ + { "5307", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \ + |MASK_BITFIELD|MASK_68881), \ + N_("Generate code for a 5307") }, \ + { "5307", (MASK_CFV3|MASK_CF_HWDIV), "" }, \ + { "5407", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \ + |MASK_BITFIELD|MASK_68881), \ + N_("Generate code for a 5407") }, \ + { "5407", (MASK_CFV4|MASK_CF_HWDIV), "" }, \ { "68851", 0, \ N_("Generate code for a 68851") }, \ { "no-68851", 0, \ N_("Do no generate code for a 68851") }, \ - { "68302", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \ + { "68302", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \ |MASK_68020|MASK_BITFIELD|MASK_68881), \ N_("Generate code for a 68302") }, \ - { "68332", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \ + { "68332", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \ |MASK_BITFIELD|MASK_68881), \ N_("Generate code for a 68332") }, \ { "68332", MASK_68020, "" }, \ - { "cpu32", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \ + { "cpu32", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \ |MASK_BITFIELD|MASK_68881), \ N_("Generate code for a cpu32") }, \ { "cpu32", MASK_68020, "" }, \ @@ -688,12 +728,12 @@ enum reg_class { this says how many the stack pointer really advances by. On the 68000, sp@- in a byte insn really pushes a word. On the 5200 (coldfire), sp@- in a byte insn pushes just a byte. */ -#define PUSH_ROUNDING(BYTES) (TARGET_5200 ? BYTES : ((BYTES) + 1) & ~1) +#define PUSH_ROUNDING(BYTES) (TARGET_COLDFIRE ? BYTES : ((BYTES) + 1) & ~1) /* We want to avoid trying to push bytes. */ #define MOVE_BY_PIECES_P(SIZE, ALIGN) \ (move_by_pieces_ninsns (SIZE, ALIGN) < MOVE_RATIO \ - && (((SIZE) >=16 && (ALIGN) >= 16) || (TARGET_5200))) + && (((SIZE) >=16 && (ALIGN) >= 16) || (TARGET_COLDFIRE))) /* Offset of first parameter from the argument pointer register value. */ #define FIRST_PARM_OFFSET(FNDECL) 8 @@ -1122,7 +1162,7 @@ __transfer_from_trampoline () \ /* coldfire/5200 does not allow HImode index registers. */ #define LEGITIMATE_INDEX_REG_P(X) \ ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \ - || (! TARGET_5200 \ + || (! TARGET_COLDFIRE \ && GET_CODE (X) == SIGN_EXTEND \ && GET_CODE (XEXP (X, 0)) == REG \ && GET_MODE (XEXP (X, 0)) == HImode \ @@ -1133,12 +1173,12 @@ __transfer_from_trampoline () \ #define LEGITIMATE_INDEX_P(X) \ (LEGITIMATE_INDEX_REG_P (X) \ - || ((TARGET_68020 || TARGET_5200) && GET_CODE (X) == MULT \ + || ((TARGET_68020 || TARGET_COLDFIRE) && GET_CODE (X) == MULT \ && LEGITIMATE_INDEX_REG_P (XEXP (X, 0)) \ && GET_CODE (XEXP (X, 1)) == CONST_INT \ && (INTVAL (XEXP (X, 1)) == 2 \ || INTVAL (XEXP (X, 1)) == 4 \ - || (INTVAL (XEXP (X, 1)) == 8 && !TARGET_5200)))) + || (INTVAL (XEXP (X, 1)) == 8 && !TARGET_COLDFIRE)))) /* If pic, we accept INDEX+LABEL, which is what do_tablejump makes. */ #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md index 68c665cc214..1917717076d 100644 --- a/gcc/config/m68k/m68k.md +++ b/gcc/config/m68k/m68k.md @@ -24,7 +24,7 @@ ;;- The MCF5200 "ColdFire" architecture is a reduced version of the ;;- 68k ISA. Differences include reduced support for byte and word ;;- operands and the removal of BCD, bitfield, rotate, and integer -;;- divide instructions. The TARGET_5200 flag turns the use of the +;;- divide instructions. The TARGET_COLDFIRE flag turns the use of the ;;- removed opcodes and addressing modes off. ;;- @@ -199,7 +199,7 @@ "" "* { - if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0])) + if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (operands[0])) return \"tst%.l %0\"; /* If you think that the 68020 does not support tstl a0, reread page B-167 of the 68020 manual more carefully. */ @@ -333,7 +333,7 @@ [(set (cc0) (compare (match_operand:SI 0 "nonimmediate_operand" "rKT,rKs,mSr,mSa,>") (match_operand:SI 1 "general_src_operand" "mSr,mSa,KTr,Ksr,>")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) @@ -373,7 +373,7 @@ [(set (cc0) (compare (match_operand:SI 0 "nonimmediate_operand" "mrKs,r") (match_operand:SI 1 "general_operand" "r,mrKs")))] - "TARGET_5200" + "TARGET_COLDFIRE" "* { if (REG_P (operands[1]) @@ -396,14 +396,14 @@ [(set (cc0) (compare (match_operand:HI 0 "nonimmediate_src_operand" "") (match_operand:HI 1 "general_src_operand" "")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "m68k_last_compare_had_fp_operands = 0;") (define_insn "" [(set (cc0) (compare (match_operand:HI 0 "nonimmediate_src_operand" "rnmS,d,n,mS,>") (match_operand:HI 1 "general_src_operand" "d,rnmS,mS,n,>")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) @@ -432,14 +432,14 @@ [(set (cc0) (compare (match_operand:QI 0 "nonimmediate_src_operand" "") (match_operand:QI 1 "general_src_operand" "")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "m68k_last_compare_had_fp_operands = 0;") (define_insn "" [(set (cc0) (compare (match_operand:QI 0 "nonimmediate_src_operand" "dn,dmS,>") (match_operand:QI 1 "general_src_operand" "dmS,nd,>")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) @@ -557,7 +557,7 @@ (const_int 1) (minus:SI (const_int 7) (match_operand:SI 1 "general_operand" "di"))))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { return output_btst (operands, operands[1], operands[0], insn, 7); }") ;; This is the same as the above pattern except for the constraints. The 'i' @@ -568,7 +568,7 @@ (const_int 1) (minus:SI (const_int 7) (match_operand:SI 1 "general_operand" "d"))))] - "TARGET_5200" + "TARGET_COLDFIRE" "* { return output_btst (operands, operands[1], operands[0], insn, 7); }") (define_insn "" @@ -609,7 +609,7 @@ [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m") (const_int 1) (match_operand:SI 1 "const_int_operand" "n")))] - "(unsigned) INTVAL (operands[1]) < 8 && !TARGET_5200" + "(unsigned) INTVAL (operands[1]) < 8 && !TARGET_COLDFIRE" "* { operands[1] = GEN_INT (7 - INTVAL (operands[1])); @@ -620,7 +620,7 @@ [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "do") (const_int 1) (match_operand:SI 1 "const_int_operand" "n")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { if (GET_CODE (operands[0]) == MEM) @@ -641,7 +641,7 @@ [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "dQ") (const_int 1) (match_operand:SI 1 "const_int_operand" "n")))] - "TARGET_5200" + "TARGET_COLDFIRE" "* { if (GET_CODE (operands[0]) == MEM) @@ -688,7 +688,7 @@ (const_int 0))] ;; clr insns on 68000 read before writing. ;; This isn't so on the 68010, but we have no TARGET_68010. - "((TARGET_68020 || TARGET_5200) + "((TARGET_68020 || TARGET_COLDFIRE) || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))" "* { @@ -712,7 +712,7 @@ } } /* moveq is faster on the 68000. */ - if (DATA_REG_P (operands[0]) && (!TARGET_68020 && !TARGET_5200)) + if (DATA_REG_P (operands[0]) && (!TARGET_68020 && !TARGET_COLDFIRE)) return \"moveq %#0,%0\"; return \"clr%.l %0\"; }") @@ -763,7 +763,7 @@ [(set (match_operand:SI 0 "nonimmediate_operand" "=g,d,a<") (match_operand:SI 1 "general_src_operand" "daymSKT,n,i"))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { return output_move_simode (operands); @@ -772,7 +772,7 @@ (define_insn "" [(set (match_operand:SI 0 "nonimmediate_operand" "=r,g") (match_operand:SI 1 "general_operand" "g,r"))] - "TARGET_5200" + "TARGET_COLDFIRE" "* return output_move_simode (operands);") ;; Special case of fullword move, where we need to get a non-GOT PIC @@ -797,13 +797,13 @@ (define_insn "" [(set (match_operand:HI 0 "nonimmediate_operand" "=g") (match_operand:HI 1 "general_src_operand" "gS"))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* return output_move_himode (operands);") (define_insn "" [(set (match_operand:HI 0 "nonimmediate_operand" "=r,g") (match_operand:HI 1 "general_operand" "g,r"))] - "TARGET_5200" + "TARGET_COLDFIRE" "* return output_move_himode (operands);") (define_expand "movstricthi" @@ -815,13 +815,13 @@ (define_insn "" [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm")) (match_operand:HI 1 "general_src_operand" "rmSn"))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* return output_move_stricthi (operands);") (define_insn "" [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+d,m")) (match_operand:HI 1 "general_src_operand" "rmn,r"))] - "TARGET_5200" + "TARGET_COLDFIRE" "* return output_move_stricthi (operands);") (define_expand "movqi" @@ -833,13 +833,13 @@ (define_insn "" [(set (match_operand:QI 0 "nonimmediate_operand" "=d,*a,m") (match_operand:QI 1 "general_src_operand" "dmSi*a,di*a,dmSi"))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* return output_move_qimode (operands);") (define_insn "" [(set (match_operand:QI 0 "nonimmediate_operand" "=d,dm,d*a") (match_operand:QI 1 "general_src_operand" "dmi,d,di*a"))] - "TARGET_5200" + "TARGET_COLDFIRE" "* return output_move_qimode (operands);") (define_expand "movstrictqi" @@ -851,20 +851,20 @@ (define_insn "" [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm")) (match_operand:QI 1 "general_src_operand" "dmSn"))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* return output_move_strictqi (operands);") (define_insn "" [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+d,m")) (match_operand:QI 1 "general_src_operand" "dmn,d"))] - "TARGET_5200" + "TARGET_COLDFIRE" "* return output_move_strictqi (operands);") (define_expand "pushqi1" [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int -2))) (set (mem:QI (plus:SI (reg:SI 15) (const_int 1))) (match_operand:QI 0 "general_operand" ""))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "") (define_expand "movsf" @@ -876,7 +876,7 @@ (define_insn "" [(set (match_operand:SF 0 "nonimmediate_operand" "=rmf") (match_operand:SF 1 "general_operand" "rmfF"))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { if (FP_REG_P (operands[0])) @@ -898,7 +898,7 @@ if (operands[1] == CONST0_RTX (SFmode) /* clr insns on 68000 read before writing. This isn't so on the 68010, but we have no TARGET_68010. */ - && ((TARGET_68020 || TARGET_5200) + && ((TARGET_68020 || TARGET_COLDFIRE) || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))) { if (ADDRESS_REG_P (operands[0])) @@ -921,7 +921,7 @@ } } /* moveq is faster on the 68000. */ - if (DATA_REG_P (operands[0]) && !(TARGET_68020 || TARGET_5200)) + if (DATA_REG_P (operands[0]) && !(TARGET_68020 || TARGET_COLDFIRE)) { return \"moveq %#0,%0\"; } @@ -933,7 +933,7 @@ (define_insn "" [(set (match_operand:SF 0 "nonimmediate_operand" "=r,g") (match_operand:SF 1 "general_operand" "g,r"))] - "TARGET_5200" + "TARGET_COLDFIRE" "* return \"move%.l %1,%0\";") (define_expand "movdf" @@ -947,7 +947,7 @@ (match_operand:DF 1 "general_operand" "*rf,m,0,*rofE<>"))] ; [(set (match_operand:DF 0 "nonimmediate_operand" "=rm,&rf,&rof<>") ; (match_operand:DF 1 "general_operand" "rf,m,rofF<>"))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { if (FP_REG_P (operands[0])) @@ -983,7 +983,7 @@ (define_insn "" [(set (match_operand:DF 0 "nonimmediate_operand" "=r,g") (match_operand:DF 1 "general_operand" "g,r"))] - "TARGET_5200" + "TARGET_COLDFIRE" "* return output_move_double (operands);") ;; ??? The XFmode patterns are schizophrenic about whether constants are @@ -1062,7 +1062,7 @@ (define_insn "" [(set (match_operand:XF 0 "nonimmediate_operand" "=rm,rf,&rof<>") (match_operand:XF 1 "nonimmediate_operand" "rf,m,rof<>"))] - "! TARGET_68881 && ! TARGET_5200" + "! TARGET_68881 && ! TARGET_COLDFIRE" "* { if (FP_REG_P (operands[0])) @@ -1103,7 +1103,7 @@ (define_insn "" [(set (match_operand:XF 0 "nonimmediate_operand" "=r,g") (match_operand:XF 1 "nonimmediate_operand" "g,r"))] - "! TARGET_68881 && TARGET_5200" + "! TARGET_68881 && TARGET_COLDFIRE" "* return output_move_double (operands);") (define_expand "movdi" @@ -1122,7 +1122,7 @@ ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF"))] ; [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,&rf,&ro<>,!&rm,!&f") ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfF"))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { if (FP_REG_P (operands[0])) @@ -1158,7 +1158,7 @@ (define_insn "" [(set (match_operand:DI 0 "nonimmediate_operand" "=r,g") (match_operand:DI 1 "general_operand" "g,r"))] - "TARGET_5200" + "TARGET_COLDFIRE" "* return output_move_double (operands);") ;; Thus goes after the move instructions @@ -1273,7 +1273,7 @@ (define_insn "*zero_extendsidi2_cf" [(set (match_operand:DI 0 "nonimmediate_operand" "=r,m") (zero_extend:DI (match_operand:SI 1 "general_operand" "rm,r")))] - "TARGET_5200" + "TARGET_COLDFIRE" "* { CC_STATUS_INIT; @@ -1297,7 +1297,7 @@ (define_insn "*zero_extendsidi2" [(set (match_operand:DI 0 "nonimmediate_operand" "=rm") (zero_extend:DI (match_operand:SI 1 "general_operand" "rm")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { CC_STATUS_INIT; @@ -1398,9 +1398,9 @@ { if (GET_CODE (operands[1]) == REG && REGNO (operands[0]) == REGNO (operands[1])) - return (!TARGET_5200 ? \"and%.w %#0xFF,%0\" : \"and%.l %#0xFF,%0\"); + return (!TARGET_COLDFIRE ? \"and%.w %#0xFF,%0\" : \"and%.l %#0xFF,%0\"); if (reg_mentioned_p (operands[0], operands[1])) - return (!TARGET_5200 ? \"move%.b %1,%0\;and%.w %#0xFF,%0\" + return (!TARGET_COLDFIRE ? \"move%.b %1,%0\;and%.w %#0xFF,%0\" : \"move%.b %1,%0\;and%.l %#0xFF,%0\"); return \"clr%.w %0\;move%.b %1,%0\"; } @@ -1490,7 +1490,7 @@ { CC_STATUS_INIT; operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); - if (TARGET_68020 || TARGET_5200) + if (TARGET_68020 || TARGET_COLDFIRE) return \"move%.b %1,%2\;extb%.l %2\;smi %0\;extb%.l %0\"; else return \"move%.b %1,%2\;ext%.w %0\;ext%.l %2\;move%.l %2,%0\;smi %0\"; @@ -1505,7 +1505,7 @@ { CC_STATUS_INIT; operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); - if (TARGET_68020 || TARGET_5200) + if (TARGET_68020 || TARGET_COLDFIRE) return \"move%.w %1,%2\;ext%.l %2\;smi %0\;extb%.l %0\"; else return \"move%.w %1,%2\;ext%.l %2\;smi %0\;ext%.w %0\;ext%.l %0\"; @@ -1520,7 +1520,7 @@ { CC_STATUS_INIT; operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); - if (TARGET_68020 || TARGET_5200) + if (TARGET_68020 || TARGET_COLDFIRE) return \"move%.l %1,%2\;smi %0\;extb%.l %0\"; else return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\"; @@ -1552,7 +1552,7 @@ output_asm_insn (\"add%.l %2,%3\", operands); else output_asm_insn (\"move%.l %2,%3\;add%.l %1,%3\", operands); - if (TARGET_68020 || TARGET_5200) + if (TARGET_68020 || TARGET_COLDFIRE) return \"smi %0\;extb%.l %0\"; else return \"smi %0\;ext%.w %0\;ext%.l %0\"; @@ -1579,7 +1579,7 @@ (define_insn "extendqisi2" [(set (match_operand:SI 0 "nonimmediate_operand" "=d") (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0")))] - "TARGET_68020 || TARGET_5200" + "TARGET_68020 || TARGET_COLDFIRE" "extb%.l %0") ;; Conversions between float and double. @@ -1836,7 +1836,7 @@ && GET_CODE (XEXP (operands[1], 0)) == PRE_DEC) output_asm_insn (\"move%.l %4,%3\", operands); output_asm_insn (\"move%.l %1,%0\;smi %2\", operands); - if (TARGET_68020 || TARGET_5200) + if (TARGET_68020 || TARGET_COLDFIRE) output_asm_insn (\"extb%.l %2\", operands); else output_asm_insn (\"ext%.w %2\;ext%.l %2\", operands); @@ -1853,7 +1853,7 @@ (const_int 32)) (match_operand:DI 2 "general_operand" "0,0,0,0"))) (clobber (match_scratch:SI 3 "=&d,X,a,?d"))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { CC_STATUS_INIT; @@ -2031,14 +2031,14 @@ (match_operand:SI 2 "general_src_operand" "dIKLT,rJK,a,mSrIKLT,mSrIKLs")))] - "! TARGET_5200" + "! TARGET_COLDFIRE" "* return output_addsi3 (operands);") (define_insn "*addsi3_5200" [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?a,?a,r") (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0") (match_operand:SI 2 "general_src_operand" "d,rJK,a,mrIKLs")))] - "TARGET_5200" + "TARGET_COLDFIRE" "* return output_addsi3 (operands);") (define_insn "" @@ -2046,14 +2046,14 @@ (plus:SI (match_operand:SI 1 "general_operand" "0") (sign_extend:SI (match_operand:HI 2 "nonimmediate_src_operand" "rmS"))))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "add%.w %2,%0") (define_insn "addhi3" [(set (match_operand:HI 0 "nonimmediate_operand" "=m,r") (plus:HI (match_operand:HI 1 "general_operand" "%0,0") (match_operand:HI 2 "general_src_operand" "dn,rmSn")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { if (GET_CODE (operands[2]) == CONST_INT) @@ -2113,7 +2113,7 @@ [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d")) (plus:HI (match_dup 0) (match_operand:HI 1 "general_src_operand" "dn,rmSn")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { if (GET_CODE (operands[1]) == CONST_INT) @@ -2167,7 +2167,7 @@ [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d")) (plus:HI (match_operand:HI 1 "general_src_operand" "dn,rmSn") (match_dup 0)))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { if (GET_CODE (operands[1]) == CONST_INT) @@ -2221,7 +2221,7 @@ [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d") (plus:QI (match_operand:QI 1 "general_operand" "%0,0") (match_operand:QI 2 "general_src_operand" "dn,dmSn")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { if (GET_CODE (operands[2]) == CONST_INT) @@ -2245,7 +2245,7 @@ [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d")) (plus:QI (match_dup 0) (match_operand:QI 1 "general_src_operand" "dn,dmSn")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { if (GET_CODE (operands[1]) == CONST_INT) @@ -2269,7 +2269,7 @@ [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d")) (plus:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn") (match_dup 0)))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { if (GET_CODE (operands[1]) == CONST_INT) @@ -2377,7 +2377,7 @@ (ashift:DI (sign_extend:DI (match_operand:HI 2 "general_operand" "rm,rm,rm,rm")) (const_int 32)))) (clobber (match_scratch:SI 3 "=&d,X,a,?d"))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { CC_STATUS_INIT; @@ -2501,35 +2501,35 @@ (minus:SI (match_operand:SI 1 "general_operand" "0") (sign_extend:SI (match_operand:HI 2 "nonimmediate_src_operand" "rmS"))))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "sub%.w %2,%0") (define_insn "subhi3" [(set (match_operand:HI 0 "nonimmediate_operand" "=m,r") (minus:HI (match_operand:HI 1 "general_operand" "0,0") (match_operand:HI 2 "general_src_operand" "dn,rmSn")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "sub%.w %2,%0") (define_insn "" [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d")) (minus:HI (match_dup 0) (match_operand:HI 1 "general_src_operand" "dn,rmSn")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "sub%.w %1,%0") (define_insn "subqi3" [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d") (minus:QI (match_operand:QI 1 "general_operand" "0,0") (match_operand:QI 2 "general_src_operand" "dn,dmSn")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "sub%.b %2,%0") (define_insn "" [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d")) (minus:QI (match_dup 0) (match_operand:QI 1 "general_src_operand" "dn,dmSn")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "sub%.b %1,%0") (define_expand "subdf3" @@ -2663,7 +2663,7 @@ [(set (match_operand:SI 0 "nonimmediate_operand" "") (mult:SI (match_operand:SI 1 "general_operand" "") (match_operand:SI 2 "general_operand" "")))] - "TARGET_68020 || TARGET_5200" + "TARGET_68020 || TARGET_COLDFIRE" "") (define_insn "" @@ -2678,7 +2678,7 @@ [(set (match_operand:SI 0 "nonimmediate_operand" "=d") (mult:SI (match_operand:SI 1 "general_operand" "%0") (match_operand:SI 2 "general_operand" "d")))] - "TARGET_5200" + "TARGET_COLDFIRE" "muls%.l %2,%0") (define_insn "umulhisi3" @@ -2724,7 +2724,7 @@ (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1)) (zero_extend:DI (match_dup 2))) (const_int 32))))])] - "TARGET_68020 && !TARGET_68060 && !TARGET_5200" + "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE" "") (define_insn "" @@ -2735,7 +2735,7 @@ (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1)) (zero_extend:DI (match_dup 2))) (const_int 32))))] - "TARGET_68020 && !TARGET_68060 && !TARGET_5200" + "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE" "mulu%.l %2,%3:%0") ; Match immediate case. For 2.4 only match things < 2^31. @@ -2750,7 +2750,7 @@ (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1)) (match_dup 2)) (const_int 32))))] - "TARGET_68020 && !TARGET_68060 && !TARGET_5200 + "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE && (unsigned) INTVAL (operands[2]) <= 0x7fffffff" "mulu%.l %2,%3:%0") @@ -2763,7 +2763,7 @@ (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1)) (sign_extend:DI (match_dup 2))) (const_int 32))))])] - "TARGET_68020 && !TARGET_68060 && !TARGET_5200" + "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE" "") (define_insn "" @@ -2774,7 +2774,7 @@ (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1)) (sign_extend:DI (match_dup 2))) (const_int 32))))] - "TARGET_68020 && !TARGET_68060 && !TARGET_5200" + "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE" "muls%.l %2,%3:%0") (define_insn "" @@ -2785,7 +2785,7 @@ (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1)) (match_dup 2)) (const_int 32))))] - "TARGET_68020 && !TARGET_68060 && !TARGET_5200" + "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE" "muls%.l %2,%3:%0") (define_expand "umulsi3_highpart" @@ -2797,7 +2797,7 @@ (zero_extend:DI (match_operand:SI 2 "general_operand" ""))) (const_int 32)))) (clobber (match_dup 3))])] - "TARGET_68020 && !TARGET_68060 && !TARGET_5200" + "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE" " { operands[3] = gen_reg_rtx (SImode); @@ -2822,7 +2822,7 @@ (zero_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm"))) (const_int 32)))) (clobber (match_operand:SI 1 "register_operand" "=d"))] - "TARGET_68020 && !TARGET_68060 && !TARGET_5200" + "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE" "mulu%.l %3,%0:%1") (define_insn "const_umulsi3_highpart" @@ -2833,7 +2833,7 @@ (match_operand:DI 3 "const_uint32_operand" "n")) (const_int 32)))) (clobber (match_operand:SI 1 "register_operand" "=d"))] - "TARGET_68020 && !TARGET_68060 && !TARGET_5200" + "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE" "mulu%.l %3,%0:%1") (define_expand "smulsi3_highpart" @@ -2845,7 +2845,7 @@ (sign_extend:DI (match_operand:SI 2 "general_operand" ""))) (const_int 32)))) (clobber (match_dup 3))])] - "TARGET_68020 && !TARGET_68060 && !TARGET_5200" + "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE" " { operands[3] = gen_reg_rtx (SImode); @@ -2866,7 +2866,7 @@ (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm"))) (const_int 32)))) (clobber (match_operand:SI 1 "register_operand" "=d"))] - "TARGET_68020 && !TARGET_68060 && !TARGET_5200" + "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE" "muls%.l %3,%0:%1") (define_insn "const_smulsi3_highpart" @@ -2877,7 +2877,7 @@ (match_operand:DI 3 "const_sint32_operand" "n")) (const_int 32)))) (clobber (match_operand:SI 1 "register_operand" "=d"))] - "TARGET_68020 && !TARGET_68060 && !TARGET_5200" + "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE" "muls%.l %3,%0:%1") (define_expand "muldf3" @@ -3089,13 +3089,40 @@ ;; Remainder instructions. -(define_insn "divmodsi4" +(define_expand "divmodsi4" + [(parallel + [(set (match_operand:SI 0 "nonimmediate_operand" "") + (div:SI (match_operand:SI 1 "general_operand" "") + (match_operand:SI 2 "general_src_operand" ""))) + (set (match_operand:SI 3 "nonimmediate_operand" "") + (mod:SI (match_dup 1) (match_dup 2)))])] + "TARGET_68020 || TARGET_CF_HWDIV" + "") + +(define_insn "" + [(set (match_operand:SI 0 "nonimmediate_operand" "=d") + (div:SI (match_operand:SI 1 "general_operand" "0") + (match_operand:SI 2 "general_src_operand" "dU"))) + (set (match_operand:SI 3 "nonimmediate_operand" "=&d") + (mod:SI (match_dup 1) (match_dup 2)))] + "TARGET_CF_HWDIV" + "* +{ + if (find_reg_note (insn, REG_UNUSED, operands[3])) + return \"divs%.l %2,%0\"; + else if (find_reg_note (insn, REG_UNUSED, operands[0])) + return \"rems%.l %2,%3:%0\"; + else + return \"rems%.l %2,%3:%0\;divs%.l %2,%0\"; +}") + +(define_insn "" [(set (match_operand:SI 0 "nonimmediate_operand" "=d") (div:SI (match_operand:SI 1 "general_operand" "0") (match_operand:SI 2 "general_src_operand" "dmSTK"))) (set (match_operand:SI 3 "nonimmediate_operand" "=d") (mod:SI (match_dup 1) (match_dup 2)))] - "TARGET_68020 && !TARGET_5200" + "TARGET_68020" "* { if (find_reg_note (insn, REG_UNUSED, operands[3])) @@ -3104,13 +3131,40 @@ return \"divsl%.l %2,%3:%0\"; }") -(define_insn "udivmodsi4" +(define_expand "udivmodsi4" + [(parallel + [(set (match_operand:SI 0 "nonimmediate_operand" "=d") + (udiv:SI (match_operand:SI 1 "general_operand" "0") + (match_operand:SI 2 "general_src_operand" "dmSTK"))) + (set (match_operand:SI 3 "nonimmediate_operand" "=d") + (umod:SI (match_dup 1) (match_dup 2)))])] + "TARGET_68020 || TARGET_CF_HWDIV" + "") + +(define_insn "" + [(set (match_operand:SI 0 "nonimmediate_operand" "=d") + (udiv:SI (match_operand:SI 1 "general_operand" "0") + (match_operand:SI 2 "general_src_operand" "dU"))) + (set (match_operand:SI 3 "nonimmediate_operand" "=&d") + (umod:SI (match_dup 1) (match_dup 2)))] + "TARGET_CF_HWDIV" + "* +{ + if (find_reg_note (insn, REG_UNUSED, operands[3])) + return \"divu%.l %2,%0\"; + else if (find_reg_note (insn, REG_UNUSED, operands[0])) + return \"remu%.l %2,%3:%0\"; + else + return \"remu%.l %2,%3:%0\;divu%.l %2,%0\"; +}") + +(define_insn "" [(set (match_operand:SI 0 "nonimmediate_operand" "=d") (udiv:SI (match_operand:SI 1 "general_operand" "0") (match_operand:SI 2 "general_src_operand" "dmSTK"))) (set (match_operand:SI 3 "nonimmediate_operand" "=d") (umod:SI (match_dup 1) (match_dup 2)))] - "TARGET_68020 && !TARGET_5200" + "TARGET_68020 && !TARGET_COLDFIRE" "* { if (find_reg_note (insn, REG_UNUSED, operands[3])) @@ -3125,7 +3179,7 @@ (match_operand:HI 2 "general_src_operand" "dmSKT"))) (set (match_operand:HI 3 "nonimmediate_operand" "=d") (mod:HI (match_dup 1) (match_dup 2)))] - "!TARGET_5200" + "!TARGET_COLDFIRE || TARGET_CF_HWDIV" "* { #ifdef MOTOROLA @@ -3148,7 +3202,7 @@ (match_operand:HI 2 "general_src_operand" "dmSKT"))) (set (match_operand:HI 3 "nonimmediate_operand" "=d") (umod:HI (match_dup 1) (match_dup 2)))] - "!TARGET_5200" + "!TARGET_COLDFIRE || TARGET_CF_HWDIV" "* { #ifdef MOTOROLA @@ -3172,7 +3226,7 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "=o,d") (and:DI (match_operand:DI 1 "general_operand" "%0,0") (match_operand:DI 2 "general_operand" "dn,don")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { CC_STATUS_INIT; @@ -3249,7 +3303,7 @@ [(set (match_operand:SI 0 "not_sp_operand" "=m,d") (and:SI (match_operand:SI 1 "general_operand" "%0,0") (match_operand:SI 2 "general_src_operand" "dKT,dmSM")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { return output_andsi3 (operands); @@ -3259,49 +3313,49 @@ [(set (match_operand:SI 0 "not_sp_operand" "=m,d") (and:SI (match_operand:SI 1 "general_operand" "%0,0") (match_operand:SI 2 "general_src_operand" "d,dmsK")))] - "TARGET_5200" + "TARGET_COLDFIRE" "and%.l %2,%0") (define_insn "andhi3" [(set (match_operand:HI 0 "nonimmediate_operand" "=m,d") (and:HI (match_operand:HI 1 "general_operand" "%0,0") (match_operand:HI 2 "general_src_operand" "dn,dmSn")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "and%.w %2,%0") (define_insn "" [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d")) (and:HI (match_dup 0) (match_operand:HI 1 "general_src_operand" "dn,dmSn")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "and%.w %1,%0") (define_insn "" [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d")) (and:HI (match_operand:HI 1 "general_src_operand" "dn,dmSn") (match_dup 0)))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "and%.w %1,%0") (define_insn "andqi3" [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d") (and:QI (match_operand:QI 1 "general_operand" "%0,0") (match_operand:QI 2 "general_src_operand" "dn,dmSn")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "and%.b %2,%0") (define_insn "" [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d")) (and:QI (match_dup 0) (match_operand:QI 1 "general_src_operand" "dn,dmSn")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "and%.b %1,%0") (define_insn "" [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d")) (and:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn") (match_dup 0)))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "and%.b %1,%0") ;; inclusive-or instructions @@ -3310,7 +3364,7 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "=o,d") (ior:DI (zero_extend:DI (match_operand 1 "general_operand" "dn,dmn")) (match_operand:DI 2 "general_operand" "0,0")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { int byte_mode; @@ -3337,7 +3391,7 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "=o,d") (ior:DI (match_operand:DI 1 "general_operand" "%0,0") (match_operand:DI 2 "general_operand" "dn,don")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { CC_STATUS_INIT; @@ -3414,7 +3468,7 @@ [(set (match_operand:SI 0 "nonimmediate_operand" "=m,d") (ior:SI (match_operand:SI 1 "general_operand" "%0,0") (match_operand:SI 2 "general_src_operand" "dKT,dmSMT")))] - "! TARGET_5200" + "! TARGET_COLDFIRE" "* { return output_iorsi3 (operands); @@ -3424,49 +3478,49 @@ [(set (match_operand:SI 0 "nonimmediate_operand" "=m,d") (ior:SI (match_operand:SI 1 "general_operand" "%0,0") (match_operand:SI 2 "general_src_operand" "d,dmsK")))] - "TARGET_5200" + "TARGET_COLDFIRE" "or%.l %2,%0") (define_insn "iorhi3" [(set (match_operand:HI 0 "nonimmediate_operand" "=m,d") (ior:HI (match_operand:HI 1 "general_operand" "%0,0") (match_operand:HI 2 "general_src_operand" "dn,dmSn")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "or%.w %2,%0") (define_insn "" [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d")) (ior:HI (match_dup 0) (match_operand:HI 1 "general_src_operand" "dn,dmSn")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "or%.w %1,%0") (define_insn "" [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d")) (ior:HI (match_operand:HI 1 "general_src_operand" "dn,dmSn") (match_dup 0)))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "or%.w %1,%0") (define_insn "iorqi3" [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d") (ior:QI (match_operand:QI 1 "general_operand" "%0,0") (match_operand:QI 2 "general_src_operand" "dn,dmSn")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "or%.b %2,%0") (define_insn "" [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d")) (ior:QI (match_dup 0) (match_operand:QI 1 "general_src_operand" "dn,dmSn")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "or%.b %1,%0") (define_insn "" [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d")) (ior:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn") (match_dup 0)))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "or%.b %1,%0") ;; On all 68k models, this makes faster code in a special case. @@ -3493,7 +3547,7 @@ [(set (match_operand:SI 0 "nonimmediate_operand" "=o,d") (ior:SI (zero_extend:SI (match_operand 1 "general_operand" "dn,dmn")) (match_operand:SI 2 "general_operand" "0,0")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { int byte_mode; @@ -3516,7 +3570,7 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "=od") (xor:DI (match_operand:DI 1 "general_operand" "%0") (match_operand:DI 2 "general_operand" "dn")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { CC_STATUS_INIT; @@ -3597,7 +3651,7 @@ (xor:SI (match_operand:SI 1 "general_operand" "%0,0") (match_operand:SI 2 "general_operand" "di,dKT")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { return output_xorsi3 (operands); @@ -3607,49 +3661,49 @@ [(set (match_operand:SI 0 "nonimmediate_operand" "=dm,d") (xor:SI (match_operand:SI 1 "general_operand" "%0,0") (match_operand:SI 2 "general_operand" "d,Ks")))] - "TARGET_5200" + "TARGET_COLDFIRE" "eor%.l %2,%0") (define_insn "xorhi3" [(set (match_operand:HI 0 "nonimmediate_operand" "=dm") (xor:HI (match_operand:HI 1 "general_operand" "%0") (match_operand:HI 2 "general_operand" "dn")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "eor%.w %2,%0") (define_insn "" [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm")) (xor:HI (match_dup 0) (match_operand:HI 1 "general_operand" "dn")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "eor%.w %1,%0") (define_insn "" [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm")) (xor:HI (match_operand:HI 1 "general_operand" "dn") (match_dup 0)))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "eor%.w %1,%0") (define_insn "xorqi3" [(set (match_operand:QI 0 "nonimmediate_operand" "=dm") (xor:QI (match_operand:QI 1 "general_operand" "%0") (match_operand:QI 2 "general_operand" "dn")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "eor%.b %2,%0") (define_insn "" [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm")) (xor:QI (match_dup 0) (match_operand:QI 1 "general_operand" "dn")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "eor%.b %1,%0") (define_insn "" [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm")) (xor:QI (match_operand:QI 1 "general_operand" "dn") (match_dup 0)))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "eor%.b %1,%0") ;; negation instructions @@ -3660,7 +3714,7 @@ "" " { - if (TARGET_5200) + if (TARGET_COLDFIRE) emit_insn (gen_negdi2_5200 (operands[0], operands[1])); else emit_insn (gen_negdi2_internal (operands[0], operands[1])); @@ -3670,7 +3724,7 @@ (define_insn "negdi2_internal" [(set (match_operand:DI 0 "nonimmediate_operand" "=<,do,!*a") (neg:DI (match_operand:DI 1 "general_operand" "0,0,0")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { if (which_alternative == 0) @@ -3688,7 +3742,7 @@ (define_insn "negdi2_5200" [(set (match_operand:DI 0 "nonimmediate_operand" "=d") (neg:DI (match_operand:DI 1 "general_operand" "0")))] - "TARGET_5200" + "TARGET_COLDFIRE" "* { operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); @@ -3701,7 +3755,7 @@ "" " { - if (TARGET_5200) + if (TARGET_COLDFIRE) emit_insn (gen_negsi2_5200 (operands[0], operands[1])); else emit_insn (gen_negsi2_internal (operands[0], operands[1])); @@ -3711,37 +3765,37 @@ (define_insn "negsi2_internal" [(set (match_operand:SI 0 "nonimmediate_operand" "=dm") (neg:SI (match_operand:SI 1 "general_operand" "0")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "neg%.l %0") (define_insn "negsi2_5200" [(set (match_operand:SI 0 "nonimmediate_operand" "=d") (neg:SI (match_operand:SI 1 "general_operand" "0")))] - "TARGET_5200" + "TARGET_COLDFIRE" "neg%.l %0") (define_insn "neghi2" [(set (match_operand:HI 0 "nonimmediate_operand" "=dm") (neg:HI (match_operand:HI 1 "general_operand" "0")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "neg%.w %0") (define_insn "" [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm")) (neg:HI (match_dup 0)))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "neg%.w %0") (define_insn "negqi2" [(set (match_operand:QI 0 "nonimmediate_operand" "=dm") (neg:QI (match_operand:QI 1 "general_operand" "0")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "neg%.b %0") (define_insn "" [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm")) (neg:QI (match_dup 0)))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "neg%.b %0") ;; If using software floating point, just flip the sign bit. @@ -3957,7 +4011,7 @@ (define_insn "one_cmpldi2" [(set (match_operand:DI 0 "nonimmediate_operand" "=dm") (not:DI (match_operand:DI 1 "general_operand" "0")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { CC_STATUS_INIT; @@ -3977,7 +4031,7 @@ "" " { - if (TARGET_5200) + if (TARGET_COLDFIRE) emit_insn (gen_one_cmplsi2_5200 (operands[0], operands[1])); else emit_insn (gen_one_cmplsi2_internal (operands[0], operands[1])); @@ -3987,37 +4041,37 @@ (define_insn "one_cmplsi2_internal" [(set (match_operand:SI 0 "nonimmediate_operand" "=dm") (not:SI (match_operand:SI 1 "general_operand" "0")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "not%.l %0") (define_insn "one_cmplsi2_5200" [(set (match_operand:SI 0 "nonimmediate_operand" "=d") (not:SI (match_operand:SI 1 "general_operand" "0")))] - "TARGET_5200" + "TARGET_COLDFIRE" "not%.l %0") (define_insn "one_cmplhi2" [(set (match_operand:HI 0 "nonimmediate_operand" "=dm") (not:HI (match_operand:HI 1 "general_operand" "0")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "not%.w %0") (define_insn "" [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm")) (not:HI (match_dup 0)))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "not%.w %0") (define_insn "one_cmplqi2" [(set (match_operand:QI 0 "nonimmediate_operand" "=dm") (not:QI (match_operand:QI 1 "general_operand" "0")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "not%.b %0") (define_insn "" [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm")) (not:QI (match_dup 0)))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "not%.b %0") ;; arithmetic shift instructions @@ -4101,7 +4155,7 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "=d") (ashift:DI (match_operand:DI 1 "general_operand" "0") (match_operand 2 "const_int_operand" "n")))] - "(!TARGET_5200 + "(!TARGET_COLDFIRE && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3) || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))" @@ -4133,7 +4187,7 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "") (ashift:DI (match_operand:DI 1 "general_operand" "") (match_operand 2 "const_int_operand" "")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" " { /* ??? This is a named pattern like this is not allowed to FAIL based @@ -4167,7 +4221,7 @@ [(set (match_operand:SI 0 "register_operand" "=d") (ashift:SI (match_operand:SI 1 "register_operand" "0") (match_operand:SI 2 "const_int_operand" "n")))] - "(! TARGET_68020 && !TARGET_5200 + "(! TARGET_68020 && !TARGET_COLDFIRE && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)" "* { @@ -4196,28 +4250,28 @@ [(set (match_operand:HI 0 "register_operand" "=d") (ashift:HI (match_operand:HI 1 "register_operand" "0") (match_operand:HI 2 "general_operand" "dI")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "lsl%.w %2,%0") (define_insn "" [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d")) (ashift:HI (match_dup 0) (match_operand:HI 1 "general_operand" "dI")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "lsl%.w %1,%0") (define_insn "ashlqi3" [(set (match_operand:QI 0 "register_operand" "=d") (ashift:QI (match_operand:QI 1 "register_operand" "0") (match_operand:QI 2 "general_operand" "dI")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "lsl%.b %2,%0") (define_insn "" [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d")) (ashift:QI (match_dup 0) (match_operand:QI 1 "general_operand" "dI")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "lsl%.b %1,%0") ;; On most 68k models, this makes faster code in a special case. @@ -4235,7 +4289,7 @@ [(set (match_operand:SI 0 "register_operand" "=d") (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") (match_operand:SI 2 "const_int_operand" "n")))] - "(! TARGET_68020 && !TARGET_5200 + "(! TARGET_68020 && !TARGET_COLDFIRE && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)" "* { @@ -4304,7 +4358,7 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "=d") (ashiftrt:DI (match_operand:DI 1 "general_operand" "0") (match_operand 2 "const_int_operand" "n")))] - "(!TARGET_5200 + "(!TARGET_COLDFIRE && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3) || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16 || INTVAL (operands[2]) == 31 @@ -4344,7 +4398,7 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "") (ashiftrt:DI (match_operand:DI 1 "general_operand" "") (match_operand 2 "const_int_operand" "")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" " { /* ??? This is a named pattern like this is not allowed to FAIL based @@ -4379,28 +4433,28 @@ [(set (match_operand:HI 0 "register_operand" "=d") (ashiftrt:HI (match_operand:HI 1 "register_operand" "0") (match_operand:HI 2 "general_operand" "dI")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "asr%.w %2,%0") (define_insn "" [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d")) (ashiftrt:HI (match_dup 0) (match_operand:HI 1 "general_operand" "dI")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "asr%.w %1,%0") (define_insn "ashrqi3" [(set (match_operand:QI 0 "register_operand" "=d") (ashiftrt:QI (match_operand:QI 1 "register_operand" "0") (match_operand:QI 2 "general_operand" "dI")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "asr%.b %2,%0") (define_insn "" [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d")) (ashiftrt:QI (match_dup 0) (match_operand:QI 1 "general_operand" "dI")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "asr%.b %1,%0") ;; logical shift instructions @@ -4477,7 +4531,7 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "=d") (lshiftrt:DI (match_operand:DI 1 "general_operand" "0") (match_operand 2 "const_int_operand" "n")))] - "(!TARGET_5200 + "(!TARGET_COLDFIRE && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3) || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))" @@ -4512,7 +4566,7 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "") (lshiftrt:DI (match_operand:DI 1 "general_operand" "") (match_operand 2 "const_int_operand" "")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" " { /* ??? This is a named pattern like this is not allowed to FAIL based @@ -4555,7 +4609,7 @@ [(set (match_operand:SI 0 "register_operand" "=d") (lshiftrt:SI (match_operand:SI 1 "register_operand" "0") (match_operand:SI 2 "const_int_operand" "n")))] - "(! TARGET_68020 && !TARGET_5200 + "(! TARGET_68020 && !TARGET_COLDFIRE && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)" "* { @@ -4575,28 +4629,28 @@ [(set (match_operand:HI 0 "register_operand" "=d") (lshiftrt:HI (match_operand:HI 1 "register_operand" "0") (match_operand:HI 2 "general_operand" "dI")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "lsr%.w %2,%0") (define_insn "" [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d")) (lshiftrt:HI (match_dup 0) (match_operand:HI 1 "general_operand" "dI")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "lsr%.w %1,%0") (define_insn "lshrqi3" [(set (match_operand:QI 0 "register_operand" "=d") (lshiftrt:QI (match_operand:QI 1 "register_operand" "0") (match_operand:QI 2 "general_operand" "dI")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "lsr%.b %2,%0") (define_insn "" [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d")) (lshiftrt:QI (match_dup 0) (match_operand:QI 1 "general_operand" "dI")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "lsr%.b %1,%0") ;; rotate instructions @@ -4605,7 +4659,7 @@ [(set (match_operand:SI 0 "register_operand" "=d") (rotate:SI (match_operand:SI 1 "register_operand" "0") (match_operand:SI 2 "general_operand" "dINO")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16) @@ -4623,7 +4677,7 @@ [(set (match_operand:HI 0 "register_operand" "=d") (rotate:HI (match_operand:HI 1 "register_operand" "0") (match_operand:HI 2 "general_operand" "dIP")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8) @@ -4639,7 +4693,7 @@ [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d")) (rotate:HI (match_dup 0) (match_operand:HI 1 "general_operand" "dIP")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8) @@ -4655,7 +4709,7 @@ [(set (match_operand:QI 0 "register_operand" "=d") (rotate:QI (match_operand:QI 1 "register_operand" "0") (match_operand:QI 2 "general_operand" "dI")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4) @@ -4671,7 +4725,7 @@ [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d")) (rotate:QI (match_dup 0) (match_operand:QI 1 "general_operand" "dI")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4) @@ -4687,35 +4741,35 @@ [(set (match_operand:SI 0 "register_operand" "=d") (rotatert:SI (match_operand:SI 1 "register_operand" "0") (match_operand:SI 2 "general_operand" "dI")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "ror%.l %2,%0") (define_insn "rotrhi3" [(set (match_operand:HI 0 "register_operand" "=d") (rotatert:HI (match_operand:HI 1 "register_operand" "0") (match_operand:HI 2 "general_operand" "dI")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "ror%.w %2,%0") (define_insn "" [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d")) (rotatert:HI (match_dup 0) (match_operand:HI 1 "general_operand" "dI")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "ror%.w %1,%0") (define_insn "rotrqi3" [(set (match_operand:QI 0 "register_operand" "=d") (rotatert:QI (match_operand:QI 1 "register_operand" "0") (match_operand:QI 2 "general_operand" "dI")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "ror%.b %2,%0") (define_insn "" [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d")) (rotatert:QI (match_dup 0) (match_operand:QI 1 "general_operand" "dI")))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "ror%.b %1,%0") @@ -5179,7 +5233,7 @@ [(set (match_operand:QI 0 "nonimmediate_operand" "=dm") (match_operator 1 "valid_dbcc_comparison_p" [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))] - "! TARGET_5200" + "! TARGET_COLDFIRE" "* { return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]); @@ -5189,7 +5243,7 @@ [(set (match_operand:QI 0 "nonimmediate_operand" "=d") (match_operator 1 "valid_dbcc_comparison_p" [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))] - "TARGET_5200" + "TARGET_COLDFIRE" "* { return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]); @@ -5200,7 +5254,7 @@ (match_operator 1 "valid_dbcc_comparison_p" [(match_operand:DI 2 "general_operand" "ro,r") (match_operand:DI 3 "general_operand" "r,ro")]))] - "! TARGET_5200" + "! TARGET_COLDFIRE" "* { return output_scc_di (operands[1], operands[2], operands[3], operands[0]); @@ -5211,7 +5265,7 @@ (match_operator 1 "valid_dbcc_comparison_p" [(match_operand:DI 2 "general_operand" "ro,r") (match_operand:DI 3 "general_operand" "r,ro")]))] - "TARGET_5200" + "TARGET_COLDFIRE" "* { return output_scc_di (operands[1], operands[2], operands[3], operands[0]); @@ -5658,7 +5712,7 @@ #endif } operands[4] = gen_label_rtx(); - if (TARGET_68020 || TARGET_5200) + if (TARGET_68020 || TARGET_COLDFIRE) { #ifdef MOTOROLA output_asm_insn (\"tst%.l %0\;jbne %l4\;tst%.l %3\;jbeq %l1\", operands); @@ -5737,7 +5791,7 @@ return \"move%.l %0,%2\;or%.l %3,%2\;jne %l1\"; #endif } - if (TARGET_68020 || TARGET_5200) + if (TARGET_68020 || TARGET_COLDFIRE) { #ifdef MOTOROLA return \"tst%.l %0\;jbne %l1\;tst%.l %3\;jbne %l1\"; @@ -5792,7 +5846,7 @@ } } CC_STATUS_INIT; - if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0])) + if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (operands[0])) output_asm_insn(\"tst%.l %0\", operands); else { @@ -5844,7 +5898,7 @@ } } CC_STATUS_INIT; - if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0])) + if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (operands[0])) output_asm_insn(\"tst%.l %0\", operands); else { @@ -6463,7 +6517,7 @@ #else #ifdef SGS #ifdef ASM_OUTPUT_CASE_LABEL - if (TARGET_5200) + if (TARGET_COLDFIRE) { if (ADDRESS_REG_P (operands[0])) return \"jmp 6(%%pc,%0.l)\"; @@ -6473,7 +6527,7 @@ else return \"jmp 6(%%pc,%0.w)\"; #else - if (TARGET_5200) + if (TARGET_COLDFIRE) { if (ADDRESS_REG_P (operands[0])) return \"jmp 2(%%pc,%0.l)\"; @@ -6484,7 +6538,7 @@ return \"jmp 2(%%pc,%0.w)\"; #endif #else /* not SGS */ - if (TARGET_5200) + if (TARGET_COLDFIRE) { if (ADDRESS_REG_P (operands[0])) { @@ -6526,7 +6580,7 @@ (set (match_dup 0) (plus:HI (match_dup 0) (const_int -1)))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { CC_STATUS_INIT; @@ -6561,7 +6615,7 @@ (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))] - "!TARGET_5200" + "!TARGET_COLDFIRE" "* { CC_STATUS_INIT; @@ -6597,7 +6651,7 @@ (set (match_dup 0) (plus:HI (match_dup 0) (const_int -1)))] - "!TARGET_5200 && find_reg_note (insn, REG_NONNEG, 0)" + "!TARGET_COLDFIRE && find_reg_note (insn, REG_NONNEG, 0)" "* { CC_STATUS_INIT; @@ -6645,7 +6699,7 @@ (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))] - "!TARGET_5200 && find_reg_note (insn, REG_NONNEG, 0)" + "!TARGET_COLDFIRE && find_reg_note (insn, REG_NONNEG, 0)" "* { CC_STATUS_INIT; @@ -6973,7 +7027,7 @@ xoperands[1] = GEN_INT (INTVAL (operands[0]) - 4); if (INTVAL (xoperands[1]) <= 8) { - if (!TARGET_5200) + if (!TARGET_COLDFIRE) output_asm_insn (\"addq%.w %1,%0\", xoperands); else output_asm_insn (\"addq%.l %1,%0\", xoperands); @@ -7020,7 +7074,7 @@ xoperands[1] = GEN_INT (INTVAL (operands[0]) - 4); if (INTVAL (xoperands[1]) <= 8) { - if (!TARGET_5200) + if (!TARGET_COLDFIRE) output_asm_insn (\"addq%.w %1,%0\", xoperands); else output_asm_insn (\"addq%.l %1,%0\", xoperands); @@ -7069,7 +7123,7 @@ xoperands[2] = gen_rtx_MEM (QImode, plus_constant (stack_pointer_rtx, 3)); xoperands[3] = stack_pointer_rtx; - if (!TARGET_5200) + if (!TARGET_COLDFIRE) output_asm_insn (\"subq%.w %#4,%3\;move%.b %1,%2\", xoperands); else output_asm_insn (\"subq%.l %#4,%3\;move%.b %1,%2\", xoperands); @@ -7091,7 +7145,7 @@ || GET_CODE (operands[0]) == MEM) /* clr insns on 68000 read before writing. This isn't so on the 68010, but we have no TARGET_68010. */ - && ((TARGET_68020 || TARGET_5200) + && ((TARGET_68020 || TARGET_COLDFIRE) || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))) return \"clr%.w %0\"; @@ -7131,7 +7185,7 @@ (set (match_dup 0) (plus:HI (match_dup 0) (const_int -1)))])] - "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()" + "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()" "* { CC_STATUS_INIT; @@ -7154,7 +7208,7 @@ (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))])] - "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()" + "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()" "* { CC_STATUS_INIT; @@ -7178,7 +7232,7 @@ (set (match_dup 0) (plus:HI (match_dup 0) (const_int -1)))])] - "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()" + "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()" "* { CC_STATUS_INIT; @@ -7202,7 +7256,7 @@ (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))])] - "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()" + "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()" "* { CC_STATUS_INIT; diff --git a/gcc/config/m68k/m68kelf.h b/gcc/config/m68k/m68kelf.h index f481871c48d..bb9edccf3ca 100644 --- a/gcc/config/m68k/m68kelf.h +++ b/gcc/config/m68k/m68kelf.h @@ -75,7 +75,7 @@ Boston, MA 02111-1307, USA. */ #define ASM_RETURN_CASE_JUMP \ do { \ - if (TARGET_5200) \ + if (TARGET_COLDFIRE) \ { \ if (ADDRESS_REG_P (operands[0])) \ return "jmp %%pc@(2,%0:l)"; \ diff --git a/gcc/config/m68k/netbsd-elf.h b/gcc/config/m68k/netbsd-elf.h index 14fcf1a962a..cae6cb1d8c9 100644 --- a/gcc/config/m68k/netbsd-elf.h +++ b/gcc/config/m68k/netbsd-elf.h @@ -204,7 +204,7 @@ while (0) #undef ASM_OUTPUT_CASE_LABEL #define ASM_RETURN_CASE_JUMP \ do { \ - if (TARGET_5200) \ + if (TARGET_COLDFIRE) \ { \ if (ADDRESS_REG_P (operands[0])) \ return "jmp %%pc@(2,%0:l)"; \ diff --git a/gcc/config/m68k/t-m68kelf b/gcc/config/m68k/t-m68kelf index 6f7e3a0edc9..686e2d49054 100644 --- a/gcc/config/m68k/t-m68kelf +++ b/gcc/config/m68k/t-m68kelf @@ -12,11 +12,14 @@ xfgnulib.c: $(srcdir)/config/m68k/fpgnulib.c echo '#define EXTFLOAT' > xfgnulib.c cat $(srcdir)/config/m68k/fpgnulib.c >> xfgnulib.c -MULTILIB_OPTIONS = m68000/m68020/m5200/mcpu32/m68040/m68060 m68881/msoft-float +MULTILIB_OPTIONS = m68000/m68020/m5200/m5206e/m528x/m5307/m5407/mcpu32/m68040/m68060 m68881/msoft-float MULTILIB_DIRNAMES = -MULTILIB_MATCHES = m68000=mc68000 m68000=m68302 mcpu32=m68332 m68020=mc68020 -MULTILIB_EXCEPTIONS = m68000/msoft-float m5200/m68881 m5200/msoft-float mcpu32/m68881 mcpu32/msoft-float m68040/m68881 m68040/msoft-float m68060/m68881 m68060/msoft-float - +MULTILIB_MATCHES = m68000=mc68000 m68000=m68302 mcpu32=m68332 m68020=mc68020 m5206e=m5272 +MULTILIB_EXCEPTIONS = m68000/msoft-float m5200/m68881 m5200/msoft-float \ + m5206e/m68881 m5206e/msoft-float m528x/m68881 m528x/msoft-float \ + m5307/m68881 m5307/msoft-float m5407/m68881 m5407/msoft-float \ + mcpu32/m68881 mcpu32/msoft-float m68040/m68881 m68040/msoft-float \ + m68060/m68881 m68060/msoft-float LIBGCC = stmp-multilib INSTALL_LIBGCC = install-multilib -- 2.11.0