From 841985a7d348d2be9fbed8656ebe09b3b434ac93 Mon Sep 17 00:00:00 2001 From: uros Date: Fri, 21 Nov 2008 08:54:18 +0000 Subject: [PATCH] * config/i386/mmx.md (mmx_nand3): Rename to mmx_andnot3. * config/i386/sse.md (avx_nand3): Rename to avx_andnot3. (_nand3): Rename to _andnot3. (sse2_nand3): Rename to sse2_andnot3. (*sse_nand3): Rename to *sse_andnot3. (*avx_nand3): Rename to *avx_andnot3. (*nand3): Rename to *andnot3. (*nandtf3): rename to *andnottf3. * config/i386/i386.c (bdesc_args) [IX86_BUILTIN_PANDN]: Use CODE_FOR_mmx_andnotv2si3. [IX86_BUILTIN_ANDNPS]: Use CODE_FOR_sse_andnotv4sf3. [IX86_BUILTIN_ANDNPD]: Use CODE_FOR_sse2_andnotv2df3. [IX86_BUILTIN_PANDN128]: Use CODE_FOR_sse2_andnotv2di3. [IX86_BUILTIN_ANDNPS256]: Use CODE_FOR_avx_andnotv8sf3. [IX86_BUILTIN_ANDNPD256]: Use CODE_FOR_avx_andnotv4df3. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@142083 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 18 ++++++++++++++++++ gcc/config/i386/i386.c | 12 ++++++------ gcc/config/i386/mmx.md | 2 +- gcc/config/i386/sse.md | 18 +++++++++--------- 4 files changed, 34 insertions(+), 16 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d10c08a045a..43028ef0a96 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,23 @@ 2008-11-21 Uros Bizjak + * config/i386/mmx.md (mmx_nand3): Rename to mmx_andnot3. + * config/i386/sse.md (avx_nand3): Rename to avx_andnot3. + (_nand3): Rename to _andnot3. + (sse2_nand3): Rename to sse2_andnot3. + (*sse_nand3): Rename to *sse_andnot3. + (*avx_nand3): Rename to *avx_andnot3. + (*nand3): Rename to *andnot3. + (*nandtf3): rename to *andnottf3. + * config/i386/i386.c (bdesc_args) [IX86_BUILTIN_PANDN]: + Use CODE_FOR_mmx_andnotv2si3. + [IX86_BUILTIN_ANDNPS]: Use CODE_FOR_sse_andnotv4sf3. + [IX86_BUILTIN_ANDNPD]: Use CODE_FOR_sse2_andnotv2df3. + [IX86_BUILTIN_PANDN128]: Use CODE_FOR_sse2_andnotv2di3. + [IX86_BUILTIN_ANDNPS256]: Use CODE_FOR_avx_andnotv8sf3. + [IX86_BUILTIN_ANDNPD256]: Use CODE_FOR_avx_andnotv4df3. + +2008-11-21 Uros Bizjak + PR middle-end/37908 * config/ia64/ia64.c (ia64_expand_atomic_ope): Properly handle NAND case by calculating ~(new_reg & val) instead of (~new_reg & val). diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index fca4d859302..e6f00d7c8e7 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -20319,7 +20319,7 @@ static const struct builtin_description bdesc_args[] = { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI }, { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI }, - { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_nandv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI }, + { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI }, { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI }, { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI }, @@ -20446,7 +20446,7 @@ static const struct builtin_description bdesc_args[] = { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF }, { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF }, - { OPTION_MASK_ISA_SSE, CODE_FOR_sse_nandv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF }, + { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF }, { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF }, { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF }, @@ -20543,7 +20543,7 @@ static const struct builtin_description bdesc_args[] = { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF }, { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF }, - { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_nandv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF }, + { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF }, { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF }, { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF }, @@ -20575,7 +20575,7 @@ static const struct builtin_description bdesc_args[] = { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI }, { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI }, - { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_nandv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI }, + { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI }, { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI }, { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI }, @@ -20785,8 +20785,8 @@ static const struct builtin_description bdesc_args[] = { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF }, { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF }, { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF }, - { OPTION_MASK_ISA_AVX, CODE_FOR_avx_nandv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF }, - { OPTION_MASK_ISA_AVX, CODE_FOR_avx_nandv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF }, + { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF }, + { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF }, { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF }, { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF }, { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF }, diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 16aaf2c0793..870fc8855e7 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -1027,7 +1027,7 @@ ;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -(define_insn "mmx_nand3" +(define_insn "mmx_andnot3" [(set (match_operand:MMXMODEI 0 "register_operand" "=y") (and:MMXMODEI (not:MMXMODEI (match_operand:MMXMODEI 1 "register_operand" "0")) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index e35d8573869..48c9f6d0c1d 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -1482,7 +1482,7 @@ ;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -(define_insn "avx_nand3" +(define_insn "avx_andnot3" [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x") (and:AVXMODEF2P (not:AVXMODEF2P @@ -1494,7 +1494,7 @@ (set_attr "prefix" "vex") (set_attr "mode" "")]) -(define_insn "_nand3" +(define_insn "_andnot3" [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x") (and:SSEMODEF2P (not:SSEMODEF2P @@ -1549,7 +1549,7 @@ ;; allocation lossage. These patterns do not allow memory operands ;; because the native instructions read the full 128-bits. -(define_insn "*avx_nand3" +(define_insn "*avx_andnot3" [(set (match_operand:MODEF 0 "register_operand" "=x") (and:MODEF (not:MODEF @@ -1561,7 +1561,7 @@ (set_attr "prefix" "vex") (set_attr "mode" "")]) -(define_insn "*nand3" +(define_insn "*andnot3" [(set (match_operand:MODEF 0 "register_operand" "=x") (and:MODEF (not:MODEF @@ -5866,7 +5866,7 @@ operands[2] = force_reg (mode, gen_rtx_CONST_VECTOR (mode, v)); }) -(define_insn "*avx_nand3" +(define_insn "*avx_andnot3" [(set (match_operand:AVX256MODEI 0 "register_operand" "=x") (and:AVX256MODEI (not:AVX256MODEI (match_operand:AVX256MODEI 1 "register_operand" "x")) @@ -5877,7 +5877,7 @@ (set_attr "prefix" "vex") (set_attr "mode" "")]) -(define_insn "*sse_nand3" +(define_insn "*sse_andnot3" [(set (match_operand:SSEMODEI 0 "register_operand" "=x") (and:SSEMODEI (not:SSEMODEI (match_operand:SSEMODEI 1 "register_operand" "0")) @@ -5887,7 +5887,7 @@ [(set_attr "type" "sselog") (set_attr "mode" "V4SF")]) -(define_insn "*avx_nand3" +(define_insn "*avx_andnot3" [(set (match_operand:SSEMODEI 0 "register_operand" "=x") (and:SSEMODEI (not:SSEMODEI (match_operand:SSEMODEI 1 "register_operand" "x")) @@ -5898,7 +5898,7 @@ (set_attr "prefix" "vex") (set_attr "mode" "TI")]) -(define_insn "sse2_nand3" +(define_insn "sse2_andnot3" [(set (match_operand:SSEMODEI 0 "register_operand" "=x") (and:SSEMODEI (not:SSEMODEI (match_operand:SSEMODEI 1 "register_operand" "0")) @@ -5909,7 +5909,7 @@ (set_attr "prefix_data16" "1") (set_attr "mode" "TI")]) -(define_insn "*nandtf3" +(define_insn "*andnottf3" [(set (match_operand:TF 0 "register_operand" "=x") (and:TF (not:TF (match_operand:TF 1 "register_operand" "0")) -- 2.11.0