From 83a49fcb87b5cb6856e7a328e63cc7057364f11a Mon Sep 17 00:00:00 2001 From: uros Date: Mon, 19 May 2008 08:14:04 +0000 Subject: [PATCH] * config/i386/i386.c (ix86_secondary_reload): New static function. (TARGET_SECONDARY_RELOAD): New define. * config/i386/i386.h (SECONDARY_OUTPUT_RELOAD_CLASS): Remove. * config/i386/i386.md (reload_outqi): Remove. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@135526 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 12 +++++++++--- gcc/config/i386/i386.c | 33 +++++++++++++++++++++++++++++++++ gcc/config/i386/i386.h | 9 --------- gcc/config/i386/i386.md | 19 ------------------- 4 files changed, 42 insertions(+), 31 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 74b7b35d46e..7c0605d9719 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,7 +1,13 @@ +2008-05-19 Uros Bizjak + + * config/i386/i386.c (ix86_secondary_reload): New static function. + (TARGET_SECONDARY_RELOAD): New define. + * config/i386/i386.h (SECONDARY_OUTPUT_RELOAD_CLASS): Remove. + * config/i386/i386.md (reload_outqi): Remove. + 2008-05-18 Kaveh R. Ghazi PR middle-end/35509 - * builtins.c (mathfn_built_in_1): Renamed from mathfn_built_in. Add `implicit' parameter. Handle BUILT_IN_SIGNBIT. (mathfn_built_in): Rewrite in terms of mathfn_built_in_1. @@ -13,7 +19,6 @@ * doc/extend.texi: Document __builtin_isinf_sign. * fold-const.c (operand_equal_p): Handle COND_EXPR. - 2008-05-18 Eric Botcazou * tree-ssa-dom.c (tree_ssa_dominator_optimize): If some blocks need @@ -86,7 +91,8 @@ * ifcvt.c (dead_or_predicable): Rename df_simulate_one_insn_backwards to df_simulate_one_insn. * recog.c (peephole2_optimize): Ditto. - * rtl-factoring.c (collect_pattern_seqs, clear_regs_live_in_seq): Ditto. + * rtl-factoring.c (collect_pattern_seqs, clear_regs_live_in_seq): + Ditto. * df.h: Rename df_simulate_one_insn_backwards to df_simulate_one_insn. and delete df_simulate_one_insn_forwards. * df-problems.c (df_simulate_artificial_refs_at_top) Reversed diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index af1e6c60b55..fa3df97a2b6 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -22023,6 +22023,36 @@ ix86_preferred_output_reload_class (rtx x, enum reg_class regclass) return regclass; } +static enum reg_class +ix86_secondary_reload (bool in_p, rtx x, enum reg_class class, + enum machine_mode mode, + secondary_reload_info *sri ATTRIBUTE_UNUSED) +{ + /* QImode spills from non-QI registers require + intermediate register on 32bit targets. */ + if (!in_p && mode == QImode && !TARGET_64BIT + && (class == GENERAL_REGS + || class == LEGACY_REGS + || class == INDEX_REGS)) + { + int regno; + + if (REG_P (x)) + regno = REGNO (x); + else + regno = -1; + + if (regno >= FIRST_PSEUDO_REGISTER || GET_CODE (x) == SUBREG) + regno = true_regnum (x); + + /* Return Q_REGS if the operand is in memory. */ + if (regno == -1) + return Q_REGS; + } + + return NO_REGS; +} + /* If we are copying between general and FP registers, we need a memory location. The same is true for SSE and MMX registers. @@ -25878,6 +25908,9 @@ x86_builtin_vectorization_cost (bool runtime_test) #undef TARGET_FUNCTION_VALUE #define TARGET_FUNCTION_VALUE ix86_function_value +#undef TARGET_SECONDARY_RELOAD +#define TARGET_SECONDARY_RELOAD ix86_secondary_reload + #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST x86_builtin_vectorization_cost diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index 8516e53b41d..f259d74d9d7 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -1524,15 +1524,6 @@ enum reg_class ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \ : MODE) -/* QImode spills from non-QI registers need a scratch. This does not - happen often -- the only example so far requires an uninitialized - pseudo. */ - -#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, OUT) \ - (((CLASS) == GENERAL_REGS || (CLASS) == LEGACY_REGS \ - || (CLASS) == INDEX_REGS) && !TARGET_64BIT && (MODE) == QImode \ - ? Q_REGS : NO_REGS) - /* Return the maximum number of consecutive registers needed to represent mode MODE in a register of class CLASS. */ /* On the 80386, this is the size of MODE in words, diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 145c373ff75..a021e7c75e7 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -1810,25 +1810,6 @@ ] (const_string "QI")))]) -(define_expand "reload_outqi" - [(parallel [(match_operand:QI 0 "" "=m") - (match_operand:QI 1 "register_operand" "r") - (match_operand:QI 2 "register_operand" "=&q")])] - "" -{ - rtx op0, op1, op2; - op0 = operands[0]; op1 = operands[1]; op2 = operands[2]; - - gcc_assert (!reg_overlap_mentioned_p (op2, op0)); - if (! q_regs_operand (op1, QImode)) - { - emit_insn (gen_movqi (op2, op1)); - op1 = op2; - } - emit_insn (gen_movqi (op0, op1)); - DONE; -}) - (define_insn "*swapqi_1" [(set (match_operand:QI 0 "register_operand" "+r") (match_operand:QI 1 "register_operand" "+r")) -- 2.11.0