From 736414abfae0b48aff05d9452c4c20b7eb4d92b0 Mon Sep 17 00:00:00 2001 From: rth Date: Fri, 29 Mar 2002 18:39:56 +0000 Subject: [PATCH] * config/ia64/ia64.md (*ptr_extend_plus_1, *ptr_extend_plus_2): New. * config/ia64/ia64.c (basereg_operand): New. * config/ia64/ia64-protos.h (basereg_operand): Declare. * config/ia64/ia64.h (PREDICATE_CODES): Add basereg_operand. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@51564 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 7 +++++++ gcc/config/ia64/ia64-protos.h | 1 + gcc/config/ia64/ia64.c | 15 +++++++++++++++ gcc/config/ia64/ia64.h | 3 ++- gcc/config/ia64/ia64.md | 23 +++++++++++++++++++++++ 5 files changed, 48 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 702a2d378fc..17695ffa5db 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2002-03-29 Steve Ellcey + + * config/ia64/ia64.md (*ptr_extend_plus_1, *ptr_extend_plus_2): New. + * config/ia64/ia64.c (basereg_operand): New. + * config/ia64/ia64-protos.h (basereg_operand): Declare. + * config/ia64/ia64.h (PREDICATE_CODES): Add basereg_operand. + 2002-03-29 Hans-Peter Nilsson * config/mmix/mmix.c (mmix_target_asm_function_prologue): Correct diff --git a/gcc/config/ia64/ia64-protos.h b/gcc/config/ia64/ia64-protos.h index cedeee20ec5..2bf67b24f0f 100644 --- a/gcc/config/ia64/ia64-protos.h +++ b/gcc/config/ia64/ia64-protos.h @@ -66,6 +66,7 @@ extern int ar_pfs_reg_operand PARAMS((rtx, enum machine_mode)); extern int general_tfmode_operand PARAMS((rtx, enum machine_mode)); extern int destination_tfmode_operand PARAMS((rtx, enum machine_mode)); extern int tfreg_or_fp01_operand PARAMS((rtx, enum machine_mode)); +extern int basereg_operand PARAMS((rtx, enum machine_mode)); extern int ia64_move_ok PARAMS((rtx, rtx)); extern int ia64_depz_field_mask PARAMS((rtx, rtx)); diff --git a/gcc/config/ia64/ia64.c b/gcc/config/ia64/ia64.c index c78d6319d82..78ba70e1e85 100644 --- a/gcc/config/ia64/ia64.c +++ b/gcc/config/ia64/ia64.c @@ -864,6 +864,21 @@ tfreg_or_fp01_operand (op, mode) return 0; return fr_reg_or_fp01_operand (op, mode); } + +/* Return 1 if OP is valid as a base register in a reg + offset address. */ + +int +basereg_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + /* ??? Should I copy the flag_omit_frame_pointer and cse_not_expected + checks from pa.c basereg_operand as well? Seems to be OK without them + in test runs. */ + + return (register_operand (op, mode) && + REG_POINTER ((GET_CODE (op) == SUBREG) ? SUBREG_REG (op) : op)); +} /* Return 1 if the operands of a move are ok. */ diff --git a/gcc/config/ia64/ia64.h b/gcc/config/ia64/ia64.h index 8e3eaeea8bf..ba8c44ca710 100644 --- a/gcc/config/ia64/ia64.h +++ b/gcc/config/ia64/ia64.h @@ -2351,7 +2351,8 @@ do { \ { "ar_pfs_reg_operand", {REG}}, \ { "general_tfmode_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \ { "destination_tfmode_operand", {SUBREG, REG, MEM}}, \ -{ "tfreg_or_fp01_operand", {REG, CONST_DOUBLE}}, +{ "tfreg_or_fp01_operand", {REG, CONST_DOUBLE}}, \ +{ "basereg_operand", {SUBREG, REG}}, /* An alias for a machine mode name. This is the machine mode that elements of a jump-table should have. */ diff --git a/gcc/config/ia64/ia64.md b/gcc/config/ia64/ia64.md index c88e8b0270a..8b134a67874 100644 --- a/gcc/config/ia64/ia64.md +++ b/gcc/config/ia64/ia64.md @@ -5304,6 +5304,29 @@ [(set_attr "itanium_class" "ialu")]) ;; +;; Optimizations for ptr_extend + +(define_insn "*ptr_extend_plus_1" + [(set (match_operand:DI 0 "gr_register_operand" "=r") + (unspec:DI + [(plus:SI (match_operand:SI 1 "basereg_operand" "r") + (match_operand:SI 2 "gr_reg_or_14bit_operand" "rI"))] + 24))] + "" + "addp4 %0 = %2, %1" + [(set_attr "itanium_class" "ialu")]) + +(define_insn "*ptr_extend_plus_2" + [(set (match_operand:DI 0 "gr_register_operand" "=r") + (unspec:DI + [(plus:SI (match_operand:SI 1 "gr_register_operand" "r") + (match_operand:SI 2 "basereg_operand" "r"))] + 24))] + "" + "addp4 %0 = %1, %2" + [(set_attr "itanium_class" "ialu")]) + +;; ;; As USE insns aren't meaningful after reload, this is used instead ;; to prevent deleting instructions setting registers for EH handling (define_insn "prologue_use" -- 2.11.0