From 622e3203a873b52ca2768e6a198ee1f92528b778 Mon Sep 17 00:00:00 2001 From: bernds Date: Tue, 21 Feb 2006 15:32:21 +0000 Subject: [PATCH] * config/bfin/predicates.md (cc_operand): Delete predicate. All uses replaced with register_operand. * config/bfin/bfin.c (bfin_register_move_cost): Moving CC to any non-DREG is expensive. * config/bfin/bfin.h (FIXED_REGISTERS): CC isn't fixed. * config/bfin/bfin.md (movbi): Fix constraints and template for moves involving memory. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@111336 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 10 ++++++++++ gcc/config/bfin/bfin.c | 8 +++++++- gcc/config/bfin/bfin.h | 4 ++-- gcc/config/bfin/bfin.md | 44 +++++++++++++++++++++---------------------- gcc/config/bfin/predicates.md | 7 ++----- 5 files changed, 43 insertions(+), 30 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 78e6fc294dc..3702a69143b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +2006-02-21 Bernd Schmidt + + * config/bfin/predicates.md (cc_operand): Delete predicate. All uses + replaced with register_operand. + * config/bfin/bfin.c (bfin_register_move_cost): Moving CC to any + non-DREG is expensive. + * config/bfin/bfin.h (FIXED_REGISTERS): CC isn't fixed. + * config/bfin/bfin.md (movbi): Fix constraints and template for moves + involving memory. + 2006-02-21 Joseph S. Myers * doc/install.texi2html: Use set -e. diff --git a/gcc/config/bfin/bfin.c b/gcc/config/bfin/bfin.c index b60716d9f97..079b91916c1 100644 --- a/gcc/config/bfin/bfin.c +++ b/gcc/config/bfin/bfin.c @@ -1,5 +1,5 @@ /* The Blackfin code generation auxiliary output file. - Copyright (C) 2005 Free Software Foundation, Inc. + Copyright (C) 2005, 2006 Free Software Foundation, Inc. Contributed by Analog Devices. This file is part of GCC. @@ -1685,6 +1685,11 @@ int bfin_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED, enum reg_class class1, enum reg_class class2) { + /* These need secondary reloads, so they're more expensive. */ + if ((class1 == CCREGS && class2 != DREGS) + || (class1 != DREGS && class2 == CCREGS)) + return 4; + /* If optimizing for size, always prefer reg-reg over reg-memory moves. */ if (optimize_size) return 2; @@ -1788,6 +1793,7 @@ bfin_secondary_reload (bool in_p, rtx x, enum reg_class class, return DREGS; if (x_class == CCREGS && class != DREGS) return DREGS; + /* All registers other than AREGS can load arbitrary constants. The only case that remains is MEM. */ if (code == MEM) diff --git a/gcc/config/bfin/bfin.h b/gcc/config/bfin/bfin.h index 803aa589291..171edb928ab 100644 --- a/gcc/config/bfin/bfin.h +++ b/gcc/config/bfin/bfin.h @@ -1,5 +1,5 @@ /* Definitions for the Blackfin port. - Copyright (C) 2005 Free Software Foundation, Inc. + Copyright (C) 2005, 2006 Free Software Foundation, Inc. Contributed by Analog Devices. This file is part of GCC. @@ -256,7 +256,7 @@ extern const char *bfin_library_id_string; /*i0 i1 i2 i3 b0 b1 b2 b3 l0 l1 l2 l3 m0 m1 m2 m3 */ \ 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, \ /*a0 a1 cc rets/i/x/n/e astat seqstat usp argp */ \ - 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \ + 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1 \ } /* 1 for registers not available across function calls. diff --git a/gcc/config/bfin/bfin.md b/gcc/config/bfin/bfin.md index 63fc99ca1fe..fb806330cbe 100644 --- a/gcc/config/bfin/bfin.md +++ b/gcc/config/bfin/bfin.md @@ -1,5 +1,5 @@ ;;- Machine description for Blackfin for GNU compiler -;; Copyright 2005 Free Software Foundation, Inc. +;; Copyright 2005, 2006 Free Software Foundation, Inc. ;; Contributed by Analog Devices. ;; This file is part of GCC. @@ -239,7 +239,7 @@ (define_insn "*movsicc_insn1" [(set (match_operand:SI 0 "register_operand" "=da,da,da") (if_then_else:SI - (eq:BI (match_operand:BI 3 "cc_operand" "C,C,C") + (eq:BI (match_operand:BI 3 "register_operand" "C,C,C") (const_int 0)) (match_operand:SI 1 "register_operand" "da,0,da") (match_operand:SI 2 "register_operand" "0,da,da")))] @@ -254,7 +254,7 @@ (define_insn "*movsicc_insn2" [(set (match_operand:SI 0 "register_operand" "=da,da,da") (if_then_else:SI - (ne:BI (match_operand:BI 3 "cc_operand" "C,C,C") + (ne:BI (match_operand:BI 3 "register_operand" "C,C,C") (const_int 0)) (match_operand:SI 1 "register_operand" "0,da,da") (match_operand:SI 2 "register_operand" "da,0,da")))] @@ -344,15 +344,15 @@ }) (define_insn "movbi" - [(set (match_operand:BI 0 "nonimmediate_operand" "=x,x,d,mr,C,d,C") - (match_operand:BI 1 "general_operand" "x,xKs3,mr,d,d,C,P0"))] + [(set (match_operand:BI 0 "nonimmediate_operand" "=x,x,d,md,C,d,C") + (match_operand:BI 1 "general_operand" "x,xKs3,md,d,d,C,P0"))] "" "@ %0 = %1; %0 = %1 (X); - %0 = %1; - %0 = %1; + %0 = B %1 (Z); + B %0 = %1; CC = %1; %0 = CC; R0 = R0 | R0; CC = AC0;" @@ -967,7 +967,7 @@ ;; Bit test instructions (define_insn "*not_bittst" - [(set (match_operand:BI 0 "cc_operand" "=C") + [(set (match_operand:BI 0 "register_operand" "=C") (eq:BI (zero_extract:SI (match_operand:SI 1 "register_operand" "d") (const_int 1) (match_operand:SI 2 "immediate_operand" "Ku5")) @@ -977,7 +977,7 @@ [(set_attr "type" "alu0")]) (define_insn "*bittst" - [(set (match_operand:BI 0 "cc_operand" "=C") + [(set (match_operand:BI 0 "register_operand" "=C") (ne:BI (zero_extract:SI (match_operand:SI 1 "register_operand" "d") (const_int 1) (match_operand:SI 2 "immediate_operand" "Ku5")) @@ -1530,7 +1530,7 @@ }) (define_insn "compare_eq" - [(set (match_operand:BI 0 "cc_operand" "=C,C") + [(set (match_operand:BI 0 "register_operand" "=C,C") (eq:BI (match_operand:SI 1 "register_operand" "d,a") (match_operand:SI 2 "reg_or_const_int_operand" "dKs3,aKs3")))] "" @@ -1538,7 +1538,7 @@ [(set_attr "type" "compare")]) (define_insn "compare_ne" - [(set (match_operand:BI 0 "cc_operand" "=C,C") + [(set (match_operand:BI 0 "register_operand" "=C,C") (ne:BI (match_operand:SI 1 "register_operand" "d,a") (match_operand:SI 2 "reg_or_const_int_operand" "dKs3,aKs3")))] "0" @@ -1546,7 +1546,7 @@ [(set_attr "type" "compare")]) (define_insn "compare_lt" - [(set (match_operand:BI 0 "cc_operand" "=C,C") + [(set (match_operand:BI 0 "register_operand" "=C,C") (lt:BI (match_operand:SI 1 "register_operand" "d,a") (match_operand:SI 2 "reg_or_const_int_operand" "dKs3,aKs3")))] "" @@ -1554,7 +1554,7 @@ [(set_attr "type" "compare")]) (define_insn "compare_le" - [(set (match_operand:BI 0 "cc_operand" "=C,C") + [(set (match_operand:BI 0 "register_operand" "=C,C") (le:BI (match_operand:SI 1 "register_operand" "d,a") (match_operand:SI 2 "reg_or_const_int_operand" "dKs3,aKs3")))] "" @@ -1562,7 +1562,7 @@ [(set_attr "type" "compare")]) (define_insn "compare_leu" - [(set (match_operand:BI 0 "cc_operand" "=C,C") + [(set (match_operand:BI 0 "register_operand" "=C,C") (leu:BI (match_operand:SI 1 "register_operand" "d,a") (match_operand:SI 2 "reg_or_const_int_operand" "dKu3,aKu3")))] "" @@ -1570,7 +1570,7 @@ [(set_attr "type" "compare")]) (define_insn "compare_ltu" - [(set (match_operand:BI 0 "cc_operand" "=C,C") + [(set (match_operand:BI 0 "register_operand" "=C,C") (ltu:BI (match_operand:SI 1 "register_operand" "d,a") (match_operand:SI 2 "reg_or_const_int_operand" "dKu3,aKu3")))] "" @@ -1735,7 +1735,7 @@ [(set (pc) (if_then_else (match_operator 0 "bfin_cbranch_operator" - [(match_operand:BI 1 "cc_operand" "C") + [(match_operand:BI 1 "register_operand" "C") (match_operand:BI 2 "immediate_operand" "P0")]) (label_ref (match_operand 3 "" "")) (pc)))] @@ -1753,7 +1753,7 @@ [(set (pc) (if_then_else (match_operator 0 "bfin_cbranch_operator" - [(match_operand:BI 1 "cc_operand" "C") + [(match_operand:BI 1 "register_operand" "C") (match_operand:BI 2 "immediate_operand" "P0")]) (label_ref (match_operand 3 "" "")) (pc))) @@ -1769,7 +1769,7 @@ [(set (pc) (if_then_else (match_operator 0 "bfin_cbranch_operator" - [(match_operand:BI 1 "cc_operand" "C") + [(match_operand:BI 1 "register_operand" "C") (match_operand:BI 2 "immediate_operand" "P0")]) (label_ref (match_operand 3 "" "")) (pc))) @@ -1845,7 +1845,7 @@ ;;;;;;;;;;;;;;;;;;;; CC2dreg ;;;;;;;;;;;;;;;;;;;;;;;;; (define_insn "movsibi" - [(set (match_operand:BI 0 "cc_operand" "=C") + [(set (match_operand:BI 0 "register_operand" "=C") (ne:BI (match_operand:SI 1 "register_operand" "d") (const_int 0)))] "" @@ -1854,15 +1854,15 @@ (define_insn "movbisi" [(set (match_operand:SI 0 "register_operand" "=d") - (ne:SI (match_operand:BI 1 "cc_operand" "C") + (ne:SI (match_operand:BI 1 "register_operand" "C") (const_int 0)))] "" "%0 = CC;" [(set_attr "length" "2")]) (define_insn "" - [(set (match_operand:BI 0 "cc_operand" "=C") - (eq:BI (match_operand:BI 1 "cc_operand" " 0") + [(set (match_operand:BI 0 "register_operand" "=C") + (eq:BI (match_operand:BI 1 "register_operand" " 0") (const_int 0)))] "" "%0 = ! %0;" /* NOT CC;" */ diff --git a/gcc/config/bfin/predicates.md b/gcc/config/bfin/predicates.md index bf9972f7667..dc0da877d75 100644 --- a/gcc/config/bfin/predicates.md +++ b/gcc/config/bfin/predicates.md @@ -1,4 +1,6 @@ ;; Predicate definitions for the Blackfin. +;; Copyright (C) 2005, 2006 Free Software Foundation, Inc. +;; Contributed by Analog Devices. ;; ;; This file is part of GCC. ;; @@ -65,11 +67,6 @@ return 1; }) -;; Return nonzero if OP is the CC register. -(define_predicate "cc_operand" - (and (match_code "reg") - (match_test "REGNO (op) == REG_CC && GET_MODE (op) == BImode"))) - ;; Return nonzero if OP is a register or a 7 bit signed constant. (define_predicate "reg_or_7bit_operand" (ior (match_operand 0 "register_operand") -- 2.11.0