From 60f1f5ccc33cee0c5ab6170d0ed29d2b68e182d5 Mon Sep 17 00:00:00 2001 From: hubicka Date: Fri, 29 Sep 2000 11:40:24 +0000 Subject: [PATCH] * final.c (final_scan_insn): Remove extra extract_insn call; Use caching for constrain_operands. (cleanup_subreg_operands): Use caching for extract_insn. * recog.c (constrain_operands_cached): New. * recog.h (constrain_operands_cached): Declare. * i386.c (ix86_attr_length_immediate_default, ix86_attr_length_address_default, ix86_agi_dependant): Cache extract_insn call. * recog.c (asm_noperands): Tweak. (extract_insn): Do not call asm_noperads for non-asm instructions. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@36665 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 45 ++++++++++++++++ gcc/config/i386/i386.c | 6 +-- gcc/final.c | 6 +-- gcc/recog.c | 140 +++++++++++++++++++++++++++++-------------------- gcc/recog.h | 5 +- 5 files changed, 138 insertions(+), 64 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 0df5e8f1f8d..055714bfd59 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,48 @@ +Fri Sep 29 13:37:59 MET DST 2000 Jan Hubicka + + * final.c (final_scan_insn): Remove extra extract_insn call; + Use caching for constrain_operands. + (cleanup_subreg_operands): Use caching for extract_insn. + * recog.c (constrain_operands_cached): New. + * recog.h (constrain_operands_cached): Declare. + * i386.c (ix86_attr_length_immediate_default, + ix86_attr_length_address_default, ix86_agi_dependant): Cache + extract_insn call. + + * recog.c (asm_noperands): Tweak. + (extract_insn): Do not call asm_noperads for non-asm instructions. + +Fri Sep 29 13:20:42 MET DST 2000 Jan Hubicka + + * recog.c (recog_memoized): Rename to recog_memoized_1. + * recog.h (recog_memoized): Rename to recog_memoized_1. + (recog_memoized): New macro. + * rtl.h (single_set): Rename to single_set_1 + (single_set): New macro. + * rtlanal.c (single_set): Rename to single_set_1; expect clobbers + to be last. + + * i386.md (strmovsi_1, strmovhi_1 strmovqi_1): + Do not use match_dup of input operands at outputs. + Use register_operand for memory expression. + (rep_movsi): Put use last, canonicalize. + Use register_operand for memory expression. + (rep_movqi): Put use last. + Use register_operand for memory expression. + (strsetsi_1, strset_hi_1, strsetqi_1): Do not use match_dup + of input operands at outputs. Use register_operand for memory + expression. + (rep_stossi): Put use last; canonicalize; fix match_dup in + the address expression + (rep_stosqi): Likewise. + (memcmp expander): Update calls. + (cmpstrsi_nz_1, cmpstrsi_1, strlensi_1): Avoid match_dups in + the clobbers. + + * i386.md (fp_jcc_3, fp_jcc_4, jp_fcc_5): if_then_else operand is + VOIDmode. + (fp_jcc_4, fp_jcc_3): Refuse unordered comparisons. + 2000-09-28 David O'Brien * config/i386/freebsd-aout.h: New, FreeBSD a.out config file. diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 5521ea291a9..b66e5a4df56 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -6272,7 +6272,7 @@ ix86_attr_length_immediate_default (insn, shortform) { int len = 0; int i; - extract_insn (insn); + extract_insn_cached (insn); for (i = recog_data.n_operands - 1; i >= 0; --i) if (CONSTANT_P (recog_data.operand[i])) { @@ -6308,7 +6308,7 @@ ix86_attr_length_address_default (insn) rtx insn; { int i; - extract_insn (insn); + extract_insn_cached (insn); for (i = recog_data.n_operands - 1; i >= 0; --i) if (GET_CODE (recog_data.operand[i]) == MEM) { @@ -6409,7 +6409,7 @@ ix86_agi_dependant (insn, dep_insn, insn_type) else { int i; - extract_insn (insn); + extract_insn_cached (insn); for (i = recog_data.n_operands - 1; i >= 0; --i) if (GET_CODE (recog_data.operand[i]) == MEM) { diff --git a/gcc/final.c b/gcc/final.c index bfd47545d6a..0e22b069461 100644 --- a/gcc/final.c +++ b/gcc/final.c @@ -2919,7 +2919,6 @@ final_scan_insn (insn, file, optimize, prescan, nopeepholes) since `reload' should have changed them so that they do. */ insn_code_number = recog_memoized (insn); - extract_insn (insn); cleanup_subreg_operands (insn); /* Dump the insn in the assembly for debugging. */ @@ -2930,7 +2929,7 @@ final_scan_insn (insn, file, optimize, prescan, nopeepholes) print_rtx_head = ""; } - if (! constrain_operands (1)) + if (! constrain_operands_cached (1)) fatal_insn_not_found (insn); /* Some target machines need to prescan each insn before @@ -3138,8 +3137,7 @@ cleanup_subreg_operands (insn) rtx insn; { int i; - - extract_insn (insn); + extract_insn_cached (insn); for (i = 0; i < recog_data.n_operands; i++) { if (GET_CODE (recog_data.operand[i]) == SUBREG) diff --git a/gcc/recog.c b/gcc/recog.c index 248f8d8afed..d88ac05aaf9 100644 --- a/gcc/recog.c +++ b/gcc/recog.c @@ -1401,68 +1401,75 @@ int asm_noperands (body) rtx body; { - if (GET_CODE (body) == ASM_OPERANDS) - /* No output operands: return number of input operands. */ - return ASM_OPERANDS_INPUT_LENGTH (body); - if (GET_CODE (body) == SET && GET_CODE (SET_SRC (body)) == ASM_OPERANDS) - /* Single output operand: BODY is (set OUTPUT (asm_operands ...)). */ - return ASM_OPERANDS_INPUT_LENGTH (SET_SRC (body)) + 1; - else if (GET_CODE (body) == PARALLEL - && GET_CODE (XVECEXP (body, 0, 0)) == SET - && GET_CODE (SET_SRC (XVECEXP (body, 0, 0))) == ASM_OPERANDS) + switch (GET_CODE (body)) { - /* Multiple output operands, or 1 output plus some clobbers: - body is [(set OUTPUT (asm_operands ...))... (clobber (reg ...))...]. */ - int i; - int n_sets; - - /* Count backwards through CLOBBERs to determine number of SETs. */ - for (i = XVECLEN (body, 0); i > 0; i--) + case ASM_OPERANDS: + /* No output operands: return number of input operands. */ + return ASM_OPERANDS_INPUT_LENGTH (body); + case SET: + if (GET_CODE (SET_SRC (body)) == ASM_OPERANDS) + /* Single output operand: BODY is (set OUTPUT (asm_operands ...)). */ + return ASM_OPERANDS_INPUT_LENGTH (SET_SRC (body)) + 1; + else + return -1; + case PARALLEL: + if (GET_CODE (XVECEXP (body, 0, 0)) == SET + && GET_CODE (SET_SRC (XVECEXP (body, 0, 0))) == ASM_OPERANDS) { - if (GET_CODE (XVECEXP (body, 0, i - 1)) == SET) - break; - if (GET_CODE (XVECEXP (body, 0, i - 1)) != CLOBBER) - return -1; - } + /* Multiple output operands, or 1 output plus some clobbers: + body is [(set OUTPUT (asm_operands ...))... (clobber (reg ...))...]. */ + int i; + int n_sets; - /* N_SETS is now number of output operands. */ - n_sets = i; + /* Count backwards through CLOBBERs to determine number of SETs. */ + for (i = XVECLEN (body, 0); i > 0; i--) + { + if (GET_CODE (XVECEXP (body, 0, i - 1)) == SET) + break; + if (GET_CODE (XVECEXP (body, 0, i - 1)) != CLOBBER) + return -1; + } - /* Verify that all the SETs we have - came from a single original asm_operands insn - (so that invalid combinations are blocked). */ - for (i = 0; i < n_sets; i++) - { - rtx elt = XVECEXP (body, 0, i); - if (GET_CODE (elt) != SET) - return -1; - if (GET_CODE (SET_SRC (elt)) != ASM_OPERANDS) - return -1; - /* If these ASM_OPERANDS rtx's came from different original insns - then they aren't allowed together. */ - if (ASM_OPERANDS_INPUT_VEC (SET_SRC (elt)) - != ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP (body, 0, 0)))) - return -1; + /* N_SETS is now number of output operands. */ + n_sets = i; + + /* Verify that all the SETs we have + came from a single original asm_operands insn + (so that invalid combinations are blocked). */ + for (i = 0; i < n_sets; i++) + { + rtx elt = XVECEXP (body, 0, i); + if (GET_CODE (elt) != SET) + return -1; + if (GET_CODE (SET_SRC (elt)) != ASM_OPERANDS) + return -1; + /* If these ASM_OPERANDS rtx's came from different original insns + then they aren't allowed together. */ + if (ASM_OPERANDS_INPUT_VEC (SET_SRC (elt)) + != ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP (body, 0, 0)))) + return -1; + } + return (ASM_OPERANDS_INPUT_LENGTH (SET_SRC (XVECEXP (body, 0, 0))) + + n_sets); } - return (ASM_OPERANDS_INPUT_LENGTH (SET_SRC (XVECEXP (body, 0, 0))) - + n_sets); - } - else if (GET_CODE (body) == PARALLEL - && GET_CODE (XVECEXP (body, 0, 0)) == ASM_OPERANDS) - { - /* 0 outputs, but some clobbers: - body is [(asm_operands ...) (clobber (reg ...))...]. */ - int i; + else if (GET_CODE (XVECEXP (body, 0, 0)) == ASM_OPERANDS) + { + /* 0 outputs, but some clobbers: + body is [(asm_operands ...) (clobber (reg ...))...]. */ + int i; - /* Make sure all the other parallel things really are clobbers. */ - for (i = XVECLEN (body, 0) - 1; i > 0; i--) - if (GET_CODE (XVECEXP (body, 0, i)) != CLOBBER) - return -1; + /* Make sure all the other parallel things really are clobbers. */ + for (i = XVECLEN (body, 0) - 1; i > 0; i--) + if (GET_CODE (XVECEXP (body, 0, i)) != CLOBBER) + return -1; - return ASM_OPERANDS_INPUT_LENGTH (XVECEXP (body, 0, 0)); + return ASM_OPERANDS_INPUT_LENGTH (XVECEXP (body, 0, 0)); + } + else + return -1; + default: + return -1; } - else - return -1; } /* Assuming BODY is an insn body that uses ASM_OPERANDS, @@ -2069,6 +2076,16 @@ extract_constrain_insn_cached (insn) && !constrain_operands (reload_completed)) fatal_insn_not_found (insn); } +/* Do cached constrain_operand and complain about failures. */ +int +constrain_operands_cached (strict) + int strict; +{ + if (which_alternative == -1) + return constrain_operands (strict); + else + return 1; +} /* Analyze INSN and fill in recog_data. */ @@ -2097,8 +2114,19 @@ extract_insn (insn) return; case SET: + if (GET_CODE (SET_SRC (body)) == ASM_OPERANDS) + goto asm_insn; + else + goto normal_insn; case PARALLEL: + if ((GET_CODE (XVECEXP (body, 0, 0)) == SET + && GET_CODE (SET_SRC (XVECEXP (body, 0, 0))) == ASM_OPERANDS) + || GET_CODE (XVECEXP (body, 0, 0)) == ASM_OPERANDS) + goto asm_insn; + else + goto normal_insn; case ASM_OPERANDS: + asm_insn: recog_data.n_operands = noperands = asm_noperands (body); if (noperands >= 0) { @@ -2122,10 +2150,10 @@ extract_insn (insn) } break; } - - /* FALLTHROUGH */ + fatal_insn_not_found (insn); default: + normal_insn: /* Ordinary insn: recognize it, get the operands via insn_extract and get the constraints. */ diff --git a/gcc/recog.h b/gcc/recog.h index 3328af6850a..5987cfcbc33 100644 --- a/gcc/recog.h +++ b/gcc/recog.h @@ -21,6 +21,8 @@ Boston, MA 02111-1307, USA. */ /* Random number that should be large enough for all purposes. */ #define MAX_RECOG_ALTERNATIVES 30 +#define recog_memoized(I) (INSN_CODE (I) >= 0 \ + ? INSN_CODE (I) : recog_memoized_1 (I)) /* Types of operands. */ enum op_type { @@ -69,7 +71,7 @@ struct operand_alternative extern void init_recog PARAMS ((void)); extern void init_recog_no_volatile PARAMS ((void)); -extern int recog_memoized PARAMS ((rtx)); +extern int recog_memoized_1 PARAMS ((rtx)); extern int check_asm_operands PARAMS ((rtx)); extern int asm_operand_ok PARAMS ((rtx, const char *)); extern int validate_change PARAMS ((rtx, rtx *, rtx, int)); @@ -77,6 +79,7 @@ extern int apply_change_group PARAMS ((void)); extern int num_validated_changes PARAMS ((void)); extern void cancel_changes PARAMS ((int)); extern int constrain_operands PARAMS ((int)); +extern int constrain_operands_cached PARAMS ((int)); extern int memory_address_p PARAMS ((enum machine_mode, rtx)); extern int strict_memory_address_p PARAMS ((enum machine_mode, rtx)); extern int validate_replace_rtx_subexp PARAMS ((rtx, rtx, rtx, rtx *)); -- 2.11.0