From 048fbb59c7cfac095d07700c42cd932a84b306f2 Mon Sep 17 00:00:00 2001 From: dwarak Date: Wed, 4 Nov 2009 21:15:42 +0000 Subject: [PATCH] 2009-11-04 Harsha Jagasia Dwarakanath Rajagopal * doc/invoke.texi (-mlwp): Add documentation. * doc/extend.texi (x86 intrinsics): Add LWP intrinsics. * config.gcc (i[34567]86-*-*): Include lwpintrin.h. (x86_64-*-*): Ditto. * config/i386/lwpintrin.h: New file, provide x86 compiler intrinisics for LWP. * config/i386/cpuid.h (bit_LWP): Define LWP bit. * config/i386/x86intrin.h: Add LWP check and lwpintrin.h. * config/i386/i386-c.c (ix86_target_macros_internal): Check ISA_FLAG for LWP. * config/i386/i386.h (TARGET_LWP): New macro for LWP. * config/i386/i386.opt (-mlwp): New switch for LWP support. * config/i386/i386.c (OPTION_MASK_ISA_LWP_SET): New. (OPTION_MASK_ISA_LWP_UNSET): New. (ix86_handle_option): Handle -mlwp. (isa_opts): Handle -mlwp. (enum pta_flags): Add PTA_LWP. (override_options): Add LWP support. (IX86_BUILTIN_LLWPCB16): New for LWP intrinsic. (IX86_BUILTIN_LLWPCB32): Ditto. (IX86_BUILTIN_LLWPCB64): Ditto. (IX86_BUILTIN_SLWPCB16): Ditto. (IX86_BUILTIN_SLWPCB32): Ditto. (IX86_BUILTIN_SLWPCB64): Ditto. (IX86_BUILTIN_LWPVAL16): Ditto. (IX86_BUILTIN_LWPVAL32): Ditto. (IX86_BUILTIN_LWPVAL64): Ditto. (IX86_BUILTIN_LWPINS16): Ditto. (IX86_BUILTIN_LWPINS32): Ditto. (IX86_BUILTIN_LWPINS64): Ditto. (enum ix86_special_builtin_type): Add LWP intrinsic support. (builtin_description): Ditto. (ix86_init_mmx_sse_builtins): Ditto. (ix86_expand_special_args_builtin): Ditto. * config/i386/i386.md (UNSPEC_LLWP_INTRINSIC): Add new UNSPEC for LWP support. (UNSPEC_SLWP_INTRINSIC): Ditto. (UNSPECV_LWPVAL_INTRINSIC): Ditto. (UNSPECV_LWPINS_INTRINSIC): Ditto. (lwp_llwpcbhi1): New lwp pattern. (lwp_llwpcbsi1): Ditto. (lwp_llwpcbdi1): Ditto. (lwp_slwpcbhi1): Ditto. (lwp_slwpcbsi1): Ditto. (lwp_slwpcbdi1): Ditto. (lwp_lwpvalhi3): Ditto. (lwp_lwpvalsi3): Ditto. (lwp_lwpvaldi3): Ditto. (lwp_lwpinshi3): Ditto. (lwp_lwpinssi3): Ditto. (lwp_lwpinsdi3): Ditto. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@153917 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 55 ++++++++++++++++++ gcc/config.gcc | 4 +- gcc/config/i386/cpuid.h | 1 + gcc/config/i386/i386-c.c | 2 + gcc/config/i386/i386.c | 137 +++++++++++++++++++++++++++++++++++++++++++- gcc/config/i386/i386.h | 1 + gcc/config/i386/i386.md | 120 +++++++++++++++++++++++++++++++++++++- gcc/config/i386/i386.opt | 4 ++ gcc/config/i386/lwpintrin.h | 109 +++++++++++++++++++++++++++++++++++ gcc/config/i386/x86intrin.h | 4 ++ gcc/doc/extend.texi | 22 +++++++ gcc/doc/invoke.texi | 6 +- 12 files changed, 457 insertions(+), 8 deletions(-) create mode 100644 gcc/config/i386/lwpintrin.h diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d34908043dc..0ec0c60cf01 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,58 @@ +2009-11-04 Harsha Jagasia + Dwarakanath Rajagopal + + * doc/invoke.texi (-mlwp): Add documentation. + * doc/extend.texi (x86 intrinsics): Add LWP intrinsics. + * config.gcc (i[34567]86-*-*): Include lwpintrin.h. + (x86_64-*-*): Ditto. + * config/i386/lwpintrin.h: New file, provide x86 compiler + intrinisics for LWP. + * config/i386/cpuid.h (bit_LWP): Define LWP bit. + * config/i386/x86intrin.h: Add LWP check and lwpintrin.h. + * config/i386/i386-c.c (ix86_target_macros_internal): Check + ISA_FLAG for LWP. + * config/i386/i386.h (TARGET_LWP): New macro for LWP. + * config/i386/i386.opt (-mlwp): New switch for LWP support. + * config/i386/i386.c (OPTION_MASK_ISA_LWP_SET): New. + (OPTION_MASK_ISA_LWP_UNSET): New. + (ix86_handle_option): Handle -mlwp. + (isa_opts): Handle -mlwp. + (enum pta_flags): Add PTA_LWP. + (override_options): Add LWP support. + (IX86_BUILTIN_LLWPCB16): New for LWP intrinsic. + (IX86_BUILTIN_LLWPCB32): Ditto. + (IX86_BUILTIN_LLWPCB64): Ditto. + (IX86_BUILTIN_SLWPCB16): Ditto. + (IX86_BUILTIN_SLWPCB32): Ditto. + (IX86_BUILTIN_SLWPCB64): Ditto. + (IX86_BUILTIN_LWPVAL16): Ditto. + (IX86_BUILTIN_LWPVAL32): Ditto. + (IX86_BUILTIN_LWPVAL64): Ditto. + (IX86_BUILTIN_LWPINS16): Ditto. + (IX86_BUILTIN_LWPINS32): Ditto. + (IX86_BUILTIN_LWPINS64): Ditto. + (enum ix86_special_builtin_type): Add LWP intrinsic support. + (builtin_description): Ditto. + (ix86_init_mmx_sse_builtins): Ditto. + (ix86_expand_special_args_builtin): Ditto. + * config/i386/i386.md (UNSPEC_LLWP_INTRINSIC): Add new UNSPEC for + LWP support. + (UNSPEC_SLWP_INTRINSIC): Ditto. + (UNSPECV_LWPVAL_INTRINSIC): Ditto. + (UNSPECV_LWPINS_INTRINSIC): Ditto. + (lwp_llwpcbhi1): New lwp pattern. + (lwp_llwpcbsi1): Ditto. + (lwp_llwpcbdi1): Ditto. + (lwp_slwpcbhi1): Ditto. + (lwp_slwpcbsi1): Ditto. + (lwp_slwpcbdi1): Ditto. + (lwp_lwpvalhi3): Ditto. + (lwp_lwpvalsi3): Ditto. + (lwp_lwpvaldi3): Ditto. + (lwp_lwpinshi3): Ditto. + (lwp_lwpinssi3): Ditto. + (lwp_lwpinsdi3): Ditto. + 2009-11-04 Andrew Pinski Trevor Smigiel diff --git a/gcc/config.gcc b/gcc/config.gcc index e79d2251364..1d3c3fc84f8 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -288,7 +288,7 @@ i[34567]86-*-*) pmmintrin.h tmmintrin.h ammintrin.h smmintrin.h nmmintrin.h bmmintrin.h fma4intrin.h wmmintrin.h immintrin.h x86intrin.h avxintrin.h xopintrin.h - ia32intrin.h cross-stdarg.h" + ia32intrin.h cross-stdarg.h lwpintrin.h" ;; x86_64-*-*) cpu_type=i386 @@ -298,7 +298,7 @@ x86_64-*-*) pmmintrin.h tmmintrin.h ammintrin.h smmintrin.h nmmintrin.h bmmintrin.h fma4intrin.h wmmintrin.h immintrin.h x86intrin.h avxintrin.h xopintrin.h - ia32intrin.h cross-stdarg.h" + ia32intrin.h cross-stdarg.h lwpintrin.h" need_64bit_hwint=yes ;; ia64-*-*) diff --git a/gcc/config/i386/cpuid.h b/gcc/config/i386/cpuid.h index c37a883c260..21f0e3184ef 100644 --- a/gcc/config/i386/cpuid.h +++ b/gcc/config/i386/cpuid.h @@ -48,6 +48,7 @@ /* %ecx */ #define bit_FMA4 (1 << 16) #define bit_LAHF_LM (1 << 0) +#define bit_LWP (1 << 15) #define bit_SSE4a (1 << 6) #define bit_XOP (1 << 11) diff --git a/gcc/config/i386/i386-c.c b/gcc/config/i386/i386-c.c index cc5c8824c3a..5a5311fba0f 100644 --- a/gcc/config/i386/i386-c.c +++ b/gcc/config/i386/i386-c.c @@ -234,6 +234,8 @@ ix86_target_macros_internal (int isa_flag, def_or_undef (parse_in, "__FMA4__"); if (isa_flag & OPTION_MASK_ISA_XOP) def_or_undef (parse_in, "__XOP__"); + if (isa_flag & OPTION_MASK_ISA_LWP) + def_or_undef (parse_in, "__LWP__"); if ((fpmath & FPMATH_SSE) && (isa_flag & OPTION_MASK_ISA_SSE)) def_or_undef (parse_in, "__SSE_MATH__"); if ((fpmath & FPMATH_SSE) && (isa_flag & OPTION_MASK_ISA_SSE2)) diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index ce26a4d4ec6..1c064bf98d8 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -1966,6 +1966,8 @@ static int ix86_isa_flags_explicit; | OPTION_MASK_ISA_AVX_SET) #define OPTION_MASK_ISA_XOP_SET \ (OPTION_MASK_ISA_XOP | OPTION_MASK_ISA_FMA4_SET) +#define OPTION_MASK_ISA_LWP_SET \ + OPTION_MASK_ISA_LWP /* AES and PCLMUL need SSE2 because they use xmm registers */ #define OPTION_MASK_ISA_AES_SET \ @@ -2020,6 +2022,7 @@ static int ix86_isa_flags_explicit; #define OPTION_MASK_ISA_FMA4_UNSET \ (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_XOP_UNSET) #define OPTION_MASK_ISA_XOP_UNSET OPTION_MASK_ISA_XOP +#define OPTION_MASK_ISA_LWP_UNSET OPTION_MASK_ISA_LWP #define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES #define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL @@ -2280,6 +2283,19 @@ ix86_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED, int value) } return true; + case OPT_mlwp: + if (value) + { + ix86_isa_flags |= OPTION_MASK_ISA_LWP_SET; + ix86_isa_flags_explicit |= OPTION_MASK_ISA_LWP_SET; + } + else + { + ix86_isa_flags &= ~OPTION_MASK_ISA_LWP_UNSET; + ix86_isa_flags_explicit |= OPTION_MASK_ISA_LWP_UNSET; + } + return true; + case OPT_mabm: if (value) { @@ -2409,6 +2425,7 @@ ix86_target_string (int isa, int flags, const char *arch, const char *tune, { "-m64", OPTION_MASK_ISA_64BIT }, { "-mfma4", OPTION_MASK_ISA_FMA4 }, { "-mxop", OPTION_MASK_ISA_XOP }, + { "-mlwp", OPTION_MASK_ISA_LWP }, { "-msse4a", OPTION_MASK_ISA_SSE4A }, { "-msse4.2", OPTION_MASK_ISA_SSE4_2 }, { "-msse4.1", OPTION_MASK_ISA_SSE4_1 }, @@ -2640,7 +2657,8 @@ override_options (bool main_args_p) PTA_FMA = 1 << 19, PTA_MOVBE = 1 << 20, PTA_FMA4 = 1 << 21, - PTA_XOP = 1 << 22 + PTA_XOP = 1 << 22, + PTA_LWP = 1 << 23 }; static struct pta @@ -2989,6 +3007,9 @@ override_options (bool main_args_p) if (processor_alias_table[i].flags & PTA_XOP && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_XOP)) ix86_isa_flags |= OPTION_MASK_ISA_XOP; + if (processor_alias_table[i].flags & PTA_LWP + && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_LWP)) + ix86_isa_flags |= OPTION_MASK_ISA_LWP; if (processor_alias_table[i].flags & PTA_ABM && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_ABM)) ix86_isa_flags |= OPTION_MASK_ISA_ABM; @@ -3672,6 +3693,7 @@ ix86_valid_target_attribute_inner_p (tree args, char *p_strings[]) IX86_ATTR_ISA ("ssse3", OPT_mssse3), IX86_ATTR_ISA ("fma4", OPT_mfma4), IX86_ATTR_ISA ("xop", OPT_mxop), + IX86_ATTR_ISA ("lwp", OPT_mlwp), /* string options */ IX86_ATTR_STR ("arch=", IX86_FUNCTION_SPECIFIC_ARCH), @@ -20897,7 +20919,7 @@ enum ix86_builtins IX86_BUILTIN_CVTUDQ2PS, - /* FMA4 instructions. */ + /* FMA4 and XOP instructions. */ IX86_BUILTIN_VFMADDSS, IX86_BUILTIN_VFMADDSD, IX86_BUILTIN_VFMADDPS, @@ -21074,6 +21096,20 @@ enum ix86_builtins IX86_BUILTIN_VPCOMFALSEQ, IX86_BUILTIN_VPCOMTRUEQ, + /* LWP instructions. */ + IX86_BUILTIN_LLWPCB16, + IX86_BUILTIN_LLWPCB32, + IX86_BUILTIN_LLWPCB64, + IX86_BUILTIN_SLWPCB16, + IX86_BUILTIN_SLWPCB32, + IX86_BUILTIN_SLWPCB64, + IX86_BUILTIN_LWPVAL16, + IX86_BUILTIN_LWPVAL32, + IX86_BUILTIN_LWPVAL64, + IX86_BUILTIN_LWPINS16, + IX86_BUILTIN_LWPINS32, + IX86_BUILTIN_LWPINS64, + IX86_BUILTIN_MAX }; @@ -21287,7 +21323,13 @@ enum ix86_special_builtin_type VOID_FTYPE_PV8SF_V8SF_V8SF, VOID_FTYPE_PV4DF_V4DF_V4DF, VOID_FTYPE_PV4SF_V4SF_V4SF, - VOID_FTYPE_PV2DF_V2DF_V2DF + VOID_FTYPE_PV2DF_V2DF_V2DF, + VOID_FTYPE_USHORT_UINT_USHORT, + VOID_FTYPE_UINT_UINT_UINT, + VOID_FTYPE_UINT64_UINT_UINT, + UCHAR_FTYPE_USHORT_UINT_USHORT, + UCHAR_FTYPE_UINT_UINT_UINT, + UCHAR_FTYPE_UINT64_UINT_UINT }; /* Builtin types */ @@ -21534,6 +21576,22 @@ static const struct builtin_description bdesc_special_args[] = { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_V4SF }, { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_V4DF }, { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_V8SF }, + + { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcbhi1, "__builtin_ia32_llwpcb16", IX86_BUILTIN_LLWPCB16, UNKNOWN, (int) VOID_FTYPE_VOID }, + { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcbsi1, "__builtin_ia32_llwpcb32", IX86_BUILTIN_LLWPCB32, UNKNOWN, (int) VOID_FTYPE_VOID }, + { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcbdi1, "__builtin_ia32_llwpcb64", IX86_BUILTIN_LLWPCB64, UNKNOWN, (int) VOID_FTYPE_VOID }, + + { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcbhi1, "__builtin_ia32_slwpcb16", IX86_BUILTIN_SLWPCB16, UNKNOWN, (int) VOID_FTYPE_VOID }, + { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcbsi1, "__builtin_ia32_slwpcb32", IX86_BUILTIN_SLWPCB32, UNKNOWN, (int) VOID_FTYPE_VOID }, + { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcbdi1, "__builtin_ia32_slwpcb64", IX86_BUILTIN_SLWPCB64, UNKNOWN, (int) VOID_FTYPE_VOID }, + + { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalhi3, "__builtin_ia32_lwpval16", IX86_BUILTIN_LWPVAL16, UNKNOWN, (int) VOID_FTYPE_USHORT_UINT_USHORT }, + { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalsi3, "__builtin_ia32_lwpval32", IX86_BUILTIN_LWPVAL64, UNKNOWN, (int) VOID_FTYPE_UINT_UINT_UINT }, + { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvaldi3, "__builtin_ia32_lwpval64", IX86_BUILTIN_LWPVAL64, UNKNOWN, (int) VOID_FTYPE_UINT64_UINT_UINT }, + { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinshi3, "__builtin_ia32_lwpins16", IX86_BUILTIN_LWPINS16, UNKNOWN, (int) UCHAR_FTYPE_USHORT_UINT_USHORT }, + { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinssi3, "__builtin_ia32_lwpins32", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT_UINT_UINT }, + { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinsdi3, "__builtin_ia32_lwpins64", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT64_UINT_UINT }, + }; /* Builtins with variable number of arguments. */ @@ -23192,6 +23250,50 @@ ix86_init_mmx_sse_builtins (void) integer_type_node, NULL_TREE); + /* LWP instructions. */ + + tree void_ftype_ushort_unsigned_ushort + = build_function_type_list (void_type_node, + short_unsigned_type_node, + unsigned_type_node, + short_unsigned_type_node, + NULL_TREE); + + tree void_ftype_unsigned_unsigned_unsigned + = build_function_type_list (void_type_node, + unsigned_type_node, + unsigned_type_node, + unsigned_type_node, + NULL_TREE); + + tree void_ftype_uint64_unsigned_unsigned + = build_function_type_list (void_type_node, + long_long_unsigned_type_node, + unsigned_type_node, + unsigned_type_node, + NULL_TREE); + + tree uchar_ftype_ushort_unsigned_ushort + = build_function_type_list (unsigned_char_type_node, + short_unsigned_type_node, + unsigned_type_node, + short_unsigned_type_node, + NULL_TREE); + + tree uchar_ftype_unsigned_unsigned_unsigned + = build_function_type_list (unsigned_char_type_node, + unsigned_type_node, + unsigned_type_node, + unsigned_type_node, + NULL_TREE); + + tree uchar_ftype_uint64_unsigned_unsigned + = build_function_type_list (unsigned_char_type_node, + long_long_unsigned_type_node, + unsigned_type_node, + unsigned_type_node, + NULL_TREE); + tree ftype; /* Add all special builtins with variable number of operands. */ @@ -23305,6 +23407,25 @@ ix86_init_mmx_sse_builtins (void) case VOID_FTYPE_PV2DF_V2DF_V2DF: type = void_ftype_pv2df_v2df_v2df; break; + case VOID_FTYPE_USHORT_UINT_USHORT: + type = void_ftype_ushort_unsigned_ushort; + break; + case VOID_FTYPE_UINT_UINT_UINT: + type = void_ftype_unsigned_unsigned_unsigned; + break; + case VOID_FTYPE_UINT64_UINT_UINT: + type = void_ftype_uint64_unsigned_unsigned; + break; + case UCHAR_FTYPE_USHORT_UINT_USHORT: + type = uchar_ftype_ushort_unsigned_ushort; + break; + case UCHAR_FTYPE_UINT_UINT_UINT: + type = uchar_ftype_unsigned_unsigned_unsigned; + break; + case UCHAR_FTYPE_UINT64_UINT_UINT: + type = uchar_ftype_uint64_unsigned_unsigned; + break; + default: gcc_unreachable (); } @@ -25196,6 +25317,16 @@ ix86_expand_special_args_builtin (const struct builtin_description *d, /* Reserve memory operand for target. */ memory = ARRAY_SIZE (args); break; + case VOID_FTYPE_USHORT_UINT_USHORT: + case VOID_FTYPE_UINT_UINT_UINT: + case VOID_FTYPE_UINT64_UINT_UINT: + case UCHAR_FTYPE_USHORT_UINT_USHORT: + case UCHAR_FTYPE_UINT_UINT_UINT: + case UCHAR_FTYPE_UINT64_UINT_UINT: + nargs = 3; + klass = store; + memory = 0; + break; default: gcc_unreachable (); } diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index 94114f8d711..4bc8ef18500 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -56,6 +56,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see #define TARGET_SSE4A OPTION_ISA_SSE4A #define TARGET_FMA4 OPTION_ISA_FMA4 #define TARGET_XOP OPTION_ISA_XOP +#define TARGET_LWP OPTION_ISA_LWP #define TARGET_ROUND OPTION_ISA_ROUND #define TARGET_ABM OPTION_ISA_ABM #define TARGET_POPCNT OPTION_ISA_POPCNT diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 0e051cdee6b..c011d9b4347 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -204,6 +204,10 @@ (UNSPEC_XOP_TRUEFALSE 152) (UNSPEC_XOP_PERMUTE 153) (UNSPEC_FRCZ 154) + (UNSPEC_LLWP_INTRINSIC 155) + (UNSPEC_SLWP_INTRINSIC 156) + (UNSPECV_LWPVAL_INTRINSIC 157) + (UNSPECV_LWPINS_INTRINSIC 158) ; For AES support (UNSPEC_AESENC 159) @@ -353,7 +357,7 @@ fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp,fisttp,frndint, sselog,sselog1,sseiadd,sseiadd1,sseishft,sseimul, sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,ssecvt1,sseicvt,ssediv,sseins, - ssemuladd,sse4arg, + ssemuladd,sse4arg,lwp, mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft" (const_string "other")) @@ -21838,6 +21842,120 @@ [(set_attr "type" "other") (set_attr "length" "3")]) +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; LWP instructions +;; +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +(define_insn "lwp_llwpcbhi1" + [(unspec [(match_operand:HI 0 "register_operand" "r")] + UNSPEC_LLWP_INTRINSIC)] + "TARGET_LWP" + "llwpcb\t%0" + [(set_attr "type" "lwp") + (set_attr "mode" "HI")]) + +(define_insn "lwp_llwpcbsi1" + [(unspec [(match_operand:SI 0 "register_operand" "r")] + UNSPEC_LLWP_INTRINSIC)] + "TARGET_LWP" + "llwpcb\t%0" + [(set_attr "type" "lwp") + (set_attr "mode" "SI")]) + +(define_insn "lwp_llwpcbdi1" + [(unspec [(match_operand:DI 0 "register_operand" "r")] + UNSPEC_LLWP_INTRINSIC)] + "TARGET_LWP" + "llwpcb\t%0" + [(set_attr "type" "lwp") + (set_attr "mode" "DI")]) + +(define_insn "lwp_slwpcbhi1" + [(unspec [(match_operand:HI 0 "register_operand" "r")] + UNSPEC_SLWP_INTRINSIC)] + "TARGET_LWP" + "slwpcb\t%0" + [(set_attr "type" "lwp") + (set_attr "mode" "HI")]) + +(define_insn "lwp_slwpcbsi1" + [(unspec [(match_operand:SI 0 "register_operand" "r")] + UNSPEC_SLWP_INTRINSIC)] + "TARGET_LWP" + "slwpcb\t%0" + [(set_attr "type" "lwp") + (set_attr "mode" "SI")]) + +(define_insn "lwp_slwpcbdi1" + [(unspec [(match_operand:DI 0 "register_operand" "r")] + UNSPEC_SLWP_INTRINSIC)] + "TARGET_LWP" + "slwpcb\t%0" + [(set_attr "type" "lwp") + (set_attr "mode" "DI")]) + +(define_insn "lwp_lwpvalhi3" + [(unspec_volatile [(match_operand:HI 0 "register_operand" "r") + (match_operand:SI 1 "nonimmediate_operand" "rm") + (match_operand:HI 2 "const_int_operand" "")] + UNSPECV_LWPVAL_INTRINSIC)] + "TARGET_LWP" + "lwpval\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "type" "lwp") + (set_attr "mode" "HI")]) + +(define_insn "lwp_lwpvalsi3" + [(unspec_volatile [(match_operand:SI 0 "register_operand" "r") + (match_operand:SI 1 "nonimmediate_operand" "rm") + (match_operand:SI 2 "const_int_operand" "")] + UNSPECV_LWPVAL_INTRINSIC)] + "TARGET_LWP" + "lwpval\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "type" "lwp") + (set_attr "mode" "SI")]) + +(define_insn "lwp_lwpvaldi3" + [(unspec_volatile [(match_operand:DI 0 "register_operand" "r") + (match_operand:SI 1 "nonimmediate_operand" "rm") + (match_operand:SI 2 "const_int_operand" "")] + UNSPECV_LWPVAL_INTRINSIC)] + "TARGET_LWP" + "lwpval\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "type" "lwp") + (set_attr "mode" "DI")]) + +(define_insn "lwp_lwpinshi3" + [(unspec_volatile [(match_operand:HI 0 "register_operand" "r") + (match_operand:SI 1 "nonimmediate_operand" "rm") + (match_operand:HI 2 "const_int_operand" "")] + UNSPECV_LWPINS_INTRINSIC)] + "TARGET_LWP" + "lwpins\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "type" "lwp") + (set_attr "mode" "HI")]) + +(define_insn "lwp_lwpinssi3" + [(unspec_volatile [(match_operand:SI 0 "register_operand" "r") + (match_operand:SI 1 "nonimmediate_operand" "rm") + (match_operand:SI 2 "const_int_operand" "")] + UNSPECV_LWPINS_INTRINSIC)] + "TARGET_LWP" + "lwpins\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "type" "lwp") + (set_attr "mode" "SI")]) + +(define_insn "lwp_lwpinsdi3" + [(unspec_volatile [(match_operand:DI 0 "register_operand" "r") + (match_operand:SI 1 "nonimmediate_operand" "rm") + (match_operand:SI 2 "const_int_operand" "")] + UNSPECV_LWPINS_INTRINSIC)] + "TARGET_LWP" + "lwpins\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "type" "lwp") + (set_attr "mode" "DI")]) + (include "mmx.md") (include "sse.md") (include "sync.md") diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt index b63b84e7bef..dd47b7d1dc5 100644 --- a/gcc/config/i386/i386.opt +++ b/gcc/config/i386/i386.opt @@ -318,6 +318,10 @@ mxop Target Report Mask(ISA_XOP) Var(ix86_isa_flags) VarExists Save Support XOP built-in functions and code generation +mlwp +Target Report Mask(ISA_LWP) Var(ix86_isa_flags) VarExists Save +Support LWP built-in functions and code generation + mabm Target Report Mask(ISA_ABM) Var(ix86_isa_flags) VarExists Save Support code generation of Advanced Bit Manipulation (ABM) instructions. diff --git a/gcc/config/i386/lwpintrin.h b/gcc/config/i386/lwpintrin.h new file mode 100644 index 00000000000..e5137ec24f4 --- /dev/null +++ b/gcc/config/i386/lwpintrin.h @@ -0,0 +1,109 @@ +/* Copyright (C) 2007, 2008, 2009 Free Software Foundation, Inc. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GCC is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + . */ + +#ifndef _X86INTRIN_H_INCLUDED +# error "Never use directly; include instead." +#endif + +#ifndef _LWPINTRIN_H_INCLUDED +#define _LWPINTRIN_H_INCLUDED + +#ifndef __LWP__ +# error "LWP instruction set not enabled" +#else + +extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__llwpcb16 (void *pcbAddress) +{ + __builtin_ia32_llwpcb16 (pcbAddress); +} + +extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__llwpcb32 (void *pcbAddress) +{ + __builtin_ia32_llwpcb32 (pcbAddress); +} + +extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__llwpcb64 (void *pcbAddress) +{ + __builtin_ia32_llwpcb64 (pcbAddress); +} + +extern __inline void * __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__slwpcb16 (void) +{ + return __builtin_ia32_slwpcb16 (); +} + +extern __inline void * __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__slwpcb32 (void) +{ + return __builtin_ia32_slwpcb32 (); +} + +extern __inline void * __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__slwpcb64 (void) +{ + return __builtin_ia32_slwpcb64 (); +} + +extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__lwpval16 (unsigned short data2, unsigned int data1, unsigned short flags) +{ + __builtin_ia32_lwpval16 (data2, data1, flags); +} +/* +extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__lwpval32 (unsigned int data2, unsigned int data1, unsigned int flags) +{ + __builtin_ia32_lwpval32 (data2, data1, flags); +} + +extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__lwpval64 (unsigned __int64 data2, unsigned int data1, unsigned int flags) +{ + __builtin_ia32_lwpval64 (data2, data1, flags); +} + +extern __inline unsigned char __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__lwpins16 (unsigned short data2, unsigned int data1, unsigned short flags) +{ + return __builtin_ia32_lwpins16 (data2, data1, flags); +} + +extern __inline unsigned char __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__lwpins32 (unsigned int data2, unsigned int data1, unsigned int flags) +{ + return __builtin_ia32_lwpins32 (data2, data1, flags); +} + +extern __inline unsigned char __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +__lwpins64 (unsigned __int64 data2, unsigned int data1, unsigned int flags) +{ + return __builtin_ia32_lwpins64 (data2, data1, flags); +} +*/ +#endif /* __LWP__ */ + +#endif /* _LWPINTRIN_H_INCLUDED */ diff --git a/gcc/config/i386/x86intrin.h b/gcc/config/i386/x86intrin.h index 522415fb30a..465166aba6f 100644 --- a/gcc/config/i386/x86intrin.h +++ b/gcc/config/i386/x86intrin.h @@ -62,6 +62,10 @@ #include #endif +#ifdef __LWP__ +#include +#endif + #if defined (__AES__) || defined (__PCLMUL__) #include #endif diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 19ab465f980..e09c9ee6685 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -3212,6 +3212,11 @@ Enable/disable the generation of the FMA4 instructions. @cindex @code{target("xop")} attribute Enable/disable the generation of the XOP instructions. +@item lwp +@itemx no-lwp +@cindex @code{target("lwp")} attribute +Enable/disable the generation of the LWP instructions. + @item ssse3 @itemx no-ssse3 @cindex @code{target("ssse3")} attribute @@ -9101,6 +9106,23 @@ v8sf __builtin_ia32_fmsubaddps256 (v8sf, v8sf, v8sf) @end smallexample +The following built-in functions are available when @option{-mlwp} is used. + +@smallexample +void __builtin_ia32_llwpcb16 (void *); +void __builtin_ia32_llwpcb32 (void *); +void __builtin_ia32_llwpcb64 (void *); +void * __builtin_ia32_llwpcb16 (void); +void * __builtin_ia32_llwpcb32 (void); +void * __builtin_ia32_llwpcb64 (void); +void __builtin_ia32_lwpval16 (unsigned short, unsigned int, unsigned short) +void __builtin_ia32_lwpval32 (unsigned int, unsigned int, unsigned int) +void __builtin_ia32_lwpval64 (unsigned __int64, unsigned int, unsigned int) +unsigned char __builtin_ia32_lwpins16 (unsigned short, unsigned int, unsigned short) +unsigned char __builtin_ia32_lwpins32 (unsigned int, unsigned int, unsigned int) +unsigned char __builtin_ia32_lwpins64 (unsigned __int64, unsigned int, unsigned int) +@end smallexample + The following built-in functions are available when @option{-m3dnow} is used. All of them generate the machine instruction that is part of the name. diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 0a913e0ebc8..0a8911b6a56 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -594,7 +594,7 @@ Objective-C and Objective-C++ Dialects}. -mcld -mcx16 -msahf -mmovbe -mcrc32 -mrecip @gol -mmmx -msse -msse2 -msse3 -mssse3 -msse4.1 -msse4.2 -msse4 -mavx @gol -maes -mpclmul @gol --msse4a -m3dnow -mpopcnt -mabm -mfma4 -mxop @gol +-msse4a -m3dnow -mpopcnt -mabm -mfma4 -mxop -mlwp @gol -mthreads -mno-align-stringops -minline-all-stringops @gol -minline-stringops-dynamically -mstringop-strategy=@var{alg} @gol -mpush-args -maccumulate-outgoing-args -m128bit-long-double @gol @@ -12007,6 +12007,8 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}. @itemx -mno-fma4 @itemx -mxop @itemx -mno-xop +@itemx -mlwp +@itemx -mno-lwp @itemx -m3dnow @itemx -mno-3dnow @itemx -mpopcnt @@ -12021,7 +12023,7 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}. @opindex mno-3dnow These switches enable or disable the use of instructions in the MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, AVX, AES, PCLMUL, SSE4A, FMA4, XOP, -ABM or 3DNow!@: extended instruction sets. +LWP, ABM or 3DNow!@: extended instruction sets. These extensions are also available as built-in functions: see @ref{X86 Built-in Functions}, for details of the functions enabled and disabled by these switches. -- 2.11.0