From: dj Date: Mon, 29 Jun 2009 23:21:49 +0000 (+0000) Subject: * doc/extend.texi: Add MeP attributes and pragmas. X-Git-Url: http://git.sourceforge.jp/view?p=pf3gnuchains%2Fgcc-fork.git;a=commitdiff_plain;h=7c3116fbffbdcf18c0c4ad1ce8dbc78f73645dc7 * doc/extend.texi: Add MeP attributes and pragmas. * doc/invoke.text: Add MeP Options. * doc/contrib.texi: Add MeP contribution. * doc/md.texi: Add MeP constraints. * doc/install.texi: Add MeP target. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@149068 138bc75d-0d04-0410-961f-82ee72b054a4 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 97b6fba59f4..60d689ed143 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2009-06-29 DJ Delorie + + * doc/extend.texi: Add MeP attributes and pragmas. + * doc/invoke.text: Add MeP Options. + * doc/contrib.texi: Add MeP contribution. + * doc/md.texi: Add MeP constraints. + * doc/install.texi: Add MeP target. + 2009-06-30 Anatoly Sokolov * target.h (struct gcc_target): Add frame_pointer_required field. diff --git a/gcc/doc/contrib.texi b/gcc/doc/contrib.texi index 0499f96b131..d2d1673cc3b 100644 --- a/gcc/doc/contrib.texi +++ b/gcc/doc/contrib.texi @@ -215,7 +215,7 @@ Mo DeJong for GCJ and libgcj bug fixes. @item DJ Delorie for the DJGPP port, build and libiberty maintenance, -various bug fixes, and the M32C port. +various bug fixes, and the M32C and MeP ports. @item Arnaud Desitter for helping to debug GNU Fortran. diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 2a9fffa2d06..06bacec765d 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -2137,6 +2137,12 @@ present. The @code{deprecated} attribute can also be used for variables and types (@pxref{Variable Attributes}, @pxref{Type Attributes}.) +@item disinterrupt +@cindex @code{disinterrupt} attribute +On MeP targets, this attribute causes the compiler to emit +instructions to disable interrupts for the duration of the given +function. + @item dllexport @cindex @code{__declspec(dllexport)} On Microsoft Windows targets and Symbian OS targets the @@ -2263,6 +2269,10 @@ At the end of a function, it will jump to a board-specific routine instead of using @code{rts}. The board-specific return routine simulates the @code{rtc}. +On MeP targets this causes the compiler to use a calling convention +which assumes the called function is too far away for the built-in +addressing modes. + @item fastcall @cindex functions that pop the argument stack on the 386 On the Intel 386, the @code{fastcall} attribute causes the compiler to @@ -2450,7 +2460,7 @@ This attribute is ignored for R8C target. @item interrupt @cindex interrupt handler functions -Use this attribute on the ARM, AVR, CRX, M32C, M32R/D, m68k, MIPS +Use this attribute on the ARM, AVR, CRX, M32C, M32R/D, m68k, MeP, MIPS and Xstormy16 ports to indicate that the specified function is an interrupt handler. The compiler will generate function entry and exit sequences suitable for use in an interrupt handler when this attribute @@ -2669,6 +2679,10 @@ use the normal calling convention based on @code{jsr} and @code{rts}. This attribute can be used to cancel the effect of the @option{-mlong-calls} option. +On MeP targets this attribute causes the compiler to assume the called +function is close enough to use the normal calling convention, +overriding the @code{-mtf} command line option. + @item nesting @cindex Allow nesting in an interrupt handler on the Blackfin processor. Use this attribute together with @code{interrupt_handler}, @@ -3323,6 +3337,13 @@ visibility of their template. If both the template and enclosing class have explicit visibility, the visibility from the template is used. +@item vliw +@cindex @code{vliw} attribute +On MeP, the @code{vliw} attribute tells the compiler to emit +instructions in VLIW mode instead of core mode. Note that this +attribute is not allowed unless a VLIW coprocessor has been configured +and enabled through command line options. + @item warn_unused_result @cindex @code{warn_unused_result} attribute The @code{warn_unused_result} attribute causes a warning to be emitted @@ -4150,6 +4171,64 @@ Medium and large model objects may live anywhere in the 32-bit address space addresses). @end table +@anchor{MeP Variable Attributes} +@subsection MeP Variable Attributes + +The MeP target has a number of addressing modes and busses. The +@code{near} space spans the standard memory space's first 16 megabytes +(24 bits). The @code{far} space spans the entire 32-bit memory space. +The @code{based} space is a 128 byte region in the memory space which +is addressed relative to the @code{$tp} register. The @code{tiny} +space is a 65536 byte region relative to the @code{$gp} register. In +addition to these memory regions, the MeP target has a separate 16-bit +control bus which is specified with @code{cb} attributes. + +@table @code + +@item based +Any variable with the @code{based} attribute will be assigned to the +@code{.based} section, and will be accessed with relative to the +@code{$tp} register. + +@item tiny +Likewise, the @code{tiny} attribute assigned variables to the +@code{.tiny} section, relative to the @code{$gp} register. + +@item near +Variables with the @code{near} attribute are assumed to have addresses +that fit in a 24-bit addressing mode. This is the default for large +variables (@code{-mtiny=4} is the default) but this attribute can +override @code{-mtiny=} for small variables, or override @code{-ml}. + +@item far +Variables with the @code{far} attribute are addressed using a full +32-bit address. Since this covers the entire memory space, this +allows modules to make no assumptions about where variables might be +stored. + +@item io +@item io (@var{addr}) +Variables with the @code{io} attribute are used to address +memory-mapped peripherals. If an address is specified, the variable +is assigned that address, else it is not assigned an address (it is +assumed some other module will assign an address). Example: + +@example +int timer_count __attribute__((io(0x123))); +@end example + +@item cb +@item cb (@var{addr}) +Variables with the @code{cb} attribute are used to access the control +bus, using special instructions. @code{addr} indicates the control bus +address. Example: + +@example +int cpu_clock __attribute__((cb(0x123))); +@end example + +@end table + @anchor{i386 Variable Attributes} @subsection i386 Variable Attributes @@ -4652,6 +4731,14 @@ virtual table for @code{C} is not exported. (You can use @code{__attribute__} instead of @code{__declspec} if you prefer, but most Symbian OS code uses @code{__declspec}.) +@anchor{MeP Type Attributes} +@subsection MeP Type Attributes + +Many of the MeP variable attributes may be applied to types as well. +Specifically, the @code{based}, @code{tiny}, @code{near}, and +@code{far} attributes may be applied to either. The @code{io} and +@code{cb} attributes may not be applied to types. + @anchor{i386 Type Attributes} @subsection i386 Type Attributes @@ -11703,6 +11790,7 @@ for further explanation. @menu * ARM Pragmas:: * M32C Pragmas:: +* MeP Pragmas:: * RS/6000 and PowerPC Pragmas:: * Darwin Pragmas:: * Solaris Pragmas:: @@ -11753,6 +11841,78 @@ as it may allow you to reduce the number of memregs used. @end table +@node MeP Pragmas +@subsection MeP Pragmas + +@table @code + +@item custom io_volatile (on|off) +@cindex pragma, custom io_volatile +Overrides the command line option @code{-mio-volatile} for the current +file. Note that for compatibility with future GCC releases, this +option should only be used once before any @code{io} variables in each +file. + +@item GCC coprocessor available @var{registers} +@cindex pragma, coprocessor available +Specifies which coprocessor registers are available to the register +allocator. @var{registers} may be a single register, register range +separated by ellipses, or comma-separated list of those. Example: + +@example +#pragma GCC coprocessor available $c0...$c10, $c28 +@end example + +@item GCC coprocessor call_saved @var{registers} +@cindex pragma, coprocessor call_saved +Specifies which coprocessor registers are to be saved and restored by +any function using them. @var{registers} may be a single register, +register range separated by ellipses, or comma-separated list of +those. Example: + +@example +#pragma GCC coprocessor call_saved $c4...$c6, $c31 +@end example + +@item GCC coprocessor subclass '(A|B|C|D)' = @var{registers} +@cindex pragma, coprocessor subclass +Creates and defines a register class. These register classes can be +used by inline @code{asm} constructs. @var{registers} may be a single +register, register range separated by ellipses, or comma-separated +list of those. Example: + +@example +#pragma GCC coprocessor subclass 'B' = $c2, $c4, $c6 + +asm ("cpfoo %0" : "=B" (x)); +@end example + +@item GCC disinterrupt @var{name} , @var{name} @dots{} +@cindex pragma, disinterrupt +For the named functions, the compiler adds code to disable interrupts +for the duration of those functions. Any functions so named, which +are not encountered in the source, cause a warning that the pragma was +not used. Examples: + +@example +#pragma disinterrupt foo +#pragma disinterrupt bar, grill +int foo () { @dots{} } +@end example + +@item GCC call @var{name} , @var{name} @dots{} +@cindex pragma, call +For the named functions, the compiler always uses a register-indirect +call model when calling the named functions. Examples: + +@example +extern int foo (); +#pragma call foo +@end example + +@end table + + @node RS/6000 and PowerPC Pragmas @subsection RS/6000 and PowerPC Pragmas diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi index 4f7e433c614..908ac8d3223 100644 --- a/gcc/doc/install.texi +++ b/gcc/doc/install.texi @@ -2785,6 +2785,8 @@ information are. @item @uref{#m68k-uclinux,,m68k-uclinux} @item +@uref{#mep-x-elf,,mep-*-elf} +@item @uref{#mips-x-x,,mips-*-*} @item @uref{#mips-sgi-irix5,,mips-sgi-irix5} @@ -3624,6 +3626,14 @@ both of which were ABI changes. However, you can still use the original ABI by configuring for @samp{m68k-uclinuxoldabi} or @samp{m68k-@var{vendor}-uclinuxoldabi}. + +@html +
+@end html +@heading @anchor{mep-x-elf}mep-*-elf +Toshiba Media Processor. +This configuration is intended for embedded systems. + @html
@end html diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index ada9966d25e..34bc48c87df 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -656,6 +656,13 @@ Objective-C and Objective-C++ Dialects}. -mno-callgraph-data -mslow-bytes -mno-slow-bytes -mno-lsim @gol -mlittle-endian -mbig-endian -m210 -m340 -mstack-increment} +@emph{MeP Options} +@gccoptlist{-mabsdiff -mall-opts -maverage -mbased=@var{n} -mbitops @gol +-mc=@var{n} -mclip -mconfig=@var{name} -mcop -mcop32 -mcop64 -mivc2 @gol +-mdc -mdiv -meb -mel -mio-volatile -ml -mleadz -mm -mminmax @gol +-mmult -mno-opts -mrepeat -ms -msatur -msdram -msim -msimnovec -mtf @gol +-mtiny=@var{n}} + @emph{MIPS Options} @gccoptlist{-EL -EB -march=@var{arch} -mtune=@var{arch} @gol -mips1 -mips2 -mips3 -mips4 -mips32 -mips32r2 @gol @@ -9069,6 +9076,7 @@ platform. * M680x0 Options:: * M68hc1x Options:: * MCore Options:: +* MeP Options:: * MIPS Options:: * MMIX Options:: * MN10300 Options:: @@ -12754,6 +12762,170 @@ value is 0x1000. @end table +@node MeP Options +@subsection MeP Options +@cindex MeP options + +@table @gcctabopt + +@item -mabsdiff +@opindex mabsdiff +Enables the @code{abs} instruction, which is the absolute difference +between two registers. + +@item -mall-opts +@opindex mall-opts +Enables all the optional instructions - average, multiply, divide, bit +operations, leading zero, absolute difference, min/max, clip, and +saturation. + + +@item -maverage +@opindex maverage +Enables the @code{ave} instruction, which computes the average of two +registers. + +@item -mbased=@var{n} +@opindex mbased= +Variables of size @var{n} bytes or smaller will be placed in the +@code{.based} section by default. Based variables use the @code{$tp} +register as a base register, and there is a 128 byte limit to the +@code{.based} section. + +@item -mbitops +@opindex mbitops +Enables the bit operation instructions - bit test (@code{btstm}), set +(@code{bsetm}), clear (@code{bclrm}), invert (@code{bnotm}), and +test-and-set (@code{tas}). + +@item -mc=@var{name} +@opindex mc= +Selects which section constant data will be placed in. @var{name} may +be @code{tiny}, @code{near}, or @code{far}. + +@item -mclip +@opindex mclip +Enables the @code{clip} instruction. Note that @code{-mclip} is not +useful unless you also provide @code{-mminmax}. + +@item -mconfig=@var{name} +@opindex mconfig= +Selects one of the build-in core configurations. Each MeP chip has +one or more modules in it; each module has a core CPU and a variety of +coprocessors, optional instructions, and peripherals. The +@code{MeP-Integrator} tool, not part of GCC, provides these +configurations through this option; using this option is the same as +using all the corresponding command line options. The default +configuration is @code{default}. + +@item -mcop +@opindex mcop +Enables the coprocessor instructions. By default, this is a 32-bit +coprocessor. Note that the coprocessor is normally enabled via the +@code{-mconfig=} option. + +@item -mcop32 +@opindex mcop32 +Enables the 32-bit coprocessor's instructions. + +@item -mcop64 +@opindex mcop64 +Enables the 64-bit coprocessor's instructions. + +@item -mivc2 +@opindex mivc2 +Enables IVC2 scheduling. IVC2 is a 64-bit VLIW coprocessor. + +@item -mdc +@opindex mdc +Causes constant variables to be placed in the @code{.near} section. + +@item -mdiv +@opindex mdiv +Enables the @code{div} and @code{divu} instructions. + +@item -meb +@opindex meb +Generate big-endian code. + +@item -mel +@opindex mel +Generate little-endian code. + +@item -mio-volatile +@opindex mio-volatile +Tells the compiler that any variable marked with the @code{io} +attribute is to be considered volatile. + +@item -ml +@opindex ml +Causes variables to be assigned to the @code{.far} section by default. + +@item -mleadz +@opindex mleadz +Enables the @code{leadz} (leading zero) instruction. + +@item -mm +@opindex mm +Causes variables to be assigned to the @code{.near} section by default. + +@item -mminmax +@opindex mminmax +Enables the @code{min} and @code{max} instructions. + +@item -mmult +@opindex mmult +Enables the multiplication and multiply-accumulate instructions. + +@item -mno-opts +@opindex mno-opts +Disables all the optional instructions enabled by @code{-mall-opts}. + +@item -mrepeat +@opindex mrepeat +Enables the @code{repeat} and @code{erepeat} instructions, used for +low-overhead looping. + +@item -ms +@opindex ms +Causes all variables to default to the @code{.tiny} section. Note +that there is a 65536 byte limit to this section. Accesses to these +variables use the @code{%gp} base register. + +@item -msatur +@opindex msatur +Enables the saturation instructions. Note that the compiler does not +currently generate these itself, but this option is included for +compatibility with other tools, like @code{as}. + +@item -msdram +@opindex msdram +Link the SDRAM-based runtime instead of the default ROM-based runtime. + +@item -msim +@opindex msim +Link the simulator runtime libraries. + +@item -msimnovec +@opindex msimnovec +Link the simulator runtime libraries, excluding built-in support +for reset and exception vectors and tables. + +@item -mtf +@opindex mtf +Causes all functions to default to the @code{.far} section. Without +this option, functions default to the @code{.near} section. + +@item -mtiny=@var{n} +@opindex mtiny= +Variables that are @var{n} bytes or smaller will be allocated to the +@code{.tiny} section. These variables use the @code{$gp} base +register. The default for this option is 4, but note that there's a +65536 byte limit to the @code{.tiny} section. + +@end table + + @node MIPS Options @subsection MIPS Options @cindex MIPS options diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 5c6790009ec..f4ca2b032ff 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -2520,6 +2520,109 @@ Memory addressed using the small base register ($sb). $r1h @end table +@item MeP---@file{config/mep/constraints.md} +@table @code + +@item a +The $sp register. + +@item b +The $tp register. + +@item c +Any control register. + +@item d +Either the $hi or the $lo register. + +@item em +Coprocessor registers that can be directly loaded ($c0-$c15). + +@item ex +Coprocessor registers that can be moved to each other. + +@item er +Coprocessor registers that can be moved to core registers. + +@item h +The $hi register. + +@item j +The $rpc register. + +@item l +The $lo register. + +@item t +Registers which can be used in $tp-relative addressing. + +@item v +The $gp register. + +@item x +The coprocessor registers. + +@item y +The coprocessor control registers. + +@item z +The $0 register. + +@item A +User-defined register set A. + +@item B +User-defined register set B. + +@item C +User-defined register set C. + +@item D +User-defined register set D. + +@item I +Offsets for $gp-rel addressing. + +@item J +Constants that can be used directly with boolean insns. + +@item K +Constants that can be moved directly to registers. + +@item L +Small constants that can be added to registers. + +@item M +Long shift counts. + +@item N +Small constants that can be compared to registers. + +@item O +Constants that can be loaded into the top half of registers. + +@item S +Signed 8-bit immediates. + +@item T +Symbols encoded for $tp-rel or $gp-rel addressing. + +@item U +Non-constant addresses for loading/saving coprocessor registers. + +@item W +The top half of a symbol's value. + +@item Y +A register indirect address without offset. + +@item Z +Symbolic references to the control bus. + + + +@end table + @item MIPS---@file{config/mips/constraints.md} @table @code @item d