From: hjl <hjl@138bc75d-0d04-0410-961f-82ee72b054a4>
Date: Thu, 6 Mar 2008 05:11:52 +0000 (+0000)
Subject: 2008-03-05  H.J. Lu  <hongjiu.lu@intel.com>
X-Git-Url: http://git.sourceforge.jp/view?p=pf3gnuchains%2Fgcc-fork.git;a=commitdiff_plain;h=4a8f8ebf336054d2e1cbad4cfdf41243bbb53679

2008-03-05  H.J. Lu  <hongjiu.lu@intel.com>

	* config/i386/i386-modes.def: Use 4 byte alignment on DI for
	32bit host.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@132966 138bc75d-0d04-0410-961f-82ee72b054a4
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index a103de6a70e..110a6dc58c1 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2008-03-05  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/i386/i386-modes.def: Use 4 byte alignment on DI for
+	32bit host.
+
 2008-03-05  Ian Lance Taylor  <iant@google.com>
 
 	* alias.h (alias_set_type): Change from HOST_WIDE_INT to int.
diff --git a/gcc/config/i386/i386-modes.def b/gcc/config/i386/i386-modes.def
index 105d3872b79..f2f2b4f2acb 100644
--- a/gcc/config/i386/i386-modes.def
+++ b/gcc/config/i386/i386-modes.def
@@ -17,6 +17,10 @@ You should have received a copy of the GNU General Public License
 along with GCC; see the file COPYING3.  If not see
 <http://www.gnu.org/licenses/>.  */
 
+/* In 32bit, DI mode uses 32bit registers.  Only 4 byte alignment
+   is needed.  */
+ADJUST_ALIGNMENT (DI, (TARGET_64BIT || TARGET_ALIGN_DOUBLE) ? 8 : 4);
+
 /* The x86_64 ABI specifies both XF and TF modes.
    XFmode is __float80 is IEEE extended; TFmode is __float128
    is IEEE quad.  */