From: uros Date: Mon, 19 Sep 2011 17:13:18 +0000 (+0000) Subject: * config/i386/i386.md (maxmin): New code iterator. X-Git-Url: http://git.sourceforge.jp/view?p=pf3gnuchains%2Fgcc-fork.git;a=commitdiff_plain;h=2af8cce69529f81e44e5e0b09cd705e21337ceb8 * config/i386/i386.md (maxmin): New code iterator. * config/i386/sse.md (3): Macroize expander from 3 and 3 using maxmin code iterator. (*avx2_3): Macroize isn from *avx2_3 and *avx2_3 using maxmin code iterator. (3): Merge with v8hi3. (3): Merge with umaxv4si3 and v16qi3. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@178981 138bc75d-0d04-0410-961f-82ee72b054a4 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 347d74e2086..723bb32fb24 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,16 @@ +2011-09-19 Uros Bizjak + + * config/i386/i386.md (maxmin): New code iterator. + * config/i386/sse.md (3): Macroize expander + from 3 and 3 using maxmin + code iterator. + (*avx2_3): Macroize isn from + *avx2_3 and *avx2_3 using + maxmin code iterator. + (3): Merge with v8hi3. + (3): Merge with umaxv4si3 and + v16qi3. + 2011-09-19 Alan Modra Michael Meissner @@ -36,7 +49,6 @@ 2011-09-19 Paul Brook - gcc/ * config/arm/predicates.md (shift_amount_operand): Check constant shift count is in range. (const_shift_operand): Remove. @@ -114,12 +126,10 @@ * config/i386/i386.c (ix86_build_const_vector): Handle V8SImode and V4DImode. (ix86_build_signbit_mask): Likewise. - (ix86_expand_int_vcond): Likewise. Handle V16HImode and - V32QImode. + (ix86_expand_int_vcond): Likewise. Handle V16HImode and V32QImode. (bdesc_args): Use CODE_FOR_{s,u}m{ax,in}v{32q,16h,8s}i3 instead of CODE_FOR_avx2_{s,u}m{ax,in}v{32q,16h,8s}i3. - * config/i386/sse.md (avx2_3 umaxmin expand): Rename - to... + * config/i386/sse.md (avx2_3 umaxmin expand): Rename to... (3) ... this. (avx2_3 smaxmin expand): Rename to... (3) ... this. @@ -190,8 +200,7 @@ * Makefile.in (SYSROOT_CFLAGS_FOR_TARGET): Define from @SYSROOT_CFLAGS_FOR_TARGET@. - * configure.ac (SYSROOT_CFLAGS_FOR_TARGET): Set from - build-sysroot. + * configure.ac (SYSROOT_CFLAGS_FOR_TARGET): Set from build-sysroot. * configure: Regenerate. (site.exp): Add definition of TEST_ALWAYS_FLAGS. Remove setting of GCC_UNDER_TEST. diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 017ab09acbf..0f6de893832 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -751,6 +751,9 @@ (define_code_attr comm [(plus "%") (ss_plus "%") (us_plus "%") (minus "") (ss_minus "") (us_minus "")]) +;; Mapping of max and min +(define_code_iterator maxmin [smax smin umax umin]) + ;; Mapping of signed max and min (define_code_iterator smaxmin [smax smin]) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 6b8df03b053..5a1b597d5bd 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -5831,9 +5831,10 @@ (set_attr "prefix" "orig,vex") (set_attr "mode" "")]) + (define_expand "3" [(set (match_operand:VI124_256 0 "register_operand" "") - (umaxmin:VI124_256 + (maxmin:VI124_256 (match_operand:VI124_256 1 "nonimmediate_operand" "") (match_operand:VI124_256 2 "nonimmediate_operand" "")))] "TARGET_AVX2" @@ -5841,7 +5842,7 @@ (define_insn "*avx2_3" [(set (match_operand:VI124_256 0 "register_operand" "=x") - (umaxmin:VI124_256 + (maxmin:VI124_256 (match_operand:VI124_256 1 "nonimmediate_operand" "%x") (match_operand:VI124_256 2 "nonimmediate_operand" "xm")))] "TARGET_AVX2 && ix86_binary_operator_ok (, mode, operands)" @@ -5852,24 +5853,74 @@ (set_attr "mode" "OI")]) (define_expand "3" - [(set (match_operand:VI124_256 0 "register_operand" "") - (smaxmin:VI124_256 - (match_operand:VI124_256 1 "nonimmediate_operand" "") - (match_operand:VI124_256 2 "nonimmediate_operand" "")))] - "TARGET_AVX2" - "ix86_fixup_binary_operands_no_copy (, mode, operands);") + [(set (match_operand:VI8_AVX2 0 "register_operand" "") + (maxmin:VI8_AVX2 (match_operand:VI8_AVX2 1 "register_operand" "") + (match_operand:VI8_AVX2 2 "register_operand" "")))] + "TARGET_SSE4_2" +{ + enum rtx_code code; + rtx xops[6]; + bool ok; -(define_insn "*avx2_3" - [(set (match_operand:VI124_256 0 "register_operand" "=x") - (smaxmin:VI124_256 - (match_operand:VI124_256 1 "nonimmediate_operand" "%x") - (match_operand:VI124_256 2 "nonimmediate_operand" "xm")))] - "TARGET_AVX2 && ix86_binary_operator_ok (, mode, operands)" - "vp\t{%2, %1, %0|%0, %1, %2}" - [(set_attr "type" "sseiadd") - (set_attr "prefix_extra" "1") - (set_attr "prefix" "vex") - (set_attr "mode" "OI")]) + xops[0] = operands[0]; + + if ( == SMAX || == UMAX) + { + xops[1] = operands[1]; + xops[2] = operands[2]; + } + else + { + xops[1] = operands[2]; + xops[2] = operands[1]; + } + + code = ( == UMAX || == UMIN) ? GTU : GT; + + xops[3] = gen_rtx_fmt_ee (code, VOIDmode, operands[1], operands[2]); + xops[4] = operands[1]; + xops[5] = operands[2]; + + ok = ix86_expand_int_vcond (xops); + gcc_assert (ok); + DONE; +}) + +(define_expand "3" + [(set (match_operand:VI124_128 0 "register_operand" "") + (smaxmin:VI124_128 (match_operand:VI124_128 1 "register_operand" "") + (match_operand:VI124_128 2 "register_operand" "")))] + "TARGET_SSE2" +{ + if (TARGET_SSE4_1 || mode == V8HImode) + ix86_fixup_binary_operands_no_copy (, mode, operands); + else + { + rtx xops[6]; + bool ok; + + xops[0] = operands[0]; + + if ( == SMAX) + { + xops[1] = operands[1]; + xops[2] = operands[2]; + } + else + { + xops[1] = operands[2]; + xops[2] = operands[1]; + } + + xops[3] = gen_rtx_GT (VOIDmode, operands[1], operands[2]); + xops[4] = operands[1]; + xops[5] = operands[2]; + + ok = ix86_expand_int_vcond (xops); + gcc_assert (ok); + DONE; + } +}) (define_insn "*sse4_1_3" [(set (match_operand:VI14_128 0 "register_operand" "=x,x") @@ -5903,58 +5954,50 @@ (set_attr "mode" "TI")]) (define_expand "3" - [(set (match_operand:VI14_128 0 "register_operand" "") - (smaxmin:VI14_128 (match_operand:VI14_128 1 "register_operand" "") - (match_operand:VI14_128 2 "register_operand" "")))] + [(set (match_operand:VI124_128 0 "register_operand" "") + (umaxmin:VI124_128 (match_operand:VI124_128 1 "register_operand" "") + (match_operand:VI124_128 2 "register_operand" "")))] "TARGET_SSE2" { - if (TARGET_SSE4_1) + if (TARGET_SSE4_1 || mode == V16QImode) ix86_fixup_binary_operands_no_copy (, mode, operands); + else if ( == UMAX && mode == V8HImode) + { + rtx op0 = operands[0], op2 = operands[2], op3 = op0; + if (rtx_equal_p (op3, op2)) + op3 = gen_reg_rtx (V8HImode); + emit_insn (gen_sse2_ussubv8hi3 (op3, operands[1], op2)); + emit_insn (gen_addv8hi3 (op0, op3, op2)); + DONE; + } else { rtx xops[6]; bool ok; xops[0] = operands[0]; - xops[1] = operands[ == SMAX ? 1 : 2]; - xops[2] = operands[ == SMAX ? 2 : 1]; - xops[3] = gen_rtx_GT (VOIDmode, operands[1], operands[2]); + + if ( == UMAX) + { + xops[1] = operands[1]; + xops[2] = operands[2]; + } + else + { + xops[1] = operands[2]; + xops[2] = operands[1]; + } + + xops[3] = gen_rtx_GTU (VOIDmode, operands[1], operands[2]); xops[4] = operands[1]; xops[5] = operands[2]; + ok = ix86_expand_int_vcond (xops); gcc_assert (ok); DONE; } }) -(define_expand "v8hi3" - [(set (match_operand:V8HI 0 "register_operand" "") - (smaxmin:V8HI - (match_operand:V8HI 1 "nonimmediate_operand" "") - (match_operand:V8HI 2 "nonimmediate_operand" "")))] - "TARGET_SSE2" - "ix86_fixup_binary_operands_no_copy (, V8HImode, operands);") - -(define_expand "3" - [(set (match_operand:VI8_AVX2 0 "register_operand" "") - (smaxmin:VI8_AVX2 (match_operand:VI8_AVX2 1 "register_operand" "") - (match_operand:VI8_AVX2 2 "register_operand" "")))] - "TARGET_SSE4_2" -{ - rtx xops[6]; - bool ok; - - xops[0] = operands[0]; - xops[1] = operands[ == SMAX ? 1 : 2]; - xops[2] = operands[ == SMAX ? 2 : 1]; - xops[3] = gen_rtx_GT (VOIDmode, operands[1], operands[2]); - xops[4] = operands[1]; - xops[5] = operands[2]; - ok = ix86_expand_int_vcond (xops); - gcc_assert (ok); - DONE; -}) - (define_insn "*sse4_1_3" [(set (match_operand:VI24_128 0 "register_operand" "=x,x") (umaxmin:VI24_128 @@ -5986,103 +6029,6 @@ (set_attr "prefix" "orig,vex") (set_attr "mode" "TI")]) -(define_expand "v16qi3" - [(set (match_operand:V16QI 0 "register_operand" "") - (umaxmin:V16QI - (match_operand:V16QI 1 "nonimmediate_operand" "") - (match_operand:V16QI 2 "nonimmediate_operand" "")))] - "TARGET_SSE2" - "ix86_fixup_binary_operands_no_copy (, V16QImode, operands);") - -(define_expand "umaxv8hi3" - [(set (match_operand:V8HI 0 "register_operand" "") - (umax:V8HI (match_operand:V8HI 1 "register_operand" "") - (match_operand:V8HI 2 "nonimmediate_operand" "")))] - "TARGET_SSE2" -{ - if (TARGET_SSE4_1) - ix86_fixup_binary_operands_no_copy (UMAX, V8HImode, operands); - else - { - rtx op0 = operands[0], op2 = operands[2], op3 = op0; - if (rtx_equal_p (op3, op2)) - op3 = gen_reg_rtx (V8HImode); - emit_insn (gen_sse2_ussubv8hi3 (op3, operands[1], op2)); - emit_insn (gen_addv8hi3 (op0, op3, op2)); - DONE; - } -}) - -(define_expand "umaxv4si3" - [(set (match_operand:V4SI 0 "register_operand" "") - (umax:V4SI (match_operand:V4SI 1 "register_operand" "") - (match_operand:V4SI 2 "register_operand" "")))] - "TARGET_SSE2" -{ - if (TARGET_SSE4_1) - ix86_fixup_binary_operands_no_copy (UMAX, V4SImode, operands); - else - { - rtx xops[6]; - bool ok; - - xops[0] = operands[0]; - xops[1] = operands[1]; - xops[2] = operands[2]; - xops[3] = gen_rtx_GTU (VOIDmode, operands[1], operands[2]); - xops[4] = operands[1]; - xops[5] = operands[2]; - ok = ix86_expand_int_vcond (xops); - gcc_assert (ok); - DONE; - } -}) - -(define_expand "umin3" - [(set (match_operand:VI24_128 0 "register_operand" "") - (umin:VI24_128 (match_operand:VI24_128 1 "register_operand" "") - (match_operand:VI24_128 2 "register_operand" "")))] - "TARGET_SSE2" -{ - if (TARGET_SSE4_1) - ix86_fixup_binary_operands_no_copy (UMIN, mode, operands); - else - { - rtx xops[6]; - bool ok; - - xops[0] = operands[0]; - xops[1] = operands[2]; - xops[2] = operands[1]; - xops[3] = gen_rtx_GTU (VOIDmode, operands[1], operands[2]); - xops[4] = operands[1]; - xops[5] = operands[2]; - ok = ix86_expand_int_vcond (xops); - gcc_assert (ok); - DONE; - } -}) - -(define_expand "3" - [(set (match_operand:VI8_AVX2 0 "register_operand" "") - (umaxmin:VI8_AVX2 (match_operand:VI8_AVX2 1 "register_operand" "") - (match_operand:VI8_AVX2 2 "register_operand" "")))] - "TARGET_SSE4_2" -{ - rtx xops[6]; - bool ok; - - xops[0] = operands[0]; - xops[1] = operands[ == UMAX ? 1 : 2]; - xops[2] = operands[ == UMAX ? 2 : 1]; - xops[3] = gen_rtx_GTU (VOIDmode, operands[1], operands[2]); - xops[4] = operands[1]; - xops[5] = operands[2]; - ok = ix86_expand_int_vcond (xops); - gcc_assert (ok); - DONE; -}) - ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; Parallel integral comparisons