static bool s390_assemble_integer PARAMS ((rtx, unsigned int, int));
-static void s390_select_rtx_section PARAMS ((enum machine_mode, rtx,
+static void s390_select_rtx_section PARAMS ((enum machine_mode, rtx,
unsigned HOST_WIDE_INT));
static void s390_encode_section_info PARAMS ((tree, rtx, int));
static bool s390_cannot_force_const_mem PARAMS ((rtx));
static rtx s390_delegitimize_address PARAMS ((rtx));
static void s390_init_builtins PARAMS ((void));
-static rtx s390_expand_builtin PARAMS ((tree, rtx, rtx,
+static rtx s390_expand_builtin PARAMS ((tree, rtx, rtx,
enum machine_mode, int));
static void s390_output_mi_thunk PARAMS ((FILE *, tree, HOST_WIDE_INT,
HOST_WIDE_INT, tree));
static bool s390_rtx_costs PARAMS ((rtx, int, int, int *));
static int s390_address_cost PARAMS ((rtx));
static void s390_reorg PARAMS ((void));
-
+static bool s390_valid_pointer_mode PARAMS ((enum machine_mode));
#undef TARGET_ASM_ALIGNED_HI_OP
#define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
#undef TARGET_MACHINE_DEPENDENT_REORG
#define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
+#undef TARGET_VALID_POINTER_MODE
+#define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
+
struct gcc_target targetm = TARGET_INITIALIZER;
extern int reload_completed;
#define DISP_IN_RANGE(d) \
(TARGET_LONG_DISPLACEMENT? ((d) >= -524288 && (d) <= 524287) \
: ((d) >= 0 && (d) <= 4095))
-
+
/* Return true if SET either doesn't set the CC register, or else
- the source and destination have matching CC modes and that
+ the source and destination have matching CC modes and that
CC mode is at least as constrained as REQ_MODE. */
-
+
static int
s390_match_ccmode_set (set, req_mode)
rtx set;
if (req_mode != CCAmode)
return 0;
break;
-
+
default:
abort ();
}
-
+
return (GET_MODE (SET_SRC (set)) == set_mode);
}
-/* Return true if every SET in INSN that sets the CC register
- has source and destination with matching CC modes and that
- CC mode is at least as constrained as REQ_MODE.
+/* Return true if every SET in INSN that sets the CC register
+ has source and destination with matching CC modes and that
+ CC mode is at least as constrained as REQ_MODE.
If REQ_MODE is VOIDmode, always return false. */
-
+
int
s390_match_ccmode (insn, req_mode)
rtx insn;
return 1;
}
-/* If a test-under-mask instruction can be used to implement
+/* If a test-under-mask instruction can be used to implement
(compare (and ... OP1) OP2), return the CC mode required
- to do that. Otherwise, return VOIDmode.
+ to do that. Otherwise, return VOIDmode.
MIXED is true if the instruction can distinguish between
CC1 and CC2 for mixed selected bits (TMxx), it is false
if the instruction cannot (TM). */
return VOIDmode;
}
-/* Given a comparison code OP (EQ, NE, etc.) and the operands
- OP0 and OP1 of a COMPARE, return the mode to be used for the
+/* Given a comparison code OP (EQ, NE, etc.) and the operands
+ OP0 and OP1 of a COMPARE, return the mode to be used for the
comparison. */
enum machine_mode
-s390_select_ccmode (code, op0, op1)
+s390_select_ccmode (code, op0, op1)
enum rtx_code code;
rtx op0;
rtx op1;
case EQ:
case NE:
if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
- && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (op0, 1)), 'K'))
+ && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (op0, 1)), 'K'))
return CCAPmode;
if (GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS
|| GET_CODE (op1) == NEG)
}
}
- if (register_operand (op0, HImode)
+ if (register_operand (op0, HImode)
&& GET_CODE (op1) == CONST_INT
&& (INTVAL (op1) == -1 || INTVAL (op1) == 65535))
return CCT3mode;
- if (register_operand (op0, QImode)
+ if (register_operand (op0, QImode)
&& GET_CODE (op1) == CONST_INT
&& (INTVAL (op1) == -1 || INTVAL (op1) == 255))
return CCT3mode;
case GE:
case GT:
if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
- && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (op0, 1)), 'K'))
+ && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (op0, 1)), 'K'))
{
if (INTVAL (XEXP((op0), 1)) < 0)
return CCANmode;
}
}
-/* Return branch condition mask to implement a branch
+/* Return branch condition mask to implement a branch
specified by CODE. */
static int
s390_branch_condition_mask (code)
rtx code;
-{
+{
const int CC0 = 1 << 3;
const int CC1 = 1 << 2;
const int CC2 = 1 << 1;
}
}
-/* If INV is false, return assembler mnemonic string to implement
- a branch specified by CODE. If INV is true, return mnemonic
+/* If INV is false, return assembler mnemonic string to implement
+ a branch specified by CODE. If INV is true, return mnemonic
for the corresponding inverted branch. */
static const char *
}
/* If OP is an integer constant of mode MODE with exactly one
- HImode subpart unequal to DEF, return the number of that
+ HImode subpart unequal to DEF, return the number of that
subpart. As a special case, all HImode subparts of OP are
equal to DEF, return zero. Otherwise, return -1. */
return part == -1 ? 0 : (n_parts - 1 - part);
}
- return -1;
+ return -1;
}
-/* Extract the HImode part number PART from integer
+/* Extract the HImode part number PART from integer
constant OP of mode MODE. */
int
value = (unsigned HOST_WIDE_INT) CONST_DOUBLE_HIGH (op),
part -= HOST_BITS_PER_WIDE_INT / 16;
- return ((value >> (16 * part)) & 0xffff);
+ return ((value >> (16 * part)) & 0xffff);
}
abort ();
}
/* If OP is an integer constant of mode MODE with exactly one
- QImode subpart unequal to DEF, return the number of that
+ QImode subpart unequal to DEF, return the number of that
subpart. As a special case, all QImode subparts of OP are
equal to DEF, return zero. Otherwise, return -1. */
return part == -1 ? 0 : (n_parts - 1 - part);
}
- return -1;
+ return -1;
}
-/* Extract the QImode part number PART from integer
+/* Extract the QImode part number PART from integer
constant OP of mode MODE. */
int
value = (unsigned HOST_WIDE_INT) CONST_DOUBLE_HIGH (op),
part -= HOST_BITS_PER_WIDE_INT / 8;
- return ((value >> (8 * part)) & 0xff);
+ return ((value >> (8 * part)) & 0xff);
}
abort ();
}
-/* Check whether we can (and want to) split a double-word
- move in mode MODE from SRC to DST into two single-word
+/* Check whether we can (and want to) split a double-word
+ move in mode MODE from SRC to DST into two single-word
moves, moving the subword FIRST_SUBWORD first. */
bool
}
-/* Change optimizations to be performed, depending on the
+/* Change optimizations to be performed, depending on the
optimization level.
LEVEL is the optimization level specified; 2 if `-O2' is
{"g5", PROCESSOR_9672_G5, PF_IEEE_FLOAT},
{"g6", PROCESSOR_9672_G6, PF_IEEE_FLOAT},
{"z900", PROCESSOR_2064_Z900, PF_IEEE_FLOAT | PF_ZARCH},
- {"z990", PROCESSOR_2084_Z990, PF_IEEE_FLOAT | PF_ZARCH
+ {"z990", PROCESSOR_2084_Z990, PF_IEEE_FLOAT | PF_ZARCH
| PF_LONG_DISPLACEMENT},
};
FP_REGS, FP_REGS, FP_REGS, FP_REGS,
FP_REGS, FP_REGS, FP_REGS, FP_REGS,
FP_REGS, FP_REGS, FP_REGS, FP_REGS,
- ADDR_REGS, NO_REGS, ADDR_REGS
+ ADDR_REGS, NO_REGS, ADDR_REGS
};
/* Return attribute type of insn. */
/* Return true if OP a (const_int 0) operand.
OP is the current operation.
MODE is the current operation mode. */
-
+
int
const0_operand (op, mode)
register rtx op;
}
/* Return true if the mode of operand OP matches MODE.
- If MODE is set to VOIDmode, set it to the mode of OP. */
+ If MODE is set to VOIDmode, set it to the mode of OP. */
static int
check_mode (op, mode)
if (INTVAL (XEXP (op, 1)) >= (HOST_WIDE_INT)1 << 32
|| INTVAL (XEXP (op, 1)) < -((HOST_WIDE_INT)1 << 32))
return 0;
-#endif
+#endif
op = XEXP (op, 0);
}
/* Just like memory_operand, allow (subreg (mem ...))
after reload. */
- if (reload_completed
- && GET_CODE (op) == SUBREG
+ if (reload_completed
+ && GET_CODE (op) == SUBREG
&& GET_CODE (SUBREG_REG (op)) == MEM)
op = SUBREG_REG (op);
/* Constants that we are sure will be forced to the
literal pool in reload are OK as s-operand. Note
that we cannot call s390_preferred_reload_class here
- because it might not be known yet at this point
+ because it might not be known yet at this point
whether the current function is a leaf or not. */
case CONST_INT:
case CONST_DOUBLE:
case MEM:
if (GET_CODE (XEXP (op, 0)) == ADDRESSOF)
return 1;
- if (s390_decompose_address (XEXP (op, 0), &addr)
+ if (s390_decompose_address (XEXP (op, 0), &addr)
&& !addr.indx)
return 1;
break;
return general_s_operand (op, mode, 0);
}
-/* Return true if OP is a valid S-type operand or an immediate
- operand that can be addressed as S-type operand by forcing
+/* Return true if OP is a valid S-type operand or an immediate
+ operand that can be addressed as S-type operand by forcing
it into the literal pool.
OP is the current operation.
MODE is the current operation mode. */
}
\f
/* Return true if OP is a load multiple operation. It is known to be a
- PARALLEL and the first section will be tested.
+ PARALLEL and the first section will be tested.
OP is the current operation.
MODE is the current operation mode. */
if (GET_CODE (src_addr) == REG)
off = 0;
else if (GET_CODE (src_addr) == PLUS
- && GET_CODE (XEXP (src_addr, 0)) == REG
+ && GET_CODE (XEXP (src_addr, 0)) == REG
&& GET_CODE (XEXP (src_addr, 1)) == CONST_INT)
{
off = INTVAL (XEXP (src_addr, 1));
}
/* Return true if OP is a store multiple operation. It is known to be a
- PARALLEL and the first section will be tested.
+ PARALLEL and the first section will be tested.
OP is the current operation.
MODE is the current operation mode. */
if (GET_CODE (dest_addr) == REG)
off = 0;
else if (GET_CODE (dest_addr) == PLUS
- && GET_CODE (XEXP (dest_addr, 0)) == REG
+ && GET_CODE (XEXP (dest_addr, 0)) == REG
&& GET_CODE (XEXP (dest_addr, 1)) == CONST_INT)
{
off = INTVAL (XEXP (dest_addr, 1));
}
-/* Return true if OP is a legitimate general operand when
- generating PIC code. It is given that flag_pic is on
+/* Return true if OP is a legitimate general operand when
+ generating PIC code. It is given that flag_pic is on
and that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
int
if (!SYMBOLIC_CONST (op))
return 1;
- /* Reject everything else; must be handled
+ /* Reject everything else; must be handled
via emit_symbolic_move. */
return 0;
}
}
/* Returns true if the constant value OP is a legitimate general
- operand during and after reload. The difference to
+ operand during and after reload. The difference to
legitimate_constant_p is that this function will not accept
a constant that would need to be forced to the literal pool
before it can be used as operand. */
register rtx op;
{
/* Accept la(y) operands. */
- if (GET_CODE (op) == CONST_INT
+ if (GET_CODE (op) == CONST_INT
&& DISP_IN_RANGE (INTVAL (op)))
return 1;
/* Return the register class of a scratch register needed to
store a register of class CLASS in MODE into OUT:
- We need a temporary when storing a double-word to a
+ We need a temporary when storing a double-word to a
non-offsettable memory address. */
enum reg_class
}
/* Return true if OP is a PLUS that is not a legitimate
- operand for the LA instruction.
+ operand for the LA instruction.
OP is the current operation.
MODE is the current operation mode. */
{
pointer = TRUE;
}
-
+
/* Likewise if a constant offset is present. */
else if (GET_CODE (disp) == CONST
&& GET_CODE (XEXP (disp, 0)) == PLUS
pointer = TRUE;
}
- /* We can convert literal pool addresses to
+ /* We can convert literal pool addresses to
displacements by basing them off the base register. */
else
{
if (offset && offset >= GET_MODE_SIZE (get_pool_mode (disp)))
return FALSE;
- /* Either base or index must be free to
+ /* Either base or index must be free to
hold the base register. */
if (base && indx)
return FALSE;
else
base = gen_rtx_REG (Pmode, BASE_REGISTER);
- disp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, disp),
+ disp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, disp),
UNSPEC_LTREL_OFFSET);
disp = gen_rtx_CONST (Pmode, disp);
if (!base && !indx)
pointer = TRUE;
-
+
if (out)
{
out->base = base;
/* Return 1 if OP is a valid operand for the LA instruction,
and we prefer to use LA over addition to compute it. */
-
+
int
preferred_la_operand_p (op)
register rtx op;
/* This is a local symbol. */
if (TARGET_64BIT && larl_operand (addr, VOIDmode))
{
- /* Access local symbols PC-relative via LARL.
- This is the same as in the non-PIC case, so it is
+ /* Access local symbols PC-relative via LARL.
+ This is the same as in the non-PIC case, so it is
handled automatically ... */
}
else
}
else
{
- /* If the GOT offset might be >= 4k, we have to load it
+ /* If the GOT offset might be >= 4k, we have to load it
from the literal pool (@GOT). */
rtx temp = gen_reg_rtx (Pmode);
emit_move_insn (reg, new);
new = reg;
}
- }
+ }
else
{
if (GET_CODE (addr) == CONST)
regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
addr = XVECEXP (addr, 0, 0);
- addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr),
+ addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr),
UNSPEC_PLTOFF);
addr = gen_rtx_CONST (Pmode, addr);
addr = force_const_mem (Pmode, addr);
if (GET_CODE (addr) == PLUS)
{
rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
- /* Check first to see if this is a constant offset
+ /* Check first to see if this is a constant offset
from a local symbol reference. */
if ((GET_CODE (op0) == LABEL_REF
|| (GET_CODE (op0) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op0)))
{
if (INTVAL (op1) & 1)
{
- /* LARL can't handle odd offsets, so emit a
+ /* LARL can't handle odd offsets, so emit a
pair of LARL and LA. */
rtx temp = reg? reg : gen_reg_rtx (Pmode);
if (reload_in_progress || reload_completed)
regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
- addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
+ addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
UNSPEC_GOTOFF);
addr = gen_rtx_PLUS (Pmode, addr, op1);
addr = gen_rtx_CONST (Pmode, addr);
}
else if (flag_pic)
{
- /* If the GOT offset might be >= 4k, we have to load it
+ /* If the GOT offset might be >= 4k, we have to load it
from the literal pool. */
if (reload_in_progress || reload_completed)
else if (flag_pic)
{
if (SYMBOLIC_CONST (x)
- || (GET_CODE (x) == PLUS
- && (SYMBOLIC_CONST (XEXP (x, 0))
+ || (GET_CODE (x) == PLUS
+ && (SYMBOLIC_CONST (XEXP (x, 0))
|| SYMBOLIC_CONST (XEXP (x, 1)))))
x = legitimize_pic_address (x, 0);
/* Optimize loading of large displacements by splitting them
into the multiple of 4K and the rest; this allows the
- former to be CSE'd if possible.
+ former to be CSE'd if possible.
Don't do this if the displacement is added to a register
pointing into the stack frame, as the offsets will
rtx src;
rtx len;
{
- rtx (*gen_short) PARAMS ((rtx, rtx, rtx)) =
+ rtx (*gen_short) PARAMS ((rtx, rtx, rtx)) =
TARGET_64BIT ? gen_movstr_short_64 : gen_movstr_short_31;
- rtx (*gen_long) PARAMS ((rtx, rtx, rtx, rtx)) =
+ rtx (*gen_long) PARAMS ((rtx, rtx, rtx, rtx)) =
TARGET_64BIT ? gen_movstr_long_64 : gen_movstr_long_31;
rtx reg0 = gen_reg_rtx (double_mode);
rtx reg1 = gen_reg_rtx (double_mode);
- emit_move_insn (gen_highpart (single_mode, reg0),
+ emit_move_insn (gen_highpart (single_mode, reg0),
force_operand (XEXP (dst, 0), NULL_RTX));
- emit_move_insn (gen_highpart (single_mode, reg1),
+ emit_move_insn (gen_highpart (single_mode, reg1),
force_operand (XEXP (src, 0), NULL_RTX));
convert_move (gen_lowpart (single_mode, reg0), len, 1);
blocks = gen_reg_rtx (mode);
convert_move (count, len, 1);
- emit_cmp_and_jump_insns (count, const0_rtx,
+ emit_cmp_and_jump_insns (count, const0_rtx,
EQ, NULL_RTX, mode, 1, end_label);
emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
emit_move_insn (src_addr, force_operand (XEXP (src, 0), NULL_RTX));
dst = change_address (dst, VOIDmode, dst_addr);
src = change_address (src, VOIDmode, src_addr);
-
+
temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1, 0);
if (temp != count)
emit_move_insn (count, temp);
make_tree (type, const0_rtx)));
emit_insn ((*gen_short) (dst, src, GEN_INT (255)));
- s390_load_address (dst_addr,
+ s390_load_address (dst_addr,
gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
- s390_load_address (src_addr,
+ s390_load_address (src_addr,
gen_rtx_PLUS (Pmode, src_addr, GEN_INT (256)));
-
+
temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1, 0);
if (temp != blocks)
emit_move_insn (blocks, temp);
rtx dst;
rtx len;
{
- rtx (*gen_short) PARAMS ((rtx, rtx)) =
+ rtx (*gen_short) PARAMS ((rtx, rtx)) =
TARGET_64BIT ? gen_clrstr_short_64 : gen_clrstr_short_31;
- rtx (*gen_long) PARAMS ((rtx, rtx, rtx)) =
+ rtx (*gen_long) PARAMS ((rtx, rtx, rtx)) =
TARGET_64BIT ? gen_clrstr_long_64 : gen_clrstr_long_31;
rtx reg0 = gen_reg_rtx (double_mode);
rtx reg1 = gen_reg_rtx (double_mode);
- emit_move_insn (gen_highpart (single_mode, reg0),
+ emit_move_insn (gen_highpart (single_mode, reg0),
force_operand (XEXP (dst, 0), NULL_RTX));
convert_move (gen_lowpart (single_mode, reg0), len, 1);
blocks = gen_reg_rtx (mode);
convert_move (count, len, 1);
- emit_cmp_and_jump_insns (count, const0_rtx,
+ emit_cmp_and_jump_insns (count, const0_rtx,
EQ, NULL_RTX, mode, 1, end_label);
emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
dst = change_address (dst, VOIDmode, dst_addr);
-
+
temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1, 0);
if (temp != count)
emit_move_insn (count, temp);
make_tree (type, const0_rtx)));
emit_insn ((*gen_short) (dst, GEN_INT (255)));
- s390_load_address (dst_addr,
+ s390_load_address (dst_addr,
gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
-
+
temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1, 0);
if (temp != blocks)
emit_move_insn (blocks, temp);
rtx op1;
rtx len;
{
- rtx (*gen_short) PARAMS ((rtx, rtx, rtx)) =
+ rtx (*gen_short) PARAMS ((rtx, rtx, rtx)) =
TARGET_64BIT ? gen_cmpmem_short_64 : gen_cmpmem_short_31;
- rtx (*gen_long) PARAMS ((rtx, rtx, rtx, rtx)) =
+ rtx (*gen_long) PARAMS ((rtx, rtx, rtx, rtx)) =
TARGET_64BIT ? gen_cmpmem_long_64 : gen_cmpmem_long_31;
rtx (*gen_result) PARAMS ((rtx)) =
GET_MODE (target) == DImode ? gen_cmpint_di : gen_cmpint_si;
rtx reg0 = gen_reg_rtx (double_mode);
rtx reg1 = gen_reg_rtx (double_mode);
- emit_move_insn (gen_highpart (single_mode, reg0),
+ emit_move_insn (gen_highpart (single_mode, reg0),
force_operand (XEXP (op0, 0), NULL_RTX));
- emit_move_insn (gen_highpart (single_mode, reg1),
+ emit_move_insn (gen_highpart (single_mode, reg1),
force_operand (XEXP (op1, 0), NULL_RTX));
convert_move (gen_lowpart (single_mode, reg0), len, 1);
blocks = gen_reg_rtx (mode);
convert_move (count, len, 1);
- emit_cmp_and_jump_insns (count, const0_rtx,
+ emit_cmp_and_jump_insns (count, const0_rtx,
EQ, NULL_RTX, mode, 1, end_label);
emit_move_insn (addr0, force_operand (XEXP (op0, 0), NULL_RTX));
emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
op0 = change_address (op0, VOIDmode, addr0);
op1 = change_address (op1, VOIDmode, addr1);
-
+
temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1, 0);
if (temp != count)
emit_move_insn (count, temp);
emit_insn ((*gen_short) (op0, op1, GEN_INT (255)));
temp = gen_rtx_NE (VOIDmode, gen_rtx_REG (CCSmode, 33), const0_rtx);
- temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
+ temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
gen_rtx_LABEL_REF (VOIDmode, end_label), pc_rtx);
temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
emit_jump_insn (temp);
- s390_load_address (addr0,
+ s390_load_address (addr0,
gen_rtx_PLUS (Pmode, addr0, GEN_INT (256)));
- s390_load_address (addr1,
+ s390_load_address (addr1,
gen_rtx_PLUS (Pmode, addr1, GEN_INT (256)));
-
+
temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1, 0);
if (temp != blocks)
emit_move_insn (blocks, temp);
return orig_x;
}
- return orig_x;
+ return orig_x;
}
/* Locate some local-dynamic symbol still in use by this function
return 0;
}
-/* Output symbolic constant X in assembler syntax to
+/* Output symbolic constant X in assembler syntax to
stdio stream FILE. */
void
{
case UNSPEC_LTREL_OFFSET:
s390_output_symbolic_const (file, XVECEXP (x, 0, 0));
- fprintf (file, "-");
+ fprintf (file, "-");
s390_output_symbolic_const (file, cfun->machine->literal_pool_label);
break;
case UNSPEC_GOTENT:
}
}
-/* Output address operand ADDR in assembler syntax to
+/* Output address operand ADDR in assembler syntax to
stdio stream FILE. */
void
|| (ad.base && !REG_OK_FOR_BASE_STRICT_P (ad.base))
|| (ad.indx && !REG_OK_FOR_INDEX_STRICT_P (ad.indx)))
output_operand_lossage ("Cannot decompose address.");
-
+
if (ad.disp)
s390_output_symbolic_const (file, ad.disp);
else
fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
}
-/* Output operand X in assembler syntax to stdio stream FILE.
- CODE specified the format flag. The following format flags
+/* Output operand X in assembler syntax to stdio stream FILE.
+ CODE specified the format flag. The following format flags
are recognized:
'C': print opcode suffix for branch condition.
return default_assemble_integer (x, size, aligned_p);
}
-/* Returns true if register REGNO is used for forming
+/* Returns true if register REGNO is used for forming
a memory address in expression X. */
static int
enum rtx_code code = GET_CODE (x);
int i, j;
const char *fmt;
-
+
if (code == MEM)
{
if (refers_to_regno_p (regno, regno+1,
XEXP (x, 0), 0))
return 1;
}
- else if (code == SET
+ else if (code == SET
&& GET_CODE (SET_DEST (x)) == PC)
{
if (refers_to_regno_p (regno, regno+1,
if (fmt[i] == 'e'
&& reg_used_in_mem_p (regno, XEXP (x, i)))
return 1;
-
+
else if (fmt[i] == 'E')
for (j = 0; j < XVECLEN (x, i); j++)
if (reg_used_in_mem_p (regno, XVECEXP (x, i, j)))
/* Returns true if expression DEP_RTX sets an address register
used by instruction INSN to address memory. */
-static int
+static int
addr_generation_dependency_p (dep_rtx, insn)
- rtx dep_rtx;
+ rtx dep_rtx;
rtx insn;
{
rtx target, pat;
/* Return 1, if dep_insn sets register used in insn in the agen unit. */
-int
+int
s390_agen_dep_p(dep_insn, insn)
rtx dep_insn;
rtx insn;
-{
+{
rtx dep_rtx = PATTERN (dep_insn);
int i;
-
- if (GET_CODE (dep_rtx) == SET
+
+ if (GET_CODE (dep_rtx) == SET
&& addr_generation_dependency_p (dep_rtx, insn))
return 1;
else if (GET_CODE (dep_rtx) == PARALLEL)
}
/* Return the modified cost of the dependency of instruction INSN
- on instruction DEP_INSN through the link LINK. COST is the
+ on instruction DEP_INSN through the link LINK. COST is the
default cost of that dependency.
Data dependencies are all handled without delay. However, if a
- register is modified and subsequently used as base or index
+ register is modified and subsequently used as base or index
register of a memory reference, at least 4 cycles need to pass
- between setting and using the register to avoid pipeline stalls.
+ between setting and using the register to avoid pipeline stalls.
An exception is the LA instruction. An address generated by LA can
be used by introducing only a one cycle stall on the pipeline. */
/* DFA based scheduling checks address dependency in md file. */
if (s390_use_dfa_pipeline_interface ())
{
- /* Operand forward in case of lr, load and la. */
+ /* Operand forward in case of lr, load and la. */
if (s390_tune == PROCESSOR_2084_Z990
&& cost == 1
&& (s390_safe_attr_type (dep_insn) == TYPE_LA
dep_rtx = PATTERN (dep_insn);
- if (GET_CODE (dep_rtx) == SET
+ if (GET_CODE (dep_rtx) == SET
&& addr_generation_dependency_p (dep_rtx, insn))
- cost += (s390_safe_attr_type (dep_insn) == TYPE_LA) ? 1 : 4;
+ cost += (s390_safe_attr_type (dep_insn) == TYPE_LA) ? 1 : 4;
else if (GET_CODE (dep_rtx) == PARALLEL)
{
for (i = 0; i < XVECLEN (dep_rtx, 0); i++)
{
if (addr_generation_dependency_p (XVECEXP (dep_rtx, 0, i), insn))
- cost += (s390_safe_attr_type (dep_insn) == TYPE_LA) ? 1 : 4;
+ cost += (s390_safe_attr_type (dep_insn) == TYPE_LA) ? 1 : 4;
}
}
/* A C statement (sans semicolon) to update the integer scheduling priority
INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier,
reduce the priority to execute INSN later. Do not define this macro if
- you do not need to adjust the scheduling priorities of insns.
+ you do not need to adjust the scheduling priorities of insns.
- A STD instruction should be scheduled earlier,
+ A STD instruction should be scheduled earlier,
in order to use the bypass. */
static int
static int
s390_issue_rate ()
{
- if (s390_tune == PROCESSOR_2084_Z990)
+ if (s390_tune == PROCESSOR_2084_Z990)
return 3;
return 1;
}
}
-/* Split all branches that exceed the maximum distance.
- Returns true if this created a new literal pool entry.
+/* Split all branches that exceed the maximum distance.
+ Returns true if this created a new literal pool entry.
Code generated by this routine is allowed to use
TEMP_REG as temporary scratch register. If this is
done, TEMP_USED is set to true. */
-static int
+static int
s390_split_branches (temp_reg, temp_used)
rtx temp_reg;
bool *temp_used;
if (GET_CODE (pat) != SET || SET_DEST (pat) != pc_rtx)
continue;
- if (GET_CODE (SET_SRC (pat)) == LABEL_REF)
+ if (GET_CODE (SET_SRC (pat)) == LABEL_REF)
{
label = &SET_SRC (pat);
- }
- else if (GET_CODE (SET_SRC (pat)) == IF_THEN_ELSE)
+ }
+ else if (GET_CODE (SET_SRC (pat)) == IF_THEN_ELSE)
{
- if (GET_CODE (XEXP (SET_SRC (pat), 1)) == LABEL_REF)
+ if (GET_CODE (XEXP (SET_SRC (pat), 1)) == LABEL_REF)
label = &XEXP (SET_SRC (pat), 1);
- else if (GET_CODE (XEXP (SET_SRC (pat), 2)) == LABEL_REF)
+ else if (GET_CODE (XEXP (SET_SRC (pat), 2)) == LABEL_REF)
label = &XEXP (SET_SRC (pat), 2);
else
continue;
else
{
new_literal = 1;
- target = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, *label),
+ target = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, *label),
UNSPEC_LTREL_OFFSET);
target = gen_rtx_CONST (Pmode, target);
target = force_const_mem (Pmode, target);
tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, target), insn);
INSN_ADDRESSES_NEW (tmp, -1);
- target = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (target, 0)),
+ target = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (target, 0)),
UNSPEC_LTREL_BASE);
target = gen_rtx_PLUS (Pmode, temp_reg, target);
}
}
-/* Find a literal pool symbol referenced in RTX X, and store
- it at REF. Will abort if X contains references to more than
+/* Find a literal pool symbol referenced in RTX X, and store
+ it at REF. Will abort if X contains references to more than
one such pool symbol; multiple references to the same symbol
- are allowed, however.
+ are allowed, however.
- The rtx pointed to by REF must be initialized to NULL_RTX
+ The rtx pointed to by REF must be initialized to NULL_RTX
by the caller before calling this routine. */
static void
}
}
-/* Check whether X contains an UNSPEC_LTREL_BASE.
+/* Check whether X contains an UNSPEC_LTREL_BASE.
Return its constant pool symbol if found, NULL_RTX otherwise. */
static rtx
constant tables in the middle of large functions. */
#define NR_C_MODES 7
-enum machine_mode constant_modes[NR_C_MODES] =
+enum machine_mode constant_modes[NR_C_MODES] =
{
TImode,
DFmode, DImode,
/* Find constant VAL of mode MODE in the constant pool POOL.
Return an RTX describing the distance from the start of
the pool to the location of the new constant. */
-
+
static rtx
s390_find_constant (pool, val, mode)
struct constant_pool *pool;
struct constant *c;
rtx offset;
int i;
-
+
for (i = 0; i < NR_C_MODES; i++)
if (constant_modes[i] == mode)
break;
if (i == NR_C_MODES)
abort ();
-
+
for (c = pool->constants[i]; c != NULL; c = c->next)
if (rtx_equal_p (val, c->value))
break;
-
+
if (c == NULL)
abort ();
-
+
offset = gen_rtx_MINUS (Pmode, gen_rtx_LABEL_REF (Pmode, c->label),
gen_rtx_LABEL_REF (Pmode, pool->label));
offset = gen_rtx_CONST (Pmode, offset);
rtx insn;
int i;
- /* Pool start insn switches to proper section
+ /* Pool start insn switches to proper section
and guarantees necessary alignment. */
if (TARGET_64BIT)
insn = emit_insn_after (gen_pool_start_64 (), pool->pool_insn);
INSN_ADDRESSES_NEW (insn, -1);
}
- /* Pool end insn switches back to previous section
+ /* Pool end insn switches back to previous section
and guarantees necessary alignment. */
if (TARGET_64BIT)
insn = emit_insn_after (gen_pool_end_64 (), insn);
BITMAP_XFREE (pool->insns);
free (pool);
-}
+}
/* Chunkify the literal pool if required. */
#define S390_POOL_CHUNK_MIN 0xc00
#define S390_POOL_CHUNK_MAX 0xe00
-static struct constant_pool *
+static struct constant_pool *
s390_chunkify_start (void)
{
rtx base_reg = gen_rtx_REG (Pmode, BASE_REGISTER);
abort ();
}
- if (!curr_pool
+ if (!curr_pool
|| INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn)
|| INSN_ADDRESSES (INSN_UID (insn)) == -1)
continue;
if (get_attr_length (insn) == 0)
continue;
- /* Don't separate LTREL_BASE from the corresponding
+ /* Don't separate LTREL_BASE from the corresponding
LTREL_OFFSET load. */
if (pending_ltrel)
continue;
abort ();
- /* Find all labels that are branched into
+ /* Find all labels that are branched into
from an insn belonging to a different chunk. */
far_labels = BITMAP_XMALLOC ();
Don't do that, however, if it is the label before
a jump table. */
- if (GET_CODE (insn) == CODE_LABEL
+ if (GET_CODE (insn) == CODE_LABEL
&& (LABEL_PRESERVE_P (insn) || LABEL_NAME (insn)))
{
rtx vec_insn = next_real_insn (insn);
- rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
+ rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
PATTERN (vec_insn) : NULL_RTX;
if (!vec_pat
|| !(GET_CODE (vec_pat) == ADDR_VEC
/* If we have a direct jump (conditional or unconditional)
or a casesi jump, check all potential targets. */
- else if (GET_CODE (insn) == JUMP_INSN)
+ else if (GET_CODE (insn) == JUMP_INSN)
{
rtx pat = PATTERN (insn);
if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
pat = XVECEXP (pat, 0, 0);
- if (GET_CODE (pat) == SET)
+ if (GET_CODE (pat) == SET)
{
rtx label = JUMP_LABEL (insn);
if (label)
{
- if (s390_find_pool (pool_list, label)
+ if (s390_find_pool (pool_list, label)
!= s390_find_pool (pool_list, insn))
bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
}
- }
+ }
else if (GET_CODE (pat) == PARALLEL
&& XVECLEN (pat, 0) == 2
&& GET_CODE (XVECEXP (pat, 0, 0)) == SET
/* Find the jump table used by this casesi jump. */
rtx vec_label = XEXP (XEXP (XVECEXP (pat, 0, 1), 0), 0);
rtx vec_insn = next_real_insn (vec_label);
- rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
+ rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
PATTERN (vec_insn) : NULL_RTX;
if (vec_pat
&& (GET_CODE (vec_pat) == ADDR_VEC
{
rtx label = XEXP (XVECEXP (vec_pat, diff_p, i), 0);
- if (s390_find_pool (pool_list, label)
+ if (s390_find_pool (pool_list, label)
!= s390_find_pool (pool_list, insn))
bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
}
/* Insert base register reload insns at every far label. */
for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
- if (GET_CODE (insn) == CODE_LABEL
+ if (GET_CODE (insn) == CODE_LABEL
&& bitmap_bit_p (far_labels, CODE_LABEL_NUMBER (insn)))
{
struct constant_pool *pool = s390_find_pool (pool_list, insn);
}
/* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
- After we have decided to use this list, finish implementing
+ After we have decided to use this list, finish implementing
all changes to the current function as required. */
-
+
static void
s390_chunkify_finish (pool_list)
struct constant_pool *pool_list;
rtx base_reg = gen_rtx_REG (Pmode, BASE_REGISTER);
struct constant_pool *curr_pool = NULL;
rtx insn;
-
-
+
+
/* Replace all literal pool references. */
- for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
+ for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
{
if (INSN_P (insn))
replace_ltrel_base (&PATTERN (insn), base_reg);
}
/* Dump out all literal pools. */
-
+
for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
s390_dump_pool (curr_pool);
-
+
/* Free pool list. */
while (pool_list)
/* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
We have decided we cannot use this list, so revert all changes
to the current function that were done by s390_chunkify_start. */
-
+
static void
s390_chunkify_cancel (pool_list)
struct constant_pool *pool_list;
/* Number of elements of current constant pool. */
int s390_nr_constants;
-/* Output main constant pool to stdio stream FILE. */
+/* Output main constant pool to stdio stream FILE. */
void
s390_output_constant_pool (start_label, end_label)
rtx start_label;
rtx end_label;
{
- if (TARGET_64BIT)
+ if (TARGET_64BIT)
{
readonly_data_section ();
ASM_OUTPUT_ALIGN (asm_out_file, 3);
- (*targetm.asm_out.internal_label) (asm_out_file, "L",
+ (*targetm.asm_out.internal_label) (asm_out_file, "L",
CODE_LABEL_NUMBER (start_label));
- }
- else
+ }
+ else
{
(*targetm.asm_out.internal_label) (asm_out_file, "L",
CODE_LABEL_NUMBER (start_label));
- ASM_OUTPUT_ALIGN (asm_out_file, 2);
+ ASM_OUTPUT_ALIGN (asm_out_file, 2);
}
s390_pool_count = 0;
else
{
ASM_OUTPUT_ALIGN (asm_out_file, 1);
- (*targetm.asm_out.internal_label) (asm_out_file, "L",
+ (*targetm.asm_out.internal_label) (asm_out_file, "L",
CODE_LABEL_NUMBER (end_label));
}
}
/* Rework the prolog/epilog to avoid saving/restoring
registers unnecessarily. If TEMP_REGNO is nonnegative,
- it specifies the number of a caller-saved register used
- as temporary scratch register by code emitted during
+ it specifies the number of a caller-saved register used
+ as temporary scratch register by code emitted during
machine dependent reorg. */
static void
regs_ever_live[STACK_POINTER_REGNUM] = cfun->machine->frame_size > 0;
/* If there is (possibly) any pool entry, we need to
- load the base register.
+ load the base register.
??? FIXME: this should be more precise. */
if (get_pool_size ())
regs_ever_live[BASE_REGISTER] = 1;
- /* In non-leaf functions, the prolog/epilog code relies
+ /* In non-leaf functions, the prolog/epilog code relies
on RETURN_REGNUM being saved in any case. */
if (!current_function_is_leaf)
regs_ever_live[RETURN_REGNUM] = 1;
/* Find first and last gpr to be saved. */
-
+
for (i = 6; i < 16; i++)
if (regs_ever_live[i])
if (!global_regs[i]
- || i == STACK_POINTER_REGNUM
+ || i == STACK_POINTER_REGNUM
|| i == RETURN_REGNUM
- || i == BASE_REGISTER
+ || i == BASE_REGISTER
|| (flag_pic && i == (int)PIC_OFFSET_TABLE_REGNUM))
break;
for (j = 15; j > i; j--)
if (regs_ever_live[j])
if (!global_regs[j]
- || j == STACK_POINTER_REGNUM
+ || j == STACK_POINTER_REGNUM
|| j == RETURN_REGNUM
- || j == BASE_REGISTER
+ || j == BASE_REGISTER
|| (flag_pic && j == (int)PIC_OFFSET_TABLE_REGNUM))
break;
/* There are two problematic situations we need to correct:
-
+
- the literal pool might be > 4096 bytes in size, so that
some of its elements cannot be directly accessed
-
+
- a branch target might be > 64K away from the branch, so that
it is not possible to use a PC-relative instruction.
-
+
To fix those, we split the single literal pool into multiple
pool chunks, reloading the pool base register at various
points throughout the function to ensure it always points to
the pool chunk the following code expects, and / or replace
PC-relative branches by absolute branches.
-
+
However, the two problems are interdependent: splitting the
literal pool can move a branch further away from its target,
causing the 64K limit to overflow, and on the other hand,
replacing a PC-relative branch by an absolute branch means
we need to put the branch target address into the literal
pool, possibly causing it to overflow.
-
+
So, we loop trying to fix up both problems until we manage
to satisfy both conditions at the same time. Note that the
loop is guaranteed to terminate as every pass of the loop
in the function. (This is not completely true as there
might be branch-over-pool insns introduced by chunkify_start.
Those never need to be split however.) */
-
+
for (;;)
{
struct constant_pool *pool_list;
-
+
/* Try to chunkify the literal pool. */
pool_list = s390_chunkify_start ();
{
if (pool_list)
s390_chunkify_cancel (pool_list);
-
+
continue;
}
continue;
}
-
+
/* If we made it up to here, both conditions are satisfied.
Finish up pool chunkification if required. */
if (pool_list)
s390_chunkify_finish (pool_list);
-
+
break;
}
-
+
s390_optimize_prolog (temp_used? RETURN_REGNUM : -1);
}
addr = plus_constant (frame, RETURN_REGNUM * UNITS_PER_WORD);
addr = memory_address (Pmode, addr);
return gen_rtx_MEM (Pmode, addr);
-}
+}
/* Find first call clobbered register unsused in a function.
This could be used as base register in a leaf function
/* fprs 8 - 15 are caller saved for 64 Bit ABI. */
cfun->machine->save_fprs_p = 0;
if (TARGET_64BIT)
- for (i = 24; i < 32; i++)
+ for (i = 24; i < 32; i++)
if (regs_ever_live[i] && !global_regs[i])
{
cfun->machine->save_fprs_p = 1;
cfun->machine->frame_size = fsize + cfun->machine->save_fprs_p * 64;
/* Does function need to setup frame and save area. */
-
+
if (! current_function_is_leaf
|| cfun->machine->frame_size > 0
- || current_function_calls_alloca
+ || current_function_calls_alloca
|| current_function_stdarg)
cfun->machine->frame_size += STARTING_FRAME_OFFSET;
gprs_ever_live[BASE_REGISTER] = 1;
gprs_ever_live[RETURN_REGNUM] = 1;
gprs_ever_live[STACK_POINTER_REGNUM] = cfun->machine->frame_size > 0;
-
+
for (i = 6; i < 16; i++)
if (gprs_ever_live[i])
break;
cfun->machine->first_save_gpr = 2;
}
-/* Return offset between argument pointer and frame pointer
+/* Return offset between argument pointer and frame pointer
initially after prologue. */
-int
+int
s390_arg_frame_offset ()
{
HOST_WIDE_INT fsize = get_frame_size ();
/* fprs 8 - 15 are caller saved for 64 Bit ABI. */
save_fprs_p = 0;
if (TARGET_64BIT)
- for (i = 24; i < 32; i++)
+ for (i = 24; i < 32; i++)
if (regs_ever_live[i] && !global_regs[i])
{
save_fprs_p = 1;
fsize = fsize + save_fprs_p * 64;
/* Does function need to setup frame and save area. */
-
+
if (! current_function_is_leaf
|| fsize > 0
- || current_function_calls_alloca
+ || current_function_calls_alloca
|| current_function_stdarg)
fsize += STARTING_FRAME_OFFSET;
return fsize + STACK_POINTER_OFFSET;
}
/* Emit insn to save fpr REGNUM at offset OFFSET relative
- to register BASE. Return generated insn. */
+ to register BASE. Return generated insn. */
static rtx
save_fpr (base, offset, regnum)
rtx base;
int offset;
- int regnum;
+ int regnum;
{
rtx addr;
addr = gen_rtx_MEM (DFmode, plus_constant (base, offset));
}
/* Emit insn to restore fpr REGNUM from offset OFFSET relative
- to register BASE. Return generated insn. */
+ to register BASE. Return generated insn. */
static rtx
restore_fpr (base, offset, regnum)
}
/* Generate insn to save registers FIRST to LAST into
- the register save area located at offset OFFSET
+ the register save area located at offset OFFSET
relative to register BASE. */
static rtx
inside the store-multiple pattern.
However, we must not emit DWARF records for registers 2..5
- if they are stored for use by variable arguments ...
+ if they are stored for use by variable arguments ...
??? Unfortunately, it is not enough to simply not the the
FRAME_RELATED flags for those SETs, because the first SET
else if (last >= 6)
{
addr = plus_constant (base, offset + 6 * UNITS_PER_WORD);
- note = gen_store_multiple (gen_rtx_MEM (Pmode, addr),
+ note = gen_store_multiple (gen_rtx_MEM (Pmode, addr),
gen_rtx_REG (Pmode, 6),
GEN_INT (last - 6 + 1));
note = PATTERN (note);
REG_NOTES (insn) =
- gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
+ gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
note, REG_NOTES (insn));
for (i = 0; i < XVECLEN (note, 0); i++)
}
/* Generate insn to restore registers FIRST to LAST from
- the register save area located at offset OFFSET
+ the register save area located at offset OFFSET
relative to register BASE. */
static rtx
{
rtx offset, insn;
- offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, got_symbol),
+ offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, got_symbol),
UNSPEC_LTREL_OFFSET);
offset = gen_rtx_CONST (Pmode, offset);
offset = force_const_mem (Pmode, offset);
REG_NOTES(insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, NULL_RTX,
REG_NOTES (insn));
- offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (offset, 0)),
+ offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (offset, 0)),
UNSPEC_LTREL_BASE);
offset = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, offset);
s390_frame_info ();
- /* Choose best register to use for temp use within prologue. */
-
+ /* Choose best register to use for temp use within prologue.
+ See below for why TPF must use the register 1. */
+
if (!current_function_is_leaf
&& !has_hard_reg_initial_val (Pmode, RETURN_REGNUM)
- && get_pool_size () < S390_POOL_CHUNK_MAX / 2)
+ && get_pool_size () < S390_POOL_CHUNK_MAX / 2
+ && !TARGET_TPF)
temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
else
temp_reg = gen_rtx_REG (Pmode, 1);
/* Save call saved gprs. */
- insn = save_gprs (stack_pointer_rtx, 0,
+ insn = save_gprs (stack_pointer_rtx, 0,
cfun->machine->first_save_gpr, cfun->machine->last_save_gpr);
emit_insn (insn);
pool_start_label = gen_label_rtx();
pool_end_label = gen_label_rtx();
cfun->machine->literal_pool_label = pool_start_label;
-
+
if (TARGET_64BIT)
insn = emit_insn (gen_literal_pool_64 (gen_rtx_REG (Pmode, BASE_REGISTER),
pool_start_label, pool_end_label));
else
insn = emit_insn (gen_literal_pool_31 (gen_rtx_REG (Pmode, BASE_REGISTER),
- pool_start_label, pool_end_label));
-
+ pool_start_label, pool_end_label));
+
/* Save fprs for variable args. */
if (current_function_stdarg)
{
- /* Save fpr 0 and 2. */
+ /* Save fpr 0 and 2. */
+
+ save_fpr (stack_pointer_rtx, STACK_POINTER_OFFSET - 32, 16);
+ save_fpr (stack_pointer_rtx, STACK_POINTER_OFFSET - 24, 17);
- save_fpr (stack_pointer_rtx, STACK_POINTER_OFFSET - 32, 16);
- save_fpr (stack_pointer_rtx, STACK_POINTER_OFFSET - 24, 17);
-
if (TARGET_64BIT)
{
/* Save fpr 4 and 6. */
-
- save_fpr (stack_pointer_rtx, STACK_POINTER_OFFSET - 16, 18);
- save_fpr (stack_pointer_rtx, STACK_POINTER_OFFSET - 8, 19);
+
+ save_fpr (stack_pointer_rtx, STACK_POINTER_OFFSET - 16, 18);
+ save_fpr (stack_pointer_rtx, STACK_POINTER_OFFSET - 8, 19);
}
}
}
if (regs_ever_live[19] && !global_regs[19])
{
- insn = save_fpr (stack_pointer_rtx, STACK_POINTER_OFFSET - 8, 19);
+ insn = save_fpr (stack_pointer_rtx, STACK_POINTER_OFFSET - 8, 19);
RTX_FRAME_RELATED_P (insn) = 1;
}
}
rtx frame_off = GEN_INT (-cfun->machine->frame_size);
/* Save incoming stack pointer into temp reg. */
-
+
if (TARGET_BACKCHAIN || cfun->machine->save_fprs_p)
{
insn = emit_insn (gen_move_insn (temp_reg, stack_pointer_rtx));
}
-
+
/* Subtract frame size from stack pointer. */
if (DISP_IN_RANGE (INTVAL (frame_off)))
{
- insn = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
- gen_rtx_PLUS (Pmode, stack_pointer_rtx,
+ insn = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
+ gen_rtx_PLUS (Pmode, stack_pointer_rtx,
frame_off));
insn = emit_insn (insn);
}
}
RTX_FRAME_RELATED_P (insn) = 1;
- REG_NOTES (insn) =
+ REG_NOTES (insn) =
gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
gen_rtx_SET (VOIDmode, stack_pointer_rtx,
gen_rtx_PLUS (Pmode, stack_pointer_rtx,
REG_NOTES (insn));
/* Set backchain. */
-
+
if (TARGET_BACKCHAIN)
{
addr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
}
/* Save fprs 8 - 15 (64 bit ABI). */
-
+
if (cfun->machine->save_fprs_p)
{
insn = emit_insn (gen_add2_insn (temp_reg, GEN_INT(-64)));
for (i = 24; i < 32; i++)
if (regs_ever_live[i] && !global_regs[i])
{
- rtx addr = plus_constant (stack_pointer_rtx,
+ rtx addr = plus_constant (stack_pointer_rtx,
cfun->machine->frame_size - 64 + (i-24)*8);
insn = save_fpr (temp_reg, (i-24)*8, i);
RTX_FRAME_RELATED_P (insn) = 1;
- REG_NOTES (insn) =
+ REG_NOTES (insn) =
gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
- gen_rtx_SET (VOIDmode,
+ gen_rtx_SET (VOIDmode,
gen_rtx_MEM (DFmode, addr),
gen_rtx_REG (DFmode, i)),
REG_NOTES (insn));
}
}
-
+
/* Set frame pointer, if needed. */
-
+
if (frame_pointer_needed)
{
insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
}
/* Set up got pointer, if needed. */
-
+
if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
- s390_load_got (true);
+ s390_load_got(true);
+
+ if (TARGET_TPF)
+ {
+ /* Generate a BAS instruction to serve as a function
+ entry intercept to facilitate the use of tracing
+ algorithms located at the branch target.
+
+ This must use register 1. */
+ rtx addr;
+ rtx unkn;
+ rtx link;
+
+ addr = GEN_INT (0xfe0);
+ unkn = CONST0_RTX (SImode);
+ link = gen_rtx_REG (Pmode, 1);
+
+ emit_call_insn (gen_call_exp (gen_rtx_MEM (QImode, addr), unkn, link));
+
+ /* Emit a blockage here so that all code
+ lies between the profiling mechanisms. */
+ emit_insn (gen_blockage ());
+ }
}
/* Expand the epilogue into a bunch of separate insns. */
int area_bottom, area_top, offset = 0;
rtvec p;
+ if (TARGET_TPF)
+ {
+
+ /* Generate a BAS instruction to serve as a function
+ entry intercept to facilitate the use of tracing
+ algorithms located at the branch target.
+
+ This must use register 1. */
+
+ rtx addr;
+ rtx unkn;
+ rtx link;
+
+ addr = GEN_INT (0xfe6);
+ unkn = CONST0_RTX (SImode);
+ link = gen_rtx_REG (Pmode, 1);
+
+ /* Emit a blockage here so that all code
+ lies between the profiling mechanisms. */
+ emit_insn (gen_blockage ());
+
+ emit_call_insn (gen_call_exp (gen_rtx_MEM (QImode, addr), unkn, link));
+ }
+
/* Check whether to use frame or stack pointer for restore. */
- frame_pointer = frame_pointer_needed ?
+ frame_pointer = frame_pointer_needed ?
hard_frame_pointer_rtx : stack_pointer_rtx;
/* Compute which parts of the save area we need to access. */
}
}
- /* Check whether we can access the register save area.
+ /* Check whether we can access the register save area.
If not, increment the frame pointer as required. */
if (area_top <= area_bottom)
{
rtx insn, frame_off;
- offset = area_bottom < 0 ? -area_bottom : 0;
+ offset = area_bottom < 0 ? -area_bottom : 0;
frame_off = GEN_INT (cfun->machine->frame_size - offset);
if (DISP_IN_RANGE (INTVAL (frame_off)))
{
- insn = gen_rtx_SET (VOIDmode, frame_pointer,
+ insn = gen_rtx_SET (VOIDmode, frame_pointer,
gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
insn = emit_insn (insn);
}
if (cfun->machine->save_fprs_p)
for (i = 24; i < 32; i++)
if (regs_ever_live[i] && !global_regs[i])
- restore_fpr (frame_pointer,
+ restore_fpr (frame_pointer,
offset - 64 + (i-24) * 8, i);
}
else
/* Return register. */
- return_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
+ return_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
/* Restore call saved gprs. */
rtx insn, addr;
int i;
- /* Check for global register and save them
+ /* Check for global register and save them
to stack location from where they get restored. */
- for (i = cfun->machine->first_restore_gpr;
+ for (i = cfun->machine->first_restore_gpr;
i <= cfun->machine->last_save_gpr;
i++)
{
- /* These registers are special and need to be
+ /* These registers are special and need to be
restored in any case. */
- if (i == STACK_POINTER_REGNUM
+ if (i == STACK_POINTER_REGNUM
|| i == RETURN_REGNUM
- || i == BASE_REGISTER
+ || i == BASE_REGISTER
|| (flag_pic && i == (int)PIC_OFFSET_TABLE_REGNUM))
continue;
if (global_regs[i])
{
- addr = plus_constant (frame_pointer,
+ addr = plus_constant (frame_pointer,
offset + i * UNITS_PER_WORD);
addr = gen_rtx_MEM (Pmode, addr);
set_mem_alias_set (addr, s390_sr_alias_set);
emit_move_insn (addr, gen_rtx_REG (Pmode, i));
- }
+ }
}
/* Fetch return address from stack before load multiple,
if (!return_regnum)
return_regnum = 4;
return_reg = gen_rtx_REG (Pmode, return_regnum);
-
- addr = plus_constant (frame_pointer,
- offset + RETURN_REGNUM * UNITS_PER_WORD);
+
+ addr = plus_constant (frame_pointer,
+ offset + RETURN_REGNUM * UNITS_PER_WORD);
addr = gen_rtx_MEM (Pmode, addr);
set_mem_alias_set (addr, s390_sr_alias_set);
emit_move_insn (return_reg, addr);
explicit in insn RTX code, we have to add a barrier here
to prevent incorrect scheduling. */
- emit_insn (gen_blockage());
+ emit_insn (gen_blockage());
- insn = restore_gprs (frame_pointer, offset,
- cfun->machine->first_restore_gpr,
+ insn = restore_gprs (frame_pointer, offset,
+ cfun->machine->first_restore_gpr,
cfun->machine->last_save_gpr);
emit_insn (insn);
}
/* Return to caller. */
p = rtvec_alloc (2);
-
+
RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, return_reg);
emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
}
-/* Return the size in bytes of a function argument of
+/* Return the size in bytes of a function argument of
type TYPE and/or mode MODE. At least one of TYPE or
MODE must be specified. */
if (TREE_CODE (type) == COMPLEX_TYPE)
return 1;
}
-
+
return 0;
}
CUM is a variable of type CUMULATIVE_ARGS which gives info about
the preceding args and about the function being called.
NAMED is nonzero if this argument is a named parameter
- (otherwise it is an extra parameter matching an ellipsis).
+ (otherwise it is an extra parameter matching an ellipsis).
On S/390, we use general purpose registers 2 through 6 to
pass integer, pointer, and certain structure arguments, and
long __fpr;
void *__overflow_arg_area;
void *__reg_save_area;
-
+
} va_list[1];
where __gpr and __fpr hold the number of general purpose
or floating point arguments used up to now, respectively,
- __overflow_arg_area points to the stack location of the
+ __overflow_arg_area points to the stack location of the
next argument passed on the stack, and __reg_save_area
always points to the start of the register area in the
call frame of the current function. The function prologue
type_decl =
build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
- f_gpr = build_decl (FIELD_DECL, get_identifier ("__gpr"),
+ f_gpr = build_decl (FIELD_DECL, get_identifier ("__gpr"),
long_integer_type_node);
- f_fpr = build_decl (FIELD_DECL, get_identifier ("__fpr"),
+ f_fpr = build_decl (FIELD_DECL, get_identifier ("__fpr"),
long_integer_type_node);
f_ovf = build_decl (FIELD_DECL, get_identifier ("__overflow_arg_area"),
ptr_type_node);
expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
}
-/* Implement va_arg by updating the va_list structure
+/* Implement va_arg by updating the va_list structure
VALIST as required to retrieve an argument of type
- TYPE, and returning that argument.
-
+ TYPE, and returning that argument.
+
Generates code equivalent to:
-
+
if (integral value) {
if (size <= 4 && args.gpr < 5 ||
- size > 4 && args.gpr < 4 )
+ size > 4 && args.gpr < 4 )
ret = args.reg_save_area[args.gpr+8]
else
ret = *args.overflow_arg_area++;
reg = gpr;
n_reg = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
sav_ofs = 2 * UNITS_PER_WORD;
+
if (size < UNITS_PER_WORD)
sav_ofs += UNITS_PER_WORD - size;
emit_label (lab_over);
- /* If less than max_regs a registers are retrieved out
+ /* If less than max_regs a registers are retrieved out
of register save area, increment. */
- u = build (PREINCREMENT_EXPR, TREE_TYPE (reg), reg,
+ u = build (PREINCREMENT_EXPR, TREE_TYPE (reg), reg,
build_int_2 (n_reg, 0));
TREE_SIDE_EFFECTS (u) = 1;
expand_expr (u, const0_rtx, VOIDmode, EXPAND_NORMAL);
{
#define MAX_ARGS 2
- unsigned int const *code_for_builtin =
+ unsigned int const *code_for_builtin =
TARGET_64BIT ? code_for_builtin_64 : code_for_builtin_31;
tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
rtx fnaddr;
rtx cxt;
{
- emit_move_insn (gen_rtx
+ emit_move_insn (gen_rtx
(MEM, Pmode,
- memory_address (Pmode,
+ memory_address (Pmode,
plus_constant (addr, (TARGET_64BIT ? 20 : 12) ))), cxt);
emit_move_insn (gen_rtx
(MEM, Pmode,
- memory_address (Pmode,
+ memory_address (Pmode,
plus_constant (addr, (TARGET_64BIT ? 28 : 16) ))), fnaddr);
}
val = (HOST_WIDE_INT)high;
val <<= 32;
val |= (HOST_WIDE_INT)low;
-
+
return GEN_INT (val);
#else
#if HOST_BITS_PER_WIDE_INT >= 32
abort ();
#endif
#endif
-}
+}
/* Output assembler code to FILE to increment profiler label # LABELNO
for profiling a function entry. */
/* If a variable has a forced alignment to < 2 bytes, mark it with
SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL operand. */
- if (TREE_CODE (decl) == VAR_DECL
+ if (TREE_CODE (decl) == VAR_DECL
&& DECL_USER_ALIGN (decl) && DECL_ALIGN (decl) < 16)
SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_ALIGN1;
}
/* Output thunk to FILE that implements a C++ virtual function call (with
- multiple inheritance) to FUNCTION. The thunk adjusts the this pointer
+ multiple inheritance) to FUNCTION. The thunk adjusts the this pointer
by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment
stored at VCALL_OFFSET in the vtable whose address is located at offset 0
relative to the resulting this pointer. */
if (TARGET_64BIT)
{
/* Setup literal pool pointer if required. */
- if ((!DISP_IN_RANGE (delta)
+ if ((!DISP_IN_RANGE (delta)
&& !CONST_OK_FOR_LETTER_P (delta, 'K'))
- || (!DISP_IN_RANGE (vcall_offset)
+ || (!DISP_IN_RANGE (vcall_offset)
&& !CONST_OK_FOR_LETTER_P (vcall_offset, 'K')))
{
op[5] = gen_label_rtx ();
output_asm_insn ("ag\t%1,0(%4)", op);
}
}
-
+
/* Jump to target. */
output_asm_insn ("jg\t%0", op);
}
}
+bool
+s390_valid_pointer_mode (mode)
+ enum machine_mode mode;
+{
+ return (mode == SImode || (TARGET_64BIT && mode == DImode));
+}
+
/* How to allocate a 'struct machine_function'. */
static struct machine_function *
fmuld,fmuls,fdivd,fdivs,
ftoi,itof,fsqrtd,fsqrts,
other,o2,o3"
- (const_string "integer"))
+ (const_string "integer"))
;; Operand type. Used to default length attribute values
(eq_attr "op_type" "SIY") (const_string "agen")]
(const_string "reg")))
-;; Generic pipeline function unit.
+;; Generic pipeline function unit.
(define_function_unit "integer" 1 0
(eq_attr "type" "none") 0 0)
; CCU: Equal ULess UGreater -- (CL, CLR, CLI, CLM)
; CCS: Equal SLess SGreater -- (C, CR, CH, CHI, ICM)
; CCT: Zero Mixed Mixed Ones (TM, TMH, TML)
-
+
; CCZ -> CCL / CCZ1
; CCZ1 -> CCA/CCU/CCS/CCT
; CCS -> CCA
-
+
; String: CLC, CLCL, CLCLE, CLST, CUSE, MVCL, MVCLE, MVPG, MVST, SRST
; Clobber: CKSM, CFC, CS, CDS, CUUTF, CUTFU, PLO, SPM, STCK, STCKE, TS, TRT, TRE, UPT
(match_operand:DI 2 "const_int_operand" "n"))
(const_int 0)))]
"s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
- && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
+ && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
&& INTVAL (operands[1]) + INTVAL (operands[2]) <= 64
&& (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4
== INTVAL (operands[2]) >> 4"
(match_operand:SI 2 "const_int_operand" "n"))
(const_int 0)))]
"s390_match_ccmode(insn, CCTmode)
- && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
+ && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
&& INTVAL (operands[1]) + INTVAL (operands[2]) <= 32
&& (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4
== INTVAL (operands[2]) >> 4"
(match_operand:SI 2 "const_int_operand" "n,n"))
(const_int 0)))]
"s390_match_ccmode(insn, CCTmode)
- && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
+ && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
&& INTVAL (operands[1]) + INTVAL (operands[2]) <= 8"
"*
{
int part = s390_single_qi (operands[1], DImode, 0);
operands[1] = GEN_INT (s390_extract_qi (operands[1], DImode, part));
- operands[0] = gen_rtx_MEM (QImode,
+ operands[0] = gen_rtx_MEM (QImode,
plus_constant (XEXP (operands[0], 0), part));
return which_alternative == 0 ? \"tm\\t%0,%b1\" : \"tmy\\t%0,%b1\";
}"
int part = s390_single_qi (operands[1], SImode, 0);
operands[1] = GEN_INT (s390_extract_qi (operands[1], SImode, part));
- operands[0] = gen_rtx_MEM (QImode,
+ operands[0] = gen_rtx_MEM (QImode,
plus_constant (XEXP (operands[0], 0), part));
return which_alternative == 0 ? \"tm\\t%0,%b1\" : \"tmy\\t%0,%b1\";
}"
int part = s390_single_qi (operands[1], HImode, 0);
operands[1] = GEN_INT (s390_extract_qi (operands[1], HImode, part));
- operands[0] = gen_rtx_MEM (QImode,
+ operands[0] = gen_rtx_MEM (QImode,
plus_constant (XEXP (operands[0], 0), part));
return which_alternative == 0 ? \"tm\\t%0,%b1\" : \"tmy\\t%0,%b1\";
}"
cghi\\t%0,%c1
cg\\t%0,%1"
[(set_attr "op_type" "RRE,RI,RXY")])
-
+
(define_insn "*cmpsi_ccs_sign"
[(set (reg 33)
(compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T"))
c\\t%0,%1
cy\\t%0,%1"
[(set_attr "op_type" "RR,RI,RX,RXY")])
-
+
; Compare (unsigned) instructions
/* During and after reload, we need to force constants
to the literal pool ourselves, if necessary. */
if ((reload_in_progress || reload_completed)
- && CONSTANT_P (operands[1])
+ && CONSTANT_P (operands[1])
&& (!legitimate_reload_constant_p (operands[1])
|| FP_REG_P (operands[0])))
operands[1] = force_const_mem (DImode, operands[1]);
(define_insn "*movdi_lay"
[(set (match_operand:DI 0 "register_operand" "=d")
(match_operand:DI 1 "address_operand" "p"))]
- "TARGET_64BIT
+ "TARGET_64BIT
&& TARGET_LONG_DISPLACEMENT
&& GET_CODE (operands[1]) == CONST_INT
&& !FP_REG_P (operands[0])"
if (!TARGET_64BIT && SYMBOLIC_CONST (operands[1]))
emit_symbolic_move (operands);
- /* expr.c tries to load an effective address using
- force_reg. This fails because we don't have a
+ /* expr.c tries to load an effective address using
+ force_reg. This fails because we don't have a
generic load_address pattern. Convert the move
to a proper arithmetic operation instead, unless
it is guaranteed to be OK. */
/* During and after reload, we need to force constants
to the literal pool ourselves, if necessary. */
if ((reload_in_progress || reload_completed)
- && CONSTANT_P (operands[1])
+ && CONSTANT_P (operands[1])
&& (!legitimate_reload_constant_p (operands[1])
|| FP_REG_P (operands[0])))
operands[1] = force_const_mem (SImode, operands[1]);
(set_attr "type" "lm")])
;
-; store multiple pattern(s).
+; store multiple pattern(s).
;
(define_expand "store_multiple"
if (to == frame_pointer_rtx || to == arg_pointer_rtx)
FAIL;
}
- else
+ else
{
to = force_reg (Pmode, XEXP (operands[0], 0));
off = 0;
(use (match_operand:DI 3 "general_operand" ""))
(use (match_operand:DI 4 "" ""))]
"TARGET_64BIT"
- "s390_expand_cmpmem (operands[0], operands[1],
+ "s390_expand_cmpmem (operands[0], operands[1],
operands[2], operands[3]); DONE;")
(define_expand "cmpmemsi"
(use (match_operand:SI 3 "general_operand" ""))
(use (match_operand:SI 4 "" ""))]
""
- "s390_expand_cmpmem (operands[0], operands[1],
+ "s390_expand_cmpmem (operands[0], operands[1],
operands[2], operands[3]); DONE;")
; Compare a block that is up to 256 bytes in length.
{
operands[1] = gen_lowpart (DImode, operands[1]);
emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48)));
- emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (48)));
+ emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (48)));
DONE;
}
}
{
operands[1] = gen_lowpart (DImode, operands[1]);
emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
- emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (56)));
+ emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (56)));
DONE;
}
}
{
operands[1] = gen_lowpart (SImode, operands[1]);
emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (16)));
- emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (16)));
+ emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (16)));
DONE;
}
")
{
operands[1] = gen_lowpart (SImode, operands[1]);
emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (24)));
- emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (24)));
+ emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (24)));
DONE;
}
")
{
operands[1] = gen_lowpart (DImode, operands[1]);
emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48)));
- emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (48)));
+ emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (48)));
DONE;
}
}
{
operands[1] = gen_lowpart (DImode, operands[1]);
emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
- emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (56)));
+ emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (56)));
DONE;
}
}
(clobber (reg:CC 33))])]
"operands[2] = gen_lowpart (HImode, operands[0]);"
[(set_attr "atype" "agen")])
-
+
;
; zero_extendqisi2 instruction pattern(s).
;
(set (strict_low_part (match_dup 2)) (match_dup 1))]
"operands[2] = gen_lowpart (QImode, operands[0]);"
[(set_attr "atype" "agen")])
-
+
;
; zero_extendqihi2 instruction pattern(s).
;
rtx temp = gen_reg_rtx (DFmode);
operands[1] = force_reg (DFmode, operands[1]);
- emit_insn (gen_cmpdf (operands[1],
+ emit_insn (gen_cmpdf (operands[1],
CONST_DOUBLE_FROM_REAL_VALUE (
REAL_VALUE_ATOF (\"9223372036854775808.0\", DFmode), DFmode)));
emit_jump_insn (gen_blt (label1));
rtx temp = gen_reg_rtx (DFmode);
operands[1] = force_reg (DFmode,operands[1]);
- emit_insn (gen_cmpdf (operands[1],
+ emit_insn (gen_cmpdf (operands[1],
CONST_DOUBLE_FROM_REAL_VALUE (
REAL_VALUE_ATOF (\"2147483648.0\", DFmode), DFmode)));
emit_jump_insn (gen_blt (label1));
"TARGET_HARD_FLOAT"
"
{
- if (TARGET_IBM_FLOAT)
+ if (TARGET_IBM_FLOAT)
{
/* This is the algorithm from POP chapter A.5.7.2. */
rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000);
operands[1] = force_reg (DFmode, operands[1]);
- emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1],
+ emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1],
two31r, two32, temp));
- }
- else
+ }
+ else
{
operands[1] = force_reg (DFmode, operands[1]);
emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
rtx temp = gen_reg_rtx (SFmode);
operands[1] = force_reg (SFmode, operands[1]);
- emit_insn (gen_cmpsf (operands[1],
+ emit_insn (gen_cmpsf (operands[1],
CONST_DOUBLE_FROM_REAL_VALUE (
REAL_VALUE_ATOF (\"9223372036854775808.0\", SFmode), SFmode)));
emit_jump_insn (gen_blt (label1));
"TARGET_HARD_FLOAT"
"
{
- if (TARGET_IBM_FLOAT)
+ if (TARGET_IBM_FLOAT)
{
/* This is the algorithm from POP chapter A.5.7.1. */
rtx temp = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD);
- rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000);
+ rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000);
emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp));
DONE;
[(set_attr "op_type" "NN,NN")
(set_attr "atype" "reg,agen")
(set_attr "length" "4,6")
- (set_attr "type" "o2,o2")])
+ (set_attr "type" "o2,o2")])
;;
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_zero_cc"
- [(set (reg 33)
+ [(set (reg 33)
(compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
(match_operand:DI 1 "register_operand" "0,0"))
(const_int 0)))
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_zero_cconly"
- [(set (reg 33)
+ [(set (reg 33)
(compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
(match_operand:DI 1 "register_operand" "0,0"))
(const_int 0)))
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_imm_cc"
- [(set (reg 33)
+ [(set (reg 33)
(compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0")
(match_operand:DI 2 "const_int_operand" "K"))
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d")
(plus:DI (match_dup 1) (match_dup 2)))]
- "TARGET_64BIT
- && s390_match_ccmode (insn, CCAmode)
+ "TARGET_64BIT
+ && s390_match_ccmode (insn, CCAmode)
&& CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
"aghi\\t%0,%h2"
[(set_attr "op_type" "RI")])
(define_insn "*adddi3_cc"
- [(set (reg 33)
+ [(set (reg 33)
(compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
(match_operand:DI 2 "general_operand" "d,m"))
(const_int 0)))
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_cconly"
- [(set (reg 33)
+ [(set (reg 33)
(compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
(match_operand:DI 2 "general_operand" "d,m"))
(const_int 0)))
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*adddi3_cconly2"
- [(set (reg 33)
+ [(set (reg 33)
(compare (match_operand:DI 1 "nonimmediate_operand" "%0,0")
(neg:SI (match_operand:DI 2 "general_operand" "d,m"))))
(clobber (match_scratch:DI 0 "=d,d"))]
DONE;
}")
-
+
;
; addsi3 instruction pattern(s).
;
(define_insn "*addsi3_imm_cc"
- [(set (reg 33)
+ [(set (reg 33)
(compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0")
(match_operand:SI 2 "const_int_operand" "K"))
(const_int 0)))
[(set_attr "op_type" "RI")])
(define_insn "*addsi3_carry1_cc"
- [(set (reg 33)
+ [(set (reg 33)
(compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:SI 2 "general_operand" "d,R,T"))
(match_dup 1)))
(set (match_operand:SI 0 "register_operand" "=d,d,d")
(plus:SI (match_dup 1) (match_dup 2)))]
- "s390_match_ccmode (insn, CCL1mode)"
+ "s390_match_ccmode (insn, CCL1mode)"
"@
alr\\t%0,%2
al\\t%0,%2
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*addsi3_carry1_cconly"
- [(set (reg 33)
+ [(set (reg 33)
(compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:SI 2 "general_operand" "d,R,T"))
(match_dup 1)))
(clobber (match_scratch:SI 0 "=d,d,d"))]
- "s390_match_ccmode (insn, CCL1mode)"
+ "s390_match_ccmode (insn, CCL1mode)"
"@
alr\\t%0,%2
al\\t%0,%2
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*addsi3_carry2_cc"
- [(set (reg 33)
+ [(set (reg 33)
(compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:SI 2 "general_operand" "d,R,T"))
(match_dup 2)))
(set (match_operand:SI 0 "register_operand" "=d,d,d")
(plus:SI (match_dup 1) (match_dup 2)))]
- "s390_match_ccmode (insn, CCL1mode)"
+ "s390_match_ccmode (insn, CCL1mode)"
"@
alr\\t%0,%2
al\\t%0,%2
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*addsi3_carry2_cconly"
- [(set (reg 33)
+ [(set (reg 33)
(compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:SI 2 "general_operand" "d,R,T"))
(match_dup 2)))
(clobber (match_scratch:SI 0 "=d,d,d"))]
- "s390_match_ccmode (insn, CCL1mode)"
+ "s390_match_ccmode (insn, CCL1mode)"
"@
alr\\t%0,%2
al\\t%0,%2
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*addsi3_cc"
- [(set (reg 33)
+ [(set (reg 33)
(compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0)))
(set (match_operand:SI 0 "register_operand" "=d,d,d")
(plus:SI (match_dup 1) (match_dup 2)))]
- "s390_match_ccmode (insn, CCLmode)"
+ "s390_match_ccmode (insn, CCLmode)"
"@
alr\\t%0,%2
al\\t%0,%2
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*addsi3_cconly"
- [(set (reg 33)
+ [(set (reg 33)
(compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
(match_operand:SI 2 "general_operand" "d,R,T"))
(const_int 0)))
(clobber (match_scratch:SI 0 "=d,d,d"))]
- "s390_match_ccmode (insn, CCLmode)"
+ "s390_match_ccmode (insn, CCLmode)"
"@
alr\\t%0,%2
al\\t%0,%2
[(set_attr "op_type" "RR,RX,RXY")])
(define_insn "*addsi3_cconly2"
- [(set (reg 33)
+ [(set (reg 33)
(compare (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
(neg:SI (match_operand:SI 2 "general_operand" "d,R,T"))))
(clobber (match_scratch:SI 0 "=d,d,d"))]
"!TARGET_64BIT"
"#"
"&& reload_completed"
- [(set (match_dup 0)
+ [(set (match_dup 0)
(and:SI (match_dup 1) (const_int 2147483647)))]
""
[(set_attr "op_type" "RX")
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_zero_cc"
- [(set (reg 33)
+ [(set (reg 33)
(compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
(zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
(const_int 0)))
[(set_attr "op_type" "RRE,RXY")])
(define_insn "*subdi3_zero_cconly"
- [(set (reg 33)
+ [(set (reg 33)
(compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
(zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
(const_int 0)))
insn = emit_insn (gen_mulsi_6432 (operands[0], operands[0], operands[2]));
REG_NOTES (insn) =
- gen_rtx_EXPR_LIST (REG_EQUAL,
- gen_rtx_MULT (DImode,
+ gen_rtx_EXPR_LIST (REG_EQUAL,
+ gen_rtx_MULT (DImode,
gen_rtx_SIGN_EXTEND (DImode, operands[1]),
gen_rtx_SIGN_EXTEND (DImode, operands[2])),
REG_NOTES (insn));
DONE;
}")
-
+
(define_insn "mulsi_6432"
[(set (match_operand:DI 0 "register_operand" "=d,d")
- (mult:DI (sign_extend:DI
+ (mult:DI (sign_extend:DI
(truncate:SI (match_operand:DI 1 "register_operand" "0,0")))
(sign_extend:DI
(match_operand:SI 2 "nonimmediate_operand" "d,R"))))]
m\\t%0,%2"
[(set_attr "op_type" "RR,RX")
(set_attr "type" "imul")])
-
+
;
; muldf3 instruction pattern(s).
;
(match_operand:DI 2 "general_operand" "d,m")))
(ashift:TI
(zero_extend:TI
- (mod:DI (truncate:DI (match_dup 1))
+ (mod:DI (truncate:DI (match_dup 1))
(match_dup 2)))
(const_int 64))))]
"TARGET_64BIT"
(sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
(ashift:TI
(zero_extend:TI
- (mod:DI (truncate:DI (match_dup 1))
+ (mod:DI (truncate:DI (match_dup 1))
(sign_extend:DI (match_dup 2))))
(const_int 64))))]
"TARGET_64BIT"
(define_insn "udivmodtidi3"
[(set (match_operand:TI 0 "register_operand" "=d,d")
- (ior:TI (zero_extend:TI
+ (ior:TI (zero_extend:TI
(truncate:DI
(udiv:TI (match_operand:TI 1 "register_operand" "0,0")
(zero_extend:TI
(ior:DI (zero_extend:DI
(truncate:SI
(div:DI (match_operand:DI 1 "register_operand" "0,0")
- (sign_extend:DI
+ (sign_extend:DI
(match_operand:SI 2 "nonimmediate_operand" "d,R")))))
(ashift:DI
(zero_extend:DI
}
else
{
- operands[2] = force_reg (SImode, operands[2]);
- operands[2] = make_safe_from (operands[2], operands[0]);
+ operands[2] = force_reg (SImode, operands[2]);
+ operands[2] = make_safe_from (operands[2], operands[0]);
emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
operands[2]));
REG_NOTES (insn) =
gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
-
- insn = emit_move_insn (operands[0],
+
+ insn = emit_move_insn (operands[0],
gen_lowpart (SImode, operands[3]));
REG_NOTES (insn) =
- gen_rtx_EXPR_LIST (REG_EQUAL,
+ gen_rtx_EXPR_LIST (REG_EQUAL,
udiv_equal, REG_NOTES (insn));
}
}
else
- {
+ {
rtx label1 = gen_label_rtx ();
rtx label2 = gen_label_rtx ();
rtx label3 = gen_label_rtx ();
- operands[1] = force_reg (SImode, operands[1]);
- operands[1] = make_safe_from (operands[1], operands[0]);
- operands[2] = force_reg (SImode, operands[2]);
- operands[2] = make_safe_from (operands[2], operands[0]);
+ operands[1] = force_reg (SImode, operands[1]);
+ operands[1] = make_safe_from (operands[1], operands[0]);
+ operands[2] = force_reg (SImode, operands[2]);
+ operands[2] = make_safe_from (operands[2], operands[0]);
emit_move_insn (operands[0], const0_rtx);
emit_insn (gen_cmpsi (operands[2], operands[1]));
operands[2]));
REG_NOTES (insn) =
gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
-
- insn = emit_move_insn (operands[0],
+
+ insn = emit_move_insn (operands[0],
gen_lowpart (SImode, operands[3]));
REG_NOTES (insn) =
- gen_rtx_EXPR_LIST (REG_EQUAL,
+ gen_rtx_EXPR_LIST (REG_EQUAL,
udiv_equal, REG_NOTES (insn));
emit_jump (label3);
emit_label (label1);
emit_move_insn (operands[0], const1_rtx);
emit_label (label3);
}
- emit_move_insn (operands[0], operands[0]);
+ emit_move_insn (operands[0], operands[0]);
DONE;
}")
}
else
{
- operands[2] = force_reg (SImode, operands[2]);
- operands[2] = make_safe_from (operands[2], operands[0]);
+ operands[2] = force_reg (SImode, operands[2]);
+ operands[2] = make_safe_from (operands[2], operands[0]);
emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
operands[2]));
REG_NOTES (insn) =
gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
-
- insn = emit_move_insn (operands[0],
+
+ insn = emit_move_insn (operands[0],
gen_highpart (SImode, operands[3]));
REG_NOTES (insn) =
- gen_rtx_EXPR_LIST (REG_EQUAL,
+ gen_rtx_EXPR_LIST (REG_EQUAL,
umod_equal, REG_NOTES (insn));
}
}
rtx label2 = gen_label_rtx ();
rtx label3 = gen_label_rtx ();
- operands[1] = force_reg (SImode, operands[1]);
- operands[1] = make_safe_from (operands[1], operands[0]);
- operands[2] = force_reg (SImode, operands[2]);
- operands[2] = make_safe_from (operands[2], operands[0]);
+ operands[1] = force_reg (SImode, operands[1]);
+ operands[1] = make_safe_from (operands[1], operands[0]);
+ operands[2] = force_reg (SImode, operands[2]);
+ operands[2] = make_safe_from (operands[2], operands[0]);
- emit_move_insn(operands[0], operands[1]);
+ emit_move_insn(operands[0], operands[1]);
emit_insn (gen_cmpsi (operands[2], operands[1]));
emit_jump_insn (gen_bgtu (label3));
emit_insn (gen_cmpsi (operands[2], const1_rtx));
operands[2]));
REG_NOTES (insn) =
gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
-
- insn = emit_move_insn (operands[0],
+
+ insn = emit_move_insn (operands[0],
gen_highpart (SImode, operands[3]));
REG_NOTES (insn) =
- gen_rtx_EXPR_LIST (REG_EQUAL,
+ gen_rtx_EXPR_LIST (REG_EQUAL,
umod_equal, REG_NOTES (insn));
emit_jump (label3);
emit_label (label1);
;
; one_cmpldi2 instruction pattern(s).
;
-
+
(define_expand "one_cmpldi2"
[(parallel
[(set (match_operand:DI 0 "register_operand" "")
(clobber (reg:CC 33))])]
"TARGET_64BIT"
"")
-
+
;
; one_cmplsi2 instruction pattern(s).
;
-
+
(define_expand "one_cmplsi2"
[(parallel
[(set (match_operand:SI 0 "register_operand" "")
(clobber (reg:CC 33))])]
""
"")
-
+
;
; one_cmplhi2 instruction pattern(s).
;
-
+
(define_expand "one_cmplhi2"
[(parallel
[(set (match_operand:HI 0 "register_operand" "")
(clobber (reg:CC 33))])]
""
"")
-
+
;
; one_cmplqi2 instruction pattern(s).
;
-
+
(define_expand "one_cmplqi2"
[(parallel
[(set (match_operand:QI 0 "register_operand" "")
"!TARGET_64BIT"
"@
sldl\\t%0,%c2
- sldl\\t%0,0(%2)"
+ sldl\\t%0,0(%2)"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
"!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
"@
srda\\t%0,%c2
- srda\\t%0,0(%2)"
+ srda\\t%0,0(%2)"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
"!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
"@
srda\\t%0,%c2
- srda\\t%0,0(%2)"
+ srda\\t%0,0(%2)"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
"!TARGET_64BIT"
"@
srda\\t%0,%c2
- srda\\t%0,0(%2)"
+ srda\\t%0,0(%2)"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
-
+
(define_insn "*ashrdi3_cc_64"
[(set (reg 33)
(compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
"!TARGET_64BIT"
"@
srdl\\t%0,%c2
- srdl\\t%0,0(%2)"
+ srdl\\t%0,0(%2)"
[(set_attr "op_type" "RS,RS")
(set_attr "atype" "reg")])
(define_insn "cjump"
[(set (pc)
- (if_then_else
+ (if_then_else
(match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
(label_ref (match_operand 0 "" ""))
(pc)))]
else
return \"b%C1\\t%a0\";
}"
- [(set (attr "op_type")
+ [(set (attr "op_type")
(if_then_else (match_operand 0 "register_operand" "")
(const_string "RR") (const_string "RX")))
(set_attr "type" "branch")
[(set (pc)
(if_then_else
(match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
- (pc)
+ (pc)
(label_ref (match_operand 0 "" ""))))]
""
"*
-{
+{
if (get_attr_length (insn) == 4)
return \"j%D1\\t%l0\";
else if (TARGET_64BIT)
else
return \"b%D1\\t%a0\";
}"
- [(set (attr "op_type")
+ [(set (attr "op_type")
(if_then_else (match_operand 0 "register_operand" "")
(const_string "RR") (const_string "RX")))
(set_attr "type" "branch")
{
enum machine_mode ccmode;
- if (operands[1] != const0_rtx) FAIL;
+ if (operands[1] != const0_rtx) FAIL;
- ccmode = s390_select_ccmode (GET_CODE (operands[0]),
- s390_compare_op0, s390_compare_op1);
+ ccmode = s390_select_ccmode (GET_CODE (operands[0]),
+ s390_compare_op0, s390_compare_op1);
operands[2] = gen_rtx_REG (ccmode, 33);
operands[3] = gen_rtx_COMPARE (ccmode, s390_compare_op0, s390_compare_op1);
}")
;;
;; This is all complicated by the fact that since this is a jump insn
;; we must handle our own output reloads.
-
+
(define_expand "doloop_end"
[(use (match_operand 0 "" "")) ; loop pseudo
(use (match_operand 1 "" "")) ; iterations; zero if unknown
else
return \"bct\\t%1,%a0\";
}"
- [(set (attr "op_type")
+ [(set (attr "op_type")
(if_then_else (match_operand 0 "register_operand" "")
(const_string "RR") (const_string "RX")))
(set_attr "type" "branch")
else
return \"bctg\\t%1,%a0\";
}"
- [(set (attr "op_type")
+ [(set (attr "op_type")
(if_then_else (match_operand 0 "register_operand" "")
(const_string "RRE") (const_string "RXE")))
(set_attr "type" "branch")
else
return \"b\\t%a0\";
}"
- [(set (attr "op_type")
+ [(set (attr "op_type")
(if_then_else (match_operand 0 "register_operand" "")
(const_string "RR") (const_string "RX")))
(set_attr "type" "branch")
else
return \"b\\t%a0\";
}"
- [(set (attr "op_type")
+ [(set (attr "op_type")
(if_then_else (match_operand 0 "register_operand" "")
(const_string "RR") (const_string "RX")))
(set_attr "type" "branch")
sym = gen_rtx_CONST (Pmode, sym);
}
- /* Unless we can use the bras(l) insn, force the
+ /* Unless we can use the bras(l) insn, force the
routine address into a register. */
if (!TARGET_SMALL_EXEC && !TARGET_64BIT)
{
sym = gen_rtx_CONST (Pmode, sym);
}
- /* Unless we can use the bras(l) insn, force the
+ /* Unless we can use the bras(l) insn, force the
routine address into a register. */
if (!TARGET_SMALL_EXEC && !TARGET_64BIT)
{
sar\\t%%a0,%0
lam\\t%%a0,%%a0,%0"
[(set_attr "op_type" "RRE,RS")])
-
+
(define_insn "*tls_load_64"
[(set (match_operand:DI 0 "register_operand" "=d")
(unspec:DI [(match_operand:DI 1 "memory_operand" "m")
sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), UNSPEC_PLT);
sym = gen_rtx_CONST (Pmode, sym);
- /* Unless we can use the bras(l) insn, force the
+ /* Unless we can use the bras(l) insn, force the
routine address into a register. */
if (!TARGET_SMALL_EXEC && !TARGET_64BIT)
{
rtx stack = gen_rtx (REG, Pmode, STACK_POINTER_REGNUM);
rtx chain = gen_rtx (MEM, Pmode, stack);
rtx temp = gen_reg_rtx (Pmode);
-
+
emit_move_insn (temp, chain);
if (TARGET_64BIT)
emit_move_insn (chain, temp);
- emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
+ emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
DONE;
}")
;
(define_insn "consttable_qi"
- [(unspec_volatile [(match_operand:QI 0 "consttable_operand" "X")]
+ [(unspec_volatile [(match_operand:QI 0 "consttable_operand" "X")]
UNSPECV_POOL_QI)]
""
{
(set_attr "length" "1")])
(define_insn "consttable_hi"
- [(unspec_volatile [(match_operand:HI 0 "consttable_operand" "X")]
+ [(unspec_volatile [(match_operand:HI 0 "consttable_operand" "X")]
UNSPECV_POOL_HI)]
""
{
(set_attr "length" "2")])
(define_insn "consttable_si"
- [(unspec_volatile [(match_operand:SI 0 "consttable_operand" "X")]
+ [(unspec_volatile [(match_operand:SI 0 "consttable_operand" "X")]
UNSPECV_POOL_SI)]
""
".long\t%0"
(set_attr "length" "4")])
(define_insn "consttable_di"
- [(unspec_volatile [(match_operand:DI 0 "consttable_operand" "X")]
+ [(unspec_volatile [(match_operand:DI 0 "consttable_operand" "X")]
UNSPECV_POOL_DI)]
""
".quad\t%0"
(set_attr "length" "8")])
(define_insn "consttable_ti"
- [(unspec_volatile [(match_operand:TI 0 "consttable_operand" "X")]
+ [(unspec_volatile [(match_operand:TI 0 "consttable_operand" "X")]
UNSPECV_POOL_TI)]
""
{
(set_attr "length" "16")])
(define_insn "consttable_sf"
- [(unspec_volatile [(match_operand:SF 0 "consttable_operand" "X")]
+ [(unspec_volatile [(match_operand:SF 0 "consttable_operand" "X")]
UNSPECV_POOL_SF)]
""
{
"!TARGET_64BIT"
"br\\t%0"
[(set_attr "op_type" "RR")
- (set_attr "type" "jsr")
+ (set_attr "type" "jsr")
(set_attr "atype" "agen")])
(define_insn "*return_di"
"TARGET_64BIT"
"br\\t%0"
[(set_attr "op_type" "RR")
- (set_attr "type" "jsr")
+ (set_attr "type" "jsr")
(set_attr "atype" "agen")])
(define_insn "literal_pool_31"
[(unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL)
- (set (match_operand:SI 0 "register_operand" "=a")
- (label_ref (match_operand 1 "" "")))
+ (set (match_operand:SI 0 "register_operand" "=a")
+ (label_ref (match_operand 1 "" "")))
(use (label_ref (match_operand 2 "" "")))]
""
{
- if (s390_nr_constants)
+ if (s390_nr_constants)
{
output_asm_insn ("bras\\t%0,%2", operands);
s390_output_constant_pool (operands[1], operands[2]);
- }
+ }
else if (flag_pic)
{
/* We need the anchor label in any case. */
CODE_LABEL_NUMBER (operands[1]));
}
- return "";
+ return "";
}
[(set_attr "op_type" "NN")
(set_attr "type" "larl")])
(define_insn "literal_pool_64"
[(unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL)
- (set (match_operand:DI 0 "register_operand" "=a")
- (label_ref (match_operand 1 "" "")))
+ (set (match_operand:DI 0 "register_operand" "=a")
+ (label_ref (match_operand 1 "" "")))
(use (label_ref (match_operand 2 "" "")))]
""
{
- if (s390_nr_constants)
+ if (s390_nr_constants)
{
output_asm_insn ("larl\\t%0,%1", operands);
s390_output_constant_pool (operands[1], operands[2]);
}
- return "";
+ return "";
}
[(set_attr "op_type" "NN")
(set_attr "type" "larl")])
+
+;; Instruction definition to extend a 31-bit pointer into a 64-bit
+;; pointer. This is used for compatability.
+
+(define_expand "ptr_extend"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (match_operand:SI 1 "register_operand" "r"))]
+ ""
+ "
+{
+ /*
+ emit_insn (gen_zero_extendsidi2 (operands[0], operands[1]));
+ emit_insn (gen_anddi3 (operands[0], operands[0], GEN_INT (0x7fffffff)));
+ */
+
+ emit_insn (gen_anddi3 (operands[0],
+ gen_lowpart (DImode, operands[1]),
+ GEN_INT (0x7fffffff)));
+
+ DONE;
+}")
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