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* config/i386/sse.md (sse4_1): New mode attribute.
authoruros <uros@138bc75d-0d04-0410-961f-82ee72b054a4>
Thu, 14 Apr 2011 17:55:30 +0000 (17:55 +0000)
committeruros <uros@138bc75d-0d04-0410-961f-82ee72b054a4>
Thu, 14 Apr 2011 17:55:30 +0000 (17:55 +0000)
(<sse4_1>_blend<ssemodesuffix><avxmodesuffix>): Macroize from
avx_blend<ssemodesuffix><avxmodesuffix> and
sse4_1_blend<ssemodesuffix> using VF mode iterator.
(<sse4_1>_blendv<ssemodesuffix><avxmodesuffix>): Macroize from
avx_blendv<ssemodesuffix><avxmodesuffix> and
sse4_1_blendv<ssemodesuffix> using VF mode iterator.
(<sse4_1>_dp<ssemodesuffix><avxmodesuffix>): Macroize from
avx_dp<ssemodesuffix><avxmodesuffix> and
sse4_1_dp<ssemodesuffix> using VF mode iterator.
(sse4_1_mpsadbw): Merge with *avx_mpsadbw.
(sse4_1_packusdw): Merge with *avx_packusdw.
(sse4_1_pblendvb): Merge with *avx_pblendvb.
(sse4_1_pblendw): Merge with *avx_pblendw.
(avx_vtest<ssemodesuffix><avxmodesuffix>): Use VF mode iterator.
(<sse4_1>_round<ssemodesuffix><avxmodesuffix>): Macroize from
avx_round<ssemodesuffix>256 and sse4_1_round<ssemodesuffix> using
VF mode iterator.
(sse4_1_round<ssescalarmodesuffix>): Merge with
*avx_round<ssescalarmodesuffix>.
(aesenc): Merge with *avx_aesenc.
(aesenclast): Merge with *avx_aesenclast.
(aesdec): Merge with *avx_aesdec.
(aesdeclast): Merge with *avx_aesdeclast.
(pclmulqdq): Merge with *pclmulqdq.
* config/i386/predicates.md (reg_not_xmm0_operand_maybe_avx):
New predicate.
(nonimm_not_xmm0_operand_maybe_avx): Ditto.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@172439 138bc75d-0d04-0410-961f-82ee72b054a4

gcc/ChangeLog patch | blob | history
gcc/config/i386/predicates.md patch | blob | history
gcc/config/i386/sse.md patch | blob | history

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 97c08fc..010f781 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,34 @@
+2011-04-14  Uros Bizjak  <ubizjak@gmail.com>
+
+       * config/i386/sse.md (sse4_1): New mode attribute.
+       (<sse4_1>_blend<ssemodesuffix><avxmodesuffix>): Macroize from
+       avx_blend<ssemodesuffix><avxmodesuffix> and
+       sse4_1_blend<ssemodesuffix> using VF mode iterator.
+       (<sse4_1>_blendv<ssemodesuffix><avxmodesuffix>): Macroize from
+       avx_blendv<ssemodesuffix><avxmodesuffix> and
+       sse4_1_blendv<ssemodesuffix> using VF mode iterator.
+       (<sse4_1>_dp<ssemodesuffix><avxmodesuffix>): Macroize from
+       avx_dp<ssemodesuffix><avxmodesuffix> and
+       sse4_1_dp<ssemodesuffix> using VF mode iterator.
+       (sse4_1_mpsadbw): Merge with *avx_mpsadbw.
+       (sse4_1_packusdw): Merge with *avx_packusdw.
+       (sse4_1_pblendvb): Merge with *avx_pblendvb.
+       (sse4_1_pblendw): Merge with *avx_pblendw.
+       (avx_vtest<ssemodesuffix><avxmodesuffix>): Use VF mode iterator.
+       (<sse4_1>_round<ssemodesuffix><avxmodesuffix>): Macroize from
+       avx_round<ssemodesuffix>256 and sse4_1_round<ssemodesuffix> using
+       VF mode iterator.
+       (sse4_1_round<ssescalarmodesuffix>): Merge with
+       *avx_round<ssescalarmodesuffix>.
+       (aesenc): Merge with *avx_aesenc.
+       (aesenclast): Merge with *avx_aesenclast.
+       (aesdec): Merge with *avx_aesdec.
+       (aesdeclast): Merge with *avx_aesdeclast.
+       (pclmulqdq): Merge with *pclmulqdq.
+       * config/i386/predicates.md (reg_not_xmm0_operand_maybe_avx):
+       New predicate.
+       (nonimm_not_xmm0_operand_maybe_avx): Ditto.
+
 2011-04-14  H.J. Lu  <hongjiu.lu@intel.com>
 
        PR middle-end/48608
@@ -48,9 +79,10 @@
        (inline_summary_vec): Define.
        (inline_summary_alloc, dump_inline_summary, debug_inline_summary,
        dump_inline_summaries): New functions.
-       (estimate_function_body_sizes): Properly compute size/time of outgoing calls.
-       (compute_inline_parameters): Alloc inline_summary; do not compute size/time
-       of incomming calls.
+       (estimate_function_body_sizes): Properly compute size/time of outgoing
+       calls.
+       (compute_inline_parameters): Alloc inline_summary; do not compute
+       size/time of incomming calls.
        (estimate_edge_time): Avoid missing time summary hack.
        (inline_read_summary): Read inline summary info.
        (inline_write_summary): Write inline summary info.
@@ -133,9 +165,9 @@
        * function.c (block_chainon): Define.
 
 2011-04-14  Anatoly Sokolov  <aesok@post.ru>
-            Eric Weddington  <eric.weddington@atmel.com>
-            Georg-Johann Lay <avr@gjlay.de> 
-       
+           Eric Weddington  <eric.weddington@atmel.com>
+           Georg-Johann Lay <avr@gjlay.de>
+
        * config/avr/avr.c: ("insn-codes.h", "optabs.h", "langhooks.h"):
        New Includes
        (avr_init_builtins, avr_expand_builtin,
@@ -145,9 +177,9 @@
        (struct avr_builtin_description): New struct
        (bdesc_1arg, bdesc_2arg): New arrays describing some RTL builtins.
        (TARGET_INIT_BUILTINS, TARGET_EXPAND_BUILTIN): Define.
-       
+
        * config/avr/avr.md (UNSPEC_FMUL, UNSPEC_FMULS, UNSPEC_FMULSU,
-       UNSPECV_ENABLE_IRQS, UNSPECV_NOP, UNSPECV_SLEEP, UNSPECV_WDR, 
+       UNSPECV_ENABLE_IRQS, UNSPECV_NOP, UNSPECV_SLEEP, UNSPECV_WDR,
        UNSPECV_DELAY_CYCLES): new enumeration values
        (UNSPEC_SEI, UNSPEC_CLI): Remove enumeration values
        ("enable_interrupt"): Use UNSPECV_ENABLE_IRQS
@@ -156,14 +188,14 @@
        ("delay_cycles_1", "delay_cycles_2", "delay_cycles_3",
        "delay_cycles_4", "nopv", "sleep", "wdr", "fmul", "fmuls",
        "fmulsu"): New insns
-       
+
        * config/avr/avr-c.c: fix line endings
        (avr_cpu_cpp_builtins): New builtin defines: __BUILTIN_AVR_NOP,
        __BUILTIN_AVR_SEI, __BUILTIN_AVR_CLI, __BUILTIN_AVR_WDR,
        __BUILTIN_AVR_SLEEP, __BUILTIN_AVR_SWAP,
        __BUILTIN_AVR_DELAY_CYCLES, __BUILTIN_AVR_FMUL,
        __BUILTIN_AVR_FMULS, __BUILTIN_AVR_FMULSU.
-       
+
        * doc/extend.texi (AVR Built-in Functions): New node
        (Target Builtins): Add documentation of AVR
        built-in functions.
@@ -181,7 +213,7 @@
        * tree.c (initialize_tree_contains_struct): Mark TS_CONSTRUCTOR as
        TS_TYPED instead of TS_COMMON.
 
-2011-04-12  Uros Bizjak  <ubizjak@gmail.com>
+2011-04-13  Uros Bizjak  <ubizjak@gmail.com>
 
        * config/i386/sse.md (*sse2_uavgv16qi3): Merge with *avx_uavgv16qi3.
        (*sse2_uavgv8hi3): Merge with *avx_uavgv8hi3.
diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md
index 03ec158..32d8efd 100644 (file)
--- a/gcc/config/i386/predicates.md
+++ b/gcc/config/i386/predicates.md
@@ -106,11 +106,23 @@
   return !REG_P (op) || REGNO (op) != FIRST_SSE_REG;
 })
 
-;; As above, but allow nonimmediate operands.
+;; As above, but also allow memory operands.
 (define_predicate "nonimm_not_xmm0_operand"
   (ior (match_operand 0 "memory_operand")
        (match_operand 0 "reg_not_xmm0_operand")))
 
+;; Return true if op is not xmm0 register, but only for non-AVX targets.
+(define_predicate "reg_not_xmm0_operand_maybe_avx"
+  (if_then_else (match_test "TARGET_AVX")
+    (match_operand 0 "register_operand")
+    (match_operand 0 "reg_not_xmm0_operand")))
+
+;; As above, but also allow memory operands.
+(define_predicate "nonimm_not_xmm0_operand_maybe_avx"
+  (if_then_else (match_test "TARGET_AVX")
+    (match_operand 0 "nonimmediate_operand")
+    (match_operand 0 "nonimm_not_xmm0_operand")))
+
 ;; Return true if VALUE can be stored in a sign extended immediate field.
 (define_predicate "x86_64_immediate_operand"
   (match_code "const_int,symbol_ref,label_ref,const")
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index cea13cb..c98d464 100644 (file)
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -124,6 +124,10 @@
    (V4SF "sse") (V2DF "sse2")
    (V8SF "avx") (V4DF "avx")])
 
+(define_mode_attr sse4_1
+  [(V4SF "sse4_1") (V2DF "sse4_1")
+   (V8SF "avx") (V4DF "avx")])
+
 ;; Mapping from integer vector mode to mnemonic suffix
 (define_mode_attr ssevecsize [(V16QI "b") (V8HI "w") (V4SI "d") (V2DI "q")])
 
@@ -8124,91 +8128,60 @@
 ;;
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
-(define_insn "avx_blend<ssemodesuffix><avxmodesuffix>"
-  [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
-       (vec_merge:AVXMODEF2P
-         (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")
-         (match_operand:AVXMODEF2P 1 "register_operand" "x")
-         (match_operand:SI 3 "const_0_to_<blendbits>_operand" "n")))]
-  "TARGET_AVX"
-  "vblend<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
-  [(set_attr "type" "ssemov")
-   (set_attr "prefix_extra" "1")
-   (set_attr "length_immediate" "1")
-   (set_attr "prefix" "vex")
-   (set_attr "mode" "<avxvecmode>")])
-
-(define_insn "avx_blendv<ssemodesuffix><avxmodesuffix>"
-  [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
-       (unspec:AVXMODEF2P
-         [(match_operand:AVXMODEF2P 1 "register_operand" "x")
-          (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")
-          (match_operand:AVXMODEF2P 3 "register_operand" "x")]
-         UNSPEC_BLENDV))]
-  "TARGET_AVX"
-  "vblendv<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
-  [(set_attr "type" "ssemov")
-   (set_attr "prefix_extra" "1")
-   (set_attr "length_immediate" "1")
-   (set_attr "prefix" "vex")
-   (set_attr "mode" "<avxvecmode>")])
-
-(define_insn "sse4_1_blend<ssemodesuffix>"
-  [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
-       (vec_merge:SSEMODEF2P
-         (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")
-         (match_operand:SSEMODEF2P 1 "register_operand" "0")
-         (match_operand:SI 3 "const_0_to_<blendbits>_operand" "n")))]
+(define_insn "<sse4_1>_blend<ssemodesuffix><avxmodesuffix>"
+  [(set (match_operand:VF 0 "register_operand" "=x,x")
+       (vec_merge:VF
+         (match_operand:VF 2 "nonimmediate_operand" "xm,xm")
+         (match_operand:VF 1 "register_operand" "0,x")
+         (match_operand:SI 3 "const_0_to_<blendbits>_operand" "n,n")))]
   "TARGET_SSE4_1"
-  "blend<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}"
-  [(set_attr "type" "ssemov")
-   (set_attr "prefix_data16" "1")
-   (set_attr "prefix_extra" "1")
+  "@
+   blend<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}
+   vblend<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
+  [(set_attr "isa" "noavx,avx")
+   (set_attr "type" "ssemov")
    (set_attr "length_immediate" "1")
+   (set_attr "prefix_data16" "1,*")
+   (set_attr "prefix_extra" "1")
+   (set_attr "prefix" "orig,vex")
    (set_attr "mode" "<MODE>")])
 
-(define_insn "sse4_1_blendv<ssemodesuffix>"
-  [(set (match_operand:SSEMODEF2P 0 "reg_not_xmm0_operand" "=x")
-       (unspec:SSEMODEF2P
-         [(match_operand:SSEMODEF2P 1 "reg_not_xmm0_operand" "0")
-          (match_operand:SSEMODEF2P 2 "nonimm_not_xmm0_operand" "xm")
-          (match_operand:SSEMODEF2P 3 "register_operand" "Yz")]
+(define_insn "<sse4_1>_blendv<ssemodesuffix><avxmodesuffix>"
+  [(set (match_operand:VF 0 "reg_not_xmm0_operand_maybe_avx" "=x,x")
+       (unspec:VF
+         [(match_operand:VF 1 "reg_not_xmm0_operand_maybe_avx" "0,x")
+          (match_operand:VF 2 "nonimm_not_xmm0_operand_maybe_avx" "xm,xm")
+          (match_operand:VF 3 "register_operand" "Yz,x")]
          UNSPEC_BLENDV))]
   "TARGET_SSE4_1"
-  "blendv<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}"
-  [(set_attr "type" "ssemov")
-   (set_attr "prefix_data16" "1")
+  "@
+   blendv<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}
+   vblendv<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
+  [(set_attr "isa" "noavx,avx")
+   (set_attr "type" "ssemov")
+   (set_attr "length_immediate" "1")
+   (set_attr "prefix_data16" "1,*")
    (set_attr "prefix_extra" "1")
+   (set_attr "prefix" "orig,vex")
    (set_attr "mode" "<MODE>")])
 
-(define_insn "avx_dp<ssemodesuffix><avxmodesuffix>"
-  [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
-       (unspec:AVXMODEF2P
-         [(match_operand:AVXMODEF2P 1 "nonimmediate_operand" "%x")
-          (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")
-          (match_operand:SI 3 "const_0_to_255_operand" "n")]
-         UNSPEC_DP))]
-  "TARGET_AVX"
-  "vdp<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
-  [(set_attr "type" "ssemul")
-   (set_attr "prefix" "vex")
-   (set_attr "prefix_extra" "1")
-   (set_attr "length_immediate" "1")
-   (set_attr "mode" "<avxvecmode>")])
-
-(define_insn "sse4_1_dp<ssemodesuffix>"
-  [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
-       (unspec:SSEMODEF2P
-         [(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "%0")
-          (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")
-          (match_operand:SI 3 "const_0_to_255_operand" "n")]
+(define_insn "<sse4_1>_dp<ssemodesuffix><avxmodesuffix>"
+  [(set (match_operand:VF 0 "register_operand" "=x,x")
+       (unspec:VF
+         [(match_operand:VF 1 "nonimmediate_operand" "%0,x")
+          (match_operand:VF 2 "nonimmediate_operand" "xm,xm")
+          (match_operand:SI 3 "const_0_to_255_operand" "n,n")]
          UNSPEC_DP))]
   "TARGET_SSE4_1"
-  "dp<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}"
-  [(set_attr "type" "ssemul")
-   (set_attr "prefix_data16" "1")
-   (set_attr "prefix_extra" "1")
+  "@
+   dp<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}
+   vdp<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
+  [(set_attr "isa" "noavx,avx")
+   (set_attr "type" "ssemul")
    (set_attr "length_immediate" "1")
+   (set_attr "prefix_data16" "1,*")
+   (set_attr "prefix_extra" "1")
+   (set_attr "prefix" "orig,vex")
    (set_attr "mode" "<MODE>")])
 
 (define_insn "sse4_1_movntdqa"
@@ -8222,111 +8195,73 @@
    (set_attr "prefix" "maybe_vex")
    (set_attr "mode" "TI")])
 
-(define_insn "*avx_mpsadbw"
-  [(set (match_operand:V16QI 0 "register_operand" "=x")
-       (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x")
-                      (match_operand:V16QI 2 "nonimmediate_operand" "xm")
-                      (match_operand:SI 3 "const_0_to_255_operand" "n")]
-                     UNSPEC_MPSADBW))]
-  "TARGET_AVX"
-  "vmpsadbw\t{%3, %2, %1, %0|%0, %1, %2, %3}"
-  [(set_attr "type" "sselog1")
-   (set_attr "prefix" "vex")
-   (set_attr "prefix_extra" "1")
-   (set_attr "length_immediate" "1")
-   (set_attr "mode" "TI")])
-
 (define_insn "sse4_1_mpsadbw"
-  [(set (match_operand:V16QI 0 "register_operand" "=x")
-       (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "0")
-                      (match_operand:V16QI 2 "nonimmediate_operand" "xm")
-                      (match_operand:SI 3 "const_0_to_255_operand" "n")]
+  [(set (match_operand:V16QI 0 "register_operand" "=x,x")
+       (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "0,x")
+                      (match_operand:V16QI 2 "nonimmediate_operand" "xm,xm")
+                      (match_operand:SI 3 "const_0_to_255_operand" "n,n")]
                      UNSPEC_MPSADBW))]
   "TARGET_SSE4_1"
-  "mpsadbw\t{%3, %2, %0|%0, %2, %3}"
-  [(set_attr "type" "sselog1")
-   (set_attr "prefix_extra" "1")
+  "@
+   mpsadbw\t{%3, %2, %0|%0, %2, %3}
+   vmpsadbw\t{%3, %2, %1, %0|%0, %1, %2, %3}"
+  [(set_attr "isa" "noavx,avx")
+   (set_attr "type" "sselog1")
    (set_attr "length_immediate" "1")
-   (set_attr "mode" "TI")])
-
-(define_insn "*avx_packusdw"
-  [(set (match_operand:V8HI 0 "register_operand" "=x")
-       (vec_concat:V8HI
-         (us_truncate:V4HI
-           (match_operand:V4SI 1 "register_operand" "x"))
-         (us_truncate:V4HI
-           (match_operand:V4SI 2 "nonimmediate_operand" "xm"))))]
-  "TARGET_AVX"
-  "vpackusdw\t{%2, %1, %0|%0, %1, %2}"
-  [(set_attr "type" "sselog")
    (set_attr "prefix_extra" "1")
-   (set_attr "prefix" "vex")
+   (set_attr "prefix" "orig,vex")
    (set_attr "mode" "TI")])
 
 (define_insn "sse4_1_packusdw"
-  [(set (match_operand:V8HI 0 "register_operand" "=x")
+  [(set (match_operand:V8HI 0 "register_operand" "=x,x")
        (vec_concat:V8HI
          (us_truncate:V4HI
-           (match_operand:V4SI 1 "register_operand" "0"))
+           (match_operand:V4SI 1 "register_operand" "0,x"))
          (us_truncate:V4HI
-           (match_operand:V4SI 2 "nonimmediate_operand" "xm"))))]
+           (match_operand:V4SI 2 "nonimmediate_operand" "xm,xm"))))]
   "TARGET_SSE4_1"
-  "packusdw\t{%2, %0|%0, %2}"
-  [(set_attr "type" "sselog")
-   (set_attr "prefix_extra" "1")
-   (set_attr "mode" "TI")])
-
-(define_insn "*avx_pblendvb"
-  [(set (match_operand:V16QI 0 "register_operand" "=x")
-       (unspec:V16QI [(match_operand:V16QI 1 "register_operand"  "x")
-                      (match_operand:V16QI 2 "nonimmediate_operand" "xm")
-                      (match_operand:V16QI 3 "register_operand" "x")]
-                     UNSPEC_BLENDV))]
-  "TARGET_AVX"
-  "vpblendvb\t{%3, %2, %1, %0|%0, %1, %2, %3}"
-  [(set_attr "type" "ssemov")
+  "@
+   packusdw\t{%2, %0|%0, %2}
+   vpackusdw\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "isa" "noavx,avx")
+   (set_attr "type" "sselog")
    (set_attr "prefix_extra" "1")
-   (set_attr "length_immediate" "1")
-   (set_attr "prefix" "vex")
+   (set_attr "prefix" "orig,vex")
    (set_attr "mode" "TI")])
 
 (define_insn "sse4_1_pblendvb"
-  [(set (match_operand:V16QI 0 "reg_not_xmm0_operand" "=x")
-       (unspec:V16QI [(match_operand:V16QI 1 "reg_not_xmm0_operand"  "0")
-                      (match_operand:V16QI 2 "nonimm_not_xmm0_operand" "xm")
-                      (match_operand:V16QI 3 "register_operand" "Yz")]
-                     UNSPEC_BLENDV))]
+  [(set (match_operand:V16QI 0 "reg_not_xmm0_operand" "=x,x")
+       (unspec:V16QI
+         [(match_operand:V16QI 1 "reg_not_xmm0_operand_maybe_avx"  "0,x")
+          (match_operand:V16QI 2 "nonimm_not_xmm0_operand_maybe_avx" "xm,xm")
+          (match_operand:V16QI 3 "register_operand" "Yz,x")]
+         UNSPEC_BLENDV))]
   "TARGET_SSE4_1"
-  "pblendvb\t{%3, %2, %0|%0, %2, %3}"
-  [(set_attr "type" "ssemov")
-   (set_attr "prefix_extra" "1")
-   (set_attr "mode" "TI")])
-
-(define_insn "*avx_pblendw"
-  [(set (match_operand:V8HI 0 "register_operand" "=x")
-       (vec_merge:V8HI
-         (match_operand:V8HI 2 "nonimmediate_operand" "xm")
-         (match_operand:V8HI 1 "register_operand" "x")
-         (match_operand:SI 3 "const_0_to_255_operand" "n")))]
-  "TARGET_AVX"
-  "vpblendw\t{%3, %2, %1, %0|%0, %1, %2, %3}"
-  [(set_attr "type" "ssemov")
-   (set_attr "prefix" "vex")
+  "@
+   pblendvb\t{%3, %2, %0|%0, %2, %3}
+   vpblendvb\t{%3, %2, %1, %0|%0, %1, %2, %3}"
+  [(set_attr "isa" "noavx,avx")
+   (set_attr "type" "ssemov")
    (set_attr "prefix_extra" "1")
-   (set_attr "length_immediate" "1")
+   (set_attr "length_immediate" "*,1")
+   (set_attr "prefix" "orig,vex")
    (set_attr "mode" "TI")])
 
 (define_insn "sse4_1_pblendw"
-  [(set (match_operand:V8HI 0 "register_operand" "=x")
+  [(set (match_operand:V8HI 0 "register_operand" "=x,x")
        (vec_merge:V8HI
-         (match_operand:V8HI 2 "nonimmediate_operand" "xm")
-         (match_operand:V8HI 1 "register_operand" "0")
-         (match_operand:SI 3 "const_0_to_255_operand" "n")))]
+         (match_operand:V8HI 2 "nonimmediate_operand" "xm,xm")
+         (match_operand:V8HI 1 "register_operand" "0,x")
+         (match_operand:SI 3 "const_0_to_255_operand" "n,n")))]
   "TARGET_SSE4_1"
-  "pblendw\t{%3, %2, %0|%0, %2, %3}"
-  [(set_attr "type" "ssemov")
+  "@
+   pblendw\t{%3, %2, %0|%0, %2, %3}
+   vpblendw\t{%3, %2, %1, %0|%0, %1, %2, %3}"
+  [(set_attr "isa" "noavx,avx")
+   (set_attr "type" "ssemov")
    (set_attr "prefix_extra" "1")
    (set_attr "length_immediate" "1")
+   (set_attr "prefix" "orig,vex")
    (set_attr "mode" "TI")])
 
 (define_insn "sse4_1_phminposuw"
@@ -8438,8 +8373,8 @@
 ;; setting FLAGS_REG. But it is not a really compare instruction.
 (define_insn "avx_vtest<ssemodesuffix><avxmodesuffix>"
   [(set (reg:CC FLAGS_REG)
-       (unspec:CC [(match_operand:AVXMODEF2P 0 "register_operand" "x")
-                   (match_operand:AVXMODEF2P 1 "nonimmediate_operand" "xm")]
+       (unspec:CC [(match_operand:VF 0 "register_operand" "x")
+                   (match_operand:VF 1 "nonimmediate_operand" "xm")]
                   UNSPEC_VTESTP))]
   "TARGET_AVX"
   "vtest<ssemodesuffix>\t{%1, %0|%0, %1}"
@@ -8474,67 +8409,44 @@
    (set_attr "prefix" "maybe_vex")
    (set_attr "mode" "TI")])
 
-(define_insn "avx_round<ssemodesuffix>256"
-  [(set (match_operand:AVX256MODEF2P 0 "register_operand" "=x")
-       (unspec:AVX256MODEF2P
-         [(match_operand:AVX256MODEF2P 1 "nonimmediate_operand" "xm")
-          (match_operand:SI 2 "const_0_to_15_operand" "n")]
-         UNSPEC_ROUND))]
-  "TARGET_AVX"
-  "vround<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
-  [(set_attr "type" "ssecvt")
-   (set_attr "prefix_extra" "1")
-   (set_attr "length_immediate" "1")
-   (set_attr "prefix" "vex")
-   (set_attr "mode" "<MODE>")])
-
-(define_insn "sse4_1_round<ssemodesuffix>"
-  [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
-       (unspec:SSEMODEF2P
-         [(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "xm")
+(define_insn "<sse4_1>_round<ssemodesuffix><avxmodesuffix>"
+  [(set (match_operand:VF 0 "register_operand" "=x")
+       (unspec:VF
+         [(match_operand:VF 1 "nonimmediate_operand" "xm")
           (match_operand:SI 2 "const_0_to_15_operand" "n")]
          UNSPEC_ROUND))]
   "TARGET_ROUND"
   "%vround<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "ssecvt")
-   (set_attr "prefix_data16" "1")
+   (set (attr "prefix_data16")
+     (if_then_else
+       (ne (symbol_ref "TARGET_AVX") (const_int 0))
+     (const_string "*")
+     (const_string "1")))
    (set_attr "prefix_extra" "1")
    (set_attr "length_immediate" "1")
    (set_attr "prefix" "maybe_vex")
    (set_attr "mode" "<MODE>")])
 
-(define_insn "*avx_round<ssescalarmodesuffix>"
-  [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
-       (vec_merge:SSEMODEF2P
-         (unspec:SSEMODEF2P
-           [(match_operand:SSEMODEF2P 2 "register_operand" "x")
-            (match_operand:SI 3 "const_0_to_15_operand" "n")]
-           UNSPEC_ROUND)
-         (match_operand:SSEMODEF2P 1 "register_operand" "x")
-         (const_int 1)))]
-  "TARGET_AVX"
-  "vround<ssescalarmodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
-  [(set_attr "type" "ssecvt")
-   (set_attr "prefix_extra" "1")
-   (set_attr "length_immediate" "1")
-   (set_attr "prefix" "vex")
-   (set_attr "mode" "<MODE>")])
-
 (define_insn "sse4_1_round<ssescalarmodesuffix>"
-  [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
-       (vec_merge:SSEMODEF2P
-         (unspec:SSEMODEF2P
-           [(match_operand:SSEMODEF2P 2 "register_operand" "x")
-            (match_operand:SI 3 "const_0_to_15_operand" "n")]
+  [(set (match_operand:VF_128 0 "register_operand" "=x,x")
+       (vec_merge:VF_128
+         (unspec:VF_128
+           [(match_operand:VF_128 2 "register_operand" "x,x")
+            (match_operand:SI 3 "const_0_to_15_operand" "n,n")]
            UNSPEC_ROUND)
-         (match_operand:SSEMODEF2P 1 "register_operand" "0")
+         (match_operand:VF_128 1 "register_operand" "0,x")
          (const_int 1)))]
   "TARGET_ROUND"
-  "round<ssescalarmodesuffix>\t{%3, %2, %0|%0, %2, %3}"
-  [(set_attr "type" "ssecvt")
-   (set_attr "prefix_data16" "1")
-   (set_attr "prefix_extra" "1")
+  "@
+   round<ssescalarmodesuffix>\t{%3, %2, %0|%0, %2, %3}
+   vround<ssescalarmodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
+  [(set_attr "isa" "noavx,avx")
+   (set_attr "type" "ssecvt")
    (set_attr "length_immediate" "1")
+   (set_attr "prefix_data16" "1,*")
+   (set_attr "prefix_extra" "1")
+   (set_attr "prefix" "orig,vex")
    (set_attr "mode" "<MODE>")])
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
@@ -10084,96 +9996,65 @@
    (set_attr "mode" "<MODE>")])
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-(define_insn "*avx_aesenc"
-  [(set (match_operand:V2DI 0 "register_operand" "=x")
-       (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x")
-                      (match_operand:V2DI 2 "nonimmediate_operand" "xm")]
-                     UNSPEC_AESENC))]
-  "TARGET_AES && TARGET_AVX"
-  "vaesenc\t{%2, %1, %0|%0, %1, %2}"
-  [(set_attr "type" "sselog1")
-   (set_attr "prefix_extra" "1")
-   (set_attr "prefix" "vex")
-   (set_attr "mode" "TI")])
 
 (define_insn "aesenc"
-  [(set (match_operand:V2DI 0 "register_operand" "=x")
-       (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
-                      (match_operand:V2DI 2 "nonimmediate_operand" "xm")]
+  [(set (match_operand:V2DI 0 "register_operand" "=x,x")
+       (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0,x")
+                      (match_operand:V2DI 2 "nonimmediate_operand" "xm,xm")]
                      UNSPEC_AESENC))]
   "TARGET_AES"
-  "aesenc\t{%2, %0|%0, %2}"
-  [(set_attr "type" "sselog1")
-   (set_attr "prefix_extra" "1")
-   (set_attr "mode" "TI")])
-
-(define_insn "*avx_aesenclast"
-  [(set (match_operand:V2DI 0 "register_operand" "=x")
-       (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x")
-                      (match_operand:V2DI 2 "nonimmediate_operand" "xm")]
-                     UNSPEC_AESENCLAST))]
-  "TARGET_AES && TARGET_AVX"
-  "vaesenclast\t{%2, %1, %0|%0, %1, %2}"
-  [(set_attr "type" "sselog1")
+  "@
+   aesenc\t{%2, %0|%0, %2}
+   vaesenc\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "isa" "noavx,avx")
+   (set_attr "type" "sselog1")
    (set_attr "prefix_extra" "1")
-   (set_attr "prefix" "vex")
+   (set_attr "prefix" "orig,vex")
    (set_attr "mode" "TI")])
 
 (define_insn "aesenclast"
-  [(set (match_operand:V2DI 0 "register_operand" "=x")
-       (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
-                      (match_operand:V2DI 2 "nonimmediate_operand" "xm")]
+  [(set (match_operand:V2DI 0 "register_operand" "=x,x")
+       (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0,x")
+                      (match_operand:V2DI 2 "nonimmediate_operand" "xm,xm")]
                      UNSPEC_AESENCLAST))]
   "TARGET_AES"
-  "aesenclast\t{%2, %0|%0, %2}"
-  [(set_attr "type" "sselog1")
-   (set_attr "prefix_extra" "1")
-   (set_attr "mode" "TI")])
-
-(define_insn "*avx_aesdec"
-  [(set (match_operand:V2DI 0 "register_operand" "=x")
-       (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x")
-                      (match_operand:V2DI 2 "nonimmediate_operand" "xm")]
-                     UNSPEC_AESDEC))]
-  "TARGET_AES && TARGET_AVX"
-  "vaesdec\t{%2, %1, %0|%0, %1, %2}"
-  [(set_attr "type" "sselog1")
+  "@
+   aesenclast\t{%2, %0|%0, %2}
+   vaesenclast\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "isa" "noavx,avx")
+   (set_attr "type" "sselog1")
    (set_attr "prefix_extra" "1")
-   (set_attr "prefix" "vex")
+   (set_attr "prefix" "orig,vex")
    (set_attr "mode" "TI")])
 
 (define_insn "aesdec"
-  [(set (match_operand:V2DI 0 "register_operand" "=x")
-       (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
-                      (match_operand:V2DI 2 "nonimmediate_operand" "xm")]
+  [(set (match_operand:V2DI 0 "register_operand" "=x,x")
+       (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0,x")
+                      (match_operand:V2DI 2 "nonimmediate_operand" "xm,xm")]
                      UNSPEC_AESDEC))]
   "TARGET_AES"
-  "aesdec\t{%2, %0|%0, %2}"
-  [(set_attr "type" "sselog1")
-   (set_attr "prefix_extra" "1")
-   (set_attr "mode" "TI")])
-
-(define_insn "*avx_aesdeclast"
-  [(set (match_operand:V2DI 0 "register_operand" "=x")
-       (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x")
-                      (match_operand:V2DI 2 "nonimmediate_operand" "xm")]
-                     UNSPEC_AESDECLAST))]
-  "TARGET_AES && TARGET_AVX"
-  "vaesdeclast\t{%2, %1, %0|%0, %1, %2}"
-  [(set_attr "type" "sselog1")
+  "@
+   aesdec\t{%2, %0|%0, %2}
+   vaesdec\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "isa" "noavx,avx")
+   (set_attr "type" "sselog1")
    (set_attr "prefix_extra" "1")
-   (set_attr "prefix" "vex")
+   (set_attr "prefix" "orig,vex")
    (set_attr "mode" "TI")])
 
 (define_insn "aesdeclast"
-  [(set (match_operand:V2DI 0 "register_operand" "=x")
-       (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
-                      (match_operand:V2DI 2 "nonimmediate_operand" "xm")]
+  [(set (match_operand:V2DI 0 "register_operand" "=x,x")
+       (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0,x")
+                      (match_operand:V2DI 2 "nonimmediate_operand" "xm,xm")]
                      UNSPEC_AESDECLAST))]
   "TARGET_AES"
-  "aesdeclast\t{%2, %0|%0, %2}"
-  [(set_attr "type" "sselog1")
+  "@
+   aesdeclast\t{%2, %0|%0, %2}
+   vaesdeclast\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "isa" "noavx,avx")
+   (set_attr "type" "sselog1")
    (set_attr "prefix_extra" "1")
+   (set_attr "prefix" "orig,vex")
    (set_attr "mode" "TI")])
 
 (define_insn "aesimc"
@@ -10200,31 +10081,21 @@
    (set_attr "prefix" "maybe_vex")
    (set_attr "mode" "TI")])
 
-(define_insn "*vpclmulqdq"
-  [(set (match_operand:V2DI 0 "register_operand" "=x")
-       (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x")
-                     (match_operand:V2DI 2 "nonimmediate_operand" "xm")
-                     (match_operand:SI 3 "const_0_to_255_operand" "n")]
-                    UNSPEC_PCLMUL))]
-  "TARGET_PCLMUL && TARGET_AVX"
-  "vpclmulqdq\t{%3, %2, %1, %0|%0, %1, %2, %3}"
-  [(set_attr "type" "sselog1")
-   (set_attr "prefix_extra" "1")
-   (set_attr "length_immediate" "1")
-   (set_attr "prefix" "vex")
-   (set_attr "mode" "TI")])
-
 (define_insn "pclmulqdq"
-  [(set (match_operand:V2DI 0 "register_operand" "=x")
-       (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
-                     (match_operand:V2DI 2 "nonimmediate_operand" "xm")
-                     (match_operand:SI 3 "const_0_to_255_operand" "n")]
+  [(set (match_operand:V2DI 0 "register_operand" "=x,x")
+       (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0,x")
+                     (match_operand:V2DI 2 "nonimmediate_operand" "xm,xm")
+                     (match_operand:SI 3 "const_0_to_255_operand" "n,n")]
                     UNSPEC_PCLMUL))]
   "TARGET_PCLMUL"
-  "pclmulqdq\t{%3, %2, %0|%0, %2, %3}"
-  [(set_attr "type" "sselog1")
+  "@
+   pclmulqdq\t{%3, %2, %0|%0, %2, %3}
+   vpclmulqdq\t{%3, %2, %1, %0|%0, %1, %2, %3}"
+  [(set_attr "isa" "noavx,avx")
+   (set_attr "type" "sselog1")
    (set_attr "prefix_extra" "1")
    (set_attr "length_immediate" "1")
+   (set_attr "prefix" "orig,vex")
    (set_attr "mode" "TI")])
 
 (define_expand "avx_vzeroall"
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