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Add smaxv2di3, umaxv2di3, sminv2di3 and uminv2di3
authorhjl <hjl@138bc75d-0d04-0410-961f-82ee72b054a4>
Tue, 5 Jan 2010 23:53:29 +0000 (23:53 +0000)
committerhjl <hjl@138bc75d-0d04-0410-961f-82ee72b054a4>
Tue, 5 Jan 2010 23:53:29 +0000 (23:53 +0000)
gcc/

2010-01-05  H.J. Lu  <hongjiu.lu@intel.com>

PR target/42542
* config/i386/sse.md (smaxv2di3): New.
(umaxv2di3): Likewise.
(sminv2di3): Likewise.
(uminv2di3): Likewise.

gcc/testsuite/

2010-01-05  H.J. Lu  <hongjiu.lu@intel.com>

PR target/42542
* gcc.target/i386/pr42542-4.c: New.
* gcc.target/i386/pr42542-4a.c: Likewise.
* gcc.target/i386/pr42542-5.c: Likewise.
* gcc.target/i386/pr42542-5a.c: Likewise.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@155666 138bc75d-0d04-0410-961f-82ee72b054a4

gcc/ChangeLog
gcc/config/i386/sse.md
gcc/testsuite/ChangeLog
gcc/testsuite/gcc.target/i386/pr42542-4.c [new file with mode: 0644]
gcc/testsuite/gcc.target/i386/pr42542-4a.c [new file with mode: 0644]
gcc/testsuite/gcc.target/i386/pr42542-5.c [new file with mode: 0644]
gcc/testsuite/gcc.target/i386/pr42542-5a.c [new file with mode: 0644]

index 40a277b..123a62a 100644 (file)
@@ -1,3 +1,11 @@
+2010-01-05  H.J. Lu  <hongjiu.lu@intel.com>
+
+       PR target/42542
+       * config/i386/sse.md (smaxv2di3): New.
+       (umaxv2di3): Likewise.
+       (sminv2di3): Likewise.
+       (uminv2di3): Likewise.
+
 2010-01-05  Eric Botcazou  <ebotcazou@adacore.com>
 
        PR target/42564
index 406dc0c..54befb4 100644 (file)
    (set_attr "prefix_extra" "1")
    (set_attr "mode" "TI")])
 
+(define_expand "smaxv2di3"
+  [(set (match_operand:V2DI 0 "register_operand" "")
+       (smax:V2DI (match_operand:V2DI 1 "register_operand" "")
+                  (match_operand:V2DI 2 "register_operand" "")))]
+  "TARGET_SSE4_2"
+{
+  rtx xops[6];
+  bool ok;
+
+  xops[0] = operands[0];
+  xops[1] = operands[1];
+  xops[2] = operands[2];
+  xops[3] = gen_rtx_GT (VOIDmode, operands[1], operands[2]);
+  xops[4] = operands[1];
+  xops[5] = operands[2];
+  ok = ix86_expand_int_vcond (xops);
+  gcc_assert (ok);
+  DONE;
+})
+
 (define_expand "umaxv4si3"
   [(set (match_operand:V4SI 0 "register_operand" "")
        (umax:V4SI (match_operand:V4SI 1 "register_operand" "")
    (set_attr "prefix_extra" "1")
    (set_attr "mode" "TI")])
 
+(define_expand "umaxv2di3"
+  [(set (match_operand:V2DI 0 "register_operand" "")
+       (umax:V2DI (match_operand:V2DI 1 "register_operand" "")
+                  (match_operand:V2DI 2 "register_operand" "")))]
+  "TARGET_SSE4_2"
+{
+  rtx xops[6];
+  bool ok;
+
+  xops[0] = operands[0];
+  xops[1] = operands[1];
+  xops[2] = operands[2];
+  xops[3] = gen_rtx_GTU (VOIDmode, operands[1], operands[2]);
+  xops[4] = operands[1];
+  xops[5] = operands[2];
+  ok = ix86_expand_int_vcond (xops);
+  gcc_assert (ok);
+  DONE;
+})
+
 (define_expand "smin<mode>3"
   [(set (match_operand:SSEMODE14 0 "register_operand" "")
        (smin:SSEMODE14 (match_operand:SSEMODE14 1 "register_operand" "")
     }
 })
 
+(define_expand "sminv2di3"
+  [(set (match_operand:V2DI 0 "register_operand" "")
+       (smin:V2DI (match_operand:V2DI 1 "register_operand" "")
+                  (match_operand:V2DI 2 "register_operand" "")))]
+  "TARGET_SSE4_2"
+{
+  rtx xops[6];
+  bool ok;
+
+  xops[0] = operands[0];
+  xops[1] = operands[2];
+  xops[2] = operands[1];
+  xops[3] = gen_rtx_GT (VOIDmode, operands[1], operands[2]);
+  xops[4] = operands[1];
+  xops[5] = operands[2];
+  ok = ix86_expand_int_vcond (xops);
+  gcc_assert (ok);
+  DONE;
+})
+
 (define_expand "umin<mode>3"
   [(set (match_operand:SSEMODE24 0 "register_operand" "")
        (umin:SSEMODE24 (match_operand:SSEMODE24 1 "register_operand" "")
     }
 })
 
+(define_expand "uminv2di3"
+  [(set (match_operand:V2DI 0 "register_operand" "")
+       (umin:V2DI (match_operand:V2DI 1 "register_operand" "")
+                  (match_operand:V2DI 2 "register_operand" "")))]
+  "TARGET_SSE4_2"
+{
+  rtx xops[6];
+  bool ok;
+
+  xops[0] = operands[0];
+  xops[1] = operands[2];
+  xops[2] = operands[1];
+  xops[3] = gen_rtx_GTU (VOIDmode, operands[1], operands[2]);
+  xops[4] = operands[1];
+  xops[5] = operands[2];
+  ok = ix86_expand_int_vcond (xops);
+  gcc_assert (ok);
+  DONE;
+})
+
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;;
 ;; Parallel integral comparisons
index 4f6aa65..e9c215d 100644 (file)
@@ -1,3 +1,11 @@
+2010-01-05  H.J. Lu  <hongjiu.lu@intel.com>
+       PR target/42542
+       * gcc.target/i386/pr42542-4.c: New.
+       * gcc.target/i386/pr42542-4a.c: Likewise.
+       * gcc.target/i386/pr42542-5.c: Likewise.
+       * gcc.target/i386/pr42542-5a.c: Likewise.
+
 2010-01-05  Eric Botcazou  <ebotcazou@adacore.com>
 
        * gcc.dg/tls/opt-15.c: New test.
diff --git a/gcc/testsuite/gcc.target/i386/pr42542-4.c b/gcc/testsuite/gcc.target/i386/pr42542-4.c
new file mode 100644 (file)
index 0000000..afb2989
--- /dev/null
@@ -0,0 +1,70 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O1 -msse4.2 -ftree-vectorize" } */
+
+#include "sse4_2-check.h"
+
+unsigned long long v1[] __attribute__ ((aligned(16))) =
+{
+  0x8000000000000000ULL, 2,
+  3, 0xd000000000000000ULL
+};
+unsigned long long v2[] __attribute__ ((aligned(16))) =
+{
+  4, 0xb000000000000000ULL,
+  0xf000000000000000ULL, 6
+};
+
+unsigned long long max[] =
+{
+  0x8000000000000000ULL, 0xb000000000000000ULL,
+  0xf000000000000000ULL, 0xd000000000000000ULL
+};
+
+unsigned long long min[] =
+{
+  4, 2,
+  3, 6
+};
+
+unsigned long long res[4] __attribute__ ((aligned(16)));
+
+extern void abort (void);
+
+void
+find_max (void)
+{
+  int i;
+
+  for (i = 0; i < 4; i++)
+    res[i] = v1[i] < v2[i] ? v2[i] : v1[i];
+}
+
+void
+find_min (void)
+{
+  int i;
+
+  for (i = 0; i < 4; i++)
+    res[i] = v1[i] > v2[i] ? v2[i] : v1[i];
+}
+
+static void
+sse4_2_test (void)
+{
+  int i;
+  int err = 0;
+
+  find_max ();
+  for (i = 0; i < 4; i++)
+    if (res[i] != max[i])
+      err++;
+
+  find_min ();
+  for (i = 0; i < 4; i++)
+    if (res[i] != min[i])
+      err++;
+
+  if (err)
+    abort ();
+}
diff --git a/gcc/testsuite/gcc.target/i386/pr42542-4a.c b/gcc/testsuite/gcc.target/i386/pr42542-4a.c
new file mode 100644 (file)
index 0000000..bea6c1f
--- /dev/null
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-O1 -msse4.2 -ftree-vectorize" } */
+
+#include "pr42542-4.c"
+
+/* { dg-final { scan-assembler "pcmpgtq" } } */
diff --git a/gcc/testsuite/gcc.target/i386/pr42542-5.c b/gcc/testsuite/gcc.target/i386/pr42542-5.c
new file mode 100644 (file)
index 0000000..7d77a18
--- /dev/null
@@ -0,0 +1,66 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O1 -msse4.2 -ftree-vectorize" } */
+
+#include "sse4_2-check.h"
+
+long long v1[] __attribute__ ((aligned(16))) =
+{
+  -3, 2, 3, -4 
+};
+long long v2[] __attribute__ ((aligned(16))) =
+{
+  4, -10, -20, 6
+};
+
+long long max[] =
+{
+  4, 2, 3, 6
+};
+
+long long min[] =
+{
+  -3, -10, -20, -4
+};
+
+long long res[4] __attribute__ ((aligned(16)));
+
+extern void abort (void);
+
+void
+find_max (void)
+{
+  int i;
+
+  for (i = 0; i < 4; i++)
+    res[i] = v1[i] < v2[i] ? v2[i] : v1[i];
+}
+
+void
+find_min (void)
+{
+  int i;
+
+  for (i = 0; i < 4; i++)
+    res[i] = v1[i] > v2[i] ? v2[i] : v1[i];
+}
+
+static void
+sse4_2_test (void)
+{
+  int i;
+  int err = 0;
+
+  find_max ();
+  for (i = 0; i < 4; i++)
+    if (res[i] != max[i])
+      err++;
+
+  find_min ();
+  for (i = 0; i < 4; i++)
+    if (res[i] != min[i])
+      err++;
+
+  if (err)
+    abort ();
+}
diff --git a/gcc/testsuite/gcc.target/i386/pr42542-5a.c b/gcc/testsuite/gcc.target/i386/pr42542-5a.c
new file mode 100644 (file)
index 0000000..bba0a11
--- /dev/null
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-O1 -msse4.2 -ftree-vectorize" } */
+
+#include "pr42542-5.c"
+
+/* { dg-final { scan-assembler "pcmpgtq" } } */