+2007-09-13 Bernd Schmidt <bernd.schmidt@analog.com>
+
+ * config/bfin/bfin.md (reload_outpdi, reload_inpdi): New patterns.
+ * config/bfin/bfin.c (bfin_secondary_reload): Make sure we use them.
+
2007-09-13 James E. Wilson <wilson@specifix.com>
PR tree-optimization/33389
scratch register. */
static enum reg_class
-bfin_secondary_reload (bool in_p ATTRIBUTE_UNUSED, rtx x, enum reg_class class,
- enum machine_mode mode, secondary_reload_info *sri)
+bfin_secondary_reload (bool in_p, rtx x, enum reg_class class,
+ enum machine_mode mode, secondary_reload_info *sri)
{
/* If we have HImode or QImode, we can only use DREGS as secondary registers;
in most other cases we can also use PREGS. */
if (class == AREGS || class == EVEN_AREGS || class == ODD_AREGS)
{
+ if (code == MEM)
+ {
+ sri->icode = in_p ? CODE_FOR_reload_inpdi : CODE_FOR_reload_outpdi;
+ return NO_REGS;
+ }
+
if (x != const0_rtx && x_class != DREGS)
- return DREGS;
+ {
+ return DREGS;
+ }
else
return NO_REGS;
}
if (code == MEM)
if (! reg_class_subset_p (class, default_class))
return default_class;
+
return NO_REGS;
}
\f
DONE;
})
+(define_insn "reload_inpdi"
+ [(set (match_operand:PDI 0 "register_operand" "=e")
+ (match_operand:PDI 1 "memory_operand" "m"))
+ (clobber (match_operand:SI 2 "register_operand" "=d"))]
+ ""
+{
+ rtx xops[4];
+ xops[0] = operands[0];
+ xops[1] = operands[2];
+ split_di (operands + 1, 1, xops + 2, xops + 3);
+ output_asm_insn ("%1 = %2;", xops);
+ output_asm_insn ("%w0 = %1;", xops);
+ output_asm_insn ("%1 = %3;", xops);
+ output_asm_insn ("%x0 = %1;", xops);
+ return "";
+}
+ [(set_attr "seq_insns" "multi")
+ (set_attr "type" "mcld")
+ (set_attr "length" "12")])
+
+(define_insn "reload_outpdi"
+ [(set (match_operand:PDI 0 "memory_operand" "=m")
+ (match_operand:PDI 1 "register_operand" "e"))
+ (clobber (match_operand:SI 2 "register_operand" "=d"))]
+ ""
+{
+ rtx xops[4];
+ xops[0] = operands[1];
+ xops[1] = operands[2];
+ split_di (operands, 1, xops + 2, xops + 3);
+ output_asm_insn ("%1 = %w0;", xops);
+ output_asm_insn ("%2 = %1;", xops);
+ output_asm_insn ("%1 = %x0;", xops);
+ output_asm_insn ("%3 = %1;", xops);
+ return "";
+}
+ [(set_attr "seq_insns" "multi")
+ (set_attr "type" "mcld")
+ (set_attr "length" "12")])
+
;; Jump instructions
(define_insn "jump"