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* arm.md (adddi_sesidi_di): Place tied contraint first.
authorrearnsha <rearnsha@138bc75d-0d04-0410-961f-82ee72b054a4>
Sat, 14 Nov 2009 18:16:18 +0000 (18:16 +0000)
committerrearnsha <rearnsha@138bc75d-0d04-0410-961f-82ee72b054a4>
Sat, 14 Nov 2009 18:16:18 +0000 (18:16 +0000)
(adddi_zesidi_di, subdi_di_zesidi, subdi_di_sesidi): Likewise
(subdi_zesidi_di, subdi_sesidi_di): Likewise.
(mulsi3_compare0, mulsi_compare0_scratch): Likewise.
(mulsi3addsi, mulsi3addsi_compare0): Likewise.
(mulsi3addsi_compare0_scratch, smulsi3_highpart_nov6): Likewise.
(umulsi3_highpart_nov6, anddi_zesidi_di, anddi_sesdi_di): Likewise.
(anddi_notdi_di, iordi_sesidi_di, xordi_sesidi_di): Likewise.
(andsi_iorsi3_notsi, arm_ashldi3_1bit, arm_ashrdi3_1_bit): Likewise.
(arm_lshrdi3_1bit, one_cmpldi2): Likewise.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@154181 138bc75d-0d04-0410-961f-82ee72b054a4

gcc/ChangeLog
gcc/config/arm/arm.md

index ed5f059..b5578e4 100644 (file)
@@ -1,3 +1,16 @@
+2009-11-14  Richard Earnshaw  <rearnsha@arm.com>
+
+       * arm.md (adddi_sesidi_di): Place tied contraint first.
+       (adddi_zesidi_di, subdi_di_zesidi, subdi_di_sesidi): Likewise
+       (subdi_zesidi_di, subdi_sesidi_di): Likewise.
+       (mulsi3_compare0, mulsi_compare0_scratch): Likewise.
+       (mulsi3addsi, mulsi3addsi_compare0): Likewise.
+       (mulsi3addsi_compare0_scratch, smulsi3_highpart_nov6): Likewise.
+       (umulsi3_highpart_nov6, anddi_zesidi_di, anddi_sesdi_di): Likewise.
+       (anddi_notdi_di, iordi_sesidi_di, xordi_sesidi_di): Likewise.
+       (andsi_iorsi3_notsi, arm_ashldi3_1bit, arm_ashrdi3_1_bit): Likewise.
+       (arm_lshrdi3_1bit, one_cmpldi2): Likewise.
+
 2009-11-14  Uros Bizjak  <ubizjak@gmail.com>
 
        * config/i386/predicates.md (call_register_no_elim_operand):
index 691bd55..8527208 100644 (file)
   [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
        (plus:DI (sign_extend:DI
                  (match_operand:SI 2 "s_register_operand" "r,r"))
-                (match_operand:DI 1 "s_register_operand" "r,0")))
+                (match_operand:DI 1 "s_register_operand" "0,r")))
    (clobber (reg:CC CC_REGNUM))]
   "TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)"
   "#"
   [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
        (plus:DI (zero_extend:DI
                  (match_operand:SI 2 "s_register_operand" "r,r"))
-                (match_operand:DI 1 "s_register_operand" "r,0")))
+                (match_operand:DI 1 "s_register_operand" "0,r")))
    (clobber (reg:CC CC_REGNUM))]
   "TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)"
   "#"
 
 (define_insn "*subdi_di_zesidi"
   [(set (match_operand:DI           0 "s_register_operand" "=&r,&r")
-       (minus:DI (match_operand:DI 1 "s_register_operand"  "?r,0")
+       (minus:DI (match_operand:DI 1 "s_register_operand"  "0,r")
                  (zero_extend:DI
                   (match_operand:SI 2 "s_register_operand"  "r,r"))))
    (clobber (reg:CC CC_REGNUM))]
 
 (define_insn "*subdi_di_sesidi"
   [(set (match_operand:DI            0 "s_register_operand" "=&r,&r")
-       (minus:DI (match_operand:DI  1 "s_register_operand"  "r,0")
+       (minus:DI (match_operand:DI  1 "s_register_operand"  "0,r")
                  (sign_extend:DI
                   (match_operand:SI 2 "s_register_operand"  "r,r"))))
    (clobber (reg:CC CC_REGNUM))]
   [(set (match_operand:DI            0 "s_register_operand" "=&r,&r")
        (minus:DI (zero_extend:DI
                   (match_operand:SI 2 "s_register_operand"  "r,r"))
-                 (match_operand:DI  1 "s_register_operand" "?r,0")))
+                 (match_operand:DI  1 "s_register_operand" "0,r")))
    (clobber (reg:CC CC_REGNUM))]
   "TARGET_ARM"
   "rsbs\\t%Q0, %Q1, %2\;rsc\\t%R0, %R1, #0"
   [(set (match_operand:DI            0 "s_register_operand" "=&r,&r")
        (minus:DI (sign_extend:DI
                   (match_operand:SI 2 "s_register_operand"   "r,r"))
-                 (match_operand:DI  1 "s_register_operand"  "?r,0")))
+                 (match_operand:DI  1 "s_register_operand"  "0,r")))
    (clobber (reg:CC CC_REGNUM))]
   "TARGET_ARM"
   "rsbs\\t%Q0, %Q1, %2\;rsc\\t%R0, %R1, %2, asr #31"
 (define_insn "*arm_mulsi3"
   [(set (match_operand:SI          0 "s_register_operand" "=&r,&r")
        (mult:SI (match_operand:SI 2 "s_register_operand" "r,r")
-                (match_operand:SI 1 "s_register_operand" "%?r,0")))]
+                (match_operand:SI 1 "s_register_operand" "%0,r")))]
   "TARGET_32BIT && !arm_arch6"
   "mul%?\\t%0, %2, %1"
   [(set_attr "insn" "mul")
   [(set (reg:CC_NOOV CC_REGNUM)
        (compare:CC_NOOV (mult:SI
                          (match_operand:SI 2 "s_register_operand" "r,r")
-                         (match_operand:SI 1 "s_register_operand" "%?r,0"))
+                         (match_operand:SI 1 "s_register_operand" "%0,r"))
                         (const_int 0)))
    (set (match_operand:SI 0 "s_register_operand" "=&r,&r")
        (mult:SI (match_dup 2) (match_dup 1)))]
   [(set (reg:CC_NOOV CC_REGNUM)
        (compare:CC_NOOV (mult:SI
                          (match_operand:SI 2 "s_register_operand" "r,r")
-                         (match_operand:SI 1 "s_register_operand" "%?r,0"))
+                         (match_operand:SI 1 "s_register_operand" "%0,r"))
                         (const_int 0)))
    (clobber (match_scratch:SI 0 "=&r,&r"))]
   "TARGET_ARM && !arm_arch6"
   [(set (match_operand:SI 0 "s_register_operand" "=&r,&r,&r,&r")
        (plus:SI
          (mult:SI (match_operand:SI 2 "s_register_operand" "r,r,r,r")
-                  (match_operand:SI 1 "s_register_operand" "%r,0,r,0"))
-         (match_operand:SI 3 "s_register_operand" "?r,r,0,0")))]
+                  (match_operand:SI 1 "s_register_operand" "%0,r,0,r"))
+         (match_operand:SI 3 "s_register_operand" "r,r,0,0")))]
   "TARGET_32BIT && !arm_arch6"
   "mla%?\\t%0, %2, %1, %3"
   [(set_attr "insn" "mla")
        (compare:CC_NOOV
         (plus:SI (mult:SI
                   (match_operand:SI 2 "s_register_operand" "r,r,r,r")
-                  (match_operand:SI 1 "s_register_operand" "%r,0,r,0"))
-                 (match_operand:SI 3 "s_register_operand" "?r,r,0,0"))
+                  (match_operand:SI 1 "s_register_operand" "%0,r,0,r"))
+                 (match_operand:SI 3 "s_register_operand" "r,r,0,0"))
         (const_int 0)))
    (set (match_operand:SI 0 "s_register_operand" "=&r,&r,&r,&r")
        (plus:SI (mult:SI (match_dup 2) (match_dup 1))
        (compare:CC_NOOV
         (plus:SI (mult:SI
                   (match_operand:SI 2 "s_register_operand" "r,r,r,r")
-                  (match_operand:SI 1 "s_register_operand" "%r,0,r,0"))
+                  (match_operand:SI 1 "s_register_operand" "%0,r,0,r"))
                  (match_operand:SI 3 "s_register_operand" "?r,r,0,0"))
         (const_int 0)))
    (clobber (match_scratch:SI 0 "=&r,&r,&r,&r"))]
        (truncate:SI
         (lshiftrt:DI
          (mult:DI
-          (sign_extend:DI (match_operand:SI 1 "s_register_operand" "%r,0"))
+          (sign_extend:DI (match_operand:SI 1 "s_register_operand" "%0,r"))
           (sign_extend:DI (match_operand:SI 2 "s_register_operand" "r,r")))
          (const_int 32))))
    (clobber (match_scratch:SI 3 "=&r,&r"))]
        (truncate:SI
         (lshiftrt:DI
          (mult:DI
-          (zero_extend:DI (match_operand:SI 1 "s_register_operand" "%r,0"))
+          (zero_extend:DI (match_operand:SI 1 "s_register_operand" "%0,r"))
           (zero_extend:DI (match_operand:SI 2 "s_register_operand" "r,r")))
          (const_int 32))))
    (clobber (match_scratch:SI 3 "=&r,&r"))]
   [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
        (and:DI (zero_extend:DI
                 (match_operand:SI 2 "s_register_operand" "r,r"))
-               (match_operand:DI 1 "s_register_operand" "?r,0")))]
+               (match_operand:DI 1 "s_register_operand" "0,r")))]
   "TARGET_32BIT"
   "#"
   "TARGET_32BIT && reload_completed"
   [(set (match_operand:DI          0 "s_register_operand" "=&r,&r")
        (and:DI (sign_extend:DI
                 (match_operand:SI 2 "s_register_operand" "r,r"))
-               (match_operand:DI  1 "s_register_operand" "?r,0")))]
+               (match_operand:DI  1 "s_register_operand" "0,r")))]
   "TARGET_32BIT"
   "#"
   [(set_attr "length" "8")]
 ; constants for op 2 will never be given to these patterns.
 (define_insn_and_split "*anddi_notdi_di"
   [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
-       (and:DI (not:DI (match_operand:DI 1 "s_register_operand" "r,0"))
-               (match_operand:DI 2 "s_register_operand" "0,r")))]
+       (and:DI (not:DI (match_operand:DI 1 "s_register_operand" "0,r"))
+               (match_operand:DI 2 "s_register_operand" "r,0")))]
   "TARGET_32BIT"
   "#"
   "TARGET_32BIT && reload_completed && ! IS_IWMMXT_REGNUM (REGNO (operands[0]))"
   [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
        (ior:DI (sign_extend:DI
                 (match_operand:SI 2 "s_register_operand" "r,r"))
-               (match_operand:DI 1 "s_register_operand" "?r,0")))]
+               (match_operand:DI 1 "s_register_operand" "0,r")))]
   "TARGET_32BIT"
   "#"
   [(set_attr "length" "8")
   [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
        (xor:DI (sign_extend:DI
                 (match_operand:SI 2 "s_register_operand" "r,r"))
-               (match_operand:DI 1 "s_register_operand" "?r,0")))]
+               (match_operand:DI 1 "s_register_operand" "0,r")))]
   "TARGET_32BIT"
   "#"
   [(set_attr "length" "8")
 
 (define_insn "*andsi_iorsi3_notsi"
   [(set (match_operand:SI 0 "s_register_operand" "=&r,&r,&r")
-       (and:SI (ior:SI (match_operand:SI 1 "s_register_operand" "r,r,0")
+       (and:SI (ior:SI (match_operand:SI 1 "s_register_operand" "%0,r,r")
                        (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI"))
                (not:SI (match_operand:SI 3 "arm_rhs_operand" "rI,rI,rI"))))]
   "TARGET_32BIT"
 
 (define_insn "arm_ashldi3_1bit"
   [(set (match_operand:DI            0 "s_register_operand" "=&r,r")
-        (ashift:DI (match_operand:DI 1 "s_register_operand" "?r,0")
+        (ashift:DI (match_operand:DI 1 "s_register_operand" "0,r")
                    (const_int 1)))
    (clobber (reg:CC CC_REGNUM))]
   "TARGET_32BIT"
 
 (define_insn "arm_ashrdi3_1bit"
   [(set (match_operand:DI              0 "s_register_operand" "=&r,r")
-        (ashiftrt:DI (match_operand:DI 1 "s_register_operand" "?r,0")
+        (ashiftrt:DI (match_operand:DI 1 "s_register_operand" "0,r")
                      (const_int 1)))
    (clobber (reg:CC CC_REGNUM))]
   "TARGET_32BIT"
 
 (define_insn "arm_lshrdi3_1bit"
   [(set (match_operand:DI              0 "s_register_operand" "=&r,r")
-        (lshiftrt:DI (match_operand:DI 1 "s_register_operand" "?r,0")
+        (lshiftrt:DI (match_operand:DI 1 "s_register_operand" "0,r")
                      (const_int 1)))
    (clobber (reg:CC CC_REGNUM))]
   "TARGET_32BIT"
 )
 
 ;; The constraints here are to prevent a *partial* overlap (where %Q0 == %R1).
-;; The second alternative is to allow the common case of a *full* overlap.
+;; The first alternative allows the common case of a *full* overlap.
 (define_insn "*arm_negdi2"
   [(set (match_operand:DI         0 "s_register_operand" "=&r,r")
-       (neg:DI (match_operand:DI 1 "s_register_operand"  "?r,0")))
+       (neg:DI (match_operand:DI 1 "s_register_operand"  "0,r")))
    (clobber (reg:CC CC_REGNUM))]
   "TARGET_ARM"
   "rsbs\\t%Q0, %Q1, #0\;rsc\\t%R0, %R1, #0"
 
 (define_insn_and_split "one_cmpldi2"
   [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
-       (not:DI (match_operand:DI 1 "s_register_operand" "?r,0")))]
+       (not:DI (match_operand:DI 1 "s_register_operand" "0,r")))]
   "TARGET_32BIT"
   "#"
   "TARGET_32BIT && reload_completed"