+2011-10-29 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
+
+ PR target/50617
+ * config/pa/protos.h (attr_length_save_restore_dltp): Delete.
+ (cmpib_comparison_operator): Likewise.
+ (following_cal, output_and, output_ior, output_move_double,
+ output_fp_move_double, output_block_move, output_block_clear,
+ output_cbranch, output_lbranch, output_bb, output_bvb, output_dbra,
+ output_movb, output_parallel_movb, output_parallel_addb, output_call,
+ output_indirect_call, output_millicode_call, output_mul_insn,
+ output_div_insn, output_mod_insn, singlemove_string,
+ output_arg_descriptor, output_global_address, print_operand,
+ legitimize_pic_address, hppa_encode_label, symbolic_expression_p,
+ fmpyaddoperands, fmpysuboperands, emit_bcond_fp, emit_move_sequence,
+ emit_hpdiv_const, is_function_label_plus_const, jump_in_call_delay,
+ hppa_fpstore_bypass_p, attr_length_millicode_call, attr_length_call,
+ attr_length_indirect_call, return_addr_rtx, function_arg_padding,
+ insn_refs_are_delayed, get_deferred_plabel, ldil_cint_p, zdepi_cint_p,
+ output_ascii, compute_frame_size, and_mask_p, cint_ok_for_move,
+ hppa_expand_prologue, hppa_expand_epilogue, ior_mask_p,
+ compute_zdepdi_operands, output_64bit_and, output_64bit_ior,
+ reloc_needed, magic_milli, shadd_constant_p): Consistently prefix
+ exported functions and variables with "pa_".
+ * config/pa/predicates.md: Likewise.
+ * config/pa/pa64-hpux.h: likewise.
+ * config/pa/som.h: Likewise.
+ * config/pa/elf.h: Likewise.
+ * config/pa/pa64-linux.h: Likewise.
+ * config/pa/pa.md: Likewise.
+ * config/pa/pa.c: Likewise.
+ * config/pa/pa-linux.h: Likewise.
+ * config/pa/pa.h: Likewise.
+ * config/pa/constraints.md: Likewise.
+
2011-10-29 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.md (xop_sha<mode>3): Rename from xop_ashl<mode>3.
(define_constraint "K"
"Integer constant that can be deposited with a zdepi instruction."
(and (match_code "const_int")
- (match_test "zdepi_cint_p (ival)")))
+ (match_test "pa_zdepi_cint_p (ival)")))
(define_constraint "L"
"Signed 5-bit integer constant."
(define_constraint "N"
"Integer constant that can be loaded with a ldil instruction."
(and (match_code "const_int")
- (match_test "ldil_cint_p (ival)")))
+ (match_test "pa_ldil_cint_p (ival)")))
(define_constraint "O"
"Integer constant such that ival+1 is a power of 2."
"Integer constant that can be used as an and mask in depi and
extru instructions."
(and (match_code "const_int")
- (match_test "and_mask_p (ival)")))
+ (match_test "pa_and_mask_p (ival)")))
(define_constraint "S"
"Integer constant 31."
#define ASM_OUTPUT_EXTERNAL_LIBCALL(FILE, RTL) \
do { fputs ("\t.IMPORT ", FILE); \
if (!function_label_operand (RTL, VOIDmode)) \
- hppa_encode_label (RTL); \
+ pa_encode_label (RTL); \
assemble_name (FILE, XSTR ((RTL), 0)); \
fputs (",ENTRY\n", FILE); \
} while (0)
do \
{ \
if (!FUNCTION_NAME_P (XSTR (FUN, 0))) \
- hppa_encode_label (FUN); \
+ pa_encode_label (FUN); \
(*targetm.asm_out.globalize_label) (FILE, XSTR (FUN, 0)); \
} \
while (0)
extern rtx pa_eh_return_handler_rtx (void);
/* Used in insn-*.c. */
-extern int following_call (rtx);
+extern int pa_following_call (rtx);
/* Define functions in pa.c and used in insn-output.c. */
-extern const char *output_and (rtx *);
-extern const char *output_ior (rtx *);
-extern const char *output_move_double (rtx *);
-extern const char *output_fp_move_double (rtx *);
-extern const char *output_block_move (rtx *, int);
-extern const char *output_block_clear (rtx *, int);
-extern const char *output_cbranch (rtx *, int, rtx);
-extern const char *output_lbranch (rtx, rtx, int);
-extern const char *output_bb (rtx *, int, rtx, int);
-extern const char *output_bvb (rtx *, int, rtx, int);
-extern const char *output_dbra (rtx *, rtx, int);
-extern const char *output_movb (rtx *, rtx, int, int);
-extern const char *output_parallel_movb (rtx *, rtx);
-extern const char *output_parallel_addb (rtx *, rtx);
-extern const char *output_call (rtx, rtx, int);
-extern const char *output_indirect_call (rtx, rtx);
-extern const char *output_millicode_call (rtx, rtx);
-extern const char *output_mul_insn (int, rtx);
-extern const char *output_div_insn (rtx *, int, rtx);
-extern const char *output_mod_insn (int, rtx);
-extern const char *singlemove_string (rtx *);
-extern void output_arg_descriptor (rtx);
-extern void output_global_address (FILE *, rtx, int);
-extern void print_operand (FILE *, rtx, int);
-extern rtx legitimize_pic_address (rtx, enum machine_mode, rtx);
-extern void hppa_encode_label (rtx);
-extern int symbolic_expression_p (rtx);
+extern const char *pa_output_and (rtx *);
+extern const char *pa_output_64bit_and (rtx *);
+extern const char *pa_output_ior (rtx *);
+extern const char *pa_output_64bit_ior (rtx *);
+extern const char *pa_output_move_double (rtx *);
+extern const char *pa_output_fp_move_double (rtx *);
+extern const char *pa_output_block_move (rtx *, int);
+extern const char *pa_output_block_clear (rtx *, int);
+extern const char *pa_output_cbranch (rtx *, int, rtx);
+extern const char *pa_output_lbranch (rtx, rtx, int);
+extern const char *pa_output_bb (rtx *, int, rtx, int);
+extern const char *pa_output_bvb (rtx *, int, rtx, int);
+extern const char *pa_output_dbra (rtx *, rtx, int);
+extern const char *pa_output_movb (rtx *, rtx, int, int);
+extern const char *pa_output_parallel_movb (rtx *, rtx);
+extern const char *pa_output_parallel_addb (rtx *, rtx);
+extern const char *pa_output_call (rtx, rtx, int);
+extern const char *pa_output_indirect_call (rtx, rtx);
+extern const char *pa_output_millicode_call (rtx, rtx);
+extern const char *pa_output_mul_insn (int, rtx);
+extern const char *pa_output_div_insn (rtx *, int, rtx);
+extern const char *pa_output_mod_insn (int, rtx);
+extern const char *pa_singlemove_string (rtx *);
+extern void pa_output_arg_descriptor (rtx);
+extern void pa_output_global_address (FILE *, rtx, int);
+extern void pa_print_operand (FILE *, rtx, int);
+extern void pa_encode_label (rtx);
+extern int pa_symbolic_expression_p (rtx);
extern bool pa_tls_referenced_p (rtx);
extern int pa_adjust_insn_length (rtx, int);
-extern int fmpyaddoperands (rtx *);
-extern int fmpysuboperands (rtx *);
-extern void emit_bcond_fp (rtx[]);
-extern int emit_move_sequence (rtx *, enum machine_mode, rtx);
-extern int emit_hpdiv_const (rtx *, int);
-extern int is_function_label_plus_const (rtx);
-extern int jump_in_call_delay (rtx);
-extern int hppa_fpstore_bypass_p (rtx, rtx);
-extern int attr_length_millicode_call (rtx);
-extern int attr_length_call (rtx, int);
-extern int attr_length_indirect_call (rtx);
-extern int attr_length_save_restore_dltp (rtx);
+extern int pa_fmpyaddoperands (rtx *);
+extern int pa_fmpysuboperands (rtx *);
+extern void pa_emit_bcond_fp (rtx[]);
+extern int pa_emit_move_sequence (rtx *, enum machine_mode, rtx);
+extern int pa_emit_hpdiv_const (rtx *, int);
+extern int pa_is_function_label_plus_const (rtx);
+extern int pa_jump_in_call_delay (rtx);
+extern int pa_fpstore_bypass_p (rtx, rtx);
+extern int pa_attr_length_millicode_call (rtx);
+extern int pa_attr_length_call (rtx, int);
+extern int pa_attr_length_indirect_call (rtx);
/* Declare functions defined in pa.c and used in templates. */
-extern rtx return_addr_rtx (int, rtx);
+extern rtx pa_return_addr_rtx (int, rtx);
#ifdef ARGS_SIZE_RTX
/* expr.h defines ARGS_SIZE_RTX and `enum direction' */
#ifdef TREE_CODE
-extern enum direction function_arg_padding (enum machine_mode, const_tree);
+extern enum direction pa_function_arg_padding (enum machine_mode, const_tree);
#endif
#endif /* ARGS_SIZE_RTX */
-extern int insn_refs_are_delayed (rtx);
-extern rtx get_deferred_plabel (rtx);
+extern int pa_insn_refs_are_delayed (rtx);
+extern rtx pa_get_deferred_plabel (rtx);
#endif /* RTX_CODE */
-extern int ldil_cint_p (HOST_WIDE_INT);
-extern int zdepi_cint_p (unsigned HOST_WIDE_INT);
-
-extern void output_ascii (FILE *, const char *, int);
-extern HOST_WIDE_INT compute_frame_size (HOST_WIDE_INT, int *);
-extern int and_mask_p (unsigned HOST_WIDE_INT);
-extern int cint_ok_for_move (HOST_WIDE_INT);
-extern void hppa_expand_prologue (void);
-extern void hppa_expand_epilogue (void);
+extern int pa_and_mask_p (unsigned HOST_WIDE_INT);
+extern int pa_cint_ok_for_move (HOST_WIDE_INT);
+extern int pa_ior_mask_p (unsigned HOST_WIDE_INT);
+extern int pa_ldil_cint_p (HOST_WIDE_INT);
+extern int pa_shadd_constant_p (int);
+extern int pa_zdepi_cint_p (unsigned HOST_WIDE_INT);
+
+extern void pa_output_ascii (FILE *, const char *, int);
+extern HOST_WIDE_INT pa_compute_frame_size (HOST_WIDE_INT, int *);
+extern void pa_expand_prologue (void);
+extern void pa_expand_epilogue (void);
extern bool pa_can_use_return_insn (void);
-extern int ior_mask_p (unsigned HOST_WIDE_INT);
-extern void compute_zdepdi_operands (unsigned HOST_WIDE_INT,
- unsigned *);
-#ifdef RTX_CODE
-extern const char * output_64bit_and (rtx *);
-extern const char * output_64bit_ior (rtx *);
-extern int cmpib_comparison_operator (rtx, enum machine_mode);
-#endif
-
/* Miscellaneous functions in pa.c. */
#ifdef TREE_CODE
-extern int reloc_needed (tree);
+extern int pa_reloc_needed (tree);
extern bool pa_return_in_memory (const_tree, const_tree);
#endif /* TREE_CODE */
extern bool pa_modes_tieable_p (enum machine_mode, enum machine_mode);
extern HOST_WIDE_INT pa_initial_elimination_offset (int, int);
-extern const int magic_milli[];
-extern int shadd_constant_p (int);
+extern const int pa_magic_milli[];
/* Return nonzero if there is a bypass for the output of
OUT_INSN and the fp store IN_INSN. */
int
-hppa_fpstore_bypass_p (rtx out_insn, rtx in_insn)
+pa_fpstore_bypass_p (rtx out_insn, rtx in_insn)
{
enum machine_mode store_mode;
enum machine_mode other_mode;
static int pa_can_combine_p (rtx, rtx, rtx, int, rtx, rtx, rtx);
static bool forward_branch_p (rtx);
static void compute_zdepwi_operands (unsigned HOST_WIDE_INT, unsigned *);
+static void compute_zdepdi_operands (unsigned HOST_WIDE_INT, unsigned *);
static int compute_movmem_length (rtx);
static int compute_clrmem_length (rtx);
static bool pa_assemble_integer (rtx, unsigned int, int);
expressions will have one of a few well defined forms, so
we need only check those forms. */
int
-symbolic_expression_p (rtx x)
+pa_symbolic_expression_p (rtx x)
{
/* Strip off any HIGH. */
/* Accept any constant that can be moved in one instruction into a
general register. */
int
-cint_ok_for_move (HOST_WIDE_INT ival)
+pa_cint_ok_for_move (HOST_WIDE_INT ival)
{
/* OK if ldo, ldil, or zdepi, can be used. */
return (VAL_14_BITS_P (ival)
- || ldil_cint_p (ival)
- || zdepi_cint_p (ival));
+ || pa_ldil_cint_p (ival)
+ || pa_zdepi_cint_p (ival));
}
\f
/* True iff ldil can be used to load this CONST_INT. The least
significant 11 bits of the value must be zero and the value must
not change sign when extended from 32 to 64 bits. */
int
-ldil_cint_p (HOST_WIDE_INT ival)
+pa_ldil_cint_p (HOST_WIDE_INT ival)
{
HOST_WIDE_INT x = ival & (((HOST_WIDE_INT) -1 << 31) | 0x7ff);
zdepi first sign extends a 5-bit signed number to a given field
length, then places this field anywhere in a zero. */
int
-zdepi_cint_p (unsigned HOST_WIDE_INT x)
+pa_zdepi_cint_p (unsigned HOST_WIDE_INT x)
{
unsigned HOST_WIDE_INT lsb_mask, t;
1....10....0
1..10..01..1 */
int
-and_mask_p (unsigned HOST_WIDE_INT mask)
+pa_and_mask_p (unsigned HOST_WIDE_INT mask)
{
mask = ~mask;
mask += mask & -mask;
/* True iff depi can be used to compute (reg | MASK). */
int
-ior_mask_p (unsigned HOST_WIDE_INT mask)
+pa_ior_mask_p (unsigned HOST_WIDE_INT mask)
{
mask += mask & -mask;
return (mask & (mask - 1)) == 0;
position-independent addresses go to REG. If we need more
than one register, we lose. */
-rtx
+static rtx
legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
{
rtx pic_ref = orig;
if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT
&& GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
- && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))
+ && pa_shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))
&& (OBJECT_P (XEXP (x, 1))
|| GET_CODE (XEXP (x, 1)) == SUBREG)
&& GET_CODE (XEXP (x, 1)) != CONST)
&& GET_CODE (XEXP (x, 0)) == PLUS
&& GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
&& GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
- && shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)))
+ && pa_shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)))
&& (mode == SFmode || mode == DFmode))
{
idx = NULL_RTX;
/* Make sure they're both regs. If one was a SYMBOL_REF [+ const],
- then emit_move_sequence will turn on REG_POINTER so we'll know
+ then pa_emit_move_sequence will turn on REG_POINTER so we'll know
it's a base register below. */
if (GET_CODE (reg1) != REG)
reg1 = force_reg (Pmode, force_operand (reg1, 0));
do the optimization for floatint point modes. */
if (GET_CODE (x) == PLUS
- && symbolic_expression_p (XEXP (x, 1)))
+ && pa_symbolic_expression_p (XEXP (x, 1)))
{
/* Ugly. We modify things here so that the address offset specified
by the index expression is computed first, then added to x to form
&& INTVAL (XEXP (y, 1)) >= -4096
&& INTVAL (XEXP (y, 1)) <= 4095
&& GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
- && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
+ && pa_shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
{
int val = INTVAL (XEXP (XEXP (x, 0), 1));
rtx reg1, reg2;
&& GET_CODE (XEXP (y, 1)) == CONST_INT
&& INTVAL (XEXP (y, 1)) % INTVAL (XEXP (XEXP (x, 0), 1)) == 0
&& GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
- && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
+ && pa_shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
{
regx1
= force_reg (Pmode, GEN_INT (INTVAL (XEXP (y, 1))
of SCRATCH_REG in the proper mode. */
int
-emit_move_sequence (rtx *operands, enum machine_mode mode, rtx scratch_reg)
+pa_emit_move_sequence (rtx *operands, enum machine_mode mode, rtx scratch_reg)
{
register rtx operand0 = operands[0];
register rtx operand1 = operands[1];
const_mem = force_const_mem (mode, operand1);
xoperands[0] = scratch_reg;
xoperands[1] = XEXP (const_mem, 0);
- emit_move_sequence (xoperands, Pmode, 0);
+ pa_emit_move_sequence (xoperands, Pmode, 0);
/* Now load the destination register. */
emit_insn (gen_rtx_SET (mode, operand0,
if (register_operand (operand1, mode)
|| (GET_CODE (operand1) == CONST_INT
- && cint_ok_for_move (INTVAL (operand1)))
+ && pa_cint_ok_for_move (INTVAL (operand1)))
|| (operand1 == CONST0_RTX (mode))
|| (GET_CODE (operand1) == HIGH
&& !symbolic_operand (XEXP (operand1, 0), VOIDmode))
/* Put the address of the memory location into our destination
register. */
operands[1] = temp;
- emit_move_sequence (operands, mode, scratch_reg);
+ pa_emit_move_sequence (operands, mode, scratch_reg);
/* Now load from the memory location into our destination
register. */
operands[1] = gen_rtx_MEM (Pmode, operands[0]);
- emit_move_sequence (operands, mode, scratch_reg);
+ pa_emit_move_sequence (operands, mode, scratch_reg);
/* And add back in the constant part. */
if (const_part != NULL_RTX)
operands[1] = legitimize_pic_address (XEXP (const_mem, 0),
mode, temp);
operands[1] = replace_equiv_address (const_mem, operands[1]);
- emit_move_sequence (operands, mode, temp);
+ pa_emit_move_sequence (operands, mode, temp);
}
else
{
operands[1] = tmp;
}
else if (GET_CODE (operand1) != CONST_INT
- || !cint_ok_for_move (INTVAL (operand1)))
+ || !pa_cint_ok_for_move (INTVAL (operand1)))
{
rtx insn, temp;
rtx op1 = operand1;
it will need a link/runtime reloc). */
int
-reloc_needed (tree exp)
+pa_reloc_needed (tree exp)
{
int reloc = 0;
case POINTER_PLUS_EXPR:
case PLUS_EXPR:
case MINUS_EXPR:
- reloc = reloc_needed (TREE_OPERAND (exp, 0));
- reloc |= reloc_needed (TREE_OPERAND (exp, 1));
+ reloc = pa_reloc_needed (TREE_OPERAND (exp, 0));
+ reloc |= pa_reloc_needed (TREE_OPERAND (exp, 1));
break;
CASE_CONVERT:
case NON_LVALUE_EXPR:
- reloc = reloc_needed (TREE_OPERAND (exp, 0));
+ reloc = pa_reloc_needed (TREE_OPERAND (exp, 0));
break;
case CONSTRUCTOR:
FOR_EACH_CONSTRUCTOR_VALUE (CONSTRUCTOR_ELTS (exp), ix, value)
if (value)
- reloc |= reloc_needed (value);
+ reloc |= pa_reloc_needed (value);
}
break;
/* Return the best assembler insn template
for moving operands[1] into operands[0] as a fullword. */
const char *
-singlemove_string (rtx *operands)
+pa_singlemove_string (rtx *operands)
{
HOST_WIDE_INT intval;
return "ldi %1,%0";
else if ((intval & 0x7ff) == 0)
return "ldil L'%1,%0";
- else if (zdepi_cint_p (intval))
+ else if (pa_zdepi_cint_p (intval))
return "{zdepi %Z1,%0|depwi,z %Z1,%0}";
else
return "ldil L'%1,%0\n\tldo R'%1(%0),%0";
/* Compute position (in OP[1]) and width (in OP[2])
useful for copying IMM to a register using the depdi,z
instructions. Store the immediate value to insert in OP[0]. */
-void
+
+static void
compute_zdepdi_operands (unsigned HOST_WIDE_INT imm, unsigned *op)
{
int lsb, len, maxlen;
with operands OPERANDS. */
const char *
-output_move_double (rtx *operands)
+pa_output_move_double (rtx *operands)
{
enum { REGOP, OFFSOP, MEMOP, CNSTOP, RNDOP } optype0, optype1;
rtx latehalf[2];
/* Do the late half first. */
if (addreg1)
output_asm_insn ("ldo 4(%0),%0", &addreg1);
- output_asm_insn (singlemove_string (latehalf), latehalf);
+ output_asm_insn (pa_singlemove_string (latehalf), latehalf);
/* Then clobber. */
if (addreg1)
output_asm_insn ("ldo -4(%0),%0", &addreg1);
- return singlemove_string (operands);
+ return pa_singlemove_string (operands);
}
/* Now handle register -> register case. */
if (optype0 == REGOP && optype1 == REGOP
&& REGNO (operands[0]) == REGNO (operands[1]) + 1)
{
- output_asm_insn (singlemove_string (latehalf), latehalf);
- return singlemove_string (operands);
+ output_asm_insn (pa_singlemove_string (latehalf), latehalf);
+ return pa_singlemove_string (operands);
}
/* Normal case: do the two words, low-numbered first. */
- output_asm_insn (singlemove_string (operands), operands);
+ output_asm_insn (pa_singlemove_string (operands), operands);
/* Make any unoffsettable addresses point at high-numbered word. */
if (addreg0)
output_asm_insn ("ldo 4(%0),%0", &addreg1);
/* Do that word. */
- output_asm_insn (singlemove_string (latehalf), latehalf);
+ output_asm_insn (pa_singlemove_string (latehalf), latehalf);
/* Undo the adds we just did. */
if (addreg0)
}
\f
const char *
-output_fp_move_double (rtx *operands)
+pa_output_fp_move_double (rtx *operands)
{
if (FP_REG_P (operands[0]))
{
OPERANDS[6] is another temporary register. */
const char *
-output_block_move (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED)
+pa_output_block_move (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED)
{
int align = INTVAL (operands[5]);
unsigned long n_bytes = INTVAL (operands[4]);
OPERANDS[3] is the alignment safe to use, as a CONST_INT. */
const char *
-output_block_clear (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED)
+pa_output_block_clear (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED)
{
int align = INTVAL (operands[3]);
unsigned long n_bytes = INTVAL (operands[2]);
\f
const char *
-output_and (rtx *operands)
+pa_output_and (rtx *operands)
{
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
{
/* Return a string to perform a bitwise-and of operands[1] with operands[2]
storing the result in operands[0]. */
const char *
-output_64bit_and (rtx *operands)
+pa_output_64bit_and (rtx *operands)
{
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
{
}
const char *
-output_ior (rtx *operands)
+pa_output_ior (rtx *operands)
{
unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
int bs0, bs1, p, len;
/* Return a string to perform a bitwise-and of operands[1] with operands[2]
storing the result in operands[0]. */
const char *
-output_64bit_ior (rtx *operands)
+pa_output_64bit_ior (rtx *operands)
{
unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
int bs0, bs1, p, len;
\f
/* Output an ascii string. */
void
-output_ascii (FILE *file, const char *p, int size)
+pa_output_ascii (FILE *file, const char *p, int size)
{
int i;
int chars_output;
}
HOST_WIDE_INT
-compute_frame_size (HOST_WIDE_INT size, int *fregs_live)
+pa_compute_frame_size (HOST_WIDE_INT size, int *fregs_live)
{
int freg_saved = 0;
int i, j;
- /* The code in hppa_expand_prologue and hppa_expand_epilogue must
+ /* The code in pa_expand_prologue and pa_expand_epilogue must
be consistent with the rounding and size calculation done here.
Change them at the same time. */
ASM_OUTPUT_LABEL (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));
fputs ("\t.PROC\n", file);
- /* hppa_expand_prologue does the dirty work now. We just need
+ /* pa_expand_prologue does the dirty work now. We just need
to output the assembler directives which denote the start
of a function. */
fprintf (file, "\t.CALLINFO FRAME=" HOST_WIDE_INT_PRINT_DEC, actual_fsize);
}
void
-hppa_expand_prologue (void)
+pa_expand_prologue (void)
{
int merge_sp_adjust_with_store = 0;
HOST_WIDE_INT size = get_frame_size ();
save_fregs = 0;
/* Compute total size for frame pointer, filler, locals and rounding to
- the next word boundary. Similar code appears in compute_frame_size
+ the next word boundary. Similar code appears in pa_compute_frame_size
and must be changed in tandem with this code. */
local_fsize = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1);
if (local_fsize || frame_pointer_needed)
local_fsize += STARTING_FRAME_OFFSET;
- actual_fsize = compute_frame_size (size, &save_fregs);
+ actual_fsize = pa_compute_frame_size (size, &save_fregs);
if (flag_stack_usage_info)
current_function_static_stack_size = actual_fsize;
last_address = 0;
- /* hppa_expand_epilogue does the dirty work now. We just need
+ /* pa_expand_epilogue does the dirty work now. We just need
to output the assembler directives which denote the end
of a function.
}
void
-hppa_expand_epilogue (void)
+pa_expand_epilogue (void)
{
rtx tmpreg;
HOST_WIDE_INT offset;
if (crtl->profile)
return false;
- return compute_frame_size (get_frame_size (), 0) == 0;
+ return pa_compute_frame_size (get_frame_size (), 0) == 0;
}
rtx
return location is in a shared library. */
rtx
-return_addr_rtx (int count, rtx frameaddr)
+pa_return_addr_rtx (int count, rtx frameaddr)
{
rtx label;
rtx rp;
}
void
-emit_bcond_fp (rtx operands[])
+pa_emit_bcond_fp (rtx operands[])
{
enum rtx_code code = GET_CODE (operands[0]);
rtx operand0 = operands[1];
For `%' followed by punctuation, CODE is the punctuation and X is null. */
void
-print_operand (FILE *file, rtx x, int code)
+pa_print_operand (FILE *file, rtx x, int code)
{
switch (code)
{
xoperands[0] = XEXP (XEXP (x, 0), 0);
xoperands[1] = XVECEXP (XEXP (XEXP (x, 0), 1), 0, 0);
- output_global_address (file, xoperands[1], 0);
+ pa_output_global_address (file, xoperands[1], 0);
fprintf (file, "(%s)", reg_names [REGNO (xoperands[0])]);
return;
}
}
return;
case 'G':
- output_global_address (file, x, 0);
+ pa_output_global_address (file, x, 0);
return;
case 'H':
- output_global_address (file, x, 1);
+ pa_output_global_address (file, x, 1);
return;
case 0: /* Don't do anything special */
break;
/* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */
void
-output_global_address (FILE *file, rtx x, int round_constant)
+pa_output_global_address (FILE *file, rtx x, int round_constant)
{
/* Imagine (high (const (plus ...))). */
label. If an entry for SYMBOL is not found, a new entry is created. */
rtx
-get_deferred_plabel (rtx symbol)
+pa_get_deferred_plabel (rtx symbol)
{
const char *fname = XSTR (symbol, 0);
size_t i;
the proper registers. */
const char *
-output_mul_insn (int unsignedp ATTRIBUTE_UNUSED, rtx insn)
+pa_output_mul_insn (int unsignedp ATTRIBUTE_UNUSED, rtx insn)
{
import_milli (mulI);
- return output_millicode_call (insn, gen_rtx_SYMBOL_REF (Pmode, "$$mulI"));
+ return pa_output_millicode_call (insn, gen_rtx_SYMBOL_REF (Pmode, "$$mulI"));
}
/* Emit the rtl for doing a division by a constant. */
/* Do magic division millicodes exist for this value? */
-const int magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0, 1, 1};
+const int pa_magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0, 1, 1};
/* We'll use an array to keep track of the magic millicodes and
whether or not we've used them already. [n][0] is signed, [n][1] is
static int div_milli[16][2];
int
-emit_hpdiv_const (rtx *operands, int unsignedp)
+pa_emit_hpdiv_const (rtx *operands, int unsignedp)
{
if (GET_CODE (operands[2]) == CONST_INT
&& INTVAL (operands[2]) > 0
&& INTVAL (operands[2]) < 16
- && magic_milli[INTVAL (operands[2])])
+ && pa_magic_milli[INTVAL (operands[2])])
{
rtx ret = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
}
const char *
-output_div_insn (rtx *operands, int unsignedp, rtx insn)
+pa_output_div_insn (rtx *operands, int unsignedp, rtx insn)
{
int divisor;
{
sprintf (buf, "$$divU_" HOST_WIDE_INT_PRINT_DEC,
INTVAL (operands[0]));
- return output_millicode_call (insn,
- gen_rtx_SYMBOL_REF (SImode, buf));
+ return pa_output_millicode_call (insn,
+ gen_rtx_SYMBOL_REF (SImode, buf));
}
else
{
sprintf (buf, "$$divI_" HOST_WIDE_INT_PRINT_DEC,
INTVAL (operands[0]));
- return output_millicode_call (insn,
- gen_rtx_SYMBOL_REF (SImode, buf));
+ return pa_output_millicode_call (insn,
+ gen_rtx_SYMBOL_REF (SImode, buf));
}
}
/* Divisor isn't a special constant. */
if (unsignedp)
{
import_milli (divU);
- return output_millicode_call (insn,
+ return pa_output_millicode_call (insn,
gen_rtx_SYMBOL_REF (SImode, "$$divU"));
}
else
{
import_milli (divI);
- return output_millicode_call (insn,
+ return pa_output_millicode_call (insn,
gen_rtx_SYMBOL_REF (SImode, "$$divI"));
}
}
/* Output a $$rem millicode to do mod. */
const char *
-output_mod_insn (int unsignedp, rtx insn)
+pa_output_mod_insn (int unsignedp, rtx insn)
{
if (unsignedp)
{
import_milli (remU);
- return output_millicode_call (insn,
- gen_rtx_SYMBOL_REF (SImode, "$$remU"));
+ return pa_output_millicode_call (insn,
+ gen_rtx_SYMBOL_REF (SImode, "$$remU"));
}
else
{
import_milli (remI);
- return output_millicode_call (insn,
- gen_rtx_SYMBOL_REF (SImode, "$$remI"));
+ return pa_output_millicode_call (insn,
+ gen_rtx_SYMBOL_REF (SImode, "$$remI"));
}
}
void
-output_arg_descriptor (rtx call_insn)
+pa_output_arg_descriptor (rtx call_insn)
{
const char *arg_regs[4];
enum machine_mode arg_mode;
/* Secondary reloads of symbolic operands require %r1 as a scratch
register when we're generating PIC code and when the operand isn't
readonly. */
- if (symbolic_expression_p (x))
+ if (pa_symbolic_expression_p (x))
{
if (GET_CODE (x) == HIGH)
x = XEXP (x, 0);
/* In order to allow 14-bit displacements in integer loads and stores,
we need to prevent reload from generating out of range integer mode
loads and stores to the floating point registers. Previously, we
- used to call for a secondary reload and have emit_move_sequence()
+ used to call for a secondary reload and have pa_emit_move_sequence()
fix the instruction sequence. However, reload occasionally wouldn't
generate the reload and we would end up with an invalid REG+D memory
address. So, now we use an intermediate general register for most
}
enum direction
-function_arg_padding (enum machine_mode mode, const_tree type)
+pa_function_arg_padding (enum machine_mode mode, const_tree type)
{
if (mode == BLKmode
|| (TARGET_64BIT
parameters. */
const char *
-output_cbranch (rtx *operands, int negated, rtx insn)
+pa_output_cbranch (rtx *operands, int negated, rtx insn)
{
static char buf[100];
bool useskip;
default:
/* The reversed conditional branch must branch over one additional
instruction if the delay slot is filled and needs to be extracted
- by output_lbranch. If the delay slot is empty or this is a
+ by pa_output_lbranch. If the delay slot is empty or this is a
nullified forward branch, the instruction after the reversed
condition branch must be nullified. */
if (dbr_sequence_length () == 0
}
output_asm_insn (buf, operands);
- return output_lbranch (operands[0], insn, xdelay);
+ return pa_output_lbranch (operands[0], insn, xdelay);
}
return buf;
}
bytes for the portable runtime, non-PIC and PIC cases, respectively. */
const char *
-output_lbranch (rtx dest, rtx insn, int xdelay)
+pa_output_lbranch (rtx dest, rtx insn, int xdelay)
{
rtx xoperands[2];
above. it returns the appropriate output template to emit the branch. */
const char *
-output_bb (rtx *operands ATTRIBUTE_UNUSED, int negated, rtx insn, int which)
+pa_output_bb (rtx *operands ATTRIBUTE_UNUSED, int negated, rtx insn, int which)
{
static char buf[100];
bool useskip;
default:
/* The reversed conditional branch must branch over one additional
instruction if the delay slot is filled and needs to be extracted
- by output_lbranch. If the delay slot is empty or this is a
+ by pa_output_lbranch. If the delay slot is empty or this is a
nullified forward branch, the instruction after the reversed
condition branch must be nullified. */
if (dbr_sequence_length () == 0
else
strcat (buf, " %0,%1,.+%4");
output_asm_insn (buf, operands);
- return output_lbranch (negated ? operands[3] : operands[2],
- insn, xdelay);
+ return pa_output_lbranch (negated ? operands[3] : operands[2],
+ insn, xdelay);
}
return buf;
}
branch. */
const char *
-output_bvb (rtx *operands ATTRIBUTE_UNUSED, int negated, rtx insn, int which)
+pa_output_bvb (rtx *operands ATTRIBUTE_UNUSED, int negated, rtx insn,
+ int which)
{
static char buf[100];
bool useskip;
default:
/* The reversed conditional branch must branch over one additional
instruction if the delay slot is filled and needs to be extracted
- by output_lbranch. If the delay slot is empty or this is a
+ by pa_output_lbranch. If the delay slot is empty or this is a
nullified forward branch, the instruction after the reversed
condition branch must be nullified. */
if (dbr_sequence_length () == 0
else
strcat (buf, " {%0,.+%4|%0,%%sar,.+%4}");
output_asm_insn (buf, operands);
- return output_lbranch (negated ? operands[3] : operands[2],
- insn, xdelay);
+ return pa_output_lbranch (negated ? operands[3] : operands[2],
+ insn, xdelay);
}
return buf;
}
Note it may perform some output operations on its own before
returning the final output string. */
const char *
-output_dbra (rtx *operands, rtx insn, int which_alternative)
+pa_output_dbra (rtx *operands, rtx insn, int which_alternative)
{
int length = get_attr_length (insn);
default:
/* The reversed conditional branch must branch over one additional
instruction if the delay slot is filled and needs to be extracted
- by output_lbranch. If the delay slot is empty or this is a
+ by pa_output_lbranch. If the delay slot is empty or this is a
nullified forward branch, the instruction after the reversed
condition branch must be nullified. */
if (dbr_sequence_length () == 0
else
output_asm_insn ("addib,%N2 %1,%0,.+%4", operands);
- return output_lbranch (operands[3], insn, xdelay);
+ return pa_output_lbranch (operands[3], insn, xdelay);
}
}
operands[5] = GEN_INT (length - 16);
output_asm_insn ("{comb|cmpb},%B2 %%r0,%4,.+%5", operands);
output_asm_insn ("{fldws|fldw} -16(%%r30),%0", operands);
- return output_lbranch (operands[3], insn, 0);
+ return pa_output_lbranch (operands[3], insn, 0);
}
}
/* Deal with gross reload from memory case. */
{
operands[5] = GEN_INT (length - 4);
output_asm_insn ("addib,%N2 %1,%4,.+%5\n\tstw %4,%0", operands);
- return output_lbranch (operands[3], insn, 0);
+ return pa_output_lbranch (operands[3], insn, 0);
}
}
}
Note it may perform some output operations on its own before
returning the final output string. */
const char *
-output_movb (rtx *operands, rtx insn, int which_alternative,
+pa_output_movb (rtx *operands, rtx insn, int which_alternative,
int reverse_comparison)
{
int length = get_attr_length (insn);
default:
/* The reversed conditional branch must branch over one additional
instruction if the delay slot is filled and needs to be extracted
- by output_lbranch. If the delay slot is empty or this is a
+ by pa_output_lbranch. If the delay slot is empty or this is a
nullified forward branch, the instruction after the reversed
condition branch must be nullified. */
if (dbr_sequence_length () == 0
else
output_asm_insn ("movb,%N2 %1,%0,.+%4", operands);
- return output_lbranch (operands[3], insn, xdelay);
+ return pa_output_lbranch (operands[3], insn, xdelay);
}
}
/* Deal with gross reload for FP destination register case. */
operands[4] = GEN_INT (length - 4);
output_asm_insn ("{comb|cmpb},%B2 %%r0,%1,.+%4", operands);
output_asm_insn ("{fldws|fldw} -16(%%r30),%0", operands);
- return output_lbranch (operands[3], insn, 0);
+ return pa_output_lbranch (operands[3], insn, 0);
}
}
/* Deal with gross reload from memory case. */
operands[4] = GEN_INT (length);
output_asm_insn ("{comb|cmpb},%B2 %%r0,%1,.+%4\n\tstw %1,%0",
operands);
- return output_lbranch (operands[3], insn, 0);
+ return pa_output_lbranch (operands[3], insn, 0);
}
}
/* Handle SAR as a destination. */
operands[4] = GEN_INT (length);
output_asm_insn ("{comb|cmpb},%B2 %%r0,%1,.+%4\n\tmtsar %r1",
operands);
- return output_lbranch (operands[3], insn, 0);
+ return pa_output_lbranch (operands[3], insn, 0);
}
}
}
}
/* Return the attribute length for the millicode call instruction INSN.
- The length must match the code generated by output_millicode_call.
+ The length must match the code generated by pa_output_millicode_call.
We include the delay slot in the returned length as it is better to
over estimate the length than to under estimate it. */
int
-attr_length_millicode_call (rtx insn)
+pa_attr_length_millicode_call (rtx insn)
{
unsigned long distance = -1;
unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
CALL_DEST is the routine we are calling. */
const char *
-output_millicode_call (rtx insn, rtx call_dest)
+pa_output_millicode_call (rtx insn, rtx call_dest)
{
int attr_length = get_attr_length (insn);
int seq_length = dbr_sequence_length ();
/* Return the attribute length of the call instruction INSN. The SIBCALL
flag indicates whether INSN is a regular call or a sibling call. The
length returned must be longer than the code actually generated by
- output_call. Since branch shortening is done before delay branch
+ pa_output_call. Since branch shortening is done before delay branch
sequencing, there is no way to determine whether or not the delay
slot will be filled during branch shortening. Even when the delay
slot is filled, we may have to add a nop if the delay slot contains
these sequences. */
int
-attr_length_call (rtx insn, int sibcall)
+pa_attr_length_call (rtx insn, int sibcall)
{
int local_call;
rtx call, call_dest;
CALL_DEST is the routine we are calling. */
const char *
-output_call (rtx insn, rtx call_dest, int sibcall)
+pa_output_call (rtx insn, rtx call_dest, int sibcall)
{
int delay_insn_deleted = 0;
int delay_slot_filled = 0;
/* Handle the common case where we're sure that the branch will reach
the beginning of the "$CODE$" subspace. This is the beginning of
the current function if we are in a named section. */
- if (!TARGET_LONG_CALLS && attr_length_call (insn, sibcall) == 8)
+ if (!TARGET_LONG_CALLS && pa_attr_length_call (insn, sibcall) == 8)
{
xoperands[1] = gen_rtx_REG (word_mode, sibcall ? 0 : 2);
output_asm_insn ("{bl|b,l} %0,%1", xoperands);
/* ??? As far as I can tell, the HP linker doesn't support the
long pc-relative sequence described in the 64-bit runtime
architecture. So, we use a slightly longer indirect call. */
- xoperands[0] = get_deferred_plabel (call_dest);
+ xoperands[0] = pa_get_deferred_plabel (call_dest);
xoperands[1] = gen_label_rtx ();
/* If this isn't a sibcall, we put the load of %r27 into the
essentially an inline implementation of $$dyncall.
We don't actually try to call $$dyncall as this is
as difficult as calling the function itself. */
- xoperands[0] = get_deferred_plabel (call_dest);
+ xoperands[0] = pa_get_deferred_plabel (call_dest);
xoperands[1] = gen_label_rtx ();
/* Since the call is indirect, FP arguments in registers
the sequence itself. */
int
-attr_length_indirect_call (rtx insn)
+pa_attr_length_indirect_call (rtx insn)
{
unsigned long distance = -1;
unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
}
const char *
-output_indirect_call (rtx insn, rtx call_dest)
+pa_output_indirect_call (rtx insn, rtx call_dest)
{
rtx xoperands[1];
No need to check target flags as the length uniquely identifies
the remaining cases. */
- if (attr_length_indirect_call (insn) == 8)
+ if (pa_attr_length_indirect_call (insn) == 8)
{
/* The HP linker sometimes substitutes a BLE for BL/B,L calls to
$$dyncall. Since BLE uses %r31 as the link register, the 22-bit
/* Long millicode call, but we are not generating PIC or portable runtime
code. */
- if (attr_length_indirect_call (insn) == 12)
+ if (pa_attr_length_indirect_call (insn) == 12)
return ".CALL\tARGW0=GR\n\tldil L'$$dyncall,%%r2\n\tble R'$$dyncall(%%sr4,%%r2)\n\tcopy %%r31,%%r2";
/* Long millicode call for portable runtime. */
- if (attr_length_indirect_call (insn) == 20)
+ if (pa_attr_length_indirect_call (insn) == 20)
return "ldil L'$$dyncall,%%r31\n\tldo R'$$dyncall(%%r31),%%r31\n\tblr %%r0,%%r2\n\tbv,n %%r0(%%r31)\n\tnop";
/* We need a long PIC call to $$dyncall. */
return "";
}
-/* Return the total length of the save and restore instructions needed for
- the data linkage table pointer (i.e., the PIC register) across the call
- instruction INSN. No-return calls do not require a save and restore.
- In addition, we may be able to avoid the save and restore for calls
- within the same translation unit. */
-
-int
-attr_length_save_restore_dltp (rtx insn)
-{
- if (find_reg_note (insn, REG_NORETURN, NULL_RTX))
- return 0;
-
- return 8;
-}
-
/* In HPUX 8.0's shared library scheme, special relocations are needed
for function labels if they might be passed to a function
in a shared library (because shared libraries don't live in code
space), and special magic is needed to construct their address. */
void
-hppa_encode_label (rtx sym)
+pa_encode_label (rtx sym)
{
const char *str = XSTR (sym, 0);
int len = strlen (str) + 1;
{
SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
if (TREE_CODE (decl) == FUNCTION_DECL)
- hppa_encode_label (XEXP (rtl, 0));
+ pa_encode_label (XEXP (rtl, 0));
}
else if (old_referenced)
SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= old_referenced;
with a constant. Used to keep certain patterns from matching
during instruction combination. */
int
-is_function_label_plus_const (rtx op)
+pa_is_function_label_plus_const (rtx op)
{
/* Strip off any CONST. */
if (GET_CODE (op) == CONST)
single subspace mode and the call is not indirect. As far as I know,
there is no operating system support for the multiple subspace mode.
It might be possible to support indirect calls if we didn't use
- $$dyncall (see the indirect sequence generated in output_call). */
+ $$dyncall (see the indirect sequence generated in pa_output_call). */
if (TARGET_ELF32)
return (decl != NULL_TREE);
/* Returns 1 if the 6 operands specified in OPERANDS are suitable for
use in fmpyadd instructions. */
int
-fmpyaddoperands (rtx *operands)
+pa_fmpyaddoperands (rtx *operands)
{
enum machine_mode mode = GET_MODE (operands[0]);
pa_asm_out_constructor (rtx symbol, int priority)
{
if (!function_label_operand (symbol, VOIDmode))
- hppa_encode_label (symbol);
+ pa_encode_label (symbol);
#ifdef CTORS_SECTION_ASM_OP
default_ctor_section_asm_out_constructor (symbol, priority);
pa_asm_out_destructor (rtx symbol, int priority)
{
if (!function_label_operand (symbol, VOIDmode))
- hppa_encode_label (symbol);
+ pa_encode_label (symbol);
#ifdef DTORS_SECTION_ASM_OP
default_dtor_section_asm_out_destructor (symbol, priority);
/* Returns 1 if the 6 operands specified in OPERANDS are suitable for
use in fmpysub instructions. */
int
-fmpysuboperands (rtx *operands)
+pa_fmpysuboperands (rtx *operands)
{
enum machine_mode mode = GET_MODE (operands[0]);
/* Return 1 if the given constant is 2, 4, or 8. These are the valid
constants for shadd instructions. */
int
-shadd_constant_p (int val)
+pa_shadd_constant_p (int val)
{
if (val == 2 || val == 4 || val == 8)
return 1;
/* Return 1 if INSN is in the delay slot of a call instruction. */
int
-jump_in_call_delay (rtx insn)
+pa_jump_in_call_delay (rtx insn)
{
if (GET_CODE (insn) != JUMP_INSN)
/* Output an unconditional move and branch insn. */
const char *
-output_parallel_movb (rtx *operands, rtx insn)
+pa_output_parallel_movb (rtx *operands, rtx insn)
{
int length = get_attr_length (insn);
output_asm_insn ("ldi %1,%0", operands);
else
output_asm_insn ("copy %1,%0", operands);
- return output_lbranch (operands[2], insn, 1);
+ return pa_output_lbranch (operands[2], insn, 1);
}
/* Output an unconditional add and branch insn. */
const char *
-output_parallel_addb (rtx *operands, rtx insn)
+pa_output_parallel_addb (rtx *operands, rtx insn)
{
int length = get_attr_length (insn);
}
output_asm_insn ("add%I1 %1,%0,%0", operands);
- return output_lbranch (operands[3], insn, 1);
+ return pa_output_lbranch (operands[3], insn, 1);
}
/* Return nonzero if INSN (a jump insn) immediately follows a call
the delay slot of the call. */
int
-following_call (rtx insn)
+pa_following_call (rtx insn)
{
if (! TARGET_JUMP_IN_DELAY)
return 0;
filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
in particular. */
int
-insn_refs_are_delayed (rtx insn)
+pa_insn_refs_are_delayed (rtx insn)
{
return ((GET_CODE (insn) == INSN
&& GET_CODE (PATTERN (insn)) != SEQUENCE
if ((from == HARD_FRAME_POINTER_REGNUM || from == FRAME_POINTER_REGNUM)
&& to == STACK_POINTER_REGNUM)
- offset = -compute_frame_size (get_frame_size (), 0);
+ offset = -pa_compute_frame_size (get_frame_size (), 0);
else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
offset = 0;
else
&& !reload_in_progress
&& !reload_completed
&& !LEGITIMATE_64BIT_CONST_INT_P (INTVAL (x))
- && !cint_ok_for_move (INTVAL (x)))
+ && !pa_cint_ok_for_move (INTVAL (x)))
return false;
if (function_label_operand (x, mode))
the stack pointer at the function's entry. Yuk! */
#define DEBUGGER_AUTO_OFFSET(X) \
((GET_CODE (X) == PLUS ? INTVAL (XEXP (X, 1)) : 0) \
- + (frame_pointer_needed ? 0 : compute_frame_size (get_frame_size (), 0)))
+ + (frame_pointer_needed ? 0 : pa_compute_frame_size (get_frame_size (), 0)))
#define DEBUGGER_ARG_OFFSET(OFFSET, X) \
((GET_CODE (X) == PLUS ? OFFSET : 0) \
- + (frame_pointer_needed ? 0 : compute_frame_size (get_frame_size (), 0)))
+ + (frame_pointer_needed ? 0 : pa_compute_frame_size (get_frame_size (), 0)))
#define TARGET_CPU_CPP_BUILTINS() \
do { \
{ \
fputs (integer_asm_op (SIZE, FALSE), FILE); \
if ((ENCODING) & DW_EH_PE_indirect) \
- output_addr_const (FILE, get_deferred_plabel (ADDR)); \
+ output_addr_const (FILE, pa_get_deferred_plabel (ADDR)); \
else \
assemble_name (FILE, XSTR ((ADDR), 0)); \
fputs ("+8-$PIC_pcrel$0", FILE); \
/* If defined, a C expression which determines whether, and in which
direction, to pad out an argument with extra space. */
-#define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding ((MODE), (TYPE))
+#define FUNCTION_ARG_PADDING(MODE, TYPE) \
+ pa_function_arg_padding ((MODE), (TYPE))
/* Specify padding for the last element of a block move between registers
and memory.
so that there is only one element. This allows the object to be
correctly padded. */
#define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
- function_arg_padding ((MODE), (TYPE))
+ pa_function_arg_padding ((MODE), (TYPE))
\f
/* On HPPA, we emit profiling code as rtl via PROFILE_HOOK rather than
|| (GET_CODE (X) == SYMBOL_REF && !SYMBOL_REF_TLS_MODEL (X)) \
|| GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
|| GET_CODE (X) == HIGH) \
- && (reload_in_progress || reload_completed || ! symbolic_expression_p (X)))
+ && (reload_in_progress || reload_completed \
+ || ! pa_symbolic_expression_p (X)))
/* A C expression that is nonzero if we are using the new HP assembler. */
the REG_POINTER lossage can be fixed, it seems better canonicalize.
We initially break out scaled indexed addresses in canonical order
- in emit_move_sequence. LEGITIMIZE_ADDRESS also canonicalizes
+ in pa_emit_move_sequence. LEGITIMIZE_ADDRESS also canonicalizes
scaled indexed addresses during RTL generation. However, fold_rtx
has its own opinion on how the operands of a PLUS should be ordered.
If one of the operands is equivalent to a constant, it will make
(TREE_CODE (DECL) == FUNCTION_DECL \
|| (TREE_CODE (DECL) == VAR_DECL \
&& TREE_READONLY (DECL) && ! TREE_SIDE_EFFECTS (DECL) \
- && (! DECL_INITIAL (DECL) || ! reloc_needed (DECL_INITIAL (DECL))) \
+ && (! DECL_INITIAL (DECL) || ! pa_reloc_needed (DECL_INITIAL (DECL))) \
&& !flag_pic) \
|| CONSTANT_CLASS_P (DECL))
get_attr_type will try to recognize the given insn, so make sure to
filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
in particular. */
-#define INSN_REFERENCES_ARE_DELAYED(X) (insn_refs_are_delayed (X))
+#define INSN_REFERENCES_ARE_DELAYED(X) (pa_insn_refs_are_delayed (X))
\f
/* Control the assembler format that we output. */
#define TARGET_ASM_GLOBALIZE_LABEL pa_globalize_label
#define ASM_OUTPUT_ASCII(FILE, P, SIZE) \
- output_ascii ((FILE), (P), (SIZE))
+ pa_output_ascii ((FILE), (P), (SIZE))
/* Jump tables are always placed in the text section. Technically, it
is possible to put them in the readonly data section when -mbig-switch
M modifier to handle preincrement addressing for memory refs.
F modifier to handle preincrement addressing for fp memory refs */
-#define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
+#define PRINT_OPERAND(FILE, X, CODE) pa_print_operand (FILE, X, CODE)
\f
/* Print a memory address as an operand to reference that memory location. */
fputs ("RR'", FILE); \
else \
fputs ("RT'", FILE); \
- output_global_address (FILE, XEXP (addr, 1), 0); \
+ pa_output_global_address (FILE, XEXP (addr, 1), 0); \
fputs ("(", FILE); \
output_operand (XEXP (addr, 0), 0); \
fputs (")", FILE); \
/* Find the return address associated with the frame given by
FRAMEADDR. */
#define RETURN_ADDR_RTX(COUNT, FRAMEADDR) \
- (return_addr_rtx (COUNT, FRAMEADDR))
+ (pa_return_addr_rtx (COUNT, FRAMEADDR))
/* Used to mask out junk bits from the return address, such as
processor state, interrupt status, condition codes and the like. */
(attr_flag "backward"))])
(define_delay (and (eq_attr "type" "uncond_branch")
- (not (match_test "following_call (insn)")))
+ (not (match_test "pa_following_call (insn)")))
[(eq_attr "in_branch_delay" "true") (nil) (nil)])
;; Memory. Disregarding Cache misses, the Mustang memory times are:
;; We have a bypass for all computations in the FP unit which feed an
;; FP store as long as the sizes are the same.
-(define_bypass 2 "W1,W2" "W10,W11" "hppa_fpstore_bypass_p")
-(define_bypass 9 "W3" "W10,W11" "hppa_fpstore_bypass_p")
-(define_bypass 11 "W4" "W10,W11" "hppa_fpstore_bypass_p")
-(define_bypass 13 "W5" "W10,W11" "hppa_fpstore_bypass_p")
-(define_bypass 17 "W6" "W10,W11" "hppa_fpstore_bypass_p")
+(define_bypass 2 "W1,W2" "W10,W11" "pa_fpstore_bypass_p")
+(define_bypass 9 "W3" "W10,W11" "pa_fpstore_bypass_p")
+(define_bypass 11 "W4" "W10,W11" "pa_fpstore_bypass_p")
+(define_bypass 13 "W5" "W10,W11" "pa_fpstore_bypass_p")
+(define_bypass 17 "W6" "W10,W11" "pa_fpstore_bypass_p")
;; We have an "anti-bypass" for FP loads which feed an FP store.
-(define_bypass 4 "W8,W12" "W10,W11" "hppa_fpstore_bypass_p")
+(define_bypass 4 "W8,W12" "W10,W11" "pa_fpstore_bypass_p")
;; Function units for the 7100 and 7150. The 7100/7150 can dual-issue
;; floating point computations with non-floating point computations (fp loads
;; We have a bypass for all computations in the FP unit which feed an
;; FP store as long as the sizes are the same.
-(define_bypass 1 "X0" "X6,X7" "hppa_fpstore_bypass_p")
-(define_bypass 7 "X1" "X6,X7" "hppa_fpstore_bypass_p")
-(define_bypass 14 "X2" "X6,X7" "hppa_fpstore_bypass_p")
+(define_bypass 1 "X0" "X6,X7" "pa_fpstore_bypass_p")
+(define_bypass 7 "X1" "X6,X7" "pa_fpstore_bypass_p")
+(define_bypass 14 "X2" "X6,X7" "pa_fpstore_bypass_p")
;; We have an "anti-bypass" for FP loads which feed an FP store.
-(define_bypass 3 "X4,X8" "X6,X7" "hppa_fpstore_bypass_p")
+(define_bypass 3 "X4,X8" "X6,X7" "pa_fpstore_bypass_p")
;; The 7100LC has three floating-point units: ALU, MUL, and DIV.
;; There's no value in modeling the ALU and MUL separately though
"i1_7100lc,i1_7100lc+mem_7100lc")
;; We have an "anti-bypass" for FP loads which feed an FP store.
-(define_bypass 3 "Y3,Y7,Y13,Y17" "Y5,Y6,Y11,Y12,Y15,Y16" "hppa_fpstore_bypass_p")
+(define_bypass 3 "Y3,Y7,Y13,Y17" "Y5,Y6,Y11,Y12,Y15,Y16" "pa_fpstore_bypass_p")
;; Scheduling for the PA8000 is somewhat different than scheduling for a
;; traditional architecture.
""
"
{
- emit_bcond_fp (operands);
+ pa_emit_bcond_fp (operands);
DONE;
}")
""
"
{
- emit_bcond_fp (operands);
+ pa_emit_bcond_fp (operands);
DONE;
}")
""
"*
{
- return output_cbranch (operands, 0, insn);
+ return pa_output_cbranch (operands, 0, insn);
}"
[(set_attr "type" "cbranch")
(set (attr "length")
""
"*
{
- return output_cbranch (operands, 1, insn);
+ return pa_output_cbranch (operands, 1, insn);
}"
[(set_attr "type" "cbranch")
(set (attr "length")
"TARGET_64BIT"
"*
{
- return output_cbranch (operands, 0, insn);
+ return pa_output_cbranch (operands, 0, insn);
}"
[(set_attr "type" "cbranch")
(set (attr "length")
"TARGET_64BIT"
"*
{
- return output_cbranch (operands, 1, insn);
+ return pa_output_cbranch (operands, 1, insn);
}"
[(set_attr "type" "cbranch")
(set (attr "length")
"TARGET_64BIT"
"*
{
- return output_cbranch (operands, 0, insn);
+ return pa_output_cbranch (operands, 0, insn);
}"
[(set_attr "type" "cbranch")
(set (attr "length")
"TARGET_64BIT"
"*
{
- return output_cbranch (operands, 1, insn);
+ return pa_output_cbranch (operands, 1, insn);
}"
[(set_attr "type" "cbranch")
(set (attr "length")
""
"*
{
- return output_bb (operands, 0, insn, 0);
+ return pa_output_bb (operands, 0, insn, 0);
}"
[(set_attr "type" "cbranch")
(set (attr "length")
"TARGET_64BIT"
"*
{
- return output_bb (operands, 0, insn, 0);
+ return pa_output_bb (operands, 0, insn, 0);
}"
[(set_attr "type" "cbranch")
(set (attr "length")
""
"*
{
- return output_bb (operands, 1, insn, 0);
+ return pa_output_bb (operands, 1, insn, 0);
}"
[(set_attr "type" "cbranch")
(set (attr "length")
"TARGET_64BIT"
"*
{
- return output_bb (operands, 1, insn, 0);
+ return pa_output_bb (operands, 1, insn, 0);
}"
[(set_attr "type" "cbranch")
(set (attr "length")
""
"*
{
- return output_bb (operands, 0, insn, 1);
+ return pa_output_bb (operands, 0, insn, 1);
}"
[(set_attr "type" "cbranch")
(set (attr "length")
"TARGET_64BIT"
"*
{
- return output_bb (operands, 0, insn, 1);
+ return pa_output_bb (operands, 0, insn, 1);
}"
[(set_attr "type" "cbranch")
(set (attr "length")
""
"*
{
- return output_bb (operands, 1, insn, 1);
+ return pa_output_bb (operands, 1, insn, 1);
}"
[(set_attr "type" "cbranch")
(set (attr "length")
"TARGET_64BIT"
"*
{
- return output_bb (operands, 1, insn, 1);
+ return pa_output_bb (operands, 1, insn, 1);
}"
[(set_attr "type" "cbranch")
(set (attr "length")
""
"*
{
- return output_bvb (operands, 0, insn, 0);
+ return pa_output_bvb (operands, 0, insn, 0);
}"
[(set_attr "type" "cbranch")
(set (attr "length")
"TARGET_64BIT"
"*
{
- return output_bvb (operands, 0, insn, 0);
+ return pa_output_bvb (operands, 0, insn, 0);
}"
[(set_attr "type" "cbranch")
(set (attr "length")
""
"*
{
- return output_bvb (operands, 1, insn, 0);
+ return pa_output_bvb (operands, 1, insn, 0);
}"
[(set_attr "type" "cbranch")
(set (attr "length")
"TARGET_64BIT"
"*
{
- return output_bvb (operands, 1, insn, 0);
+ return pa_output_bvb (operands, 1, insn, 0);
}"
[(set_attr "type" "cbranch")
(set (attr "length")
""
"*
{
- return output_bvb (operands, 0, insn, 1);
+ return pa_output_bvb (operands, 0, insn, 1);
}"
[(set_attr "type" "cbranch")
(set (attr "length")
"TARGET_64BIT"
"*
{
- return output_bvb (operands, 0, insn, 1);
+ return pa_output_bvb (operands, 0, insn, 1);
}"
[(set_attr "type" "cbranch")
(set (attr "length")
""
"*
{
- return output_bvb (operands, 1, insn, 1);
+ return pa_output_bvb (operands, 1, insn, 1);
}"
[(set_attr "type" "cbranch")
(set (attr "length")
"TARGET_64BIT"
"*
{
- return output_bvb (operands, 1, insn, 1);
+ return pa_output_bvb (operands, 1, insn, 1);
}"
[(set_attr "type" "cbranch")
(set (attr "length")
output_asm_insn (\"ftest\;add,tr %%r0,%%r0,%%r0\;b,n .+%0\", xoperands);
else
output_asm_insn (\"ftest\;add,tr %%r0,%%r0,%%r0\;b .+%0\", xoperands);
- return output_lbranch (operands[0], insn, xdelay);
+ return pa_output_lbranch (operands[0], insn, xdelay);
}"
[(set_attr "type" "fbranch")
(set (attr "length")
output_asm_insn (\"ftest\;b,n .+%0\", xoperands);
else
output_asm_insn (\"ftest\;b .+%0\", xoperands);
- return output_lbranch (operands[0], insn, xdelay);
+ return pa_output_lbranch (operands[0], insn, xdelay);
}"
[(set_attr "type" "fbranch")
(set (attr "length")
""
"
{
- if (emit_move_sequence (operands, SImode, 0))
+ if (pa_emit_move_sequence (operands, SImode, 0))
DONE;
}")
""
"
{
- if (emit_move_sequence (operands, SImode, operands[2]))
+ if (pa_emit_move_sequence (operands, SImode, operands[2]))
DONE;
/* We don't want the clobber emitted, so handle this ourselves. */
""
"
{
- if (emit_move_sequence (operands, SImode, operands[2]))
+ if (pa_emit_move_sequence (operands, SImode, operands[2]))
DONE;
/* We don't want the clobber emitted, so handle this ourselves. */
""
"
{
- if (emit_move_sequence (operands, SImode, operands[2]))
+ if (pa_emit_move_sequence (operands, SImode, operands[2]))
DONE;
/* We don't want the clobber emitted, so handle this ourselves. */
[(set (match_operand:SI 0 "register_operand" "=r")
(high:SI (match_operand 1 "" "")))]
"(!flag_pic || !symbolic_operand (operands[1], Pmode))
- && !is_function_label_plus_const (operands[1])"
+ && !pa_is_function_label_plus_const (operands[1])"
"*
{
if (symbolic_operand (operands[1], Pmode))
[(set (match_operand:SI 0 "register_operand" "=r")
(lo_sum:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "immediate_operand" "i")))]
- "!is_function_label_plus_const (operands[2])"
+ "!pa_is_function_label_plus_const (operands[2])"
"*
{
gcc_assert (!flag_pic || !symbolic_operand (operands[2], Pmode));
""
"
{
- if (emit_move_sequence (operands, HImode, 0))
+ if (pa_emit_move_sequence (operands, HImode, 0))
DONE;
}")
""
"
{
- if (emit_move_sequence (operands, HImode, operands[2]))
+ if (pa_emit_move_sequence (operands, HImode, operands[2]))
DONE;
/* We don't want the clobber emitted, so handle this ourselves. */
""
"
{
- if (emit_move_sequence (operands, HImode, operands[2]))
+ if (pa_emit_move_sequence (operands, HImode, operands[2]))
DONE;
/* We don't want the clobber emitted, so handle this ourselves. */
""
"
{
- if (emit_move_sequence (operands, QImode, 0))
+ if (pa_emit_move_sequence (operands, QImode, 0))
DONE;
}")
""
"
{
- if (emit_move_sequence (operands, QImode, operands[2]))
+ if (pa_emit_move_sequence (operands, QImode, operands[2]))
DONE;
/* We don't want the clobber emitted, so handle this ourselves. */
""
"
{
- if (emit_move_sequence (operands, QImode, operands[2]))
+ if (pa_emit_move_sequence (operands, QImode, operands[2]))
DONE;
/* We don't want the clobber emitted, so handle this ourselves. */
}")
;; The operand constraints are written like this to support both compile-time
-;; and run-time determined byte counts. The expander and output_block_move
+;; and run-time determined byte counts. The expander and pa_output_block_move
;; only support compile-time determined counts at this time.
;;
;; If the count is run-time determined, the register with the byte count
(use (match_operand:SI 5 "const_int_operand" "n,n")) ;alignment
(const_int 0)]
"!TARGET_64BIT && reload_completed"
- "* return output_block_move (operands, !which_alternative);"
+ "* return pa_output_block_move (operands, !which_alternative);"
[(set_attr "type" "multi,multi")])
(define_expand "movmemdi"
}")
;; The operand constraints are written like this to support both compile-time
-;; and run-time determined byte counts. The expander and output_block_move
+;; and run-time determined byte counts. The expander and pa_output_block_move
;; only support compile-time determined counts at this time.
;;
;; If the count is run-time determined, the register with the byte count
(use (match_operand:DI 5 "const_int_operand" "n,n")) ;alignment
(const_int 0)]
"TARGET_64BIT && reload_completed"
- "* return output_block_move (operands, !which_alternative);"
+ "* return pa_output_block_move (operands, !which_alternative);"
[(set_attr "type" "multi,multi")])
(define_expand "setmemsi"
(use (match_operand:SI 3 "const_int_operand" "n,n")) ;alignment
(const_int 0)]
"!TARGET_64BIT && reload_completed"
- "* return output_block_clear (operands, !which_alternative);"
+ "* return pa_output_block_clear (operands, !which_alternative);"
[(set_attr "type" "multi,multi")])
(define_expand "setmemdi"
(use (match_operand:DI 3 "const_int_operand" "n,n")) ;alignment
(const_int 0)]
"TARGET_64BIT && reload_completed"
- "* return output_block_clear (operands, !which_alternative);"
+ "* return pa_output_block_clear (operands, !which_alternative);"
[(set_attr "type" "multi,multi")])
\f
;; Floating point move insns
&& operands[1] != CONST0_RTX (DFmode)
&& !TARGET_64BIT
&& !TARGET_SOFT_FLOAT"
- "* return (which_alternative == 0 ? output_move_double (operands)
+ "* return (which_alternative == 0 ? pa_output_move_double (operands)
: \"fldd%F1 %1,%0\");"
[(set_attr "type" "move,fpload")
(set_attr "length" "16,4")])
operands[1] = force_const_mem (DFmode, operands[1]);
}
- if (emit_move_sequence (operands, DFmode, 0))
+ if (pa_emit_move_sequence (operands, DFmode, 0))
DONE;
}")
""
"
{
- if (emit_move_sequence (operands, DFmode, operands[2]))
+ if (pa_emit_move_sequence (operands, DFmode, operands[2]))
DONE;
/* We don't want the clobber emitted, so handle this ourselves. */
""
"
{
- if (emit_move_sequence (operands, DFmode, operands[2]))
+ if (pa_emit_move_sequence (operands, DFmode, operands[2]))
DONE;
/* We don't want the clobber emitted, so handle this ourselves. */
|| operands[1] == CONST0_RTX (DFmode))
&& !(REG_P (operands[0]) && REG_P (operands[1])
&& FP_REG_P (operands[0]) ^ FP_REG_P (operands[1])))
- return output_fp_move_double (operands);
- return output_move_double (operands);
+ return pa_output_fp_move_double (operands);
+ return pa_output_move_double (operands);
}"
[(set_attr "type" "fpalu,move,fpstore,store,store,fpload,load,load,fpstore_load,store_fpload")
(set_attr "length" "4,8,4,8,16,4,8,16,12,12")])
&& TARGET_SOFT_FLOAT"
"*
{
- return output_move_double (operands);
+ return pa_output_move_double (operands);
}"
[(set_attr "type" "move,store,store,load,load")
(set_attr "length" "8,8,16,8,16")])
&& REGNO (operands[0]) >= 32)
FAIL;
- if (emit_move_sequence (operands, DImode, 0))
+ if (pa_emit_move_sequence (operands, DImode, 0))
DONE;
}")
""
"
{
- if (emit_move_sequence (operands, DImode, operands[2]))
+ if (pa_emit_move_sequence (operands, DImode, operands[2]))
DONE;
/* We don't want the clobber emitted, so handle this ourselves. */
""
"
{
- if (emit_move_sequence (operands, DImode, operands[2]))
+ if (pa_emit_move_sequence (operands, DImode, operands[2]))
DONE;
/* We don't want the clobber emitted, so handle this ourselves. */
""
"
{
- if (emit_move_sequence (operands, DImode, operands[2]))
+ if (pa_emit_move_sequence (operands, DImode, operands[2]))
DONE;
/* We don't want the clobber emitted, so handle this ourselves. */
operands[0] = operand_subword (op0, 0, 0, DImode);
operands[1] = GEN_INT (INTVAL (op1) >> 32);
- output_asm_insn (singlemove_string (operands), operands);
+ output_asm_insn (pa_singlemove_string (operands), operands);
#endif
break;
operands[0] = operand_subword (op0, 0, 0, DImode);
operands[1] = GEN_INT (CONST_DOUBLE_HIGH (op1));
- output_asm_insn (singlemove_string (operands), operands);
+ output_asm_insn (pa_singlemove_string (operands), operands);
break;
default:
|| operands[1] == CONST0_RTX (DFmode))
&& !(REG_P (operands[0]) && REG_P (operands[1])
&& FP_REG_P (operands[0]) ^ FP_REG_P (operands[1])))
- return output_fp_move_double (operands);
- return output_move_double (operands);
+ return pa_output_fp_move_double (operands);
+ return pa_output_move_double (operands);
}"
[(set_attr "type"
"move,store,store,load,load,multi,fpalu,fpload,fpstore,fpstore_load,store_fpload")
&& TARGET_SOFT_FLOAT"
"*
{
- return output_move_double (operands);
+ return pa_output_move_double (operands);
}"
[(set_attr "type" "move,store,store,load,load,multi")
(set_attr "length" "8,8,16,8,16,16")])
"GET_CODE (operands[1]) == CONST_DOUBLE
&& operands[1] != CONST0_RTX (SFmode)
&& ! TARGET_SOFT_FLOAT"
- "* return (which_alternative == 0 ? singlemove_string (operands)
+ "* return (which_alternative == 0 ? pa_singlemove_string (operands)
: \" fldw%F1 %1,%0\");"
[(set_attr "type" "move,fpload")
(set_attr "length" "8,4")])
&& REGNO (operands[0]) >= 32)
FAIL;
- if (emit_move_sequence (operands, SFmode, 0))
+ if (pa_emit_move_sequence (operands, SFmode, 0))
DONE;
}")
""
"
{
- if (emit_move_sequence (operands, SFmode, operands[2]))
+ if (pa_emit_move_sequence (operands, SFmode, operands[2]))
DONE;
/* We don't want the clobber emitted, so handle this ourselves. */
""
"
{
- if (emit_move_sequence (operands, SFmode, operands[2]))
+ if (pa_emit_move_sequence (operands, SFmode, operands[2]))
DONE;
/* We don't want the clobber emitted, so handle this ourselves. */
(plus:SI (match_operand:SI 1 "register_operand" "")
(match_operand:SI 2 "const_int_operand" "")))
(clobber (match_operand:SI 4 "register_operand" ""))]
- "! cint_ok_for_move (INTVAL (operands[2]))
+ "! pa_cint_ok_for_move (INTVAL (operands[2]))
&& VAL_14_BITS_P (INTVAL (operands[2]) >> 1)"
[(set (match_dup 4) (plus:SI (match_dup 1) (match_dup 2)))
(set (match_dup 0) (plus:SI (match_dup 4) (match_dup 3)))]
(plus:SI (match_operand:SI 1 "register_operand" "")
(match_operand:SI 2 "const_int_operand" "")))
(clobber (match_operand:SI 4 "register_operand" ""))]
- "! cint_ok_for_move (INTVAL (operands[2]))"
+ "! pa_cint_ok_for_move (INTVAL (operands[2]))"
[(set (match_dup 4) (match_dup 2))
(set (match_dup 0) (plus:SI (mult:SI (match_dup 4) (match_dup 3))
(match_dup 1)))]
/* Try dividing the constant by 2, then 4, and finally 8 to see
if we can get a constant which can be loaded into a register
- in a single instruction (cint_ok_for_move).
+ in a single instruction (pa_cint_ok_for_move).
If that fails, try to negate the constant and subtract it
from our input operand. */
- if (intval % 2 == 0 && cint_ok_for_move (intval / 2))
+ if (intval % 2 == 0 && pa_cint_ok_for_move (intval / 2))
{
operands[2] = GEN_INT (intval / 2);
operands[3] = const2_rtx;
}
- else if (intval % 4 == 0 && cint_ok_for_move (intval / 4))
+ else if (intval % 4 == 0 && pa_cint_ok_for_move (intval / 4))
{
operands[2] = GEN_INT (intval / 4);
operands[3] = GEN_INT (4);
}
- else if (intval % 8 == 0 && cint_ok_for_move (intval / 8))
+ else if (intval % 8 == 0 && pa_cint_ok_for_move (intval / 8))
{
operands[2] = GEN_INT (intval / 8);
operands[3] = GEN_INT (8);
}
- else if (cint_ok_for_move (-intval))
+ else if (pa_cint_ok_for_move (-intval))
{
emit_insn (gen_rtx_SET (VOIDmode, operands[4], GEN_INT (-intval)));
emit_insn (gen_subsi3 (operands[0], operands[1], operands[4]));
(clobber (reg:SI 25))
(clobber (reg:SI 31))]
"!TARGET_64BIT"
- "* return output_mul_insn (0, insn);"
+ "* return pa_output_mul_insn (0, insn);"
[(set_attr "type" "milli")
- (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
+ (set (attr "length") (symbol_ref "pa_attr_length_millicode_call (insn)"))])
(define_insn ""
[(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
(clobber (reg:SI 25))
(clobber (reg:SI 2))]
"TARGET_64BIT"
- "* return output_mul_insn (0, insn);"
+ "* return pa_output_mul_insn (0, insn);"
[(set_attr "type" "milli")
- (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
+ (set (attr "length") (symbol_ref "pa_attr_length_millicode_call (insn)"))])
(define_expand "muldi3"
[(set (match_operand:DI 0 "register_operand" "")
operands[5] = gen_rtx_REG (SImode, 31);
operands[4] = gen_reg_rtx (SImode);
}
- if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 0))
+ if (GET_CODE (operands[2]) == CONST_INT && pa_emit_hpdiv_const (operands, 0))
DONE;
}")
(clobber (reg:SI 31))]
"!TARGET_64BIT"
"*
- return output_div_insn (operands, 0, insn);"
+ return pa_output_div_insn (operands, 0, insn);"
[(set_attr "type" "milli")
- (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
+ (set (attr "length") (symbol_ref "pa_attr_length_millicode_call (insn)"))])
(define_insn ""
[(set (reg:SI 29)
(clobber (reg:SI 2))]
"TARGET_64BIT"
"*
- return output_div_insn (operands, 0, insn);"
+ return pa_output_div_insn (operands, 0, insn);"
[(set_attr "type" "milli")
- (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
+ (set (attr "length") (symbol_ref "pa_attr_length_millicode_call (insn)"))])
(define_expand "udivsi3"
[(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
operands[5] = gen_rtx_REG (SImode, 31);
operands[4] = gen_reg_rtx (SImode);
}
- if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 1))
+ if (GET_CODE (operands[2]) == CONST_INT && pa_emit_hpdiv_const (operands, 1))
DONE;
}")
(clobber (reg:SI 31))]
"!TARGET_64BIT"
"*
- return output_div_insn (operands, 1, insn);"
+ return pa_output_div_insn (operands, 1, insn);"
[(set_attr "type" "milli")
- (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
+ (set (attr "length") (symbol_ref "pa_attr_length_millicode_call (insn)"))])
(define_insn ""
[(set (reg:SI 29)
(clobber (reg:SI 2))]
"TARGET_64BIT"
"*
- return output_div_insn (operands, 1, insn);"
+ return pa_output_div_insn (operands, 1, insn);"
[(set_attr "type" "milli")
- (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
+ (set (attr "length") (symbol_ref "pa_attr_length_millicode_call (insn)"))])
(define_expand "modsi3"
[(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
(clobber (reg:SI 31))]
"!TARGET_64BIT"
"*
- return output_mod_insn (0, insn);"
+ return pa_output_mod_insn (0, insn);"
[(set_attr "type" "milli")
- (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
+ (set (attr "length") (symbol_ref "pa_attr_length_millicode_call (insn)"))])
(define_insn ""
[(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
(clobber (reg:SI 2))]
"TARGET_64BIT"
"*
- return output_mod_insn (0, insn);"
+ return pa_output_mod_insn (0, insn);"
[(set_attr "type" "milli")
- (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
+ (set (attr "length") (symbol_ref "pa_attr_length_millicode_call (insn)"))])
(define_expand "umodsi3"
[(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
(clobber (reg:SI 31))]
"!TARGET_64BIT"
"*
- return output_mod_insn (1, insn);"
+ return pa_output_mod_insn (1, insn);"
[(set_attr "type" "milli")
- (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
+ (set (attr "length") (symbol_ref "pa_attr_length_millicode_call (insn)"))])
(define_insn ""
[(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
(clobber (reg:SI 2))]
"TARGET_64BIT"
"*
- return output_mod_insn (1, insn);"
+ return pa_output_mod_insn (1, insn);"
[(set_attr "type" "milli")
- (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
+ (set (attr "length") (symbol_ref "pa_attr_length_millicode_call (insn)"))])
;;- and instructions
;; We define DImode `and` so with DImode `not` we can get
(and:DI (match_operand:DI 1 "register_operand" "%?r,0")
(match_operand:DI 2 "and_operand" "rO,P")))]
"TARGET_64BIT"
- "* return output_64bit_and (operands); "
+ "* return pa_output_64bit_and (operands); "
[(set_attr "type" "binary")
(set_attr "length" "4")])
(and:SI (match_operand:SI 1 "register_operand" "%?r,0")
(match_operand:SI 2 "and_operand" "rO,P")))]
""
- "* return output_and (operands); "
+ "* return pa_output_and (operands); "
[(set_attr "type" "binary,shift")
(set_attr "length" "4,4")])
(ior:DI (match_operand:DI 1 "register_operand" "0,0")
(match_operand:DI 2 "cint_ior_operand" "M,i")))]
"TARGET_64BIT"
- "* return output_64bit_ior (operands); "
+ "* return pa_output_64bit_ior (operands); "
[(set_attr "type" "binary,shift")
(set_attr "length" "4,4")])
(ior:SI (match_operand:SI 1 "register_operand" "0,0")
(match_operand:SI 2 "cint_ior_operand" "M,i")))]
""
- "* return output_ior (operands); "
+ "* return pa_output_ior (operands); "
[(set_attr "type" "binary,shift")
(set_attr "length" "4,4")])
(define_expand "prologue"
[(const_int 0)]
""
- "hppa_expand_prologue ();DONE;")
+ "pa_expand_prologue ();DONE;")
(define_expand "sibcall_epilogue"
[(return)]
""
"
{
- hppa_expand_epilogue ();
+ pa_expand_epilogue ();
DONE;
}")
x = gen_return ();
else
{
- hppa_expand_epilogue ();
+ pa_expand_epilogue ();
/* EH returns bypass the normal return stub. Thus, we must do an
interspace branch to return from functions that call eh_return.
if (get_attr_length (insn) < 16)
return \"b%* %l0\";
- return output_lbranch (operands[0], insn, 1);
+ return pa_output_lbranch (operands[0], insn, 1);
}"
[(set_attr "type" "uncond_branch")
(set_attr "pa_combine_type" "uncond_branch")
(set (attr "length")
- (cond [(match_test "jump_in_call_delay (insn)")
+ (cond [(match_test "pa_jump_in_call_delay (insn)")
(if_then_else (lt (abs (minus (match_dup 0)
(plus (pc) (const_int 8))))
(const_int MAX_12BIT_OFFSET))
"!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
"*
{
- output_arg_descriptor (insn);
- return output_call (insn, operands[0], 0);
+ pa_output_arg_descriptor (insn);
+ return pa_output_call (insn, operands[0], 0);
}"
[(set_attr "type" "call")
- (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
+ (set (attr "length") (symbol_ref "pa_attr_length_call (insn, 0)"))])
(define_insn "call_symref_pic"
[(set (match_operand:SI 2 "register_operand" "=&r") (reg:SI 19))
"!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
"*
{
- output_arg_descriptor (insn);
- return output_call (insn, operands[0], 0);
+ pa_output_arg_descriptor (insn);
+ return pa_output_call (insn, operands[0], 0);
}"
[(set_attr "type" "call")
- (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
+ (set (attr "length") (symbol_ref "pa_attr_length_call (insn, 0)"))])
;; This pattern is split if it is necessary to save and restore the
;; PIC register.
"TARGET_64BIT"
"*
{
- output_arg_descriptor (insn);
- return output_call (insn, operands[0], 0);
+ pa_output_arg_descriptor (insn);
+ return pa_output_call (insn, operands[0], 0);
}"
[(set_attr "type" "call")
- (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
+ (set (attr "length") (symbol_ref "pa_attr_length_call (insn, 0)"))])
(define_insn "call_reg"
[(call (mem:SI (reg:SI 22))
"!TARGET_64BIT"
"*
{
- return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
+ return pa_output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
}"
[(set_attr "type" "dyncall")
- (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
+ (set (attr "length") (symbol_ref "pa_attr_length_indirect_call (insn)"))])
;; This pattern is split if it is necessary to save and restore the
;; PIC register.
"!TARGET_64BIT"
"*
{
- return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
+ return pa_output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
}"
[(set_attr "type" "dyncall")
- (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
+ (set (attr "length") (symbol_ref "pa_attr_length_indirect_call (insn)"))])
;; This pattern is split if it is necessary to save and restore the
;; PIC register.
"TARGET_64BIT"
"*
{
- return output_indirect_call (insn, operands[0]);
+ return pa_output_indirect_call (insn, operands[0]);
}"
[(set_attr "type" "dyncall")
- (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
+ (set (attr "length") (symbol_ref "pa_attr_length_indirect_call (insn)"))])
(define_expand "call_value"
[(parallel [(set (match_operand 0 "" "")
"!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
"*
{
- output_arg_descriptor (insn);
- return output_call (insn, operands[1], 0);
+ pa_output_arg_descriptor (insn);
+ return pa_output_call (insn, operands[1], 0);
}"
[(set_attr "type" "call")
- (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
+ (set (attr "length") (symbol_ref "pa_attr_length_call (insn, 0)"))])
(define_insn "call_val_symref_pic"
[(set (match_operand:SI 3 "register_operand" "=&r") (reg:SI 19))
"!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
"*
{
- output_arg_descriptor (insn);
- return output_call (insn, operands[1], 0);
+ pa_output_arg_descriptor (insn);
+ return pa_output_call (insn, operands[1], 0);
}"
[(set_attr "type" "call")
- (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
+ (set (attr "length") (symbol_ref "pa_attr_length_call (insn, 0)"))])
;; This pattern is split if it is necessary to save and restore the
;; PIC register.
"TARGET_64BIT"
"*
{
- output_arg_descriptor (insn);
- return output_call (insn, operands[1], 0);
+ pa_output_arg_descriptor (insn);
+ return pa_output_call (insn, operands[1], 0);
}"
[(set_attr "type" "call")
- (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
+ (set (attr "length") (symbol_ref "pa_attr_length_call (insn, 0)"))])
(define_insn "call_val_reg"
[(set (match_operand 0 "" "")
"!TARGET_64BIT"
"*
{
- return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
+ return pa_output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
}"
[(set_attr "type" "dyncall")
- (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
+ (set (attr "length") (symbol_ref "pa_attr_length_indirect_call (insn)"))])
;; This pattern is split if it is necessary to save and restore the
;; PIC register.
"!TARGET_64BIT"
"*
{
- return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
+ return pa_output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
}"
[(set_attr "type" "dyncall")
- (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
+ (set (attr "length") (symbol_ref "pa_attr_length_indirect_call (insn)"))])
;; This pattern is split if it is necessary to save and restore the
;; PIC register.
"TARGET_64BIT"
"*
{
- return output_indirect_call (insn, operands[1]);
+ return pa_output_indirect_call (insn, operands[1]);
}"
[(set_attr "type" "dyncall")
- (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
+ (set (attr "length") (symbol_ref "pa_attr_length_indirect_call (insn)"))])
;; Call subroutine returning any type.
"!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
"*
{
- output_arg_descriptor (insn);
- return output_call (insn, operands[0], 1);
+ pa_output_arg_descriptor (insn);
+ return pa_output_call (insn, operands[0], 1);
}"
[(set_attr "type" "call")
- (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
+ (set (attr "length") (symbol_ref "pa_attr_length_call (insn, 1)"))])
(define_insn "sibcall_internal_symref_64bit"
[(call (mem:SI (match_operand 0 "call_operand_address" ""))
"TARGET_64BIT"
"*
{
- output_arg_descriptor (insn);
- return output_call (insn, operands[0], 1);
+ pa_output_arg_descriptor (insn);
+ return pa_output_call (insn, operands[0], 1);
}"
[(set_attr "type" "call")
- (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
+ (set (attr "length") (symbol_ref "pa_attr_length_call (insn, 1)"))])
(define_expand "sibcall_value"
[(set (match_operand 0 "" "")
"!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
"*
{
- output_arg_descriptor (insn);
- return output_call (insn, operands[1], 1);
+ pa_output_arg_descriptor (insn);
+ return pa_output_call (insn, operands[1], 1);
}"
[(set_attr "type" "call")
- (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
+ (set (attr "length") (symbol_ref "pa_attr_length_call (insn, 1)"))])
(define_insn "sibcall_value_internal_symref_64bit"
[(set (match_operand 0 "" "")
"TARGET_64BIT"
"*
{
- output_arg_descriptor (insn);
- return output_call (insn, operands[1], 1);
+ pa_output_arg_descriptor (insn);
+ return pa_output_call (insn, operands[1], 1);
}"
[(set_attr "type" "call")
- (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
+ (set (attr "length") (symbol_ref "pa_attr_length_call (insn, 1)"))])
(define_insn "nop"
[(const_int 0)]
(plus:SI (match_dup 0) (match_dup 1)))
(clobber (match_scratch:SI 4 "=X,r,r"))]
""
- "* return output_dbra (operands, insn, which_alternative); "
+ "* return pa_output_dbra (operands, insn, which_alternative); "
;; Do not expect to understand this the first time through.
[(set_attr "type" "cbranch,multi,multi")
(set (attr "length")
(set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*m,!*q")
(match_dup 1))]
""
-"* return output_movb (operands, insn, which_alternative, 0); "
+"* return pa_output_movb (operands, insn, which_alternative, 0); "
;; Do not expect to understand this the first time through.
[(set_attr "type" "cbranch,multi,multi,multi")
(set (attr "length")
(set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*m,!*q")
(match_dup 1))]
""
-"* return output_movb (operands, insn, which_alternative, 1); "
+"* return pa_output_movb (operands, insn, which_alternative, 1); "
;; Do not expect to understand this the first time through.
[(set_attr "type" "cbranch,multi,multi,multi")
(set (attr "length")
"(reload_completed && operands[0] == operands[1]) || operands[0] == operands[2]"
"*
{
- return output_parallel_addb (operands, insn);
+ return pa_output_parallel_addb (operands, insn);
}"
[(set_attr "type" "parallel_branch")
(set (attr "length")
"reload_completed"
"*
{
- return output_parallel_movb (operands, insn);
+ return pa_output_parallel_movb (operands, insn);
}"
[(set_attr "type" "parallel_branch")
(set (attr "length")
"reload_completed"
"*
{
- return output_parallel_movb (operands, insn);
+ return pa_output_parallel_movb (operands, insn);
}"
[(set_attr "type" "parallel_branch")
(set (attr "length")
"reload_completed"
"*
{
- return output_parallel_movb (operands, insn);
+ return pa_output_parallel_movb (operands, insn);
}"
[(set_attr "type" "parallel_branch")
(set (attr "length")
"reload_completed"
"*
{
- return output_parallel_movb (operands, insn);
+ return pa_output_parallel_movb (operands, insn);
}"
[(set_attr "type" "parallel_branch")
(set (attr "length")
(plus (match_operand 4 "register_operand" "f")
(match_operand 5 "register_operand" "f")))]
"TARGET_PA_11 && ! TARGET_SOFT_FLOAT
- && reload_completed && fmpyaddoperands (operands)"
+ && reload_completed && pa_fmpyaddoperands (operands)"
"*
{
if (GET_MODE (operands[0]) == DFmode)
(mult (match_operand 1 "register_operand" "f")
(match_operand 2 "register_operand" "f")))]
"TARGET_PA_11 && ! TARGET_SOFT_FLOAT
- && reload_completed && fmpyaddoperands (operands)"
+ && reload_completed && pa_fmpyaddoperands (operands)"
"*
{
if (GET_MODE (operands[0]) == DFmode)
(minus (match_operand 4 "register_operand" "f")
(match_operand 5 "register_operand" "f")))]
"TARGET_PA_11 && ! TARGET_SOFT_FLOAT
- && reload_completed && fmpysuboperands (operands)"
+ && reload_completed && pa_fmpysuboperands (operands)"
"*
{
if (GET_MODE (operands[0]) == DFmode)
(mult (match_operand 1 "register_operand" "f")
(match_operand 2 "register_operand" "f")))]
"TARGET_PA_11 && ! TARGET_SOFT_FLOAT
- && reload_completed && fmpysuboperands (operands)"
+ && reload_completed && pa_fmpysuboperands (operands)"
"*
{
if (GET_MODE (operands[0]) == DFmode)
output_asm_insn (\"{comb|cmpb},<<,n %%r26,%%r31,.+%1\", xoperands);
/* Finally, call $$sh_func_adrs to extract the function's real add24. */
- return output_millicode_call (insn,
- gen_rtx_SYMBOL_REF (SImode,
- \"$$sh_func_adrs\"));
+ return pa_output_millicode_call (insn,
+ gen_rtx_SYMBOL_REF (SImode,
+ \"$$sh_func_adrs\"));
}"
[(set_attr "type" "multi")
(set (attr "length")
- (plus (symbol_ref "attr_length_millicode_call (insn)")
+ (plus (symbol_ref "pa_attr_length_millicode_call (insn)")
(const_int 20)))])
;; On the PA, the PIC register is call clobbered, so it must
#define ASM_OUTPUT_EXTERNAL_LIBCALL(FILE, FUN) \
do { \
if (!FUNCTION_NAME_P (XSTR (FUN, 0))) \
- hppa_encode_label (FUN); \
+ pa_encode_label (FUN); \
ASM_OUTPUT_TYPE_DIRECTIVE (FILE, XSTR (FUN, 0), "function"); \
} while (0)
{ \
int fsize; \
\
- fsize = compute_frame_size (get_frame_size (), 0); \
+ fsize = pa_compute_frame_size (get_frame_size (), 0); \
if ((TO) == FRAME_POINTER_REGNUM \
&& (FROM) == ARG_POINTER_REGNUM) \
{ \
(define_predicate "cint_ior_operand"
(and (match_code "const_int")
- (match_test "ior_mask_p (INTVAL (op))")))
+ (match_test "pa_ior_mask_p (INTVAL (op))")))
;; True iff OP is CONST_INT that can be moved in one instruction
;; into a general register.
(define_predicate "cint_move_operand"
(and (match_code "const_int")
- (match_test "cint_ok_for_move (INTVAL (op))")))
+ (match_test "pa_cint_ok_for_move (INTVAL (op))")))
;; True iff OP is a CONST0_RTX for MODE.
(define_predicate "and_operand"
(ior (match_operand 0 "register_operand")
(and (match_code "const_int")
- (match_test "and_mask_p (INTVAL (op))"))))
+ (match_test "pa_and_mask_p (INTVAL (op))"))))
;; Return truth value of whether OP can be used as an operand in a
;; three operand arithmetic insn that accepts registers of mode MODE
&& ((REG_P (op) && REGNO (op) == 25)
|| (CONST_INT_P (op)
&& INTVAL (op) > 0 && INTVAL (op) < 16
- && magic_milli[INTVAL (op)])));
+ && pa_magic_milli[INTVAL (op)])));
})
;; True iff OP is a reloading floating point register
return true;
if (CONST_INT_P (op))
- return cint_ok_for_move (INTVAL (op));
+ return pa_cint_ok_for_move (INTVAL (op));
if (GET_MODE (op) != mode)
return false;
(define_predicate "shadd_operand"
(and (match_code "const_int")
- (match_test "shadd_constant_p (INTVAL (op))")))
+ (match_test "pa_shadd_constant_p (INTVAL (op))")))
;; Return truth value of statement that OP is a symbolic memory operand.
op = SUBREG_REG (op);
if (!MEM_P (op))
return false;
- return symbolic_expression_p (XEXP (op, 0));
+ return pa_symbolic_expression_p (XEXP (op, 0));
})
;; True iff OP is a symbolic operand.
tree id; \
\
if (!function_label_operand (RTL, VOIDmode)) \
- hppa_encode_label (RTL); \
+ pa_encode_label (RTL); \
\
name = targetm.strip_name_encoding (XSTR ((RTL), 0)); \
id = maybe_get_identifier (name); \
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