2008-02-18 H.J. Lu <hongjiu.lu@intel.com>

	* config/i386/i386-modes.def: Use 4 byte alignment on DI for
	32bit host.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@132397 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 3ecc40c..733d076 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2008-02-18  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * config/i386/i386-modes.def: Use 4 byte alignment on DI for
+       32bit host.
+

 2008-02-18  Joey Ye  <joey.ye@intel.com>
 
        PR middle-end/34921
 2008-02-18  Joey Ye  <joey.ye@intel.com>
 
        PR middle-end/34921

diff --git a/gcc/config/i386/i386-modes.def b/gcc/config/i386/i386-modes.def
index 105d387..f2f2b4f 100644 (file)
--- a/gcc/config/i386/i386-modes.def
+++ b/gcc/config/i386/i386-modes.def
@@ -17,6 +17,10 @@ You should have received a copy of the GNU General Public License
 along with GCC; see the file COPYING3.  If not see
 <http://www.gnu.org/licenses/>.  */
 
 along with GCC; see the file COPYING3.  If not see
 <http://www.gnu.org/licenses/>.  */
 

+/* In 32bit, DI mode uses 32bit registers.  Only 4 byte alignment
+   is needed.  */
+ADJUST_ALIGNMENT (DI, (TARGET_64BIT || TARGET_ALIGN_DOUBLE) ? 8 : 4);
+

 /* The x86_64 ABI specifies both XF and TF modes.
    XFmode is __float80 is IEEE extended; TFmode is __float128
    is IEEE quad.  */
 /* The x86_64 ABI specifies both XF and TF modes.
    XFmode is __float80 is IEEE extended; TFmode is __float128
    is IEEE quad.  */