* config/mips/mips.h (ISA_HAS_INT_CONDMOVE): New.

	* config/mips/mips.md: Use ISA_HAS_INT_CONDMOVE.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@31424 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index fae6e7b..476f400 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2000-01-13  Gavin Romig-Koch  <gavin@cygnus.com>
+
+       * config/mips/mips.h (ISA_HAS_INT_CONDMOVE): New.
+       * config/mips/mips.md: Use ISA_HAS_INT_CONDMOVE.
+
 2000-01-14  Clinton Popetz  <cpopetz@cygnus.com>
 
        * config/mips/mips.c (override_options): Don't turn on extra

diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index b6d7559..b09d106 100644 (file)
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -588,6 +588,11 @@ extern void                sbss_section PARAMS ((void));
 #define ISA_HAS_CONDMOVE        (mips_isa == 4                         \
                                 )
 
+/* ISA has just the integer condition move instructions (movn,movz) */
+#define ISA_HAS_INT_CONDMOVE     0
+
+
+
 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
    branch on CC, and move (both FP and non-FP) on CC. */
 #define ISA_HAS_8CC            (mips_isa == 4                          \

diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 478f34c..3544390 100644 (file)
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -1,5 +1,5 @@
 ;;  Mips.md         Machine Description for MIPS based processors
-;;  Copyright (C) 1989, 90-98, 1999 Free Software Foundation, Inc.
+;;  Copyright (C) 1989, 90-98, 1999, 2000 Free Software Foundation, Inc.
 ;;  Contributed by   A. Lichnewsky, lich@inria.inria.fr
 ;;  Changes by       Michael Meissner, meissner@osf.org
 ;;  64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
@@ -9962,7 +9962,7 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\;j\\t%2"
                          (const_int 0)])
         (match_operand:SI 2 "reg_or_0_operand" "dJ,0")
         (match_operand:SI 3 "reg_or_0_operand" "0,dJ")))]
-  "ISA_HAS_CONDMOVE"
+  "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
   "@
     mov%B4\\t%0,%z2,%1
     mov%b4\\t%0,%z3,%1"
@@ -9977,7 +9977,7 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\;j\\t%2"
                          (const_int 0)])
         (match_operand:SI 2 "reg_or_0_operand" "dJ,0")
         (match_operand:SI 3 "reg_or_0_operand" "0,dJ")))]
-  "ISA_HAS_CONDMOVE"
+  "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
   "@
     mov%B4\\t%0,%z2,%1
     mov%b4\\t%0,%z3,%1"
@@ -10008,7 +10008,7 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\;j\\t%2"
                          (const_int 0)])
         (match_operand:DI 2 "se_reg_or_0_operand" "dJ,0")
         (match_operand:DI 3 "se_reg_or_0_operand" "0,dJ")))]
-  "ISA_HAS_CONDMOVE"
+  "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
   "@
     mov%B4\\t%0,%z2,%1
     mov%b4\\t%0,%z3,%1"
@@ -10023,7 +10023,7 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\;j\\t%2"
                          (const_int 0)])
         (match_operand:DI 2 "se_reg_or_0_operand" "dJ,0")
         (match_operand:DI 3 "se_reg_or_0_operand" "0,dJ")))]
-  "ISA_HAS_CONDMOVE"
+  "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
   "@
     mov%B4\\t%0,%z2,%1
     mov%b4\\t%0,%z3,%1"
@@ -10146,7 +10146,7 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\;j\\t%2"
        (if_then_else:SI (match_dup 5)
                         (match_operand:SI 2 "reg_or_0_operand" "")
                         (match_operand:SI 3 "reg_or_0_operand" "")))]
-  "ISA_HAS_CONDMOVE"
+  "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
   "
 {
   gen_conditional_move (operands);
@@ -10159,7 +10159,7 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\;j\\t%2"
        (if_then_else:DI (match_dup 5)
                         (match_operand:DI 2 "se_reg_or_0_operand" "")
                         (match_operand:DI 3 "se_reg_or_0_operand" "")))]
-  "ISA_HAS_CONDMOVE" 
+  "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE" 
   "
 {
   gen_conditional_move (operands);