+2009-11-24 Uros Bizjak <ubizjak@gmail.com>
+
+ * config/i386/i386.md (add<mode>3_carry): Change insn pattern
+ to expander.
+ (sub<mode>3_carry): Ditto.
+ (x86_mov<mode>cc_0_m1): Ditto.
+ (*add<mode>3_carry): New insn pattern. Use VOIDmode match_operator
+ for ix86_carry_flag_operator operator predicate.
+ (*sub<mode>3_carry): Ditto.
+ (*x86_mov<mode>cc_0_m1): Ditto.
+ (*addsi3_carry_zext): Use VOIDmode match_operator for
+ ix86_carry_flag_operator operator predicate.
+ (*subsi3_carry_zext): Ditto.
+ (*x86_mov<mode>cc_0_m1_s): Ditto.
+ (*x86_mov<mode>cc_0_m1_neg): Ditto.
+ * config/i386/predocates.md (ix86_carry_flag_operator): Do not
+ check operator sub-expressions for FLAGS_REG and const0_rtx.
+ * config/i386/i386.c (*ix86_gen_sub3_carry): Update prototype.
+ (ix86_expand_int_movcc): Update calls to gen_x86_mov{si,di}cc_0_m1.
+ (ix86_expand_int_addcc): Update calls to
+ gen_{add,sub}{qi,hi,si,di}3_carry. Do not set mode of compare_op.
+ (ix86_expand_strlensi_unroll_1): Update calls to ix86_gen_sub3_carry.
+ Do not set mode of compare operation.
+
2009-11-23 Jan Hubicka <jh@suse.cz>
PR middle-end/42151
(mips_mulsidi3_gen_fn): Declare new function.
* config/mips/mips.c (mips_mulsidi3_gen_fn): New function.
* config/mips/mips.md (<u>mulsidi3): Change condition to use
- mips_mulsidi3_gen_fn. Use mips_mulsidi3_gen_fn to generate the
- insn.
+ mips_mulsidi3_gen_fn. Use mips_mulsidi3_gen_fn to generate the insn.
(<u>mulsidi3_64bit): Don't match for ISA_HAS_DMUL3.
(mulsidi3_64bit_dmul): New define_insn.
(INT8_TYPE, INT16_TYPE, INT32_TYPE, INT64_TYPE): Define.
(UINT8_TYPE, UINT16_TYPE, UINT32_TYPE, UINT64_TYPE): Define.
(INT_LEAST8_TYPE, INT_LEAST16_TYPE, INT_LEAST32_TYPE,
- (INT_LEAST64_TYPE): Define.
+ INT_LEAST64_TYPE): Define.
(UINT_LEAST8_TYPE, UINT_LEAST16_TYPE, UINT_LEAST32_TYPE,
UINT_LEAST64_TYPE): Define.
(INT_FAST8_TYPE, INT_FAST16_TYPE, INT_FAST32_TYPE,
* dwarf2out.c (get_context_die): Take TYPE_MAIN_VARIANT.
2009-11-19 Basile Starynkevitch <basile@starynkevitch.net>
- Rafael Avila de Espindola <espindola@google.com>
+ Rafael Avila de Espindola <espindola@google.com>
* doc/plugins.texi (Plugin initialization): Added advices for
- retrieving the version of GCC at plugin compilation and loading
- times.
+ retrieving the version of GCC at plugin compilation and loading times.
2009-11-19 Basile Starynkevitch <basile@starynkevitch.net>
2009-11-18 Daniel Jacobowitz <dan@codesourcery.com>
- * config/arm/neon-docgen.ml (analyze_shape_elt): Handle
- Alternatives.
+ * config/arm/neon-docgen.ml (analyze_shape_elt): Handle alternatives.
2009-11-18 Paul Brook <paul@codesourcery.com>
- Daniel Jacobowitz <dan@codesourcery.com>
+ Daniel Jacobowitz <dan@codesourcery.com>
* config/arm/arm.c (FL_ARCH7EM, FL_FOR_ARCH7EM): Define.
(arm_arch7em): New variable.
2009-11-18 Shujing Zhao <pearly.zhao@oracle.com>
PR middle-end/22201
- * params.def (PARAM_INLINE_UNIT_GROWTH)
- PARAM_IPCP_UNIT_GROWTH)
+ * params.def (PARAM_INLINE_UNIT_GROWTH, PARAM_IPCP_UNIT_GROWTH)
(PARAM_EARLY_INLINING_INSNS, PARAM_IRA_MAX_LOOPS_NUM)
(PARAM_IRA_MAX_CONFLICT_TABLE_SIZE)
(PARAM_LOOP_INVARIANT_MAX_BBS_IN_LOOP)
(PARAM_MIN_INSN_TO_PREFETCH_RATIO)
(PARAM_PREFETCH_MIN_INSN_TO_MEM_RATIO)
- PARAM_IPA_SRA_PTR_GROWTH_FACTOR): Uppercase the first letter of the
+ (PARAM_IPA_SRA_PTR_GROWTH_FACTOR): Uppercase the first letter of the
description string.
2009-11-18 Jakub Jelinek <jakub@redhat.com>
static rtx (*ix86_gen_pop1) (rtx);
static rtx (*ix86_gen_add3) (rtx, rtx, rtx);
static rtx (*ix86_gen_sub3) (rtx, rtx, rtx);
-static rtx (*ix86_gen_sub3_carry) (rtx, rtx, rtx, rtx);
+static rtx (*ix86_gen_sub3_carry) (rtx, rtx, rtx, rtx, rtx);
static rtx (*ix86_gen_one_cmpl2) (rtx, rtx);
static rtx (*ix86_gen_monitor) (rtx, rtx, rtx);
static rtx (*ix86_gen_andsp) (rtx, rtx, rtx);
if (!sign_bit_compare_p)
{
+ rtx flags;
+ rtx (*insn)(rtx, rtx, rtx);
bool fpcmp = false;
compare_code = GET_CODE (compare_op);
- if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
- || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
+ flags = XEXP (compare_op, 0);
+
+ if (GET_MODE (flags) == CCFPmode
+ || GET_MODE (flags) == CCFPUmode)
{
fpcmp = true;
- compare_code = ix86_fp_compare_code_to_integer (compare_code);
+ compare_code
+ = ix86_fp_compare_code_to_integer (compare_code);
}
/* To simplify rest of code, restrict to the GEU case. */
reverse_condition_maybe_unordered
(GET_CODE (compare_op)));
else
- PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
+ PUT_CODE (compare_op,
+ reverse_condition (GET_CODE (compare_op)));
}
diff = ct - cf;
tmp = gen_reg_rtx (mode);
if (mode == DImode)
- emit_insn (gen_x86_movdicc_0_m1 (tmp, compare_op));
+ insn = gen_x86_movdicc_0_m1;
else
- emit_insn (gen_x86_movsicc_0_m1 (gen_lowpart (SImode, tmp),
- compare_op));
+ insn = gen_x86_movsicc_0_m1;
+
+ emit_insn (insn (tmp, flags, compare_op));
}
else
{
ix86_expand_int_addcc (rtx operands[])
{
enum rtx_code code = GET_CODE (operands[1]);
- rtx (*insn)(rtx, rtx, rtx, rtx);
+ rtx flags;
+ rtx (*insn)(rtx, rtx, rtx, rtx, rtx);
rtx compare_op;
rtx val = const0_rtx;
bool fpcmp = false;
- enum machine_mode mode = GET_MODE (operands[0]);
+ enum machine_mode mode;
ix86_compare_op0 = XEXP (operands[1], 0);
ix86_compare_op1 = XEXP (operands[1], 1);
return 0;
code = GET_CODE (compare_op);
- if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
- || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
+ flags = XEXP (compare_op, 0);
+
+ if (GET_MODE (flags) == CCFPmode
+ || GET_MODE (flags) == CCFPUmode)
{
fpcmp = true;
code = ix86_fp_compare_code_to_integer (code);
else
PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
}
- PUT_MODE (compare_op, mode);
+
+ mode = GET_MODE (operands[0]);
/* Construct either adc or sbb insn. */
if ((code == LTU) == (operands[3] == constm1_rtx))
{
- switch (GET_MODE (operands[0]))
+ switch (mode)
{
case QImode:
insn = gen_subqi3_carry;
}
else
{
- switch (GET_MODE (operands[0]))
+ switch (mode)
{
case QImode:
insn = gen_addqi3_carry;
gcc_unreachable ();
}
}
- emit_insn (insn (operands[0], operands[2], val, compare_op));
+ emit_insn (insn (operands[0], operands[2], val, flags, compare_op));
return 1; /* DONE */
}
gen_rtx_IF_THEN_ELSE (Pmode, tmp,
reg2,
out)));
-
}
else
{
/* Avoid branch in fixing the byte. */
tmpreg = gen_lowpart (QImode, tmpreg);
emit_insn (gen_addqi3_cc (tmpreg, tmpreg, tmpreg));
- cmp = gen_rtx_LTU (Pmode, gen_rtx_REG (CCmode, FLAGS_REG), const0_rtx);
- emit_insn ((*ix86_gen_sub3_carry) (out, out, GEN_INT (3), cmp));
+ tmp = gen_rtx_REG (CCmode, FLAGS_REG);
+ cmp = gen_rtx_LTU (VOIDmode, tmp, const0_rtx);
+ emit_insn ((*ix86_gen_sub3_carry) (out, out, GEN_INT (3), tmp, cmp));
emit_label (end_0_label);
}
(clobber (reg:CC FLAGS_REG))])]
"split_<dwi> (&operands[0], 3, &operands[0], &operands[3]);")
-(define_insn "add<mode>3_carry"
+(define_expand "add<mode>3_carry"
+ [(parallel
+ [(set (match_operand:SWI 0 "nonimmediate_operand" "")
+ (plus:SWI
+ (plus:SWI (match_operator:SWI 4 "ix86_carry_flag_operator"
+ [(match_operand 3 "flags_reg_operand" "")
+ (const_int 0)])
+ (match_operand:SWI 1 "nonimmediate_operand" ""))
+ (match_operand:SWI 2 "<general_operand>" "")))
+ (clobber (reg:CC FLAGS_REG))])]
+ "ix86_binary_operator_ok (PLUS, <MODE>mode, operands)"
+ "")
+
+(define_insn "*add<mode>3_carry"
[(set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>")
(plus:SWI
- (plus:SWI (match_operand:SWI 3 "ix86_carry_flag_operator" "")
+ (plus:SWI (match_operator 3 "ix86_carry_flag_operator"
+ [(reg FLAGS_REG) (const_int 0)])
(match_operand:SWI 1 "nonimmediate_operand" "%0,0"))
(match_operand:SWI 2 "<general_operand>" "<r><i>,<r>m")))
(clobber (reg:CC FLAGS_REG))]
[(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI
(plus:SI
- (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
+ (plus:SI (match_operator 3 "ix86_carry_flag_operator"
+ [(reg FLAGS_REG) (const_int 0)])
(match_operand:SI 1 "nonimmediate_operand" "%0"))
(match_operand:SI 2 "general_operand" "g"))))
(clobber (reg:CC FLAGS_REG))]
(clobber (reg:CC FLAGS_REG))])]
"split_<dwi> (&operands[0], 3, &operands[0], &operands[3]);")
-(define_insn "sub<mode>3_carry"
+(define_expand "sub<mode>3_carry"
+ [(parallel
+ [(set (match_operand:SWI 0 "nonimmediate_operand" "")
+ (minus:SWI
+ (match_operand:SWI 1 "nonimmediate_operand" "")
+ (plus:SWI
+ (match_operator:SWI 4 "ix86_carry_flag_operator"
+ [(match_operand 3 "flags_reg_operand" "")
+ (const_int 0)])
+ (match_operand:SWI 2 "<general_operand>" ""))))
+ (clobber (reg:CC FLAGS_REG))])]
+ "ix86_binary_operator_ok (MINUS, <MODE>mode, operands)"
+ "")
+
+(define_insn "*sub<mode>3_carry"
[(set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>")
(minus:SWI
(match_operand:SWI 1 "nonimmediate_operand" "0,0")
(plus:SWI
- (match_operand:SWI 3 "ix86_carry_flag_operator" "")
+ (match_operator 3 "ix86_carry_flag_operator"
+ [(reg FLAGS_REG) (const_int 0)])
(match_operand:SWI 2 "<general_operand>" "<r><i>,<r>m"))))
(clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (MINUS, <MODE>mode, operands)"
[(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI
(minus:SI (match_operand:SI 1 "register_operand" "0")
- (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
+ (plus:SI (match_operator 3 "ix86_carry_flag_operator"
+ [(reg FLAGS_REG) (const_int 0)])
(match_operand:SI 2 "general_operand" "g")))))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
;; the register first winds up with `sbbl $0,reg', which is also weird.
;; So just document what we're doing explicitly.
-(define_insn "x86_mov<mode>cc_0_m1"
+(define_expand "x86_mov<mode>cc_0_m1"
+ [(parallel
+ [(set (match_operand:SWI48 0 "register_operand" "")
+ (if_then_else:SWI48
+ (match_operator:SWI48 2 "ix86_carry_flag_operator"
+ [(match_operand 1 "flags_reg_operand" "")
+ (const_int 0)])
+ (const_int -1)
+ (const_int 0)))
+ (clobber (reg:CC FLAGS_REG))])]
+ ""
+ "")
+
+(define_insn "*x86_mov<mode>cc_0_m1"
[(set (match_operand:SWI48 0 "register_operand" "=r")
- (if_then_else:SWI48 (match_operand 1 "ix86_carry_flag_operator" "")
+ (if_then_else:SWI48 (match_operator 1 "ix86_carry_flag_operator"
+ [(reg FLAGS_REG) (const_int 0)])
(const_int -1)
(const_int 0)))
(clobber (reg:CC FLAGS_REG))]
(define_insn "*x86_mov<mode>cc_0_m1_se"
[(set (match_operand:SWI48 0 "register_operand" "=r")
- (sign_extract:SWI48 (match_operand 1 "ix86_carry_flag_operator" "")
+ (sign_extract:SWI48 (match_operator 1 "ix86_carry_flag_operator"
+ [(reg FLAGS_REG) (const_int 0)])
(const_int 1)
(const_int 0)))
(clobber (reg:CC FLAGS_REG))]
(define_insn "*x86_mov<mode>cc_0_m1_neg"
[(set (match_operand:SWI48 0 "register_operand" "=r")
- (neg:SWI48 (match_operand 1 "ix86_carry_flag_operator" "")))]
+ (neg:SWI48 (match_operator 1 "ix86_carry_flag_operator"
+ [(reg FLAGS_REG) (const_int 0)])))]
""
"sbb{<imodesuffix>}\t%0, %0"
[(set_attr "type" "alu")
enum machine_mode inmode = GET_MODE (XEXP (op, 0));
enum rtx_code code = GET_CODE (op);
- if (!REG_P (XEXP (op, 0))
- || REGNO (XEXP (op, 0)) != FLAGS_REG
- || XEXP (op, 1) != const0_rtx)
- return 0;
-
if (inmode == CCFPmode || inmode == CCFPUmode)
{
if (!ix86_trivial_fp_comparison_operator (op, mode))
OSDN Git Service
