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PR target/18973
authorrearnsha <rearnsha@138bc75d-0d04-0410-961f-82ee72b054a4>
Tue, 14 Dec 2004 14:06:02 +0000 (14:06 +0000)
committerrearnsha <rearnsha@138bc75d-0d04-0410-961f-82ee72b054a4>
Tue, 14 Dec 2004 14:06:02 +0000 (14:06 +0000)
arm-cores.def (arm926ej-s, arm1026ej-s, arm1136j-s, arm1136-jfs)
(arm1176jz-s, arm1176jzf-s, mpcorenovfp, mpcore): Add load-scheduling
property to flags.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@92135 138bc75d-0d04-0410-961f-82ee72b054a4

gcc/ChangeLog
gcc/config/arm/arm-cores.def

index ac417a9..81f345d 100644 (file)
@@ -1,3 +1,10 @@
+2004-12-14  Richard Earnshaw  <rearnsha@arm.com>
+
+       PR target/18973
+       arm-cores.def (arm926ej-s, arm1026ej-s, arm1136j-s, arm1136-jfs)
+       (arm1176jz-s, arm1176jzf-s, mpcorenovfp, mpcore): Add load-scheduling
+       property to flags.
+
 2004-12-14  Diego Novillo  <dnovillo@redhat.com>
 
        * tree-gimple.c (get_base_address): Update documentation.
index d01fc7a..abc5230 100644 (file)
@@ -105,13 +105,13 @@ ARM_CORE("xscale",        xscale, 5TE,                             FL_LDSCHED | FL_
 ARM_CORE("iwmmxt",        iwmmxt,      5TE,                             FL_LDSCHED | FL_STRONG | FL_XSCALE | FL_IWMMXT, xscale)
 
 /* V5TEJ Architecture Processors */
-ARM_CORE("arm926ej-s",    arm926ejs,   5TEJ,                            0, 9e)
-ARM_CORE("arm1026ej-s",   arm1026ejs,  5TEJ,                            0, 9e)
+ARM_CORE("arm926ej-s",    arm926ejs,   5TEJ,                            FL_LDSCHED, 9e)
+ARM_CORE("arm1026ej-s",   arm1026ejs,  5TEJ,                            FL_LDSCHED, 9e)
 
 /* V6 Architecture Processors */
-ARM_CORE("arm1136j-s",    arm1136js,   6J,                              0, 9e)
-ARM_CORE("arm1136jf-s",   arm1136jfs,  6J,                              FL_VFPV2, 9e)
-ARM_CORE("arm1176jz-s",          arm1176jzs,   6ZK,                             0, 9e)
-ARM_CORE("arm1176jzf-s",  arm1176jzfs, 6ZK,                             FL_VFPV2, 9e)
-ARM_CORE("mpcorenovfp",          mpcorenovfp,  6K,                              0, 9e)
-ARM_CORE("mpcore",       mpcore,       6K,                              FL_VFPV2, 9e)
+ARM_CORE("arm1136j-s",    arm1136js,   6J,                              FL_LDSCHED, 9e)
+ARM_CORE("arm1136jf-s",   arm1136jfs,  6J,                              FL_LDSCHED | FL_VFPV2, 9e)
+ARM_CORE("arm1176jz-s",          arm1176jzs,   6ZK,                             FL_LDSCHED, 9e)
+ARM_CORE("arm1176jzf-s",  arm1176jzfs, 6ZK,                             FL_LDSCHED | FL_VFPV2, 9e)
+ARM_CORE("mpcorenovfp",          mpcorenovfp,  6K,                              FL_LDSCHED, 9e)
+ARM_CORE("mpcore",       mpcore,       6K,                              FL_LDSCHED | FL_VFPV2, 9e)