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* config/m68hc11/m68hc11.md ("andqi3"): Accept d as second operand.
authorciceron <ciceron@138bc75d-0d04-0410-961f-82ee72b054a4>
Sat, 21 Jul 2001 11:39:13 +0000 (11:39 +0000)
committerciceron <ciceron@138bc75d-0d04-0410-961f-82ee72b054a4>
Sat, 21 Jul 2001 11:39:13 +0000 (11:39 +0000)
("iorqi3"): Likewise.
("xorqi3"): Likewise.
("*addhi3"): Fix constraint to avoid reloading in a soft register.
("*subhi3_sp): Likewise.
("*subhi3"): Likewise.
("extendhisi2"): Accept D, X and Y as source operand to avoid
reload problems.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@44229 138bc75d-0d04-0410-961f-82ee72b054a4

gcc/ChangeLog
gcc/config/m68hc11/m68hc11.md

index 5421fd0..b5c95a9 100644 (file)
@@ -1,3 +1,14 @@
+2001-07-21  Stephane Carrez  <Stephane.Carrez@worldnet.fr>
+
+       * config/m68hc11/m68hc11.md ("andqi3"): Accept d as second operand.
+       ("iorqi3"): Likewise.
+       ("xorqi3"): Likewise.
+       ("*addhi3"): Fix constraint to avoid reloading in a soft register.
+       ("*subhi3_sp): Likewise.
+       ("*subhi3"): Likewise.
+       ("extendhisi2"): Accept D, X and Y as source operand to avoid 
+       reload problems.
+
 2001-07-21  Nathan Sidwell  <nathan@codesourcery.com>
 
        * doc/tm.texi: Remove DEFAULT_VTABLE_THUNKS.
index e75f1ad..8392c2c 100644 (file)
 
 (define_insn "extendhisi2"
   [(set (match_operand:SI 0 "register_operand" "=D,D,D")
-       (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "m,!r,0")))]
+       (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "m,!r,dA")))]
   ""
   "*
 {
 (define_insn "*addhi3"
   [(set (match_operand:HI 0 "hard_reg_operand" "=A,d,!A,d*A,!d")
        (plus:HI (match_operand:HI 1 "general_operand" "%0,0,0,0,0")
-                (match_operand:HI 2 "general_operand" "N,i,I,umi*A*d,!*d*w")))]
+                (match_operand:HI 2 "general_operand" "N,i,I,mi*A*d,!u*d*w")))]
   "TARGET_M6811"
   "*
 {
 (define_insn "*subhi3_sp"
   [(set (match_operand:HI 0 "stack_register_operand" "=w,w")
        (minus:HI (match_operand:HI 1 "register_operand" "0,0")
-                 (match_operand:HI 2 "general_operand" "uim*d,!*A")))
+                 (match_operand:HI 2 "general_operand" "im*d,!u*A")))
    (clobber (match_scratch:HI 3 "=A*d,A*d"))]
   ""
   "*
 
 
 (define_insn "*subhi3"
-  [(set (match_operand:HI 0 "register_operand" "=d,*A")
-       (minus:HI (match_operand:HI 1 "register_operand" "0,0")
-                 (match_operand:HI 2 "general_operand" "uim*A*d,uim*d*A")))]
+  [(set (match_operand:HI 0 "register_operand" "=d,*A,d*A")
+       (minus:HI (match_operand:HI 1 "register_operand" "0,0,0")
+                 (match_operand:HI 2 "general_operand" "im*A*d,im*d*A,!u")))]
   ""
   "*
 {
 (define_insn "andqi3"
   [(set (match_operand:QI 0 "register_operand" "=d,!u,d,d,?*A,?*A,!*q")
         (and:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,0,0,0")
-             (match_operand:QI 2 "general_operand" "i,i,!um,?*A,i!um,?*A,i!um*A")))]
+             (match_operand:QI 2 "general_operand" "i,i,!um,?*A,!ium,?*A*d,!ium*A")))]
   ""
   "*
 {
 (define_insn "iorqi3"
   [(set (match_operand:QI 0 "register_operand" "=d,!u,d,d,?*A,?*A,!*q")
        (ior:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,0,0,0")
-            (match_operand:QI 2 "general_operand" "i,i,!um,!*A,i!um,!*A,i!um*A")))]
+            (match_operand:QI 2 "general_operand" "i,i,!um,!*A,!ium,?*A*d,!ium*A")))]
   ""
   "*
 {
 }")
 
 (define_insn "xorqi3"
-  [(set (match_operand:QI 0 "register_operand" "=d,d,!*u*A,!*u*A,!*q")
-        (xor:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,0")
-             (match_operand:QI 2 "general_operand" "ium,!*A,ium,!*A,ium*A*u")))]
+  [(set (match_operand:QI 0 "register_operand" "=d,d,d,?*A,?*A,!*q")
+        (xor:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,0,0")
+             (match_operand:QI 2 "general_operand" "i,!um,!*A,!ium,?*A*d,!ium*A")))]
   ""
   "*
 {