+Tue Oct 13 17:51:04 1998 Jim Wilson <wilson@cygnus.com>
+
+ * config/m68k/m68k.h (HARD_REGNO_MODE_OK): For FP regs, add REGNO >= 16
+ check. Add comment to document problems with TARGET_SUN_FPA version
+ of this macro.
+ * config/m68k/m68k.md (movxf+1): Support 'r'/'r' moves.
+
Tue Oct 13 17:46:18 1998 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
* Makefile.in (gencheck.o): Depend on gansidecl.h.
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
(((REGNO) < 16 \
- && !((REGNO) < 8 && (REGNO) + GET_MODE_SIZE ((MODE)) / 4 > 8)) \
- || ((REGNO) < 24 \
+ && !((REGNO) < 8 && (REGNO) + GET_MODE_SIZE (MODE) / 4 > 8)) \
+ || ((REGNO) >= 16 && (REGNO) < 24 \
&& TARGET_68881 \
&& (GET_MODE_CLASS (MODE) == MODE_FLOAT \
|| GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)))
(apparently) hold whatever you feel like putting in them.
If using the fpa, don't put a double in d7/a0. */
+/* ??? This is confused. The check to prohibit d7/a0 overlaps should always
+ be enabled regardless of whether TARGET_FPA is specified. It isn't clear
+ what the other d/a register checks are for. Every check using REGNO
+ actually needs to use a range, e.g. 24>=X<56 not <56. There is probably
+ no one using this code anymore. */
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
(((REGNO) < 16 \
&& !(TARGET_FPA \
}")
(define_insn ""
- [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,!r,!f")
- (match_operand:XF 1 "nonimmediate_operand" "m,f,f,f,r"))]
+ [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,!r,!f,!r")
+ (match_operand:XF 1 "nonimmediate_operand" "m,f,f,f,r,!r"))]
"TARGET_68881"
"*
{
return \"fmove%.x %1,%0\";
return \"fmove%.x %f1,%0\";
}
- if (REG_P (operands[0]))
+ if (FP_REG_P (operands[1]))
{
- output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands);
- operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
- output_asm_insn (\"move%.l %+,%0\", operands);
- operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
- return \"move%.l %+,%0\";
+ if (REG_P (operands[0]))
+ {
+ output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands);
+ operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
+ output_asm_insn (\"move%.l %+,%0\", operands);
+ operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
+ return \"move%.l %+,%0\";
+ }
+ /* Must be memory destination. */
+ return \"fmove%.x %f1,%0\";
}
- return \"fmove%.x %f1,%0\";
+ return output_move_double (operands);
}
")