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2012-03-23 Michael Meissner <meissner@linux.vnet.ibm.com>
authormeissner <meissner@138bc75d-0d04-0410-961f-82ee72b054a4>
Fri, 23 Mar 2012 16:16:38 +0000 (16:16 +0000)
committermeissner <meissner@138bc75d-0d04-0410-961f-82ee72b054a4>
Fri, 23 Mar 2012 16:16:38 +0000 (16:16 +0000)
Backported from mainline
2012-03-06  Michael Meissner  <meissner@linux.vnet.ibm.com>

PR target/50310
* config/rs6000/vector.md (vector_uneq<mode>): Add support for
UNEQ, LTGT, ORDERED, and UNORDERED IEEE vector comparisons.
(vector_ltgt<mode>): Likewise.
(vector_ordered<mode>): Likewise.
(vector_unordered<mode>): Likewise.
* config/rs6000/rs6000.c (rs6000_emit_vector_compare_inner): Likewise.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_7-branch@185743 138bc75d-0d04-0410-961f-82ee72b054a4

gcc/ChangeLog
gcc/config/rs6000/rs6000.c
gcc/config/rs6000/vector.md

index fa1ae57..1264e67 100644 (file)
@@ -1,3 +1,16 @@
+2012-03-23  Michael Meissner  <meissner@linux.vnet.ibm.com>
+
+       Backported from mainline
+       2012-03-06  Michael Meissner  <meissner@linux.vnet.ibm.com>
+
+       PR target/50310
+       * config/rs6000/vector.md (vector_uneq<mode>): Add support for
+       UNEQ, LTGT, ORDERED, and UNORDERED IEEE vector comparisons.
+       (vector_ltgt<mode>): Likewise.
+       (vector_ordered<mode>): Likewise.
+       (vector_unordered<mode>): Likewise.
+       * config/rs6000/rs6000.c (rs6000_emit_vector_compare_inner): Likewise.
+
 2012-03-23  Joern Rennecke  <joern.rennecke@embecosm.com>
 
        * config/epiphany/epiphany.c (epiphany_function_value_regno_p):
index 423adb2..0bcb9f0 100644 (file)
@@ -16137,6 +16137,10 @@ rs6000_emit_vector_compare_inner (enum rtx_code code, rtx op0, rtx op1)
     case EQ:
     case GT:
     case GTU:
+    case ORDERED:
+    case UNORDERED:
+    case UNEQ:
+    case LTGT:
       mask = gen_reg_rtx (mode);
       emit_insn (gen_rtx_SET (VOIDmode,
                              mask,
index bcb23ac..6674054 100644 (file)
   "VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
   "")
 
+(define_insn_and_split "*vector_uneq<mode>"
+  [(set (match_operand:VEC_F 0 "vfloat_operand" "")
+       (uneq:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
+                   (match_operand:VEC_F 2 "vfloat_operand" "")))]
+  "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
+  "#"
+  ""
+  [(set (match_dup 3)
+       (gt:VEC_F (match_dup 1)
+                 (match_dup 2)))
+   (set (match_dup 4)
+       (gt:VEC_F (match_dup 2)
+                 (match_dup 1)))
+   (set (match_dup 0)
+       (not:VEC_F (ior:VEC_F (match_dup 3)
+                             (match_dup 4))))]
+  "
+{
+  operands[3] = gen_reg_rtx (<MODE>mode);
+  operands[4] = gen_reg_rtx (<MODE>mode);
+}")
+
+(define_insn_and_split "*vector_ltgt<mode>"
+  [(set (match_operand:VEC_F 0 "vfloat_operand" "")
+       (ltgt:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
+                   (match_operand:VEC_F 2 "vfloat_operand" "")))]
+  "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
+  "#"
+  ""
+  [(set (match_dup 3)
+       (gt:VEC_F (match_dup 1)
+                 (match_dup 2)))
+   (set (match_dup 4)
+       (gt:VEC_F (match_dup 2)
+                 (match_dup 1)))
+   (set (match_dup 0)
+       (ior:VEC_F (match_dup 3)
+                  (match_dup 4)))]
+  "
+{
+  operands[3] = gen_reg_rtx (<MODE>mode);
+  operands[4] = gen_reg_rtx (<MODE>mode);
+}")
+
+(define_insn_and_split "*vector_ordered<mode>"
+  [(set (match_operand:VEC_F 0 "vfloat_operand" "")
+       (ordered:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
+                      (match_operand:VEC_F 2 "vfloat_operand" "")))]
+  "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
+  "#"
+  ""
+  [(set (match_dup 3)
+       (ge:VEC_F (match_dup 1)
+                 (match_dup 2)))
+   (set (match_dup 4)
+       (ge:VEC_F (match_dup 2)
+                 (match_dup 1)))
+   (set (match_dup 0)
+       (ior:VEC_F (match_dup 3)
+                  (match_dup 4)))]
+  "
+{
+  operands[3] = gen_reg_rtx (<MODE>mode);
+  operands[4] = gen_reg_rtx (<MODE>mode);
+}")
+
+(define_insn_and_split "*vector_unordered<mode>"
+  [(set (match_operand:VEC_F 0 "vfloat_operand" "")
+       (unordered:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
+                        (match_operand:VEC_F 2 "vfloat_operand" "")))]
+  "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
+  "#"
+  ""
+  [(set (match_dup 3)
+       (ge:VEC_F (match_dup 1)
+                 (match_dup 2)))
+   (set (match_dup 4)
+       (ge:VEC_F (match_dup 2)
+                 (match_dup 1)))
+   (set (match_dup 0)
+       (not:VEC_F (ior:VEC_F (match_dup 3)
+                             (match_dup 4))))]
+  "
+{
+  operands[3] = gen_reg_rtx (<MODE>mode);
+  operands[4] = gen_reg_rtx (<MODE>mode);
+}")
+
 ;; Note the arguments for __builtin_altivec_vsel are op2, op1, mask
 ;; which is in the reverse order that we want
 (define_expand "vector_select_<mode>"