Back port Fix PR 52908 - xop-mul-1:f9 miscompiled on bulldozer (-mxop) to 4.7 branch

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_7-branch@188736 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 4bb24fa..51b2b13 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,18 @@
+2012-06-18  Venkataramanan Kumar <venkataramanan.kumar@amd.com>
+
+       Backport from mainline 
+       2012-05-09 Uros Bizjak  <ubizjak@gmail.com>
+
+       PR target/52908
+       * config/i386/sse.md (vec_widen_smult_hi_v4si): Expand using
+       xop_pmacsdqh insn pattern instead of xop_mulv2div2di3_high.
+       (vec_widen_smult_lo_v4si): Expand using xop_pmacsdql insn pattern
+       instead of xop_mulv2div2di3_low.
+       (xop_p<macs>dql): Fix vec_select selector.
+       (xop_p<macs>dqh): Ditto.
+       (xop_mulv2div2di3_low): Remove insn_and_split pattern.
+       (xop_mulv2div2di3_high): Ditto.
+

 2012-06-17  Uros Bizjak  <ubizjak@gmail.com>
 
        Backport from mainline:
 2012-06-17  Uros Bizjak  <ubizjak@gmail.com>
 
        Backport from mainline:

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 0c9e9d8..39620c1 100644 (file)
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -5722,11 +5722,15 @@
 
   if (TARGET_XOP)
     {
 
   if (TARGET_XOP)
     {

+      rtx t3 = gen_reg_rtx (V2DImode);
+

       emit_insn (gen_sse2_pshufd_1 (t1, op1, GEN_INT (0), GEN_INT (2),
                                    GEN_INT (1), GEN_INT (3)));
       emit_insn (gen_sse2_pshufd_1 (t2, op2, GEN_INT (0), GEN_INT (2),
                                    GEN_INT (1), GEN_INT (3)));
       emit_insn (gen_sse2_pshufd_1 (t1, op1, GEN_INT (0), GEN_INT (2),
                                    GEN_INT (1), GEN_INT (3)));
       emit_insn (gen_sse2_pshufd_1 (t2, op2, GEN_INT (0), GEN_INT (2),
                                    GEN_INT (1), GEN_INT (3)));

-      emit_insn (gen_xop_mulv2div2di3_high (operands[0], t1, t2));
+      emit_move_insn (t3, CONST0_RTX (V2DImode));
+
+      emit_insn (gen_xop_pmacsdqh (operands[0], t1, t2, t3));

       DONE;
     }
 
       DONE;
     }
 


@@ -5751,11 +5755,15 @@
 
   if (TARGET_XOP)
     {
 
   if (TARGET_XOP)
     {

+      rtx t3 = gen_reg_rtx (V2DImode);
+

       emit_insn (gen_sse2_pshufd_1 (t1, op1, GEN_INT (0), GEN_INT (2),
                                    GEN_INT (1), GEN_INT (3)));
       emit_insn (gen_sse2_pshufd_1 (t2, op2, GEN_INT (0), GEN_INT (2),
                                    GEN_INT (1), GEN_INT (3)));
       emit_insn (gen_sse2_pshufd_1 (t1, op1, GEN_INT (0), GEN_INT (2),
                                    GEN_INT (1), GEN_INT (3)));
       emit_insn (gen_sse2_pshufd_1 (t2, op2, GEN_INT (0), GEN_INT (2),
                                    GEN_INT (1), GEN_INT (3)));

-      emit_insn (gen_xop_mulv2div2di3_low (operands[0], t1, t2));
+      emit_move_insn (t3, CONST0_RTX (V2DImode));
+
+      emit_insn (gen_xop_pmacsdql (operands[0], t1, t2, t3));

       DONE;
     }
 
       DONE;
     }
 


@@ -10422,12 +10430,12 @@
          (sign_extend:V2DI
           (vec_select:V2SI
            (match_operand:V4SI 1 "nonimmediate_operand" "%x")
          (sign_extend:V2DI
           (vec_select:V2SI
            (match_operand:V4SI 1 "nonimmediate_operand" "%x")

-           (parallel [(const_int 1)
-                      (const_int 3)])))
-         (vec_select:V2SI
+            (parallel [(const_int 0)
+                       (const_int 2)])))
+          (vec_select:V2SI

           (match_operand:V4SI 2 "nonimmediate_operand" "xm")
           (match_operand:V4SI 2 "nonimmediate_operand" "xm")

-          (parallel [(const_int 1)
-                     (const_int 3)])))
+          (parallel [(const_int 0)
+                     (const_int 2)])))

         (match_operand:V2DI 3 "nonimmediate_operand" "x")))]
   "TARGET_XOP"
   "vpmacssdql\t{%3, %2, %1, %0|%0, %1, %2, %3}"
         (match_operand:V2DI 3 "nonimmediate_operand" "x")))]
   "TARGET_XOP"
   "vpmacssdql\t{%3, %2, %1, %0|%0, %1, %2, %3}"


@@ -10441,13 +10449,13 @@
          (sign_extend:V2DI
           (vec_select:V2SI
            (match_operand:V4SI 1 "nonimmediate_operand" "%x")
          (sign_extend:V2DI
           (vec_select:V2SI
            (match_operand:V4SI 1 "nonimmediate_operand" "%x")

-           (parallel [(const_int 0)
-                      (const_int 2)])))
+           (parallel [(const_int 1)
+                      (const_int 3)])))

          (sign_extend:V2DI
           (vec_select:V2SI
            (match_operand:V4SI 2 "nonimmediate_operand" "xm")
          (sign_extend:V2DI
           (vec_select:V2SI
            (match_operand:V4SI 2 "nonimmediate_operand" "xm")

-           (parallel [(const_int 0)
-                      (const_int 2)]))))
+           (parallel [(const_int 1)
+                      (const_int 3)]))))

         (match_operand:V2DI 3 "nonimmediate_operand" "x")))]
   "TARGET_XOP"
   "vpmacssdqh\t{%3, %2, %1, %0|%0, %1, %2, %3}"
         (match_operand:V2DI 3 "nonimmediate_operand" "x")))]
   "TARGET_XOP"
   "vpmacssdqh\t{%3, %2, %1, %0|%0, %1, %2, %3}"


@@ -10461,61 +10469,19 @@
          (sign_extend:V2DI
           (vec_select:V2SI
            (match_operand:V4SI 1 "nonimmediate_operand" "%x")
          (sign_extend:V2DI
           (vec_select:V2SI
            (match_operand:V4SI 1 "nonimmediate_operand" "%x")

-           (parallel [(const_int 1)
-                      (const_int 3)])))
+           (parallel [(const_int 0)
+                      (const_int 2)])))

          (sign_extend:V2DI
           (vec_select:V2SI
            (match_operand:V4SI 2 "nonimmediate_operand" "xm")
          (sign_extend:V2DI
           (vec_select:V2SI
            (match_operand:V4SI 2 "nonimmediate_operand" "xm")

-           (parallel [(const_int 1)
-                      (const_int 3)]))))
+           (parallel [(const_int 0)
+                      (const_int 2)]))))

         (match_operand:V2DI 3 "nonimmediate_operand" "x")))]
   "TARGET_XOP"
   "vpmacsdql\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ssemuladd")
    (set_attr "mode" "TI")])
 
         (match_operand:V2DI 3 "nonimmediate_operand" "x")))]
   "TARGET_XOP"
   "vpmacsdql\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ssemuladd")
    (set_attr "mode" "TI")])
 

-;; We don't have a straight 32-bit parallel multiply and extend on XOP, so
-;; fake it with a multiply/add.  In general, we expect the define_split to
-;; occur before register allocation, so we have to handle the corner case where
-;; the target is the same as operands 1/2
-(define_insn_and_split "xop_mulv2div2di3_low"
-  [(set (match_operand:V2DI 0 "register_operand" "=&x")
-       (mult:V2DI
-         (sign_extend:V2DI
-           (vec_select:V2SI
-             (match_operand:V4SI 1 "register_operand" "%x")
-             (parallel [(const_int 1)
-                        (const_int 3)])))
-         (sign_extend:V2DI
-           (vec_select:V2SI
-             (match_operand:V4SI 2 "nonimmediate_operand" "xm")
-             (parallel [(const_int 1)
-                        (const_int 3)])))))]
-  "TARGET_XOP"
-  "#"
-  "&& reload_completed"
-  [(set (match_dup 0)
-       (match_dup 3))
-   (set (match_dup 0)
-       (plus:V2DI
-        (mult:V2DI
-         (sign_extend:V2DI
-          (vec_select:V2SI
-           (match_dup 1)
-           (parallel [(const_int 1)
-                      (const_int 3)])))
-         (sign_extend:V2DI
-          (vec_select:V2SI
-           (match_dup 2)
-           (parallel [(const_int 1)
-                      (const_int 3)]))))
-        (match_dup 0)))]
-{
-  operands[3] = CONST0_RTX (V2DImode);
-}
-  [(set_attr "type" "ssemul")
-   (set_attr "mode" "TI")])
-

 (define_insn "xop_pmacsdqh"
   [(set (match_operand:V2DI 0 "register_operand" "=x")
        (plus:V2DI
 (define_insn "xop_pmacsdqh"
   [(set (match_operand:V2DI 0 "register_operand" "=x")
        (plus:V2DI


@@ -10523,61 +10489,19 @@
          (sign_extend:V2DI
           (vec_select:V2SI
            (match_operand:V4SI 1 "nonimmediate_operand" "%x")
          (sign_extend:V2DI
           (vec_select:V2SI
            (match_operand:V4SI 1 "nonimmediate_operand" "%x")

-           (parallel [(const_int 0)
-                      (const_int 2)])))
+           (parallel [(const_int 1)
+                      (const_int 3)])))

          (sign_extend:V2DI
           (vec_select:V2SI
            (match_operand:V4SI 2 "nonimmediate_operand" "xm")
          (sign_extend:V2DI
           (vec_select:V2SI
            (match_operand:V4SI 2 "nonimmediate_operand" "xm")

-           (parallel [(const_int 0)
-                      (const_int 2)]))))
+           (parallel [(const_int 1)
+                      (const_int 3)]))))

         (match_operand:V2DI 3 "nonimmediate_operand" "x")))]
   "TARGET_XOP"
   "vpmacsdqh\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ssemuladd")
    (set_attr "mode" "TI")])
 
         (match_operand:V2DI 3 "nonimmediate_operand" "x")))]
   "TARGET_XOP"
   "vpmacsdqh\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ssemuladd")
    (set_attr "mode" "TI")])
 

-;; We don't have a straight 32-bit parallel multiply and extend on XOP, so
-;; fake it with a multiply/add.  In general, we expect the define_split to
-;; occur before register allocation, so we have to handle the corner case where
-;; the target is the same as either operands[1] or operands[2]
-(define_insn_and_split "xop_mulv2div2di3_high"
-  [(set (match_operand:V2DI 0 "register_operand" "=&x")
-       (mult:V2DI
-         (sign_extend:V2DI
-           (vec_select:V2SI
-             (match_operand:V4SI 1 "register_operand" "%x")
-             (parallel [(const_int 0)
-                        (const_int 2)])))
-         (sign_extend:V2DI
-           (vec_select:V2SI
-             (match_operand:V4SI 2 "nonimmediate_operand" "xm")
-             (parallel [(const_int 0)
-                        (const_int 2)])))))]
-  "TARGET_XOP"
-  "#"
-  "&& reload_completed"
-  [(set (match_dup 0)
-       (match_dup 3))
-   (set (match_dup 0)
-       (plus:V2DI
-        (mult:V2DI
-         (sign_extend:V2DI
-          (vec_select:V2SI
-           (match_dup 1)
-           (parallel [(const_int 0)
-                      (const_int 2)])))
-         (sign_extend:V2DI
-          (vec_select:V2SI
-           (match_dup 2)
-           (parallel [(const_int 0)
-                      (const_int 2)]))))
-        (match_dup 0)))]
-{
-  operands[3] = CONST0_RTX (V2DImode);
-}
-  [(set_attr "type" "ssemul")
-   (set_attr "mode" "TI")])
-

 ;; XOP parallel integer multiply/add instructions for the intrinisics
 (define_insn "xop_pmacsswd"
   [(set (match_operand:V4SI 0 "register_operand" "=x")
 ;; XOP parallel integer multiply/add instructions for the intrinisics
 (define_insn "xop_pmacsswd"
   [(set (match_operand:V4SI 0 "register_operand" "=x")

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index dfc86cd..97a7950 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,12 @@
+2012-06-16  Venkataramanan Kumar  <venkataramanan.kumar@amd.com>
+
+       Back port from mainline
+       2012-05-09 Uros Bizjak  <ubizjak@gmail.com>
+
+       PR target/52908
+       * gcc.target/i386/xop-imul32widen-vector.c: Update scan-assembler
+       directive to Scan for vpmuldq, not vpmacsdql.
+

 2012-06-15  Eric Botcazou  <ebotcazou@adacore.com>
 
        * gnat.dg/vect8.ad[sb]: New test.
 2012-06-15  Eric Botcazou  <ebotcazou@adacore.com>
 
        * gnat.dg/vect8.ad[sb]: New test.

diff --git a/gcc/testsuite/gcc.target/i386/xop-imul32widen-vector.c b/gcc/testsuite/gcc.target/i386/xop-imul32widen-vector.c
index 0406d02..0730987 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/xop-imul32widen-vector.c
+++ b/gcc/testsuite/gcc.target/i386/xop-imul32widen-vector.c
@@ -32,5 +32,5 @@ int main ()
   exit (0);
 }
 
   exit (0);
 }
 

-/* { dg-final { scan-assembler "vpmacsdql" } } */
+/* { dg-final { scan-assembler "vpmuldq" } } */

 /* { dg-final { scan-assembler "vpmacsdqh" } } */
 /* { dg-final { scan-assembler "vpmacsdqh" } } */