2013-11-23 Uros Bizjak <ubizjak@gmail.com>
PR target/56788
* config/i386/i386.c (bdesc_multi_arg) <IX86_BUILTIN_VFRCZSS>:
Declare as MULTI_ARG_1_SF instruction.
<IX86_BUILTIN_VFRCZSD>: Decleare as MULTI_ARG_1_DF instruction.
* config/i386/sse.md (*xop_vmfrcz<mode>2): Rename
from *xop_vmfrcz_<mode>.
* config/i386/xopintrin.h (_mm_frcz_ss): Use __builtin_ia32_movss
to merge scalar result with __A.
(_mm_frcz_sd): Use __builtin_ia32_movsd to merge scalar
result with __A.
testsuite/ChangeLog:
Backport from mainline
2013-11-27 Uros Bizjak <ubizjak@gmail.com>
Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
PR target/56788
* gcc.target/i386/xop-frczX.c: New test.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_7-branch@205497
138bc75d-0d04-0410-961f-
82ee72b054a4
+2013-11-28 Uros Bizjak <ubizjak@gmail.com>
+
+ Backport from mainline
+ 2013-11-23 Uros Bizjak <ubizjak@gmail.com>
+
+ PR target/56788
+ * config/i386/i386.c (bdesc_multi_arg) <IX86_BUILTIN_VFRCZSS>:
+ Declare as MULTI_ARG_1_SF instruction.
+ <IX86_BUILTIN_VFRCZSD>: Decleare as MULTI_ARG_1_DF instruction.
+ * config/i386/sse.md (*xop_vmfrcz<mode>2): Rename
+ from *xop_vmfrcz_<mode>.
+ * config/i386/xopintrin.h (_mm_frcz_ss): Use __builtin_ia32_movss
+ to merge scalar result with __A.
+ (_mm_frcz_sd): Use __builtin_ia32_movsd to merge scalar
+ result with __A.
+
2013-11-19 Uros Bizjak <ubizjak@gmail.com>
Backport from mainline
{ OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI },
{ OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI },
- { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_2_SF },
- { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_2_DF },
+ { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_1_SF },
+ { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_1_DF },
{ OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2, "__builtin_ia32_vfrczps", IX86_BUILTIN_VFRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF },
{ OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2, "__builtin_ia32_vfrczpd", IX86_BUILTIN_VFRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF },
{ OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2, "__builtin_ia32_vfrczps256", IX86_BUILTIN_VFRCZPS256, UNKNOWN, (int)MULTI_ARG_1_SF2 },
[(set_attr "type" "ssecvt1")
(set_attr "mode" "<MODE>")])
-;; scalar insns
(define_expand "xop_vmfrcz<mode>2"
[(set (match_operand:VF_128 0 "register_operand")
(vec_merge:VF_128
(match_dup 3)
(const_int 1)))]
"TARGET_XOP"
-{
- operands[3] = CONST0_RTX (<MODE>mode);
-})
+ "operands[3] = CONST0_RTX (<MODE>mode);")
-(define_insn "*xop_vmfrcz_<mode>"
+(define_insn "*xop_vmfrcz<mode>2"
[(set (match_operand:VF_128 0 "register_operand" "=x")
(vec_merge:VF_128
(unspec:VF_128
extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
_mm_frcz_ss (__m128 __A, __m128 __B)
{
- return (__m128) __builtin_ia32_vfrczss ((__v4sf)__A, (__v4sf)__B);
+ return (__m128) __builtin_ia32_movss ((__v4sf)__A,
+ (__v4sf)
+ __builtin_ia32_vfrczss ((__v4sf)__B));
}
extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
_mm_frcz_sd (__m128d __A, __m128d __B)
{
- return (__m128d) __builtin_ia32_vfrczsd ((__v2df)__A, (__v2df)__B);
+ return (__m128d) __builtin_ia32_movsd ((__v2df)__A,
+ (__v2df)
+ __builtin_ia32_vfrczsd ((__v2df)__B));
}
extern __inline __m256 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
+2013-11-28 Uros Bizjak <ubizjak@gmail.com>
+
+ Backport from mainline
+ 2013-11-27 Uros Bizjak <ubizjak@gmail.com>
+ Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
+
+ PR target/56788
+ * gcc.target/i386/xop-frczX.c: New test.
+
2013-11-25 Vidya Praveen <vidyapraveen@arm.com>
Backport from mainline
--- /dev/null
+/* { dg-do run } */
+/* { dg-require-effective-target xop } */
+/* { dg-options "-O2 -mxop" } */
+
+#include "xop-check.h"
+
+#include <x86intrin.h>
+
+void
+check_mm_vmfrcz_sd (__m128d __A, __m128d __B)
+{
+ union128d a, b, c;
+ double d[2];
+
+ a.x = __A;
+ b.x = __B;
+ c.x = _mm_frcz_sd (__A, __B);
+ d[0] = b.a[0] - (int)b.a[0] ;
+ d[1] = a.a[1];
+ if (check_union128d (c, d))
+ abort ();
+}
+
+void
+check_mm_vmfrcz_ss (__m128 __A, __m128 __B)
+{
+ union128 a, b, c;
+ float f[4];
+
+ a.x = __A;
+ b.x = __B;
+ c.x = _mm_frcz_ss (__A, __B);
+ f[0] = b.a[0] - (int)b.a[0] ;
+ f[1] = a.a[1];
+ f[2] = a.a[2];
+ f[3] = a.a[3];
+ if (check_union128 (c, f))
+ abort ();
+}
+
+static void
+xop_test (void)
+{
+ union128 a, b;
+ union128d c,d;
+ int i;
+
+ for (i = 0; i < 4; i++)
+ {
+ a.a[i] = i + 3.5;
+ b.a[i] = i + 7.9;
+ }
+ for (i = 0; i < 2; i++)
+ {
+ c.a[i] = i + 3.5;
+ d.a[i] = i + 7.987654321;
+ }
+ check_mm_vmfrcz_ss (a.x, b.x);
+ check_mm_vmfrcz_sd (c.x, d.x);
+}
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