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* config/mcore/mcore.c (TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE):
authorsteven <steven@138bc75d-0d04-0410-961f-82ee72b054a4>
Tue, 6 Jul 2004 07:12:32 +0000 (07:12 +0000)
committersteven <steven@138bc75d-0d04-0410-961f-82ee72b054a4>
Tue, 6 Jul 2004 07:12:32 +0000 (07:12 +0000)
Define.
* config/mcore/mcore.md: Model memory latency with a simple DFA
pipeline description instead of a define_function_unit.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@84146 138bc75d-0d04-0410-961f-82ee72b054a4

gcc/ChangeLog
gcc/config/mcore/mcore.c
gcc/config/mcore/mcore.md

index 878bc56..9255926 100644 (file)
@@ -1,3 +1,10 @@
+2004-07-06  Steven Bosscher  <stevenb@suse.de>
+
+       * config/mcore/mcore.c (TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE):
+       Define.
+       * config/mcore/mcore.md: Model memory latency with a simple DFA
+       pipeline description instead of a define_function_unit.
+
 2004-07-05  Richard Kenner  <kenner@vlsi1.ultra.nyu.edu>
 
        * langhooks-def.h (LANG_HOOKS_TREE_INLINING_VAR_MOD_TYPE_P): Extra arg.
index 468b7d1..97d06d0 100644 (file)
@@ -196,6 +196,9 @@ static bool       mcore_return_in_memory    (tree, tree);
 #undef  TARGET_SETUP_INCOMING_VARARGS
 #define TARGET_SETUP_INCOMING_VARARGS  mcore_setup_incoming_varargs
 
+#undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
+#define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE hook_int_void_1
+
 struct gcc_target targetm = TARGET_INITIALIZER;
 \f
 /* Adjust the stack and return the number of bytes taken to do it.  */
index f57da64..32cb71c 100644 (file)
 ;; calculations and the literal table placement into the assembler,
 ;; where their interactions can be managed in a single place.
 
-; All MCORE instructions are two bytes long.
+;; All MCORE instructions are two bytes long.
 
 (define_attr "length" "" (const_int 2))
 
-;; (define_function_unit {name} {num-units} {n-users} {test}
-;;                       {ready-delay} {issue-delay} [{conflict-list}])
-                                     
-
-(define_function_unit "memory" 1 1 (eq_attr "type" "load") 2 0)
+;; Scheduling.  We only model a simple load latency.
+(define_insn_reservation "any_insn" 1
+                        (eq_attr "type" "!load")
+                        "nothing")
+(define_insn_reservation "memory" 2
+                        (eq_attr "type" "load")
+                        "nothing")
 
 ;; -------------------------------------------------------------------------
 ;; Test and bit test