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* config/i386/i386.md: Use {} for multi-line preparation statements.
authoruros <uros@138bc75d-0d04-0410-961f-82ee72b054a4>
Thu, 3 Nov 2011 16:59:37 +0000 (16:59 +0000)
committeruros <uros@138bc75d-0d04-0410-961f-82ee72b054a4>
Thu, 3 Nov 2011 16:59:37 +0000 (16:59 +0000)
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@180832 138bc75d-0d04-0410-961f-82ee72b054a4

gcc/ChangeLog
gcc/config/i386/i386.md

index 47e1621..539551a 100644 (file)
@@ -1,3 +1,7 @@
+2011-11-03  Uros Bizjak  <ubizjak@gmail.com>
+
+       * config/i386/i386.md: Use {} for multi-line preparation statements.
+
 2011-11-03  Eric Botcazou  <ebotcazou@adacore.com>
 
        * config/sparc/sparc.md (movtf_insn_sp32_no_fpu): Consolidate into...
 2011-11-02  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>
            Paolo Bonzini  <bonzini@gnu.org>
 
-       * configure.ac (libgcc_tm_file_list, libgcc_tm_include_list):
-       Remove.
+       * configure.ac (libgcc_tm_file_list, libgcc_tm_include_list): Remove.
        * configure: Regenerate.
        * Makefile.in (libgcc_tm_file_list, libgcc_tm_include_list): Remove.
        (TM_H): Remove libgcc_tm.h, $(libgcc_tm_file_list).
        * config/t-libunwind (TARGET_LIBGCC2_CFLAGS): Remove.
        * config/t-linux: Remove.
        * config/t-lynx (TARGET_LIBGCC2_CFLAGS, LIBGCC, INSTALL_LIBGCC):
-       Remove
+       Remove.
        * config/t-openbsd-thread: Move to ../libgcc/config.
        * config/t-rtems (LIBGCC2_INCLUDES): Remove.
        * config/t-sol2 (TARGET_LIBGCC2_CFLAGS): Remove.
        * config/vxlib.c, config/vxlib-tls.c: Move to ../libgcc/config.
        * config/alpha/qrnnd.asm: Move to ../libgcc/config/alpha/qrnnd.S.
        * config/alpha/t-alpha, config/alpha/t-ieee: Remove.
-       * config/alpha/t-vms (LIB2FUNCS_EXTRA, LIBGCC, INSTALL_LIBGCC):
-       Remove.
+       * config/alpha/t-vms (LIB2FUNCS_EXTRA, LIBGCC, INSTALL_LIBGCC): Remove.
        * config/alpha/vms-gcc_shell_handler.c: Move to ../libgcc/config/alpha.
        * config/arm/bpabi.c, config/arm/unaligned-funcs.c,
        config/arm/fp16.c, config/arm/linux-atomic.c,
        config/c6x/gef.c, config/c6x/gtd.c, config/c6x/gtf.c,
        config/c6x/led.c, config/c6x/lef.c, config/c6x/ltd.c,
        config/c6x/ltf.c: Move to ../libgcc/config/c6x.
-       * config/c6x/t-c6x-elf (LIB2FUNCS_EXCLUDE, LIB2FUNCS_EXTRA):
-       Remove.
+       * config/c6x/t-c6x-elf (LIB2FUNCS_EXCLUDE, LIB2FUNCS_EXTRA): Remove.
        * config/c6x/t-c6x-uclinux (TARGET_LIBGCC2_CFLAGS): Remove.
        * config/cris/arit.c: Move to ../libgcc/config/cris.
        * config/cris/cris_abi_symbol.c: Remove.
        (LIB2FUNCS_STATIC_EXTRA, tramp.S, crtsavfpr.S, crtresfpr.S)
        (crtsavgpr.S, crtresgpr.S, crtresxfpr.S, crtresxgpr.S, LIBGCC)
        (INSTALL_LIBGCC, $(T)crtsavfpr$(objext), $(T)crtresfpr$(objext))
-       (($(T)crtsavgpr$(objext), $(T)crtresgpr$(objext),
-       $(T)crtresxfpr$(objext), $(T)crtresxgpr$(objext)): Remove.
+       ($(T)crtsavgpr$(objext), $(T)crtresgpr$(objext))
+       ($(T)crtresxfpr$(objext), $(T)crtresxgpr$(objext)): Remove.
        * config/rs6000/t-ppccomm (LIB2FUNCS_EXTRA)
        (LIB2FUNCS_STATIC_EXTRA, eabi.S, tramp.S): Remove.
        * config/rs6000/t-spe (LIBGCC, INSTALL_LIBGCC): Remove.
        (*-*-netbsd*): Remove t-libgcc-pic from tmake_file.
        (*-*-openbsd*): Likewise.
        Remove t-openbsd-thread for posix threads.
-       (alpha*-*-linux*): Remove alpha/t-alpha, alpha/t-ieee
-       from tmake_file.
+       (alpha*-*-linux*): Remove alpha/t-alpha, alpha/t-ieee from tmake_file.
        (alpha*-*-freebsd*): Likewise.
        (alpha*-*-netbsd*): Likewise.
        (alpha*-*-openbsd*): Likewise.
        * config/arm/t-wince-pe: Likewise.
        * config/avr/libgcc.S: Move to ../libgcc/config/avr.
        * config/avr/t-avr (LIB1ASMSRC, LIB1ASMFUNCS): Remove.
-       * config/bfin/lib1funcs.asm: Move to
-       ../libgcc/config/bfin/lib1funcs.S.
+       * config/bfin/lib1funcs.asm: Move to ../libgcc/config/bfin/lib1funcs.S.
        * config/bfin/t-bfin: Remove.
        * config/bfin/t-bfin-elf (LIB1ASMSRC, LIB1ASMFUNCS): Remove.
        * config/bfin/t-bfin-linux: Likewise.
        * config/bfin/t-bfin-uclinux: Likewise.
-       * config/c6x/lib1funcs.asm: Move to
-       ../libgcc/config/c6x/lib1funcs.S.
+       * config/c6x/lib1funcs.asm: Move to ../libgcc/config/c6x/lib1funcs.S.
        * config/c6x/t-c6x-elf (LIB1ASMSRC, LIB1ASMFUNCS): Remove.
-       * config/fr30/lib1funcs.asm: Move to
-       ../libgcc/config/fr30/lib1funcs.S.
+       * config/fr30/lib1funcs.asm: Move to ../libgcc/config/fr30/lib1funcs.S.
        * config/fr30/t-fr30 (LIB1ASMSRC, LIB1ASMFUNCS): Remove.
-       * config/frv/lib1funcs.asm: Move to
-       ../libgcc/config/frv/lib1funcs.S.
+       * config/frv/lib1funcs.asm: Move to ../libgcc/config/frv/lib1funcs.S.
        * config/frv/t-frv (CROSS_LIBGCC1, LIB1ASMSRC, LIB1ASMFUNCS): Remove.
        * config/h8300/fixunssfsi.c: Update lib1funcs.asm filename.
        * config/h8300/lib1funcs.asm: Move to
        * config/i386/cygwin.asm: Move to ../libgcc/config/i386/cygwin.S.
        * config/i386/t-cygming (LIB1ASMSRC, LIB1ASMFUNCS): Remove.
        * config/i386/t-interix: Likewise.
-       * config/ia64/lib1funcs.asm: Move to
-       ../libgcc/config/ia64/lib1funcs.S.
+       * config/ia64/lib1funcs.asm: Move to ../libgcc/config/ia64/lib1funcs.S.
        * config/ia64/t-hpux (LIB1ASMFUNCS, LIBGCC1_TEST): Remove.
        * config/ia64/t-ia64 (LIB1ASMSRC, LIB1ASMFUNCS): Remove.
        * config/iq2000/t-iq2000 (LIBGCC1, CROSS_LIBGCC1): Remove.
        t-libc-ok from tmake_file.
        (i[34567]86-*-linux*, i[34567]86-*-kfreebsd*-gnu,
        i[34567]86-*-knetbsd*-gnu, i[34567]86-*-gnu*,
-       i[34567]86-*-kopensolaris*-gnu): Remove i386/t-crtstuff from tmake_file.
+       i[34567]86-*-kopensolaris*-gnu): Remove i386/t-crtstuff from
+       tmake_file.
        Remove extra_parts.
        (x86_64-*-linux*, x86_64-*-kfreebsd*-gnu, x86_64-*-knetbsd*-gnu):
        Remove i386/t-crtstuff from tmake_file.
        * config/i386/t-i386elf: Remove.
        * config/i386/t-linux64 (EXTRA_MULTILIB_PARTS): Remove.
        * config/i386/t-nto (CRTSTUFF_T_CFLAGS, EXTRA_PARTS): Remove.
-       * config/ia64/crtbegin.asm: Move to
-       ../libgcc/config/ia64/crtbegin.S.
-       * config/ia64/crtend.asm: Move to
-       ../libgcc/config/ia64/crtend.S.
+       * config/ia64/crtbegin.asm: Move to ../libgcc/config/ia64/crtbegin.S.
+       * config/ia64/crtend.asm: Move to ../libgcc/config/ia64/crtend.S.
        * config/ia64/crti.asm: Move to ../libgcc/config/ia64/crti.S.
        * config/ia64/crtn.asm: Move to ../libgcc/config/ia64/crtn.S.
        * config/ia64/t-vms: Remove.
        * config/rs6000/t-ppccomm (EXTRA_MULTILIB_PARTS): Remove.
        (ecrti.S, ecrtn.S, ncrti.S, ncrtn.S): Remove.
        ($(T)ecrti$(objext), $(T)ecrtn$(objext), $(T)ncrti$(objext),
-       $(T)ncrtn$(objext)): Remove.
+       ($(T)ncrtn$(objext)): Remove.
        (CRTSTUFF_T_CFLAGS, CRTSTUFF_T_CFLAGS_S): Remove.
        * config/rs6000/t-vxworks (EXTRA_MULTILIB_PARTS): Remove.
        * config/rx/t-rx (EXTRA_MULTILIB_PARTS): Remove.
        * config/vms/vms-ucrt0.c: Move to ../libgcc/config/vms.
        * config/xtensa/crti.asm: Move to ../libgcc/config/xtensa/crti.S.
        * config/xtensa/crtn.asm: Move to ../libgcc/config/xtensa/crtn.S.
-       * config/xtensa/t-elf (CRTSTUFF_T_CFLAGS, CRTSTUFF_T_CFLAGS_S):
-       Remove.
+       * config/xtensa/t-elf (CRTSTUFF_T_CFLAGS, CRTSTUFF_T_CFLAGS_S): Remove.
        (EXTRA_MULTILIB_PARTS): Remove.
        * config/xtensa/t-linux: Remove.
        * config/xtensa/t-xtensa ($(T)crti.o, $(T)crtn.o): Remove.
 
        PR target/50940
        * config/i386/i386.md (floatsi<mode>2_vector_sse_with_temp splitter):
-       Compare <ssevecmode>mode with V4SFmode, not V4SImode.
+       Compare <ssevecmode>mode to V4SFmode, not V4SImode.
 
 2011-11-01  Peter Bergner  <bergner@vnet.ibm.com>
 
index 11c866b..6fe06b4 100644 (file)
          [(and:SI (zero_extract:SI (match_dup 2) (const_int 8) (const_int 8))
                   (match_dup 3))
           (const_int 0)]))]
-  "operands[2] = gen_lowpart (SImode, operands[2]);
-   operands[3] = gen_int_mode (INTVAL (operands[3]) >> 8, SImode);")
+{
+  operands[2] = gen_lowpart (SImode, operands[2]);
+  operands[3] = gen_int_mode (INTVAL (operands[3]) >> 8, SImode);
+})
 
 (define_split
   [(set (match_operand 0 "flags_reg_operand" "")
   [(set (match_dup 0)
        (match_op_dup 1 [(and:QI (match_dup 2) (match_dup 3))
                         (const_int 0)]))]
-  "operands[2] = gen_lowpart (QImode, operands[2]);
-   operands[3] = gen_lowpart (QImode, operands[3]);")
+{
+  operands[2] = gen_lowpart (QImode, operands[2]);
+  operands[3] = gen_lowpart (QImode, operands[3]);
+})
 
 ;; %%% This used to optimize known byte-wide and operations to memory,
 ;; and sometimes to QImode registers.  If this is considered useful,
                                            (const_int 8) (const_int 8))
                           (match_dup 2)))
              (clobber (reg:CC FLAGS_REG))])]
-  "operands[0] = gen_lowpart (SImode, operands[0]);
-   operands[1] = gen_lowpart (SImode, operands[1]);
-   operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);")
+{
+  operands[0] = gen_lowpart (SImode, operands[0]);
+  operands[1] = gen_lowpart (SImode, operands[1]);
+  operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);
+})
 
 ;; Since AND can be encoded with sign extended immediate, this is only
 ;; profitable when 7th bit is not set.
                   (and:QI (match_dup 1)
                           (match_dup 2)))
              (clobber (reg:CC FLAGS_REG))])]
-  "operands[0] = gen_lowpart (QImode, operands[0]);
-   operands[1] = gen_lowpart (QImode, operands[1]);
-   operands[2] = gen_lowpart (QImode, operands[2]);")
+{
+  operands[0] = gen_lowpart (QImode, operands[0]);
+  operands[1] = gen_lowpart (QImode, operands[1]);
+  operands[2] = gen_lowpart (QImode, operands[2]);
+})
 \f
 ;; Logical inclusive and exclusive OR instructions
 
                                               (const_int 8) (const_int 8))
                              (match_dup 2)))
              (clobber (reg:CC FLAGS_REG))])]
-  "operands[0] = gen_lowpart (SImode, operands[0]);
-   operands[1] = gen_lowpart (SImode, operands[1]);
-   operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);")
+{
+  operands[0] = gen_lowpart (SImode, operands[0]);
+  operands[1] = gen_lowpart (SImode, operands[1]);
+  operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);
+})
 
 ;; Since OR can be encoded with sign extended immediate, this is only
 ;; profitable when 7th bit is set.
                   (any_or:QI (match_dup 1)
                              (match_dup 2)))
              (clobber (reg:CC FLAGS_REG))])]
-  "operands[0] = gen_lowpart (QImode, operands[0]);
-   operands[1] = gen_lowpart (QImode, operands[1]);
-   operands[2] = gen_lowpart (QImode, operands[2]);")
+{
+  operands[0] = gen_lowpart (QImode, operands[0]);
+  operands[1] = gen_lowpart (QImode, operands[1]);
+  operands[2] = gen_lowpart (QImode, operands[2]);
+})
 
 (define_expand "xorqi_cc_ext_1"
   [(parallel [
 
   ;; The % modifier is not operational anymore in peephole2's, so we have to
   ;; swap the operands manually in the case of addition and multiplication.
-  "if (COMMUTATIVE_ARITH_P (operands[2]))
-     operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[2]),
-                                  GET_MODE (operands[2]),
-                                  operands[0], operands[1]);
-   else
-     operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[2]),
-                                  GET_MODE (operands[2]),
-                                  operands[1], operands[0]);")
+{
+  rtx op0, op1;
+
+  if (COMMUTATIVE_ARITH_P (operands[2]))
+    op0 = operands[0], op1 = operands[1];
+  else
+    op0 = operands[1], op1 = operands[0];
+
+  operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[2]),
+                               GET_MODE (operands[2]),
+                               op0, op1);
+})
 
 ;; Conditional addition patterns
 (define_expand "add<mode>cc"
   [(parallel [(set (match_dup 0)
                   (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
              (clobber (reg:CC FLAGS_REG))])]
-  "operands[0] = gen_lowpart (SImode, operands[0]);
-   operands[1] = gen_lowpart (SImode, operands[1]);
-   if (GET_CODE (operands[3]) != ASHIFT)
-     operands[2] = gen_lowpart (SImode, operands[2]);
-   PUT_MODE (operands[3], SImode);")
+{
+  operands[0] = gen_lowpart (SImode, operands[0]);
+  operands[1] = gen_lowpart (SImode, operands[1]);
+  if (GET_CODE (operands[3]) != ASHIFT)
+    operands[2] = gen_lowpart (SImode, operands[2]);
+  PUT_MODE (operands[3], SImode);
+})
 
 ; Promote the QImode tests, as i386 has encoding of the AND
 ; instruction with 32-bit sign-extended immediate and thus the
   [(parallel [(set (match_dup 0)
                   (neg:SI (match_dup 1)))
              (clobber (reg:CC FLAGS_REG))])]
-  "operands[0] = gen_lowpart (SImode, operands[0]);
-   operands[1] = gen_lowpart (SImode, operands[1]);")
+{
+  operands[0] = gen_lowpart (SImode, operands[0]);
+  operands[1] = gen_lowpart (SImode, operands[1]);
+})
 
 (define_split
   [(set (match_operand 0 "register_operand" "")
               || optimize_insn_for_size_p ())))"
   [(set (match_dup 0)
        (not:SI (match_dup 1)))]
-  "operands[0] = gen_lowpart (SImode, operands[0]);
-   operands[1] = gen_lowpart (SImode, operands[1]);")
+{
+  operands[0] = gen_lowpart (SImode, operands[0]);
+  operands[1] = gen_lowpart (SImode, operands[1]);
+})
 
 (define_split
   [(set (match_operand 0 "register_operand" "")
               || optimize_insn_for_size_p ())))"
   [(set (match_dup 0)
        (if_then_else:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
-  "operands[0] = gen_lowpart (SImode, operands[0]);
-   operands[2] = gen_lowpart (SImode, operands[2]);
-   operands[3] = gen_lowpart (SImode, operands[3]);")
+{
+  operands[0] = gen_lowpart (SImode, operands[0]);
+  operands[2] = gen_lowpart (SImode, operands[2]);
+  operands[3] = gen_lowpart (SImode, operands[3]);
+})
 \f
 ;; RTL Peephole optimizations, run before sched2.  These primarily look to
 ;; transform a complex memory operation into two memory to register operations.
   [(parallel [(set (match_dup 4) (match_dup 5))
              (set (match_dup 1) (match_op_dup 3 [(match_dup 1)
                                                  (match_dup 2)]))])]
-  "operands[4] = SET_DEST (PATTERN (peep2_next_insn (3)));
-   operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), <MODE>mode,
-                                copy_rtx (operands[1]),
-                                copy_rtx (operands[2]));
-   operands[5] = gen_rtx_COMPARE (GET_MODE (operands[4]),
-                                 operands[5], const0_rtx);")
+{
+  operands[4] = SET_DEST (PATTERN (peep2_next_insn (3)));
+  operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), <MODE>mode,
+                               copy_rtx (operands[1]),
+                               copy_rtx (operands[2]));
+  operands[5] = gen_rtx_COMPARE (GET_MODE (operands[4]),
+                                operands[5], const0_rtx);
+})
 
 (define_peephole2
   [(parallel [(set (match_operand:SWI 0 "register_operand" "")
   [(parallel [(set (match_dup 3) (match_dup 4))
              (set (match_dup 1) (match_op_dup 2 [(match_dup 1)
                                                  (match_dup 0)]))])]
-  "operands[3] = SET_DEST (PATTERN (peep2_next_insn (2)));
-   operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[2]), <MODE>mode,
-                                copy_rtx (operands[1]),
-                                copy_rtx (operands[0]));
-   operands[4] = gen_rtx_COMPARE (GET_MODE (operands[3]),
-                                 operands[4], const0_rtx);")
+{
+  operands[3] = SET_DEST (PATTERN (peep2_next_insn (2)));
+  operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[2]), <MODE>mode,
+                               copy_rtx (operands[1]),
+                               copy_rtx (operands[0]));
+  operands[4] = gen_rtx_COMPARE (GET_MODE (operands[3]),
+                                operands[4], const0_rtx);
+})
 
 (define_peephole2
   [(set (match_operand:SWI12 0 "register_operand" "")
                         ? CCGOCmode : CCNOmode)"
   [(parallel [(set (match_dup 4) (match_dup 5))
              (set (match_dup 1) (match_dup 6))])]
-  "operands[2] = gen_lowpart (<MODE>mode, operands[2]);
-   operands[4] = SET_DEST (PATTERN (peep2_next_insn (3)));
-   operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), <MODE>mode,
-                                copy_rtx (operands[1]), operands[2]);
-   operands[5] = gen_rtx_COMPARE (GET_MODE (operands[4]),
-                                 operands[5], const0_rtx);
-   operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[3]), <MODE>mode,
-                                copy_rtx (operands[1]),
-                                copy_rtx (operands[2]));")
+{
+  operands[2] = gen_lowpart (<MODE>mode, operands[2]);
+  operands[4] = SET_DEST (PATTERN (peep2_next_insn (3)));
+  operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), <MODE>mode,
+                               copy_rtx (operands[1]), operands[2]);
+  operands[5] = gen_rtx_COMPARE (GET_MODE (operands[4]),
+                                operands[5], const0_rtx);
+  operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[3]), <MODE>mode,
+                               copy_rtx (operands[1]),
+                               copy_rtx (operands[2]));
+})
 
 ;; Attempt to always use XOR for zeroing registers.
 (define_peephole2
                     (match_operand:SI 3 "const_int_operand" "i")]
                    UNSPECV_LWPVAL_INTRINSIC)]
   "TARGET_LWP"
-  "/* Avoid unused variable warning.  */
-   (void) operand0;")
+  ;; Avoid unused variable warning.
+  "(void) operand0;")
 
 (define_insn "*lwp_lwpval<mode>3_1"
   [(unspec_volatile [(match_operand:SWI48 0 "register_operand" "r")