OSDN Git Service

2006-09-07 H.J. Lu <hongjiu.lu@intel.com>
authorhjl <hjl@138bc75d-0d04-0410-961f-82ee72b054a4>
Thu, 7 Sep 2006 17:53:18 +0000 (17:53 +0000)
committerhjl <hjl@138bc75d-0d04-0410-961f-82ee72b054a4>
Thu, 7 Sep 2006 17:53:18 +0000 (17:53 +0000)
* config/i386/i386.c (x86_partial_flag_reg_stall): New.

* config/i386/i386.h (x86_partial_flag_reg_stall): New.
(TARGET_PARTIAL_FLAG_REG_STALL): New.

* config/i386/i386.md (*ashldi3_cmp_rex64): Disabled for
TARGET_PARTIAL_FLAG_REG_STALL.
(*ashldi3_cconly_rex64): Likewise.
(*ashlsi3_cmp): Likewise.
(*ashlsi3_cconly): Likewise.
(*ashlsi3_cmp_zext): Likewise.
(*ashlhi3_cmp): Likewise.
(*ashlhi3_cconly): Likewise.
(*ashlqi3_cmp): Likewise.
(*ashlqi3_cconly): Likewise.
(*ashrdi3_cmp_rex64): Likewise.
(*ashrdi3_cconly_rex64): Likewise.
(*ashrsi3_cmp): Likewise.
(*ashrsi3_cconly): Likewise.
(*ashrsi3_cmp_zext): Likewise.
(*ashrhi3_cmp): Likewise.
(*ashrhi3_cconly): Likewise.
(*ashrqi3_cmp): Likewise.
(*ashrqi3_cconly): Likewise.
(*lshrdi3_cmp_rex64): Likewise.
(*lshrdi3_cconly_rex64): Likewise.
(*lshrsi3_cmp): Likewise.
(*lshrsi3_cconly): Likewise.
(*lshrsi3_cmp_zext): Likewise.
(*lshrhi3_cmp): Likewise.
(*lshrhi3_cconly): Likewise.
(*lshrqi2_cmp): Likewise.
(*lshrqi2_cconly): Likewise.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@116757 138bc75d-0d04-0410-961f-82ee72b054a4

gcc/ChangeLog
gcc/config/i386/i386.c
gcc/config/i386/i386.h
gcc/config/i386/i386.md

index 8d02f20..ec6214a 100644 (file)
@@ -1,3 +1,39 @@
+2006-09-07  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * config/i386/i386.c (x86_partial_flag_reg_stall): New.
+
+       * config/i386/i386.h (x86_partial_flag_reg_stall): New.
+       (TARGET_PARTIAL_FLAG_REG_STALL): New.
+
+       * config/i386/i386.md (*ashldi3_cmp_rex64): Disabled for
+       TARGET_PARTIAL_FLAG_REG_STALL.
+       (*ashldi3_cconly_rex64): Likewise.
+       (*ashlsi3_cmp): Likewise.
+       (*ashlsi3_cconly): Likewise.
+       (*ashlsi3_cmp_zext): Likewise.
+       (*ashlhi3_cmp): Likewise.
+       (*ashlhi3_cconly): Likewise.
+       (*ashlqi3_cmp): Likewise.
+       (*ashlqi3_cconly): Likewise.
+       (*ashrdi3_cmp_rex64): Likewise.
+       (*ashrdi3_cconly_rex64): Likewise.
+       (*ashrsi3_cmp): Likewise.
+       (*ashrsi3_cconly): Likewise.
+       (*ashrsi3_cmp_zext): Likewise.
+       (*ashrhi3_cmp): Likewise.
+       (*ashrhi3_cconly): Likewise.
+       (*ashrqi3_cmp): Likewise.
+       (*ashrqi3_cconly): Likewise.
+       (*lshrdi3_cmp_rex64): Likewise.
+       (*lshrdi3_cconly_rex64): Likewise.
+       (*lshrsi3_cmp): Likewise.
+       (*lshrsi3_cconly): Likewise.
+       (*lshrsi3_cmp_zext): Likewise.
+       (*lshrhi3_cmp): Likewise.
+       (*lshrhi3_cconly): Likewise.
+       (*lshrqi2_cmp): Likewise.
+       (*lshrqi2_cconly): Likewise.
+
 2006-09-07 Uros Bizjak <uros@kss-loka.si>
 
        PR target/28946
index a7f3c0d..f668782 100644 (file)
@@ -761,6 +761,7 @@ const int x86_use_sahf = m_PPRO | m_K6 | m_PENT4 | m_NOCONA | m_GENERIC32; /*m_G
    with partial reg. dependencies used by Athlon/P4 based chips, it is better
    to leave it off for generic32 for now.  */
 const int x86_partial_reg_stall = m_PPRO;
+const int x86_partial_flag_reg_stall = m_GENERIC;
 const int x86_use_himode_fiop = m_386 | m_486 | m_K6;
 const int x86_use_simode_fiop = ~(m_PPRO | m_ATHLON_K8 | m_PENT | m_GENERIC);
 const int x86_use_mov0 = m_K6;
index 10b446b..19cc591 100644 (file)
@@ -164,6 +164,7 @@ extern const int x86_use_bt;
 extern const int x86_cmpxchg, x86_cmpxchg8b, x86_cmpxchg16b, x86_xadd;
 extern const int x86_use_incdec;
 extern const int x86_pad_returns;
+extern const int x86_partial_flag_reg_stall;
 extern int x86_prefetch_sse;
 
 #define TARGET_USE_LEAVE (x86_use_leave & TUNEMASK)
@@ -182,6 +183,7 @@ extern int x86_prefetch_sse;
 #define TARGET_USE_SAHF ((x86_use_sahf & TUNEMASK) && !TARGET_64BIT)
 #define TARGET_MOVX (x86_movx & TUNEMASK)
 #define TARGET_PARTIAL_REG_STALL (x86_partial_reg_stall & TUNEMASK)
+#define TARGET_PARTIAL_FLAG_REG_STALL (x86_partial_flag_reg_stall & TUNEMASK)
 #define TARGET_USE_HIMODE_FIOP (x86_use_himode_fiop & TUNEMASK)
 #define TARGET_USE_SIMODE_FIOP (x86_use_simode_fiop & TUNEMASK)
 #define TARGET_USE_MOV0 (x86_use_mov0 & TUNEMASK)
index f9be68f..639f0b4 100644 (file)
    (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
        (ashift:DI (match_dup 1) (match_dup 2)))]
   "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
-   && ix86_binary_operator_ok (ASHIFT, DImode, operands)"
+   && ix86_binary_operator_ok (ASHIFT, DImode, operands)
+   && (optimize_size
+       || !TARGET_PARTIAL_FLAG_REG_STALL
+       || (operands[2] == const1_rtx
+          && (TARGET_SHIFT1
+              || (TARGET_DOUBLE_WITH_ADD && REG_P (operands[0])))))"
 {
   switch (get_attr_type (insn))
     {
          (const_int 0)))
    (clobber (match_scratch:DI 0 "=r"))]
   "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
-   && ix86_binary_operator_ok (ASHIFT, DImode, operands)"
+   && ix86_binary_operator_ok (ASHIFT, DImode, operands)
+   && (optimize_size
+       || !TARGET_PARTIAL_FLAG_REG_STALL
+       || (operands[2] == const1_rtx
+          && (TARGET_SHIFT1
+              || TARGET_DOUBLE_WITH_ADD)))"
 {
   switch (get_attr_type (insn))
     {
    (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
        (ashift:SI (match_dup 1) (match_dup 2)))]
   "ix86_match_ccmode (insn, CCGOCmode)
-   && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
+   && ix86_binary_operator_ok (ASHIFT, SImode, operands)
+   && (optimize_size
+       || !TARGET_PARTIAL_FLAG_REG_STALL
+       || (operands[2] == const1_rtx
+          && (TARGET_SHIFT1
+              || (TARGET_DOUBLE_WITH_ADD && REG_P (operands[0])))))"
 {
   switch (get_attr_type (insn))
     {
          (const_int 0)))
    (clobber (match_scratch:SI 0 "=r"))]
   "ix86_match_ccmode (insn, CCGOCmode)
-   && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
+   && ix86_binary_operator_ok (ASHIFT, SImode, operands)
+   && (optimize_size
+       || !TARGET_PARTIAL_FLAG_REG_STALL
+       || (operands[2] == const1_rtx
+          && (TARGET_SHIFT1
+              || TARGET_DOUBLE_WITH_ADD)))"
 {
   switch (get_attr_type (insn))
     {
    (set (match_operand:DI 0 "register_operand" "=r")
        (zero_extend:DI (ashift:SI (match_dup 1) (match_dup 2))))]
   "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
-   && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
+   && ix86_binary_operator_ok (ASHIFT, SImode, operands)
+   && (optimize_size
+       || !TARGET_PARTIAL_FLAG_REG_STALL
+       || (operands[2] == const1_rtx
+          && (TARGET_SHIFT1
+              || TARGET_DOUBLE_WITH_ADD)))"
 {
   switch (get_attr_type (insn))
     {
    (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
        (ashift:HI (match_dup 1) (match_dup 2)))]
   "ix86_match_ccmode (insn, CCGOCmode)
-   && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
+   && ix86_binary_operator_ok (ASHIFT, HImode, operands)
+   && (optimize_size
+       || !TARGET_PARTIAL_FLAG_REG_STALL
+       || (operands[2] == const1_rtx
+          && (TARGET_SHIFT1
+              || (TARGET_DOUBLE_WITH_ADD && REG_P (operands[0])))))"
 {
   switch (get_attr_type (insn))
     {
          (const_int 0)))
    (clobber (match_scratch:HI 0 "=r"))]
   "ix86_match_ccmode (insn, CCGOCmode)
-   && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
+   && ix86_binary_operator_ok (ASHIFT, HImode, operands)
+   && (optimize_size
+       || !TARGET_PARTIAL_FLAG_REG_STALL
+       || (operands[2] == const1_rtx
+          && (TARGET_SHIFT1
+              || TARGET_DOUBLE_WITH_ADD)))"
 {
   switch (get_attr_type (insn))
     {
    (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
        (ashift:QI (match_dup 1) (match_dup 2)))]
   "ix86_match_ccmode (insn, CCGOCmode)
-   && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
+   && ix86_binary_operator_ok (ASHIFT, QImode, operands)
+   && (optimize_size
+       || !TARGET_PARTIAL_FLAG_REG_STALL
+       || (operands[2] == const1_rtx
+          && (TARGET_SHIFT1
+              || (TARGET_DOUBLE_WITH_ADD && REG_P (operands[0])))))"
 {
   switch (get_attr_type (insn))
     {
          (const_int 0)))
    (clobber (match_scratch:QI 0 "=q"))]
   "ix86_match_ccmode (insn, CCGOCmode)
-   && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
+   && ix86_binary_operator_ok (ASHIFT, QImode, operands)
+   && (optimize_size
+       || !TARGET_PARTIAL_FLAG_REG_STALL
+       || (operands[2] == const1_rtx
+          && (TARGET_SHIFT1
+              || TARGET_DOUBLE_WITH_ADD)))"
 {
   switch (get_attr_type (insn))
     {
    (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
        (ashiftrt:DI (match_dup 1) (match_dup 2)))]
   "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
-   && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
+   && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)
+   && (optimize_size
+       || !TARGET_PARTIAL_FLAG_REG_STALL)"
   "sar{q}\t{%2, %0|%0, %2}"
   [(set_attr "type" "ishift")
    (set_attr "mode" "DI")])
          (const_int 0)))
    (clobber (match_scratch:DI 0 "=r"))]
   "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
-   && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
+   && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)
+   && (optimize_size
+       || !TARGET_PARTIAL_FLAG_REG_STALL)"
   "sar{q}\t{%2, %0|%0, %2}"
   [(set_attr "type" "ishift")
    (set_attr "mode" "DI")])
    (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
        (ashiftrt:SI (match_dup 1) (match_dup 2)))]
   "ix86_match_ccmode (insn, CCGOCmode)
-   && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
+   && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)
+   && (optimize_size
+       || !TARGET_PARTIAL_FLAG_REG_STALL)"
   "sar{l}\t{%2, %0|%0, %2}"
   [(set_attr "type" "ishift")
    (set_attr "mode" "SI")])
          (const_int 0)))
    (clobber (match_scratch:SI 0 "=r"))]
   "ix86_match_ccmode (insn, CCGOCmode)
-   && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
+   && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)
+   && (optimize_size
+       || !TARGET_PARTIAL_FLAG_REG_STALL)"
   "sar{l}\t{%2, %0|%0, %2}"
   [(set_attr "type" "ishift")
    (set_attr "mode" "SI")])
    (set (match_operand:DI 0 "register_operand" "=r")
        (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
   "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
-   && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
+   && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)
+   && (optimize_size
+       || !TARGET_PARTIAL_FLAG_REG_STALL)"
   "sar{l}\t{%2, %k0|%k0, %2}"
   [(set_attr "type" "ishift")
    (set_attr "mode" "SI")])
    (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
        (ashiftrt:HI (match_dup 1) (match_dup 2)))]
   "ix86_match_ccmode (insn, CCGOCmode)
-   && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
+   && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)
+   && (optimize_size
+       || !TARGET_PARTIAL_FLAG_REG_STALL)"
   "sar{w}\t{%2, %0|%0, %2}"
   [(set_attr "type" "ishift")
    (set_attr "mode" "HI")])
          (const_int 0)))
    (clobber (match_scratch:HI 0 "=r"))]
   "ix86_match_ccmode (insn, CCGOCmode)
-   && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
+   && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)
+   && (optimize_size
+       || !TARGET_PARTIAL_FLAG_REG_STALL)"
   "sar{w}\t{%2, %0|%0, %2}"
   [(set_attr "type" "ishift")
    (set_attr "mode" "HI")])
    (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
        (ashiftrt:QI (match_dup 1) (match_dup 2)))]
   "ix86_match_ccmode (insn, CCGOCmode)
-   && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
+   && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)
+   && (optimize_size
+       || !TARGET_PARTIAL_FLAG_REG_STALL)"
   "sar{b}\t{%2, %0|%0, %2}"
   [(set_attr "type" "ishift")
    (set_attr "mode" "QI")])
          (const_int 0)))
    (clobber (match_scratch:QI 0 "=q"))]
   "ix86_match_ccmode (insn, CCGOCmode)
-   && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
+   && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)
+   && (optimize_size
+       || !TARGET_PARTIAL_FLAG_REG_STALL)"
   "sar{b}\t{%2, %0|%0, %2}"
   [(set_attr "type" "ishift")
    (set_attr "mode" "QI")])
    (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
        (lshiftrt:DI (match_dup 1) (match_dup 2)))]
   "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
-   && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
+   && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
+   && (optimize_size
+       || !TARGET_PARTIAL_FLAG_REG_STALL)"
   "shr{q}\t{%2, %0|%0, %2}"
   [(set_attr "type" "ishift")
    (set_attr "mode" "DI")])
          (const_int 0)))
    (clobber (match_scratch:DI 0 "=r"))]
   "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
-   && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
+   && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
+   && (optimize_size
+       || !TARGET_PARTIAL_FLAG_REG_STALL)"
   "shr{q}\t{%2, %0|%0, %2}"
   [(set_attr "type" "ishift")
    (set_attr "mode" "DI")])
    (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
        (lshiftrt:SI (match_dup 1) (match_dup 2)))]
   "ix86_match_ccmode (insn, CCGOCmode)
-   && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
+   && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
+   && (optimize_size
+       || !TARGET_PARTIAL_FLAG_REG_STALL)"
   "shr{l}\t{%2, %0|%0, %2}"
   [(set_attr "type" "ishift")
    (set_attr "mode" "SI")])
         (const_int 0)))
    (clobber (match_scratch:SI 0 "=r"))]
   "ix86_match_ccmode (insn, CCGOCmode)
-   && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
+   && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
+   && (optimize_size
+       || !TARGET_PARTIAL_FLAG_REG_STALL)"
   "shr{l}\t{%2, %0|%0, %2}"
   [(set_attr "type" "ishift")
    (set_attr "mode" "SI")])
    (set (match_operand:DI 0 "register_operand" "=r")
        (lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
   "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
-   && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
+   && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
+   && (optimize_size
+       || !TARGET_PARTIAL_FLAG_REG_STALL)"
   "shr{l}\t{%2, %k0|%k0, %2}"
   [(set_attr "type" "ishift")
    (set_attr "mode" "SI")])
    (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
        (lshiftrt:HI (match_dup 1) (match_dup 2)))]
   "ix86_match_ccmode (insn, CCGOCmode)
-   && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
+   && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
+   && (optimize_size
+       || !TARGET_PARTIAL_FLAG_REG_STALL)"
   "shr{w}\t{%2, %0|%0, %2}"
   [(set_attr "type" "ishift")
    (set_attr "mode" "HI")])
          (const_int 0)))
    (clobber (match_scratch:HI 0 "=r"))]
   "ix86_match_ccmode (insn, CCGOCmode)
-   && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
+   && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
+   && (optimize_size
+       || !TARGET_PARTIAL_FLAG_REG_STALL)"
   "shr{w}\t{%2, %0|%0, %2}"
   [(set_attr "type" "ishift")
    (set_attr "mode" "HI")])
    (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
        (lshiftrt:QI (match_dup 1) (match_dup 2)))]
   "ix86_match_ccmode (insn, CCGOCmode)
-   && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
+   && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)
+   && (optimize_size
+       || !TARGET_PARTIAL_FLAG_REG_STALL)"
   "shr{b}\t{%2, %0|%0, %2}"
   [(set_attr "type" "ishift")
    (set_attr "mode" "QI")])
          (const_int 0)))
    (clobber (match_scratch:QI 0 "=q"))]
   "ix86_match_ccmode (insn, CCGOCmode)
-   && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
+   && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)
+   && (optimize_size
+       || !TARGET_PARTIAL_FLAG_REG_STALL)"
   "shr{b}\t{%2, %0|%0, %2}"
   [(set_attr "type" "ishift")
    (set_attr "mode" "QI")])