{"bf531", BFIN_CPU_BF531, 0x0006,
WA_SPECULATIVE_LOADS},
{"bf531", BFIN_CPU_BF531, 0x0005,
- WA_SPECULATIVE_LOADS | WA_RETS},
+ WA_SPECULATIVE_LOADS | WA_RETS | WA_05000283 | WA_05000315},
{"bf531", BFIN_CPU_BF531, 0x0004,
- WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS},
+ WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS
+ | WA_05000283 | WA_05000257 | WA_05000315},
{"bf531", BFIN_CPU_BF531, 0x0003,
- WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS},
+ WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS
+ | WA_05000283 | WA_05000257 | WA_05000315},
{"bf532", BFIN_CPU_BF532, 0x0006,
WA_SPECULATIVE_LOADS},
{"bf532", BFIN_CPU_BF532, 0x0005,
- WA_SPECULATIVE_LOADS | WA_RETS},
+ WA_SPECULATIVE_LOADS | WA_RETS | WA_05000283 | WA_05000315},
{"bf532", BFIN_CPU_BF532, 0x0004,
- WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS},
+ WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS
+ | WA_05000283 | WA_05000257 | WA_05000315},
{"bf532", BFIN_CPU_BF532, 0x0003,
- WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS},
+ WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS
+ | WA_05000283 | WA_05000257 | WA_05000315},
{"bf533", BFIN_CPU_BF533, 0x0006,
WA_SPECULATIVE_LOADS},
{"bf533", BFIN_CPU_BF533, 0x0005,
- WA_SPECULATIVE_LOADS | WA_RETS},
+ WA_SPECULATIVE_LOADS | WA_RETS | WA_05000283 | WA_05000315},
{"bf533", BFIN_CPU_BF533, 0x0004,
- WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS},
+ WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS
+ | WA_05000283 | WA_05000257 | WA_05000315},
{"bf533", BFIN_CPU_BF533, 0x0003,
- WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS},
+ WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS
+ | WA_05000283 | WA_05000257 | WA_05000315},
{"bf534", BFIN_CPU_BF534, 0x0003,
WA_SPECULATIVE_LOADS | WA_RETS},
{"bf534", BFIN_CPU_BF534, 0x0002,
- WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS},
+ WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS
+ | WA_05000283 | WA_05000257 | WA_05000315},
{"bf534", BFIN_CPU_BF534, 0x0001,
- WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS},
+ WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS
+ | WA_05000283 | WA_05000257 | WA_05000315},
{"bf536", BFIN_CPU_BF536, 0x0003,
WA_SPECULATIVE_LOADS | WA_RETS},
{"bf536", BFIN_CPU_BF536, 0x0002,
- WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS},
+ WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS
+ | WA_05000283 | WA_05000257 | WA_05000315},
{"bf536", BFIN_CPU_BF536, 0x0001,
- WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS},
+ WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS
+ | WA_05000283 | WA_05000257 | WA_05000315},
{"bf537", BFIN_CPU_BF537, 0x0003,
WA_SPECULATIVE_LOADS | WA_RETS},
{"bf537", BFIN_CPU_BF537, 0x0002,
- WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS},
+ WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS
+ | WA_05000283 | WA_05000257 | WA_05000315},
{"bf537", BFIN_CPU_BF537, 0x0001,
- WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS},
+ WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS
+ | WA_05000283 | WA_05000257 | WA_05000315},
{"bf538", BFIN_CPU_BF538, 0x0005,
WA_SPECULATIVE_LOADS},
{"bf538", BFIN_CPU_BF538, 0x0004,
WA_SPECULATIVE_LOADS | WA_RETS},
{"bf538", BFIN_CPU_BF538, 0x0003,
- WA_SPECULATIVE_LOADS | WA_RETS},
+ WA_SPECULATIVE_LOADS | WA_RETS
+ | WA_05000283 | WA_05000315},
{"bf538", BFIN_CPU_BF538, 0x0002,
- WA_SPECULATIVE_LOADS | WA_RETS},
+ WA_SPECULATIVE_LOADS | WA_RETS | WA_05000283 | WA_05000257 | WA_05000315},
{"bf539", BFIN_CPU_BF539, 0x0005,
WA_SPECULATIVE_LOADS},
{"bf539", BFIN_CPU_BF539, 0x0004,
WA_SPECULATIVE_LOADS | WA_RETS},
{"bf539", BFIN_CPU_BF539, 0x0003,
- WA_SPECULATIVE_LOADS | WA_RETS},
+ WA_SPECULATIVE_LOADS | WA_RETS
+ | WA_05000283 | WA_05000315},
{"bf539", BFIN_CPU_BF539, 0x0002,
- WA_SPECULATIVE_LOADS | WA_RETS},
+ WA_SPECULATIVE_LOADS | WA_RETS
+ | WA_05000283 | WA_05000257 | WA_05000315},
{"bf542", BFIN_CPU_BF542, 0x0002,
WA_SPECULATIVE_LOADS},
{"bf549", BFIN_CPU_BF549, 0x0000,
WA_SPECULATIVE_LOADS | WA_RETS},
- {"bf561", BFIN_CPU_BF561, 0x0005, WA_RETS},
+ {"bf561", BFIN_CPU_BF561, 0x0005, WA_RETS
+ | WA_05000283 | WA_05000315},
{"bf561", BFIN_CPU_BF561, 0x0003,
- WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS},
+ WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS
+ | WA_05000283 | WA_05000257 | WA_05000315},
{"bf561", BFIN_CPU_BF561, 0x0002,
- WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS},
+ WA_SPECULATIVE_LOADS | WA_SPECULATIVE_SYNCS | WA_RETS
+ | WA_05000283 | WA_05000257 | WA_05000315},
{NULL, 0, 0, 0}
};
return ((df_regs_ever_live_p (regno)
&& !fixed_regs[regno]
&& (is_inthandler || !call_used_regs[regno]))
+ || (is_inthandler
+ && (ENABLE_WA_05000283 || ENABLE_WA_05000315)
+ && regno == REG_P5)
|| (!TARGET_FDPIC
&& regno == PIC_OFFSET_TABLE_REGNUM
&& (crtl->uses_pic_offset_table
rtx insn = emit_move_insn (predec, gen_rtx_REG (SImode, REG_ASTAT));
RTX_FRAME_RELATED_P (insn) = 1;
- if (! current_function_is_leaf
- || cfun->machine->has_hardware_loops
- || cfun->machine->has_loopreg_clobber)
- for (dregno = REG_LT0; dregno <= REG_LB1; dregno++)
+ for (dregno = REG_LT0; dregno <= REG_LB1; dregno++)
+ if (! current_function_is_leaf
+ || cfun->machine->has_hardware_loops
+ || cfun->machine->has_loopreg_clobber
+ || (ENABLE_WA_05000257
+ && (dregno == REG_LC0 || dregno == REG_LC1)))
{
insn = emit_move_insn (predec, gen_rtx_REG (SImode, dregno));
RTX_FRAME_RELATED_P (insn) = 1;
}
if (saveall || is_inthandler)
{
- if (! current_function_is_leaf
- || cfun->machine->has_hardware_loops
- || cfun->machine->has_loopreg_clobber)
- for (regno = REG_LB1; regno >= REG_LT0; regno--)
+ for (regno = REG_LB1; regno >= REG_LT0; regno--)
+ if (! current_function_is_leaf
+ || cfun->machine->has_hardware_loops
+ || cfun->machine->has_loopreg_clobber
+ || (ENABLE_WA_05000257 && (regno == REG_LC0 || regno == REG_LC1)))
emit_move_insn (gen_rtx_REG (SImode, regno), postinc);
emit_move_insn (gen_rtx_REG (SImode, REG_ASTAT), postinc);
all = true;
expand_prologue_reg_save (spreg, all, true);
+ if (ENABLE_WA_05000283 || ENABLE_WA_05000315)
+ {
+ rtx chipid = GEN_INT (trunc_int_for_mode (0xFFC00014, SImode));
+ rtx p5reg = gen_rtx_REG (Pmode, REG_P5);
+ emit_insn (gen_movbi (bfin_cc_rtx, const1_rtx));
+ emit_insn (gen_movsi_high (p5reg, chipid));
+ emit_insn (gen_movsi_low (p5reg, p5reg, chipid));
+ emit_insn (gen_dummy_load (p5reg, bfin_cc_rtx));
+ }
+
if (lookup_attribute ("nesting", attrs))
{
rtx srcreg = gen_rtx_REG (Pmode, (fkind == EXCPT_HANDLER ? REG_RETX
(UNSPEC_VOLATILE_CSYNC 1)
(UNSPEC_VOLATILE_SSYNC 2)
(UNSPEC_VOLATILE_LOAD_FUNCDESC 3)
- (UNSPEC_VOLATILE_STORE_EH_HANDLER 4)])
+ (UNSPEC_VOLATILE_STORE_EH_HANDLER 4)
+ (UNSPEC_VOLATILE_DUMMY 5)])
(define_constants
[(MACFLAG_NONE 0)
})
(define_insn "movbi"
- [(set (match_operand:BI 0 "nonimmediate_operand" "=x,x,d,md,C,d,C")
- (match_operand:BI 1 "general_operand" "x,xKs3,md,d,d,C,P0"))]
+ [(set (match_operand:BI 0 "nonimmediate_operand" "=x,x,d,md,C,d,C,P1")
+ (match_operand:BI 1 "general_operand" "x,xKs3,md,d,d,C,P0,P1"))]
""
"@
B %0 = %1;
CC = %1;
%0 = CC;
- R0 = R0 | R0; CC = AC0;"
- [(set_attr "type" "move,mvi,mcld,mcst,compare,compare,alu0")
- (set_attr "length" "2,2,*,*,2,2,4")
- (set_attr "seq_insns" "*,*,*,*,*,*,multi")])
+ CC = R0 < R0;
+ CC = R0 == R0;"
+ [(set_attr "type" "move,mvi,mcld,mcst,compare,compare,compare,compare")
+ (set_attr "length" "2,2,*,*,2,2,2,2")
+ (set_attr "seq_insns" "*,*,*,*,*,*,*,*")])
(define_insn "movpdi"
[(set (match_operand:PDI 0 "nonimmediate_operand" "=e,<,e")
gcc_unreachable ();
})
+(define_insn "dummy_load"
+ [(unspec_volatile [(match_operand 0 "register_operand" "a")
+ (match_operand 1 "register_operand" "C")]
+ UNSPEC_VOLATILE_DUMMY)]
+ ""
+ "if cc jump 4;\n\tr7 = [%0];"
+ [(set_attr "type" "misc")
+ (set_attr "length" "4")
+ (set_attr "seq_insns" "multi")])
+
(define_insn "csync"
[(unspec_volatile [(const_int 0)] UNSPEC_VOLATILE_CSYNC)]
""